Lines Matching +full:grant +full:- +full:dma
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
563 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
629 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
689 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
727 /* Loop limit on how long we wait for auto-negotiation to complete */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1037 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1047 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1457 /* DMA Coalescing register fields */
1458 /* DMA Coalescing Watchdog Timer */
1460 /* DMA Coalescing Rx Threshold */
1466 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1470 /* DMA Coalescing Transmit Threshold */
1480 /* DMA Coal Rx Traffic Current Count */
1486 /* Lx power decision based on DMA coal */