Lines Matching +full:0 +full:x01010000
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
58 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
68 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
69 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
70 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
71 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
73 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
74 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
75 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */
76 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
77 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
79 #define E1000_CTRL_EXT_PFRSTD 0x00004000
80 #define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */
81 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
82 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
84 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
87 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
88 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
89 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
90 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
91 #define E1000_CTRL_EXT_EIAME 0x01000000
92 #define E1000_CTRL_EXT_IRCA 0x00000001
93 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
95 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
96 #define E1000_CTRL_EXT_LSECCK 0x00001000
97 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
100 #define E1000_I2CCMD_OPCODE_READ 0x08000000
101 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
102 #define E1000_I2CCMD_READY 0x20000000
103 #define E1000_I2CCMD_ERROR 0x80000000
104 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
105 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
108 #define E1000_IVAR_VALID 0x80
109 #define E1000_GPIE_NSICR 0x00000001
110 #define E1000_GPIE_MSIX_MODE 0x00000010
111 #define E1000_GPIE_EIAME 0x40000000
112 #define E1000_GPIE_PBA 0x80000000
115 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
116 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
117 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
118 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
119 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
120 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
121 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
123 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
124 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
125 #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
126 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
127 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
128 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
129 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
130 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
131 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
133 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
135 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
136 #define E1000_RXDEXT_STATERR_LB 0x00040000
137 #define E1000_RXDEXT_STATERR_CE 0x01000000
138 #define E1000_RXDEXT_STATERR_SE 0x02000000
139 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
140 #define E1000_RXDEXT_STATERR_CXE 0x10000000
141 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
142 #define E1000_RXDEXT_STATERR_IPE 0x40000000
143 #define E1000_RXDEXT_STATERR_RXE 0x80000000
161 #define E1000_MRQC_RSS_ENABLE_2Q 0x00000001
162 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
163 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
164 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
165 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
166 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
167 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
168 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
170 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
175 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
176 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
177 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
179 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
181 #define E1000_MANC_EN_MNG2HOST 0x00200000
183 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */
184 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */
185 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */
186 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */
189 #define E1000_RCTL_RST 0x00000001 /* Software reset */
190 #define E1000_RCTL_EN 0x00000002 /* enable */
191 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
192 #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */
193 #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */
194 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
195 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
196 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
197 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
198 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
199 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
200 #define E1000_RCTL_RDMTS_HEX 0x00010000
203 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
204 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
205 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
206 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
207 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
208 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
209 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
211 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
212 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
213 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
214 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
215 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
216 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
217 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
218 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
219 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
220 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
234 * value2 = [0..64512], default=4096
235 * value3 = [0..64512], default=0
238 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
239 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
240 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
241 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
249 #define E1000_SWFW_EEP_SM 0x01
250 #define E1000_SWFW_PHY0_SM 0x02
251 #define E1000_SWFW_PHY1_SM 0x04
252 #define E1000_SWFW_CSR_SM 0x08
253 #define E1000_SWFW_PHY2_SM 0x20
254 #define E1000_SWFW_PHY3_SM 0x40
255 #define E1000_SWFW_SW_MNG_SM 0x400
258 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
259 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
260 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
261 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
265 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
266 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
267 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
268 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
269 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
270 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
271 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
272 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
273 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */
274 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
275 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
276 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
277 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
278 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
279 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
280 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
281 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
282 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
283 #define E1000_CTRL_DEV_RST 0x20000000 /* Device reset */
284 #define E1000_CTRL_RST 0x04000000 /* Global reset */
285 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
286 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
287 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
288 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
289 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */
296 #define E1000_CONNSW_ENRGSRC 0x4
297 #define E1000_CONNSW_PHYSD 0x400
298 #define E1000_CONNSW_PHY_PDN 0x800
299 #define E1000_CONNSW_SERDESD 0x200
300 #define E1000_CONNSW_AUTOSENSE_CONF 0x2
301 #define E1000_CONNSW_AUTOSENSE_EN 0x1
304 #define E1000_PCS_LCTL_FSV_10 0
308 #define E1000_PCS_LCTL_FSD 0x10
309 #define E1000_PCS_LCTL_FORCE_LINK 0x20
310 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
311 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
312 #define E1000_PCS_LCTL_AN_RESTART 0x20000
313 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
314 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
320 #define E1000_PCS_LSTS_SYNK_OK 0x10
321 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
324 #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */
325 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
326 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
328 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
329 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
330 #define E1000_STATUS_SPEED_MASK 0x000000C0
331 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
332 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
333 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
334 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */
335 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
336 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
337 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
338 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
339 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */
340 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
348 #define E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */
359 #define ADVERTISE_10_HALF 0x0001
360 #define ADVERTISE_10_FULL 0x0002
361 #define ADVERTISE_100_HALF 0x0004
362 #define ADVERTISE_100_FULL 0x0008
363 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
364 #define ADVERTISE_1000_FULL 0x0020
380 #define E1000_PHY_LED0_MODE_MASK 0x00000007
381 #define E1000_PHY_LED0_IVRT 0x00000008
382 #define E1000_PHY_LED0_MASK 0x0000001F
384 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
385 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
386 #define E1000_LEDCTL_LED0_IVRT 0x00000040
387 #define E1000_LEDCTL_LED0_BLINK 0x00000080
389 #define E1000_LEDCTL_MODE_LINK_UP 0x2
390 #define E1000_LEDCTL_MODE_LED_ON 0xE
391 #define E1000_LEDCTL_MODE_LED_OFF 0xF
394 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
395 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
396 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
397 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
398 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
399 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
400 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
401 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
402 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
403 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
404 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
405 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
406 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
407 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
408 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
409 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
410 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
411 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
412 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
413 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
414 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
417 #define E1000_TCTL_EN 0x00000002 /* enable Tx */
418 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
419 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
420 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
422 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
425 #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
428 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
429 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410
432 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
433 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
434 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* lem(4) IPv6 checksum offload */
435 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
436 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
437 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
440 #define E1000_RFCTL_NFSW_DIS 0x00000040
441 #define E1000_RFCTL_NFSR_DIS 0x00000080
442 #define E1000_RFCTL_ACK_DIS 0x00001000
443 #define E1000_RFCTL_EXTEN 0x00008000
444 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
445 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
446 #define E1000_RFCTL_LEF 0x00040000
459 #define E1000_TIPG_IPGT_MASK 0x000003FF
471 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
474 #define MAX_JUMBO_FRAME_SIZE 0x3F00
476 #define MAX_RX_JUMBO_FRAME_SIZE 0x2600
477 #define E1000_TX_PTR_GAP 0x1F
480 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
481 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
482 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008
483 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
484 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080
485 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000
487 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000
490 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002
491 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
492 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
493 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
495 #define E1000_KABGTXD_BGSQLBIAS 0x00050000
501 #define E1000_PBA_8K 0x0008 /* 8KB */
502 #define E1000_PBA_10K 0x000A /* 10KB */
503 #define E1000_PBA_12K 0x000C /* 12KB */
504 #define E1000_PBA_14K 0x000E /* 14KB */
505 #define E1000_PBA_16K 0x0010 /* 16KB */
506 #define E1000_PBA_18K 0x0012
507 #define E1000_PBA_20K 0x0014
508 #define E1000_PBA_22K 0x0016
509 #define E1000_PBA_24K 0x0018
510 #define E1000_PBA_26K 0x001A
511 #define E1000_PBA_30K 0x001E
512 #define E1000_PBA_32K 0x0020
513 #define E1000_PBA_34K 0x0022
514 #define E1000_PBA_35K 0x0023
515 #define E1000_PBA_38K 0x0026
516 #define E1000_PBA_40K 0x0028
517 #define E1000_PBA_48K 0x0030 /* 48KB */
518 #define E1000_PBA_64K 0x0040 /* 64KB */
520 #define E1000_PBA_RXA_MASK 0xFFFF
525 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF
526 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00
528 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000
537 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
538 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
539 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
541 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */
544 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
545 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
546 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
547 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
548 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
549 #define E1000_ICR_RXO 0x00000040 /* Rx overrun */
550 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
551 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */
552 #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
553 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
554 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
555 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
556 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
557 #define E1000_ICR_TXD_LOW 0x00008000
558 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
559 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
560 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */
561 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
563 #define E1000_ICR_INT_ASSERTED 0x80000000
564 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
565 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
566 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
567 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
568 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */
569 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */
570 #define E1000_ICR_FER 0x00400000 /* Fatal Error */
572 #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
573 #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
575 #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
579 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
581 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */
582 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
583 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */
586 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
587 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
588 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
589 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
590 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
591 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
592 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
593 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
594 #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
595 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
597 #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */
598 #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */
599 #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */
600 #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */
604 * o RXT0 = Receiver Timer Interrupt (ring 0)
606 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
631 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
633 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
641 #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
645 #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
658 #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
662 #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
669 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
671 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
672 #define E1000_EITR_INTERVAL 0x00007FFC
675 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
676 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
677 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
678 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
679 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
680 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
682 #define E1000_TXDCTL_COUNT_DESC 0x00400000
685 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
686 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
687 #define FLOW_CONTROL_TYPE 0x8808
701 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
704 #define E1000_RAH_QUEUE_MASK_82575 0x000C0000
705 #define E1000_RAH_POOL_1 0x00040000
708 #define E1000_SUCCESS 0
743 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
744 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
745 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
748 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
749 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
750 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
751 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
755 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
756 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
757 #define E1000_RXCW_C 0x20000000 /* Receive config */
758 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
760 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
761 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
764 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
765 #define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
766 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
767 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
769 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
770 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
771 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
772 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
773 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
774 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
775 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
776 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
777 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
779 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000
780 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000
782 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000
783 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000
785 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
786 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
787 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
788 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
789 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
790 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
792 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
793 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
794 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
795 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
796 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
797 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
798 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
799 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
800 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
801 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
802 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
806 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF
810 #define E1000_FTQF_VF_BP 0x00008000
811 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
812 #define E1000_FTQF_MASK 0xF0000000
813 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
815 #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
816 #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
818 #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
819 #define E1000_TSICR_TXTS 0x00000002
820 #define E1000_TSIM_TXTS 0x00000002
822 #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
823 #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
824 #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
826 #define E1000_TTQF_PROTOCOL_TCP 0x0
828 #define E1000_TTQF_PROTOCOL_UDP 0x1
830 #define E1000_TTQF_PROTOCOL_SCTP 0x2
833 #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
834 #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
835 #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
836 #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
838 #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
840 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */
841 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */
842 #define E1000_MDICNFG_PHY_MASK 0x03E00000
847 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
848 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
849 #define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */
850 #define E1000_M88E1112_MAC_CTRL_1 0x10
851 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */
853 #define E1000_M88E1112_PAGE_ADDR 0x16
854 #define E1000_M88E1112_STATUS 0x01
856 #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
857 #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
858 #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
859 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */
860 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */
863 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
864 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
865 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
866 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
867 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
869 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
870 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
871 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */
872 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
873 #define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
874 #define E1000_M88E1543_EEE_CTRL_1 0x0
875 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
876 #define E1000_M88E1543_FIBER_CTRL 0x0 /* Fiber Control Register */
883 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
884 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
885 #define E1000_M88E1512_CFG_REG_1 0x0010
886 #define E1000_M88E1512_CFG_REG_2 0x0011
887 #define E1000_M88E1512_CFG_REG_3 0x0007
888 #define E1000_M88E1512_MODE 0x0014
889 #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
893 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
894 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
895 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
896 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
897 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
898 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
899 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
900 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
901 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
902 #define E1000_GCR_CAP_VER2 0x00040000
911 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
914 #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */
915 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
916 #define E1000_MPHY_DATA 0x0E10 /* Data Register */
919 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
921 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
924 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
925 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
926 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
927 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
928 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
929 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
930 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
931 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
932 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
933 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
934 #define MII_CR_SPEED_1000 0x0040
935 #define MII_CR_SPEED_100 0x2000
936 #define MII_CR_SPEED_10 0x0000
939 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
940 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
941 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
942 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
943 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
944 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
945 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
946 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
947 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
948 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
949 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
950 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
951 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
952 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
953 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
956 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
957 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
958 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
959 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
960 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
961 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
962 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
963 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
964 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
965 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
968 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
969 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
970 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
971 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
972 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
973 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
974 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
975 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
976 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
977 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
978 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
981 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
982 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
983 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
984 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
985 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
988 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
989 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
990 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
991 /* 1=Repeater/switch device port 0=DTE device */
992 #define CR_1000T_REPEATER_DTE 0x0400
993 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
994 #define CR_1000T_MS_VALUE 0x0800
995 /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
996 #define CR_1000T_MS_ENABLE 0x1000
997 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
998 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
999 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
1000 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
1001 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1004 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */
1005 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
1006 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
1007 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
1008 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1009 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
1010 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */
1011 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1017 #define PHY_CONTROL 0x00 /* Control Register */
1018 #define PHY_STATUS 0x01 /* Status Register */
1019 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1020 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1021 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
1022 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
1023 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
1024 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1025 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1028 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
1030 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1033 #define E1000_EECD_SK 0x00000001 /* NVM Clock */
1034 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */
1035 #define E1000_EECD_DI 0x00000004 /* NVM Data In */
1036 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */
1037 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */
1038 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */
1039 #define E1000_EECD_PRES 0x00000100 /* NVM Present */
1040 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */
1041 #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */
1042 #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */
1043 #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */
1044 #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */
1045 /* NVM Addressing bits based on type 0=small, 1=large */
1046 #define E1000_EECD_ADDR_BITS 0x00000400
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1049 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
1050 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
1052 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1053 #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
1054 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1056 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
1057 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */
1058 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
1059 #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */
1062 #define E1000_I210_FIFO_SEL_RX 0x00
1063 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
1064 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
1065 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
1066 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
1068 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */
1070 #define E1000_I210_FW_PTR_MASK 0x7FFF
1079 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
1083 #define NVM_COMPAT 0x0003
1084 #define NVM_ID_LED_SETTINGS 0x0004
1085 #define NVM_VERSION 0x0005
1086 #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
1087 #define NVM_PHY_CLASS_WORD 0x0007
1088 #define E1000_I210_NVM_FW_MODULE_PTR 0x0010
1089 #define E1000_I350_NVM_FW_MODULE_PTR 0x0051
1090 #define NVM_FUTURE_INIT_WORD1 0x0019
1091 #define NVM_ETRACK_WORD 0x0042
1092 #define NVM_ETRACK_HIWORD 0x0043
1093 #define NVM_COMB_VER_OFF 0x0083
1094 #define NVM_COMB_VER_PTR 0x003d
1097 #define NVM_MAJOR_MASK 0xF000
1098 #define NVM_MINOR_MASK 0x0FF0
1099 #define NVM_IMAGE_ID_MASK 0x000F
1100 #define NVM_COMB_VER_MASK 0x00FF
1104 #define NVM_VER_INVALID 0xFFFF
1106 #define NVM_ETRACK_VALID 0x8000
1107 #define NVM_NEW_DEC_MASK 0x0F00
1113 #define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01
1115 #define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04
1117 #define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05
1119 #define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06
1121 #define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07
1123 #define NVM_MAC_ADDR 0x0000
1124 #define NVM_SUB_DEV_ID 0x000B
1125 #define NVM_SUB_VEN_ID 0x000C
1126 #define NVM_DEV_ID 0x000D
1127 #define NVM_VEN_ID 0x000E
1128 #define NVM_INIT_CTRL_2 0x000F
1129 #define NVM_INIT_CTRL_4 0x0013
1130 #define NVM_LED_1_CFG 0x001C
1131 #define NVM_LED_0_2_CFG 0x001F
1133 #define NVM_COMPAT_VALID_CSUM 0x0001
1134 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040
1136 #define NVM_INIT_CONTROL2_REG 0x000F
1137 #define NVM_INIT_CONTROL3_PORT_B 0x0014
1138 #define NVM_INIT_3GIO_3 0x001A
1139 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1140 #define NVM_INIT_CONTROL3_PORT_A 0x0024
1141 #define NVM_CFG 0x0012
1142 #define NVM_ALT_MAC_ADDR_PTR 0x0037
1143 #define NVM_CHECKSUM_REG 0x003F
1144 #define NVM_COMPATIBILITY_REG_3 0x0003
1145 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
1147 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
1148 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
1149 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
1150 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
1152 #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0)
1154 /* Mask bits for fields in Word 0x24 of the NVM */
1155 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
1156 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */
1163 /* Mask bits for fields in Word 0x0f of the NVM */
1164 #define NVM_WORD0F_PAUSE_MASK 0x3000
1165 #define NVM_WORD0F_PAUSE 0x1000
1166 #define NVM_WORD0F_ASM_DIR 0x2000
1167 #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0
1169 /* Mask bits for fields in Word 0x1a of the NVM */
1170 #define NVM_WORD1A_ASPM_MASK 0x000C
1172 /* Mask bits for fields in Word 0x03 of the EEPROM */
1173 #define NVM_COMPAT_LOM 0x0800
1178 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1179 #define NVM_SUM 0xBABA
1184 #define NVM_PBA_PTR_GUARD 0xFAFA
1185 #define NVM_RESERVED_WORD 0xFFFF
1186 #define NVM_PHY_CLASS_A 0x8000
1187 #define NVM_SERDES_AMPLITUDE_MASK 0x000F
1188 #define NVM_SIZE_MASK 0x1C00
1194 #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */
1195 #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */
1196 #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */
1197 #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */
1198 #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */
1202 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */
1203 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1205 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */
1206 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */
1209 #define NVM_STATUS_RDY_SPI 0x01
1212 #define ID_LED_RESERVED_0000 0x0000
1213 #define ID_LED_RESERVED_FFFF 0xFFFF
1218 #define ID_LED_DEF1_DEF2 0x1
1219 #define ID_LED_DEF1_ON2 0x2
1220 #define ID_LED_DEF1_OFF2 0x3
1221 #define ID_LED_ON1_DEF2 0x4
1222 #define ID_LED_ON1_ON2 0x5
1223 #define ID_LED_ON1_OFF2 0x6
1224 #define ID_LED_OFF1_DEF2 0x7
1225 #define ID_LED_OFF1_ON2 0x8
1226 #define ID_LED_OFF1_OFF2 0x9
1228 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
1229 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1230 #define IGP_LED3_MODE 0x07000000
1233 #define PCIX_COMMAND_REGISTER 0xE6
1234 #define PCIX_STATUS_REGISTER_LO 0xE8
1235 #define PCIX_STATUS_REGISTER_HI 0xEA
1236 #define PCI_HEADER_TYPE_REGISTER 0x0E
1237 #define PCIE_LINK_STATUS 0x12
1238 #define PCIE_DEVICE_CONTROL2 0x28
1240 #define PCIX_COMMAND_MMRBC_MASK 0x000C
1241 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
1242 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1243 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1244 #define PCIX_STATUS_HI_MMRBC_4K 0x3
1245 #define PCIX_STATUS_HI_MMRBC_2K 0x2
1246 #define PCIX_STATUS_LO_FUNC_MASK 0x7
1247 #define PCI_HEADER_TYPE_MULTIFUNC 0x80
1248 #define PCIE_LINK_WIDTH_MASK 0x3F0
1250 #define PCIE_LINK_SPEED_MASK 0x0F
1251 #define PCIE_LINK_SPEED_2500 0x01
1252 #define PCIE_LINK_SPEED_5000 0x02
1253 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
1255 #define PHY_REVISION_MASK 0xFFFFFFF0
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1257 #define MAX_PHY_MULTI_PAGE_REG 0xF
1263 #define M88E1000_E_PHY_ID 0x01410C50
1264 #define M88E1000_I_PHY_ID 0x01410C30
1265 #define M88E1011_I_PHY_ID 0x01410C20
1266 #define IGP01E1000_I_PHY_ID 0x02A80380
1267 #define M88E1111_I_PHY_ID 0x01410CC0
1268 #define M88E1543_E_PHY_ID 0x01410EA0
1269 #define M88E1512_E_PHY_ID 0x01410DD0
1270 #define M88E1112_E_PHY_ID 0x01410C90
1271 #define I347AT4_E_PHY_ID 0x01410DC0
1272 #define M88E1340M_E_PHY_ID 0x01410DF0
1273 #define GG82563_E_PHY_ID 0x01410CA0
1274 #define IGP03E1000_E_PHY_ID 0x02A80390
1275 #define IFE_E_PHY_ID 0x02A80330
1276 #define IFE_PLUS_E_PHY_ID 0x02A80320
1277 #define IFE_C_E_PHY_ID 0x02A80310
1278 #define BME1000_E_PHY_ID 0x01410CB0
1279 #define BME1000_E_PHY_ID_R2 0x01410CB1
1280 #define I82577_E_PHY_ID 0x01540050
1281 #define I82578_E_PHY_ID 0x004DD040
1282 #define I82579_E_PHY_ID 0x01540090
1283 #define I217_E_PHY_ID 0x015400A0
1284 #define I82580_I_PHY_ID 0x015403A0
1285 #define I350_I_PHY_ID 0x015403B0
1286 #define I210_I_PHY_ID 0x01410C00
1287 #define IGP04E1000_E_PHY_ID 0x02A80391
1288 #define M88_VENDOR 0x0141
1291 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1292 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1293 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1294 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1296 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1297 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1298 #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */
1299 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
1300 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1303 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1305 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1306 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1308 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
1310 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
1311 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */
1314 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
1315 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
1316 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
1317 /* 0 = <50M
1323 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
1324 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
1325 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1326 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1327 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1328 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
1329 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1336 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1337 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1341 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1342 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1343 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
1346 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1347 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1348 #define I347AT4_PAGE_SELECT 0x16
1355 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
1356 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
1357 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
1358 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
1359 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
1360 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
1361 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
1362 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
1363 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
1364 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
1367 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */
1370 #define M88E1112_VCT_DSP_DISTANCE 0x001A
1373 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
1374 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
1376 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020
1377 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C
1380 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
1384 * 4-0: register offset
1392 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1393 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1394 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1395 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1411 #define E1000_MDIC_REG_MASK 0x001F0000
1413 #define E1000_MDIC_PHY_MASK 0x03E00000
1415 #define E1000_MDIC_OP_WRITE 0x04000000
1416 #define E1000_MDIC_OP_READ 0x08000000
1417 #define E1000_MDIC_READY 0x10000000
1418 #define E1000_MDIC_ERROR 0x40000000
1419 #define E1000_MDIC_DEST 0x80000000
1423 #define E1000_GEN_CTL_READY 0x80000000
1428 #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000
1430 #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000
1433 #define E1000_LSECTXCTRL_EN_MASK 0x00000003
1434 #define E1000_LSECTXCTRL_DISABLE 0x0
1435 #define E1000_LSECTXCTRL_AUTH 0x1
1436 #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2
1437 #define E1000_LSECTXCTRL_AISCI 0x00000020
1438 #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
1439 #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8
1441 #define E1000_LSECRXCTRL_EN_MASK 0x0000000C
1443 #define E1000_LSECRXCTRL_DISABLE 0x0
1444 #define E1000_LSECRXCTRL_CHECK 0x1
1445 #define E1000_LSECRXCTRL_STRICT 0x2
1446 #define E1000_LSECRXCTRL_DROP 0x3
1447 #define E1000_LSECRXCTRL_PLSH 0x00000040
1448 #define E1000_LSECRXCTRL_RP 0x00000080
1449 #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33
1452 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1453 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1460 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
1462 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
1465 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
1467 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */
1469 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
1472 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
1474 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */
1477 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
1479 #define E1000_DMCRTRH_LRPRCW 0x80000000
1482 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
1485 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
1488 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1490 #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1491 #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1492 #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */
1493 #define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
1494 #define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
1496 #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
1497 #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
1500 #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
1501 #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */
1502 #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */
1503 #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */
1504 #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
1505 #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
1506 #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
1507 #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
1508 #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
1510 #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
1513 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1515 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */
1517 #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */
1523 #define ERROR_REPORT(fmt) do { } while (0)