Lines Matching +full:0 +full:x18000000

56 #define E1000_SW_SYNCH_MB	0x00000100
57 #define E1000_STAT_DEV_RST_SET 0x00100000
81 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
82 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
83 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
84 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
85 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
86 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
87 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
88 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
89 #define E1000_ADV_DCMD_EOP 0x1 /* End of Packet */
90 #define E1000_ADV_DCMD_IFCS 0x2 /* Insert FCS (Ethernet CRC) */
91 #define E1000_ADV_DCMD_RS 0x8 /* Report Status */
92 #define E1000_ADV_DCMD_VLE 0x40 /* Add VLAN tag */
93 #define E1000_ADV_DCMD_TSE 0x80 /* TCP Seg enable */
95 #define E1000_CTRL_EXT_NSICR 0x00000001 /* Disable Intr Clear all on read */
124 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
126 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
127 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
128 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
129 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
130 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
131 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
132 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
133 #define E1000_SRRCTL_TIMESTAMP 0x40000000
134 #define E1000_SRRCTL_DROP_EN 0x80000000
136 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
137 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
139 #define E1000_TX_HEAD_WB_ENABLE 0x1
140 #define E1000_TX_SEQNUM_WB_ENABLE 0x2
142 #define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
143 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
144 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
145 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
146 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
147 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
152 #define E1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0)
178 #define E1000_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
179 #define E1000_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
180 #define E1000_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
181 #define E1000_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
182 #define E1000_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
183 #define E1000_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
184 #define E1000_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
185 #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
187 #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F
189 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
191 #define E1000_RXDADV_SPLITHEADER_EN 0x00001000
192 #define E1000_RXDADV_SPH 0x8000
193 #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
194 #define E1000_RXDADV_ERR_HBO 0x00800000
197 #define E1000_RXDADV_RSSTYPE_NONE 0x00000000
198 #define E1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
199 #define E1000_RXDADV_RSSTYPE_IPV4 0x00000002
200 #define E1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
201 #define E1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004
202 #define E1000_RXDADV_RSSTYPE_IPV6 0x00000005
203 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
204 #define E1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
205 #define E1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
206 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
209 #define E1000_RXDADV_PKTTYPE_ILMASK 0x000000F0
210 #define E1000_RXDADV_PKTTYPE_TLMASK 0x00000F00
211 #define E1000_RXDADV_PKTTYPE_NONE 0x00000000
212 #define E1000_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
213 #define E1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
214 #define E1000_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
215 #define E1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
216 #define E1000_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
217 #define E1000_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
218 #define E1000_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
219 #define E1000_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
221 #define E1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
222 #define E1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
223 #define E1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
224 #define E1000_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
225 #define E1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
230 #define E1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000
231 #define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
232 #define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
233 #define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
234 #define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
236 #define E1000_RXDADV_IPSEC_STATUS_SECP 0x00020000
237 #define E1000_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
238 #define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
239 #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
240 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000
243 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
244 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
245 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
246 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
247 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
248 #define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
249 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
250 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
251 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
252 #define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */
253 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */
254 #define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */
256 #define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
257 #define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
258 #define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
260 #define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800
261 #define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
265 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
266 #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */
267 /* Tx Queue Arbitration Priority 0=low, 1=high */
268 #define E1000_TXDCTL_PRIORITY 0x08000000
271 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
272 #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */
275 #define E1000_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
276 #define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
278 #define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
279 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
281 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
287 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
293 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
294 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
299 #define E1000_ICR_LSECPNS 0x00000020 /* PN threshold - server */
309 * EAPOL 802.1x (0x888e): Filter 0
311 #define E1000_ETQF_FILTER_EAPOL 0
313 #define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
314 #define E1000_FTQF_MASK_DEST_ADDR_BP 0x40000000
315 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
317 #define E1000_NVM_APME_82575 0x0400
320 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof cntrl */
321 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof cntrl */
322 #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
329 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
337 #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
338 #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
339 #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
340 #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
341 #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
342 #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
343 #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
344 #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
345 #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
346 #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
348 #define E1000_VMOLR_VPE 0x00800000 /* VLAN promiscuous enable */
349 #define E1000_VMOLR_UPE 0x20000000 /* Unicast promisuous enable */
350 #define E1000_DVMOLR_HIDVLAN 0x20000000 /* Vlan hiding enable */
351 #define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
352 #define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
354 #define E1000_PBRWAC_WALPB 0x00000007 /* Wrap around event on LAN Rx PB */
355 #define E1000_PBRWAC_PBE 0x00000008 /* Rx packet buffer empty */
358 #define E1000_VLVF_VLANID_MASK 0x00000FFF
360 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
361 #define E1000_VLVF_LVLAN 0x00100000
362 #define E1000_VLVF_VLANID_ENABLE 0x80000000
364 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
365 #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
369 #define E1000_IOVCTL 0x05BBC
370 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
372 #define E1000_RPLOLR_STRVLAN 0x40000000
373 #define E1000_RPLOLR_STRCRC 0x80000000
375 #define E1000_TCTL_EXT_COLD 0x000FFC00
378 #define E1000_DTXCTL_8023LL 0x0004
379 #define E1000_DTXCTL_VLAN_ADDED 0x0008
380 #define E1000_DTXCTL_OOS_ENABLE 0x0010
381 #define E1000_DTXCTL_MDP_EN 0x0020
382 #define E1000_DTXCTL_SPOOF_INT 0x0040
386 #define ALL_QUEUES 0xFFFF
392 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
398 e1000_promisc_disabled = 0, /* all promisc modes disabled */