Lines Matching +full:hw +full:- +full:blink
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
42 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
43 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
44 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
45 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
48 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
51 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
53 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
54 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
55 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
59 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
60 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
62 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
63 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
64 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
65 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
67 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
69 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
70 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
71 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
84 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
85 * @hw: pointer to the HW structure
87 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) in e1000_init_phy_params_80003es2lan() argument
89 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan()
94 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
95 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
98 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
99 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
102 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
103 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
104 phy->reset_delay_us = 100; in e1000_init_phy_params_80003es2lan()
105 phy->type = e1000_phy_gg82563; in e1000_init_phy_params_80003es2lan()
107 phy->ops.acquire = e1000_acquire_phy_80003es2lan; in e1000_init_phy_params_80003es2lan()
108 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_80003es2lan()
109 phy->ops.check_reset_block = e1000_check_reset_block_generic; in e1000_init_phy_params_80003es2lan()
110 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_80003es2lan()
111 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; in e1000_init_phy_params_80003es2lan()
112 phy->ops.get_info = e1000_get_phy_info_m88; in e1000_init_phy_params_80003es2lan()
113 phy->ops.release = e1000_release_phy_80003es2lan; in e1000_init_phy_params_80003es2lan()
114 phy->ops.reset = e1000_phy_hw_reset_generic; in e1000_init_phy_params_80003es2lan()
115 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; in e1000_init_phy_params_80003es2lan()
117 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; in e1000_init_phy_params_80003es2lan()
118 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; in e1000_init_phy_params_80003es2lan()
119 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; in e1000_init_phy_params_80003es2lan()
120 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; in e1000_init_phy_params_80003es2lan()
122 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; in e1000_init_phy_params_80003es2lan()
125 ret_val = e1000_get_phy_id(hw); in e1000_init_phy_params_80003es2lan()
128 if (phy->id != GG82563_E_PHY_ID) in e1000_init_phy_params_80003es2lan()
129 return -E1000_ERR_PHY; in e1000_init_phy_params_80003es2lan()
135 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
136 * @hw: pointer to the HW structure
138 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) in e1000_init_nvm_params_80003es2lan() argument
140 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_80003es2lan()
141 u32 eecd = E1000_READ_REG(hw, E1000_EECD); in e1000_init_nvm_params_80003es2lan()
146 nvm->opcode_bits = 8; in e1000_init_nvm_params_80003es2lan()
147 nvm->delay_usec = 1; in e1000_init_nvm_params_80003es2lan()
148 switch (nvm->override) { in e1000_init_nvm_params_80003es2lan()
150 nvm->page_size = 32; in e1000_init_nvm_params_80003es2lan()
151 nvm->address_bits = 16; in e1000_init_nvm_params_80003es2lan()
154 nvm->page_size = 8; in e1000_init_nvm_params_80003es2lan()
155 nvm->address_bits = 8; in e1000_init_nvm_params_80003es2lan()
158 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; in e1000_init_nvm_params_80003es2lan()
159 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; in e1000_init_nvm_params_80003es2lan()
163 nvm->type = e1000_nvm_eeprom_spi; in e1000_init_nvm_params_80003es2lan()
168 /* Added to a constant, "size" becomes the left-shift value in e1000_init_nvm_params_80003es2lan()
176 nvm->word_size = 1 << size; in e1000_init_nvm_params_80003es2lan()
179 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; in e1000_init_nvm_params_80003es2lan()
180 nvm->ops.read = e1000_read_nvm_eerd; in e1000_init_nvm_params_80003es2lan()
181 nvm->ops.release = e1000_release_nvm_80003es2lan; in e1000_init_nvm_params_80003es2lan()
182 nvm->ops.update = e1000_update_nvm_checksum_generic; in e1000_init_nvm_params_80003es2lan()
183 nvm->ops.valid_led_default = e1000_valid_led_default_generic; in e1000_init_nvm_params_80003es2lan()
184 nvm->ops.validate = e1000_validate_nvm_checksum_generic; in e1000_init_nvm_params_80003es2lan()
185 nvm->ops.write = e1000_write_nvm_80003es2lan; in e1000_init_nvm_params_80003es2lan()
191 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
192 * @hw: pointer to the HW structure
194 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) in e1000_init_mac_params_80003es2lan() argument
196 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_80003es2lan()
200 /* Set media type and media-dependent function pointers */ in e1000_init_mac_params_80003es2lan()
201 switch (hw->device_id) { in e1000_init_mac_params_80003es2lan()
203 hw->phy.media_type = e1000_media_type_internal_serdes; in e1000_init_mac_params_80003es2lan()
204 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; in e1000_init_mac_params_80003es2lan()
205 mac->ops.setup_physical_interface = in e1000_init_mac_params_80003es2lan()
209 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_80003es2lan()
210 mac->ops.check_for_link = e1000_check_for_copper_link_generic; in e1000_init_mac_params_80003es2lan()
211 mac->ops.setup_physical_interface = in e1000_init_mac_params_80003es2lan()
217 mac->mta_reg_count = 128; in e1000_init_mac_params_80003es2lan()
219 mac->rar_entry_count = E1000_RAR_ENTRIES; in e1000_init_mac_params_80003es2lan()
221 mac->asf_firmware_present = true; in e1000_init_mac_params_80003es2lan()
223 mac->has_fwsm = true; in e1000_init_mac_params_80003es2lan()
225 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & in e1000_init_mac_params_80003es2lan()
228 mac->adaptive_ifs = false; in e1000_init_mac_params_80003es2lan()
233 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; in e1000_init_mac_params_80003es2lan()
235 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; in e1000_init_mac_params_80003es2lan()
236 /* hw initialization */ in e1000_init_mac_params_80003es2lan()
237 mac->ops.init_hw = e1000_init_hw_80003es2lan; in e1000_init_mac_params_80003es2lan()
239 mac->ops.setup_link = e1000_setup_link_generic; in e1000_init_mac_params_80003es2lan()
241 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; in e1000_init_mac_params_80003es2lan()
243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; in e1000_init_mac_params_80003es2lan()
245 mac->ops.write_vfta = e1000_write_vfta_generic; in e1000_init_mac_params_80003es2lan()
247 mac->ops.clear_vfta = e1000_clear_vfta_generic; in e1000_init_mac_params_80003es2lan()
249 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; in e1000_init_mac_params_80003es2lan()
251 mac->ops.id_led_init = e1000_id_led_init_generic; in e1000_init_mac_params_80003es2lan()
252 /* blink LED */ in e1000_init_mac_params_80003es2lan()
253 mac->ops.blink_led = e1000_blink_led_generic; in e1000_init_mac_params_80003es2lan()
255 mac->ops.setup_led = e1000_setup_led_generic; in e1000_init_mac_params_80003es2lan()
257 mac->ops.cleanup_led = e1000_cleanup_led_generic; in e1000_init_mac_params_80003es2lan()
259 mac->ops.led_on = e1000_led_on_generic; in e1000_init_mac_params_80003es2lan()
260 mac->ops.led_off = e1000_led_off_generic; in e1000_init_mac_params_80003es2lan()
262 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; in e1000_init_mac_params_80003es2lan()
264 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; in e1000_init_mac_params_80003es2lan()
267 hw->mac.ops.set_lan_id(hw); in e1000_init_mac_params_80003es2lan()
273 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
274 * @hw: pointer to the HW structure
278 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) in e1000_init_function_pointers_80003es2lan() argument
282 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; in e1000_init_function_pointers_80003es2lan()
283 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; in e1000_init_function_pointers_80003es2lan()
284 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; in e1000_init_function_pointers_80003es2lan()
288 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
289 * @hw: pointer to the HW structure
293 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) in e1000_acquire_phy_80003es2lan() argument
299 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; in e1000_acquire_phy_80003es2lan()
300 return e1000_acquire_swfw_sync(hw, mask); in e1000_acquire_phy_80003es2lan()
304 * e1000_release_phy_80003es2lan - Release rights to access PHY
305 * @hw: pointer to the HW structure
309 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) in e1000_release_phy_80003es2lan() argument
315 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; in e1000_release_phy_80003es2lan()
316 e1000_release_swfw_sync(hw, mask); in e1000_release_phy_80003es2lan()
320 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
321 * @hw: pointer to the HW structure
326 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) in e1000_acquire_mac_csr_80003es2lan() argument
334 return e1000_acquire_swfw_sync(hw, mask); in e1000_acquire_mac_csr_80003es2lan()
338 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
339 * @hw: pointer to the HW structure
343 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) in e1000_release_mac_csr_80003es2lan() argument
351 e1000_release_swfw_sync(hw, mask); in e1000_release_mac_csr_80003es2lan()
355 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
356 * @hw: pointer to the HW structure
360 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) in e1000_acquire_nvm_80003es2lan() argument
366 ret_val = e1000_acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); in e1000_acquire_nvm_80003es2lan()
370 ret_val = e1000_acquire_nvm_generic(hw); in e1000_acquire_nvm_80003es2lan()
373 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); in e1000_acquire_nvm_80003es2lan()
379 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
380 * @hw: pointer to the HW structure
384 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) in e1000_release_nvm_80003es2lan() argument
388 e1000_release_nvm_generic(hw); in e1000_release_nvm_80003es2lan()
389 e1000_release_swfw_sync(hw, E1000_SWFW_EEP_SM); in e1000_release_nvm_80003es2lan()
393 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
394 * @hw: pointer to the HW structure
400 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, in e1000_read_phy_reg_gg82563_80003es2lan() argument
409 ret_val = e1000_acquire_phy_80003es2lan(hw); in e1000_read_phy_reg_gg82563_80003es2lan()
424 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); in e1000_read_phy_reg_gg82563_80003es2lan()
426 e1000_release_phy_80003es2lan(hw); in e1000_read_phy_reg_gg82563_80003es2lan()
430 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { in e1000_read_phy_reg_gg82563_80003es2lan()
438 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); in e1000_read_phy_reg_gg82563_80003es2lan()
441 e1000_release_phy_80003es2lan(hw); in e1000_read_phy_reg_gg82563_80003es2lan()
442 return -E1000_ERR_PHY; in e1000_read_phy_reg_gg82563_80003es2lan()
447 ret_val = e1000_read_phy_reg_mdic(hw, in e1000_read_phy_reg_gg82563_80003es2lan()
453 ret_val = e1000_read_phy_reg_mdic(hw, in e1000_read_phy_reg_gg82563_80003es2lan()
458 e1000_release_phy_80003es2lan(hw); in e1000_read_phy_reg_gg82563_80003es2lan()
464 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
465 * @hw: pointer to the HW structure
471 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, in e1000_write_phy_reg_gg82563_80003es2lan() argument
480 ret_val = e1000_acquire_phy_80003es2lan(hw); in e1000_write_phy_reg_gg82563_80003es2lan()
495 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); in e1000_write_phy_reg_gg82563_80003es2lan()
497 e1000_release_phy_80003es2lan(hw); in e1000_write_phy_reg_gg82563_80003es2lan()
501 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { in e1000_write_phy_reg_gg82563_80003es2lan()
509 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); in e1000_write_phy_reg_gg82563_80003es2lan()
512 e1000_release_phy_80003es2lan(hw); in e1000_write_phy_reg_gg82563_80003es2lan()
513 return -E1000_ERR_PHY; in e1000_write_phy_reg_gg82563_80003es2lan()
518 ret_val = e1000_write_phy_reg_mdic(hw, in e1000_write_phy_reg_gg82563_80003es2lan()
524 ret_val = e1000_write_phy_reg_mdic(hw, in e1000_write_phy_reg_gg82563_80003es2lan()
529 e1000_release_phy_80003es2lan(hw); in e1000_write_phy_reg_gg82563_80003es2lan()
535 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
536 * @hw: pointer to the HW structure
543 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, in e1000_write_nvm_80003es2lan() argument
548 return e1000_write_nvm_spi(hw, offset, words, data); in e1000_write_nvm_80003es2lan()
552 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
553 * @hw: pointer to the HW structure
558 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) in e1000_get_cfg_done_80003es2lan() argument
565 if (hw->bus.func == 1) in e1000_get_cfg_done_80003es2lan()
569 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) in e1000_get_cfg_done_80003es2lan()
572 timeout--; in e1000_get_cfg_done_80003es2lan()
576 return -E1000_ERR_RESET; in e1000_get_cfg_done_80003es2lan()
583 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
584 * @hw: pointer to the HW structure
589 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) in e1000_phy_force_speed_duplex_80003es2lan() argument
597 if (!(hw->phy.ops.read_reg)) in e1000_phy_force_speed_duplex_80003es2lan()
600 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI in e1000_phy_force_speed_duplex_80003es2lan()
603 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
608 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
614 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
618 e1000_phy_force_speed_duplex_setup(hw, &phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
623 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
629 if (hw->phy.autoneg_wait_to_complete) { in e1000_phy_force_speed_duplex_80003es2lan()
632 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, in e1000_phy_force_speed_duplex_80003es2lan()
641 ret_val = e1000_phy_reset_dsp_generic(hw); in e1000_phy_force_speed_duplex_80003es2lan()
647 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, in e1000_phy_force_speed_duplex_80003es2lan()
653 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
659 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. in e1000_phy_force_speed_duplex_80003es2lan()
662 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) in e1000_phy_force_speed_duplex_80003es2lan()
667 /* In addition, we must re-enable CRS on Tx for both half and full in e1000_phy_force_speed_duplex_80003es2lan()
671 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
678 * e1000_get_cable_length_80003es2lan - Set approximate cable length
679 * @hw: pointer to the HW structure
684 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) in e1000_get_cable_length_80003es2lan() argument
686 struct e1000_phy_info *phy = &hw->phy; in e1000_get_cable_length_80003es2lan()
692 if (!(hw->phy.ops.read_reg)) in e1000_get_cable_length_80003es2lan()
695 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); in e1000_get_cable_length_80003es2lan()
701 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) in e1000_get_cable_length_80003es2lan()
702 return -E1000_ERR_PHY; in e1000_get_cable_length_80003es2lan()
704 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; in e1000_get_cable_length_80003es2lan()
705 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; in e1000_get_cable_length_80003es2lan()
707 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; in e1000_get_cable_length_80003es2lan()
713 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
714 * @hw: pointer to the HW structure
720 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, in e1000_get_link_up_info_80003es2lan() argument
727 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_up_info_80003es2lan()
728 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, in e1000_get_link_up_info_80003es2lan()
730 hw->phy.ops.cfg_on_link_up(hw); in e1000_get_link_up_info_80003es2lan()
732 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, in e1000_get_link_up_info_80003es2lan()
741 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
742 * @hw: pointer to the HW structure
746 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) in e1000_reset_hw_80003es2lan() argument
754 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_80003es2lan()
757 ret_val = e1000_disable_pcie_master_generic(hw); in e1000_reset_hw_80003es2lan()
759 DEBUGOUT("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_80003es2lan()
762 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_80003es2lan()
764 E1000_WRITE_REG(hw, E1000_RCTL, 0); in e1000_reset_hw_80003es2lan()
765 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); in e1000_reset_hw_80003es2lan()
766 E1000_WRITE_FLUSH(hw); in e1000_reset_hw_80003es2lan()
770 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_reset_hw_80003es2lan()
772 ret_val = e1000_acquire_phy_80003es2lan(hw); in e1000_reset_hw_80003es2lan()
777 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); in e1000_reset_hw_80003es2lan()
778 e1000_release_phy_80003es2lan(hw); in e1000_reset_hw_80003es2lan()
780 /* Disable IBIST slave mode (far-end loopback) */ in e1000_reset_hw_80003es2lan()
781 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, in e1000_reset_hw_80003es2lan()
785 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, in e1000_reset_hw_80003es2lan()
789 DEBUGOUT("Error disabling far-end loopback\n"); in e1000_reset_hw_80003es2lan()
791 DEBUGOUT("Error disabling far-end loopback\n"); in e1000_reset_hw_80003es2lan()
793 ret_val = e1000_get_auto_rd_done_generic(hw); in e1000_reset_hw_80003es2lan()
799 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); in e1000_reset_hw_80003es2lan()
800 E1000_READ_REG(hw, E1000_ICR); in e1000_reset_hw_80003es2lan()
802 return e1000_check_alt_mac_addr_generic(hw); in e1000_reset_hw_80003es2lan()
806 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
807 * @hw: pointer to the HW structure
809 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
811 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) in e1000_init_hw_80003es2lan() argument
813 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_80003es2lan()
821 e1000_initialize_hw_bits_80003es2lan(hw); in e1000_init_hw_80003es2lan()
824 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_80003es2lan()
831 mac->ops.clear_vfta(hw); in e1000_init_hw_80003es2lan()
834 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); in e1000_init_hw_80003es2lan()
838 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_80003es2lan()
839 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_80003es2lan()
842 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_80003es2lan()
846 /* Disable IBIST slave mode (far-end loopback) */ in e1000_init_hw_80003es2lan()
848 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, in e1000_init_hw_80003es2lan()
852 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, in e1000_init_hw_80003es2lan()
856 DEBUGOUT("Error disabling far-end loopback\n"); in e1000_init_hw_80003es2lan()
858 DEBUGOUT("Error disabling far-end loopback\n"); in e1000_init_hw_80003es2lan()
860 /* Set the transmit descriptor write-back policy */ in e1000_init_hw_80003es2lan()
861 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_80003es2lan()
864 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan()
867 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_80003es2lan()
870 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan()
873 reg_data = E1000_READ_REG(hw, E1000_TCTL); in e1000_init_hw_80003es2lan()
875 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); in e1000_init_hw_80003es2lan()
878 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); in e1000_init_hw_80003es2lan()
881 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); in e1000_init_hw_80003es2lan()
883 /* Configure Transmit Inter-Packet Gap */ in e1000_init_hw_80003es2lan()
884 reg_data = E1000_READ_REG(hw, E1000_TIPG); in e1000_init_hw_80003es2lan()
887 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); in e1000_init_hw_80003es2lan()
889 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); in e1000_init_hw_80003es2lan()
891 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); in e1000_init_hw_80003es2lan()
894 hw->dev_spec._80003es2lan.mdic_wa_enable = true; in e1000_init_hw_80003es2lan()
897 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> in e1000_init_hw_80003es2lan()
902 hw->dev_spec._80003es2lan.mdic_wa_enable = false; in e1000_init_hw_80003es2lan()
910 e1000_clear_hw_cntrs_80003es2lan(hw); in e1000_init_hw_80003es2lan()
916 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
917 * @hw: pointer to the HW structure
919 * Initializes required hardware-dependent bits needed for normal operation.
921 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) in e1000_initialize_hw_bits_80003es2lan() argument
928 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_initialize_hw_bits_80003es2lan()
930 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); in e1000_initialize_hw_bits_80003es2lan()
933 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_initialize_hw_bits_80003es2lan()
935 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); in e1000_initialize_hw_bits_80003es2lan()
938 reg = E1000_READ_REG(hw, E1000_TARC(0)); in e1000_initialize_hw_bits_80003es2lan()
940 if (hw->phy.media_type != e1000_media_type_copper) in e1000_initialize_hw_bits_80003es2lan()
942 E1000_WRITE_REG(hw, E1000_TARC(0), reg); in e1000_initialize_hw_bits_80003es2lan()
945 reg = E1000_READ_REG(hw, E1000_TARC(1)); in e1000_initialize_hw_bits_80003es2lan()
946 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) in e1000_initialize_hw_bits_80003es2lan()
950 E1000_WRITE_REG(hw, E1000_TARC(1), reg); in e1000_initialize_hw_bits_80003es2lan()
955 reg = E1000_READ_REG(hw, E1000_RFCTL); in e1000_initialize_hw_bits_80003es2lan()
957 E1000_WRITE_REG(hw, E1000_RFCTL, reg); in e1000_initialize_hw_bits_80003es2lan()
963 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
964 * @hw: pointer to the HW structure
968 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) in e1000_copper_link_setup_gg82563_80003es2lan() argument
970 struct e1000_phy_info *phy = &hw->phy; in e1000_copper_link_setup_gg82563_80003es2lan()
977 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
982 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ in e1000_copper_link_setup_gg82563_80003es2lan()
985 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
990 * MDI/MDI-X = 0 (default) in e1000_copper_link_setup_gg82563_80003es2lan()
991 * 0 - Auto for all speeds in e1000_copper_link_setup_gg82563_80003es2lan()
992 * 1 - MDI mode in e1000_copper_link_setup_gg82563_80003es2lan()
993 * 2 - MDI-X mode in e1000_copper_link_setup_gg82563_80003es2lan()
994 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) in e1000_copper_link_setup_gg82563_80003es2lan()
996 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
1002 switch (phy->mdix) { in e1000_copper_link_setup_gg82563_80003es2lan()
1018 * 0 - Disabled in e1000_copper_link_setup_gg82563_80003es2lan()
1019 * 1 - Enabled in e1000_copper_link_setup_gg82563_80003es2lan()
1022 if (phy->disable_polarity_correction) in e1000_copper_link_setup_gg82563_80003es2lan()
1025 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1030 ret_val = hw->phy.ops.commit(hw); in e1000_copper_link_setup_gg82563_80003es2lan()
1040 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1045 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
1049 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1053 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1062 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); in e1000_copper_link_setup_gg82563_80003es2lan()
1064 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); in e1000_copper_link_setup_gg82563_80003es2lan()
1066 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
1070 /* Do not init these registers when the HW is in IAMT mode, since the in e1000_copper_link_setup_gg82563_80003es2lan()
1072 * them if the HW is not in IAMT mode. in e1000_copper_link_setup_gg82563_80003es2lan()
1074 if (!hw->mac.ops.check_mng_mode(hw)) { in e1000_copper_link_setup_gg82563_80003es2lan()
1077 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1082 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1088 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1097 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); in e1000_copper_link_setup_gg82563_80003es2lan()
1102 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1110 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1111 * @hw: pointer to the HW structure
1116 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) in e1000_setup_copper_link_80003es2lan() argument
1124 ctrl = E1000_READ_REG(hw, E1000_CTRL); in e1000_setup_copper_link_80003es2lan()
1127 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); in e1000_setup_copper_link_80003es2lan()
1133 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), in e1000_setup_copper_link_80003es2lan()
1137 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
1142 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), in e1000_setup_copper_link_80003es2lan()
1147 e1000_read_kmrn_reg_80003es2lan(hw, in e1000_setup_copper_link_80003es2lan()
1154 e1000_write_kmrn_reg_80003es2lan(hw, in e1000_setup_copper_link_80003es2lan()
1160 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); in e1000_setup_copper_link_80003es2lan()
1164 return e1000_setup_copper_link_generic(hw); in e1000_setup_copper_link_80003es2lan()
1168 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1169 * @hw: pointer to the HW structure
1174 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) in e1000_cfg_on_link_up_80003es2lan() argument
1182 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_cfg_on_link_up_80003es2lan()
1183 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, in e1000_cfg_on_link_up_80003es2lan()
1189 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); in e1000_cfg_on_link_up_80003es2lan()
1191 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); in e1000_cfg_on_link_up_80003es2lan()
1198 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1199 * @hw: pointer to the HW structure
1205 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) in e1000_cfg_kmrn_10_100_80003es2lan() argument
1216 e1000_write_kmrn_reg_80003es2lan(hw, in e1000_cfg_kmrn_10_100_80003es2lan()
1222 /* Configure Transmit Inter-Packet Gap */ in e1000_cfg_kmrn_10_100_80003es2lan()
1223 tipg = E1000_READ_REG(hw, E1000_TIPG); in e1000_cfg_kmrn_10_100_80003es2lan()
1226 E1000_WRITE_REG(hw, E1000_TIPG, tipg); in e1000_cfg_kmrn_10_100_80003es2lan()
1229 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_cfg_kmrn_10_100_80003es2lan()
1234 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_cfg_kmrn_10_100_80003es2lan()
1246 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); in e1000_cfg_kmrn_10_100_80003es2lan()
1250 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1251 * @hw: pointer to the HW structure
1256 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) in e1000_cfg_kmrn_1000_80003es2lan() argument
1267 e1000_write_kmrn_reg_80003es2lan(hw, in e1000_cfg_kmrn_1000_80003es2lan()
1273 /* Configure Transmit Inter-Packet Gap */ in e1000_cfg_kmrn_1000_80003es2lan()
1274 tipg = E1000_READ_REG(hw, E1000_TIPG); in e1000_cfg_kmrn_1000_80003es2lan()
1277 E1000_WRITE_REG(hw, E1000_TIPG, tipg); in e1000_cfg_kmrn_1000_80003es2lan()
1280 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_cfg_kmrn_1000_80003es2lan()
1285 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_cfg_kmrn_1000_80003es2lan()
1294 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); in e1000_cfg_kmrn_1000_80003es2lan()
1298 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1299 * @hw: pointer to the HW structure
1307 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, in e1000_read_kmrn_reg_80003es2lan() argument
1315 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); in e1000_read_kmrn_reg_80003es2lan()
1321 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); in e1000_read_kmrn_reg_80003es2lan()
1322 E1000_WRITE_FLUSH(hw); in e1000_read_kmrn_reg_80003es2lan()
1326 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); in e1000_read_kmrn_reg_80003es2lan()
1329 e1000_release_mac_csr_80003es2lan(hw); in e1000_read_kmrn_reg_80003es2lan()
1335 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1336 * @hw: pointer to the HW structure
1344 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, in e1000_write_kmrn_reg_80003es2lan() argument
1352 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); in e1000_write_kmrn_reg_80003es2lan()
1358 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); in e1000_write_kmrn_reg_80003es2lan()
1359 E1000_WRITE_FLUSH(hw); in e1000_write_kmrn_reg_80003es2lan()
1363 e1000_release_mac_csr_80003es2lan(hw); in e1000_write_kmrn_reg_80003es2lan()
1369 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1370 * @hw: pointer to the HW structure
1372 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) in e1000_read_mac_addr_80003es2lan() argument
1382 ret_val = e1000_check_alt_mac_addr_generic(hw); in e1000_read_mac_addr_80003es2lan()
1386 return e1000_read_mac_addr_generic(hw); in e1000_read_mac_addr_80003es2lan()
1390 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1391 * @hw: pointer to the HW structure
1396 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) in e1000_power_down_phy_copper_80003es2lan() argument
1399 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_80003es2lan()
1400 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_80003es2lan()
1401 e1000_power_down_phy_copper(hw); in e1000_power_down_phy_copper_80003es2lan()
1407 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1408 * @hw: pointer to the HW structure
1412 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) in e1000_clear_hw_cntrs_80003es2lan() argument
1416 e1000_clear_hw_cntrs_base_generic(hw); in e1000_clear_hw_cntrs_80003es2lan()
1418 E1000_READ_REG(hw, E1000_PRC64); in e1000_clear_hw_cntrs_80003es2lan()
1419 E1000_READ_REG(hw, E1000_PRC127); in e1000_clear_hw_cntrs_80003es2lan()
1420 E1000_READ_REG(hw, E1000_PRC255); in e1000_clear_hw_cntrs_80003es2lan()
1421 E1000_READ_REG(hw, E1000_PRC511); in e1000_clear_hw_cntrs_80003es2lan()
1422 E1000_READ_REG(hw, E1000_PRC1023); in e1000_clear_hw_cntrs_80003es2lan()
1423 E1000_READ_REG(hw, E1000_PRC1522); in e1000_clear_hw_cntrs_80003es2lan()
1424 E1000_READ_REG(hw, E1000_PTC64); in e1000_clear_hw_cntrs_80003es2lan()
1425 E1000_READ_REG(hw, E1000_PTC127); in e1000_clear_hw_cntrs_80003es2lan()
1426 E1000_READ_REG(hw, E1000_PTC255); in e1000_clear_hw_cntrs_80003es2lan()
1427 E1000_READ_REG(hw, E1000_PTC511); in e1000_clear_hw_cntrs_80003es2lan()
1428 E1000_READ_REG(hw, E1000_PTC1023); in e1000_clear_hw_cntrs_80003es2lan()
1429 E1000_READ_REG(hw, E1000_PTC1522); in e1000_clear_hw_cntrs_80003es2lan()
1431 E1000_READ_REG(hw, E1000_ALGNERRC); in e1000_clear_hw_cntrs_80003es2lan()
1432 E1000_READ_REG(hw, E1000_RXERRC); in e1000_clear_hw_cntrs_80003es2lan()
1433 E1000_READ_REG(hw, E1000_TNCRS); in e1000_clear_hw_cntrs_80003es2lan()
1434 E1000_READ_REG(hw, E1000_CEXTERR); in e1000_clear_hw_cntrs_80003es2lan()
1435 E1000_READ_REG(hw, E1000_TSCTC); in e1000_clear_hw_cntrs_80003es2lan()
1436 E1000_READ_REG(hw, E1000_TSCTFC); in e1000_clear_hw_cntrs_80003es2lan()
1438 E1000_READ_REG(hw, E1000_MGTPRC); in e1000_clear_hw_cntrs_80003es2lan()
1439 E1000_READ_REG(hw, E1000_MGTPDC); in e1000_clear_hw_cntrs_80003es2lan()
1440 E1000_READ_REG(hw, E1000_MGTPTC); in e1000_clear_hw_cntrs_80003es2lan()
1442 E1000_READ_REG(hw, E1000_IAC); in e1000_clear_hw_cntrs_80003es2lan()
1443 E1000_READ_REG(hw, E1000_ICRXOC); in e1000_clear_hw_cntrs_80003es2lan()
1445 E1000_READ_REG(hw, E1000_ICRXPTC); in e1000_clear_hw_cntrs_80003es2lan()
1446 E1000_READ_REG(hw, E1000_ICRXATC); in e1000_clear_hw_cntrs_80003es2lan()
1447 E1000_READ_REG(hw, E1000_ICTXPTC); in e1000_clear_hw_cntrs_80003es2lan()
1448 E1000_READ_REG(hw, E1000_ICTXATC); in e1000_clear_hw_cntrs_80003es2lan()
1449 E1000_READ_REG(hw, E1000_ICTXQEC); in e1000_clear_hw_cntrs_80003es2lan()
1450 E1000_READ_REG(hw, E1000_ICTXQMTC); in e1000_clear_hw_cntrs_80003es2lan()
1451 E1000_READ_REG(hw, E1000_ICRXDMTC); in e1000_clear_hw_cntrs_80003es2lan()