1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
127 	struct syscon		*grf;  member
139 	/* PHY clock */
167 	{"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
168 	{"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
169 	{"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
179 	if (!mii_contype_is_rgmii(sc->base.phy_mode))  in rk3328_set_delays()
182 	reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON0);  in rk3328_set_delays()
186 	reg = SYSCON_READ_4(sc->grf, RK3328_GRF_MAC_CON1);  in rk3328_set_delays()
188 		device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",  in rk3328_set_delays()
192 		device_printf(sc->base.dev, "setting new RK3328 RX/TX delays:  %d/%d\n",  in rk3328_set_delays()
193 			sc->tx_delay, sc->rx_delay);  in rk3328_set_delays()
198 	SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1, reg);  in rk3328_set_delays()
201 	reg |= ((sc->tx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<  in rk3328_set_delays()
203 	reg |= ((sc->rx_delay & MAC_CON0_GMAC2IO_TX_DL_CFG_MASK) <<  in rk3328_set_delays()
205 	SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON0, reg);  in rk3328_set_delays()
213 	switch (sc->base.phy_mode) {  in rk3328_set_speed()
230 			device_printf(sc->base.dev, "unsupported RGMII media %u\n", speed);  in rk3328_set_speed()
231 			return (-1);  in rk3328_set_speed()
234 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,  in rk3328_set_speed()
248 			device_printf(sc->base.dev, "unsupported RMII media %u\n", speed);  in rk3328_set_speed()
249 			return (-1);  in rk3328_set_speed()
252 		SYSCON_WRITE_4(sc->grf,  in rk3328_set_speed()
253 		    sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,  in rk3328_set_speed()
266 	switch (sc->base.phy_mode) {  in rk3328_set_phy_mode()
271 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MAC_CON1,  in rk3328_set_phy_mode()
276 		SYSCON_WRITE_4(sc->grf, sc->integrated_phy ? RK3328_GRF_MAC_CON2 : RK3328_GRF_MAC_CON1,  in rk3328_set_phy_mode()
286 	SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON1,  in rk3328_phy_powerup()
296 	if (!mii_contype_is_rgmii(sc->base.phy_mode))  in rk3399_set_delays()
299 	reg = SYSCON_READ_4(sc->grf, RK3399_GRF_SOC_CON6);  in rk3399_set_delays()
304 		device_printf(sc->base.dev, "current delays settings: tx=%u(%s) rx=%u(%s)\n",  in rk3399_set_delays()
308 		device_printf(sc->base.dev, "setting new RK3399 RX/TX delays:  %d/%d\n",  in rk3399_set_delays()
309 		    sc->rx_delay, sc->tx_delay);  in rk3399_set_delays()
313 	reg |= ((sc->tx_delay & SOC_CON6_TX_DL_CFG_MASK) <<  in rk3399_set_delays()
315 	reg |= ((sc->rx_delay & SOC_CON6_RX_DL_CFG_MASK) <<  in rk3399_set_delays()
319 	SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON6, reg);  in rk3399_set_delays()
339 		device_printf(sc->base.dev, "unsupported media %u\n", speed);  in rk3399_set_speed()
340 		return (-1);  in rk3399_set_speed()
343 	SYSCON_WRITE_4(sc->grf, RK3399_GRF_SOC_CON5,  in rk3399_set_speed()
356 	rxtx = ((sc->rx_delay << 8) | sc->tx_delay);  in if_dwc_rk_sysctl_delays()
359 	if (rv != 0 || req->newptr == NULL)  in if_dwc_rk_sysctl_delays()
361 	sc->tx_delay = rxtx & 0xff;  in if_dwc_rk_sysctl_delays()
362 	sc->rx_delay = (rxtx >> 8) & 0xff;  in if_dwc_rk_sysctl_delays()
364 	if (sc->ops->set_delays)  in if_dwc_rk_sysctl_delays()
365 	    sc->ops->set_delays(sc);  in if_dwc_rk_sysctl_delays()
376 	ctx_list = device_get_sysctl_ctx(sc->base.dev);  in if_dwc_rk_init_sysctl()
377 	child = device_get_sysctl_tree(sc->base.dev);  in if_dwc_rk_init_sysctl()
392 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in if_dwc_rk_probe()
408 	if (clk_get_by_ofw_name(dev, 0, "mac_clk_tx", &sc->mac_clk_tx) != 0) {  in if_dwc_rk_init_clocks()
409 		device_printf(sc->base.dev, "could not get mac_clk_tx clock\n");  in if_dwc_rk_init_clocks()
410 		sc->mac_clk_tx = NULL;  in if_dwc_rk_init_clocks()
413 	if (clk_get_by_ofw_name(dev, 0, "aclk_mac", &sc->aclk_mac) != 0) {  in if_dwc_rk_init_clocks()
414 		device_printf(sc->base.dev, "could not get aclk_mac clock\n");  in if_dwc_rk_init_clocks()
415 		sc->aclk_mac = NULL;  in if_dwc_rk_init_clocks()
418 	if (clk_get_by_ofw_name(dev, 0, "pclk_mac", &sc->pclk_mac) != 0) {  in if_dwc_rk_init_clocks()
419 		device_printf(sc->base.dev, "could not get pclk_mac clock\n");  in if_dwc_rk_init_clocks()
420 		sc->pclk_mac = NULL;  in if_dwc_rk_init_clocks()
424 	clk_get_by_ofw_name(dev, 0, "clk_mac_speed", &sc->clk_mac_speed);  in if_dwc_rk_init_clocks()
426 	if (sc->base.phy_mode == MII_CONTYPE_RMII) {  in if_dwc_rk_init_clocks()
427 		if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &sc->mac_clk_rx) != 0) {  in if_dwc_rk_init_clocks()
428 			device_printf(sc->base.dev, "could not get mac_clk_rx clock\n");  in if_dwc_rk_init_clocks()
429 			sc->mac_clk_rx = NULL;  in if_dwc_rk_init_clocks()
432 		if (clk_get_by_ofw_name(dev, 0, "clk_mac_ref", &sc->clk_mac_ref) != 0) {  in if_dwc_rk_init_clocks()
433 			device_printf(sc->base.dev, "could not get clk_mac_ref clock\n");  in if_dwc_rk_init_clocks()
434 			sc->clk_mac_ref = NULL;  in if_dwc_rk_init_clocks()
437 		if (!sc->clock_in) {  in if_dwc_rk_init_clocks()
438 			if (clk_get_by_ofw_name(dev, 0, "clk_mac_refout", &sc->clk_mac_refout) != 0) {  in if_dwc_rk_init_clocks()
439 				device_printf(sc->base.dev, "could not get clk_mac_refout clock\n");  in if_dwc_rk_init_clocks()
440 				sc->clk_mac_refout = NULL;  in if_dwc_rk_init_clocks()
443 			clk_set_freq(sc->clk_stmmaceth, 50000000, 0);  in if_dwc_rk_init_clocks()
447 	if ((sc->phy_node != 0) && sc->integrated_phy) {  in if_dwc_rk_init_clocks()
448 		if (clk_get_by_ofw_index(dev, sc->phy_node, 0, &sc->clk_phy) != 0) {  in if_dwc_rk_init_clocks()
449 			device_printf(sc->base.dev, "could not get PHY clock\n");  in if_dwc_rk_init_clocks()
450 			sc->clk_phy = NULL;  in if_dwc_rk_init_clocks()
453 		if (sc->clk_phy) {  in if_dwc_rk_init_clocks()
454 			clk_set_freq(sc->clk_phy, 50000000, 0);  in if_dwc_rk_init_clocks()
458 	if (sc->base.phy_mode == MII_CONTYPE_RMII) {  in if_dwc_rk_init_clocks()
459 		if (sc->mac_clk_rx)  in if_dwc_rk_init_clocks()
460 			clk_enable(sc->mac_clk_rx);  in if_dwc_rk_init_clocks()
461 		if (sc->clk_mac_ref)  in if_dwc_rk_init_clocks()
462 			clk_enable(sc->clk_mac_ref);  in if_dwc_rk_init_clocks()
463 		if (sc->clk_mac_refout)  in if_dwc_rk_init_clocks()
464 			clk_enable(sc->clk_mac_refout);  in if_dwc_rk_init_clocks()
466 	if (sc->clk_phy)  in if_dwc_rk_init_clocks()
467 		clk_enable(sc->clk_phy);  in if_dwc_rk_init_clocks()
468 	if (sc->aclk_mac)  in if_dwc_rk_init_clocks()
469 		clk_enable(sc->aclk_mac);  in if_dwc_rk_init_clocks()
470 	if (sc->pclk_mac)  in if_dwc_rk_init_clocks()
471 		clk_enable(sc->pclk_mac);  in if_dwc_rk_init_clocks()
472 	if (sc->mac_clk_tx)  in if_dwc_rk_init_clocks()
473 		clk_enable(sc->mac_clk_tx);  in if_dwc_rk_init_clocks()
474 	if (sc->clk_mac_speed)  in if_dwc_rk_init_clocks()
475 		clk_enable(sc->clk_mac_speed);  in if_dwc_rk_init_clocks()
496 	sc->ops = (struct if_dwc_rk_ops *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;  in if_dwc_rk_init()
497 	if (OF_hasprop(node, "rockchip,grf") &&  in if_dwc_rk_init()
499 	    "rockchip,grf", &sc->grf) != 0) {  in if_dwc_rk_init()
500 		device_printf(dev, "cannot get grf driver handle\n");  in if_dwc_rk_init()
508 	sc->tx_delay = tx;  in if_dwc_rk_init()
509 	sc->rx_delay = rx;  in if_dwc_rk_init()
511 	sc->clock_in = true;  in if_dwc_rk_init()
514 			sc->clock_in = true;  in if_dwc_rk_init()
516 			sc->clock_in = false;  in if_dwc_rk_init()
520 	if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,  in if_dwc_rk_init()
522 		sc->phy_node = OF_node_from_xref(phy_handle);  in if_dwc_rk_init()
524 	if (sc->phy_node)  in if_dwc_rk_init()
525 		sc->integrated_phy = OF_hasprop(sc->phy_node, "phy-is-integrated");  in if_dwc_rk_init()
527 	if (sc->integrated_phy)  in if_dwc_rk_init()
528 		device_printf(sc->base.dev, "PHY is integrated\n");  in if_dwc_rk_init()
532 	if (sc->ops->set_phy_mode)  in if_dwc_rk_init()
533 	    sc->ops->set_phy_mode(sc);  in if_dwc_rk_init()
535 	if (sc->ops->set_delays)  in if_dwc_rk_init()
536 	    sc->ops->set_delays(sc);  in if_dwc_rk_init()
545 	if (regulator_get_by_ofw_property(sc->base.dev, 0,  in if_dwc_rk_init()
546 		            "phy-supply", &phy_supply) == 0) {  in if_dwc_rk_init()
548 			device_printf(sc->base.dev,  in if_dwc_rk_init()
549 			    "cannot enable 'phy' regulator\n");  in if_dwc_rk_init()
553 		device_printf(sc->base.dev, "no phy-supply property\n");  in if_dwc_rk_init()
556 	if (sc->integrated_phy) {  in if_dwc_rk_init()
557 		if (sc->ops->phy_powerup)  in if_dwc_rk_init()
558 			sc->ops->phy_powerup(sc);  in if_dwc_rk_init()
560 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,  in if_dwc_rk_init()
563 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON0,  in if_dwc_rk_init()
566 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON2, 0xffff1234);  in if_dwc_rk_init()
567 		SYSCON_WRITE_4(sc->grf, RK3328_GRF_MACPHY_CON3, 0x003f0035);  in if_dwc_rk_init()
569 		if (hwreset_get_by_ofw_idx(dev, sc->phy_node, 0, &phy_reset)  == 0) {  in if_dwc_rk_init()
588 	if ((rv = clk_get_freq(sc->pclk_mac, &freq)) != 0)  in if_dwc_rk_mii_clk()
589 		return (-rv);  in if_dwc_rk_mii_clk()
605 	return (-ERANGE);  in if_dwc_rk_mii_clk()
615 	if (sc->ops->set_speed)  in if_dwc_rk_set_speed()
616 	    return sc->ops->set_speed(sc, speed);  in if_dwc_rk_set_speed()