Lines Matching +full:0 +full:x584
37 #define MAC_CONFIGURATION 0x0
47 #define MAC_FRAME_FILTER 0x4
53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
54 #define GMAC_MAC_HTHIGH 0x08
55 #define GMAC_MAC_HTLOW 0x0c
56 #define GMII_ADDRESS 0x10
57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
61 #define GMII_ADDRESS_CR_MASK 0xf
64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
65 #define GMII_DATA 0x14
66 #define FLOW_CONTROL 0x18
71 #define GMAC_VLAN_TAG 0x1C
72 #define VERSION 0x20
73 #define GMAC_DEBUG 0x24
74 #define LPI_CONTROL_STATUS 0x30
75 #define LPI_TIMERS_CONTROL 0x34
76 #define INTERRUPT_STATUS 0x38
77 #define INTERRUPT_MASK 0x3C
78 #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n)
79 #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n)
81 #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8
82 #define MMC_CONTROL 0x100
83 #define MMC_CONTROL_CNTRST (1 << 0)
84 #define MMC_RECEIVE_INTERRUPT 0x104
85 #define MMC_TRANSMIT_INTERRUPT 0x108
86 #define MMC_RECEIVE_INTERRUPT_MASK 0x10C
87 #define MMC_TRANSMIT_INTERRUPT_MASK 0x110
88 #define TXOCTETCOUNT_GB 0x114
89 #define TXFRAMECOUNT_GB 0x118
90 #define TXBROADCASTFRAMES_G 0x11C
91 #define TXMULTICASTFRAMES_G 0x120
92 #define TX64OCTETS_GB 0x124
93 #define TX65TO127OCTETS_GB 0x128
94 #define TX128TO255OCTETS_GB 0x12C
95 #define TX256TO511OCTETS_GB 0x130
96 #define TX512TO1023OCTETS_GB 0x134
97 #define TX1024TOMAXOCTETS_GB 0x138
98 #define TXUNICASTFRAMES_GB 0x13C
99 #define TXMULTICASTFRAMES_GB 0x140
100 #define TXBROADCASTFRAMES_GB 0x144
101 #define TXUNDERFLOWERROR 0x148
102 #define TXSINGLECOL_G 0x14C
103 #define TXMULTICOL_G 0x150
104 #define TXDEFERRED 0x154
105 #define TXLATECOL 0x158
106 #define TXEXESSCOL 0x15C
107 #define TXCARRIERERR 0x160
108 #define TXOCTETCNT 0x164
109 #define TXFRAMECOUNT_G 0x168
110 #define TXEXCESSDEF 0x16C
111 #define TXPAUSEFRAMES 0x170
112 #define TXVLANFRAMES_G 0x174
113 #define TXOVERSIZE_G 0x178
114 #define RXFRAMECOUNT_GB 0x180
115 #define RXOCTETCOUNT_GB 0x184
116 #define RXOCTETCOUNT_G 0x188
117 #define RXBROADCASTFRAMES_G 0x18C
118 #define RXMULTICASTFRAMES_G 0x190
119 #define RXCRCERROR 0x194
120 #define RXALIGNMENTERROR 0x198
121 #define RXRUNTERROR 0x19C
122 #define RXJABBERERROR 0x1A0
123 #define RXUNDERSIZE_G 0x1A4
124 #define RXOVERSIZE_G 0x1A8
125 #define RX64OCTETS_GB 0x1AC
126 #define RX65TO127OCTETS_GB 0x1B0
127 #define RX128TO255OCTETS_GB 0x1B4
128 #define RX256TO511OCTETS_GB 0x1B8
129 #define RX512TO1023OCTETS_GB 0x1BC
130 #define RX1024TOMAXOCTETS_GB 0x1C0
131 #define RXUNICASTFRAMES_G 0x1C4
132 #define RXLENGTHERROR 0x1C8
133 #define RXOUTOFRANGETYPE 0x1CC
134 #define RXPAUSEFRAMES 0x1D0
135 #define RXFIFOOVERFLOW 0x1D4
136 #define RXVLANFRAMES_GB 0x1D8
137 #define RXWATCHDOGERROR 0x1DC
138 #define RXRCVERROR 0x1E0
139 #define RXCTRLFRAMES_G 0x1E4
140 #define MMC_IPC_RECEIVE_INT_MASK 0x200
141 #define MMC_IPC_RECEIVE_INT 0x208
142 #define RXIPV4_GD_FRMS 0x210
143 #define RXIPV4_HDRERR_FRMS 0x214
144 #define RXIPV4_NOPAY_FRMS 0x218
145 #define RXIPV4_FRAG_FRMS 0x21C
146 #define RXIPV4_UDSBL_FRMS 0x220
147 #define RXIPV6_GD_FRMS 0x224
148 #define RXIPV6_HDRERR_FRMS 0x228
149 #define RXIPV6_NOPAY_FRMS 0x22C
150 #define RXUDP_GD_FRMS 0x230
151 #define RXUDP_ERR_FRMS 0x234
152 #define RXTCP_GD_FRMS 0x238
153 #define RXTCP_ERR_FRMS 0x23C
154 #define RXICMP_GD_FRMS 0x240
155 #define RXICMP_ERR_FRMS 0x244
156 #define RXIPV4_GD_OCTETS 0x250
157 #define RXIPV4_HDRERR_OCTETS 0x254
158 #define RXIPV4_NOPAY_OCTETS 0x258
159 #define RXIPV4_FRAG_OCTETS 0x25C
160 #define RXIPV4_UDSBL_OCTETS 0x260
161 #define RXIPV6_GD_OCTETS 0x264
162 #define RXIPV6_HDRERR_OCTETS 0x268
163 #define RXIPV6_NOPAY_OCTETS 0x26C
164 #define RXUDP_GD_OCTETS 0x270
165 #define RXUDP_ERR_OCTETS 0x274
166 #define RXTCP_GD_OCTETS 0x278
167 #define RXTCPERROCTETS 0x27C
168 #define RXICMP_GD_OCTETS 0x280
169 #define RXICMP_ERR_OCTETS 0x284
170 #define L3_L4_CONTROL0 0x400
171 #define LAYER4_ADDRESS0 0x404
172 #define LAYER3_ADDR0_REG0 0x410
173 #define LAYER3_ADDR1_REG0 0x414
174 #define LAYER3_ADDR2_REG0 0x418
175 #define LAYER3_ADDR3_REG0 0x41C
176 #define L3_L4_CONTROL1 0x430
177 #define LAYER4_ADDRESS1 0x434
178 #define LAYER3_ADDR0_REG1 0x440
179 #define LAYER3_ADDR1_REG1 0x444
180 #define LAYER3_ADDR2_REG1 0x448
181 #define LAYER3_ADDR3_REG1 0x44C
182 #define L3_L4_CONTROL2 0x460
183 #define LAYER4_ADDRESS2 0x464
184 #define LAYER3_ADDR0_REG2 0x470
185 #define LAYER3_ADDR1_REG2 0x474
186 #define LAYER3_ADDR2_REG2 0x478
187 #define LAYER3_ADDR3_REG2 0x47C
188 #define L3_L4_CONTROL3 0x490
189 #define LAYER4_ADDRESS3 0x494
190 #define LAYER3_ADDR0_REG3 0x4A0
191 #define LAYER3_ADDR1_REG3 0x4A4
192 #define LAYER3_ADDR2_REG3 0x4A8
193 #define LAYER3_ADDR3_REG3 0x4AC
194 #define HASH_TABLE_REG(n) 0x500 + (0x4 * n)
195 #define VLAN_INCL_REG 0x584
196 #define VLAN_HASH_TABLE_REG 0x588
197 #define TIMESTAMP_CONTROL 0x700
198 #define SUB_SECOND_INCREMENT 0x704
199 #define SYSTEM_TIME_SECONDS 0x708
200 #define SYSTEM_TIME_NANOSECONDS 0x70C
201 #define SYSTEM_TIME_SECONDS_UPDATE 0x710
202 #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714
203 #define TIMESTAMP_ADDEND 0x718
204 #define TARGET_TIME_SECONDS 0x71C
205 #define TARGET_TIME_NANOSECONDS 0x720
206 #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724
207 #define TIMESTAMP_STATUS 0x728
208 #define PPS_CONTROL 0x72C
209 #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730
210 #define AUXILIARY_TIMESTAMP_SECONDS 0x734
211 #define PPS0_INTERVAL 0x760
212 #define PPS0_WIDTH 0x764
215 #define BUS_MODE 0x1000
226 #define BUS_MODE_PRIORXTX_11 0
228 #define BUS_MODE_SWR (1 << 0) /* Reset */
229 #define TRANSMIT_POLL_DEMAND 0x1004
230 #define RECEIVE_POLL_DEMAND 0x1008
231 #define RX_DESCR_LIST_ADDR 0x100C
232 #define TX_DESCR_LIST_ADDR 0x1010
233 #define DMA_STATUS 0x1014
238 #define DMA_STATUS_TI (1 << 0)
239 #define DMA_STATUS_INTR_MASK 0x1ffff
240 #define OPERATION_MODE 0x1018
246 #define MODE_RTC_LEV32 0x1
250 #define INTERRUPT_ENABLE 0x101C
265 #define INT_EN_TIE (1 << 0) /* Transmit interrupt */
270 #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020
271 #define RECEIVE_INT_WATCHDOG_TMR 0x1024
272 #define AXI_BUS_MODE 0x1028
273 #define AHB_OR_AXI_STATUS 0x102C
274 #define CURRENT_HOST_TRANSMIT_DESCR 0x1048
275 #define CURRENT_HOST_RECEIVE_DESCR 0x104C
276 #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050
277 #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054
279 #define HW_FEATURE 0x1058
282 #define DWC_GMAC_NORMAL_DESC 0x1
283 #define DWC_GMAC_EXT_DESC 0x2
285 #define GMAC_MII_CLK_60_100M_DIV42 0x0
286 #define GMAC_MII_CLK_100_150M_DIV62 0x1
287 #define GMAC_MII_CLK_25_35M_DIV16 0x2
288 #define GMAC_MII_CLK_35_60M_DIV26 0x3
289 #define GMAC_MII_CLK_150_250M_DIV102 0x4
290 #define GMAC_MII_CLK_250_300M_DIV124 0x5
291 #define GMAC_MII_CLK_DIV4 0x8
292 #define GMAC_MII_CLK_DIV6 0x9
293 #define GMAC_MII_CLK_DIV8 0xa
294 #define GMAC_MII_CLK_DIV10 0xb
295 #define GMAC_MII_CLK_DIV12 0xc
296 #define GMAC_MII_CLK_DIV14 0xd
297 #define GMAC_MII_CLK_DIV16 0xe
298 #define GMAC_MII_CLK_DIV18 0xf