Lines Matching +full:0 +full:x105
40 #define AUX_NATIVE_WRITE 0x8
41 #define AUX_NATIVE_READ 0x9
42 #define AUX_I2C_WRITE 0x0
43 #define AUX_I2C_READ 0x1
44 #define AUX_I2C_STATUS 0x2
45 #define AUX_I2C_MOT 0x4
47 #define AUX_NATIVE_REPLY_ACK (0x0 << 4)
48 #define AUX_NATIVE_REPLY_NACK (0x1 << 4)
49 #define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
50 #define AUX_NATIVE_REPLY_MASK (0x3 << 4)
52 #define AUX_I2C_REPLY_ACK (0x0 << 6)
53 #define AUX_I2C_REPLY_NACK (0x1 << 6)
54 #define AUX_I2C_REPLY_DEFER (0x2 << 6)
55 #define AUX_I2C_REPLY_MASK (0x3 << 6)
59 #define DP_DPCD_REV 0x000
61 #define DP_MAX_LINK_RATE 0x001
63 #define DP_MAX_LANE_COUNT 0x002
64 # define DP_MAX_LANE_COUNT_MASK 0x1f
68 #define DP_MAX_DOWNSPREAD 0x003
71 #define DP_NORP 0x004
73 #define DP_DOWNSTREAMPORT_PRESENT 0x005
74 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
75 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
83 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
85 #define DP_DOWN_STREAM_PORT_COUNT 0x007
86 # define DP_PORT_COUNT_MASK 0x0f
90 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
91 # define DP_I2C_SPEED_1K 0x01
92 # define DP_I2C_SPEED_5K 0x02
93 # define DP_I2C_SPEED_10K 0x04
94 # define DP_I2C_SPEED_100K 0x08
95 # define DP_I2C_SPEED_400K 0x10
96 # define DP_I2C_SPEED_1M 0x20
98 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
99 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
102 #define DP_MSTM_CAP 0x021 /* 1.2 */
103 # define DP_MST_CAP (1 << 0)
105 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
107 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
109 # define DP_PSR_SETUP_TIME_330 (0 << 1)
120 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
127 /* offset 0 */
128 #define DP_DOWNSTREAM_PORT_0 0x80
129 # define DP_DS_PORT_TYPE_MASK (7 << 0)
130 # define DP_DS_PORT_TYPE_DP 0
138 # define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
139 # define DP_DS_VGA_8BPC 0
145 #define DP_LINK_BW_SET 0x100
146 # define DP_LINK_BW_1_62 0x06
147 # define DP_LINK_BW_2_7 0x0a
148 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
150 #define DP_LANE_COUNT_SET 0x101
151 # define DP_LANE_COUNT_MASK 0x0f
154 #define DP_TRAINING_PATTERN_SET 0x102
155 # define DP_TRAINING_PATTERN_DISABLE 0
159 # define DP_TRAINING_PATTERN_MASK 0x3
161 # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
170 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
175 #define DP_TRAINING_LANE0_SET 0x103
176 #define DP_TRAINING_LANE1_SET 0x104
177 #define DP_TRAINING_LANE2_SET 0x105
178 #define DP_TRAINING_LANE3_SET 0x106
180 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
181 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
183 # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
184 # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
185 # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
186 # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
189 # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
197 #define DP_DOWNSPREAD_CTRL 0x107
201 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
202 # define DP_SET_ANSI_8B10B (1 << 0)
204 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
207 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
209 #define DP_MSTM_CTRL 0x111 /* 1.2 */
210 # define DP_MST_EN (1 << 0)
214 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
215 # define DP_PSR_ENABLE (1 << 0)
220 #define DP_SINK_COUNT 0x200
222 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
225 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
226 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
231 #define DP_LANE0_1_STATUS 0x202
232 #define DP_LANE2_3_STATUS 0x203
233 # define DP_LANE_CR_DONE (1 << 0)
241 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
243 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
247 #define DP_SINK_STATUS 0x205
249 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
252 #define DP_ADJUST_REQUEST_LANE0_1 0x206
253 #define DP_ADJUST_REQUEST_LANE2_3 0x207
254 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
255 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
256 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
258 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
260 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
263 #define DP_TEST_REQUEST 0x218
264 # define DP_TEST_LINK_TRAINING (1 << 0)
269 #define DP_TEST_LINK_RATE 0x219
270 # define DP_LINK_RATE_162 (0x6)
271 # define DP_LINK_RATE_27 (0xa)
273 #define DP_TEST_LANE_COUNT 0x220
275 #define DP_TEST_PATTERN 0x221
277 #define DP_TEST_RESPONSE 0x260
278 # define DP_TEST_ACK (1 << 0)
282 #define DP_SOURCE_OUI 0x300
283 #define DP_SINK_OUI 0x400
284 #define DP_BRANCH_OUI 0x500
286 #define DP_SET_POWER 0x600
287 # define DP_SET_POWER_D0 0x1
288 # define DP_SET_POWER_D3 0x2
290 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
291 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
294 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
295 # define DP_PSR_CAPS_CHANGE (1 << 0)
297 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
298 # define DP_PSR_SINK_INACTIVE 0
304 # define DP_PSR_SINK_STATE_MASK 0x07
335 #define DP_RECEIVER_CAP_SIZE 0xf