Lines Matching +full:0 +full:x840
44 #define DPAA2_SWP_VALID_BIT ((uint32_t) 0x80)
67 #define DPAA2_SWP_REV_4000 0x04000000
68 #define DPAA2_SWP_REV_4100 0x04010000
69 #define DPAA2_SWP_REV_4101 0x04010001
70 #define DPAA2_SWP_REV_5000 0x05000000
72 #define DPAA2_SWP_REV_MASK 0xFFFF0000
75 #define DPAA2_SWP_CINH_CR 0x600 /* Management Command reg.*/
76 #define DPAA2_SWP_CINH_EQCR_PI 0x800 /* Enqueue Ring, Producer Index */
77 #define DPAA2_SWP_CINH_EQCR_CI 0x840 /* Enqueue Ring, Consumer Index */
78 #define DPAA2_SWP_CINH_CR_RT 0x900 /* CR Read Trigger */
79 #define DPAA2_SWP_CINH_VDQCR_RT 0x940 /* VDQCR Read Trigger */
80 #define DPAA2_SWP_CINH_EQCR_AM_RT 0x980
81 #define DPAA2_SWP_CINH_RCR_AM_RT 0x9C0
82 #define DPAA2_SWP_CINH_DQPI 0xA00 /* DQRR Producer Index reg. */
83 #define DPAA2_SWP_CINH_DQRR_ITR 0xA80 /* DQRR interrupt timeout reg. */
84 #define DPAA2_SWP_CINH_DCAP 0xAC0 /* DQRR Consumption Ack. reg. */
85 #define DPAA2_SWP_CINH_SDQCR 0xB00 /* Static Dequeue Command reg. */
86 #define DPAA2_SWP_CINH_EQCR_AM_RT2 0xB40
87 #define DPAA2_SWP_CINH_RCR_PI 0xC00 /* Release Ring, Producer Index */
88 #define DPAA2_SWP_CINH_RAR 0xCC0 /* Release Array Allocation reg. */
89 #define DPAA2_SWP_CINH_CFG 0xD00
90 #define DPAA2_SWP_CINH_ISR 0xE00
91 #define DPAA2_SWP_CINH_IER 0xE40
92 #define DPAA2_SWP_CINH_ISDR 0xE80
93 #define DPAA2_SWP_CINH_IIR 0xEC0
94 #define DPAA2_SWP_CINH_ITPR 0xF40
97 #define DPAA2_SWP_CENA_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
98 #define DPAA2_SWP_CENA_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
99 #define DPAA2_SWP_CENA_RCR(n) (0x400 + ((uint32_t)(n) << 6))
100 #define DPAA2_SWP_CENA_CR (0x600) /* Management Command reg. */
101 #define DPAA2_SWP_CENA_RR(vb) (0x700 + ((uint32_t)(vb) >> 1))
102 #define DPAA2_SWP_CENA_VDQCR (0x780)
103 #define DPAA2_SWP_CENA_EQCR_CI (0x840)
106 #define DPAA2_SWP_CENA_DQRR_MEM(n) (0x0800 + ((uint32_t)(n) << 6))
107 #define DPAA2_SWP_CENA_RCR_MEM(n) (0x1400 + ((uint32_t)(n) << 6))
108 #define DPAA2_SWP_CENA_CR_MEM (0x1600) /* Management Command reg. */
109 #define DPAA2_SWP_CENA_RR_MEM (0x1680) /* Management Response reg. */
110 #define DPAA2_SWP_CENA_VDQCR_MEM (0x1780)
111 #define DPAA2_SWP_CENA_EQCR_CI_MEMBACK (0x1840)
128 #define DPAA2_SWP_CFG_EP_SHIFT 0
132 #define DPAA2_SDQCR_FC_MASK 0x1
134 #define DPAA2_SDQCR_DCT_MASK 0x3
136 #define DPAA2_SDQCR_TOK_MASK 0xff
137 #define DPAA2_SDQCR_SRC_SHIFT 0 /* Dequeue Source */
138 #define DPAA2_SDQCR_SRC_MASK 0xffff
147 #define DPAA2_SWP_RT_MODE ((uint32_t)0x100)
150 #define DPAA2_SWP_INTR_EQRI 0x01
151 #define DPAA2_SWP_INTR_EQDI 0x02
152 #define DPAA2_SWP_INTR_DQRI 0x04
153 #define DPAA2_SWP_INTR_RCRI 0x08
154 #define DPAA2_SWP_INTR_RCDI 0x10
155 #define DPAA2_SWP_INTR_VDCI 0x20
158 #define DPAA2_WQCHAN_WE_EN (0x1u) /* Enable CDAN generation */
159 #define DPAA2_WQCHAN_WE_ICD (0x2u) /* Interrupt Coalescing Disable */
160 #define DPAA2_WQCHAN_WE_CTX (0x4u)
163 #define DPAA2_DQRR_RESULT_MASK (0x7Fu)
164 #define DPAA2_DQRR_RESULT_DQ (0x60u)
165 #define DPAA2_DQRR_RESULT_FQRN (0x21u)
166 #define DPAA2_DQRR_RESULT_FQRNI (0x22u)
167 #define DPAA2_DQRR_RESULT_FQPN (0x24u)
168 #define DPAA2_DQRR_RESULT_FQDAN (0x25u)
169 #define DPAA2_DQRR_RESULT_CDAN (0x26u)
170 #define DPAA2_DQRR_RESULT_CSCN_MEM (0x27u)
171 #define DPAA2_DQRR_RESULT_CGCU (0x28u)
172 #define DPAA2_DQRR_RESULT_BPSCN (0x29u)
173 #define DPAA2_DQRR_RESULT_CSCN_WQ (0x2au)
176 #define DPAA2_DQ_STAT_FQEMPTY (0x80u) /* FQ is empty */
177 #define DPAA2_DQ_STAT_HELDACTIVE (0x40u) /* FQ is held active */
178 #define DPAA2_DQ_STAT_FORCEELIGIBLE (0x20u) /* FQ force eligible */
179 #define DPAA2_DQ_STAT_VALIDFRAME (0x10u) /* valid frame */
180 #define DPAA2_DQ_STAT_ODPVALID (0x04u) /* FQ ODP enable */
181 #define DPAA2_DQ_STAT_VOLATILE (0x02u) /* volatile dequeue (VDC) */
182 #define DPAA2_DQ_STAT_EXPIRED (0x01u) /* VDC is expired */
189 #define DPAA2_SWP_DEF 0x0u
190 #define DPAA2_SWP_NOWAIT_ALLOC 0x2u /* Do not sleep during init */
191 #define DPAA2_SWP_LOCKED 0x4000u /* Wait till portal's unlocked */
192 #define DPAA2_SWP_DESTROYED 0x8000u /* Terminate any operations */
195 #define DPAA2_SWP_STAT_OK 0x0
196 #define DPAA2_SWP_STAT_NO_MEMORY 0x9 /* No memory available */
197 #define DPAA2_SWP_STAT_PORTAL_DISABLED 0xFD /* QBMan portal disabled */
198 #define DPAA2_SWP_STAT_EINVAL 0xFE /* Invalid argument */
199 #define DPAA2_SWP_STAT_ERR 0xFF /* General error */
213 #define DPAA2_SWP_SDQCR_TOKEN 0xBBu
215 #define DPAA2_SWP_VDQCR_TOKEN 0xCCu
222 } while (0)
228 } while (0)
231 DPAA2_FD_SINGLE = 0,
454 uint32_t valid_bit; /* 0x00 or 0x80 */
464 uint32_t valid_bit; /* 0x00 or 0x80 */
468 uint32_t valid_bit; /* 0x00 or 0x80 */