Lines Matching +full:25 +full:gbase +full:- +full:cr
1 /*-
57 * XXX: Add a TUNABLE and possible per-device sysctl for this?
61 uint16_t intr_type; /* MSI, or MSI-X */
71 {0x4800, "Chelsio T440-dbg VF"},
72 {0x4801, "Chelsio T420-CR VF"},
73 {0x4802, "Chelsio T422-CR VF"},
74 {0x4803, "Chelsio T440-CR VF"},
75 {0x4804, "Chelsio T420-BCH VF"},
76 {0x4805, "Chelsio T440-BCH VF"},
77 {0x4806, "Chelsio T440-CH VF"},
78 {0x4807, "Chelsio T420-SO VF"},
79 {0x4808, "Chelsio T420-CX VF"},
80 {0x4809, "Chelsio T420-BT VF"},
81 {0x480a, "Chelsio T404-BT VF"},
82 {0x480e, "Chelsio T440-LP-CR VF"},
84 {0x5800, "Chelsio T580-dbg VF"},
85 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */
86 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */
87 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */
88 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */
89 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */
90 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */
91 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */
92 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */
93 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */
94 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */
95 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */
96 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */
97 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */
98 {0x5818, "Chelsio T540-BT VF"}, /* 4 x 10GBaseT */
99 {0x5819, "Chelsio T540-LP-BT VF"}, /* 4 x 10GBaseT */
100 {0x581a, "Chelsio T540-SO-BT VF"}, /* 4 x 10GBaseT, nomem */
101 {0x581b, "Chelsio T540-SO-CR VF"}, /* 4 x 10G, nomem */
103 {0x6800, "Chelsio T6-DBG-25 VF"}, /* 2 x 10/25G, debug */
104 {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */
105 {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */
106 {0x6803, "Chelsio T6425-CR VF"}, /* 4 x 10/25G */
107 {0x6804, "Chelsio T6425-SO-CR VF"}, /* 4 x 10/25G, nomem */
108 {0x6805, "Chelsio T6225-SO-OCP3 VF"}, /* 2 x 10/25G, nomem */
109 {0x6806, "Chelsio T6225-OCP3 VF"}, /* 2 x 10/25G */
110 {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */
111 {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */
112 {0x6809, "Chelsio T6210-BT VF"}, /* 2 x 10GBASE-T */
113 {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */
114 {0x6810, "Chelsio T6-DBG-100 VF"}, /* 2 x 40/50/100G, debug */
115 {0x6811, "Chelsio T6225-LL-CR VF"}, /* 2 x 10/25G */
116 {0x6814, "Chelsio T62100-SO-OCP3 VF"}, /* 2 x 40/50/100G, nomem */
117 {0x6815, "Chelsio T6201-BT VF"}, /* 2 x 1000BASE-T */
122 {0x6882, "Chelsio T6225-CR 82 VF"},
123 {0x6883, "Chelsio T62100-CR 83 VF"},
124 {0x6884, "Chelsio T64100-CR 84 VF"},
125 {0x6885, "Chelsio T6240-SO 85 VF"},
126 {0x6886, "Chelsio T6225-SO-CR 86 VF"},
127 {0x6887, "Chelsio T6225-CR 87 VF"},
130 {0x7800, "Chelsio T72200-DBG VF"}, /* 2 x 200G, debug */
131 {0x7801, "Chelsio T7250 VF"}, /* 2 x 10/25/50G, 1 mem */
132 {0x7802, "Chelsio S7250 VF"}, /* 2 x 10/25/50G, nomem */
133 {0x7803, "Chelsio T7450 VF"}, /* 4 x 10/25/50G, 1 mem */
134 {0x7804, "Chelsio S7450 VF"}, /* 4 x 10/25/50G, nomem */
137 {0x7807, "Chelsio T72200-FH VF"}, /* 2 x 40/100/200G, 2 mem */
139 {0x7809, "Chelsio S7210-BT VF"}, /* 2 x 10GBASE-T, nomem */
140 {0x780a, "Chelsio T7450-RC VF"}, /* 4 x 10/25/50G, 1 mem, RC */
141 {0x780b, "Chelsio T72200-RC VF"}, /* 2 x 40/100/200G, 1 mem, RC */
142 {0x780c, "Chelsio T72200-FH-RC VF"}, /* 2 x 40/100/200G, 2 mem, RC */
143 {0x780d, "Chelsio S72200-OCP3 VF"}, /* 2 x 40/100/200G OCP3 */
144 {0x780e, "Chelsio S7450-OCP3 VF"}, /* 4 x 1/20/25/50G OCP3 */
145 {0x780f, "Chelsio S7410-BT-OCP3 VF"}, /* 4 x 10GBASE-T OCP3 */
146 {0x7810, "Chelsio S7210-BT-A VF"}, /* 2 x 10GBASE-T */
240 rc = -t4vf_query_params(sc, nitems(param), param, val);
242 device_printf(sc->dev,
247 sc->params.fw_vers = val[0];
248 sc->params.tp_vers = val[1];
249 sc->params.vpd.cclk = val[2];
251 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
252 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
253 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
254 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
255 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
257 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
258 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
259 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
260 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
261 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
272 rc = -t4vf_get_sge_params(sc);
274 device_printf(sc->dev,
279 rc = -t4vf_get_rss_glb_config(sc);
281 device_printf(sc->dev,
285 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
286 device_printf(sc->dev,
288 sc->params.rss.mode);
297 rc = -t4vf_get_vfres(sc);
299 device_printf(sc->dev,
307 if (sc->params.vfres.pmask == 0) {
308 device_printf(sc->dev, "no port access configured/usable!\n");
311 if (sc->params.vfres.nvi == 0) {
312 device_printf(sc->dev,
316 sc->params.portvec = sc->params.vfres.pmask;
319 rc = -t4vf_query_params(sc, 1, ¶m, &val);
321 sc->params.max_pkts_per_eth_tx_pkts_wr = val;
323 sc->params.max_pkts_per_eth_tx_pkts_wr = 14;
347 sc->params.port_caps32 = 1;
366 vfres = &sc->params.vfres;
367 nports = sc->params.nports;
375 navail = pci_msix_count(sc->dev);
377 navail = pci_msi_count(sc->dev);
382 iaq->intr_type = itype;
386 * forwarded interrupts when using MSI (but not MSI-X).
397 iaq->nirq = T4VF_EXTRA_INTR;
404 iq_avail = vfres->niqflint - iaq->nirq;
406 device_printf(sc->dev,
408 vfres->niqflint, nports);
418 if (iaq->nirq + nports <= navail) {
419 if (iq_avail > navail - iaq->nirq)
420 iq_avail = navail - iaq->nirq;
436 if (vfres->nethctrl < nports) {
437 device_printf(sc->dev,
439 vfres->nethctrl, nports);
444 if (ntxq > vfres->nethctrl) {
448 ntxq = (vfres->nethctrl / nports) * nports;
450 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
455 if (vfres->neq < nports * 2) {
456 device_printf(sc->dev,
458 vfres->neq, nports);
461 if (nrxq + ntxq > vfres->neq) {
466 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
467 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues"));
473 iaq->nirq += nrxq;
474 iaq->ntxq = ntxq;
475 iaq->nrxq = nrxq;
476 if (iaq->nirq <= navail &&
477 (itype != INTR_MSI || powerof2(iaq->nirq))) {
478 navail = iaq->nirq;
480 rc = pci_alloc_msix(sc->dev, &navail);
482 rc = pci_alloc_msi(sc->dev, &navail);
484 device_printf(sc->dev,
486 itype, rc, iaq->nirq, navail);
489 if (navail == iaq->nirq) {
492 pci_release_msi(sc->dev);
496 iaq->nirq = 1;
497 navail = iaq->nirq;
499 rc = pci_alloc_msix(sc->dev, &navail);
501 rc = pci_alloc_msi(sc->dev, &navail);
503 device_printf(sc->dev,
505 itype, rc, iaq->nirq, navail);
509 device_printf(sc->dev,
511 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
512 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
527 sc->dev = dev;
528 sysctl_ctx_init(&sc->ctx);
531 sc->params.pci.mps = pci_get_max_payload(dev);
533 sc->flags |= IS_VF;
534 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
536 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS);
537 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL);
538 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
540 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
543 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
544 TAILQ_INIT(&sc->sfl);
545 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
547 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
553 rc = -t4vf_prep_adapter(sc);
558 if (sc->names == NULL) {
569 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
577 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
591 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux
593 * issue an FLR because of a self- deadlock on the device semaphore.
595 * cases where they're needed -- for instance, some versions of KVM
600 rc = -t4vf_fw_reset(sc);
605 sc->flags |= FW_OK;
642 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS);
649 sc->params.nports = imin(sc->params.nports,
650 bitcount32(sc->params.vfres.pmask));
660 * First pass over all the ports - allocate VIs and initialize some
663 pmask = sc->params.vfres.pmask;
669 sc->port[i] = pi;
672 pi->adapter = sc;
673 pi->port_id = i;
674 pi->nvi = 1;
675 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE,
682 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
686 free(pi->vi, M_CXGBE);
688 sc->port[i] = NULL;
694 p = ffs(pmask) - 1;
701 sc->vlan_id = t4vf_get_vf_vlan(sc);
705 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
707 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
708 sc->chan_map[pi->tx_chan] = i;
711 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
714 pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, DEVICE_UNIT_ANY);
715 if (pi->dev == NULL) {
721 pi->vi[0].dev = pi->dev;
722 device_set_softc(pi->dev, pi);
732 sc->intr_type = iaq.intr_type;
733 sc->intr_count = iaq.nirq;
735 s = &sc->sge;
736 s->nrxq = sc->params.nports * iaq.nrxq;
737 s->ntxq = sc->params.nports * iaq.ntxq;
738 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
739 s->neq += sc->params.nports; /* ctrl queues: 1 per port */
740 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
742 s->iqmap_sz = s->niq;
743 s->eqmap_sz = s->neq;
745 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
747 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
749 s->iqmap = malloc(s->iqmap_sz * sizeof(struct sge_iq *), M_CXGBE,
751 s->eqmap = malloc(s->eqmap_sz * sizeof(struct sge_eq *), M_CXGBE,
754 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
763 struct port_info *pi = sc->port[i];
770 vi->pi = pi;
771 vi->adapter = sc;
772 vi->qsize_rxq = t4_qsize_rxq;
773 vi->qsize_txq = t4_qsize_txq;
775 vi->first_rxq = rqidx;
776 vi->first_txq = tqidx;
777 vi->tmr_idx = t4_tmr_idx;
778 vi->pktc_idx = t4_pktc_idx;
779 vi->nrxq = j == 0 ? iaq.nrxq: 1;
780 vi->ntxq = j == 0 ? iaq.ntxq: 1;
782 rqidx += vi->nrxq;
783 tqidx += vi->ntxq;
785 vi->rsrv_noflowq = 0;
800 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ?
801 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq,
802 sc->sge.niq);
818 regs->version = chip_id(sc) | (0x3f << 10);
819 t4_get_regs(sc, buf, regs->len);
837 struct adapter *sc = dev->si_drv1;
847 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
850 if (edata->size == 4)
851 edata->val = t4_read_reg(sc, edata->addr);
852 else if (edata->size == 8)
853 edata->val = t4_read_reg64(sc, edata->addr);
862 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
865 if (edata->size == 4) {
866 if (edata->val & 0xffffffff00000000)
868 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
869 } else if (edata->size == 8)
870 t4_write_reg64(sc, edata->addr, edata->val);
880 if (regs->len < reglen) {
881 regs->len = reglen; /* hint to the caller */
885 regs->len = reglen;
888 rc = copyout(buf, regs->data, reglen);
898 if (port_id >= sc->params.nports)
900 pi = sc->port[port_id];
903 pi->tx_parse_error = 0;
911 if (vi->flags & VI_INIT_DONE) {
917 rxq->lro.lro_queued = 0;
918 rxq->lro.lro_flushed = 0;
920 rxq->rxcsum = 0;
921 rxq->vlan_extraction = 0;
925 txq->txcsum = 0;
926 txq->tso_wrs = 0;
927 txq->vlan_insertion = 0;
928 txq->imm_wrs = 0;
929 txq->sgl_wrs = 0;
930 txq->txpkt_wrs = 0;
931 txq->txpkts0_wrs = 0;
932 txq->txpkts1_wrs = 0;
933 txq->txpkts0_pkts = 0;
934 txq->txpkts1_pkts = 0;
935 txq->txpkts_flush = 0;
936 mp_ring_reset_stats(txq->r);