71 	{0x4800, "Chelsio T440-dbg VF"},
72 	{0x4801, "Chelsio T420-CR VF"},
73 	{0x4802, "Chelsio T422-CR VF"},
74 	{0x4803, "Chelsio T440-CR VF"},
75 	{0x4804, "Chelsio T420-BCH VF"},
76 	{0x4805, "Chelsio T440-BCH VF"},
77 	{0x4806, "Chelsio T440-CH VF"},
78 	{0x4807, "Chelsio T420-SO VF"},
79 	{0x4808, "Chelsio T420-CX VF"},
80 	{0x4809, "Chelsio T420-BT VF"},
81 	{0x480a, "Chelsio T404-BT VF"},
82 	{0x480e, "Chelsio T440-LP-CR VF"},
84 	{0x5800, "Chelsio T580-dbg VF"},
85 	{0x5801,  "Chelsio T520-CR VF"},	/* 2 x 10G */
86 	{0x5802,  "Chelsio T522-CR VF"},	/* 2 x 10G, 2 X 1G */
87 	{0x5803,  "Chelsio T540-CR VF"},	/* 4 x 10G */
88 	{0x5807,  "Chelsio T520-SO VF"},	/* 2 x 10G, nomem */
89 	{0x5809,  "Chelsio T520-BT VF"},	/* 2 x 10GBaseT */
90 	{0x580a,  "Chelsio T504-BT VF"},	/* 4 x 1G */
91 	{0x580d,  "Chelsio T580-CR VF"},	/* 2 x 40G */
92 	{0x580e,  "Chelsio T540-LP-CR VF"},	/* 4 x 10G */
93 	{0x5810,  "Chelsio T580-LP-CR VF"},	/* 2 x 40G */
94 	{0x5811,  "Chelsio T520-LL-CR VF"},	/* 2 x 10G */
95 	{0x5812,  "Chelsio T560-CR VF"},	/* 1 x 40G, 2 x 10G */
96 	{0x5814,  "Chelsio T580-LP-SO-CR VF"},	/* 2 x 40G, nomem */
97 	{0x5815,  "Chelsio T502-BT VF"},	/* 2 x 1G */
98 	{0x5818,  "Chelsio T540-BT VF"},	/* 4 x 10GBaseT */
99 	{0x5819,  "Chelsio T540-LP-BT VF"},	/* 4 x 10GBaseT */
100 	{0x581a,  "Chelsio T540-SO-BT VF"},	/* 4 x 10GBaseT, nomem */
101 	{0x581b,  "Chelsio T540-SO-CR VF"},	/* 4 x 10G, nomem */
103 	{0x6800, "Chelsio T6-DBG-25 VF"},	/* 2 x 10/25G, debug */
104 	{0x6801, "Chelsio T6225-CR VF"},	/* 2 x 10/25G */
105 	{0x6802, "Chelsio T6225-SO-CR VF"},	/* 2 x 10/25G, nomem */
106 	{0x6803, "Chelsio T6425-CR VF"},	/* 4 x 10/25G */
107 	{0x6804, "Chelsio T6425-SO-CR VF"},	/* 4 x 10/25G, nomem */
108 	{0x6805, "Chelsio T6225-SO-OCP3 VF"},	/* 2 x 10/25G, nomem */
109 	{0x6806, "Chelsio T6225-OCP3 VF"},	/* 2 x 10/25G */
110 	{0x6807, "Chelsio T62100-LP-CR VF"},	/* 2 x 40/50/100G */
111 	{0x6808, "Chelsio T62100-SO-CR VF"},	/* 2 x 40/50/100G, nomem */
112 	{0x6809, "Chelsio T6210-BT VF"},	/* 2 x 10GBASE-T */
113 	{0x680d, "Chelsio T62100-CR VF"},	/* 2 x 40/50/100G */
114 	{0x6810, "Chelsio T6-DBG-100 VF"},	/* 2 x 40/50/100G, debug */
115 	{0x6811, "Chelsio T6225-LL-CR VF"},	/* 2 x 10/25G */
116 	{0x6814, "Chelsio T62100-SO-OCP3 VF"},	/* 2 x 40/50/100G, nomem */
117 	{0x6815, "Chelsio T6201-BT VF"},	/* 2 x 1000BASE-T */
120 	{0x6880, "Chelsio T6225 80 VF"},
121 	{0x6881, "Chelsio T62100 81 VF"},
122 	{0x6882, "Chelsio T6225-CR 82 VF"},
123 	{0x6883, "Chelsio T62100-CR 83 VF"},
124 	{0x6884, "Chelsio T64100-CR 84 VF"},
125 	{0x6885, "Chelsio T6240-SO 85 VF"},
126 	{0x6886, "Chelsio T6225-SO-CR 86 VF"},
127 	{0x6887, "Chelsio T6225-CR 87 VF"},
145 	for (i = 0; i < nitems(t4vf_pciids); i++) {  in t4vf_probe()
161 	for (i = 0; i < nitems(t5vf_pciids); i++) {  in t5vf_probe()
177 	for (i = 0; i < nitems(t6vf_pciids); i++) {  in t6vf_probe()
199 	param[0] = FW_PARAM_DEV(FWREV);  in get_params__pre_init()
203 	if (rc != 0) {  in get_params__pre_init()
209 	sc->params.fw_vers = val[0];  in get_params__pre_init()
225 	return (0);  in get_params__pre_init()
235 	if (rc != 0) {  in get_params__post_init()
242 	if (rc != 0) {  in get_params__post_init()
260 	if (rc != 0) {  in get_params__post_init()
269 	if (sc->params.vfres.pmask == 0) {  in get_params__post_init()
273 	if (sc->params.vfres.nvi == 0) {  in get_params__post_init()
282 	if (rc == 0)  in get_params__post_init()
288 	if (rc != 0)  in get_params__post_init()
292 	return (0);  in get_params__post_init()
308 	if (t4vf_set_params(sc, 1, &param, &val) == 0)  in set_params__post_init()
311 	return (0);  in set_params__post_init()
332 	for (itype = INTR_MSIX; itype != 0; itype >>= 1) {  in cfg_itype_and_nqueues()
341 		if (navail == 0)  in cfg_itype_and_nqueues()
445 			if (rc != 0) {  in cfg_itype_and_nqueues()
452 				return (0);  in cfg_itype_and_nqueues()
464 		if (rc != 0)  in cfg_itype_and_nqueues()
483 	int rc = 0, i, j, rqidx, tqidx, n, p, pmask;  in t4vf_attach()
502 	mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);  in t4vf_attach()
505 	mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);  in t4vf_attach()
507 	callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);  in t4vf_attach()
509 	mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);  in t4vf_attach()
512 	if (rc != 0)  in t4vf_attach()
516 	if (rc != 0)  in t4vf_attach()
531 	memset(sc->chan_map, 0xff, sizeof(sc->chan_map));  in t4vf_attach()
540 	if (rc != 0)  in t4vf_attach()
545 	if ((cpu_feature & CPUID_CX8) == 0) {  in t4vf_attach()
563 	if (rc != 0) {  in t4vf_attach()
578 	if (rc != 0)  in t4vf_attach()
581 	if (rc != 0)  in t4vf_attach()
585 	if (rc != 0)  in t4vf_attach()
589 	if (rc != 0)  in t4vf_attach()
593 	if (rc != 0)  in t4vf_attach()
597 	if (rc != 0)  in t4vf_attach()
644 		rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);  in t4vf_attach()
645 		if (rc != 0) {  in t4vf_attach()
657 		MPASS(p >= 0);  in t4vf_attach()
659 		if (rc == 0 && n == 1)  in t4vf_attach()
669 		mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);  in t4vf_attach()
683 		pi->vi[0].dev = pi->dev;  in t4vf_attach()
691 	if (rc != 0)  in t4vf_attach()
723 	rqidx = tqidx = 0;  in t4vf_attach()
741 			vi->nrxq = j == 0 ? iaq.nrxq: 1;  in t4vf_attach()
742 			vi->ntxq = j == 0 ? iaq.ntxq: 1;  in t4vf_attach()
747 			vi->rsrv_noflowq = 0;  in t4vf_attach()
752 	if (rc != 0) {  in t4vf_attach()
767 	if (rc != 0)  in t4vf_attach()
779 	/* 0x3f is used as the revision for VFs. */  in get_regs()
780 	regs->version = chip_id(sc) | (0x3f << 10);  in get_regs()
791 		t4_write_reg(sc, VF_MPS_REG(reg), 0);  in t4_clr_vi_stats()
802 	if (rc != 0)  in t4vf_ioctl()
809 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)  in t4vf_ioctl()
824 		if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)  in t4vf_ioctl()
828 			if (edata->val & 0xffffffff00000000)  in t4vf_ioctl()
865 		pi->tx_parse_error = 0;  in t4vf_ioctl()
879 					rxq->lro.lro_queued = 0;  in t4vf_ioctl()
880 					rxq->lro.lro_flushed = 0;  in t4vf_ioctl()
882 					rxq->rxcsum = 0;  in t4vf_ioctl()
883 					rxq->vlan_extraction = 0;  in t4vf_ioctl()
887 					txq->txcsum = 0;  in t4vf_ioctl()
888 					txq->tso_wrs = 0;  in t4vf_ioctl()
889 					txq->vlan_insertion = 0;  in t4vf_ioctl()
890 					txq->imm_wrs = 0;  in t4vf_ioctl()
891 					txq->sgl_wrs = 0;  in t4vf_ioctl()
892 					txq->txpkt_wrs = 0;  in t4vf_ioctl()
893 					txq->txpkts0_wrs = 0;  in t4vf_ioctl()
894 					txq->txpkts1_wrs = 0;  in t4vf_ioctl()
895 					txq->txpkts0_pkts = 0;  in t4vf_ioctl()
896 					txq->txpkts1_pkts = 0;  in t4vf_ioctl()
897 					txq->txpkts_flush = 0;  in t4vf_ioctl()
977 DRIVER_MODULE(t4vf, pci, t4vf_driver, 0, 0);
981 DRIVER_MODULE(t5vf, pci, t5vf_driver, 0, 0);
985 DRIVER_MODULE(t6vf, pci, t6vf_driver, 0, 0);
989 DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, 0, 0);
992 DRIVER_MODULE(cxlv, t5vf, cxlv_driver, 0, 0);
995 DRIVER_MODULE(ccv, t6vf, ccv_driver, 0, 0);