Lines Matching +full:wr +full:- +full:active
1 /*-
81 * -1: no congestion feedback (not recommended).
96 * tx credits and is suitable for bursty or non-stop tx only.
134 struct adapter *sc = vi->adapter;
135 struct netmap_adapter *na = NA(vi->ifp);
139 len = vi->qsize_rxq * IQ_ESIZE;
140 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
141 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
145 len = na->num_rx_desc * EQ_ESIZE + sc->params.sge.spg_len;
146 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
147 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
151 nm_rxq->vi = vi;
152 nm_rxq->nid = idx;
153 nm_rxq->iq_cidx = 0;
154 nm_rxq->iq_sidx = vi->qsize_rxq - sc->params.sge.spg_len / IQ_ESIZE;
155 nm_rxq->iq_gen = F_RSPD_GEN;
156 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
157 nm_rxq->fl_sidx = na->num_rx_desc;
158 nm_rxq->fl_sidx2 = nm_rxq->fl_sidx; /* copy for rxsync cacheline */
159 nm_rxq->intr_idx = intr_idx;
160 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
162 ctx = &vi->ctx;
163 children = SYSCTL_CHILDREN(vi->nm_rxq_oid);
171 &nm_rxq->iq_abs_id, 0, "absolute id of the queue");
173 &nm_rxq->iq_cntxt_id, 0, "SGE context id of the queue");
175 &nm_rxq->iq_cidx, 0, "consumer index");
183 &nm_rxq->fl_cntxt_id, 0, "SGE context id of the freelist");
185 &nm_rxq->fl_cidx, 0, "consumer index");
187 &nm_rxq->fl_pidx, 0, "producer index");
195 struct adapter *sc = vi->adapter;
197 if (!(vi->flags & VI_INIT_DONE))
200 if (nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID)
202 MPASS(nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID);
204 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
205 nm_rxq->iq_desc);
206 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
207 nm_rxq->fl_desc);
217 struct port_info *pi = vi->pi;
218 struct adapter *sc = pi->adapter;
219 struct netmap_adapter *na = NA(vi->ifp);
222 struct sysctl_oid_list *children = SYSCTL_CHILDREN(vi->nm_txq_oid);
224 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
225 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
226 &nm_txq->ba, (void **)&nm_txq->desc);
230 nm_txq->pidx = nm_txq->cidx = 0;
231 nm_txq->sidx = na->num_tx_desc;
232 nm_txq->nid = idx;
233 nm_txq->iqidx = iqidx;
234 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
235 V_TXPKT_INTF(pi->hw_port) | V_TXPKT_PF(sc->pf) |
236 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
237 if (sc->params.fw_vers >= FW_VERSION32(1, 24, 11, 0))
238 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
240 nm_txq->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
241 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
244 oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name,
248 SYSCTL_ADD_UINT(&vi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
249 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
250 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
251 &nm_txq->cidx, 0, "consumer index");
252 SYSCTL_ADD_U16(&vi->ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
253 &nm_txq->pidx, 0, "producer index");
261 struct adapter *sc = vi->adapter;
263 if (!(vi->flags & VI_INIT_DONE))
266 if (nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID)
268 MPASS(nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID);
270 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
271 nm_txq->desc);
281 struct adapter *sc = vi->adapter;
282 struct port_info *pi = vi->pi;
283 struct sge_params *sp = &sc->params.sge;
284 struct netmap_adapter *na = NA(vi->ifp);
289 MPASS(nm_rxq->iq_desc != NULL);
290 MPASS(nm_rxq->fl_desc != NULL);
292 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE);
293 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len);
297 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
300 if (nm_rxq->iq_cntxt_id == INVALID_NM_RXQ_CNTXT_ID)
303 c.iqid = htobe16(nm_rxq->iq_cntxt_id);
304 c.fl0id = htobe16(nm_rxq->fl_cntxt_id);
306 c.physiqid = htobe16(nm_rxq->iq_abs_id);
309 KASSERT(nm_rxq->intr_idx < sc->intr_count,
310 ("%s: invalid direct intr_idx %d", __func__, nm_rxq->intr_idx));
311 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
314 V_FW_IQ_CMD_VIID(vi->viid) |
316 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->hw_port) |
319 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
320 c.iqsize = htobe16(vi->qsize_rxq);
321 c.iqaddr = htobe64(nm_rxq->iq_ba);
322 if (cong_drop != -1) {
324 cong_map = 1 << pi->hw_port;
326 cong_map = pi->rx_e_chan_map;
342 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
343 c.fl0addr = htobe64(nm_rxq->fl_ba);
345 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
347 device_printf(sc->dev,
352 nm_rxq->iq_cidx = 0;
353 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE);
354 nm_rxq->iq_gen = F_RSPD_GEN;
355 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
356 nm_rxq->iq_abs_id = be16toh(c.physiqid);
357 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
358 if (cntxt_id >= sc->sge.iqmap_sz) {
359 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
360 __func__, cntxt_id, sc->sge.iqmap_sz - 1);
362 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
364 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
365 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
366 nm_rxq->fl_db_saved = 0;
368 nm_rxq->fl_db_threshold = chip_id(sc) <= CHELSIO_T5 ? 8 : 4;
369 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
370 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
371 if (cntxt_id >= sc->sge.eqmap_sz) {
372 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
373 __func__, cntxt_id, sc->sge.eqmap_sz - 1);
375 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
377 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
378 sc->chip_params->sge_fl_db;
380 if (chip_id(sc) >= CHELSIO_T5 && cong_drop != -1) {
381 t4_sge_set_conm_context(sc, nm_rxq->iq_cntxt_id, cong_drop,
385 t4_write_reg(sc, sc->sge_gts_reg,
386 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
395 struct adapter *sc = vi->adapter;
398 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
399 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
401 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
402 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
403 nm_rxq->iq_cntxt_id = INVALID_NM_RXQ_CNTXT_ID;
412 struct adapter *sc = vi->adapter;
413 struct netmap_adapter *na = NA(vi->ifp);
417 MPASS(nm_txq->desc != NULL);
419 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len;
420 bzero(nm_txq->desc, len);
424 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
427 if (nm_txq->cntxt_id == INVALID_NM_TXQ_CNTXT_ID) {
428 const int core = sc->params.ncores > 1 ?
429 nm_txq->nid % sc->params.ncores : 0;
434 c.eqid_pkd = htobe32(V_FW_EQ_ETH_CMD_EQID(nm_txq->cntxt_id));
436 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
439 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->hw_port) | F_FW_EQ_ETH_CMD_FETCHRO |
440 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
446 c.eqaddr = htobe64(nm_txq->ba);
448 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
450 device_printf(vi->dev,
455 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
456 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
457 if (cntxt_id >= sc->sge.eqmap_sz)
458 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
459 cntxt_id, sc->sge.eqmap_sz - 1);
460 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
462 nm_txq->pidx = nm_txq->cidx = 0;
463 MPASS(nm_txq->sidx == na->num_tx_desc);
464 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
466 nm_txq->doorbells = sc->doorbells;
467 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
468 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
469 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
470 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
471 uint32_t mask = (1 << s_qpp) - 1;
474 udb = sc->udbs_base + UDBS_DB_OFFSET;
475 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
476 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
477 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
478 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
480 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
481 nm_txq->udb_qid = 0;
483 nm_txq->udb = (volatile void *)udb;
486 if (sc->params.fw_vers < FW_VERSION32(1, 25, 1, 0)) {
491 V_FW_PARAMS_PARAM_YZ(nm_txq->cntxt_id);
493 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
495 device_printf(vi->dev,
497 nm_txq->cntxt_id, rc);
508 struct adapter *sc = vi->adapter;
511 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
513 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
514 nm_txq->cntxt_id, rc);
515 nm_txq->cntxt_id = INVALID_NM_TXQ_CNTXT_ID;
529 * Check if there's at least one active (or about to go active) netmap
532 defq = -1;
534 nm_state = atomic_load_int(&nm_rxq->nm_state);
535 kring = na->rx_rings[nm_rxq->nid];
538 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
539 if (defq == -1) {
540 defq = nm_rxq->iq_abs_id;
546 if (defq == -1) {
547 /* No active netmap queues. Switch back to NIC queues. */
548 rss = vi->rss;
549 defq = vi->rss[0];
551 for (i = 0; i < vi->rss_size;) {
553 nm_state = atomic_load_int(&nm_rxq->nm_state);
554 kring = na->rx_rings[nm_rxq->nid];
559 MPASS(nm_rxq->iq_cntxt_id !=
561 vi->nm_rss[i++] = nm_rxq->iq_abs_id;
562 if (i == vi->rss_size)
567 rss = vi->nm_rss;
570 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
571 vi->rss_size);
575 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
585 * be dedicated for non-RSS traffic and the rest divided into two equal halves.
595 int dq[2] = {-1, -1};
599 MPASS(vi->nnmrxq > 1);
602 j = i / ((vi->nnmrxq + 1) / 2);
603 nm_state = atomic_load_int(&nm_rxq->nm_state);
604 kring = na->rx_rings[nm_rxq->nid];
607 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
609 if (dq[j] == -1) {
610 dq[j] = nm_rxq->iq_abs_id;
619 MPASS(dq[0] != -1 && dq[1] != -1);
632 nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq];
633 while (i < vi->rss_size / 2) {
634 for (j = 0; j < (vi->nnmrxq + 1) / 2; j++) {
636 kring = na->rx_rings[nm_rxq[j].nid];
646 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
647 if (i == vi->rss_size / 2)
651 while (i < vi->rss_size) {
652 for (j = (vi->nnmrxq + 1) / 2; j < vi->nnmrxq; j++) {
654 kring = na->rx_rings[nm_rxq[j].nid];
664 vi->nm_rss[i++] = nm_rxq[j].iq_abs_id;
665 if (i == vi->rss_size)
670 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size,
671 vi->nm_rss, vi->rss_size);
675 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, vi->hashen, defq, 0, 0);
687 if (nm_split_rss == 0 || vi->nnmrxq == 1)
705 MPASS(vi->nnmrxq > 0);
706 MPASS(vi->nnmtxq > 0);
708 if ((vi->flags & VI_INIT_DONE) == 0 ||
715 rxb = &sc->sge.rx_buf_info[0];
717 if (rxb->size1 == NETMAP_BUF_SIZE(na)) {
718 hwidx = rxb->hwidx1;
721 if (rxb->size2 == NETMAP_BUF_SIZE(na)) {
722 hwidx = rxb->hwidx2;
736 kring = na->rx_rings[nm_rxq->nid];
741 nm_rxq->fl_hwidx = hwidx;
746 MPASS((na->num_rx_desc & 7) == 0);
747 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
748 for (j = 0; j < nm_rxq->fl_sidx; j++) {
753 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
755 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
759 t4_write_reg(sc, sc->sge_kdoorbell_reg,
760 nm_rxq->fl_db_val | V_PIDX(j));
762 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_OFF, NM_ON);
766 kring = na->tx_rings[nm_txq->nid];
775 if (vi->nm_rss == NULL) {
776 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE,
793 MPASS(vi->nnmrxq > 0);
794 MPASS(vi->nnmtxq > 0);
799 if ((vi->flags & VI_INIT_DONE) == 0)
808 kring = na->tx_rings[nm_txq->nid];
811 MPASS(nm_txq->cntxt_id != INVALID_NM_TXQ_CNTXT_ID);
813 rc = -t4_eth_eq_stop(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
815 device_printf(vi->dev,
821 kring->rhead = kring->rcur = kring->nr_hwcur = 0;
822 kring->rtail = kring->nr_hwtail = kring->nkr_num_slots - 1;
826 nm_state = atomic_load_int(&nm_rxq->nm_state);
827 kring = na->rx_rings[nm_rxq->nid];
833 MPASS(nm_rxq->iq_cntxt_id != INVALID_NM_RXQ_CNTXT_ID);
835 rc = -t4_iq_stop(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
836 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
838 device_printf(vi->dev,
843 while (!atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_OFF))
847 kring->rhead = kring->rcur = kring->nr_hwcur = 0;
848 kring->rtail = kring->nr_hwtail = 0;
860 if_t ifp = na->ifp;
862 struct adapter *sc = vi->adapter;
877 /* How many packets can a single type1 WR carry in n descriptors */
884 return (n * 2 - 1);
889 * Space (in descriptors) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
902 * Space (in 16B units) needed for a type1 WR (TX_PKTS or TX_PKTS2) that
914 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
920 u_int db = nm_txq->doorbells;
922 MPASS(nm_txq->pidx != nm_txq->dbidx);
929 switch (ffs(db) - 1) {
931 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
942 KASSERT(nm_txq->udb_qid == 0 && n == 1,
944 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
946 dst = (volatile void *)((uintptr_t)nm_txq->udb +
947 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
948 src = (void *)&nm_txq->desc[nm_txq->dbidx];
949 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
956 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
961 t4_write_reg(sc, sc->sge_kdoorbell_reg,
962 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
965 nm_txq->dbidx = nm_txq->pidx;
976 struct netmap_ring *ring = kring->ring;
978 const u_int lim = kring->nkr_num_slots - 1;
979 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
990 wr = (void *)&nm_txq->desc[nm_txq->pidx];
991 wr->op_pkd = nm_txq->op_pkd;
992 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
993 wr->npkt = n;
994 wr->r3 = 0;
995 wr->type = 1;
996 cpl = (void *)(wr + 1);
999 slot = &ring->slot[kring->nr_hwcur];
1000 PNMB(kring->na, slot, &ba);
1003 cpl->ctrl0 = nm_txq->cpl_ctrl0;
1004 cpl->pack = 0;
1005 cpl->len = htobe16(slot->len);
1006 cpl->ctrl1 = nm_txcsum ? 0 :
1010 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
1012 usgl->len0 = htobe32(slot->len);
1013 usgl->addr0 = htobe64(ba + nm_get_offset(kring, slot));
1015 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
1017 MPASS(slot->len + len <= UINT16_MAX);
1018 len += slot->len;
1019 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
1021 wr->plen = htobe16(len);
1023 npkt -= n;
1024 nm_txq->pidx += npkt_to_ndesc(n);
1025 MPASS(nm_txq->pidx <= nm_txq->sidx);
1026 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
1032 nm_txq->pidx = 0;
1038 NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
1039 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
1041 nm_txq->equeqidx = nm_txq->pidx;
1042 nm_txq->equiqidx = nm_txq->pidx;
1044 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1045 nm_txq->equeqidx = nm_txq->pidx;
1052 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1053 nm_txq->equeqidx = nm_txq->pidx;
1068 if (nm_txq->cidx > nm_txq->pidx)
1069 return (nm_txq->cidx - nm_txq->pidx - 1);
1070 else if (nm_txq->cidx > 0)
1071 return (nm_txq->sidx - nm_txq->pidx);
1073 return (nm_txq->sidx - nm_txq->pidx - 1);
1079 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
1080 uint16_t hw_cidx = spg->cidx; /* snapshot */
1081 struct fw_eth_tx_pkts_wr *wr;
1086 while (nm_txq->cidx != hw_cidx) {
1087 wr = (void *)&nm_txq->desc[nm_txq->cidx];
1089 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)) ||
1090 wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR)));
1091 MPASS(wr->type == 1);
1092 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
1094 n += wr->npkt;
1095 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
1098 * We never sent a WR that wrapped around so the credits coming
1099 * back, WR by WR, should never cause the cidx to wrap around
1102 MPASS(nm_txq->cidx <= nm_txq->sidx);
1103 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
1104 nm_txq->cidx = 0;
1113 struct netmap_adapter *na = kring->na;
1114 if_t ifp = na->ifp;
1116 struct adapter *sc = vi->adapter;
1117 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id];
1118 const u_int head = kring->rhead;
1123 * Tx was at kring->nr_hwcur last time around and now we need to advance
1124 * to kring->rhead. Note that the driver's pidx moves independent of
1125 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
1129 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
1130 kring->nkr_num_slots - kring->nr_hwcur + head;
1152 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
1153 npkt_remaining -= n;
1157 MPASS(kring->nr_hwcur == head);
1158 MPASS(nm_txq->dbidx == nm_txq->pidx);
1165 kring->nr_hwtail += reclaimed;
1166 if (kring->nr_hwtail >= kring->nkr_num_slots)
1167 kring->nr_hwtail -= kring->nkr_num_slots;
1176 struct netmap_adapter *na = kring->na;
1177 struct netmap_ring *ring = kring->ring;
1178 if_t ifp = na->ifp;
1180 struct adapter *sc = vi->adapter;
1181 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id];
1182 u_int const head = kring->rhead;
1184 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
1190 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
1191 kring->nr_kflags &= ~NKR_PENDINTR;
1194 if (nm_rxq->fl_db_saved > 0 && starve_fl == 0) {
1196 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1197 nm_rxq->fl_db_val | V_PIDX(nm_rxq->fl_db_saved));
1198 nm_rxq->fl_db_saved = 0;
1201 /* Userspace done with buffers from kring->nr_hwcur to head */
1202 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
1203 kring->nkr_num_slots - kring->nr_hwcur + head;
1206 u_int fl_pidx = nm_rxq->fl_pidx;
1207 struct netmap_slot *slot = &ring->slot[fl_pidx];
1209 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
1219 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
1220 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx2);
1226 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
1227 slot->flags &= ~NS_BUF_CHANGED;
1228 MPASS(fl_pidx <= nm_rxq->fl_sidx2);
1230 n -= 8;
1231 if (fl_pidx == nm_rxq->fl_sidx2) {
1233 slot = &ring->slot[0];
1235 if (++dbinc == nm_rxq->fl_db_threshold) {
1238 nm_rxq->fl_db_saved += dbinc;
1240 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1241 nm_rxq->fl_db_val | V_PIDX(dbinc));
1246 MPASS(nm_rxq->fl_pidx == fl_pidx);
1251 nm_rxq->fl_db_saved += dbinc;
1253 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1254 nm_rxq->fl_db_val | V_PIDX(dbinc));
1269 MPASS(vi->nnmrxq > 0);
1270 MPASS(vi->ifp != NULL);
1272 pi = vi->pi;
1273 sc = pi->adapter;
1277 na.ifp = vi->ifp;
1281 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE;
1289 na.num_rx_desc = rounddown(vi->qsize_rxq, 8);
1293 na.num_tx_rings = vi->nnmtxq;
1294 na.num_rx_rings = vi->nnmrxq;
1295 na.rx_buf_maxsize = MAX_MTU + sc->params.sge.fl_pktshift;
1303 MPASS(vi->nnmrxq > 0);
1304 MPASS(vi->ifp != NULL);
1306 netmap_detach(vi->ifp);
1313 MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
1316 return (&cpl->data[1]);
1326 oq = be32toh(egr->opcode_qid);
1328 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1330 netmap_tx_irq(ifp, nm_txq->nid);
1336 struct vi_info *vi = nm_rxq->vi;
1337 struct adapter *sc = vi->adapter;
1338 if_t ifp = vi->ifp;
1340 struct netmap_kring *kring = na->rx_rings[nm_rxq->nid];
1341 struct netmap_ring *ring = kring->ring;
1342 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1347 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1352 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1356 lq = be32toh(d->rsp.pldbuflen_qid);
1357 opcode = d->rss.opcode;
1358 cpl = &d->cpl[0];
1360 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1383 nm_write_offset(kring, &ring->slot[fl_cidx],
1384 sc->params.sge.fl_pktshift);
1385 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
1386 sc->params.sge.fl_pktshift;
1387 ring->slot[fl_cidx].flags = 0;
1394 if (__predict_false(++fl_cidx == nm_rxq->fl_sidx))
1410 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1414 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1415 nm_rxq->iq_cidx = 0;
1416 d = &nm_rxq->iq_desc[0];
1417 nm_rxq->iq_gen ^= F_RSPD_GEN;
1421 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1422 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1429 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1430 nm_rxq->fl_sidx);
1431 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1432 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1435 t4_write_reg(sc, sc->sge_gts_reg,
1437 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1443 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1446 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1447 t4_write_reg(sc, sc->sge_kdoorbell_reg,
1448 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1450 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1452 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndesc) |
1453 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |