Lines Matching defs:cls_lo
10828 uint32_t cls_lo, cls_hi;
10848 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
10857 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
10858 G_PORTMAP(cls_hi), G_PF(cls_lo),
10859 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
10861 if (cls_lo & F_REPLICATE) {
10896 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
10897 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
10898 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
10933 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11000 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11013 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11014 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11015 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11029 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11030 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11031 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11035 if (cls_lo & F_T6_REPLICATE) {
11076 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11077 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11078 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
11113 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
11195 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
11200 cls_lo = t4_read_reg(sc, A_MPS_CLS_SRAM_L);
11214 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11215 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11216 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11230 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
11231 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
11232 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
11235 if (cls_lo & F_T6_REPLICATE) {
11276 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
11277 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
11278 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);