Lines Matching +full:0 +full:x4001

65 	{0x4000, "Chelsio T440-dbg"},
66 {0x4001, "Chelsio T420-CR"},
67 {0x4002, "Chelsio T422-CR"},
68 {0x4003, "Chelsio T440-CR"},
69 {0x4004, "Chelsio T420-BCH"},
70 {0x4005, "Chelsio T440-BCH"},
71 {0x4006, "Chelsio T440-CH"},
72 {0x4007, "Chelsio T420-SO"},
73 {0x4008, "Chelsio T420-CX"},
74 {0x4009, "Chelsio T420-BT"},
75 {0x400a, "Chelsio T404-BT"},
76 {0x400e, "Chelsio T440-LP-CR"},
78 {0x5000, "Chelsio T580-dbg"},
79 {0x5001, "Chelsio T520-CR"}, /* 2 x 10G */
80 {0x5002, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
81 {0x5003, "Chelsio T540-CR"}, /* 4 x 10G */
82 {0x5007, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
83 {0x5009, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
84 {0x500a, "Chelsio T504-BT"}, /* 4 x 1G */
85 {0x500d, "Chelsio T580-CR"}, /* 2 x 40G */
86 {0x500e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
87 {0x5010, "Chelsio T580-LP-CR"}, /* 2 x 40G */
88 {0x5011, "Chelsio T520-LL-CR"}, /* 2 x 10G */
89 {0x5012, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
90 {0x5014, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
91 {0x5015, "Chelsio T502-BT"}, /* 2 x 1G */
92 {0x5018, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
93 {0x5019, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
94 {0x501a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
95 {0x501b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
97 {0x6000, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
98 {0x6001, "Chelsio T6225-CR"}, /* 2 x 10/25G */
99 {0x6002, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
100 {0x6003, "Chelsio T6425-CR"}, /* 4 x 10/25G */
101 {0x6004, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
102 {0x6005, "Chelsio T6225-SO-OCP3"}, /* 2 x 10/25G, nomem */
103 {0x6006, "Chelsio T6225-OCP3"}, /* 2 x 10/25G */
104 {0x6007, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
105 {0x6008, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
106 {0x6009, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
107 {0x600d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
108 {0x6010, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
109 {0x6011, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
110 {0x6014, "Chelsio T62100-SO-OCP3"}, /* 2 x 40/50/100G, nomem */
111 {0x6015, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
114 {0x6080, "Chelsio T6225 80"},
115 {0x6081, "Chelsio T62100 81"},
116 {0x6082, "Chelsio T6225-CR 82"},
117 {0x6083, "Chelsio T62100-CR 83"},
118 {0x6084, "Chelsio T64100-CR 84"},
119 {0x6085, "Chelsio T6240-SO 85"},
120 {0x6086, "Chelsio T6225-SO-CR 86"},
121 {0x6087, "Chelsio T6225-CR 87"},
143 for (i = 0; i < nitems(t4iov_pciids); i++) { in t4iov_probe()
163 for (i = 0; i < nitems(t5iov_pciids); i++) { in t5iov_probe()
183 for (i = 0; i < nitems(t6iov_pciids); i++) { in t6iov_probe()
203 sc->regs_rid = PCIR_BAR(0); in t4iov_attach()
227 if (T4_IS_MAIN_READY(sc->sc_main) == 0) { in t4iov_attach()
229 if (error != 0) in t4iov_attach()
234 return (0); in t4iov_attach()
252 * with port 0, etc.). Ask the PF4 driver for the device for in t4iov_attach_child()
258 return (0); in t4iov_attach_child()
263 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); in t4iov_attach_child()
264 pci_iov_schema_add_vlan(vf_schema, "vlan", 0, 0); in t4iov_attach_child()
269 return (0); in t4iov_attach_child()
274 return (0); in t4iov_attach_child()
287 return (0); in t4iov_detach_child()
291 if (error != 0) { in t4iov_detach_child()
298 return (0); in t4iov_detach_child()
317 return (0); in t4iov_detach()
326 return (0); in t4iov_iov_init()
354 "t4vfma") != 0) in t4iov_add_vf()
357 end_synchronized_op(adap, 0); in t4iov_add_vf()
358 if (rc != 0) { in t4iov_add_vf()
362 ma[0], ma[1], ma[2], ma[3], ma[4], ma[5], rc); in t4iov_add_vf()
370 /* We can't restrict to VID 0 */ in t4iov_add_vf()
378 "t4vfvl") != 0) in t4iov_add_vf()
381 end_synchronized_op(adap, 0); in t4iov_add_vf()
382 if (rc != 0) { in t4iov_add_vf()
390 return (0); in t4iov_add_vf()
463 DRIVER_MODULE(t4iov, pci, t4iov_driver, 0, 0);
466 DRIVER_MODULE(t5iov, pci, t5iov_driver, 0, 0);
469 DRIVER_MODULE(t6iov, pci, t6iov_driver, 0, 0);