Lines Matching +full:8 +full:- +full:port
3 # Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
6 # WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
10 # This file provides the default, power-on configuration for 2-port T6-based
25 # 4. MSI-X Vectors: 1088.
26 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
34 # functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
37 # 8. Some customers will want to support large CPU count systems with
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
40 # to be involved per port and per application function. For example,
43 # to 8 CPUs, we would want:
46 # 3 application functions (NIC, FCoE, iSCSI) per port *
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
52 # 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
53 # Machines to directly access T6 functionality via SR-IOV Virtual Functions
54 # and "PCI Device Passthrough" -- this is especially true for the NIC
125 # protocol, tos, vlan, vnic_id, port, fcoe
128 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
169 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
175 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
198 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC, 2: enable BRBC
204 #enable bottleneck-bw congestion control mode
208 # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
209 # per function per port ...
211 # NMSIX = 1088 # available MSI-X Vectors
217 # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
222 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
226 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
234 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
241 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
248 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
259 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
266 # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
285 # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
296 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
301 # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
307 # associated with it. Thus, the MSI-X Vector allocations we give to the
310 # one of PF0-3.
313 # All of the below PCI-E parameters are actually stored in various *_init.txt
316 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
317 # ports 0-3.
319 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
321 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
324 # Additionally, since the UnifiedPF isn't one of the per-port Physical
325 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
326 # different PCI Device IDs which will allow Unified and Per-Port Drivers
330 # Note that the actual values used for the PCI-E Intelectual Property will be
334 # PF0_INT = 8 # NCPUS
335 # PF1_INT = 8 # NCPUS
346 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
353 # only enough resources to support a single port's NIC application functions
354 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
355 # Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
362 nvi = 1 # 1 port
363 niqflint = 8 # NCPUS "Queue Sets"
364 nethctrl = 8 # NCPUS "Queue Sets"
366 nexactf = 8 # number of exact MPSTCAM MAC filters
368 pmask = 0x1 # access to only one port
375 nvi = 1 # 1 port
376 niqflint = 8 # NCPUS "Queue Sets"
377 nethctrl = 8 # NCPUS "Queue Sets"
379 nexactf = 8 # number of exact MPSTCAM MAC filters
381 pmask = 0x2 # access to only one port
387 nvi = 1 # 1 port
388 niqflint = 8 # NCPUS "Queue Sets"
389 nethctrl = 8 # NCPUS "Queue Sets"
391 nexactf = 8 # number of exact MPSTCAM MAC filters
393 pmask = 0x4 # access to only one port
399 nvi = 1 # 1 port
400 niqflint = 8 # NCPUS "Queue Sets"
401 nethctrl = 8 # NCPUS "Queue Sets"
403 nexactf = 8 # number of exact MPSTCAM MAC filters
405 pmask = 0x8 # access to only one port
501 nexactf = 8 # NPORTS + DCBX +
506 # access to one port (1 << PF). Note that because of limitations in the
513 r_caps = 0x86 # DMAQ | VF | PORT
514 nvi = 1 # 1 port
517 neq = 8 # 2 "Queue Sets" * 2
520 pmask = 0x1 # access to only one port ...
525 r_caps = 0x86 # DMAQ | VF | PORT
526 nvi = 1 # 1 port
529 neq = 8 # 2 "Queue Sets" * 2
532 pmask = 0x2 # access to only one port ...
536 r_caps = 0x86 # DMAQ | VF | PORT
537 nvi = 1 # 1 port
540 neq = 8 # 2 "Queue Sets" * 2
543 pmask = 0x1 # access to only one port ...
548 r_caps = 0x86 # DMAQ | VF | PORT
549 nvi = 1 # 1 port
552 neq = 8 # 2 "Queue Sets" * 2
555 pmask = 0x2 # access to only one port ...
562 # bg_mem: %-age of mem to use for port/buffer group
563 # lpbk_mem: %-age of port/bg mem to use for loopback
571 [port "0"]
582 [port "1"]
602 # MSI-X Vectors: 736