Lines Matching full:ingress
23 # 2. Ingress Queues with Free Lists: 1024.
27 # address matching on Ingress Packets.
39 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
47 # 16 Ingress Queue/MSI-X Vectors per application function
49 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
77 # round them up to the Ingress Padding Boundary.
199 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
200 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
201 # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
202 # will be specified as the "Ingress Queue Asynchronous Destination Index."
204 # than or equal to the number of Ingress Queues ...
207 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
214 # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
221 # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
229 # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
232 # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
239 # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
245 # Two extra Ingress Queues per function for Firmware Events and Forwarded
249 # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
254 # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
258 # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
293 # For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
413 # and GTS registers, the number of Ingress and Egress Queues must be a power
440 # MPS features a 196608 bytes ingress buffer that is used for ingress buffering
480 # Ingress Queues/w Free Lists and Interrupts: 526