Lines Matching full:ingress
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
23 # must use a power of 2 Ingress Queues.
35 # address matching on Ingress Packets.
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
98 # round them up to the Ingress Padding Boundary.
187 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
188 # use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
189 # would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
190 # will be specified as the "Ingress Queue Asynchronous Destination Index."
192 # than or equal to the number of Ingress Queues ...
195 # NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
202 # NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
209 # NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
217 # NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
220 # NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
227 # NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
233 # Two extra Ingress Queues per function for Firmware Events and Forwarded
237 # NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
242 # Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
246 # NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
281 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
393 # and GTS registers, the number of Ingress and Egress Queues must be a power
418 # MPS features a 196608 bytes ingress buffer that is used for ingress buffering
470 # Ingress Queues/w Free Lists and Interrupts: 526