Lines Matching +full:8 +full:- +full:port
3 # Copyright (C) 2010-2017 Chelsio Communications. All rights reserved.
6 # THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
9 # This file provides the default, power-on configuration for 4-port T4-based
22 # 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions
24 # 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a
26 # 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV
28 # same umber of MSI-X Vectors as the base Physical Function.
30 # not, their MSI-X "needs" are counted by the PCI-E implementation.
32 # Functions (PF0-3) must have the same number of configured TotalVFs in
33 # their SR-IOV Capabilities.
34 # 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
41 # to allow for this. And because of the MSI-X resource allocation
44 # or we'll need to move the Unified PF into the PF4-7 range since those
49 # functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc.
52 # 8. Some customers will want to support large CPU count systems with
54 # Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
55 # to be involved per port and per application function. For example,
58 # to 8 CPUs, we would want:
61 # 3 application functions (NIC, FCoE, iSCSI) per port *
62 # 8 Ingress Queue/MSI-X Vectors per application function
64 # for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
67 # 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow
68 # Virtual Machines to directly access T4 functionality via SR-IOV
69 # Virtual Functions and "PCI Device Passthrough" -- this is especially
122 # protocol, tos, vlan, vnic_id, port, fcoe
124 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
153 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K
156 # 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
157 # per function per port ...
159 # NMSIX = 1088 # available MSI-X Vectors
164 # NCPUS = 8 # CPUs we want to support scalably
165 # NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
170 # Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
174 # Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
182 # NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
189 # NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
196 # NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
207 # NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
214 # NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
233 # NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
244 # The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
249 # The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
255 # associated with it. Thus, the MSI-X Vector allocations we give to the
258 # one of PF0-3.
261 # All of the below PCI-E parameters are actually stored in various *_init.txt
264 # For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
265 # ports 0-3.
267 # For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
269 # For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
272 # Additionally, since the UnifiedPF isn't one of the per-port Physical
273 # Functions, we give the UnifiedPF and the PF0-3 Physical Functions
274 # different PCI Device IDs which will allow Unified and Per-Port Drivers
278 # Note that the actual values used for the PCI-E Intelectual Property will be
282 # PF0_INT = 8 # NCPUS
283 # PF1_INT = 8 # NCPUS
284 # PF2_INT = 8 # NCPUS
285 # PF3_INT = 8 # NCPUS
296 # With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
302 # only enough resources to support a single port's NIC application functions
303 # on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
304 # Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
311 nvi = 1 # 1 port
312 niqflint = 8 # NCPUS "Queue Sets"
313 nethctrl = 8 # NCPUS "Queue Sets"
315 nexactf = 8 # number of exact MPSTCAM MAC filters
317 pmask = 0x1 # access to only one port
323 nvi = 1 # 1 port
324 niqflint = 8 # NCPUS "Queue Sets"
325 nethctrl = 8 # NCPUS "Queue Sets"
327 nexactf = 8 # number of exact MPSTCAM MAC filters
329 pmask = 0x2 # access to only one port
335 nvi = 1 # 1 port
336 niqflint = 8 # NCPUS "Queue Sets"
337 nethctrl = 8 # NCPUS "Queue Sets"
339 nexactf = 8 # number of exact MPSTCAM MAC filters
341 pmask = 0x4 # access to only one port
347 nvi = 1 # 1 port
348 niqflint = 8 # NCPUS "Queue Sets"
349 nethctrl = 8 # NCPUS "Queue Sets"
351 nexactf = 8 # number of exact MPSTCAM MAC filters
353 pmask = 0x8 # access to only one port
439 nexactf = 8 # NPORTS + DCBX +
443 # access to one port (1 << PF). Note that because of limitations in the
450 r_caps = 0x86 # DMAQ | VF | PORT
451 nvi = 1 # 1 port
457 pmask = 0x1 # access to only one port ...
461 r_caps = 0x86 # DMAQ | VF | PORT
462 nvi = 1 # 1 port
468 pmask = 0x2 # access to only one port ...
472 r_caps = 0x86 # DMAQ | VF | PORT
473 nvi = 1 # 1 port
479 pmask = 0x4 # access to only one port ...
483 r_caps = 0x86 # DMAQ | VF | PORT
484 nvi = 1 # 1 port
490 pmask = 0x8 # access to only one port ...
497 # bg_mem: %-age of mem to use for port/buffer group
498 # lpbk_mem: %-age of port/bg mem to use for loopback
508 [port "0"]
519 [port "1"]
530 [port "2"]
541 [port "3"]
561 # MSI-X Vectors: 736