Lines Matching +full:1 +full:x

9  * 1. Redistributions of source code must retain the above copyright
114 #define NUM_PCIE_HMA_INSTANCES 1
120 #define NUM_PCIE_MAILBOX_INSTANCES 1
307 #define NUM_PCIE_T5_HMA_INSTANCES 1
388 #define NUM_PCIE_T6_CMD_INSTANCES 1
521 #define NUM_PCIE_T7_CMD_INSTANCES 1
524 #define NUM_PCIE_T5_ARM_INSTANCES 1
674 #define V_QID(x) ((x) << S_QID)
675 #define G_QID(x) (((x) >> S_QID) & M_QID)
678 #define V_DBPRIO(x) ((x) << S_DBPRIO)
679 #define F_DBPRIO    V_DBPRIO(1U)
683 #define V_PIDX(x) ((x) << S_PIDX)
684 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
689 #define V_DBTYPE(x) ((x) << S_DBTYPE)
690 #define F_DBTYPE    V_DBTYPE(1U)
694 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
695 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
698 #define V_SYNC_T6(x) ((x) << S_SYNC_T6)
699 #define F_SYNC_T6    V_SYNC_T6(1U)
705 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
706 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
710 #define V_TIMERREG(x) ((x) << S_TIMERREG)
711 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
714 #define V_SEINTARM(x) ((x) << S_SEINTARM)
715 #define F_SEINTARM    V_SEINTARM(1U)
719 #define V_CIDXINC(x) ((x) << S_CIDXINC)
720 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
729 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
730 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
736 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
737 #define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
741 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
742 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
746 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
747 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
750 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
751 #define F_DCASYSTYPE    V_DCASYSTYPE(1U)
754 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
755 #define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
758 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
759 #define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
762 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
763 #define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
766 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
767 #define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
770 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
771 #define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
775 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
776 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
780 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
781 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
785 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
786 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
788 #define S_EGRPCIEBOUNDARY    1
790 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
791 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
794 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
795 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
799 #define V_NUMOFFID(x) ((x) << S_NUMOFFID)
800 #define G_NUMOFFID(x) (((x) >> S_NUMOFFID) & M_NUMOFFID)
803 #define V_INGHINTENABLE2(x) ((x) << S_INGHINTENABLE2)
804 #define F_INGHINTENABLE2    V_INGHINTENABLE2(1U)
807 #define V_INGHINTENABLE3(x) ((x) << S_INGHINTENABLE3)
808 #define F_INGHINTENABLE3    V_INGHINTENABLE3(1U)
810 #define S_TF_MODE    1
812 #define V_TF_MODE(x) ((x) << S_TF_MODE)
813 #define G_TF_MODE(x) (((x) >> S_TF_MODE) & M_TF_MODE)
819 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
820 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
824 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
825 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
829 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
830 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
834 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
835 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
839 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
840 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
844 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
845 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
849 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
850 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
854 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
855 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
861 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
862 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
866 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
867 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
871 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
872 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
876 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
877 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
881 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
882 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
886 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
887 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
891 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
892 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
896 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
897 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
903 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
904 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
908 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
909 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
913 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
914 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
918 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
919 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
923 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
924 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
928 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
929 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
933 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
934 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
938 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
939 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
945 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
946 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
950 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
951 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
955 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
956 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
960 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
961 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
967 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
968 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
972 #define V_WR_SENDPATH_ERROR_OPCODE(x) ((x) << S_WR_SENDPATH_ERROR_OPCODE)
973 #define G_WR_SENDPATH_ERROR_OPCODE(x) (((x) >> S_WR_SENDPATH_ERROR_OPCODE) & M_WR_SENDPATH_ERROR_OPCODE)
977 #define V_WR_SENDPATH_OPCODE(x) ((x) << S_WR_SENDPATH_OPCODE)
978 #define G_WR_SENDPATH_OPCODE(x) (((x) >> S_WR_SENDPATH_OPCODE) & M_WR_SENDPATH_OPCODE)
982 #define S_MEMSEL    1
984 #define V_MEMSEL(x) ((x) << S_MEMSEL)
985 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
988 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
989 #define F_INJECTDATAERR    V_INJECTDATAERR(1U)
994 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
995 #define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
998 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
999 #define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
1002 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
1003 #define F_PERR_MC_PC    V_PERR_MC_PC(1U)
1006 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
1007 #define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
1010 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
1011 #define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
1014 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
1015 #define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
1018 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
1019 #define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
1022 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
1023 #define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
1026 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
1027 #define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
1030 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
1031 #define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
1034 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
1035 #define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
1038 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
1039 #define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
1042 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
1043 #define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
1046 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
1047 #define F_PERR_DMARBT    V_PERR_DMARBT(1U)
1050 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
1051 #define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
1054 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
1055 #define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
1058 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
1059 #define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
1062 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
1063 #define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
1066 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
1067 #define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
1070 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
1071 #define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
1074 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
1075 #define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
1078 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
1079 #define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
1082 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
1083 #define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
1086 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
1087 #define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
1090 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
1091 #define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
1094 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
1095 #define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
1098 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
1099 #define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
1102 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
1103 #define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
1106 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
1107 #define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
1109 #define S_PERR_ING_CTXT_MIFRSP    1
1110 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
1111 #define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
1114 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
1115 #define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
1118 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
1119 #define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
1122 #define V_PERR_PC_RSP(x) ((x) << S_PERR_PC_RSP)
1123 #define F_PERR_PC_RSP    V_PERR_PC_RSP(1U)
1126 #define V_PERR_PC_REQ(x) ((x) << S_PERR_PC_REQ)
1127 #define F_PERR_PC_REQ    V_PERR_PC_REQ(1U)
1130 #define V_PERR_HEADERSPLIT_FIFO3(x) ((x) << S_PERR_HEADERSPLIT_FIFO3)
1131 #define F_PERR_HEADERSPLIT_FIFO3    V_PERR_HEADERSPLIT_FIFO3(1U)
1134 #define V_PERR_HEADERSPLIT_FIFO2(x) ((x) << S_PERR_HEADERSPLIT_FIFO2)
1135 #define F_PERR_HEADERSPLIT_FIFO2    V_PERR_HEADERSPLIT_FIFO2(1U)
1138 #define V_PERR_PAYLOAD_FIFO3(x) ((x) << S_PERR_PAYLOAD_FIFO3)
1139 #define F_PERR_PAYLOAD_FIFO3    V_PERR_PAYLOAD_FIFO3(1U)
1142 #define V_PERR_PAYLOAD_FIFO2(x) ((x) << S_PERR_PAYLOAD_FIFO2)
1143 #define F_PERR_PAYLOAD_FIFO2    V_PERR_PAYLOAD_FIFO2(1U)
1150 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
1151 #define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
1154 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
1155 #define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
1158 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
1159 #define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
1162 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
1163 #define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
1166 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
1167 #define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
1170 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
1171 #define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
1174 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
1175 #define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
1178 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
1179 #define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
1182 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
1183 #define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
1186 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
1187 #define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
1190 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
1191 #define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
1194 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
1195 #define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
1198 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
1199 #define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
1202 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
1203 #define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
1206 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
1207 #define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
1210 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
1211 #define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
1214 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
1215 #define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
1218 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
1219 #define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
1222 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
1223 #define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
1226 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
1227 #define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
1230 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
1231 #define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
1234 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
1235 #define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
1238 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
1239 #define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
1242 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
1243 #define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
1246 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
1247 #define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
1250 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
1251 #define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
1254 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
1255 #define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
1258 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
1259 #define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
1262 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
1263 #define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
1265 #define S_PERR_EGR_CTXT_CACHE    1
1266 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
1267 #define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
1270 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
1271 #define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
1274 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
1275 #define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
1278 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
1279 #define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
1282 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
1283 #define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
1286 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
1287 #define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
1290 #define V_DEQ_LL_PERR(x) ((x) << S_DEQ_LL_PERR)
1291 #define F_DEQ_LL_PERR    V_DEQ_LL_PERR(1U)
1294 #define V_ENQ_PERR(x) ((x) << S_ENQ_PERR)
1295 #define F_ENQ_PERR    V_ENQ_PERR(1U)
1298 #define V_DEQ_OUT_PERR(x) ((x) << S_DEQ_OUT_PERR)
1299 #define F_DEQ_OUT_PERR    V_DEQ_OUT_PERR(1U)
1302 #define V_BUF_PERR(x) ((x) << S_BUF_PERR)
1303 #define F_BUF_PERR    V_BUF_PERR(1U)
1306 #define V_PERR_DB_FIFO(x) ((x) << S_PERR_DB_FIFO)
1307 #define F_PERR_DB_FIFO    V_PERR_DB_FIFO(1U)
1310 #define V_TF_FIFO_PERR(x) ((x) << S_TF_FIFO_PERR)
1311 #define F_TF_FIFO_PERR    V_TF_FIFO_PERR(1U)
1314 #define V_PERR_ISW_IDMA3_FIFO(x) ((x) << S_PERR_ISW_IDMA3_FIFO)
1315 #define F_PERR_ISW_IDMA3_FIFO    V_PERR_ISW_IDMA3_FIFO(1U)
1318 #define V_PERR_ISW_IDMA2_FIFO(x) ((x) << S_PERR_ISW_IDMA2_FIFO)
1319 #define F_PERR_ISW_IDMA2_FIFO    V_PERR_ISW_IDMA2_FIFO(1U)
1322 #define V_SGE_IPP_FIFO_PERR(x) ((x) << S_SGE_IPP_FIFO_PERR)
1323 #define F_SGE_IPP_FIFO_PERR    V_SGE_IPP_FIFO_PERR(1U)
1330 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
1331 #define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
1334 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
1335 #define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
1338 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
1339 #define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
1342 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
1343 #define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
1346 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
1347 #define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
1350 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
1351 #define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
1354 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
1355 #define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
1358 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
1359 #define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
1362 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
1363 #define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
1366 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
1367 #define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
1370 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
1371 #define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
1374 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
1375 #define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
1378 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
1379 #define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
1382 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
1383 #define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
1386 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1387 #define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1390 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1391 #define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1394 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1395 #define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
1398 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1399 #define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
1402 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1403 #define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
1406 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1407 #define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
1410 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1411 #define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
1414 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1415 #define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
1418 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1419 #define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
1422 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1423 #define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
1426 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1427 #define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
1430 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1431 #define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
1434 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1435 #define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
1438 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1439 #define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
1442 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1443 #define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
1446 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1447 #define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
1449 #define S_ERR_INV_CTXT1    1
1450 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1451 #define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
1454 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1455 #define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
1458 #define V_DBP_TBUF_FULL(x) ((x) << S_DBP_TBUF_FULL)
1459 #define F_DBP_TBUF_FULL    V_DBP_TBUF_FULL(1U)
1462 #define V_FATAL_WRE_LEN(x) ((x) << S_FATAL_WRE_LEN)
1463 #define F_FATAL_WRE_LEN    V_FATAL_WRE_LEN(1U)
1470 #define V_SIZE(x) ((x) << S_SIZE)
1471 #define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE)
1475 #define V_T6_SIZE(x) ((x) << S_T6_SIZE)
1476 #define G_T6_SIZE(x) (((x) >> S_T6_SIZE) & M_T6_SIZE)
1497 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1498 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1506 #define V_OPMODE(x) ((x) << S_OPMODE)
1507 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1510 #define V_NOHDR(x) ((x) << S_NOHDR)
1511 #define F_NOHDR    V_NOHDR(1U)
1515 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1516 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1520 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1521 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1525 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1526 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1530 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1531 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1535 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1536 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1539 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1540 #define F_NOEDRAM    V_NOEDRAM(1U)
1544 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1545 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1549 #define V_NULLPTR(x) ((x) << S_NULLPTR)
1550 #define G_NULLPTR(x) (((x) >> S_NULLPTR) & M_NULLPTR)
1553 #define V_NULLPTREN(x) ((x) << S_NULLPTREN)
1554 #define F_NULLPTREN    V_NULLPTREN(1U)
1556 #define S_HDRSTARTFLQ4K    1
1557 #define V_HDRSTARTFLQ4K(x) ((x) << S_HDRSTARTFLQ4K)
1558 #define F_HDRSTARTFLQ4K    V_HDRSTARTFLQ4K(1U)
1564 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1565 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1569 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1570 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1572 #define S_MPS_ENABLE    1
1573 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1574 #define F_MPS_ENABLE    V_MPS_ENABLE(1U)
1577 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1578 #define F_TP_ENABLE    V_TP_ENABLE(1U)
1582 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1583 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1587 #define V_T6_EGRTHRESHOLDPACKING(x) ((x) << S_T6_EGRTHRESHOLDPACKING)
1588 #define G_T6_EGRTHRESHOLDPACKING(x) (((x) >> S_T6_EGRTHRESHOLDPACKING) & M_T6_EGRTHRESHOLDPACKING)
1592 #define V_T6_EGRTHRESHOLD(x) ((x) << S_T6_EGRTHRESHOLD)
1593 #define G_T6_EGRTHRESHOLD(x) (((x) >> S_T6_EGRTHRESHOLD) & M_T6_EGRTHRESHOLD)
1600 #define V_TSOP(x) ((x) << S_TSOP)
1601 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1605 #define V_TSVAL(x) ((x) << S_TSVAL)
1606 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1612 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1613 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1617 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1618 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1622 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1623 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1627 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1628 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1634 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1635 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1639 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1640 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1644 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1645 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1649 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1650 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1653 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1654 #define F_BAR2VALID    V_BAR2VALID(1U)
1657 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1658 #define F_BAR2FULL    V_BAR2FULL(1U)
1662 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1663 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1667 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1668 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1672 #define V_VFIFO_CNT(x) ((x) << S_VFIFO_CNT)
1673 #define G_VFIFO_CNT(x) (((x) >> S_VFIFO_CNT) & M_VFIFO_CNT)
1677 #define V_COAL_CTL_FIFO_CNT(x) ((x) << S_COAL_CTL_FIFO_CNT)
1678 #define G_COAL_CTL_FIFO_CNT(x) (((x) >> S_COAL_CTL_FIFO_CNT) & M_COAL_CTL_FIFO_CNT)
1682 #define V_MERGE_FIFO_CNT(x) ((x) << S_MERGE_FIFO_CNT)
1683 #define G_MERGE_FIFO_CNT(x) (((x) >> S_MERGE_FIFO_CNT) & M_MERGE_FIFO_CNT)
1689 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1690 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1693 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1694 #define F_NOCOALESCE    V_NOCOALESCE(1U)
1698 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1699 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1702 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1703 #define F_HP_DISABLE    V_HP_DISABLE(1U)
1706 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1707 #define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
1710 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1711 #define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
1714 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1715 #define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
1718 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1719 #define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
1722 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1723 #define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
1726 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1727 #define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
1730 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1731 #define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
1734 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1735 #define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
1738 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1739 #define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
1742 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1743 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
1745 #define S_DROP_TIMEOUT    1
1747 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1748 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1751 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1752 #define F_DROPPED_DB    V_DROPPED_DB(1U)
1756 #define V_T6_DROP_TIMEOUT(x) ((x) << S_T6_DROP_TIMEOUT)
1757 #define G_T6_DROP_TIMEOUT(x) (((x) >> S_T6_DROP_TIMEOUT) & M_T6_DROP_TIMEOUT)
1760 #define V_INVONDBSYNC(x) ((x) << S_INVONDBSYNC)
1761 #define F_INVONDBSYNC    V_INVONDBSYNC(1U)
1764 #define V_INVONGTSSYNC(x) ((x) << S_INVONGTSSYNC)
1765 #define F_INVONGTSSYNC    V_INVONGTSSYNC(1U)
1768 #define V_DB_DBG_EN(x) ((x) << S_DB_DBG_EN)
1769 #define F_DB_DBG_EN    V_DB_DBG_EN(1U)
1771 #define S_GTS_DBG_TIMER_REG    1
1773 #define V_GTS_DBG_TIMER_REG(x) ((x) << S_GTS_DBG_TIMER_REG)
1774 #define G_GTS_DBG_TIMER_REG(x) (((x) >> S_GTS_DBG_TIMER_REG) & M_GTS_DBG_TIMER_REG)
1777 #define V_GTS_DBG_EN(x) ((x) << S_GTS_DBG_EN)
1778 #define F_GTS_DBG_EN    V_GTS_DBG_EN(1U)
1783 #define S_THROTTLE_COUNT    1
1785 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1786 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1789 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1790 #define F_THROTTLE_ENABLE    V_THROTTLE_ENABLE(1U)
1794 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1795 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1798 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1799 #define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
1802 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1803 #define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
1806 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1807 #define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
1813 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1814 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1818 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1819 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1822 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1823 #define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
1827 #define V_TSCALE(x) ((x) << S_TSCALE)
1828 #define G_TSCALE(x) (((x) >> S_TSCALE) & M_TSCALE)
1834 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1835 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1839 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1840 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1846 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1847 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1851 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1852 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1858 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1859 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1863 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1864 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1869 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1870 #define F_RSPCREDITEN0    V_RSPCREDITEN0(1U)
1874 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1875 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1879 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1880 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1883 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1884 #define F_RSPCREDITEN1    V_RSPCREDITEN1(1U)
1888 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1889 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1893 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1894 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1899 #define V_EN_FLM_FIFTH(x) ((x) << S_EN_FLM_FIFTH)
1900 #define F_EN_FLM_FIFTH    V_EN_FLM_FIFTH(1U)
1904 #define V_FL_PROG_THRESH(x) ((x) << S_FL_PROG_THRESH)
1905 #define G_FL_PROG_THRESH(x) (((x) >> S_FL_PROG_THRESH) & M_FL_PROG_THRESH)
1908 #define V_COAL_ALL_THREAD(x) ((x) << S_COAL_ALL_THREAD)
1909 #define F_COAL_ALL_THREAD    V_COAL_ALL_THREAD(1U)
1912 #define V_EN_PSHB(x) ((x) << S_EN_PSHB)
1913 #define F_EN_PSHB    V_EN_PSHB(1U)
1916 #define V_EN_DB_FIFTH(x) ((x) << S_EN_DB_FIFTH)
1917 #define F_EN_DB_FIFTH    V_EN_DB_FIFTH(1U)
1921 #define V_DB_PROG_THRESH(x) ((x) << S_DB_PROG_THRESH)
1922 #define G_DB_PROG_THRESH(x) (((x) >> S_DB_PROG_THRESH) & M_DB_PROG_THRESH)
1926 #define V_100NS_TIMER(x) ((x) << S_100NS_TIMER)
1927 #define G_100NS_TIMER(x) (((x) >> S_100NS_TIMER) & M_100NS_TIMER)
1932 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1933 #define F_RSPCREDITEN2    V_RSPCREDITEN2(1U)
1937 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1938 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1942 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1943 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1946 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1947 #define F_RSPCREDITEN3    V_RSPCREDITEN3(1U)
1951 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1952 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1956 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1957 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1963 #define V_DBQ_TIMER_TICK(x) ((x) << S_DBQ_TIMER_TICK)
1964 #define G_DBQ_TIMER_TICK(x) (((x) >> S_DBQ_TIMER_TICK) & M_DBQ_TIMER_TICK)
1968 #define V_FL_MERGE_CNT_THRESH(x) ((x) << S_FL_MERGE_CNT_THRESH)
1969 #define G_FL_MERGE_CNT_THRESH(x) (((x) >> S_FL_MERGE_CNT_THRESH) & M_FL_MERGE_CNT_THRESH)
1973 #define V_MERGE_CNT_THRESH(x) ((x) << S_MERGE_CNT_THRESH)
1974 #define G_MERGE_CNT_THRESH(x) (((x) >> S_MERGE_CNT_THRESH) & M_MERGE_CNT_THRESH)
1983 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1984 #define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1987 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1988 #define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1991 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1992 #define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1995 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1996 #define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1999 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
2000 #define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
2003 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
2004 #define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
2007 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
2008 #define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
2010 #define S_ERR_FLM_INVALID_PKT_DROP0    1
2011 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
2012 #define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
2015 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
2016 #define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
2019 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
2020 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
2023 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
2024 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
2027 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
2028 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
2031 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
2032 #define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
2035 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
2036 #define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
2039 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
2040 #define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
2043 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
2044 #define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
2047 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
2048 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
2051 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
2052 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
2055 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
2056 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
2059 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
2060 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
2063 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
2064 #define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
2067 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
2068 #define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
2071 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
2072 #define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
2075 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
2076 #define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
2079 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
2080 #define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
2083 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
2084 #define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
2087 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
2088 #define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
2091 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
2092 #define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
2095 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
2096 #define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
2099 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
2100 #define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
2103 #define V_ERR_ISHIFT_UR1(x) ((x) << S_ERR_ISHIFT_UR1)
2104 #define F_ERR_ISHIFT_UR1    V_ERR_ISHIFT_UR1(1U)
2107 #define V_ERR_ISHIFT_UR0(x) ((x) << S_ERR_ISHIFT_UR0)
2108 #define F_ERR_ISHIFT_UR0    V_ERR_ISHIFT_UR0(1U)
2111 #define V_ERR_TH3_MAX_FETCH(x) ((x) << S_ERR_TH3_MAX_FETCH)
2112 #define F_ERR_TH3_MAX_FETCH    V_ERR_TH3_MAX_FETCH(1U)
2115 #define V_ERR_TH2_MAX_FETCH(x) ((x) << S_ERR_TH2_MAX_FETCH)
2116 #define F_ERR_TH2_MAX_FETCH    V_ERR_TH2_MAX_FETCH(1U)
2119 #define V_ERR_TH1_MAX_FETCH(x) ((x) << S_ERR_TH1_MAX_FETCH)
2120 #define F_ERR_TH1_MAX_FETCH    V_ERR_TH1_MAX_FETCH(1U)
2123 #define V_ERR_TH0_MAX_FETCH(x) ((x) << S_ERR_TH0_MAX_FETCH)
2124 #define F_ERR_TH0_MAX_FETCH    V_ERR_TH0_MAX_FETCH(1U)
2132 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
2133 #define F_ITPOPMODE    V_ITPOPMODE(1U)
2137 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
2138 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
2142 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
2143 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
2147 #define V_STATMODE(x) ((x) << S_STATMODE)
2148 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
2152 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
2153 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
2157 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
2158 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
2162 #define V_T6_STATMODE(x) ((x) << S_T6_STATMODE)
2163 #define G_T6_STATMODE(x) (((x) >> S_T6_STATMODE) & M_T6_STATMODE)
2169 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
2170 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
2174 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
2175 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
2179 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
2180 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
2188 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
2189 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
2194 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
2195 #define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
2198 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
2199 #define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
2203 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
2204 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
2208 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
2209 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
2213 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
2214 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
2220 #define V_MINTAG3(x) ((x) << S_MINTAG3)
2221 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
2225 #define V_MINTAG2(x) ((x) << S_MINTAG2)
2226 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
2230 #define V_MINTAG1(x) ((x) << S_MINTAG1)
2231 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
2235 #define V_MINTAG0(x) ((x) << S_MINTAG0)
2236 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
2243 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
2244 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
2250 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
2251 #define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
2254 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
2255 #define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
2258 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
2259 #define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
2262 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
2263 #define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
2266 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
2267 #define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
2270 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
2271 #define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
2274 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
2275 #define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
2278 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
2279 #define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
2282 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
2283 #define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
2286 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
2287 #define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
2290 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
2291 #define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
2294 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
2295 #define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
2298 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
2299 #define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
2302 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
2303 #define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
2306 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
2307 #define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
2310 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
2311 #define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
2314 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
2315 #define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
2318 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
2319 #define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
2322 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
2323 #define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
2326 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
2327 #define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
2330 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
2331 #define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
2334 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
2335 #define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
2338 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
2339 #define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
2342 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
2343 #define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
2346 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
2347 #define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
2350 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
2351 #define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
2354 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
2355 #define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
2358 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
2359 #define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
2362 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
2363 #define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
2366 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
2367 #define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
2369 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
2370 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
2371 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
2374 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
2375 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
2378 #define V_PERR_POINTER_HDR_FIFO3(x) ((x) << S_PERR_POINTER_HDR_FIFO3)
2379 #define F_PERR_POINTER_HDR_FIFO3    V_PERR_POINTER_HDR_FIFO3(1U)
2382 #define V_PERR_POINTER_HDR_FIFO2(x) ((x) << S_PERR_POINTER_HDR_FIFO2)
2383 #define F_PERR_POINTER_HDR_FIFO2    V_PERR_POINTER_HDR_FIFO2(1U)
2386 #define V_PERR_POINTER_DATA_FIFO3(x) ((x) << S_PERR_POINTER_DATA_FIFO3)
2387 #define F_PERR_POINTER_DATA_FIFO3    V_PERR_POINTER_DATA_FIFO3(1U)
2390 #define V_PERR_POINTER_DATA_FIFO2(x) ((x) << S_PERR_POINTER_DATA_FIFO2)
2391 #define F_PERR_POINTER_DATA_FIFO2    V_PERR_POINTER_DATA_FIFO2(1U)
2394 #define V_PERR_IDMA2IMSG_FIFO3(x) ((x) << S_PERR_IDMA2IMSG_FIFO3)
2395 #define F_PERR_IDMA2IMSG_FIFO3    V_PERR_IDMA2IMSG_FIFO3(1U)
2398 #define V_PERR_IDMA2IMSG_FIFO2(x) ((x) << S_PERR_IDMA2IMSG_FIFO2)
2399 #define F_PERR_IDMA2IMSG_FIFO2    V_PERR_IDMA2IMSG_FIFO2(1U)
2402 #define V_PERR_HINT_DELAY_FIFO(x) ((x) << S_PERR_HINT_DELAY_FIFO)
2403 #define F_PERR_HINT_DELAY_FIFO    V_PERR_HINT_DELAY_FIFO(1U)
2411 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
2412 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
2416 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
2417 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
2421 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
2422 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
2426 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
2427 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
2433 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
2434 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
2438 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
2439 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
2445 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
2446 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
2450 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
2451 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
2456 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
2457 #define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
2460 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
2461 #define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
2464 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
2465 #define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
2469 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
2470 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
2473 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
2474 #define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
2477 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
2478 #define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
2481 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
2482 #define F_CGEN_IDMA    V_CGEN_IDMA(1U)
2485 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
2486 #define F_CGEN_DBP    V_CGEN_DBP(1U)
2489 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
2490 #define F_CGEN_EDMA    V_CGEN_EDMA(1U)
2493 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
2494 #define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
2497 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
2498 #define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
2502 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
2503 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
2506 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
2507 #define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
2510 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
2511 #define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
2513 #define S_COAL_STRICT_CIM_PRI    1
2514 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
2515 #define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
2518 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
2519 #define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
2522 #define V_HINT_SGE_SEL(x) ((x) << S_HINT_SGE_SEL)
2523 #define F_HINT_SGE_SEL    V_HINT_SGE_SEL(1U)
2526 #define V_HINT_SEL(x) ((x) << S_HINT_SEL)
2527 #define F_HINT_SEL    V_HINT_SEL(1U)
2530 #define V_HINT_DISABLE(x) ((x) << S_HINT_DISABLE)
2531 #define F_HINT_DISABLE    V_HINT_DISABLE(1U)
2534 #define V_RXCPLMODE_ISCSI(x) ((x) << S_RXCPLMODE_ISCSI)
2535 #define F_RXCPLMODE_ISCSI    V_RXCPLMODE_ISCSI(1U)
2538 #define V_RXCPLMODE_NVMT(x) ((x) << S_RXCPLMODE_NVMT)
2539 #define F_RXCPLMODE_NVMT    V_RXCPLMODE_NVMT(1U)
2542 #define V_WRE_REPLAY_INORDER(x) ((x) << S_WRE_REPLAY_INORDER)
2543 #define F_WRE_REPLAY_INORDER    V_WRE_REPLAY_INORDER(1U)
2546 #define V_ETH2XEN(x) ((x) << S_ETH2XEN)
2547 #define F_ETH2XEN    V_ETH2XEN(1U)
2550 #define V_ARMDBENDDIS(x) ((x) << S_ARMDBENDDIS)
2551 #define F_ARMDBENDDIS    V_ARMDBENDDIS(1U)
2554 #define V_PACKPADT7(x) ((x) << S_PACKPADT7)
2555 #define F_PACKPADT7    V_PACKPADT7(1U)
2558 #define V_WRE_UPFLCREDIT(x) ((x) << S_WRE_UPFLCREDIT)
2559 #define F_WRE_UPFLCREDIT    V_WRE_UPFLCREDIT(1U)
2564 #define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
2565 #define F_IDMA1_SLEEP_STATUS    V_IDMA1_SLEEP_STATUS(1U)
2568 #define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
2569 #define F_IDMA0_SLEEP_STATUS    V_IDMA0_SLEEP_STATUS(1U)
2572 #define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
2573 #define F_IDMA1_SLEEP_REQ    V_IDMA1_SLEEP_REQ(1U)
2576 #define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
2577 #define F_IDMA0_SLEEP_REQ    V_IDMA0_SLEEP_REQ(1U)
2580 #define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
2581 #define F_EDMA3_SLEEP_STATUS    V_EDMA3_SLEEP_STATUS(1U)
2584 #define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
2585 #define F_EDMA2_SLEEP_STATUS    V_EDMA2_SLEEP_STATUS(1U)
2588 #define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
2589 #define F_EDMA1_SLEEP_STATUS    V_EDMA1_SLEEP_STATUS(1U)
2592 #define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
2593 #define F_EDMA0_SLEEP_STATUS    V_EDMA0_SLEEP_STATUS(1U)
2596 #define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
2597 #define F_EDMA3_SLEEP_REQ    V_EDMA3_SLEEP_REQ(1U)
2600 #define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
2601 #define F_EDMA2_SLEEP_REQ    V_EDMA2_SLEEP_REQ(1U)
2603 #define S_EDMA1_SLEEP_REQ    1
2604 #define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
2605 #define F_EDMA1_SLEEP_REQ    V_EDMA1_SLEEP_REQ(1U)
2608 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
2609 #define F_EDMA0_SLEEP_REQ    V_EDMA0_SLEEP_REQ(1U)
2614 #define V_ERR_DB_SYNC(x) ((x) << S_ERR_DB_SYNC)
2615 #define F_ERR_DB_SYNC    V_ERR_DB_SYNC(1U)
2618 #define V_ERR_GTS_SYNC(x) ((x) << S_ERR_GTS_SYNC)
2619 #define F_ERR_GTS_SYNC    V_ERR_GTS_SYNC(1U)
2622 #define V_FATAL_LARGE_COAL(x) ((x) << S_FATAL_LARGE_COAL)
2623 #define F_FATAL_LARGE_COAL    V_FATAL_LARGE_COAL(1U)
2626 #define V_PL_BAR2_FRM_ERR(x) ((x) << S_PL_BAR2_FRM_ERR)
2627 #define F_PL_BAR2_FRM_ERR    V_PL_BAR2_FRM_ERR(1U)
2630 #define V_SILENT_DROP_TX_COAL(x) ((x) << S_SILENT_DROP_TX_COAL)
2631 #define F_SILENT_DROP_TX_COAL    V_SILENT_DROP_TX_COAL(1U)
2634 #define V_ERR_INV_CTXT4(x) ((x) << S_ERR_INV_CTXT4)
2635 #define F_ERR_INV_CTXT4    V_ERR_INV_CTXT4(1U)
2638 #define V_ERR_BAD_DB_PIDX4(x) ((x) << S_ERR_BAD_DB_PIDX4)
2639 #define F_ERR_BAD_DB_PIDX4    V_ERR_BAD_DB_PIDX4(1U)
2642 #define V_ERR_BAD_UPFL_INC_CREDIT4(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT4)
2643 #define F_ERR_BAD_UPFL_INC_CREDIT4    V_ERR_BAD_UPFL_INC_CREDIT4(1U)
2646 #define V_FATAL_TAG_MISMATCH(x) ((x) << S_FATAL_TAG_MISMATCH)
2647 #define F_FATAL_TAG_MISMATCH    V_FATAL_TAG_MISMATCH(1U)
2650 #define V_FATAL_ENQ_CTL_RDY(x) ((x) << S_FATAL_ENQ_CTL_RDY)
2651 #define F_FATAL_ENQ_CTL_RDY    V_FATAL_ENQ_CTL_RDY(1U)
2654 #define V_ERR_PC_RSP_LEN3(x) ((x) << S_ERR_PC_RSP_LEN3)
2655 #define F_ERR_PC_RSP_LEN3    V_ERR_PC_RSP_LEN3(1U)
2658 #define V_ERR_PC_RSP_LEN2(x) ((x) << S_ERR_PC_RSP_LEN2)
2659 #define F_ERR_PC_RSP_LEN2    V_ERR_PC_RSP_LEN2(1U)
2662 #define V_ERR_PC_RSP_LEN1(x) ((x) << S_ERR_PC_RSP_LEN1)
2663 #define F_ERR_PC_RSP_LEN1    V_ERR_PC_RSP_LEN1(1U)
2666 #define V_ERR_PC_RSP_LEN0(x) ((x) << S_ERR_PC_RSP_LEN0)
2667 #define F_ERR_PC_RSP_LEN0    V_ERR_PC_RSP_LEN0(1U)
2670 #define V_FATAL_ENQ2LL_VLD(x) ((x) << S_FATAL_ENQ2LL_VLD)
2671 #define F_FATAL_ENQ2LL_VLD    V_FATAL_ENQ2LL_VLD(1U)
2674 #define V_FATAL_LL_EMPTY(x) ((x) << S_FATAL_LL_EMPTY)
2675 #define F_FATAL_LL_EMPTY    V_FATAL_LL_EMPTY(1U)
2678 #define V_FATAL_OFF_WDENQ(x) ((x) << S_FATAL_OFF_WDENQ)
2679 #define F_FATAL_OFF_WDENQ    V_FATAL_OFF_WDENQ(1U)
2683 #define V_FATAL_DEQ_DRDY(x) ((x) << S_FATAL_DEQ_DRDY)
2684 #define G_FATAL_DEQ_DRDY(x) (((x) >> S_FATAL_DEQ_DRDY) & M_FATAL_DEQ_DRDY)
2686 #define S_FATAL_OUTP_DRDY    1
2688 #define V_FATAL_OUTP_DRDY(x) ((x) << S_FATAL_OUTP_DRDY)
2689 #define G_FATAL_OUTP_DRDY(x) (((x) >> S_FATAL_OUTP_DRDY) & M_FATAL_OUTP_DRDY)
2692 #define V_FATAL_DEQ(x) ((x) << S_FATAL_DEQ)
2693 #define F_FATAL_DEQ    V_FATAL_DEQ(1U)
2697 #define V_FATAL_DEQ0_DRDY(x) ((x) << S_FATAL_DEQ0_DRDY)
2698 #define G_FATAL_DEQ0_DRDY(x) (((x) >> S_FATAL_DEQ0_DRDY) & M_FATAL_DEQ0_DRDY)
2702 #define V_FATAL_OUT0_DRDY(x) ((x) << S_FATAL_OUT0_DRDY)
2703 #define G_FATAL_OUT0_DRDY(x) (((x) >> S_FATAL_OUT0_DRDY) & M_FATAL_OUT0_DRDY)
2706 #define V_IMSG_DBG3_STUCK(x) ((x) << S_IMSG_DBG3_STUCK)
2707 #define F_IMSG_DBG3_STUCK    V_IMSG_DBG3_STUCK(1U)
2710 #define V_IMSG_DBG2_STUCK(x) ((x) << S_IMSG_DBG2_STUCK)
2711 #define F_IMSG_DBG2_STUCK    V_IMSG_DBG2_STUCK(1U)
2714 #define V_IMSG_DBG1_STUCK(x) ((x) << S_IMSG_DBG1_STUCK)
2715 #define F_IMSG_DBG1_STUCK    V_IMSG_DBG1_STUCK(1U)
2718 #define V_IMSG_DBG0_STUCK(x) ((x) << S_IMSG_DBG0_STUCK)
2719 #define F_IMSG_DBG0_STUCK    V_IMSG_DBG0_STUCK(1U)
2723 #define V_FATAL_DEQ1_DRDY(x) ((x) << S_FATAL_DEQ1_DRDY)
2724 #define G_FATAL_DEQ1_DRDY(x) (((x) >> S_FATAL_DEQ1_DRDY) & M_FATAL_DEQ1_DRDY)
2726 #define S_FATAL_OUT1_DRDY    1
2728 #define V_FATAL_OUT1_DRDY(x) ((x) << S_FATAL_OUT1_DRDY)
2729 #define G_FATAL_OUT1_DRDY(x) (((x) >> S_FATAL_OUT1_DRDY) & M_FATAL_OUT1_DRDY)
2735 #define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
2736 #define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
2740 #define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
2741 #define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
2745 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
2746 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
2753 #define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
2754 #define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
2758 #define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
2759 #define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
2763 #define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
2764 #define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
2767 #define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
2768 #define F_DBP_FETCH_THRESHOLD_MODE    V_DBP_FETCH_THRESHOLD_MODE(1U)
2771 #define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
2772 #define F_DBP_FETCH_THRESHOLD_EN3    V_DBP_FETCH_THRESHOLD_EN3(1U)
2775 #define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
2776 #define F_DBP_FETCH_THRESHOLD_EN2    V_DBP_FETCH_THRESHOLD_EN2(1U)
2778 #define S_DBP_FETCH_THRESHOLD_EN1    1
2779 #define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
2780 #define F_DBP_FETCH_THRESHOLD_EN1    V_DBP_FETCH_THRESHOLD_EN1(1U)
2783 #define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
2784 #define F_DBP_FETCH_THRESHOLD_EN0    V_DBP_FETCH_THRESHOLD_EN0(1U)
2790 #define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
2791 #define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
2795 #define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
2796 #define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
2803 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2804 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2808 #define V_T6_DBVFIFO_SIZE(x) ((x) << S_T6_DBVFIFO_SIZE)
2809 #define G_T6_DBVFIFO_SIZE(x) (((x) >> S_T6_DBVFIFO_SIZE) & M_T6_DBVFIFO_SIZE)
2814 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2815 #define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
2818 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2819 #define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
2823 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2824 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2828 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2829 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2833 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2834 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2842 #define V_DBPTBUFRSV1(x) ((x) << S_DBPTBUFRSV1)
2843 #define G_DBPTBUFRSV1(x) (((x) >> S_DBPTBUFRSV1) & M_DBPTBUFRSV1)
2847 #define V_DBPTBUFRSV0(x) ((x) << S_DBPTBUFRSV0)
2848 #define G_DBPTBUFRSV0(x) (((x) >> S_DBPTBUFRSV0) & M_DBPTBUFRSV0)
2855 #define V_DBPTBUFRSV3(x) ((x) << S_DBPTBUFRSV3)
2856 #define G_DBPTBUFRSV3(x) (((x) >> S_DBPTBUFRSV3) & M_DBPTBUFRSV3)
2860 #define V_DBPTBUFRSV2(x) ((x) << S_DBPTBUFRSV2)
2861 #define G_DBPTBUFRSV2(x) (((x) >> S_DBPTBUFRSV2) & M_DBPTBUFRSV2)
2867 #define V_DBPTBUFRSV5(x) ((x) << S_DBPTBUFRSV5)
2868 #define G_DBPTBUFRSV5(x) (((x) >> S_DBPTBUFRSV5) & M_DBPTBUFRSV5)
2872 #define V_DBPTBUFRSV4(x) ((x) << S_DBPTBUFRSV4)
2873 #define G_DBPTBUFRSV4(x) (((x) >> S_DBPTBUFRSV4) & M_DBPTBUFRSV4)
2879 #define V_DBPTBUFRSV7(x) ((x) << S_DBPTBUFRSV7)
2880 #define G_DBPTBUFRSV7(x) (((x) >> S_DBPTBUFRSV7) & M_DBPTBUFRSV7)
2884 #define V_DBPTBUFRSV6(x) ((x) << S_DBPTBUFRSV6)
2885 #define G_DBPTBUFRSV6(x) (((x) >> S_DBPTBUFRSV6) & M_DBPTBUFRSV6)
2891 #define V_DBPTBUFRSV9(x) ((x) << S_DBPTBUFRSV9)
2892 #define G_DBPTBUFRSV9(x) (((x) >> S_DBPTBUFRSV9) & M_DBPTBUFRSV9)
2896 #define V_DBPTBUFRSV8(x) ((x) << S_DBPTBUFRSV8)
2897 #define G_DBPTBUFRSV8(x) (((x) >> S_DBPTBUFRSV8) & M_DBPTBUFRSV8)
2911 #define V_TXTIMETH3(x) ((x) << S_TXTIMETH3)
2912 #define G_TXTIMETH3(x) (((x) >> S_TXTIMETH3) & M_TXTIMETH3)
2916 #define V_TXTIMETH2(x) ((x) << S_TXTIMETH2)
2917 #define G_TXTIMETH2(x) (((x) >> S_TXTIMETH2) & M_TXTIMETH2)
2921 #define V_TXTIMETH1(x) ((x) << S_TXTIMETH1)
2922 #define G_TXTIMETH1(x) (((x) >> S_TXTIMETH1) & M_TXTIMETH1)
2926 #define V_TXTIMETH0(x) ((x) << S_TXTIMETH0)
2927 #define G_TXTIMETH0(x) (((x) >> S_TXTIMETH0) & M_TXTIMETH0)
2933 #define V_TXTIMETH7(x) ((x) << S_TXTIMETH7)
2934 #define G_TXTIMETH7(x) (((x) >> S_TXTIMETH7) & M_TXTIMETH7)
2938 #define V_TXTIMETH6(x) ((x) << S_TXTIMETH6)
2939 #define G_TXTIMETH6(x) (((x) >> S_TXTIMETH6) & M_TXTIMETH6)
2943 #define V_TXTIMETH5(x) ((x) << S_TXTIMETH5)
2944 #define G_TXTIMETH5(x) (((x) >> S_TXTIMETH5) & M_TXTIMETH5)
2948 #define V_TXTIMETH4(x) ((x) << S_TXTIMETH4)
2949 #define G_TXTIMETH4(x) (((x) >> S_TXTIMETH4) & M_TXTIMETH4)
2955 #define V_DBQ_TIMER_OP(x) ((x) << S_DBQ_TIMER_OP)
2956 #define G_DBQ_TIMER_OP(x) (((x) >> S_DBQ_TIMER_OP) & M_DBQ_TIMER_OP)
2961 #define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
2962 #define F_DBQ_TIMER_CMD    V_DBQ_TIMER_CMD(1U)
2966 #define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
2967 #define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
2971 #define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
2972 #define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
2977 #define V_TRACE_RXPERR(x) ((x) << S_TRACE_RXPERR)
2978 #define F_TRACE_RXPERR    V_TRACE_RXPERR(1U)
2981 #define V_U3_RXPERR(x) ((x) << S_U3_RXPERR)
2982 #define F_U3_RXPERR    V_U3_RXPERR(1U)
2985 #define V_U2_RXPERR(x) ((x) << S_U2_RXPERR)
2986 #define F_U2_RXPERR    V_U2_RXPERR(1U)
2989 #define V_U1_RXPERR(x) ((x) << S_U1_RXPERR)
2990 #define F_U1_RXPERR    V_U1_RXPERR(1U)
2993 #define V_U0_RXPERR(x) ((x) << S_U0_RXPERR)
2994 #define F_U0_RXPERR    V_U0_RXPERR(1U)
2997 #define V_T3_RXPERR(x) ((x) << S_T3_RXPERR)
2998 #define F_T3_RXPERR    V_T3_RXPERR(1U)
3001 #define V_T2_RXPERR(x) ((x) << S_T2_RXPERR)
3002 #define F_T2_RXPERR    V_T2_RXPERR(1U)
3004 #define S_T1_RXPERR    1
3005 #define V_T1_RXPERR(x) ((x) << S_T1_RXPERR)
3006 #define F_T1_RXPERR    V_T1_RXPERR(1U)
3009 #define V_T0_RXPERR(x) ((x) << S_T0_RXPERR)
3010 #define F_T0_RXPERR    V_T0_RXPERR(1U)
3017 #define V_BUSY(x) ((x) << S_BUSY)
3018 #define F_BUSY    V_BUSY(1U)
3022 #define V_CTXTOP(x) ((x) << S_CTXTOP)
3023 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
3027 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
3028 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
3032 #define V_CTXTQID(x) ((x) << S_CTXTQID)
3033 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
3045 #define V_DATA_UNUSED(x) ((x) << S_DATA_UNUSED)
3046 #define G_DATA_UNUSED(x) (((x) >> S_DATA_UNUSED) & M_DATA_UNUSED)
3050 #define V_DATA6(x) ((x) << S_DATA6)
3051 #define G_DATA6(x) (((x) >> S_DATA6) & M_DATA6)
3064 #define V_MASK_UNUSED(x) ((x) << S_MASK_UNUSED)
3065 #define G_MASK_UNUSED(x) (((x) >> S_MASK_UNUSED) & M_MASK_UNUSED)
3069 #define V_MASK(x) ((x) << S_MASK)
3070 #define G_MASK(x) (((x) >> S_MASK) & M_MASK)
3077 #define V_EGRESS0_SIZE(x) ((x) << S_EGRESS0_SIZE)
3078 #define G_EGRESS0_SIZE(x) (((x) >> S_EGRESS0_SIZE) & M_EGRESS0_SIZE)
3082 #define V_EGRESS1_SIZE(x) ((x) << S_EGRESS1_SIZE)
3083 #define G_EGRESS1_SIZE(x) (((x) >> S_EGRESS1_SIZE) & M_EGRESS1_SIZE)
3087 #define V_INGRESS0_SIZE(x) ((x) << S_INGRESS0_SIZE)
3088 #define G_INGRESS0_SIZE(x) (((x) >> S_INGRESS0_SIZE) & M_INGRESS0_SIZE)
3091 #define V_DESTINATION(x) ((x) << S_DESTINATION)
3092 #define F_DESTINATION    V_DESTINATION(1U)
3098 #define V_EGRESS0_BASE(x) ((x) << S_EGRESS0_BASE)
3099 #define G_EGRESS0_BASE(x) (((x) >> S_EGRESS0_BASE) & M_EGRESS0_BASE)
3105 #define V_EGRESS1_BASE(x) ((x) << S_EGRESS1_BASE)
3106 #define G_EGRESS1_BASE(x) (((x) >> S_EGRESS1_BASE) & M_EGRESS1_BASE)
3112 #define V_INGRESS1_BASE_256VF(x) ((x) << S_INGRESS1_BASE_256VF)
3113 #define G_INGRESS1_BASE_256VF(x) (((x) >> S_INGRESS1_BASE_256VF) & M_INGRESS1_BASE_256VF)
3117 #define V_INGRESS0_BASE(x) ((x) << S_INGRESS0_BASE)
3118 #define G_INGRESS0_BASE(x) (((x) >> S_INGRESS0_BASE) & M_INGRESS0_BASE)
3124 #define V_QIDX(x) ((x) << S_QIDX)
3125 #define G_QIDX(x) (((x) >> S_QIDX) & M_QIDX)
3131 #define V_FLMTHRESHPACK(x) ((x) << S_FLMTHRESHPACK)
3132 #define G_FLMTHRESHPACK(x) (((x) >> S_FLMTHRESHPACK) & M_FLMTHRESHPACK)
3136 #define V_FLMTHRESH(x) ((x) << S_FLMTHRESH)
3137 #define G_FLMTHRESH(x) (((x) >> S_FLMTHRESH) & M_FLMTHRESH)
3140 #define V_CONENMIDDLE(x) ((x) << S_CONENMIDDLE)
3141 #define F_CONENMIDDLE    V_CONENMIDDLE(1U)
3147 #define V_MPS_CH_CNG(x) ((x) << S_MPS_CH_CNG)
3148 #define G_MPS_CH_CNG(x) (((x) >> S_MPS_CH_CNG) & M_MPS_CH_CNG)
3152 #define V_TP_CH_CNG(x) ((x) << S_TP_CH_CNG)
3153 #define G_TP_CH_CNG(x) (((x) >> S_TP_CH_CNG) & M_TP_CH_CNG)
3157 #define V_ST_CONG(x) ((x) << S_ST_CONG)
3158 #define G_ST_CONG(x) (((x) >> S_ST_CONG) & M_ST_CONG)
3161 #define V_LAST_XOFF(x) ((x) << S_LAST_XOFF)
3162 #define F_LAST_XOFF    V_LAST_XOFF(1U)
3166 #define V_LAST_QID(x) ((x) << S_LAST_QID)
3167 #define G_LAST_QID(x) (((x) >> S_LAST_QID) & M_LAST_QID)
3171 #define V_CH_CNG(x) ((x) << S_CH_CNG)
3172 #define G_CH_CNG(x) (((x) >> S_CH_CNG) & M_CH_CNG)
3176 #define V_CH_SEL(x) ((x) << S_CH_SEL)
3177 #define G_CH_SEL(x) (((x) >> S_CH_SEL) & M_CH_SEL)
3182 #define V_IMSG_GTS_SEL(x) ((x) << S_IMSG_GTS_SEL)
3183 #define F_IMSG_GTS_SEL    V_IMSG_GTS_SEL(1U)
3186 #define V_MGT_SEL(x) ((x) << S_MGT_SEL)
3187 #define F_MGT_SEL    V_MGT_SEL(1U)
3191 #define V_DB_GTS_QID(x) ((x) << S_DB_GTS_QID)
3192 #define G_DB_GTS_QID(x) (((x) >> S_DB_GTS_QID) & M_DB_GTS_QID)
3205 #define V_CIM_WM(x) ((x) << S_CIM_WM)
3206 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
3210 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
3211 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
3215 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
3216 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
3220 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
3221 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
3225 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
3226 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
3230 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
3231 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
3235 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
3236 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
3240 #define V_DEBUG_BAR2_SOP_CNT(x) ((x) << S_DEBUG_BAR2_SOP_CNT)
3241 #define G_DEBUG_BAR2_SOP_CNT(x) (((x) >> S_DEBUG_BAR2_SOP_CNT) & M_DEBUG_BAR2_SOP_CNT)
3245 #define V_DEBUG_BAR2_EOP_CNT(x) ((x) << S_DEBUG_BAR2_EOP_CNT)
3246 #define G_DEBUG_BAR2_EOP_CNT(x) (((x) >> S_DEBUG_BAR2_EOP_CNT) & M_DEBUG_BAR2_EOP_CNT)
3252 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
3253 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
3257 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
3258 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
3262 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
3263 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
3267 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
3268 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
3272 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
3273 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
3277 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
3278 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
3282 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
3283 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
3287 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
3288 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
3294 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
3295 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
3299 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
3300 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
3304 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
3305 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
3309 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
3310 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
3314 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
3315 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
3319 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
3320 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
3324 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
3325 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
3329 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
3330 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
3334 #define V_DBG_TBUF_USED1(x) ((x) << S_DBG_TBUF_USED1)
3335 #define G_DBG_TBUF_USED1(x) (((x) >> S_DBG_TBUF_USED1) & M_DBG_TBUF_USED1)
3339 #define V_DBG_TBUF_USED0(x) ((x) << S_DBG_TBUF_USED0)
3340 #define G_DBG_TBUF_USED0(x) (((x) >> S_DBG_TBUF_USED0) & M_DBG_TBUF_USED0)
3346 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
3347 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
3351 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
3352 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
3356 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
3357 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
3361 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
3362 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
3366 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
3367 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
3371 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
3372 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
3376 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
3377 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
3381 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
3382 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
3388 #define V_WR_DEQ_CNT(x) ((x) << S_WR_DEQ_CNT)
3389 #define G_WR_DEQ_CNT(x) (((x) >> S_WR_DEQ_CNT) & M_WR_DEQ_CNT)
3393 #define V_WR_ENQ_CNT(x) ((x) << S_WR_ENQ_CNT)
3394 #define G_WR_ENQ_CNT(x) (((x) >> S_WR_ENQ_CNT) & M_WR_ENQ_CNT)
3398 #define V_FL_DEQ_CNT(x) ((x) << S_FL_DEQ_CNT)
3399 #define G_FL_DEQ_CNT(x) (((x) >> S_FL_DEQ_CNT) & M_FL_DEQ_CNT)
3403 #define V_FL_ENQ_CNT(x) ((x) << S_FL_ENQ_CNT)
3404 #define G_FL_ENQ_CNT(x) (((x) >> S_FL_ENQ_CNT) & M_FL_ENQ_CNT)
3410 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
3411 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
3415 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
3416 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
3420 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
3421 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
3425 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
3426 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
3430 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
3431 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
3435 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
3436 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
3440 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
3441 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
3445 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
3446 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
3452 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
3453 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
3457 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
3458 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
3462 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
3463 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
3467 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
3468 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
3472 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
3473 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
3477 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
3478 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
3482 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
3483 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
3487 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
3488 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
3494 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
3495 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
3499 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
3500 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
3504 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
3505 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
3509 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
3510 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
3514 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
3515 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
3519 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
3520 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
3524 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
3525 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
3529 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
3530 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
3536 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
3537 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
3541 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
3542 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
3546 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
3547 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
3551 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
3552 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
3556 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
3557 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
3561 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
3562 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
3566 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
3567 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
3571 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
3572 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
3576 #define V_DEBUG_PC_RSP_SOP_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP_CNT)
3577 #define G_DEBUG_PC_RSP_SOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP_CNT) & M_DEBUG_PC_RSP_SOP_CNT)
3581 #define V_DEBUG_PC_RSP_EOP_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP_CNT)
3582 #define G_DEBUG_PC_RSP_EOP_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP_CNT) & M_DEBUG_PC_RSP_EOP_CNT)
3586 #define V_DEBUG_PC_REQ_SOP_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP_CNT)
3587 #define G_DEBUG_PC_REQ_SOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP_CNT) & M_DEBUG_PC_REQ_SOP_CNT)
3591 #define V_DEBUG_PC_REQ_EOP_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP_CNT)
3592 #define G_DEBUG_PC_REQ_EOP_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP_CNT) & M_DEBUG_PC_REQ_EOP_CNT)
3597 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
3598 #define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
3602 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
3603 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
3607 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
3608 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
3611 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
3612 #define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
3615 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
3616 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
3619 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
3620 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
3623 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
3624 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
3627 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
3628 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
3631 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
3632 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
3635 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
3636 #define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
3639 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
3640 #define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
3643 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
3644 #define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
3648 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
3649 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
3653 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
3654 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
3658 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
3659 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
3663 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
3664 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
3667 #define V_DEBUG_PL_BAR2_REQVLD(x) ((x) << S_DEBUG_PL_BAR2_REQVLD)
3668 #define F_DEBUG_PL_BAR2_REQVLD    V_DEBUG_PL_BAR2_REQVLD(1U)
3671 #define V_DEBUG_PL_BAR2_REQFULL(x) ((x) << S_DEBUG_PL_BAR2_REQFULL)
3672 #define F_DEBUG_PL_BAR2_REQFULL    V_DEBUG_PL_BAR2_REQFULL(1U)
3678 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3679 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
3683 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3684 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
3688 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3689 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
3693 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3694 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
3698 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
3699 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
3703 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
3704 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
3708 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
3709 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
3713 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
3714 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
3720 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
3721 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
3725 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
3726 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
3730 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
3731 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
3735 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
3736 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
3740 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
3741 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
3745 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
3746 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
3750 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
3751 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
3755 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
3756 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
3760 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
3761 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
3765 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
3766 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
3770 #define V_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3771 #define G_DEBUG_IDMA1_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA1_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING)
3774 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY)
3775 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_SRDY(1U)
3778 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS)
3779 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_RSS(1U)
3782 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL)
3783 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA1_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3786 #define V_DEBUG_IDMA1_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FULL)
3787 #define F_DEBUG_IDMA1_IDMA2IMSG_FULL    V_DEBUG_IDMA1_IDMA2IMSG_FULL(1U)
3790 #define V_DEBUG_IDMA1_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_EOP)
3791 #define F_DEBUG_IDMA1_IDMA2IMSG_EOP    V_DEBUG_IDMA1_IDMA2IMSG_EOP(1U)
3794 #define V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY)
3795 #define F_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_FIFO_IN_DRDY(1U)
3798 #define V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY)
3799 #define F_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA1_IDMA2IMSG_CMP_IN_DRDY(1U)
3803 #define V_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) ((x) << S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3804 #define G_DEBUG_IDMA0_S_CPL_FLIT_REMAINING(x) (((x) >> S_DEBUG_IDMA0_S_CPL_FLIT_REMAINING) & M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING)
3807 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY)
3808 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_SRDY(1U)
3811 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS)
3812 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_RSS(1U)
3815 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL)
3816 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL    V_DEBUG_IDMA0_IDMA2IMSG_CMP_OUT_NOCPL(1U)
3819 #define V_DEBUG_IDMA0_IDMA2IMSG_FULL(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FULL)
3820 #define F_DEBUG_IDMA0_IDMA2IMSG_FULL    V_DEBUG_IDMA0_IDMA2IMSG_FULL(1U)
3823 #define V_DEBUG_IDMA0_IDMA2IMSG_EOP(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_EOP)
3824 #define F_DEBUG_IDMA0_IDMA2IMSG_EOP    V_DEBUG_IDMA0_IDMA2IMSG_EOP(1U)
3827 #define V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY)
3828 #define F_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_CMP_IN_DRDY(1U)
3831 #define V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(x) ((x) << S_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY)
3832 #define F_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY    V_DEBUG_IDMA0_IDMA2IMSG_FIFO_IN_DRDY(1U)
3836 #define V_T6_DEBUG_T_RXAFULL_D(x) ((x) << S_T6_DEBUG_T_RXAFULL_D)
3837 #define G_T6_DEBUG_T_RXAFULL_D(x) (((x) >> S_T6_DEBUG_T_RXAFULL_D) & M_T6_DEBUG_T_RXAFULL_D)
3841 #define V_T6_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_T6_DEBUG_PD_WRREQAFULL_D)
3842 #define G_T6_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_T6_DEBUG_PD_WRREQAFULL_D) & M_T6_DEBUG_PD_WRREQAFULL_D)
3845 #define V_T6_DEBUG_PC_RSPAFULL_D(x) ((x) << S_T6_DEBUG_PC_RSPAFULL_D)
3846 #define F_T6_DEBUG_PC_RSPAFULL_D    V_T6_DEBUG_PC_RSPAFULL_D(1U)
3849 #define V_T6_DEBUG_PC_REQAFULL_D(x) ((x) << S_T6_DEBUG_PC_REQAFULL_D)
3850 #define F_T6_DEBUG_PC_REQAFULL_D    V_T6_DEBUG_PC_REQAFULL_D(1U)
3853 #define V_T6_DEBUG_CIM_AFULL_D(x) ((x) << S_T6_DEBUG_CIM_AFULL_D)
3854 #define F_T6_DEBUG_CIM_AFULL_D    V_T6_DEBUG_CIM_AFULL_D(1U)
3859 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
3860 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
3863 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
3864 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
3867 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
3868 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
3871 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
3872 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
3876 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
3877 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
3881 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
3882 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
3885 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
3886 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
3889 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
3890 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
3893 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
3894 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
3897 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
3898 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
3902 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
3903 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
3907 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
3908 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
3914 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
3915 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
3919 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
3920 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
3924 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
3925 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
3929 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
3930 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
3934 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
3935 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
3939 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
3940 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
3944 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
3945 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
3949 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
3950 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
3954 #define V_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3955 #define G_DEBUG_IDMA1_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA1_ISHIFT_TX_SIZE) & M_DEBUG_IDMA1_ISHIFT_TX_SIZE)
3959 #define V_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) ((x) << S_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3960 #define G_DEBUG_IDMA0_ISHIFT_TX_SIZE(x) (((x) >> S_DEBUG_IDMA0_ISHIFT_TX_SIZE) & M_DEBUG_IDMA0_ISHIFT_TX_SIZE)
3969 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
3970 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
3974 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
3975 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
3979 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
3980 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
3984 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
3985 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
3989 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
3990 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
3994 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
3995 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
3999 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
4000 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
4004 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
4005 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
4008 #define V_DEBUG_ST_IDMA1_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA1_IDMA2IMSG)
4009 #define F_DEBUG_ST_IDMA1_IDMA2IMSG    V_DEBUG_ST_IDMA1_IDMA2IMSG(1U)
4012 #define V_DEBUG_ST_IDMA0_IDMA2IMSG(x) ((x) << S_DEBUG_ST_IDMA0_IDMA2IMSG)
4013 #define F_DEBUG_ST_IDMA0_IDMA2IMSG    V_DEBUG_ST_IDMA0_IDMA2IMSG(1U)
4019 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
4020 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
4024 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
4025 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
4028 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
4029 #define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
4032 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
4033 #define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
4036 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
4037 #define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
4041 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
4042 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
4048 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
4049 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
4053 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
4054 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
4058 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
4059 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
4063 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
4064 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
4068 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
4069 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
4073 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
4074 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
4078 #define V_T6_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_T6_DEBUG_ST_DBP_UPCP_MAIN)
4079 #define G_T6_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_T6_DEBUG_ST_DBP_UPCP_MAIN) & M_T6_DEBUG_ST_DBP_UPCP_MAIN)
4085 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
4086 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
4089 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
4090 #define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
4094 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
4095 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
4099 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
4100 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
4104 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
4105 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
4111 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
4112 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
4116 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
4117 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
4121 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
4122 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
4126 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
4127 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
4131 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
4132 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
4136 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
4137 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
4141 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
4142 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
4146 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
4147 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
4151 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
4152 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
4156 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
4157 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
4161 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
4162 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
4166 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
4167 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
4173 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
4174 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
4178 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
4179 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
4183 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
4184 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
4188 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
4189 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
4192 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
4193 #define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
4197 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
4198 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
4204 #define V_THREAD_ST_MAIN(x) ((x) << S_THREAD_ST_MAIN)
4205 #define G_THREAD_ST_MAIN(x) (((x) >> S_THREAD_ST_MAIN) & M_THREAD_ST_MAIN)
4209 #define V_THREAD_ST_CIMFL(x) ((x) << S_THREAD_ST_CIMFL)
4210 #define G_THREAD_ST_CIMFL(x) (((x) >> S_THREAD_ST_CIMFL) & M_THREAD_ST_CIMFL)
4214 #define V_THREAD_CMDOP(x) ((x) << S_THREAD_CMDOP)
4215 #define G_THREAD_CMDOP(x) (((x) >> S_THREAD_CMDOP) & M_THREAD_CMDOP)
4219 #define V_THREAD_QID(x) ((x) << S_THREAD_QID)
4220 #define G_THREAD_QID(x) (((x) >> S_THREAD_QID) & M_THREAD_QID)
4226 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
4227 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
4233 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
4234 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
4240 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
4241 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
4247 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
4248 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
4254 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
4255 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
4259 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
4260 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
4266 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
4267 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
4271 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
4272 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
4278 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
4279 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
4283 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
4284 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
4293 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
4294 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
4298 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
4299 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
4303 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
4304 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
4308 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
4309 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
4313 #define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
4314 #define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
4318 #define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
4319 #define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
4323 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
4324 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
4330 #define V_PFIQSPERPAGE(x) ((x) << S_PFIQSPERPAGE)
4331 #define G_PFIQSPERPAGE(x) (((x) >> S_PFIQSPERPAGE) & M_PFIQSPERPAGE)
4335 #define V_PFEQSPERPAGE(x) ((x) << S_PFEQSPERPAGE)
4336 #define G_PFEQSPERPAGE(x) (((x) >> S_PFEQSPERPAGE) & M_PFEQSPERPAGE)
4340 #define V_PFWCQSPERPAGE(x) ((x) << S_PFWCQSPERPAGE)
4341 #define G_PFWCQSPERPAGE(x) (((x) >> S_PFWCQSPERPAGE) & M_PFWCQSPERPAGE)
4344 #define V_PFWCOFFEN(x) ((x) << S_PFWCOFFEN)
4345 #define F_PFWCOFFEN    V_PFWCOFFEN(1U)
4349 #define V_PFMAXWCSIZE(x) ((x) << S_PFMAXWCSIZE)
4350 #define G_PFMAXWCSIZE(x) (((x) >> S_PFMAXWCSIZE) & M_PFMAXWCSIZE)
4354 #define V_PFWCOFFSET(x) ((x) << S_PFWCOFFSET)
4355 #define G_PFWCOFFSET(x) (((x) >> S_PFWCOFFSET) & M_PFWCOFFSET)
4361 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
4362 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
4366 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
4367 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
4373 #define V_VFIQSPERPAGE(x) ((x) << S_VFIQSPERPAGE)
4374 #define G_VFIQSPERPAGE(x) (((x) >> S_VFIQSPERPAGE) & M_VFIQSPERPAGE)
4378 #define V_VFEQSPERPAGE(x) ((x) << S_VFEQSPERPAGE)
4379 #define G_VFEQSPERPAGE(x) (((x) >> S_VFEQSPERPAGE) & M_VFEQSPERPAGE)
4383 #define V_VFWCQSPERPAGE(x) ((x) << S_VFWCQSPERPAGE)
4384 #define G_VFWCQSPERPAGE(x) (((x) >> S_VFWCQSPERPAGE) & M_VFWCQSPERPAGE)
4387 #define V_VFWCOFFEN(x) ((x) << S_VFWCOFFEN)
4388 #define F_VFWCOFFEN    V_VFWCOFFEN(1U)
4392 #define V_VFMAXWCSIZE(x) ((x) << S_VFMAXWCSIZE)
4393 #define G_VFMAXWCSIZE(x) (((x) >> S_VFMAXWCSIZE) & M_VFMAXWCSIZE)
4397 #define V_VFWCOFFSET(x) ((x) << S_VFWCOFFSET)
4398 #define G_VFWCOFFSET(x) (((x) >> S_VFWCOFFSET) & M_VFWCOFFSET)
4411 #define V_HINT_FIFO_FULL(x) ((x) << S_HINT_FIFO_FULL)
4412 #define F_HINT_FIFO_FULL    V_HINT_FIFO_FULL(1U)
4415 #define V_CERR_HINT_DELAY_FIFO(x) ((x) << S_CERR_HINT_DELAY_FIFO)
4416 #define F_CERR_HINT_DELAY_FIFO    V_CERR_HINT_DELAY_FIFO(1U)
4419 #define V_COAL_TIMER_FIFO_PERR(x) ((x) << S_COAL_TIMER_FIFO_PERR)
4420 #define F_COAL_TIMER_FIFO_PERR    V_COAL_TIMER_FIFO_PERR(1U)
4423 #define V_CMP_FIFO_PERR(x) ((x) << S_CMP_FIFO_PERR)
4424 #define F_CMP_FIFO_PERR    V_CMP_FIFO_PERR(1U)
4427 #define V_SGE_IPP_FIFO_CERR(x) ((x) << S_SGE_IPP_FIFO_CERR)
4428 #define F_SGE_IPP_FIFO_CERR    V_SGE_IPP_FIFO_CERR(1U)
4431 #define V_CERR_ING_CTXT_CACHE(x) ((x) << S_CERR_ING_CTXT_CACHE)
4432 #define F_CERR_ING_CTXT_CACHE    V_CERR_ING_CTXT_CACHE(1U)
4435 #define V_IMSG_CNTX_PERR(x) ((x) << S_IMSG_CNTX_PERR)
4436 #define F_IMSG_CNTX_PERR    V_IMSG_CNTX_PERR(1U)
4439 #define V_PD_FIFO_PERR(x) ((x) << S_PD_FIFO_PERR)
4440 #define F_PD_FIFO_PERR    V_PD_FIFO_PERR(1U)
4443 #define V_IMSG_512_FIFO_PERR(x) ((x) << S_IMSG_512_FIFO_PERR)
4444 #define F_IMSG_512_FIFO_PERR    V_IMSG_512_FIFO_PERR(1U)
4447 #define V_CPLSW_FIFO_PERR(x) ((x) << S_CPLSW_FIFO_PERR)
4448 #define F_CPLSW_FIFO_PERR    V_CPLSW_FIFO_PERR(1U)
4451 #define V_IMSG_FIFO_PERR(x) ((x) << S_IMSG_FIFO_PERR)
4452 #define F_IMSG_FIFO_PERR    V_IMSG_FIFO_PERR(1U)
4455 #define V_CERR_ITP_EVR(x) ((x) << S_CERR_ITP_EVR)
4456 #define F_CERR_ITP_EVR    V_CERR_ITP_EVR(1U)
4459 #define V_CERR_CONM_SRAM(x) ((x) << S_CERR_CONM_SRAM)
4460 #define F_CERR_CONM_SRAM    V_CERR_CONM_SRAM(1U)
4463 #define V_CERR_EGR_CTXT_CACHE(x) ((x) << S_CERR_EGR_CTXT_CACHE)
4464 #define F_CERR_EGR_CTXT_CACHE    V_CERR_EGR_CTXT_CACHE(1U)
4467 #define V_CERR_FLM_CNTXMEM(x) ((x) << S_CERR_FLM_CNTXMEM)
4468 #define F_CERR_FLM_CNTXMEM    V_CERR_FLM_CNTXMEM(1U)
4471 #define V_CERR_FUNC_QBASE(x) ((x) << S_CERR_FUNC_QBASE)
4472 #define F_CERR_FUNC_QBASE    V_CERR_FUNC_QBASE(1U)
4475 #define V_IMSG_CNTX_CERR(x) ((x) << S_IMSG_CNTX_CERR)
4476 #define F_IMSG_CNTX_CERR    V_IMSG_CNTX_CERR(1U)
4479 #define V_PD_FIFO_CERR(x) ((x) << S_PD_FIFO_CERR)
4480 #define F_PD_FIFO_CERR    V_PD_FIFO_CERR(1U)
4483 #define V_IMSG_512_FIFO_CERR(x) ((x) << S_IMSG_512_FIFO_CERR)
4484 #define F_IMSG_512_FIFO_CERR    V_IMSG_512_FIFO_CERR(1U)
4487 #define V_CPLSW_FIFO_CERR(x) ((x) << S_CPLSW_FIFO_CERR)
4488 #define F_CPLSW_FIFO_CERR    V_CPLSW_FIFO_CERR(1U)
4491 #define V_IMSG_FIFO_CERR(x) ((x) << S_IMSG_FIFO_CERR)
4492 #define F_IMSG_FIFO_CERR    V_IMSG_FIFO_CERR(1U)
4495 #define V_CERR_HEADERSPLIT_FIFO3(x) ((x) << S_CERR_HEADERSPLIT_FIFO3)
4496 #define F_CERR_HEADERSPLIT_FIFO3    V_CERR_HEADERSPLIT_FIFO3(1U)
4499 #define V_CERR_HEADERSPLIT_FIFO2(x) ((x) << S_CERR_HEADERSPLIT_FIFO2)
4500 #define F_CERR_HEADERSPLIT_FIFO2    V_CERR_HEADERSPLIT_FIFO2(1U)
4503 #define V_CERR_HEADERSPLIT_FIFO1(x) ((x) << S_CERR_HEADERSPLIT_FIFO1)
4504 #define F_CERR_HEADERSPLIT_FIFO1    V_CERR_HEADERSPLIT_FIFO1(1U)
4506 #define S_CERR_HEADERSPLIT_FIFO0    1
4507 #define V_CERR_HEADERSPLIT_FIFO0(x) ((x) << S_CERR_HEADERSPLIT_FIFO0)
4508 #define F_CERR_HEADERSPLIT_FIFO0    V_CERR_HEADERSPLIT_FIFO0(1U)
4511 #define V_CERR_FLM_L1CACHE(x) ((x) << S_CERR_FLM_L1CACHE)
4512 #define F_CERR_FLM_L1CACHE    V_CERR_FLM_L1CACHE(1U)
4519 #define V_USE_PTP_TIMER(x) ((x) << S_USE_PTP_TIMER)
4520 #define F_USE_PTP_TIMER    V_USE_PTP_TIMER(1U)
4523 #define V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(x) ((x) << S_IMSG_SET_OFLOW_ALL_ENTRIES_43060)
4524 #define F_IMSG_SET_OFLOW_ALL_ENTRIES_43060    V_IMSG_SET_OFLOW_ALL_ENTRIES_43060(1U)
4527 #define V_IMSG_STUCK_INDIRECT_QUEUE_42907(x) ((x) << S_IMSG_STUCK_INDIRECT_QUEUE_42907)
4528 #define F_IMSG_STUCK_INDIRECT_QUEUE_42907    V_IMSG_STUCK_INDIRECT_QUEUE_42907(1U)
4531 #define V_COMP_COAL_PIDX_INCR(x) ((x) << S_COMP_COAL_PIDX_INCR)
4532 #define F_COMP_COAL_PIDX_INCR    V_COMP_COAL_PIDX_INCR(1U)
4536 #define V_COMP_COAL_TIMER_CNT(x) ((x) << S_COMP_COAL_TIMER_CNT)
4537 #define G_COMP_COAL_TIMER_CNT(x) (((x) >> S_COMP_COAL_TIMER_CNT) & M_COMP_COAL_TIMER_CNT)
4541 #define V_COMP_COAL_CNTR_TH(x) ((x) << S_COMP_COAL_CNTR_TH)
4542 #define G_COMP_COAL_CNTR_TH(x) (((x) >> S_COMP_COAL_CNTR_TH) & M_COMP_COAL_CNTR_TH)
4546 #define V_COMP_COAL_OPCODE(x) ((x) << S_COMP_COAL_OPCODE)
4547 #define G_COMP_COAL_OPCODE(x) (((x) >> S_COMP_COAL_OPCODE) & M_COMP_COAL_OPCODE)
4551 #define S_STUCK_CTR_TH    1
4553 #define V_STUCK_CTR_TH(x) ((x) << S_STUCK_CTR_TH)
4554 #define G_STUCK_CTR_TH(x) (((x) >> S_STUCK_CTR_TH) & M_STUCK_CTR_TH)
4557 #define V_STUCK_INT_EN(x) ((x) << S_STUCK_INT_EN)
4558 #define F_STUCK_INT_EN    V_STUCK_INT_EN(1U)
4564 #define V_IDMA1_QID(x) ((x) << S_IDMA1_QID)
4565 #define G_IDMA1_QID(x) (((x) >> S_IDMA1_QID) & M_IDMA1_QID)
4569 #define V_IDMA0_QID(x) ((x) << S_IDMA0_QID)
4570 #define G_IDMA0_QID(x) (((x) >> S_IDMA0_QID) & M_IDMA0_QID)
4576 #define V_IDMA3_QID(x) ((x) << S_IDMA3_QID)
4577 #define G_IDMA3_QID(x) (((x) >> S_IDMA3_QID) & M_IDMA3_QID)
4581 #define V_IDMA2_QID(x) ((x) << S_IDMA2_QID)
4582 #define G_IDMA2_QID(x) (((x) >> S_IDMA2_QID) & M_IDMA2_QID)
4588 #define V_LB_MODE(x) ((x) << S_LB_MODE)
4589 #define G_LB_MODE(x) (((x) >> S_LB_MODE) & M_LB_MODE)
4594 #define V_IMSG_QUESCENT(x) ((x) << S_IMSG_QUESCENT)
4595 #define F_IMSG_QUESCENT    V_IMSG_QUESCENT(1U)
4600 #define V_LA_GLOBAL_EN(x) ((x) << S_LA_GLOBAL_EN)
4601 #define F_LA_GLOBAL_EN    V_LA_GLOBAL_EN(1U)
4604 #define V_PTP_TIMESTAMP_SEL(x) ((x) << S_PTP_TIMESTAMP_SEL)
4605 #define F_PTP_TIMESTAMP_SEL    V_PTP_TIMESTAMP_SEL(1U)
4608 #define V_CIM2SGE_ID_CHK_VLD(x) ((x) << S_CIM2SGE_ID_CHK_VLD)
4609 #define F_CIM2SGE_ID_CHK_VLD    V_CIM2SGE_ID_CHK_VLD(1U)
4612 #define V_CPLSW_ID_CHK_VLD(x) ((x) << S_CPLSW_ID_CHK_VLD)
4613 #define F_CPLSW_ID_CHK_VLD    V_CPLSW_ID_CHK_VLD(1U)
4616 #define V_FLM_ID_CHK_VLD(x) ((x) << S_FLM_ID_CHK_VLD)
4617 #define F_FLM_ID_CHK_VLD    V_FLM_ID_CHK_VLD(1U)
4620 #define V_IQ_DBP_ID_CHK_VLD(x) ((x) << S_IQ_DBP_ID_CHK_VLD)
4621 #define F_IQ_DBP_ID_CHK_VLD    V_IQ_DBP_ID_CHK_VLD(1U)
4624 #define V_UP_OBQ_ID_CHK_VLD(x) ((x) << S_UP_OBQ_ID_CHK_VLD)
4625 #define F_UP_OBQ_ID_CHK_VLD    V_UP_OBQ_ID_CHK_VLD(1U)
4627 #define S_CIM_ID_CHK_VLD    1
4628 #define V_CIM_ID_CHK_VLD(x) ((x) << S_CIM_ID_CHK_VLD)
4629 #define F_CIM_ID_CHK_VLD    V_CIM_ID_CHK_VLD(1U)
4632 #define V_DBP_ID_CHK_VLD(x) ((x) << S_DBP_ID_CHK_VLD)
4633 #define F_DBP_ID_CHK_VLD    V_DBP_ID_CHK_VLD(1U)
4639 #define V_EQ_ID_CHK_LOW(x) ((x) << S_EQ_ID_CHK_LOW)
4640 #define G_EQ_ID_CHK_LOW(x) (((x) >> S_EQ_ID_CHK_LOW) & M_EQ_ID_CHK_LOW)
4646 #define V_EQ_ID_CHK_HIGH(x) ((x) << S_EQ_ID_CHK_HIGH)
4647 #define G_EQ_ID_CHK_HIGH(x) (((x) >> S_EQ_ID_CHK_HIGH) & M_EQ_ID_CHK_HIGH)
4653 #define V_IQ_ID_CHK_HIGH(x) ((x) << S_IQ_ID_CHK_HIGH)
4654 #define G_IQ_ID_CHK_HIGH(x) (((x) >> S_IQ_ID_CHK_HIGH) & M_IQ_ID_CHK_HIGH)
4658 #define V_IQ_ID_CHK_LOW(x) ((x) << S_IQ_ID_CHK_LOW)
4659 #define G_IQ_ID_CHK_LOW(x) (((x) >> S_IQ_ID_CHK_LOW) & M_IQ_ID_CHK_LOW)
4665 #define V_TID_CHK_LOW(x) ((x) << S_TID_CHK_LOW)
4666 #define G_TID_CHK_LOW(x) (((x) >> S_TID_CHK_LOW) & M_TID_CHK_LOW)
4672 #define V_TID_CHK_HIGH(x) ((x) << S_TID_CHK_HIGH)
4673 #define G_TID_CHK_HIGH(x) (((x) >> S_TID_CHK_HIGH) & M_TID_CHK_HIGH)
4679 #define V_TP_ERR_STATUS_CH3(x) ((x) << S_TP_ERR_STATUS_CH3)
4680 #define G_TP_ERR_STATUS_CH3(x) (((x) >> S_TP_ERR_STATUS_CH3) & M_TP_ERR_STATUS_CH3)
4684 #define V_TP_ERR_STATUS_CH2(x) ((x) << S_TP_ERR_STATUS_CH2)
4685 #define G_TP_ERR_STATUS_CH2(x) (((x) >> S_TP_ERR_STATUS_CH2) & M_TP_ERR_STATUS_CH2)
4689 #define V_TP_ERR_STATUS_CH1(x) ((x) << S_TP_ERR_STATUS_CH1)
4690 #define G_TP_ERR_STATUS_CH1(x) (((x) >> S_TP_ERR_STATUS_CH1) & M_TP_ERR_STATUS_CH1)
4694 #define V_TP_ERR_STATUS_CH0(x) ((x) << S_TP_ERR_STATUS_CH0)
4695 #define G_TP_ERR_STATUS_CH0(x) (((x) >> S_TP_ERR_STATUS_CH0) & M_TP_ERR_STATUS_CH0)
4699 #define V_CPL0_SIZE(x) ((x) << S_CPL0_SIZE)
4700 #define G_CPL0_SIZE(x) (((x) >> S_CPL0_SIZE) & M_CPL0_SIZE)
4704 #define V_CPL1_SIZE(x) ((x) << S_CPL1_SIZE)
4705 #define G_CPL1_SIZE(x) (((x) >> S_CPL1_SIZE) & M_CPL1_SIZE)
4708 #define V_SIZE_LATCH_CLR(x) ((x) << S_SIZE_LATCH_CLR)
4709 #define F_SIZE_LATCH_CLR    V_SIZE_LATCH_CLR(1U)
4712 #define V_EXT_LATCH_CLR(x) ((x) << S_EXT_LATCH_CLR)
4713 #define F_EXT_LATCH_CLR    V_EXT_LATCH_CLR(1U)
4715 #define S_EXT_CHANGE_42875    1
4716 #define V_EXT_CHANGE_42875(x) ((x) << S_EXT_CHANGE_42875)
4717 #define F_EXT_CHANGE_42875    V_EXT_CHANGE_42875(1U)
4720 #define V_SIZE_CHANGE_42913(x) ((x) << S_SIZE_CHANGE_42913)
4721 #define F_SIZE_CHANGE_42913    V_SIZE_CHANGE_42913(1U)
4731 #define V_RDMA_INV_HANDLING(x) ((x) << S_RDMA_INV_HANDLING)
4732 #define G_RDMA_INV_HANDLING(x) (((x) >> S_RDMA_INV_HANDLING) & M_RDMA_INV_HANDLING)
4735 #define V_T7_TERMINATE_STATUS_EN(x) ((x) << S_T7_TERMINATE_STATUS_EN)
4736 #define F_T7_TERMINATE_STATUS_EN    V_T7_TERMINATE_STATUS_EN(1U)
4739 #define V_T7_DISABLE(x) ((x) << S_T7_DISABLE)
4740 #define F_T7_DISABLE    V_T7_DISABLE(1U)
4817 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
4818 #define F_INTXSTAT    V_INTXSTAT(1U)
4821 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
4822 #define F_AUXPWRPMEN    V_AUXPWRPMEN(1U)
4825 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
4826 #define F_NOSOFTRESET    V_NOSOFTRESET(1U)
4830 #define V_AIVEC(x) ((x) << S_AIVEC)
4831 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
4835 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
4836 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
4838 #define S_D3HOTEN    1
4839 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
4840 #define F_D3HOTEN    V_D3HOTEN(1U)
4843 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
4844 #define F_CLIDECEN    V_CLIDECEN(1U)
4851 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
4852 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
4858 #define V_OFFSET(x) ((x) << S_OFFSET)
4859 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
4864 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
4865 #define F_NONFATALERR    V_NONFATALERR(1U)
4868 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
4869 #define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)
4872 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
4873 #define F_PCIEPINT    V_PCIEPINT(1U)
4876 #define V_PCIESINT(x) ((x) << S_PCIESINT)
4877 #define F_PCIESINT    V_PCIESINT(1U)
4880 #define V_RPLPERR(x) ((x) << S_RPLPERR)
4881 #define F_RPLPERR    V_RPLPERR(1U)
4884 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
4885 #define F_RXWRPERR    V_RXWRPERR(1U)
4888 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
4889 #define F_RXCPLPERR    V_RXCPLPERR(1U)
4892 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
4893 #define F_PIOTAGPERR    V_PIOTAGPERR(1U)
4896 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
4897 #define F_MATAGPERR    V_MATAGPERR(1U)
4900 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
4901 #define F_INTXCLRPERR    V_INTXCLRPERR(1U)
4904 #define V_FIDPERR(x) ((x) << S_FIDPERR)
4905 #define F_FIDPERR    V_FIDPERR(1U)
4908 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
4909 #define F_CFGSNPPERR    V_CFGSNPPERR(1U)
4912 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
4913 #define F_HRSPPERR    V_HRSPPERR(1U)
4916 #define V_HREQPERR(x) ((x) << S_HREQPERR)
4917 #define F_HREQPERR    V_HREQPERR(1U)
4920 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
4921 #define F_HCNTPERR    V_HCNTPERR(1U)
4924 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
4925 #define F_DRSPPERR    V_DRSPPERR(1U)
4928 #define V_DREQPERR(x) ((x) << S_DREQPERR)
4929 #define F_DREQPERR    V_DREQPERR(1U)
4932 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
4933 #define F_DCNTPERR    V_DCNTPERR(1U)
4936 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
4937 #define F_CRSPPERR    V_CRSPPERR(1U)
4940 #define V_CREQPERR(x) ((x) << S_CREQPERR)
4941 #define F_CREQPERR    V_CREQPERR(1U)
4944 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
4945 #define F_CCNTPERR    V_CCNTPERR(1U)
4948 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
4949 #define F_TARTAGPERR    V_TARTAGPERR(1U)
4952 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
4953 #define F_PIOREQPERR    V_PIOREQPERR(1U)
4956 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
4957 #define F_PIOCPLPERR    V_PIOCPLPERR(1U)
4960 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
4961 #define F_MSIXDIPERR    V_MSIXDIPERR(1U)
4964 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
4965 #define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)
4968 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
4969 #define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)
4972 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
4973 #define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)
4976 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
4977 #define F_MSIDATAPERR    V_MSIDATAPERR(1U)
4979 #define S_MSIADDRHPERR    1
4980 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
4981 #define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)
4984 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
4985 #define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)
4988 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
4989 #define F_IPGRPPERR    V_IPGRPPERR(1U)
4992 #define V_READRSPERR(x) ((x) << S_READRSPERR)
4993 #define F_READRSPERR    V_READRSPERR(1U)
4996 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
4997 #define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)
5000 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
5001 #define F_IPSOTPERR    V_IPSOTPERR(1U)
5004 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
5005 #define F_IPRETRYPERR    V_IPRETRYPERR(1U)
5008 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
5009 #define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)
5012 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
5013 #define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)
5016 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
5017 #define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)
5020 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
5021 #define F_MAGRPPERR    V_MAGRPPERR(1U)
5024 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
5025 #define F_VFIDPERR    V_VFIDPERR(1U)
5028 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
5029 #define F_HREQRDPERR    V_HREQRDPERR(1U)
5032 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
5033 #define F_HREQWRPERR    V_HREQWRPERR(1U)
5036 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
5037 #define F_DREQRDPERR    V_DREQRDPERR(1U)
5040 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
5041 #define F_DREQWRPERR    V_DREQWRPERR(1U)
5044 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
5045 #define F_CREQRDPERR    V_CREQRDPERR(1U)
5048 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
5049 #define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)
5052 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
5053 #define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)
5056 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
5057 #define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)
5060 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
5061 #define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)
5064 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
5065 #define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)
5067 #define S_MSTTIMEOUTPERR    1
5068 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
5069 #define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)
5072 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
5073 #define F_MSTGRPPERR    V_MSTGRPPERR(1U)
5079 #define V_TGTTAGQCLIENT1PERR(x) ((x) << S_TGTTAGQCLIENT1PERR)
5080 #define F_TGTTAGQCLIENT1PERR    V_TGTTAGQCLIENT1PERR(1U)
5085 #define V_IDE(x) ((x) << S_IDE)
5086 #define F_IDE    V_IDE(1U)
5088 #define S_MEMSEL_PCIE    1
5090 #define V_MEMSEL_PCIE(x) ((x) << S_MEMSEL_PCIE)
5091 #define G_MEMSEL_PCIE(x) (((x) >> S_MEMSEL_PCIE) & M_MEMSEL_PCIE)
5096 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
5097 #define F_RDRSPERR    V_RDRSPERR(1U)
5100 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
5101 #define F_VPDRSPERR    V_VPDRSPERR(1U)
5104 #define V_POPD(x) ((x) << S_POPD)
5105 #define F_POPD    V_POPD(1U)
5108 #define V_POPH(x) ((x) << S_POPH)
5109 #define F_POPH    V_POPH(1U)
5112 #define V_POPC(x) ((x) << S_POPC)
5113 #define F_POPC    V_POPC(1U)
5116 #define V_MEMREQ(x) ((x) << S_MEMREQ)
5117 #define F_MEMREQ    V_MEMREQ(1U)
5120 #define V_PIOREQ(x) ((x) << S_PIOREQ)
5121 #define F_PIOREQ    V_PIOREQ(1U)
5124 #define V_TAGDROP(x) ((x) << S_TAGDROP)
5125 #define F_TAGDROP    V_TAGDROP(1U)
5127 #define S_TAGCPL    1
5128 #define V_TAGCPL(x) ((x) << S_TAGCPL)
5129 #define F_TAGCPL    V_TAGCPL(1U)
5132 #define V_CFGSNP(x) ((x) << S_CFGSNP)
5133 #define F_CFGSNP    V_CFGSNP(1U)
5136 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
5137 #define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)
5140 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
5141 #define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)
5144 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
5145 #define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)
5148 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
5149 #define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)
5152 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
5153 #define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)
5156 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
5157 #define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)
5160 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
5161 #define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)
5164 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
5165 #define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)
5168 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
5169 #define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)
5172 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
5173 #define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)
5176 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
5177 #define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)
5180 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
5181 #define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)
5184 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
5185 #define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)
5188 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
5189 #define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)
5192 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
5193 #define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)
5196 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
5197 #define F_DBITIMEOUT    V_DBITIMEOUT(1U)
5200 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
5201 #define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)
5204 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
5205 #define F_BAR2RDERR    V_BAR2RDERR(1U)
5208 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
5209 #define F_MAWREOPERR    V_MAWREOPERR(1U)
5212 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
5213 #define F_MARDEOPERR    V_MARDEOPERR(1U)
5216 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
5217 #define F_BAR2REQ    V_BAR2REQ(1U)
5220 #define V_MARSPUE(x) ((x) << S_MARSPUE)
5221 #define F_MARSPUE    V_MARSPUE(1U)
5224 #define V_KDBEOPERR(x) ((x) << S_KDBEOPERR)
5225 #define F_KDBEOPERR    V_KDBEOPERR(1U)
5231 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
5232 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
5236 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
5237 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
5241 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
5242 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
5245 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
5246 #define F_MASYNCEN    V_MASYNCEN(1U)
5249 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
5250 #define F_DCAENDMA    V_DCAENDMA(1U)
5253 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
5254 #define F_DCAENCMD    V_DCAENCMD(1U)
5257 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
5258 #define F_VFMSIPNDEN    V_VFMSIPNDEN(1U)
5261 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
5262 #define F_FORCETXERROR    V_FORCETXERROR(1U)
5265 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
5266 #define F_VPDREQPROTECT    V_VPDREQPROTECT(1U)
5269 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
5270 #define F_FIDTABLEINVALID    V_FIDTABLEINVALID(1U)
5273 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
5274 #define F_BYPASSMSIXCACHE    V_BYPASSMSIXCACHE(1U)
5277 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
5278 #define F_BYPASSMSICACHE    V_BYPASSMSICACHE(1U)
5281 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
5282 #define F_SIMSPEED    V_SIMSPEED(1U)
5285 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
5286 #define F_TC0_STAMP    V_TC0_STAMP(1U)
5290 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
5291 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
5294 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
5295 #define F_DMASTOPEN    V_DMASTOPEN(1U)
5298 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
5299 #define F_DEVSTATERSTMODE    V_DEVSTATERSTMODE(1U)
5302 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
5303 #define F_HOTRSTPCIECRSTMODE    V_HOTRSTPCIECRSTMODE(1U)
5306 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
5307 #define F_DLDNPCIECRSTMODE    V_DLDNPCIECRSTMODE(1U)
5309 #define S_DLDNPCIEPRECRSTMODE    1
5310 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
5311 #define F_DLDNPCIEPRECRSTMODE    V_DLDNPCIEPRECRSTMODE(1U)
5314 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
5315 #define F_LINKDNRSTEN    V_LINKDNRSTEN(1U)
5318 #define V_T5_PIOSTOPEN(x) ((x) << S_T5_PIOSTOPEN)
5319 #define F_T5_PIOSTOPEN    V_T5_PIOSTOPEN(1U)
5323 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
5324 #define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
5327 #define V_IPPERREN(x) ((x) << S_IPPERREN)
5328 #define F_IPPERREN    V_IPPERREN(1U)
5331 #define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
5332 #define F_CFGDEXTTAGEN    V_CFGDEXTTAGEN(1U)
5336 #define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
5337 #define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
5340 #define V_DCAEN(x) ((x) << S_DCAEN)
5341 #define F_DCAEN    V_DCAEN(1U)
5344 #define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
5345 #define F_T5CMDREQPRIORITY    V_T5CMDREQPRIORITY(1U)
5349 #define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
5350 #define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
5353 #define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
5354 #define F_DROPPEDRDRSPDATA    V_DROPPEDRDRSPDATA(1U)
5357 #define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
5358 #define F_AI_INTX_REASSERTEN    V_AI_INTX_REASSERTEN(1U)
5361 #define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
5362 #define F_AUTOTXNDISABLE    V_AUTOTXNDISABLE(1U)
5365 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
5366 #define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
5371 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
5372 #define F_LITTLEENDIAN    V_LITTLEENDIAN(1U)
5378 #define V_VPDTIMER(x) ((x) << S_VPDTIMER)
5379 #define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
5383 #define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
5384 #define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
5387 #define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
5388 #define F_MSTREQRDRRASIMPLE    V_MSTREQRDRRASIMPLE(1U)
5392 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
5393 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
5397 #define V_T6_TOTMAXTAG(x) ((x) << S_T6_TOTMAXTAG)
5398 #define G_T6_TOTMAXTAG(x) (((x) >> S_T6_TOTMAXTAG) & M_T6_TOTMAXTAG)
5401 #define V_REG_VDM_ONLY(x) ((x) << S_REG_VDM_ONLY)
5402 #define F_REG_VDM_ONLY    V_REG_VDM_ONLY(1U)
5405 #define V_MULT_REQID_SUP(x) ((x) << S_MULT_REQID_SUP)
5406 #define F_MULT_REQID_SUP    V_MULT_REQID_SUP(1U)
5412 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
5413 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
5417 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
5418 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
5422 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
5423 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
5427 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
5428 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
5432 #define V_MAXTAG(x) ((x) << S_MAXTAG)
5433 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
5438 #define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
5439 #define F_AUTOPIOCOOKIEMATCH    V_AUTOPIOCOOKIEMATCH(1U)
5443 #define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
5444 #define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
5447 #define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
5448 #define F_HMADCASTFIRSTONLY    V_HMADCASTFIRSTONLY(1U)
5450 #define S_CMDDCASTFIRSTONLY    1
5451 #define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
5452 #define F_CMDDCASTFIRSTONLY    V_CMDDCASTFIRSTONLY(1U)
5455 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
5456 #define F_DMADCASTFIRSTONLY    V_DMADCASTFIRSTONLY(1U)
5459 #define V_ARMDCASTFIRSTONLY(x) ((x) << S_ARMDCASTFIRSTONLY)
5460 #define F_ARMDCASTFIRSTONLY    V_ARMDCASTFIRSTONLY(1U)
5466 #define V_STATEREQ(x) ((x) << S_STATEREQ)
5467 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
5471 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
5472 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
5476 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
5477 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
5480 #define V_TAGFREE(x) ((x) << S_TAGFREE)
5481 #define F_TAGFREE    V_TAGFREE(1U)
5485 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
5486 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
5491 #define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
5492 #define F_L1CLKREMOVALEN    V_L1CLKREMOVALEN(1U)
5495 #define V_READYENTERL23(x) ((x) << S_READYENTERL23)
5496 #define F_READYENTERL23    V_READYENTERL23(1U)
5499 #define V_EXITL1(x) ((x) << S_EXITL1)
5500 #define F_EXITL1    V_EXITL1(1U)
5503 #define V_ENTERL1(x) ((x) << S_ENTERL1)
5504 #define F_ENTERL1    V_ENTERL1(1U)
5508 #define V_GENPME(x) ((x) << S_GENPME)
5509 #define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
5514 #define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
5515 #define F_ENABLESKPPARITYFIX    V_ENABLESKPPARITYFIX(1U)
5517 #define S_ENABLEL2ENTRYINL1    1
5518 #define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
5519 #define F_ENABLEL2ENTRYINL1    V_ENABLEL2ENTRYINL1(1U)
5522 #define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
5523 #define F_HOLDCPLENTERINGL1    V_HOLDCPLENTERINGL1(1U)
5529 #define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
5530 #define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
5533 #define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
5534 #define F_PERSTTIMEOUT    V_PERSTTIMEOUT(1U)
5538 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
5539 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
5545 #define V_TCAMRSPERR(x) ((x) << S_TCAMRSPERR)
5546 #define F_TCAMRSPERR    V_TCAMRSPERR(1U)
5549 #define V_IPFORMQPERR(x) ((x) << S_IPFORMQPERR)
5550 #define F_IPFORMQPERR    V_IPFORMQPERR(1U)
5553 #define V_IPFORMQCERR(x) ((x) << S_IPFORMQCERR)
5554 #define F_IPFORMQCERR    V_IPFORMQCERR(1U)
5557 #define V_TRGT1GRPCERR(x) ((x) << S_TRGT1GRPCERR)
5558 #define F_TRGT1GRPCERR    V_TRGT1GRPCERR(1U)
5561 #define V_IPSOTCERR(x) ((x) << S_IPSOTCERR)
5562 #define F_IPSOTCERR    V_IPSOTCERR(1U)
5565 #define V_IPRETRYCERR(x) ((x) << S_IPRETRYCERR)
5566 #define F_IPRETRYCERR    V_IPRETRYCERR(1U)
5569 #define V_IPRXDATAGRPCERR(x) ((x) << S_IPRXDATAGRPCERR)
5570 #define F_IPRXDATAGRPCERR    V_IPRXDATAGRPCERR(1U)
5573 #define V_IPRXHDRGRPCERR(x) ((x) << S_IPRXHDRGRPCERR)
5574 #define F_IPRXHDRGRPCERR    V_IPRXHDRGRPCERR(1U)
5577 #define V_A0ARBRSPORDFIFOPERR(x) ((x) << S_A0ARBRSPORDFIFOPERR)
5578 #define F_A0ARBRSPORDFIFOPERR    V_A0ARBRSPORDFIFOPERR(1U)
5581 #define V_HRSPCERR(x) ((x) << S_HRSPCERR)
5582 #define F_HRSPCERR    V_HRSPCERR(1U)
5585 #define V_HREQRDCERR(x) ((x) << S_HREQRDCERR)
5586 #define F_HREQRDCERR    V_HREQRDCERR(1U)
5589 #define V_HREQWRCERR(x) ((x) << S_HREQWRCERR)
5590 #define F_HREQWRCERR    V_HREQWRCERR(1U)
5593 #define V_DRSPCERR(x) ((x) << S_DRSPCERR)
5594 #define F_DRSPCERR    V_DRSPCERR(1U)
5597 #define V_DREQRDCERR(x) ((x) << S_DREQRDCERR)
5598 #define F_DREQRDCERR    V_DREQRDCERR(1U)
5601 #define V_DREQWRCERR(x) ((x) << S_DREQWRCERR)
5602 #define F_DREQWRCERR    V_DREQWRCERR(1U)
5605 #define V_CRSPCERR(x) ((x) << S_CRSPCERR)
5606 #define F_CRSPCERR    V_CRSPCERR(1U)
5609 #define V_ARSPPERR(x) ((x) << S_ARSPPERR)
5610 #define F_ARSPPERR    V_ARSPPERR(1U)
5613 #define V_AREQRDPERR(x) ((x) << S_AREQRDPERR)
5614 #define F_AREQRDPERR    V_AREQRDPERR(1U)
5617 #define V_AREQWRPERR(x) ((x) << S_AREQWRPERR)
5618 #define F_AREQWRPERR    V_AREQWRPERR(1U)
5621 #define V_PIOREQGRPCERR(x) ((x) << S_PIOREQGRPCERR)
5622 #define F_PIOREQGRPCERR    V_PIOREQGRPCERR(1U)
5625 #define V_ARSPCERR(x) ((x) << S_ARSPCERR)
5626 #define F_ARSPCERR    V_ARSPCERR(1U)
5629 #define V_AREQRDCERR(x) ((x) << S_AREQRDCERR)
5630 #define F_AREQRDCERR    V_AREQRDCERR(1U)
5633 #define V_AREQWRCERR(x) ((x) << S_AREQWRCERR)
5634 #define F_AREQWRCERR    V_AREQWRCERR(1U)
5637 #define V_MARSPPERR(x) ((x) << S_MARSPPERR)
5638 #define F_MARSPPERR    V_MARSPPERR(1U)
5641 #define V_INICMAWDATAORDPERR(x) ((x) << S_INICMAWDATAORDPERR)
5642 #define F_INICMAWDATAORDPERR    V_INICMAWDATAORDPERR(1U)
5645 #define V_EMUPERR(x) ((x) << S_EMUPERR)
5646 #define F_EMUPERR    V_EMUPERR(1U)
5648 #define S_ERRSPPERR    1
5649 #define V_ERRSPPERR(x) ((x) << S_ERRSPPERR)
5650 #define F_ERRSPPERR    V_ERRSPPERR(1U)
5653 #define V_MSTGRPCERR(x) ((x) << S_MSTGRPCERR)
5654 #define F_MSTGRPCERR    V_MSTGRPCERR(1U)
5659 #define V_X8TGTGRPPERR(x) ((x) << S_X8TGTGRPPERR)
5660 #define F_X8TGTGRPPERR    V_X8TGTGRPPERR(1U)
5663 #define V_X8IPSOTPERR(x) ((x) << S_X8IPSOTPERR)
5664 #define F_X8IPSOTPERR    V_X8IPSOTPERR(1U)
5667 #define V_X8IPRETRYPERR(x) ((x) << S_X8IPRETRYPERR)
5668 #define F_X8IPRETRYPERR    V_X8IPRETRYPERR(1U)
5671 #define V_X8IPRXDATAGRPPERR(x) ((x) << S_X8IPRXDATAGRPPERR)
5672 #define F_X8IPRXDATAGRPPERR    V_X8IPRXDATAGRPPERR(1U)
5675 #define V_X8IPRXHDRGRPPERR(x) ((x) << S_X8IPRXHDRGRPPERR)
5676 #define F_X8IPRXHDRGRPPERR    V_X8IPRXHDRGRPPERR(1U)
5679 #define V_X8IPCORECERR(x) ((x) << S_X8IPCORECERR)
5680 #define F_X8IPCORECERR    V_X8IPCORECERR(1U)
5683 #define V_X8MSTGRPPERR(x) ((x) << S_X8MSTGRPPERR)
5684 #define F_X8MSTGRPPERR    V_X8MSTGRPPERR(1U)
5686 #define S_X8MSTGRPCERR    1
5687 #define V_X8MSTGRPCERR(x) ((x) << S_X8MSTGRPCERR)
5688 #define F_X8MSTGRPCERR    V_X8MSTGRPCERR(1U)
5697 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
5698 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
5702 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
5703 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
5708 #define V_T7_ARSPPERR(x) ((x) << S_T7_ARSPPERR)
5709 #define F_T7_ARSPPERR    V_T7_ARSPPERR(1U)
5712 #define V_T7_AREQRDPERR(x) ((x) << S_T7_AREQRDPERR)
5713 #define F_T7_AREQRDPERR    V_T7_AREQRDPERR(1U)
5716 #define V_T7_AREQWRPERR(x) ((x) << S_T7_AREQWRPERR)
5717 #define F_T7_AREQWRPERR    V_T7_AREQWRPERR(1U)
5720 #define V_T7_A0ARBRSPORDFIFOPERR(x) ((x) << S_T7_A0ARBRSPORDFIFOPERR)
5721 #define F_T7_A0ARBRSPORDFIFOPERR    V_T7_A0ARBRSPORDFIFOPERR(1U)
5724 #define V_T7_MARSPPERR(x) ((x) << S_T7_MARSPPERR)
5725 #define F_T7_MARSPPERR    V_T7_MARSPPERR(1U)
5728 #define V_T7_INICMAWDATAORDPERR(x) ((x) << S_T7_INICMAWDATAORDPERR)
5729 #define F_T7_INICMAWDATAORDPERR    V_T7_INICMAWDATAORDPERR(1U)
5732 #define V_T7_EMUPERR(x) ((x) << S_T7_EMUPERR)
5733 #define F_T7_EMUPERR    V_T7_EMUPERR(1U)
5736 #define V_T7_ERRSPPERR(x) ((x) << S_T7_ERRSPPERR)
5737 #define F_T7_ERRSPPERR    V_T7_ERRSPPERR(1U)
5743 #define V_RSPCNT(x) ((x) << S_RSPCNT)
5744 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
5748 #define V_REQCNT(x) ((x) << S_REQCNT)
5749 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
5754 #define V_T7_X8TGTGRPPERR(x) ((x) << S_T7_X8TGTGRPPERR)
5755 #define F_T7_X8TGTGRPPERR    V_T7_X8TGTGRPPERR(1U)
5758 #define V_T7_X8IPSOTPERR(x) ((x) << S_T7_X8IPSOTPERR)
5759 #define F_T7_X8IPSOTPERR    V_T7_X8IPSOTPERR(1U)
5762 #define V_T7_X8IPRETRYPERR(x) ((x) << S_T7_X8IPRETRYPERR)
5763 #define F_T7_X8IPRETRYPERR    V_T7_X8IPRETRYPERR(1U)
5766 #define V_T7_X8IPRXDATAGRPPERR(x) ((x) << S_T7_X8IPRXDATAGRPPERR)
5767 #define F_T7_X8IPRXDATAGRPPERR    V_T7_X8IPRXDATAGRPPERR(1U)
5770 #define V_T7_X8IPRXHDRGRPPERR(x) ((x) << S_T7_X8IPRXHDRGRPPERR)
5771 #define F_T7_X8IPRXHDRGRPPERR    V_T7_X8IPRXHDRGRPPERR(1U)
5774 #define V_T7_X8MSTGRPPERR(x) ((x) << S_T7_X8MSTGRPPERR)
5775 #define F_T7_X8MSTGRPPERR    V_T7_X8MSTGRPPERR(1U)
5781 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
5782 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
5786 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
5787 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
5793 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
5794 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
5800 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
5801 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
5807 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
5808 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
5811 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
5812 #define F_PIOSTOPEN    V_PIOSTOPEN(1U)
5815 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
5816 #define F_IPLANESWAP    V_IPLANESWAP(1U)
5819 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
5820 #define F_FORCESTRICTTS1    V_FORCESTRICTTS1(1U)
5824 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
5825 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
5830 #define V_ENABLE(x) ((x) << S_ENABLE)
5831 #define F_ENABLE    V_ENABLE(1U)
5834 #define V_AI(x) ((x) << S_AI)
5835 #define F_AI    V_AI(1U)
5838 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
5839 #define F_LOCALCFG    V_LOCALCFG(1U)
5843 #define V_BUS(x) ((x) << S_BUS)
5844 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
5848 #define V_DEVICE(x) ((x) << S_DEVICE)
5849 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
5853 #define V_FUNCTION(x) ((x) << S_FUNCTION)
5854 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
5858 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
5859 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
5863 #define V_REGISTER(x) ((x) << S_REGISTER)
5864 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
5867 #define V_CS2(x) ((x) << S_CS2)
5868 #define F_CS2    V_CS2(1U)
5872 #define V_WRBE(x) ((x) << S_WRBE)
5873 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
5876 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
5877 #define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)
5881 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
5882 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
5886 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
5887 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
5890 #define V_T6_ENABLE(x) ((x) << S_T6_ENABLE)
5891 #define F_T6_ENABLE    V_T6_ENABLE(1U)
5894 #define V_T6_1_AI(x) ((x) << S_T6_1_AI)
5895 #define F_T6_1_AI    V_T6_1_AI(1U)
5898 #define V_T6_CS2(x) ((x) << S_T6_CS2)
5899 #define F_T6_CS2    V_T6_CS2(1U)
5903 #define V_T6_WRBE(x) ((x) << S_T6_WRBE)
5904 #define G_T6_WRBE(x) (((x) >> S_T6_WRBE) & M_T6_WRBE)
5907 #define V_T6_CFG_SPACE_VFVLD(x) ((x) << S_T6_CFG_SPACE_VFVLD)
5908 #define F_T6_CFG_SPACE_VFVLD    V_T6_CFG_SPACE_VFVLD(1U)
5912 #define V_T6_CFG_SPACE_RVF(x) ((x) << S_T6_CFG_SPACE_RVF)
5913 #define G_T6_CFG_SPACE_RVF(x) (((x) >> S_T6_CFG_SPACE_RVF) & M_T6_CFG_SPACE_RVF)
5920 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
5921 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
5925 #define V_BIR(x) ((x) << S_BIR)
5926 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
5930 #define V_WINDOW(x) ((x) << S_WINDOW)
5931 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
5937 #define V_MEMOFST(x) ((x) << S_MEMOFST)
5938 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
5945 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
5946 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
5950 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
5951 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
5955 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
5956 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
5962 #define V_MEMOFST0(x) ((x) << S_MEMOFST0)
5963 #define G_MEMOFST0(x) (((x) >> S_MEMOFST0) & M_MEMOFST0)
5970 #define V_MEMOFST1(x) ((x) << S_MEMOFST1)
5971 #define G_MEMOFST1(x) (((x) >> S_MEMOFST1) & M_MEMOFST1)
5976 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
5977 #define F_MA_TAGFREE    V_MA_TAGFREE(1U)
5981 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
5982 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
5986 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
5987 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
5990 #define V_MA_LE(x) ((x) << S_MA_LE)
5991 #define F_MA_LE    V_MA_LE(1U)
5995 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
5996 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
6000 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
6001 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
6005 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
6006 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
6010 #define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
6011 #define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
6015 #define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
6016 #define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
6024 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
6025 #define F_PIOPAUSEDONE    V_PIOPAUSEDONE(1U)
6029 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
6030 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
6033 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
6034 #define F_PIOPAUSE    V_PIOPAUSE(1U)
6037 #define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
6038 #define F_MSTPAUSEDONE    V_MSTPAUSEDONE(1U)
6040 #define S_MSTPAUSE    1
6041 #define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
6042 #define F_MSTPAUSE    V_MSTPAUSE(1U)
6049 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
6050 #define F_LINKDOWN_RESET_EN    V_LINKDOWN_RESET_EN(1U)
6053 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
6054 #define F_IN_WR_DISCONTIG    V_IN_WR_DISCONTIG(1U)
6058 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
6059 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
6063 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
6064 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
6068 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
6069 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
6073 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
6074 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
6078 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
6079 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
6083 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
6084 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
6088 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
6089 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
6093 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
6094 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
6098 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
6099 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
6102 #define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
6103 #define F_AUXPOWER_DETECTED    V_AUXPOWER_DETECTED(1U)
6109 #define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
6110 #define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
6114 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
6115 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
6119 #define V_T7_STATIC_SPARE3(x) ((x) << S_T7_STATIC_SPARE3)
6120 #define G_T7_STATIC_SPARE3(x) (((x) >> S_T7_STATIC_SPARE3) & M_T7_STATIC_SPARE3)
6125 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
6126 #define F_DBGENABLE    V_DBGENABLE(1U)
6129 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
6130 #define F_DBGAUTOINC    V_DBGAUTOINC(1U)
6134 #define V_POINTER(x) ((x) << S_POINTER)
6135 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
6139 #define V_SELECT(x) ((x) << S_SELECT)
6140 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
6150 #define V_PBAOFST(x) ((x) << S_PBAOFST)
6151 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
6155 #define V_TABOFST(x) ((x) << S_TABOFST)
6156 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
6160 #define V_VECNUM(x) ((x) << S_VECNUM)
6161 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
6165 #define V_VECBASE(x) ((x) << S_VECBASE)
6166 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
6171 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
6172 #define F_SENDFLRRSP    V_SENDFLRRSP(1U)
6175 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
6176 #define F_IMMFLRRSP    V_IMMFLRRSP(1U)
6179 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
6180 #define F_TXNDISABLE    V_TXNDISABLE(1U)
6184 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
6185 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
6188 #define V_VFVLD(x) ((x) << S_VFVLD)
6189 #define F_VFVLD    V_VFVLD(1U)
6193 #define V_PFNUM(x) ((x) << S_PFNUM)
6194 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
6200 #define V_T7_VECNUM(x) ((x) << S_T7_VECNUM)
6201 #define G_T7_VECNUM(x) (((x) >> S_T7_VECNUM) & M_T7_VECNUM)
6205 #define V_T7_VECBASE(x) ((x) << S_T7_VECBASE)
6206 #define G_T7_VECBASE(x) (((x) >> S_T7_VECBASE) & M_T7_VECBASE)
6215 #define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
6216 #define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
6226 #define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
6227 #define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
6237 #define V_T7_WRITE(x) ((x) << S_T7_WRITE)
6238 #define F_T7_WRITE    V_T7_WRITE(1U)
6244 #define V_T7_ADDR(x) ((x) << S_T7_ADDR)
6245 #define G_T7_ADDR(x) (((x) >> S_T7_ADDR) & M_T7_ADDR)
6251 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
6252 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
6257 #define V_FID_VFID_NVMEGROUPEN(x) ((x) << S_FID_VFID_NVMEGROUPEN)
6258 #define F_FID_VFID_NVMEGROUPEN    V_FID_VFID_NVMEGROUPEN(1U)
6262 #define V_FID_VFID_GROUPSEL(x) ((x) << S_FID_VFID_GROUPSEL)
6263 #define G_FID_VFID_GROUPSEL(x) (((x) >> S_FID_VFID_GROUPSEL) & M_FID_VFID_GROUPSEL)
6269 #define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
6270 #define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
6273 #define V_IDO(x) ((x) << S_IDO)
6274 #define F_IDO    V_IDO(1U)
6278 #define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
6279 #define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
6283 #define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
6284 #define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
6287 #define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
6288 #define F_FID_VFID_VFVLD    V_FID_VFID_VFVLD(1U)
6292 #define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
6293 #define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
6297 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
6298 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
6302 #define V_T6_FID_VFID_VFID(x) ((x) << S_T6_FID_VFID_VFID)
6303 #define G_T6_FID_VFID_VFID(x) (((x) >> S_T6_FID_VFID_VFID) & M_T6_FID_VFID_VFID)
6307 #define V_T6_FID_VFID_TC(x) ((x) << S_T6_FID_VFID_TC)
6308 #define G_T6_FID_VFID_TC(x) (((x) >> S_T6_FID_VFID_TC) & M_T6_FID_VFID_TC)
6311 #define V_T6_FID_VFID_VFVLD(x) ((x) << S_T6_FID_VFID_VFVLD)
6312 #define F_T6_FID_VFID_VFVLD    V_T6_FID_VFID_VFVLD(1U)
6316 #define V_T6_FID_VFID_PF(x) ((x) << S_T6_FID_VFID_PF)
6317 #define G_T6_FID_VFID_PF(x) (((x) >> S_T6_FID_VFID_PF) & M_T6_FID_VFID_PF)
6321 #define V_T6_FID_VFID_RVF(x) ((x) << S_T6_FID_VFID_RVF)
6322 #define G_T6_FID_VFID_RVF(x) (((x) >> S_T6_FID_VFID_RVF) & M_T6_FID_VFID_RVF)
6329 #define V_NVMEDISABLE(x) ((x) << S_NVMEDISABLE)
6330 #define F_NVMEDISABLE    V_NVMEDISABLE(1U)
6334 #define V_NVMELENGTH(x) ((x) << S_NVMELENGTH)
6335 #define G_NVMELENGTH(x) (((x) >> S_NVMELENGTH) & M_NVMELENGTH)
6341 #define V_NVMEGROUPSEL(x) ((x) << S_NVMEGROUPSEL)
6342 #define G_NVMEGROUPSEL(x) (((x) >> S_NVMEGROUPSEL) & M_NVMEGROUPSEL)
6349 #define V_PCIEOFST1(x) ((x) << S_PCIEOFST1)
6350 #define G_PCIEOFST1(x) (((x) >> S_PCIEOFST1) & M_PCIEOFST1)
6356 #define S_PTM_AUTO_UPDATE    1
6357 #define V_PTM_AUTO_UPDATE(x) ((x) << S_PTM_AUTO_UPDATE)
6358 #define F_PTM_AUTO_UPDATE    V_PTM_AUTO_UPDATE(1U)
6361 #define V_PTM_EXT_STROBE(x) ((x) << S_PTM_EXT_STROBE)
6362 #define F_PTM_EXT_STROBE    V_PTM_EXT_STROBE(1U)
6369 #define V_PTM_MAN_UPD_PULSE(x) ((x) << S_PTM_MAN_UPD_PULSE)
6370 #define F_PTM_MAN_UPD_PULSE    V_PTM_MAN_UPD_PULSE(1U)
6376 #define V_PERST(x) ((x) << S_PERST)
6377 #define F_PERST    V_PERST(1U)
6383 #define V_DS8_SEL(x) ((x) << S_DS8_SEL)
6384 #define G_DS8_SEL(x) (((x) >> S_DS8_SEL) & M_DS8_SEL)
6388 #define V_DS7_SEL(x) ((x) << S_DS7_SEL)
6389 #define G_DS7_SEL(x) (((x) >> S_DS7_SEL) & M_DS7_SEL)
6393 #define V_DS6_SEL(x) ((x) << S_DS6_SEL)
6394 #define G_DS6_SEL(x) (((x) >> S_DS6_SEL) & M_DS6_SEL)
6398 #define V_DS5_SEL(x) ((x) << S_DS5_SEL)
6399 #define G_DS5_SEL(x) (((x) >> S_DS5_SEL) & M_DS5_SEL)
6403 #define V_DS4_SEL(x) ((x) << S_DS4_SEL)
6404 #define G_DS4_SEL(x) (((x) >> S_DS4_SEL) & M_DS4_SEL)
6408 #define V_DS3_SEL(x) ((x) << S_DS3_SEL)
6409 #define G_DS3_SEL(x) (((x) >> S_DS3_SEL) & M_DS3_SEL)
6413 #define V_DS2_SEL(x) ((x) << S_DS2_SEL)
6414 #define G_DS2_SEL(x) (((x) >> S_DS2_SEL) & M_DS2_SEL)
6418 #define V_DS1_SEL(x) ((x) << S_DS1_SEL)
6419 #define G_DS1_SEL(x) (((x) >> S_DS1_SEL) & M_DS1_SEL)
6423 #define V_LN14_SEL(x) ((x) << S_LN14_SEL)
6424 #define G_LN14_SEL(x) (((x) >> S_LN14_SEL) & M_LN14_SEL)
6428 #define V_LN12_SEL(x) ((x) << S_LN12_SEL)
6429 #define G_LN12_SEL(x) (((x) >> S_LN12_SEL) & M_LN12_SEL)
6433 #define V_LN10_SEL(x) ((x) << S_LN10_SEL)
6434 #define G_LN10_SEL(x) (((x) >> S_LN10_SEL) & M_LN10_SEL)
6438 #define V_LN8_SEL(x) ((x) << S_LN8_SEL)
6439 #define G_LN8_SEL(x) (((x) >> S_LN8_SEL) & M_LN8_SEL)
6443 #define V_LN6_SEL(x) ((x) << S_LN6_SEL)
6444 #define G_LN6_SEL(x) (((x) >> S_LN6_SEL) & M_LN6_SEL)
6448 #define V_LN4_SEL(x) ((x) << S_LN4_SEL)
6449 #define G_LN4_SEL(x) (((x) >> S_LN4_SEL) & M_LN4_SEL)
6453 #define V_LN2_SEL(x) ((x) << S_LN2_SEL)
6454 #define G_LN2_SEL(x) (((x) >> S_LN2_SEL) & M_LN2_SEL)
6458 #define V_LN0_SEL(x) ((x) << S_LN0_SEL)
6459 #define G_LN0_SEL(x) (((x) >> S_LN0_SEL) & M_LN0_SEL)
6465 #define V_MSIX_ENABLE(x) ((x) << S_MSIX_ENABLE)
6466 #define G_MSIX_ENABLE(x) (((x) >> S_MSIX_ENABLE) & M_MSIX_ENABLE)
6472 #define V_WR_LFSR_CMP_DATA(x) ((x) << S_WR_LFSR_CMP_DATA)
6473 #define G_WR_LFSR_CMP_DATA(x) (((x) >> S_WR_LFSR_CMP_DATA) & M_WR_LFSR_CMP_DATA)
6477 #define V_WR_LFSR_RSVD(x) ((x) << S_WR_LFSR_RSVD)
6478 #define G_WR_LFSR_RSVD(x) (((x) >> S_WR_LFSR_RSVD) & M_WR_LFSR_RSVD)
6480 #define S_WR_LFSR_EN    1
6481 #define V_WR_LFSR_EN(x) ((x) << S_WR_LFSR_EN)
6482 #define F_WR_LFSR_EN    V_WR_LFSR_EN(1U)
6485 #define V_WR_LFSR_START(x) ((x) << S_WR_LFSR_START)
6486 #define F_WR_LFSR_START    V_WR_LFSR_START(1U)
6492 #define V_CMD_LFSR_CMP_DATA(x) ((x) << S_CMD_LFSR_CMP_DATA)
6493 #define G_CMD_LFSR_CMP_DATA(x) (((x) >> S_CMD_LFSR_CMP_DATA) & M_CMD_LFSR_CMP_DATA)
6497 #define V_RD_LFSR_CMD_DATA(x) ((x) << S_RD_LFSR_CMD_DATA)
6498 #define G_RD_LFSR_CMD_DATA(x) (((x) >> S_RD_LFSR_CMD_DATA) & M_RD_LFSR_CMD_DATA)
6502 #define V_RD_LFSR_RSVD(x) ((x) << S_RD_LFSR_RSVD)
6503 #define G_RD_LFSR_RSVD(x) (((x) >> S_RD_LFSR_RSVD) & M_RD_LFSR_RSVD)
6506 #define V_RD3_LFSR_EN(x) ((x) << S_RD3_LFSR_EN)
6507 #define F_RD3_LFSR_EN    V_RD3_LFSR_EN(1U)
6510 #define V_RD3_LFSR_START(x) ((x) << S_RD3_LFSR_START)
6511 #define F_RD3_LFSR_START    V_RD3_LFSR_START(1U)
6514 #define V_RD2_LFSR_EN(x) ((x) << S_RD2_LFSR_EN)
6515 #define F_RD2_LFSR_EN    V_RD2_LFSR_EN(1U)
6518 #define V_RD2_LFSR_START(x) ((x) << S_RD2_LFSR_START)
6519 #define F_RD2_LFSR_START    V_RD2_LFSR_START(1U)
6522 #define V_RD1_LFSR_EN(x) ((x) << S_RD1_LFSR_EN)
6523 #define F_RD1_LFSR_EN    V_RD1_LFSR_EN(1U)
6526 #define V_RD1_LFSR_START(x) ((x) << S_RD1_LFSR_START)
6527 #define F_RD1_LFSR_START    V_RD1_LFSR_START(1U)
6530 #define V_RD0_LFSR_EN(x) ((x) << S_RD0_LFSR_EN)
6531 #define F_RD0_LFSR_EN    V_RD0_LFSR_EN(1U)
6534 #define V_RD0_LFSR_START(x) ((x) << S_RD0_LFSR_START)
6535 #define F_RD0_LFSR_START    V_RD0_LFSR_START(1U)
6537 #define S_CMD_LFSR_EN    1
6538 #define V_CMD_LFSR_EN(x) ((x) << S_CMD_LFSR_EN)
6539 #define F_CMD_LFSR_EN    V_CMD_LFSR_EN(1U)
6542 #define V_CMD_LFSR_START(x) ((x) << S_CMD_LFSR_START)
6543 #define F_CMD_LFSR_START    V_CMD_LFSR_START(1U)
6548 #define V_PAD(x) ((x) << S_PAD)
6549 #define F_PAD    V_PAD(1U)
6553 #define V_TC(x) ((x) << S_TC)
6554 #define G_TC(x) (((x) >> S_TC) & M_TC)
6558 #define V_FUNC(x) ((x) << S_FUNC)
6559 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
6565 #define V_EMU_ADDR(x) ((x) << S_EMU_ADDR)
6566 #define G_EMU_ADDR(x) (((x) >> S_EMU_ADDR) & M_EMU_ADDR)
6571 #define V_EMUENABLE(x) ((x) << S_EMUENABLE)
6572 #define F_EMUENABLE    V_EMUENABLE(1U)
6576 #define V_EMUTYPE(x) ((x) << S_EMUTYPE)
6577 #define G_EMUTYPE(x) (((x) >> S_EMUTYPE) & M_EMUTYPE)
6581 #define V_BAR0TARGET(x) ((x) << S_BAR0TARGET)
6582 #define G_BAR0TARGET(x) (((x) >> S_BAR0TARGET) & M_BAR0TARGET)
6586 #define V_BAR2TARGET(x) ((x) << S_BAR2TARGET)
6587 #define G_BAR2TARGET(x) (((x) >> S_BAR2TARGET) & M_BAR2TARGET)
6591 #define V_BAR4TARGET(x) ((x) << S_BAR4TARGET)
6592 #define G_BAR4TARGET(x) (((x) >> S_BAR4TARGET) & M_BAR4TARGET)
6596 #define V_RELEATIVEEMUID(x) ((x) << S_RELEATIVEEMUID)
6597 #define G_RELEATIVEEMUID(x) (((x) >> S_RELEATIVEEMUID) & M_RELEATIVEEMUID)
6603 #define V_T7_MEMOFST0(x) ((x) << S_T7_MEMOFST0)
6604 #define G_T7_MEMOFST0(x) (((x) >> S_T7_MEMOFST0) & M_T7_MEMOFST0)
6610 #define V_SIZE0(x) ((x) << S_SIZE0)
6611 #define G_SIZE0(x) (((x) >> S_SIZE0) & M_SIZE0)
6617 #define V_T7_MEMOFST1(x) ((x) << S_T7_MEMOFST1)
6618 #define G_T7_MEMOFST1(x) (((x) >> S_T7_MEMOFST1) & M_T7_MEMOFST1)
6624 #define V_SIZE1(x) ((x) << S_SIZE1)
6625 #define G_SIZE1(x) (((x) >> S_SIZE1) & M_SIZE1)
6631 #define V_MEMOFST2(x) ((x) << S_MEMOFST2)
6632 #define G_MEMOFST2(x) (((x) >> S_MEMOFST2) & M_MEMOFST2)
6638 #define V_SIZE2(x) ((x) << S_SIZE2)
6639 #define G_SIZE2(x) (((x) >> S_SIZE2) & M_SIZE2)
6645 #define V_MEMOFST3(x) ((x) << S_MEMOFST3)
6646 #define G_MEMOFST3(x) (((x) >> S_MEMOFST3) & M_MEMOFST3)
6652 #define V_SIZE3(x) ((x) << S_SIZE3)
6653 #define G_SIZE3(x) (((x) >> S_SIZE3) & M_SIZE3)
6660 #define V_TCAMADDR(x) ((x) << S_TCAMADDR)
6661 #define G_TCAMADDR(x) (((x) >> S_TCAMADDR) & M_TCAMADDR)
6664 #define V_CAMEN(x) ((x) << S_CAMEN)
6665 #define F_CAMEN    V_CAMEN(1U)
6670 #define V_CBPASS(x) ((x) << S_CBPASS)
6671 #define F_CBPASS    V_CBPASS(1U)
6674 #define V_CBBUSY(x) ((x) << S_CBBUSY)
6675 #define F_CBBUSY    V_CBBUSY(1U)
6678 #define V_CBSTART(x) ((x) << S_CBSTART)
6679 #define F_CBSTART    V_CBSTART(1U)
6682 #define V_RSTCB(x) ((x) << S_RSTCB)
6683 #define F_RSTCB    V_RSTCB(1U)
6687 #define V_TCAM_DBG_DATA(x) ((x) << S_TCAM_DBG_DATA)
6688 #define G_TCAM_DBG_DATA(x) (((x) >> S_TCAM_DBG_DATA) & M_TCAM_DBG_DATA)
6739 #define V_MRS(x) ((x) << S_MRS)
6740 #define G_MRS(x) (((x) >> S_MRS) & M_MRS)
6744 #define V_T7_MPS(x) ((x) << S_T7_MPS)
6745 #define G_T7_MPS(x) (((x) >> S_T7_MPS) & M_T7_MPS)
6750 #define V_T7_DCAEN(x) ((x) << S_T7_DCAEN)
6751 #define F_T7_DCAEN    V_T7_DCAEN(1U)
6753 #define S_DCASTFITTRAONLEN    1
6754 #define V_DCASTFITTRAONLEN(x) ((x) << S_DCASTFITTRAONLEN)
6755 #define F_DCASTFITTRAONLEN    V_DCASTFITTRAONLEN(1U)
6758 #define V_REQCTLDYNSTCLKEN(x) ((x) << S_REQCTLDYNSTCLKEN)
6759 #define F_REQCTLDYNSTCLKEN    V_REQCTLDYNSTCLKEN(1U)
6764 #define V_APP_LTSSM_ENABLE(x) ((x) << S_APP_LTSSM_ENABLE)
6765 #define F_APP_LTSSM_ENABLE    V_APP_LTSSM_ENABLE(1U)
6771 #define V_A1_RSVD1(x) ((x) << S_A1_RSVD1)
6772 #define G_A1_RSVD1(x) (((x) >> S_A1_RSVD1) & M_A1_RSVD1)
6776 #define V_A1_PRIMBUSNUMBER(x) ((x) << S_A1_PRIMBUSNUMBER)
6777 #define G_A1_PRIMBUSNUMBER(x) (((x) >> S_A1_PRIMBUSNUMBER) & M_A1_PRIMBUSNUMBER)
6781 #define V_A1_REQUESTERID(x) ((x) << S_A1_REQUESTERID)
6782 #define G_A1_REQUESTERID(x) (((x) >> S_A1_REQUESTERID) & M_A1_REQUESTERID)
6786 #define S_CFGRD_SWAP_EN    1
6787 #define V_CFGRD_SWAP_EN(x) ((x) << S_CFGRD_SWAP_EN)
6788 #define F_CFGRD_SWAP_EN    V_CFGRD_SWAP_EN(1U)
6791 #define V_CFGWR_SWAP_EN(x) ((x) << S_CFGWR_SWAP_EN)
6792 #define F_CFGWR_SWAP_EN    V_CFGWR_SWAP_EN(1U)
6868 #define V_COOKIEB(x) ((x) << S_COOKIEB)
6869 #define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
6873 #define V_COOKIEA(x) ((x) << S_COOKIEA)
6874 #define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
6880 #define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
6881 #define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
6885 #define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
6886 #define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
6890 #define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
6891 #define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
6895 #define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
6896 #define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
6902 #define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
6903 #define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
6907 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
6908 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
6912 #define V_RCVDVDMRXCOOKIE(x) ((x) << S_RCVDVDMRXCOOKIE)
6913 #define G_RCVDVDMRXCOOKIE(x) (((x) >> S_RCVDVDMRXCOOKIE) & M_RCVDVDMRXCOOKIE)
6917 #define V_RCVDVDMTXCOOKIE(x) ((x) << S_RCVDVDMTXCOOKIE)
6918 #define G_RCVDVDMTXCOOKIE(x) (((x) >> S_RCVDVDMTXCOOKIE) & M_RCVDVDMTXCOOKIE)
6922 #define V_T6_RCVDMAREQCOOKIE(x) ((x) << S_T6_RCVDMAREQCOOKIE)
6923 #define G_T6_RCVDMAREQCOOKIE(x) (((x) >> S_T6_RCVDMAREQCOOKIE) & M_T6_RCVDMAREQCOOKIE)
6927 #define V_T6_RCVDPIOREQCOOKIE(x) ((x) << S_T6_RCVDPIOREQCOOKIE)
6928 #define G_T6_RCVDPIOREQCOOKIE(x) (((x) >> S_T6_RCVDPIOREQCOOKIE) & M_T6_RCVDPIOREQCOOKIE)
6934 #define V_T7_CPLD0(x) ((x) << S_T7_CPLD0)
6935 #define G_T7_CPLD0(x) (((x) >> S_T7_CPLD0) & M_T7_CPLD0)
6939 #define V_T7_CPLH0(x) ((x) << S_T7_CPLH0)
6940 #define G_T7_CPLH0(x) (((x) >> S_T7_CPLH0) & M_T7_CPLH0)
6946 #define V_T7_PD0(x) ((x) << S_T7_PD0)
6947 #define G_T7_PD0(x) (((x) >> S_T7_PD0) & M_T7_PD0)
6951 #define V_T7_PH0(x) ((x) << S_T7_PH0)
6952 #define G_T7_PH0(x) (((x) >> S_T7_PH0) & M_T7_PH0)
6958 #define V_CPLD0(x) ((x) << S_CPLD0)
6959 #define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
6963 #define V_PH0(x) ((x) << S_PH0)
6964 #define G_PH0(x) (((x) >> S_PH0) & M_PH0)
6968 #define V_PD0(x) ((x) << S_PD0)
6969 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
6975 #define V_T7_NPD0(x) ((x) << S_T7_NPD0)
6976 #define G_T7_NPD0(x) (((x) >> S_T7_NPD0) & M_T7_NPD0)
6980 #define V_T7_NPH0(x) ((x) << S_T7_NPH0)
6981 #define G_T7_NPH0(x) (((x) >> S_T7_NPH0) & M_T7_NPH0)
6987 #define V_CPLH0(x) ((x) << S_CPLH0)
6988 #define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
6992 #define V_NPH0(x) ((x) << S_NPH0)
6993 #define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
6997 #define V_NPD0(x) ((x) << S_NPD0)
6998 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
7005 #define V_CPLD1(x) ((x) << S_CPLD1)
7006 #define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
7010 #define V_PH1(x) ((x) << S_PH1)
7011 #define G_PH1(x) (((x) >> S_PH1) & M_PH1)
7015 #define V_PD1(x) ((x) << S_PD1)
7016 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
7023 #define V_CPLH1(x) ((x) << S_CPLH1)
7024 #define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
7028 #define V_NPH1(x) ((x) << S_NPH1)
7029 #define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
7033 #define V_NPD1(x) ((x) << S_NPD1)
7034 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
7046 #define V_PM_STATUS(x) ((x) << S_PM_STATUS)
7047 #define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
7051 #define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
7052 #define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
7055 #define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
7056 #define F_LTSSMENABLE    V_LTSSMENABLE(1U)
7060 #define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
7061 #define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
7065 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
7066 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
7069 #define V_LTSSMENABLE_PCIE(x) ((x) << S_LTSSMENABLE_PCIE)
7070 #define F_LTSSMENABLE_PCIE    V_LTSSMENABLE_PCIE(1U)
7074 #define V_STATECFGINITF_PCIE(x) ((x) << S_STATECFGINITF_PCIE)
7075 #define G_STATECFGINITF_PCIE(x) (((x) >> S_STATECFGINITF_PCIE) & M_STATECFGINITF_PCIE)
7079 #define V_STATECFGINIT_PCIE(x) ((x) << S_STATECFGINIT_PCIE)
7080 #define G_STATECFGINIT_PCIE(x) (((x) >> S_STATECFGINIT_PCIE) & M_STATECFGINIT_PCIE)
7085 #define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
7086 #define F_CRS_ENABLE    V_CRS_ENABLE(1U)
7091 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
7092 #define F_LTSSM_ENABLE    V_LTSSM_ENABLE(1U)
7094 #define S_LTSSM_STALL_DISABLE    1
7095 #define V_LTSSM_STALL_DISABLE(x) ((x) << S_LTSSM_STALL_DISABLE)
7096 #define F_LTSSM_STALL_DISABLE    V_LTSSM_STALL_DISABLE(1U)
7102 #define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
7103 #define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
7107 #define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
7108 #define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
7115 #define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
7116 #define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
7120 #define V_LINK_STATE(x) ((x) << S_LINK_STATE)
7121 #define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
7124 #define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
7125 #define F_FORCE_LINK    V_FORCE_LINK(1U)
7129 #define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
7130 #define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
7135 #define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
7136 #define F_ENTER_ASPM_L1_WO_L0S    V_ENTER_ASPM_L1_WO_L0S(1U)
7140 #define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
7141 #define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
7145 #define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
7146 #define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
7150 #define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
7151 #define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
7155 #define V_N_FTS(x) ((x) << S_N_FTS)
7156 #define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
7160 #define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
7161 #define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
7166 #define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
7167 #define F_CROSSLINK_ACTIVE    V_CROSSLINK_ACTIVE(1U)
7170 #define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
7171 #define F_CROSSLINK_ENABLE    V_CROSSLINK_ENABLE(1U)
7175 #define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
7176 #define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
7179 #define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
7180 #define F_FAST_LINK_MODE    V_FAST_LINK_MODE(1U)
7183 #define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
7184 #define F_DLL_LINK_ENABLE    V_DLL_LINK_ENABLE(1U)
7187 #define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
7188 #define F_RESET_ASSERT    V_RESET_ASSERT(1U)
7191 #define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
7192 #define F_LOOPBACK_ENABLE    V_LOOPBACK_ENABLE(1U)
7194 #define S_SCRAMBLE_DISABLE    1
7195 #define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
7196 #define F_SCRAMBLE_DISABLE    V_SCRAMBLE_DISABLE(1U)
7199 #define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
7200 #define F_VENDOR_SPECIFIC_DLLP_REQUEST    V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
7205 #define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
7206 #define F_DISABLE_DESKEW    V_DISABLE_DESKEW(1U)
7209 #define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
7210 #define F_ACK_NAK_DISABLE    V_ACK_NAK_DISABLE(1U)
7213 #define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
7214 #define F_FLOW_CONTROL_DISABLE    V_FLOW_CONTROL_DISABLE(1U)
7218 #define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
7219 #define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
7225 #define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
7226 #define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
7230 #define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
7231 #define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
7235 #define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
7236 #define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
7240 #define V_MAXFUNC(x) ((x) << S_MAXFUNC)
7241 #define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
7247 #define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
7248 #define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
7251 #define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
7252 #define F_DISABLE_FC_WATCHDOG    V_DISABLE_FC_WATCHDOG(1U)
7256 #define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
7257 #define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
7266 #define V_TXPH_FC(x) ((x) << S_TXPH_FC)
7267 #define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
7271 #define V_TXPD_FC(x) ((x) << S_TXPD_FC)
7272 #define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
7278 #define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
7279 #define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
7283 #define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
7284 #define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
7290 #define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
7291 #define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
7295 #define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
7296 #define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
7301 #define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
7302 #define F_RXQUEUE_NOT_EMPTY    V_RXQUEUE_NOT_EMPTY(1U)
7304 #define S_TXRETRYBUF_NOT_EMPTY    1
7305 #define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
7306 #define F_TXRETRYBUF_NOT_EMPTY    V_TXRETRYBUF_NOT_EMPTY(1U)
7309 #define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
7310 #define F_RXTLP_FC_NOT_RETURNED    V_RXTLP_FC_NOT_RETURNED(1U)
7316 #define V_VC3_WRR(x) ((x) << S_VC3_WRR)
7317 #define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
7321 #define V_VC2_WRR(x) ((x) << S_VC2_WRR)
7322 #define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
7326 #define V_VC1_WRR(x) ((x) << S_VC1_WRR)
7327 #define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
7331 #define V_VC0_WRR(x) ((x) << S_VC0_WRR)
7332 #define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
7338 #define V_VC7_WRR(x) ((x) << S_VC7_WRR)
7339 #define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
7343 #define V_VC6_WRR(x) ((x) << S_VC6_WRR)
7344 #define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
7348 #define V_VC5_WRR(x) ((x) << S_VC5_WRR)
7349 #define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
7353 #define V_VC4_WRR(x) ((x) << S_VC4_WRR)
7354 #define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
7359 #define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
7360 #define F_VC0_RX_ORDERING    V_VC0_RX_ORDERING(1U)
7363 #define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
7364 #define F_VC0_TLP_ORDERING    V_VC0_TLP_ORDERING(1U)
7368 #define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
7369 #define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
7373 #define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
7374 #define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
7378 #define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
7379 #define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
7385 #define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
7386 #define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
7390 #define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
7391 #define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
7395 #define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
7396 #define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
7402 #define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
7403 #define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
7407 #define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
7408 #define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
7412 #define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
7413 #define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
7418 #define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
7419 #define F_VC1_TLP_ORDERING    V_VC1_TLP_ORDERING(1U)
7423 #define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
7424 #define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
7428 #define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
7429 #define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
7433 #define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
7434 #define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
7440 #define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
7441 #define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
7445 #define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
7446 #define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
7450 #define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
7451 #define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
7457 #define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
7458 #define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
7462 #define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
7463 #define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
7467 #define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
7468 #define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
7473 #define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
7474 #define F_SEL_DEEMPHASIS    V_SEL_DEEMPHASIS(1U)
7477 #define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
7478 #define F_TXCMPLRCV    V_TXCMPLRCV(1U)
7481 #define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
7482 #define F_PHYTXSWING    V_PHYTXSWING(1U)
7485 #define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
7486 #define F_DIRSPDCHANGE    V_DIRSPDCHANGE(1U)
7490 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
7491 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
7495 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
7496 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
7499 #define V_AUTO_LANE_FLIP_CTRL_EN(x) ((x) << S_AUTO_LANE_FLIP_CTRL_EN)
7500 #define F_AUTO_LANE_FLIP_CTRL_EN    V_AUTO_LANE_FLIP_CTRL_EN(1U)
7504 #define V_T6_NUM_LANES(x) ((x) << S_T6_NUM_LANES)
7505 #define G_T6_NUM_LANES(x) (((x) >> S_T6_NUM_LANES) & M_T6_NUM_LANES)
7512 #define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
7513 #define F_DC_BALANCE_DISABLE    V_DC_BALANCE_DISABLE(1U)
7516 #define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
7517 #define F_DLLP_DELAY_DISABLE    V_DLLP_DELAY_DISABLE(1U)
7520 #define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
7521 #define F_EQL_DISABLE    V_EQL_DISABLE(1U)
7524 #define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
7525 #define F_EQL_REDO_DISABLE    V_EQL_REDO_DISABLE(1U)
7528 #define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
7529 #define F_EQL_EIEOS_CNTRST_DISABLE    V_EQL_EIEOS_CNTRST_DISABLE(1U)
7532 #define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
7533 #define F_EQL_PH2_PH3_DISABLE    V_EQL_PH2_PH3_DISABLE(1U)
7536 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
7537 #define F_DISABLE_SCRAMBLER    V_DISABLE_SCRAMBLER(1U)
7541 #define V_RATE_SHADOW_SEL(x) ((x) << S_RATE_SHADOW_SEL)
7542 #define G_RATE_SHADOW_SEL(x) (((x) >> S_RATE_SHADOW_SEL) & M_RATE_SHADOW_SEL)
7548 #define V_FULL_SWING(x) ((x) << S_FULL_SWING)
7549 #define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
7553 #define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
7554 #define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
7560 #define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
7561 #define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
7565 #define V_CURSOR(x) ((x) << S_CURSOR)
7566 #define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
7570 #define V_PRECURSOR(x) ((x) << S_PRECURSOR)
7571 #define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
7577 #define V_INDEX(x) ((x) << S_INDEX)
7578 #define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
7583 #define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
7584 #define F_LEGALITY_STATUS    V_LEGALITY_STATUS(1U)
7589 #define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
7590 #define F_INCLUDE_INITIAL_FOM    V_INCLUDE_INITIAL_FOM(1U)
7594 #define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
7595 #define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
7598 #define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
7599 #define F_PHASE23_2MS_TIMEOUT_DISABLE    V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
7602 #define V_AFTER24MS(x) ((x) << S_AFTER24MS)
7603 #define F_AFTER24MS    V_AFTER24MS(1U)
7607 #define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
7608 #define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
7614 #define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
7615 #define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
7619 #define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
7620 #define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
7624 #define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
7625 #define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
7629 #define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
7630 #define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
7635 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
7636 #define F_PIPE_LOOPBACK_EN    V_PIPE_LOOPBACK_EN(1U)
7639 #define V_T6_PIPE_LOOPBACK_EN(x) ((x) << S_T6_PIPE_LOOPBACK_EN)
7640 #define F_T6_PIPE_LOOPBACK_EN    V_T6_PIPE_LOOPBACK_EN(1U)
7645 #define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
7646 #define F_READONLY_WRITEEN    V_READONLY_WRITEEN(1U)
7651 #define V_SMTD(x) ((x) << S_SMTD)
7652 #define F_SMTD    V_SMTD(1U)
7655 #define V_SSTD(x) ((x) << S_SSTD)
7656 #define F_SSTD    V_SSTD(1U)
7659 #define V_SWD0(x) ((x) << S_SWD0)
7660 #define F_SWD0    V_SWD0(1U)
7663 #define V_SWD1(x) ((x) << S_SWD1)
7664 #define F_SWD1    V_SWD1(1U)
7667 #define V_SWD2(x) ((x) << S_SWD2)
7668 #define F_SWD2    V_SWD2(1U)
7671 #define V_SWD3(x) ((x) << S_SWD3)
7672 #define F_SWD3    V_SWD3(1U)
7675 #define V_SWD4(x) ((x) << S_SWD4)
7676 #define F_SWD4    V_SWD4(1U)
7679 #define V_SWD5(x) ((x) << S_SWD5)
7680 #define F_SWD5    V_SWD5(1U)
7683 #define V_SWD6(x) ((x) << S_SWD6)
7684 #define F_SWD6    V_SWD6(1U)
7687 #define V_SWD7(x) ((x) << S_SWD7)
7688 #define F_SWD7    V_SWD7(1U)
7691 #define V_SWD8(x) ((x) << S_SWD8)
7692 #define F_SWD8    V_SWD8(1U)
7695 #define V_SRD0(x) ((x) << S_SRD0)
7696 #define F_SRD0    V_SRD0(1U)
7699 #define V_SRD1(x) ((x) << S_SRD1)
7700 #define F_SRD1    V_SRD1(1U)
7703 #define V_SRD2(x) ((x) << S_SRD2)
7704 #define F_SRD2    V_SRD2(1U)
7707 #define V_SRD3(x) ((x) << S_SRD3)
7708 #define F_SRD3    V_SRD3(1U)
7711 #define V_SRD4(x) ((x) << S_SRD4)
7712 #define F_SRD4    V_SRD4(1U)
7715 #define V_SRD5(x) ((x) << S_SRD5)
7716 #define F_SRD5    V_SRD5(1U)
7719 #define V_SRD6(x) ((x) << S_SRD6)
7720 #define F_SRD6    V_SRD6(1U)
7723 #define V_SRD7(x) ((x) << S_SRD7)
7724 #define F_SRD7    V_SRD7(1U)
7727 #define V_SRD8(x) ((x) << S_SRD8)
7728 #define F_SRD8    V_SRD8(1U)
7731 #define V_CRRE(x) ((x) << S_CRRE)
7732 #define F_CRRE    V_CRRE(1U)
7736 #define V_CRMC(x) ((x) << S_CRMC)
7737 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
7742 #define V_USBP(x) ((x) << S_USBP)
7743 #define F_USBP    V_USBP(1U)
7746 #define V_UPEP(x) ((x) << S_UPEP)
7747 #define F_UPEP    V_UPEP(1U)
7750 #define V_RCEP(x) ((x) << S_RCEP)
7751 #define F_RCEP    V_RCEP(1U)
7754 #define V_EPEP(x) ((x) << S_EPEP)
7755 #define F_EPEP    V_EPEP(1U)
7758 #define V_USBS(x) ((x) << S_USBS)
7759 #define F_USBS    V_USBS(1U)
7762 #define V_UPES(x) ((x) << S_UPES)
7763 #define F_UPES    V_UPES(1U)
7766 #define V_RCES(x) ((x) << S_RCES)
7767 #define F_RCES    V_RCES(1U)
7770 #define V_EPES(x) ((x) << S_EPES)
7771 #define F_EPES    V_EPES(1U)
7776 #define V_RNPP(x) ((x) << S_RNPP)
7777 #define F_RNPP    V_RNPP(1U)
7780 #define V_RPCP(x) ((x) << S_RPCP)
7781 #define F_RPCP    V_RPCP(1U)
7784 #define V_RCIP(x) ((x) << S_RCIP)
7785 #define F_RCIP    V_RCIP(1U)
7788 #define V_RCCP(x) ((x) << S_RCCP)
7789 #define F_RCCP    V_RCCP(1U)
7792 #define V_RFTP(x) ((x) << S_RFTP)
7793 #define F_RFTP    V_RFTP(1U)
7796 #define V_PTRP(x) ((x) << S_PTRP)
7797 #define F_PTRP    V_PTRP(1U)
7802 #define V_RNPS(x) ((x) << S_RNPS)
7803 #define F_RNPS    V_RNPS(1U)
7806 #define V_RPCS(x) ((x) << S_RPCS)
7807 #define F_RPCS    V_RPCS(1U)
7810 #define V_RCIS(x) ((x) << S_RCIS)
7811 #define F_RCIS    V_RCIS(1U)
7814 #define V_RCCS(x) ((x) << S_RCCS)
7815 #define F_RCCS    V_RCCS(1U)
7818 #define V_RFTS(x) ((x) << S_RFTS)
7819 #define F_RFTS    V_RFTS(1U)
7824 #define V_RNPI(x) ((x) << S_RNPI)
7825 #define F_RNPI    V_RNPI(1U)
7828 #define V_RPCI(x) ((x) << S_RPCI)
7829 #define F_RPCI    V_RPCI(1U)
7832 #define V_RCII(x) ((x) << S_RCII)
7833 #define F_RCII    V_RCII(1U)
7836 #define V_RCCI(x) ((x) << S_RCCI)
7837 #define F_RCCI    V_RCCI(1U)
7840 #define V_RFTI(x) ((x) << S_RFTI)
7841 #define F_RFTI    V_RFTI(1U)
7847 #define V_SBRS(x) ((x) << S_SBRS)
7848 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
7852 #define V_OTWS(x) ((x) << S_OTWS)
7853 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
7859 #define V_RVID(x) ((x) << S_RVID)
7860 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
7864 #define V_BRVN(x) ((x) << S_BRVN)
7865 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
7871 #define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
7872 #define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
7876 #define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
7877 #define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
7881 #define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
7882 #define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
7885 #define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
7886 #define F_SEQCHKDIS    V_SEQCHKDIS(1U)
7890 #define V_MINTAG(x) ((x) << S_MINTAG)
7891 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
7895 #define V_T6_T5_DMA_MAXREQCNT(x) ((x) << S_T6_T5_DMA_MAXREQCNT)
7896 #define G_T6_T5_DMA_MAXREQCNT(x) (((x) >> S_T6_T5_DMA_MAXREQCNT) & M_T6_T5_DMA_MAXREQCNT)
7900 #define V_T6_T5_DMA_MAXRSPCNT(x) ((x) << S_T6_T5_DMA_MAXRSPCNT)
7901 #define G_T6_T5_DMA_MAXRSPCNT(x) (((x) >> S_T6_T5_DMA_MAXRSPCNT) & M_T6_T5_DMA_MAXRSPCNT)
7904 #define V_T6_SEQCHKDIS(x) ((x) << S_T6_SEQCHKDIS)
7905 #define F_T6_SEQCHKDIS    V_T6_SEQCHKDIS(1U)
7909 #define V_T6_MINTAG(x) ((x) << S_T6_MINTAG)
7910 #define G_T6_MINTAG(x) (((x) >> S_T6_MINTAG) & M_T6_MINTAG)
7916 #define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
7917 #define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
7921 #define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
7922 #define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
7926 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
7927 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
7931 #define V_T6_DMA_RESPCNT(x) ((x) << S_T6_DMA_RESPCNT)
7932 #define G_T6_DMA_RESPCNT(x) (((x) >> S_T6_DMA_RESPCNT) & M_T6_DMA_RESPCNT)
7936 #define V_T6_DMA_RDREQCNT(x) ((x) << S_T6_DMA_RDREQCNT)
7937 #define G_T6_DMA_RDREQCNT(x) (((x) >> S_T6_DMA_RDREQCNT) & M_T6_DMA_RDREQCNT)
7941 #define V_T6_DMA_WRREQCNT(x) ((x) << S_T6_DMA_WRREQCNT)
7942 #define G_T6_DMA_WRREQCNT(x) (((x) >> S_T6_DMA_WRREQCNT) & M_T6_DMA_WRREQCNT)
7948 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
7949 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
7953 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
7954 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
7958 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
7959 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
7962 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
7963 #define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)
7967 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
7968 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
7972 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
7973 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
7977 #define V_DMA_COOKIECNT(x) ((x) << S_DMA_COOKIECNT)
7978 #define G_DMA_COOKIECNT(x) (((x) >> S_DMA_COOKIECNT) & M_DMA_COOKIECNT)
7982 #define V_DMA_RDSEQNUMUPDCNT(x) ((x) << S_DMA_RDSEQNUMUPDCNT)
7983 #define G_DMA_RDSEQNUMUPDCNT(x) (((x) >> S_DMA_RDSEQNUMUPDCNT) & M_DMA_RDSEQNUMUPDCNT)
7987 #define V_DMA_SIREQCNT(x) ((x) << S_DMA_SIREQCNT)
7988 #define G_DMA_SIREQCNT(x) (((x) >> S_DMA_SIREQCNT) & M_DMA_SIREQCNT)
7991 #define V_DMA_WREOPMATCHSOP(x) ((x) << S_DMA_WREOPMATCHSOP)
7992 #define F_DMA_WREOPMATCHSOP    V_DMA_WREOPMATCHSOP(1U)
7996 #define V_DMA_WRSOPCNT(x) ((x) << S_DMA_WRSOPCNT)
7997 #define G_DMA_WRSOPCNT(x) (((x) >> S_DMA_WRSOPCNT) & M_DMA_WRSOPCNT)
8001 #define V_DMA_RDSOPCNT(x) ((x) << S_DMA_RDSOPCNT)
8002 #define G_DMA_RDSOPCNT(x) (((x) >> S_DMA_RDSOPCNT) & M_DMA_RDSOPCNT)
8008 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
8009 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
8012 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
8013 #define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)
8016 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
8017 #define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)
8021 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
8022 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
8026 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
8027 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
8031 #define V_DMA_ATMREQSOPCNT(x) ((x) << S_DMA_ATMREQSOPCNT)
8032 #define G_DMA_ATMREQSOPCNT(x) (((x) >> S_DMA_ATMREQSOPCNT) & M_DMA_ATMREQSOPCNT)
8035 #define V_DMA_ATMEOPMATCHSOP(x) ((x) << S_DMA_ATMEOPMATCHSOP)
8036 #define F_DMA_ATMEOPMATCHSOP    V_DMA_ATMEOPMATCHSOP(1U)
8039 #define V_DMA_RSPEOPMATCHSOP(x) ((x) << S_DMA_RSPEOPMATCHSOP)
8040 #define F_DMA_RSPEOPMATCHSOP    V_DMA_RSPEOPMATCHSOP(1U)
8044 #define V_DMA_RSPERRCNT(x) ((x) << S_DMA_RSPERRCNT)
8045 #define G_DMA_RSPERRCNT(x) (((x) >> S_DMA_RSPERRCNT) & M_DMA_RSPERRCNT)
8049 #define V_DMA_RSPSOPCNT(x) ((x) << S_DMA_RSPSOPCNT)
8050 #define G_DMA_RSPSOPCNT(x) (((x) >> S_DMA_RSPSOPCNT) & M_DMA_RSPSOPCNT)
8056 #define V_OP0H(x) ((x) << S_OP0H)
8057 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
8061 #define V_OP1H(x) ((x) << S_OP1H)
8062 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
8066 #define V_OP2H(x) ((x) << S_OP2H)
8067 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
8071 #define V_OP3H(x) ((x) << S_OP3H)
8072 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
8078 #define V_OP0D(x) ((x) << S_OP0D)
8079 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
8083 #define V_OP1D(x) ((x) << S_OP1D)
8084 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
8088 #define V_OP2D(x) ((x) << S_OP2D)
8089 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
8093 #define V_OP3D(x) ((x) << S_OP3D)
8094 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
8100 #define V_IP0H(x) ((x) << S_IP0H)
8101 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
8105 #define V_IP1H(x) ((x) << S_IP1H)
8106 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
8110 #define V_IP2H(x) ((x) << S_IP2H)
8111 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
8115 #define V_IP3H(x) ((x) << S_IP3H)
8116 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
8122 #define V_IP0D(x) ((x) << S_IP0D)
8123 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
8127 #define V_IP1D(x) ((x) << S_IP1D)
8128 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
8132 #define V_IP2D(x) ((x) << S_IP2D)
8133 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
8137 #define V_IP3D(x) ((x) << S_IP3D)
8138 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
8144 #define V_ON0H(x) ((x) << S_ON0H)
8145 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
8149 #define V_ON1H(x) ((x) << S_ON1H)
8150 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
8154 #define V_ON2H(x) ((x) << S_ON2H)
8155 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
8159 #define V_ON3H(x) ((x) << S_ON3H)
8160 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
8166 #define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
8167 #define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
8171 #define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
8172 #define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
8175 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
8176 #define F_USECMDPOOL    V_USECMDPOOL(1U)
8180 #define V_T6_T5_CMD_MAXRSPCNT(x) ((x) << S_T6_T5_CMD_MAXRSPCNT)
8181 #define G_T6_T5_CMD_MAXRSPCNT(x) (((x) >> S_T6_T5_CMD_MAXRSPCNT) & M_T6_T5_CMD_MAXRSPCNT)
8184 #define V_T6_USECMDPOOL(x) ((x) << S_T6_USECMDPOOL)
8185 #define F_T6_USECMDPOOL    V_T6_USECMDPOOL(1U)
8191 #define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
8192 #define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
8196 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
8197 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
8201 #define V_T6_T5_STAT_RSPCNT(x) ((x) << S_T6_T5_STAT_RSPCNT)
8202 #define G_T6_T5_STAT_RSPCNT(x) (((x) >> S_T6_T5_STAT_RSPCNT) & M_T6_T5_STAT_RSPCNT)
8206 #define V_T6_RDREQCNT(x) ((x) << S_T6_RDREQCNT)
8207 #define G_T6_RDREQCNT(x) (((x) >> S_T6_RDREQCNT) & M_T6_RDREQCNT)
8213 #define V_IN0H(x) ((x) << S_IN0H)
8214 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
8218 #define V_IN1H(x) ((x) << S_IN1H)
8219 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
8223 #define V_IN2H(x) ((x) << S_IN2H)
8224 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
8228 #define V_IN3H(x) ((x) << S_IN3H)
8229 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
8235 #define V_CMD_RSPEOPMATCHSOP(x) ((x) << S_CMD_RSPEOPMATCHSOP)
8236 #define F_CMD_RSPEOPMATCHSOP    V_CMD_RSPEOPMATCHSOP(1U)
8240 #define V_CMD_RSPERRCNT(x) ((x) << S_CMD_RSPERRCNT)
8241 #define G_CMD_RSPERRCNT(x) (((x) >> S_CMD_RSPERRCNT) & M_CMD_RSPERRCNT)
8245 #define V_CMD_RSPSOPCNT(x) ((x) << S_CMD_RSPSOPCNT)
8246 #define G_CMD_RSPSOPCNT(x) (((x) >> S_CMD_RSPSOPCNT) & M_CMD_RSPSOPCNT)
8252 #define V_OC0T(x) ((x) << S_OC0T)
8253 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
8257 #define V_OC1T(x) ((x) << S_OC1T)
8258 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
8262 #define V_OC2T(x) ((x) << S_OC2T)
8263 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
8267 #define V_OC3T(x) ((x) << S_OC3T)
8268 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
8274 #define V_IC0T(x) ((x) << S_IC0T)
8275 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
8279 #define V_IC1T(x) ((x) << S_IC1T)
8280 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
8284 #define V_IC2T(x) ((x) << S_IC2T)
8285 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
8289 #define V_IC3T(x) ((x) << S_IC3T)
8290 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
8295 #define V_VRB0(x) ((x) << S_VRB0)
8296 #define F_VRB0    V_VRB0(1U)
8299 #define V_VRB1(x) ((x) << S_VRB1)
8300 #define F_VRB1    V_VRB1(1U)
8303 #define V_VRB2(x) ((x) << S_VRB2)
8304 #define F_VRB2    V_VRB2(1U)
8307 #define V_VRB3(x) ((x) << S_VRB3)
8308 #define F_VRB3    V_VRB3(1U)
8311 #define V_PSFE(x) ((x) << S_PSFE)
8312 #define F_PSFE    V_PSFE(1U)
8315 #define V_RVDE(x) ((x) << S_RVDE)
8316 #define F_RVDE    V_RVDE(1U)
8319 #define V_TXE0(x) ((x) << S_TXE0)
8320 #define F_TXE0    V_TXE0(1U)
8323 #define V_TXE1(x) ((x) << S_TXE1)
8324 #define F_TXE1    V_TXE1(1U)
8327 #define V_TXE2(x) ((x) << S_TXE2)
8328 #define F_TXE2    V_TXE2(1U)
8331 #define V_TXE3(x) ((x) << S_TXE3)
8332 #define F_TXE3    V_TXE3(1U)
8335 #define V_RPAM(x) ((x) << S_RPAM)
8336 #define F_RPAM    V_RPAM(1U)
8340 #define V_RTOS(x) ((x) << S_RTOS)
8341 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
8346 #define V_TPCP(x) ((x) << S_TPCP)
8347 #define F_TPCP    V_TPCP(1U)
8350 #define V_TNPP(x) ((x) << S_TNPP)
8351 #define F_TNPP    V_TNPP(1U)
8354 #define V_TFTP(x) ((x) << S_TFTP)
8355 #define F_TFTP    V_TFTP(1U)
8358 #define V_TCAP(x) ((x) << S_TCAP)
8359 #define F_TCAP    V_TCAP(1U)
8362 #define V_TCIP(x) ((x) << S_TCIP)
8363 #define F_TCIP    V_TCIP(1U)
8366 #define V_RCAP(x) ((x) << S_RCAP)
8367 #define F_RCAP    V_RCAP(1U)
8370 #define V_PLUP(x) ((x) << S_PLUP)
8371 #define F_PLUP    V_PLUP(1U)
8374 #define V_PLDN(x) ((x) << S_PLDN)
8375 #define F_PLDN    V_PLDN(1U)
8378 #define V_OTDD(x) ((x) << S_OTDD)
8379 #define F_OTDD    V_OTDD(1U)
8382 #define V_GTRP(x) ((x) << S_GTRP)
8383 #define F_GTRP    V_GTRP(1U)
8386 #define V_RDPE(x) ((x) << S_RDPE)
8387 #define F_RDPE    V_RDPE(1U)
8390 #define V_TDCE(x) ((x) << S_TDCE)
8391 #define F_TDCE    V_TDCE(1U)
8394 #define V_TDUE(x) ((x) << S_TDUE)
8395 #define F_TDUE    V_TDUE(1U)
8400 #define V_TPCS(x) ((x) << S_TPCS)
8401 #define F_TPCS    V_TPCS(1U)
8404 #define V_TNPS(x) ((x) << S_TNPS)
8405 #define F_TNPS    V_TNPS(1U)
8408 #define V_TFTS(x) ((x) << S_TFTS)
8409 #define F_TFTS    V_TFTS(1U)
8412 #define V_TCAS(x) ((x) << S_TCAS)
8413 #define F_TCAS    V_TCAS(1U)
8416 #define V_TCIS(x) ((x) << S_TCIS)
8417 #define F_TCIS    V_TCIS(1U)
8420 #define V_RCAS(x) ((x) << S_RCAS)
8421 #define F_RCAS    V_RCAS(1U)
8424 #define V_PLUS(x) ((x) << S_PLUS)
8425 #define F_PLUS    V_PLUS(1U)
8428 #define V_PLDS(x) ((x) << S_PLDS)
8429 #define F_PLDS    V_PLDS(1U)
8432 #define V_OTDS(x) ((x) << S_OTDS)
8433 #define F_OTDS    V_OTDS(1U)
8436 #define V_RDPS(x) ((x) << S_RDPS)
8437 #define F_RDPS    V_RDPS(1U)
8440 #define V_TDCS(x) ((x) << S_TDCS)
8441 #define F_TDCS    V_TDCS(1U)
8444 #define V_TDUS(x) ((x) << S_TDUS)
8445 #define F_TDUS    V_TDUS(1U)
8450 #define V_TPCI(x) ((x) << S_TPCI)
8451 #define F_TPCI    V_TPCI(1U)
8454 #define V_TNPI(x) ((x) << S_TNPI)
8455 #define F_TNPI    V_TNPI(1U)
8458 #define V_TFTI(x) ((x) << S_TFTI)
8459 #define F_TFTI    V_TFTI(1U)
8462 #define V_TCAI(x) ((x) << S_TCAI)
8463 #define F_TCAI    V_TCAI(1U)
8466 #define V_TCII(x) ((x) << S_TCII)
8467 #define F_TCII    V_TCII(1U)
8470 #define V_RCAI(x) ((x) << S_RCAI)
8471 #define F_RCAI    V_RCAI(1U)
8474 #define V_PLUI(x) ((x) << S_PLUI)
8475 #define F_PLUI    V_PLUI(1U)
8478 #define V_PLDI(x) ((x) << S_PLDI)
8479 #define F_PLDI    V_PLDI(1U)
8482 #define V_OTDI(x) ((x) << S_OTDI)
8483 #define F_OTDI    V_OTDI(1U)
8488 #define V_RLCE(x) ((x) << S_RLCE)
8489 #define F_RLCE    V_RLCE(1U)
8492 #define V_RLNE(x) ((x) << S_RLNE)
8493 #define F_RLNE    V_RLNE(1U)
8496 #define V_RLFE(x) ((x) << S_RLFE)
8497 #define F_RLFE    V_RLFE(1U)
8500 #define V_RCPE(x) ((x) << S_RCPE)
8501 #define F_RCPE    V_RCPE(1U)
8504 #define V_RCTO(x) ((x) << S_RCTO)
8505 #define F_RCTO    V_RCTO(1U)
8508 #define V_PINA(x) ((x) << S_PINA)
8509 #define F_PINA    V_PINA(1U)
8512 #define V_PINB(x) ((x) << S_PINB)
8513 #define F_PINB    V_PINB(1U)
8516 #define V_PINC(x) ((x) << S_PINC)
8517 #define F_PINC    V_PINC(1U)
8520 #define V_PIND(x) ((x) << S_PIND)
8521 #define F_PIND    V_PIND(1U)
8524 #define V_ALER(x) ((x) << S_ALER)
8525 #define F_ALER    V_ALER(1U)
8528 #define V_CRSE(x) ((x) << S_CRSE)
8529 #define F_CRSE    V_CRSE(1U)
8535 #define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
8536 #define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
8540 #define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
8541 #define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
8545 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
8546 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
8550 #define V_T6_HMA_MAXREQCNT(x) ((x) << S_T6_HMA_MAXREQCNT)
8551 #define G_T6_HMA_MAXREQCNT(x) (((x) >> S_T6_HMA_MAXREQCNT) & M_T6_HMA_MAXREQCNT)
8555 #define V_T6_T5_HMA_MAXRSPCNT(x) ((x) << S_T6_T5_HMA_MAXRSPCNT)
8556 #define G_T6_T5_HMA_MAXRSPCNT(x) (((x) >> S_T6_T5_HMA_MAXRSPCNT) & M_T6_T5_HMA_MAXRSPCNT)
8559 #define V_T5_HMA_SEQCHKDIS(x) ((x) << S_T5_HMA_SEQCHKDIS)
8560 #define F_T5_HMA_SEQCHKDIS    V_T5_HMA_SEQCHKDIS(1U)
8564 #define V_T5_MINTAG(x) ((x) << S_T5_MINTAG)
8565 #define G_T5_MINTAG(x) (((x) >> S_T5_MINTAG) & M_T5_MINTAG)
8570 #define V_RLCS(x) ((x) << S_RLCS)
8571 #define F_RLCS    V_RLCS(1U)
8574 #define V_RLNS(x) ((x) << S_RLNS)
8575 #define F_RLNS    V_RLNS(1U)
8578 #define V_RLFS(x) ((x) << S_RLFS)
8579 #define F_RLFS    V_RLFS(1U)
8582 #define V_RCPS(x) ((x) << S_RCPS)
8583 #define F_RCPS    V_RCPS(1U)
8586 #define V_RCTS(x) ((x) << S_RCTS)
8587 #define F_RCTS    V_RCTS(1U)
8590 #define V_PAAS(x) ((x) << S_PAAS)
8591 #define F_PAAS    V_PAAS(1U)
8594 #define V_PABS(x) ((x) << S_PABS)
8595 #define F_PABS    V_PABS(1U)
8598 #define V_PACS(x) ((x) << S_PACS)
8599 #define F_PACS    V_PACS(1U)
8602 #define V_PADS(x) ((x) << S_PADS)
8603 #define F_PADS    V_PADS(1U)
8606 #define V_ALES(x) ((x) << S_ALES)
8607 #define F_ALES    V_ALES(1U)
8610 #define V_CRSS(x) ((x) << S_CRSS)
8611 #define F_CRSS    V_CRSS(1U)
8617 #define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
8618 #define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
8622 #define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
8623 #define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
8627 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
8628 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
8632 #define V_T6_HMA_RESPCNT(x) ((x) << S_T6_HMA_RESPCNT)
8633 #define G_T6_HMA_RESPCNT(x) (((x) >> S_T6_HMA_RESPCNT) & M_T6_HMA_RESPCNT)
8638 #define V_RLCI(x) ((x) << S_RLCI)
8639 #define F_RLCI    V_RLCI(1U)
8642 #define V_RLNI(x) ((x) << S_RLNI)
8643 #define F_RLNI    V_RLNI(1U)
8646 #define V_RLFI(x) ((x) << S_RLFI)
8647 #define F_RLFI    V_RLFI(1U)
8650 #define V_RCPI(x) ((x) << S_RCPI)
8651 #define F_RCPI    V_RCPI(1U)
8654 #define V_RCTI(x) ((x) << S_RCTI)
8655 #define F_RCTI    V_RCTI(1U)
8658 #define V_PAAI(x) ((x) << S_PAAI)
8659 #define F_PAAI    V_PAAI(1U)
8662 #define V_PABI(x) ((x) << S_PABI)
8663 #define F_PABI    V_PABI(1U)
8666 #define V_PACI(x) ((x) << S_PACI)
8667 #define F_PACI    V_PACI(1U)
8670 #define V_PADI(x) ((x) << S_PADI)
8671 #define F_PADI    V_PADI(1U)
8674 #define V_ALEI(x) ((x) << S_ALEI)
8675 #define F_ALEI    V_ALEI(1U)
8678 #define V_CRSI(x) ((x) << S_CRSI)
8679 #define F_CRSI    V_CRSI(1U)
8685 #define V_HMA_COOKIECNT(x) ((x) << S_HMA_COOKIECNT)
8686 #define G_HMA_COOKIECNT(x) (((x) >> S_HMA_COOKIECNT) & M_HMA_COOKIECNT)
8690 #define V_HMA_RDSEQNUMUPDCNT(x) ((x) << S_HMA_RDSEQNUMUPDCNT)
8691 #define G_HMA_RDSEQNUMUPDCNT(x) (((x) >> S_HMA_RDSEQNUMUPDCNT) & M_HMA_RDSEQNUMUPDCNT)
8694 #define V_HMA_WREOPMATCHSOP(x) ((x) << S_HMA_WREOPMATCHSOP)
8695 #define F_HMA_WREOPMATCHSOP    V_HMA_WREOPMATCHSOP(1U)
8699 #define V_HMA_WRSOPCNT(x) ((x) << S_HMA_WRSOPCNT)
8700 #define G_HMA_WRSOPCNT(x) (((x) >> S_HMA_WRSOPCNT) & M_HMA_WRSOPCNT)
8704 #define V_HMA_RDSOPCNT(x) ((x) << S_HMA_RDSOPCNT)
8705 #define G_HMA_RDSOPCNT(x) (((x) >> S_HMA_RDSOPCNT) & M_HMA_RDSOPCNT)
8710 #define V_PTOM(x) ((x) << S_PTOM)
8711 #define F_PTOM    V_PTOM(1U)
8714 #define V_ALEA(x) ((x) << S_ALEA)
8715 #define F_ALEA    V_ALEA(1U)
8718 #define V_PMC0(x) ((x) << S_PMC0)
8719 #define F_PMC0    V_PMC0(1U)
8722 #define V_PMC1(x) ((x) << S_PMC1)
8723 #define F_PMC1    V_PMC1(1U)
8726 #define V_PMC2(x) ((x) << S_PMC2)
8727 #define F_PMC2    V_PMC2(1U)
8730 #define V_PMC3(x) ((x) << S_PMC3)
8731 #define F_PMC3    V_PMC3(1U)
8734 #define V_PMC4(x) ((x) << S_PMC4)
8735 #define F_PMC4    V_PMC4(1U)
8738 #define V_PMC5(x) ((x) << S_PMC5)
8739 #define F_PMC5    V_PMC5(1U)
8742 #define V_PMC6(x) ((x) << S_PMC6)
8743 #define F_PMC6    V_PMC6(1U)
8746 #define V_PMC7(x) ((x) << S_PMC7)
8747 #define F_PMC7    V_PMC7(1U)
8752 #define V_HMA_RSPEOPMATCHSOP(x) ((x) << S_HMA_RSPEOPMATCHSOP)
8753 #define F_HMA_RSPEOPMATCHSOP    V_HMA_RSPEOPMATCHSOP(1U)
8757 #define V_HMA_RSPERRCNT(x) ((x) << S_HMA_RSPERRCNT)
8758 #define G_HMA_RSPERRCNT(x) (((x) >> S_HMA_RSPERRCNT) & M_HMA_RSPERRCNT)
8762 #define V_HMA_RSPSOPCNT(x) ((x) << S_HMA_RSPSOPCNT)
8763 #define G_HMA_RSPSOPCNT(x) (((x) >> S_HMA_RSPSOPCNT) & M_HMA_RSPSOPCNT)
8768 #define V_PTOS(x) ((x) << S_PTOS)
8769 #define F_PTOS    V_PTOS(1U)
8772 #define V_AENS(x) ((x) << S_AENS)
8773 #define F_AENS    V_AENS(1U)
8776 #define V_PC0S(x) ((x) << S_PC0S)
8777 #define F_PC0S    V_PC0S(1U)
8780 #define V_PC1S(x) ((x) << S_PC1S)
8781 #define F_PC1S    V_PC1S(1U)
8784 #define V_PC2S(x) ((x) << S_PC2S)
8785 #define F_PC2S    V_PC2S(1U)
8788 #define V_PC3S(x) ((x) << S_PC3S)
8789 #define F_PC3S    V_PC3S(1U)
8792 #define V_PC4S(x) ((x) << S_PC4S)
8793 #define F_PC4S    V_PC4S(1U)
8796 #define V_PC5S(x) ((x) << S_PC5S)
8797 #define F_PC5S    V_PC5S(1U)
8800 #define V_PC6S(x) ((x) << S_PC6S)
8801 #define F_PC6S    V_PC6S(1U)
8804 #define V_PC7S(x) ((x) << S_PC7S)
8805 #define F_PC7S    V_PC7S(1U)
8808 #define V_PME0(x) ((x) << S_PME0)
8809 #define F_PME0    V_PME0(1U)
8812 #define V_PME1(x) ((x) << S_PME1)
8813 #define F_PME1    V_PME1(1U)
8816 #define V_PME2(x) ((x) << S_PME2)
8817 #define F_PME2    V_PME2(1U)
8820 #define V_PME3(x) ((x) << S_PME3)
8821 #define F_PME3    V_PME3(1U)
8824 #define V_PME4(x) ((x) << S_PME4)
8825 #define F_PME4    V_PME4(1U)
8828 #define V_PME5(x) ((x) << S_PME5)
8829 #define F_PME5    V_PME5(1U)
8832 #define V_PME6(x) ((x) << S_PME6)
8833 #define F_PME6    V_PME6(1U)
8836 #define V_PME7(x) ((x) << S_PME7)
8837 #define F_PME7    V_PME7(1U)
8842 #define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
8843 #define F_VPD_DYNAMIC_CGEN    V_VPD_DYNAMIC_CGEN(1U)
8846 #define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
8847 #define F_MA_DYNAMIC_CGEN    V_MA_DYNAMIC_CGEN(1U)
8850 #define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
8851 #define F_TAGQ_DYNAMIC_CGEN    V_TAGQ_DYNAMIC_CGEN(1U)
8854 #define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
8855 #define F_REQCTL_DYNAMIC_CGEN    V_REQCTL_DYNAMIC_CGEN(1U)
8858 #define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
8859 #define F_RSPDATAPROC_DYNAMIC_CGEN    V_RSPDATAPROC_DYNAMIC_CGEN(1U)
8862 #define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
8863 #define F_RSPRDQ_DYNAMIC_CGEN    V_RSPRDQ_DYNAMIC_CGEN(1U)
8866 #define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
8867 #define F_RSPIPIF_DYNAMIC_CGEN    V_RSPIPIF_DYNAMIC_CGEN(1U)
8870 #define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
8871 #define F_HMA_STATIC_CGEN    V_HMA_STATIC_CGEN(1U)
8874 #define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
8875 #define F_HMA_DYNAMIC_CGEN    V_HMA_DYNAMIC_CGEN(1U)
8878 #define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
8879 #define F_CMD_STATIC_CGEN    V_CMD_STATIC_CGEN(1U)
8882 #define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
8883 #define F_CMD_DYNAMIC_CGEN    V_CMD_DYNAMIC_CGEN(1U)
8886 #define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
8887 #define F_DMA_STATIC_CGEN    V_DMA_STATIC_CGEN(1U)
8890 #define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
8891 #define F_DMA_DYNAMIC_CGEN    V_DMA_DYNAMIC_CGEN(1U)
8894 #define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
8895 #define F_VFID_SLEEPSTATUS    V_VFID_SLEEPSTATUS(1U)
8898 #define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
8899 #define F_VC1_SLEEPSTATUS    V_VC1_SLEEPSTATUS(1U)
8902 #define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
8903 #define F_STI_SLEEPSTATUS    V_STI_SLEEPSTATUS(1U)
8906 #define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
8907 #define F_VFID_SLEEPREQ    V_VFID_SLEEPREQ(1U)
8909 #define S_VC1_SLEEPREQ    1
8910 #define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
8911 #define F_VC1_SLEEPREQ    V_VC1_SLEEPREQ(1U)
8914 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
8915 #define F_STI_SLEEPREQ    V_STI_SLEEPREQ(1U)
8918 #define V_ARM_STATIC_CGEN(x) ((x) << S_ARM_STATIC_CGEN)
8919 #define F_ARM_STATIC_CGEN    V_ARM_STATIC_CGEN(1U)
8922 #define V_ARM_DYNAMIC_CGEN(x) ((x) << S_ARM_DYNAMIC_CGEN)
8923 #define F_ARM_DYNAMIC_CGEN    V_ARM_DYNAMIC_CGEN(1U)
8928 #define V_PTOI(x) ((x) << S_PTOI)
8929 #define F_PTOI    V_PTOI(1U)
8932 #define V_AENI(x) ((x) << S_AENI)
8933 #define F_AENI    V_AENI(1U)
8936 #define V_PC0I(x) ((x) << S_PC0I)
8937 #define F_PC0I    V_PC0I(1U)
8940 #define V_PC1I(x) ((x) << S_PC1I)
8941 #define F_PC1I    V_PC1I(1U)
8944 #define V_PC2I(x) ((x) << S_PC2I)
8945 #define F_PC2I    V_PC2I(1U)
8948 #define V_PC3I(x) ((x) << S_PC3I)
8949 #define F_PC3I    V_PC3I(1U)
8952 #define V_PC4I(x) ((x) << S_PC4I)
8953 #define F_PC4I    V_PC4I(1U)
8956 #define V_PC5I(x) ((x) << S_PC5I)
8957 #define F_PC5I    V_PC5I(1U)
8960 #define V_PC6I(x) ((x) << S_PC6I)
8961 #define F_PC6I    V_PC6I(1U)
8964 #define V_PC7I(x) ((x) << S_PC7I)
8965 #define F_PC7I    V_PC7I(1U)
8971 #define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
8972 #define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
8974 #define S_MAREQTIMEREN    1
8975 #define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
8976 #define F_MAREQTIMEREN    V_MAREQTIMEREN(1U)
8979 #define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
8980 #define F_MARSPTIMEREN    V_MARSPTIMEREN(1U)
8985 #define V_TOAK(x) ((x) << S_TOAK)
8986 #define F_TOAK    V_TOAK(1U)
8989 #define V_L1RS(x) ((x) << S_L1RS)
8990 #define F_L1RS    V_L1RS(1U)
8993 #define V_L23S(x) ((x) << S_L23S)
8994 #define F_L23S    V_L23S(1U)
8997 #define V_AL1S(x) ((x) << S_AL1S)
8998 #define F_AL1S    V_AL1S(1U)
9001 #define V_ALET(x) ((x) << S_ALET)
9002 #define F_ALET    V_ALET(1U)
9008 #define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
9009 #define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
9013 #define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
9014 #define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
9018 #define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
9019 #define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
9023 #define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
9024 #define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
9028 #define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
9029 #define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
9033 #define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
9034 #define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
9038 #define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
9039 #define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
9041 #define S_REQBURSTFREQUENCY    1
9043 #define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
9044 #define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
9047 #define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
9048 #define F_ENABLEVC1    V_ENABLEVC1(1U)
9054 #define V_CPM0(x) ((x) << S_CPM0)
9055 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
9059 #define V_CPM1(x) ((x) << S_CPM1)
9060 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
9064 #define V_CPM2(x) ((x) << S_CPM2)
9065 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
9069 #define V_CPM3(x) ((x) << S_CPM3)
9070 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
9074 #define V_CPM4(x) ((x) << S_CPM4)
9075 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
9079 #define V_CPM5(x) ((x) << S_CPM5)
9080 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
9084 #define V_CPM6(x) ((x) << S_CPM6)
9085 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
9089 #define V_CPM7(x) ((x) << S_CPM7)
9090 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
9094 #define V_OPM0(x) ((x) << S_OPM0)
9095 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
9099 #define V_OPM1(x) ((x) << S_OPM1)
9100 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
9104 #define V_OPM2(x) ((x) << S_OPM2)
9105 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
9109 #define V_OPM3(x) ((x) << S_OPM3)
9110 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
9114 #define V_OPM4(x) ((x) << S_OPM4)
9115 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
9119 #define V_OPM5(x) ((x) << S_OPM5)
9120 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
9124 #define V_OPM6(x) ((x) << S_OPM6)
9125 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
9129 #define V_OPM7(x) ((x) << S_OPM7)
9130 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
9136 #define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
9137 #define F_MST_DATAPATHPERR    V_MST_DATAPATHPERR(1U)
9140 #define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
9141 #define F_MST_RSPRDQPERR    V_MST_RSPRDQPERR(1U)
9144 #define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
9145 #define F_IP_RXPERR    V_IP_RXPERR(1U)
9148 #define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
9149 #define F_IP_BACKTXPERR    V_IP_BACKTXPERR(1U)
9152 #define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
9153 #define F_IP_FRONTTXPERR    V_IP_FRONTTXPERR(1U)
9156 #define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
9157 #define F_TRGT1_FIDLKUPHDRPERR    V_TRGT1_FIDLKUPHDRPERR(1U)
9160 #define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
9161 #define F_TRGT1_ALINDDATAPERR    V_TRGT1_ALINDDATAPERR(1U)
9164 #define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
9165 #define F_TRGT1_UNALINDATAPERR    V_TRGT1_UNALINDATAPERR(1U)
9168 #define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
9169 #define F_TRGT1_REQDATAPERR    V_TRGT1_REQDATAPERR(1U)
9172 #define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
9173 #define F_TRGT1_REQHDRPERR    V_TRGT1_REQHDRPERR(1U)
9176 #define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
9177 #define F_IPRXDATA_VC1PERR    V_IPRXDATA_VC1PERR(1U)
9180 #define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
9181 #define F_IPRXDATA_VC0PERR    V_IPRXDATA_VC0PERR(1U)
9184 #define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
9185 #define F_IPRXHDR_VC1PERR    V_IPRXHDR_VC1PERR(1U)
9188 #define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
9189 #define F_IPRXHDR_VC0PERR    V_IPRXHDR_VC0PERR(1U)
9192 #define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
9193 #define F_MA_RSPDATAPERR    V_MA_RSPDATAPERR(1U)
9196 #define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
9197 #define F_MA_CPLTAGQPERR    V_MA_CPLTAGQPERR(1U)
9200 #define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
9201 #define F_MA_REQTAGQPERR    V_MA_REQTAGQPERR(1U)
9204 #define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
9205 #define F_PIOREQ_BAR2CTLPERR    V_PIOREQ_BAR2CTLPERR(1U)
9208 #define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
9209 #define F_PIOREQ_MEMCTLPERR    V_PIOREQ_MEMCTLPERR(1U)
9212 #define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
9213 #define F_PIOREQ_PLMCTLPERR    V_PIOREQ_PLMCTLPERR(1U)
9216 #define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
9217 #define F_PIOREQ_BAR2DATAPERR    V_PIOREQ_BAR2DATAPERR(1U)
9220 #define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
9221 #define F_PIOREQ_MEMDATAPERR    V_PIOREQ_MEMDATAPERR(1U)
9224 #define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
9225 #define F_PIOREQ_PLMDATAPERR    V_PIOREQ_PLMDATAPERR(1U)
9228 #define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
9229 #define F_PIOCPL_CTLPERR    V_PIOCPL_CTLPERR(1U)
9231 #define S_PIOCPL_DATAPERR    1
9232 #define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
9233 #define F_PIOCPL_DATAPERR    V_PIOCPL_DATAPERR(1U)
9236 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
9237 #define F_PIOCPL_PLMRSPPERR    V_PIOCPL_PLMRSPPERR(1U)
9240 #define V_MA_RSPCTLPERR(x) ((x) << S_MA_RSPCTLPERR)
9241 #define F_MA_RSPCTLPERR    V_MA_RSPCTLPERR(1U)
9244 #define V_T6_IPRXDATA_VC0PERR(x) ((x) << S_T6_IPRXDATA_VC0PERR)
9245 #define F_T6_IPRXDATA_VC0PERR    V_T6_IPRXDATA_VC0PERR(1U)
9248 #define V_T6_IPRXHDR_VC0PERR(x) ((x) << S_T6_IPRXHDR_VC0PERR)
9249 #define F_T6_IPRXHDR_VC0PERR    V_T6_IPRXHDR_VC0PERR(1U)
9252 #define V_PIOCPL_VDMTXCTLPERR(x) ((x) << S_PIOCPL_VDMTXCTLPERR)
9253 #define F_PIOCPL_VDMTXCTLPERR    V_PIOCPL_VDMTXCTLPERR(1U)
9256 #define V_PIOCPL_VDMTXDATAPERR(x) ((x) << S_PIOCPL_VDMTXDATAPERR)
9257 #define F_PIOCPL_VDMTXDATAPERR    V_PIOCPL_VDMTXDATAPERR(1U)
9260 #define V_TGT1_MEM_PERR(x) ((x) << S_TGT1_MEM_PERR)
9261 #define F_TGT1_MEM_PERR    V_TGT1_MEM_PERR(1U)
9264 #define V_TGT2_MEM_PERR(x) ((x) << S_TGT2_MEM_PERR)
9265 #define F_TGT2_MEM_PERR    V_TGT2_MEM_PERR(1U)
9271 #define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
9272 #define F_CPLSTATUSINTEN    V_CPLSTATUSINTEN(1U)
9275 #define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
9276 #define F_REQTIMEOUTINTEN    V_REQTIMEOUTINTEN(1U)
9279 #define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
9280 #define F_DISABLEDINTEN    V_DISABLEDINTEN(1U)
9283 #define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
9284 #define F_RSPDROPFLRINTEN    V_RSPDROPFLRINTEN(1U)
9287 #define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
9288 #define F_REQUNDERFLRINTEN    V_REQUNDERFLRINTEN(1U)
9291 #define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
9292 #define F_CPLSTATUSLOGEN    V_CPLSTATUSLOGEN(1U)
9295 #define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
9296 #define F_TIMEOUTLOGEN    V_TIMEOUTLOGEN(1U)
9299 #define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
9300 #define F_DISABLEDLOGEN    V_DISABLEDLOGEN(1U)
9302 #define S_RSPDROPFLRLOGEN    1
9303 #define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
9304 #define F_RSPDROPFLRLOGEN    V_RSPDROPFLRLOGEN(1U)
9307 #define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
9308 #define F_REQUNDERFLRLOGEN    V_REQUNDERFLRLOGEN(1U)
9314 #define V_REQTAG(x) ((x) << S_REQTAG)
9315 #define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
9319 #define V_CID(x) ((x) << S_CID)
9320 #define G_CID(x) (((x) >> S_CID) & M_CID)
9324 #define V_CHNUM(x) ((x) << S_CHNUM)
9325 #define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
9329 #define V_BYTELEN(x) ((x) << S_BYTELEN)
9330 #define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
9334 #define V_REASON(x) ((x) << S_REASON)
9335 #define G_REASON(x) (((x) >> S_REASON) & M_REASON)
9339 #define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
9340 #define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
9345 #define V_LOGVALID(x) ((x) << S_LOGVALID)
9346 #define F_LOGVALID    V_LOGVALID(1U)
9350 #define V_ADDR10B(x) ((x) << S_ADDR10B)
9351 #define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
9355 #define V_REQVFID(x) ((x) << S_REQVFID)
9356 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
9360 #define V_T6_ADDR10B(x) ((x) << S_T6_ADDR10B)
9361 #define G_T6_ADDR10B(x) (((x) >> S_T6_ADDR10B) & M_T6_ADDR10B)
9365 #define V_T6_REQVFID(x) ((x) << S_T6_REQVFID)
9366 #define G_T6_REQVFID(x) (((x) >> S_T6_REQVFID) & M_T6_REQVFID)
9370 #define V_LOGADDR10B(x) ((x) << S_LOGADDR10B)
9371 #define G_LOGADDR10B(x) (((x) >> S_LOGADDR10B) & M_LOGADDR10B)
9375 #define V_LOGREQVFID(x) ((x) << S_LOGREQVFID)
9376 #define G_LOGREQVFID(x) (((x) >> S_LOGREQVFID) & M_LOGREQVFID)
9384 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
9385 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
9389 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
9390 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
9394 #define V_T6_PDEBUGSELH(x) ((x) << S_T6_PDEBUGSELH)
9395 #define G_T6_PDEBUGSELH(x) (((x) >> S_T6_PDEBUGSELH) & M_T6_PDEBUGSELH)
9399 #define V_T6_PDEBUGSELL(x) ((x) << S_T6_PDEBUGSELL)
9400 #define G_T6_PDEBUGSELL(x) (((x) >> S_T6_PDEBUGSELL) & M_T6_PDEBUGSELL)
9404 #define V_T7_1_PDEBUGSELH(x) ((x) << S_T7_1_PDEBUGSELH)
9405 #define G_T7_1_PDEBUGSELH(x) (((x) >> S_T7_1_PDEBUGSELH) & M_T7_1_PDEBUGSELH)
9409 #define V_T7_1_PDEBUGSELL(x) ((x) << S_T7_1_PDEBUGSELL)
9410 #define G_T7_1_PDEBUGSELL(x) (((x) >> S_T7_1_PDEBUGSELL) & M_T7_1_PDEBUGSELL)
9418 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
9419 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
9423 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
9424 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
9432 #define V_CH3(x) ((x) << S_CH3)
9433 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
9437 #define V_CH2(x) ((x) << S_CH2)
9438 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
9442 #define V_CH1(x) ((x) << S_CH1)
9443 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
9447 #define V_CH0(x) ((x) << S_CH0)
9448 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
9460 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
9461 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
9465 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
9466 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
9470 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
9471 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
9475 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
9476 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
9485 #define V_CH0_READ(x) ((x) << S_CH0_READ)
9486 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
9490 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
9491 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
9495 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
9496 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
9503 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
9504 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
9508 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
9509 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
9515 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
9516 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
9520 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
9521 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
9527 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
9528 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
9532 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
9533 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
9544 #define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
9545 #define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
9558 #define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
9559 #define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
9566 #define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
9567 #define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
9576 #define V_SOURCE(x) ((x) << S_SOURCE)
9577 #define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
9581 #define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
9582 #define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
9585 #define V_DBI_CS2(x) ((x) << S_DBI_CS2)
9586 #define F_DBI_CS2    V_DBI_CS2(1U)
9590 #define V_DBI_PF(x) ((x) << S_DBI_PF)
9591 #define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
9594 #define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
9595 #define F_PL_TOVFVLD    V_PL_TOVFVLD(1U)
9599 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
9600 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
9604 #define V_T6_SOURCE(x) ((x) << S_T6_SOURCE)
9605 #define G_T6_SOURCE(x) (((x) >> S_T6_SOURCE) & M_T6_SOURCE)
9609 #define V_T6_DBI_WRITE(x) ((x) << S_T6_DBI_WRITE)
9610 #define G_T6_DBI_WRITE(x) (((x) >> S_T6_DBI_WRITE) & M_T6_DBI_WRITE)
9613 #define V_T6_DBI_CS2(x) ((x) << S_T6_DBI_CS2)
9614 #define F_T6_DBI_CS2    V_T6_DBI_CS2(1U)
9618 #define V_T6_DBI_PF(x) ((x) << S_T6_DBI_PF)
9619 #define G_T6_DBI_PF(x) (((x) >> S_T6_DBI_PF) & M_T6_DBI_PF)
9622 #define V_T6_PL_TOVFVLD(x) ((x) << S_T6_PL_TOVFVLD)
9623 #define F_T6_PL_TOVFVLD    V_T6_PL_TOVFVLD(1U)
9627 #define V_T6_PL_TOVF(x) ((x) << S_T6_PL_TOVF)
9628 #define G_T6_PL_TOVF(x) (((x) >> S_T6_PL_TOVF) & M_T6_PL_TOVF)
9650 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
9651 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
9655 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
9656 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
9660 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
9661 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
9667 #define V_PB_SEL(x) ((x) << S_PB_SEL)
9668 #define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
9672 #define V_PB_SELREG(x) ((x) << S_PB_SELREG)
9673 #define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
9677 #define V_PB_FUNC(x) ((x) << S_PB_FUNC)
9678 #define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
9684 #define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
9685 #define F_CFGINITCOEFFDONESEEN    V_CFGINITCOEFFDONESEEN(1U)
9688 #define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
9689 #define F_CFGINITCOEFFDONE    V_CFGINITCOEFFDONE(1U)
9692 #define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
9693 #define F_XMLH_LINK_UP    V_XMLH_LINK_UP(1U)
9696 #define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
9697 #define F_PM_LINKST_IN_L0S    V_PM_LINKST_IN_L0S(1U)
9700 #define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
9701 #define F_PM_LINKST_IN_L1    V_PM_LINKST_IN_L1(1U)
9704 #define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
9705 #define F_PM_LINKST_IN_L2    V_PM_LINKST_IN_L2(1U)
9708 #define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
9709 #define F_PM_LINKST_L2_EXIT    V_PM_LINKST_L2_EXIT(1U)
9712 #define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
9713 #define F_XMLH_IN_RL0S    V_XMLH_IN_RL0S(1U)
9716 #define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
9717 #define F_XMLH_LTSSM_STATE_RCVRY_EQ    V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
9721 #define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
9722 #define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
9726 #define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
9727 #define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
9732 #define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
9733 #define F_LNH_RXSTATEDONE    V_LNH_RXSTATEDONE(1U)
9736 #define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
9737 #define F_LNH_RXSTATEREQ    V_LNH_RXSTATEREQ(1U)
9741 #define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
9742 #define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
9745 #define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
9746 #define F_LNG_RXSTATEDONE    V_LNG_RXSTATEDONE(1U)
9749 #define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
9750 #define F_LNG_RXSTATEREQ    V_LNG_RXSTATEREQ(1U)
9754 #define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
9755 #define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
9758 #define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
9759 #define F_LNF_RXSTATEDONE    V_LNF_RXSTATEDONE(1U)
9762 #define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
9763 #define F_LNF_RXSTATEREQ    V_LNF_RXSTATEREQ(1U)
9767 #define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
9768 #define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
9771 #define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
9772 #define F_LNE_RXSTATEDONE    V_LNE_RXSTATEDONE(1U)
9775 #define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
9776 #define F_LNE_RXSTATEREQ    V_LNE_RXSTATEREQ(1U)
9780 #define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
9781 #define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
9784 #define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
9785 #define F_LND_RXSTATEDONE    V_LND_RXSTATEDONE(1U)
9788 #define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
9789 #define F_LND_RXSTATEREQ    V_LND_RXSTATEREQ(1U)
9793 #define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
9794 #define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
9797 #define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
9798 #define F_LNC_RXSTATEDONE    V_LNC_RXSTATEDONE(1U)
9801 #define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
9802 #define F_LNC_RXSTATEREQ    V_LNC_RXSTATEREQ(1U)
9806 #define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
9807 #define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
9810 #define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
9811 #define F_LNB_RXSTATEDONE    V_LNB_RXSTATEDONE(1U)
9814 #define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
9815 #define F_LNB_RXSTATEREQ    V_LNB_RXSTATEREQ(1U)
9819 #define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
9820 #define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
9823 #define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
9824 #define F_LNA_RXSTATEDONE    V_LNA_RXSTATEDONE(1U)
9827 #define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
9828 #define F_LNA_RXSTATEREQ    V_LNA_RXSTATEREQ(1U)
9832 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
9833 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
9836 #define V_REQ_LNH_RXSTATEDONE(x) ((x) << S_REQ_LNH_RXSTATEDONE)
9837 #define F_REQ_LNH_RXSTATEDONE    V_REQ_LNH_RXSTATEDONE(1U)
9840 #define V_REQ_LNH_RXSTATEREQ(x) ((x) << S_REQ_LNH_RXSTATEREQ)
9841 #define F_REQ_LNH_RXSTATEREQ    V_REQ_LNH_RXSTATEREQ(1U)
9845 #define V_REQ_LNH_RXPWRSTATE(x) ((x) << S_REQ_LNH_RXPWRSTATE)
9846 #define G_REQ_LNH_RXPWRSTATE(x) (((x) >> S_REQ_LNH_RXPWRSTATE) & M_REQ_LNH_RXPWRSTATE)
9849 #define V_REQ_LNG_RXSTATEDONE(x) ((x) << S_REQ_LNG_RXSTATEDONE)
9850 #define F_REQ_LNG_RXSTATEDONE    V_REQ_LNG_RXSTATEDONE(1U)
9853 #define V_REQ_LNG_RXSTATEREQ(x) ((x) << S_REQ_LNG_RXSTATEREQ)
9854 #define F_REQ_LNG_RXSTATEREQ    V_REQ_LNG_RXSTATEREQ(1U)
9858 #define V_REQ_LNG_RXPWRSTATE(x) ((x) << S_REQ_LNG_RXPWRSTATE)
9859 #define G_REQ_LNG_RXPWRSTATE(x) (((x) >> S_REQ_LNG_RXPWRSTATE) & M_REQ_LNG_RXPWRSTATE)
9862 #define V_REQ_LNF_RXSTATEDONE(x) ((x) << S_REQ_LNF_RXSTATEDONE)
9863 #define F_REQ_LNF_RXSTATEDONE    V_REQ_LNF_RXSTATEDONE(1U)
9866 #define V_REQ_LNF_RXSTATEREQ(x) ((x) << S_REQ_LNF_RXSTATEREQ)
9867 #define F_REQ_LNF_RXSTATEREQ    V_REQ_LNF_RXSTATEREQ(1U)
9871 #define V_REQ_LNF_RXPWRSTATE(x) ((x) << S_REQ_LNF_RXPWRSTATE)
9872 #define G_REQ_LNF_RXPWRSTATE(x) (((x) >> S_REQ_LNF_RXPWRSTATE) & M_REQ_LNF_RXPWRSTATE)
9875 #define V_REQ_LNE_RXSTATEDONE(x) ((x) << S_REQ_LNE_RXSTATEDONE)
9876 #define F_REQ_LNE_RXSTATEDONE    V_REQ_LNE_RXSTATEDONE(1U)
9879 #define V_REQ_LNE_RXSTATEREQ(x) ((x) << S_REQ_LNE_RXSTATEREQ)
9880 #define F_REQ_LNE_RXSTATEREQ    V_REQ_LNE_RXSTATEREQ(1U)
9884 #define V_REQ_LNE_RXPWRSTATE(x) ((x) << S_REQ_LNE_RXPWRSTATE)
9885 #define G_REQ_LNE_RXPWRSTATE(x) (((x) >> S_REQ_LNE_RXPWRSTATE) & M_REQ_LNE_RXPWRSTATE)
9888 #define V_REQ_LND_RXSTATEDONE(x) ((x) << S_REQ_LND_RXSTATEDONE)
9889 #define F_REQ_LND_RXSTATEDONE    V_REQ_LND_RXSTATEDONE(1U)
9892 #define V_REQ_LND_RXSTATEREQ(x) ((x) << S_REQ_LND_RXSTATEREQ)
9893 #define F_REQ_LND_RXSTATEREQ    V_REQ_LND_RXSTATEREQ(1U)
9897 #define V_REQ_LND_RXPWRSTATE(x) ((x) << S_REQ_LND_RXPWRSTATE)
9898 #define G_REQ_LND_RXPWRSTATE(x) (((x) >> S_REQ_LND_RXPWRSTATE) & M_REQ_LND_RXPWRSTATE)
9901 #define V_REQ_LNC_RXSTATEDONE(x) ((x) << S_REQ_LNC_RXSTATEDONE)
9902 #define F_REQ_LNC_RXSTATEDONE    V_REQ_LNC_RXSTATEDONE(1U)
9905 #define V_REQ_LNC_RXSTATEREQ(x) ((x) << S_REQ_LNC_RXSTATEREQ)
9906 #define F_REQ_LNC_RXSTATEREQ    V_REQ_LNC_RXSTATEREQ(1U)
9910 #define V_REQ_LNC_RXPWRSTATE(x) ((x) << S_REQ_LNC_RXPWRSTATE)
9911 #define G_REQ_LNC_RXPWRSTATE(x) (((x) >> S_REQ_LNC_RXPWRSTATE) & M_REQ_LNC_RXPWRSTATE)
9914 #define V_REQ_LNB_RXSTATEDONE(x) ((x) << S_REQ_LNB_RXSTATEDONE)
9915 #define F_REQ_LNB_RXSTATEDONE    V_REQ_LNB_RXSTATEDONE(1U)
9918 #define V_REQ_LNB_RXSTATEREQ(x) ((x) << S_REQ_LNB_RXSTATEREQ)
9919 #define F_REQ_LNB_RXSTATEREQ    V_REQ_LNB_RXSTATEREQ(1U)
9923 #define V_REQ_LNB_RXPWRSTATE(x) ((x) << S_REQ_LNB_RXPWRSTATE)
9924 #define G_REQ_LNB_RXPWRSTATE(x) (((x) >> S_REQ_LNB_RXPWRSTATE) & M_REQ_LNB_RXPWRSTATE)
9927 #define V_REQ_LNA_RXSTATEDONE(x) ((x) << S_REQ_LNA_RXSTATEDONE)
9928 #define F_REQ_LNA_RXSTATEDONE    V_REQ_LNA_RXSTATEDONE(1U)
9931 #define V_REQ_LNA_RXSTATEREQ(x) ((x) << S_REQ_LNA_RXSTATEREQ)
9932 #define F_REQ_LNA_RXSTATEREQ    V_REQ_LNA_RXSTATEREQ(1U)
9936 #define V_REQ_LNA_RXPWRSTATE(x) ((x) << S_REQ_LNA_RXPWRSTATE)
9937 #define G_REQ_LNA_RXPWRSTATE(x) (((x) >> S_REQ_LNA_RXPWRSTATE) & M_REQ_LNA_RXPWRSTATE)
9943 #define V_T5_LNH_RXPWRSTATE(x) ((x) << S_T5_LNH_RXPWRSTATE)
9944 #define G_T5_LNH_RXPWRSTATE(x) (((x) >> S_T5_LNH_RXPWRSTATE) & M_T5_LNH_RXPWRSTATE)
9948 #define V_T5_LNG_RXPWRSTATE(x) ((x) << S_T5_LNG_RXPWRSTATE)
9949 #define G_T5_LNG_RXPWRSTATE(x) (((x) >> S_T5_LNG_RXPWRSTATE) & M_T5_LNG_RXPWRSTATE)
9953 #define V_T5_LNF_RXPWRSTATE(x) ((x) << S_T5_LNF_RXPWRSTATE)
9954 #define G_T5_LNF_RXPWRSTATE(x) (((x) >> S_T5_LNF_RXPWRSTATE) & M_T5_LNF_RXPWRSTATE)
9958 #define V_T5_LNE_RXPWRSTATE(x) ((x) << S_T5_LNE_RXPWRSTATE)
9959 #define G_T5_LNE_RXPWRSTATE(x) (((x) >> S_T5_LNE_RXPWRSTATE) & M_T5_LNE_RXPWRSTATE)
9963 #define V_T5_LND_RXPWRSTATE(x) ((x) << S_T5_LND_RXPWRSTATE)
9964 #define G_T5_LND_RXPWRSTATE(x) (((x) >> S_T5_LND_RXPWRSTATE) & M_T5_LND_RXPWRSTATE)
9968 #define V_T5_LNC_RXPWRSTATE(x) ((x) << S_T5_LNC_RXPWRSTATE)
9969 #define G_T5_LNC_RXPWRSTATE(x) (((x) >> S_T5_LNC_RXPWRSTATE) & M_T5_LNC_RXPWRSTATE)
9973 #define V_T5_LNB_RXPWRSTATE(x) ((x) << S_T5_LNB_RXPWRSTATE)
9974 #define G_T5_LNB_RXPWRSTATE(x) (((x) >> S_T5_LNB_RXPWRSTATE) & M_T5_LNB_RXPWRSTATE)
9978 #define V_T5_LNA_RXPWRSTATE(x) ((x) << S_T5_LNA_RXPWRSTATE)
9979 #define G_T5_LNA_RXPWRSTATE(x) (((x) >> S_T5_LNA_RXPWRSTATE) & M_T5_LNA_RXPWRSTATE)
9983 #define V_CUR_LNH_RXPWRSTATE(x) ((x) << S_CUR_LNH_RXPWRSTATE)
9984 #define G_CUR_LNH_RXPWRSTATE(x) (((x) >> S_CUR_LNH_RXPWRSTATE) & M_CUR_LNH_RXPWRSTATE)
9988 #define V_CUR_LNG_RXPWRSTATE(x) ((x) << S_CUR_LNG_RXPWRSTATE)
9989 #define G_CUR_LNG_RXPWRSTATE(x) (((x) >> S_CUR_LNG_RXPWRSTATE) & M_CUR_LNG_RXPWRSTATE)
9993 #define V_CUR_LNF_RXPWRSTATE(x) ((x) << S_CUR_LNF_RXPWRSTATE)
9994 #define G_CUR_LNF_RXPWRSTATE(x) (((x) >> S_CUR_LNF_RXPWRSTATE) & M_CUR_LNF_RXPWRSTATE)
9998 #define V_CUR_LNE_RXPWRSTATE(x) ((x) << S_CUR_LNE_RXPWRSTATE)
9999 #define G_CUR_LNE_RXPWRSTATE(x) (((x) >> S_CUR_LNE_RXPWRSTATE) & M_CUR_LNE_RXPWRSTATE)
10003 #define V_CUR_LND_RXPWRSTATE(x) ((x) << S_CUR_LND_RXPWRSTATE)
10004 #define G_CUR_LND_RXPWRSTATE(x) (((x) >> S_CUR_LND_RXPWRSTATE) & M_CUR_LND_RXPWRSTATE)
10008 #define V_CUR_LNC_RXPWRSTATE(x) ((x) << S_CUR_LNC_RXPWRSTATE)
10009 #define G_CUR_LNC_RXPWRSTATE(x) (((x) >> S_CUR_LNC_RXPWRSTATE) & M_CUR_LNC_RXPWRSTATE)
10013 #define V_CUR_LNB_RXPWRSTATE(x) ((x) << S_CUR_LNB_RXPWRSTATE)
10014 #define G_CUR_LNB_RXPWRSTATE(x) (((x) >> S_CUR_LNB_RXPWRSTATE) & M_CUR_LNB_RXPWRSTATE)
10018 #define V_CUR_LNA_RXPWRSTATE(x) ((x) << S_CUR_LNA_RXPWRSTATE)
10019 #define G_CUR_LNA_RXPWRSTATE(x) (((x) >> S_CUR_LNA_RXPWRSTATE) & M_CUR_LNA_RXPWRSTATE)
10025 #define V_LND_STAT(x) ((x) << S_LND_STAT)
10026 #define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
10030 #define V_LND_CMD(x) ((x) << S_LND_CMD)
10031 #define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
10035 #define V_LNC_STAT(x) ((x) << S_LNC_STAT)
10036 #define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
10040 #define V_LNC_CMD(x) ((x) << S_LNC_CMD)
10041 #define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
10045 #define V_LNB_STAT(x) ((x) << S_LNB_STAT)
10046 #define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
10050 #define V_LNB_CMD(x) ((x) << S_LNB_CMD)
10051 #define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
10055 #define V_LNA_STAT(x) ((x) << S_LNA_STAT)
10056 #define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
10060 #define V_LNA_CMD(x) ((x) << S_LNA_CMD)
10061 #define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
10067 #define V_LNH_STAT(x) ((x) << S_LNH_STAT)
10068 #define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
10072 #define V_LNH_CMD(x) ((x) << S_LNH_CMD)
10073 #define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
10077 #define V_LNG_STAT(x) ((x) << S_LNG_STAT)
10078 #define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
10082 #define V_LNG_CMD(x) ((x) << S_LNG_CMD)
10083 #define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
10087 #define V_LNF_STAT(x) ((x) << S_LNF_STAT)
10088 #define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
10092 #define V_LNF_CMD(x) ((x) << S_LNF_CMD)
10093 #define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
10097 #define V_LNE_STAT(x) ((x) << S_LNE_STAT)
10098 #define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
10102 #define V_LNE_CMD(x) ((x) << S_LNE_CMD)
10103 #define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
10109 #define V_LANE1LF(x) ((x) << S_LANE1LF)
10110 #define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
10114 #define V_LANE1FS(x) ((x) << S_LANE1FS)
10115 #define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
10119 #define V_LANE0LF(x) ((x) << S_LANE0LF)
10120 #define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
10124 #define V_LANE0FS(x) ((x) << S_LANE0FS)
10125 #define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
10131 #define V_LANE3LF(x) ((x) << S_LANE3LF)
10132 #define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
10136 #define V_LANE3FS(x) ((x) << S_LANE3FS)
10137 #define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
10141 #define V_LANE2LF(x) ((x) << S_LANE2LF)
10142 #define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
10146 #define V_LANE2FS(x) ((x) << S_LANE2FS)
10147 #define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
10153 #define V_LANE5LF(x) ((x) << S_LANE5LF)
10154 #define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
10158 #define V_LANE5FS(x) ((x) << S_LANE5FS)
10159 #define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
10163 #define V_LANE4LF(x) ((x) << S_LANE4LF)
10164 #define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
10168 #define V_LANE4FS(x) ((x) << S_LANE4FS)
10169 #define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
10175 #define V_LANE7LF(x) ((x) << S_LANE7LF)
10176 #define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
10180 #define V_LANE7FS(x) ((x) << S_LANE7FS)
10181 #define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
10185 #define V_LANE6LF(x) ((x) << S_LANE6LF)
10186 #define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
10190 #define V_LANE6FS(x) ((x) << S_LANE6FS)
10191 #define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
10196 #define V_COEFFDONE(x) ((x) << S_COEFFDONE)
10197 #define F_COEFFDONE    V_COEFFDONE(1U)
10201 #define V_COEFFLANE(x) ((x) << S_COEFFLANE)
10202 #define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
10205 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
10206 #define F_COEFFSTART    V_COEFFSTART(1U)
10210 #define V_T6_COEFFLANE(x) ((x) << S_T6_COEFFLANE)
10211 #define G_T6_COEFFLANE(x) (((x) >> S_T6_COEFFLANE) & M_T6_COEFFLANE)
10217 #define V_COEFF(x) ((x) << S_COEFF)
10218 #define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
10223 #define V_PHYENABLE(x) ((x) << S_PHYENABLE)
10224 #define F_PHYENABLE    V_PHYENABLE(1U)
10228 #define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
10229 #define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
10236 #define V_X8_SW_EN(x) ((x) << S_X8_SW_EN)
10237 #define F_X8_SW_EN    V_X8_SW_EN(1U)
10241 #define V_SWITCHCFG(x) ((x) << S_SWITCHCFG)
10242 #define G_SWITCHCFG(x) (((x) >> S_SWITCHCFG) & M_SWITCHCFG)
10246 #define V_STATIC_SPARE2(x) ((x) << S_STATIC_SPARE2)
10247 #define G_STATIC_SPARE2(x) (((x) >> S_STATIC_SPARE2) & M_STATIC_SPARE2)
10253 #define V_KDB_PF_LEN(x) ((x) << S_KDB_PF_LEN)
10254 #define G_KDB_PF_LEN(x) (((x) >> S_KDB_PF_LEN) & M_KDB_PF_LEN)
10258 #define V_KDB_PF_BASEADDR(x) ((x) << S_KDB_PF_BASEADDR)
10259 #define G_KDB_PF_BASEADDR(x) (((x) >> S_KDB_PF_BASEADDR) & M_KDB_PF_BASEADDR)
10265 #define V_KDB_VF_LEN(x) ((x) << S_KDB_VF_LEN)
10266 #define G_KDB_VF_LEN(x) (((x) >> S_KDB_VF_LEN) & M_KDB_VF_LEN)
10270 #define V_KDB_VF_BASEADDR(x) ((x) << S_KDB_VF_BASEADDR)
10271 #define G_KDB_VF_BASEADDR(x) (((x) >> S_KDB_VF_BASEADDR) & M_KDB_VF_BASEADDR)
10277 #define V_KDB_VF_MODOFST(x) ((x) << S_KDB_VF_MODOFST)
10278 #define G_KDB_VF_MODOFST(x) (((x) >> S_KDB_VF_MODOFST) & M_KDB_VF_MODOFST)
10283 #define V_REQ_LNP_RXSTATEDONE(x) ((x) << S_REQ_LNP_RXSTATEDONE)
10284 #define F_REQ_LNP_RXSTATEDONE    V_REQ_LNP_RXSTATEDONE(1U)
10287 #define V_REQ_LNP_RXSTATEREQ(x) ((x) << S_REQ_LNP_RXSTATEREQ)
10288 #define F_REQ_LNP_RXSTATEREQ    V_REQ_LNP_RXSTATEREQ(1U)
10292 #define V_REQ_LNP_RXPWRSTATE(x) ((x) << S_REQ_LNP_RXPWRSTATE)
10293 #define G_REQ_LNP_RXPWRSTATE(x) (((x) >> S_REQ_LNP_RXPWRSTATE) & M_REQ_LNP_RXPWRSTATE)
10296 #define V_REQ_LNO_RXSTATEDONE(x) ((x) << S_REQ_LNO_RXSTATEDONE)
10297 #define F_REQ_LNO_RXSTATEDONE    V_REQ_LNO_RXSTATEDONE(1U)
10300 #define V_REQ_LNO_RXSTATEREQ(x) ((x) << S_REQ_LNO_RXSTATEREQ)
10301 #define F_REQ_LNO_RXSTATEREQ    V_REQ_LNO_RXSTATEREQ(1U)
10305 #define V_REQ_LNO_RXPWRSTATE(x) ((x) << S_REQ_LNO_RXPWRSTATE)
10306 #define G_REQ_LNO_RXPWRSTATE(x) (((x) >> S_REQ_LNO_RXPWRSTATE) & M_REQ_LNO_RXPWRSTATE)
10309 #define V_REQ_LNN_RXSTATEDONE(x) ((x) << S_REQ_LNN_RXSTATEDONE)
10310 #define F_REQ_LNN_RXSTATEDONE    V_REQ_LNN_RXSTATEDONE(1U)
10313 #define V_REQ_LNN_RXSTATEREQ(x) ((x) << S_REQ_LNN_RXSTATEREQ)
10314 #define F_REQ_LNN_RXSTATEREQ    V_REQ_LNN_RXSTATEREQ(1U)
10318 #define V_REQ_LNN_RXPWRSTATE(x) ((x) << S_REQ_LNN_RXPWRSTATE)
10319 #define G_REQ_LNN_RXPWRSTATE(x) (((x) >> S_REQ_LNN_RXPWRSTATE) & M_REQ_LNN_RXPWRSTATE)
10322 #define V_REQ_LNM_RXSTATEDONE(x) ((x) << S_REQ_LNM_RXSTATEDONE)
10323 #define F_REQ_LNM_RXSTATEDONE    V_REQ_LNM_RXSTATEDONE(1U)
10326 #define V_REQ_LNM_RXSTATEREQ(x) ((x) << S_REQ_LNM_RXSTATEREQ)
10327 #define F_REQ_LNM_RXSTATEREQ    V_REQ_LNM_RXSTATEREQ(1U)
10331 #define V_REQ_LNM_RXPWRSTATE(x) ((x) << S_REQ_LNM_RXPWRSTATE)
10332 #define G_REQ_LNM_RXPWRSTATE(x) (((x) >> S_REQ_LNM_RXPWRSTATE) & M_REQ_LNM_RXPWRSTATE)
10335 #define V_REQ_LNL_RXSTATEDONE(x) ((x) << S_REQ_LNL_RXSTATEDONE)
10336 #define F_REQ_LNL_RXSTATEDONE    V_REQ_LNL_RXSTATEDONE(1U)
10339 #define V_REQ_LNL_RXSTATEREQ(x) ((x) << S_REQ_LNL_RXSTATEREQ)
10340 #define F_REQ_LNL_RXSTATEREQ    V_REQ_LNL_RXSTATEREQ(1U)
10344 #define V_REQ_LNL_RXPWRSTATE(x) ((x) << S_REQ_LNL_RXPWRSTATE)
10345 #define G_REQ_LNL_RXPWRSTATE(x) (((x) >> S_REQ_LNL_RXPWRSTATE) & M_REQ_LNL_RXPWRSTATE)
10348 #define V_REQ_LNK_RXSTATEDONE(x) ((x) << S_REQ_LNK_RXSTATEDONE)
10349 #define F_REQ_LNK_RXSTATEDONE    V_REQ_LNK_RXSTATEDONE(1U)
10352 #define V_REQ_LNK_RXSTATEREQ(x) ((x) << S_REQ_LNK_RXSTATEREQ)
10353 #define F_REQ_LNK_RXSTATEREQ    V_REQ_LNK_RXSTATEREQ(1U)
10357 #define V_REQ_LNK_RXPWRSTATE(x) ((x) << S_REQ_LNK_RXPWRSTATE)
10358 #define G_REQ_LNK_RXPWRSTATE(x) (((x) >> S_REQ_LNK_RXPWRSTATE) & M_REQ_LNK_RXPWRSTATE)
10361 #define V_REQ_LNJ_RXSTATEDONE(x) ((x) << S_REQ_LNJ_RXSTATEDONE)
10362 #define F_REQ_LNJ_RXSTATEDONE    V_REQ_LNJ_RXSTATEDONE(1U)
10365 #define V_REQ_LNJ_RXSTATEREQ(x) ((x) << S_REQ_LNJ_RXSTATEREQ)
10366 #define F_REQ_LNJ_RXSTATEREQ    V_REQ_LNJ_RXSTATEREQ(1U)
10370 #define V_REQ_LNJ_RXPWRSTATE(x) ((x) << S_REQ_LNJ_RXPWRSTATE)
10371 #define G_REQ_LNJ_RXPWRSTATE(x) (((x) >> S_REQ_LNJ_RXPWRSTATE) & M_REQ_LNJ_RXPWRSTATE)
10374 #define V_REQ_LNI_RXSTATEDONE(x) ((x) << S_REQ_LNI_RXSTATEDONE)
10375 #define F_REQ_LNI_RXSTATEDONE    V_REQ_LNI_RXSTATEDONE(1U)
10378 #define V_REQ_LNI_RXSTATEREQ(x) ((x) << S_REQ_LNI_RXSTATEREQ)
10379 #define F_REQ_LNI_RXSTATEREQ    V_REQ_LNI_RXSTATEREQ(1U)
10383 #define V_REQ_LNI_RXPWRSTATE(x) ((x) << S_REQ_LNI_RXPWRSTATE)
10384 #define G_REQ_LNI_RXPWRSTATE(x) (((x) >> S_REQ_LNI_RXPWRSTATE) & M_REQ_LNI_RXPWRSTATE)
10390 #define V_CUR_LNP_RXPWRSTATE(x) ((x) << S_CUR_LNP_RXPWRSTATE)
10391 #define G_CUR_LNP_RXPWRSTATE(x) (((x) >> S_CUR_LNP_RXPWRSTATE) & M_CUR_LNP_RXPWRSTATE)
10395 #define V_CUR_LNO_RXPWRSTATE(x) ((x) << S_CUR_LNO_RXPWRSTATE)
10396 #define G_CUR_LNO_RXPWRSTATE(x) (((x) >> S_CUR_LNO_RXPWRSTATE) & M_CUR_LNO_RXPWRSTATE)
10400 #define V_CUR_LNN_RXPWRSTATE(x) ((x) << S_CUR_LNN_RXPWRSTATE)
10401 #define G_CUR_LNN_RXPWRSTATE(x) (((x) >> S_CUR_LNN_RXPWRSTATE) & M_CUR_LNN_RXPWRSTATE)
10405 #define V_CUR_LNM_RXPWRSTATE(x) ((x) << S_CUR_LNM_RXPWRSTATE)
10406 #define G_CUR_LNM_RXPWRSTATE(x) (((x) >> S_CUR_LNM_RXPWRSTATE) & M_CUR_LNM_RXPWRSTATE)
10410 #define V_CUR_LNL_RXPWRSTATE(x) ((x) << S_CUR_LNL_RXPWRSTATE)
10411 #define G_CUR_LNL_RXPWRSTATE(x) (((x) >> S_CUR_LNL_RXPWRSTATE) & M_CUR_LNL_RXPWRSTATE)
10415 #define V_CUR_LNK_RXPWRSTATE(x) ((x) << S_CUR_LNK_RXPWRSTATE)
10416 #define G_CUR_LNK_RXPWRSTATE(x) (((x) >> S_CUR_LNK_RXPWRSTATE) & M_CUR_LNK_RXPWRSTATE)
10420 #define V_CUR_LNJ_RXPWRSTATE(x) ((x) << S_CUR_LNJ_RXPWRSTATE)
10421 #define G_CUR_LNJ_RXPWRSTATE(x) (((x) >> S_CUR_LNJ_RXPWRSTATE) & M_CUR_LNJ_RXPWRSTATE)
10425 #define V_CUR_LNI_RXPWRSTATE(x) ((x) << S_CUR_LNI_RXPWRSTATE)
10426 #define G_CUR_LNI_RXPWRSTATE(x) (((x) >> S_CUR_LNI_RXPWRSTATE) & M_CUR_LNI_RXPWRSTATE)
10432 #define V_LNL_STAT(x) ((x) << S_LNL_STAT)
10433 #define G_LNL_STAT(x) (((x) >> S_LNL_STAT) & M_LNL_STAT)
10437 #define V_LNL_CMD(x) ((x) << S_LNL_CMD)
10438 #define G_LNL_CMD(x) (((x) >> S_LNL_CMD) & M_LNL_CMD)
10442 #define V_LNK_STAT(x) ((x) << S_LNK_STAT)
10443 #define G_LNK_STAT(x) (((x) >> S_LNK_STAT) & M_LNK_STAT)
10447 #define V_LNK_CMD(x) ((x) << S_LNK_CMD)
10448 #define G_LNK_CMD(x) (((x) >> S_LNK_CMD) & M_LNK_CMD)
10452 #define V_LNJ_STAT(x) ((x) << S_LNJ_STAT)
10453 #define G_LNJ_STAT(x) (((x) >> S_LNJ_STAT) & M_LNJ_STAT)
10457 #define V_LNJ_CMD(x) ((x) << S_LNJ_CMD)
10458 #define G_LNJ_CMD(x) (((x) >> S_LNJ_CMD) & M_LNJ_CMD)
10462 #define V_LNI_STAT(x) ((x) << S_LNI_STAT)
10463 #define G_LNI_STAT(x) (((x) >> S_LNI_STAT) & M_LNI_STAT)
10467 #define V_LNI_CMD(x) ((x) << S_LNI_CMD)
10468 #define G_LNI_CMD(x) (((x) >> S_LNI_CMD) & M_LNI_CMD)
10474 #define V_LNP_STAT(x) ((x) << S_LNP_STAT)
10475 #define G_LNP_STAT(x) (((x) >> S_LNP_STAT) & M_LNP_STAT)
10479 #define V_LNP_CMD(x) ((x) << S_LNP_CMD)
10480 #define G_LNP_CMD(x) (((x) >> S_LNP_CMD) & M_LNP_CMD)
10484 #define V_LNO_STAT(x) ((x) << S_LNO_STAT)
10485 #define G_LNO_STAT(x) (((x) >> S_LNO_STAT) & M_LNO_STAT)
10489 #define V_LNO_CMD(x) ((x) << S_LNO_CMD)
10490 #define G_LNO_CMD(x) (((x) >> S_LNO_CMD) & M_LNO_CMD)
10494 #define V_LNN_STAT(x) ((x) << S_LNN_STAT)
10495 #define G_LNN_STAT(x) (((x) >> S_LNN_STAT) & M_LNN_STAT)
10499 #define V_LNN_CMD(x) ((x) << S_LNN_CMD)
10500 #define G_LNN_CMD(x) (((x) >> S_LNN_CMD) & M_LNN_CMD)
10504 #define V_LNM_STAT(x) ((x) << S_LNM_STAT)
10505 #define G_LNM_STAT(x) (((x) >> S_LNM_STAT) & M_LNM_STAT)
10509 #define V_LNM_CMD(x) ((x) << S_LNM_CMD)
10510 #define G_LNM_CMD(x) (((x) >> S_LNM_CMD) & M_LNM_CMD)
10516 #define V_LANE9LF(x) ((x) << S_LANE9LF)
10517 #define G_LANE9LF(x) (((x) >> S_LANE9LF) & M_LANE9LF)
10521 #define V_LANE9FS(x) ((x) << S_LANE9FS)
10522 #define G_LANE9FS(x) (((x) >> S_LANE9FS) & M_LANE9FS)
10526 #define V_LANE8LF(x) ((x) << S_LANE8LF)
10527 #define G_LANE8LF(x) (((x) >> S_LANE8LF) & M_LANE8LF)
10531 #define V_LANE8FS(x) ((x) << S_LANE8FS)
10532 #define G_LANE8FS(x) (((x) >> S_LANE8FS) & M_LANE8FS)
10538 #define V_LANE11LF(x) ((x) << S_LANE11LF)
10539 #define G_LANE11LF(x) (((x) >> S_LANE11LF) & M_LANE11LF)
10543 #define V_LANE11FS(x) ((x) << S_LANE11FS)
10544 #define G_LANE11FS(x) (((x) >> S_LANE11FS) & M_LANE11FS)
10548 #define V_LANE10LF(x) ((x) << S_LANE10LF)
10549 #define G_LANE10LF(x) (((x) >> S_LANE10LF) & M_LANE10LF)
10553 #define V_LANE10FS(x) ((x) << S_LANE10FS)
10554 #define G_LANE10FS(x) (((x) >> S_LANE10FS) & M_LANE10FS)
10560 #define V_LANE13LF(x) ((x) << S_LANE13LF)
10561 #define G_LANE13LF(x) (((x) >> S_LANE13LF) & M_LANE13LF)
10565 #define V_LANE13FS(x) ((x) << S_LANE13FS)
10566 #define G_LANE13FS(x) (((x) >> S_LANE13FS) & M_LANE13FS)
10570 #define V_LANE12LF(x) ((x) << S_LANE12LF)
10571 #define G_LANE12LF(x) (((x) >> S_LANE12LF) & M_LANE12LF)
10575 #define V_LANE12FS(x) ((x) << S_LANE12FS)
10576 #define G_LANE12FS(x) (((x) >> S_LANE12FS) & M_LANE12FS)
10582 #define V_LANE15LF(x) ((x) << S_LANE15LF)
10583 #define G_LANE15LF(x) (((x) >> S_LANE15LF) & M_LANE15LF)
10587 #define V_LANE15FS(x) ((x) << S_LANE15FS)
10588 #define G_LANE15FS(x) (((x) >> S_LANE15FS) & M_LANE15FS)
10592 #define V_LANE14LF(x) ((x) << S_LANE14LF)
10593 #define G_LANE14LF(x) (((x) >> S_LANE14LF) & M_LANE14LF)
10597 #define V_LANE14FS(x) ((x) << S_LANE14FS)
10598 #define G_LANE14FS(x) (((x) >> S_LANE14FS) & M_LANE14FS)
10603 #define V_PHY_REG_ENABLE(x) ((x) << S_PHY_REG_ENABLE)
10604 #define F_PHY_REG_ENABLE    V_PHY_REG_ENABLE(1U)
10608 #define V_PHY_REG_SELECT(x) ((x) << S_PHY_REG_SELECT)
10609 #define G_PHY_REG_SELECT(x) (((x) >> S_PHY_REG_SELECT) & M_PHY_REG_SELECT)
10613 #define V_PHY_REG_REGADDR(x) ((x) << S_PHY_REG_REGADDR)
10614 #define G_PHY_REG_REGADDR(x) (((x) >> S_PHY_REG_REGADDR) & M_PHY_REG_REGADDR)
10620 #define V_PHY_REG_DATA(x) ((x) << S_PHY_REG_DATA)
10621 #define G_PHY_REG_DATA(x) (((x) >> S_PHY_REG_DATA) & M_PHY_REG_DATA)
10626 #define V_ENABLE_VF(x) ((x) << S_ENABLE_VF)
10627 #define F_ENABLE_VF    V_ENABLE_VF(1U)
10630 #define V_AI_VF(x) ((x) << S_AI_VF)
10631 #define F_AI_VF    V_AI_VF(1U)
10635 #define V_VFID_PCIE(x) ((x) << S_VFID_PCIE)
10636 #define G_VFID_PCIE(x) (((x) >> S_VFID_PCIE) & M_VFID_PCIE)
10664 #define V_BUSMST_263_256(x) ((x) << S_BUSMST_263_256)
10665 #define G_BUSMST_263_256(x) (((x) >> S_BUSMST_263_256) & M_BUSMST_263_256)
10671 #define V_HDRFREECNT(x) ((x) << S_HDRFREECNT)
10672 #define G_HDRFREECNT(x) (((x) >> S_HDRFREECNT) & M_HDRFREECNT)
10676 #define V_DATAFREECNT(x) ((x) << S_DATAFREECNT)
10677 #define G_DATAFREECNT(x) (((x) >> S_DATAFREECNT) & M_DATAFREECNT)
10691 #define V_RSPERR_263_256(x) ((x) << S_RSPERR_263_256)
10692 #define G_RSPERR_263_256(x) (((x) >> S_RSPERR_263_256) & M_RSPERR_263_256)
10697 #define V_PHY0_RTUNE_ACK(x) ((x) << S_PHY0_RTUNE_ACK)
10698 #define F_PHY0_RTUNE_ACK    V_PHY0_RTUNE_ACK(1U)
10701 #define V_PHY1_RTUNE_ACK(x) ((x) << S_PHY1_RTUNE_ACK)
10702 #define F_PHY1_RTUNE_ACK    V_PHY1_RTUNE_ACK(1U)
10707 #define V_PHY0_RTUNE_REQ(x) ((x) << S_PHY0_RTUNE_REQ)
10708 #define F_PHY0_RTUNE_REQ    V_PHY0_RTUNE_REQ(1U)
10711 #define V_PHY1_RTUNE_REQ(x) ((x) << S_PHY1_RTUNE_REQ)
10712 #define F_PHY1_RTUNE_REQ    V_PHY1_RTUNE_REQ(1U)
10716 #define V_TXDEEMPH_GEN1(x) ((x) << S_TXDEEMPH_GEN1)
10717 #define G_TXDEEMPH_GEN1(x) (((x) >> S_TXDEEMPH_GEN1) & M_TXDEEMPH_GEN1)
10721 #define V_TXDEEMPH_GEN2_3P5DB(x) ((x) << S_TXDEEMPH_GEN2_3P5DB)
10722 #define G_TXDEEMPH_GEN2_3P5DB(x) (((x) >> S_TXDEEMPH_GEN2_3P5DB) & M_TXDEEMPH_GEN2_3P5DB)
10726 #define V_TXDEEMPH_GEN2_6DB(x) ((x) << S_TXDEEMPH_GEN2_6DB)
10727 #define G_TXDEEMPH_GEN2_6DB(x) (((x) >> S_TXDEEMPH_GEN2_6DB) & M_TXDEEMPH_GEN2_6DB)
10733 #define V_PON_RST_STATE_FLAG(x) ((x) << S_PON_RST_STATE_FLAG)
10734 #define F_PON_RST_STATE_FLAG    V_PON_RST_STATE_FLAG(1U)
10737 #define V_BUS_RST_STATE_FLAG(x) ((x) << S_BUS_RST_STATE_FLAG)
10738 #define F_BUS_RST_STATE_FLAG    V_BUS_RST_STATE_FLAG(1U)
10741 #define V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE0_STATE_FLAG)
10742 #define F_DL_DOWN_PCIECRST_MODE0_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE0_STATE_FLAG(1U)
10745 #define V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(x) ((x) << S_DL_DOWN_PCIECRST_MODE1_STATE_FLAG)
10746 #define F_DL_DOWN_PCIECRST_MODE1_STATE_FLAG    V_DL_DOWN_PCIECRST_MODE1_STATE_FLAG(1U)
10749 #define V_PCIE_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE0_STATE_FLAG)
10750 #define F_PCIE_WARM_RST_MODE0_STATE_FLAG    V_PCIE_WARM_RST_MODE0_STATE_FLAG(1U)
10753 #define V_PCIE_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PCIE_WARM_RST_MODE1_STATE_FLAG)
10754 #define F_PCIE_WARM_RST_MODE1_STATE_FLAG    V_PCIE_WARM_RST_MODE1_STATE_FLAG(1U)
10757 #define V_PIO_WARM_RST_MODE0_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE0_STATE_FLAG)
10758 #define F_PIO_WARM_RST_MODE0_STATE_FLAG    V_PIO_WARM_RST_MODE0_STATE_FLAG(1U)
10761 #define V_PIO_WARM_RST_MODE1_STATE_FLAG(x) ((x) << S_PIO_WARM_RST_MODE1_STATE_FLAG)
10762 #define F_PIO_WARM_RST_MODE1_STATE_FLAG    V_PIO_WARM_RST_MODE1_STATE_FLAG(1U)
10766 #define V_LASTRESETSTATE(x) ((x) << S_LASTRESETSTATE)
10767 #define G_LASTRESETSTATE(x) (((x) >> S_LASTRESETSTATE) & M_LASTRESETSTATE)
10773 #define V_PF7_DSTATE(x) ((x) << S_PF7_DSTATE)
10774 #define G_PF7_DSTATE(x) (((x) >> S_PF7_DSTATE) & M_PF7_DSTATE)
10778 #define V_PF6_DSTATE(x) ((x) << S_PF6_DSTATE)
10779 #define G_PF6_DSTATE(x) (((x) >> S_PF6_DSTATE) & M_PF6_DSTATE)
10783 #define V_PF5_DSTATE(x) ((x) << S_PF5_DSTATE)
10784 #define G_PF5_DSTATE(x) (((x) >> S_PF5_DSTATE) & M_PF5_DSTATE)
10788 #define V_PF4_DSTATE(x) ((x) << S_PF4_DSTATE)
10789 #define G_PF4_DSTATE(x) (((x) >> S_PF4_DSTATE) & M_PF4_DSTATE)
10793 #define V_PF3_DSTATE(x) ((x) << S_PF3_DSTATE)
10794 #define G_PF3_DSTATE(x) (((x) >> S_PF3_DSTATE) & M_PF3_DSTATE)
10798 #define V_PF2_DSTATE(x) ((x) << S_PF2_DSTATE)
10799 #define G_PF2_DSTATE(x) (((x) >> S_PF2_DSTATE) & M_PF2_DSTATE)
10803 #define V_PF1_DSTATE(x) ((x) << S_PF1_DSTATE)
10804 #define G_PF1_DSTATE(x) (((x) >> S_PF1_DSTATE) & M_PF1_DSTATE)
10808 #define V_PF0_DSTATE(x) ((x) << S_PF0_DSTATE)
10809 #define G_PF0_DSTATE(x) (((x) >> S_PF0_DSTATE) & M_PF0_DSTATE)
10817 #define V_HSS_PMLD_ACC_EN(x) ((x) << S_HSS_PMLD_ACC_EN)
10818 #define F_HSS_PMLD_ACC_EN    V_HSS_PMLD_ACC_EN(1U)
10822 #define V_HSS_PMRDWR_ADDR(x) ((x) << S_HSS_PMRDWR_ADDR)
10823 #define G_HSS_PMRDWR_ADDR(x) (((x) >> S_HSS_PMRDWR_ADDR) & M_HSS_PMRDWR_ADDR)
10830 #define V_HSS_PCS_AGGREGATION_MODE(x) ((x) << S_HSS_PCS_AGGREGATION_MODE)
10831 #define G_HSS_PCS_AGGREGATION_MODE(x) (((x) >> S_HSS_PCS_AGGREGATION_MODE) & M_HSS_PCS_AGGREGATION_MODE)
10835 #define V_HSS_PCS_FURCATE_MODE(x) ((x) << S_HSS_PCS_FURCATE_MODE)
10836 #define G_HSS_PCS_FURCATE_MODE(x) (((x) >> S_HSS_PCS_FURCATE_MODE) & M_HSS_PCS_FURCATE_MODE)
10839 #define V_HSS_PCS_PCLK_ON_IN_P2(x) ((x) << S_HSS_PCS_PCLK_ON_IN_P2)
10840 #define F_HSS_PCS_PCLK_ON_IN_P2    V_HSS_PCS_PCLK_ON_IN_P2(1U)
10844 #define V_HSS0_PHY_CTRL_REFCLK(x) ((x) << S_HSS0_PHY_CTRL_REFCLK)
10845 #define G_HSS0_PHY_CTRL_REFCLK(x) (((x) >> S_HSS0_PHY_CTRL_REFCLK) & M_HSS0_PHY_CTRL_REFCLK)
10849 #define V_HSS1_PHY_CTRL_REFCLK(x) ((x) << S_HSS1_PHY_CTRL_REFCLK)
10850 #define G_HSS1_PHY_CTRL_REFCLK(x) (((x) >> S_HSS1_PHY_CTRL_REFCLK) & M_HSS1_PHY_CTRL_REFCLK)
10853 #define V_HSS0_PHY_REXT_MASTER(x) ((x) << S_HSS0_PHY_REXT_MASTER)
10854 #define F_HSS0_PHY_REXT_MASTER    V_HSS0_PHY_REXT_MASTER(1U)
10857 #define V_HSS1_PHY_REXT_MASTER(x) ((x) << S_HSS1_PHY_REXT_MASTER)
10858 #define F_HSS1_PHY_REXT_MASTER    V_HSS1_PHY_REXT_MASTER(1U)
10861 #define V_HSS0_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDA_SEL)
10862 #define F_HSS0_PHY_CTRL_VDDA_SEL    V_HSS0_PHY_CTRL_VDDA_SEL(1U)
10865 #define V_HSS0_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS0_PHY_CTRL_VDDHA_SEL)
10866 #define F_HSS0_PHY_CTRL_VDDHA_SEL    V_HSS0_PHY_CTRL_VDDHA_SEL(1U)
10869 #define V_HSS1_PHY_CTRL_VDDA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDA_SEL)
10870 #define F_HSS1_PHY_CTRL_VDDA_SEL    V_HSS1_PHY_CTRL_VDDA_SEL(1U)
10873 #define V_HSS1_PHY_CTRL_VDDHA_SEL(x) ((x) << S_HSS1_PHY_CTRL_VDDHA_SEL)
10874 #define F_HSS1_PHY_CTRL_VDDHA_SEL    V_HSS1_PHY_CTRL_VDDHA_SEL(1U)
10877 #define V_HSS1_CPU_MEMPSACK(x) ((x) << S_HSS1_CPU_MEMPSACK)
10878 #define F_HSS1_CPU_MEMPSACK    V_HSS1_CPU_MEMPSACK(1U)
10881 #define V_HSS0_CPU_MEMPSACK(x) ((x) << S_HSS0_CPU_MEMPSACK)
10882 #define F_HSS0_CPU_MEMPSACK    V_HSS0_CPU_MEMPSACK(1U)
10885 #define V_HSS1_CPU_MEMACK(x) ((x) << S_HSS1_CPU_MEMACK)
10886 #define F_HSS1_CPU_MEMACK    V_HSS1_CPU_MEMACK(1U)
10889 #define V_HSS0_CPU_MEMACK(x) ((x) << S_HSS0_CPU_MEMACK)
10890 #define F_HSS0_CPU_MEMACK    V_HSS0_CPU_MEMACK(1U)
10892 #define S_HSS_PM_IS_ROM    1
10893 #define V_HSS_PM_IS_ROM(x) ((x) << S_HSS_PM_IS_ROM)
10894 #define F_HSS_PM_IS_ROM    V_HSS_PM_IS_ROM(1U)
10899 #define V_HSS_RST_CTRL_BY_FW(x) ((x) << S_HSS_RST_CTRL_BY_FW)
10900 #define F_HSS_RST_CTRL_BY_FW    V_HSS_RST_CTRL_BY_FW(1U)
10903 #define V_HSS_PIPE0_RESET_N(x) ((x) << S_HSS_PIPE0_RESET_N)
10904 #define F_HSS_PIPE0_RESET_N    V_HSS_PIPE0_RESET_N(1U)
10907 #define V_HSS0_POR_N(x) ((x) << S_HSS0_POR_N)
10908 #define F_HSS0_POR_N    V_HSS0_POR_N(1U)
10911 #define V_HSS1_POR_N(x) ((x) << S_HSS1_POR_N)
10912 #define F_HSS1_POR_N    V_HSS1_POR_N(1U)
10915 #define V_HSS0_CPU_RESET(x) ((x) << S_HSS0_CPU_RESET)
10916 #define F_HSS0_CPU_RESET    V_HSS0_CPU_RESET(1U)
10919 #define V_HSS1_CPU_RESET(x) ((x) << S_HSS1_CPU_RESET)
10920 #define F_HSS1_CPU_RESET    V_HSS1_CPU_RESET(1U)
10923 #define V_HSS_PCS_POR_N(x) ((x) << S_HSS_PCS_POR_N)
10924 #define F_HSS_PCS_POR_N    V_HSS_PCS_POR_N(1U)
10927 #define V_SW_CRST_(x) ((x) << S_SW_CRST_)
10928 #define F_SW_CRST_    V_SW_CRST_(1U)
10931 #define V_SW_PCIECRST_(x) ((x) << S_SW_PCIECRST_)
10932 #define F_SW_PCIECRST_    V_SW_PCIECRST_(1U)
10935 #define V_SW_PCIEPIPERST_(x) ((x) << S_SW_PCIEPIPERST_)
10936 #define F_SW_PCIEPIPERST_    V_SW_PCIEPIPERST_(1U)
10939 #define V_SW_PCIEPHYRST_(x) ((x) << S_SW_PCIEPHYRST_)
10940 #define F_SW_PCIEPHYRST_    V_SW_PCIEPHYRST_(1U)
10943 #define V_HSS1_ERR_O(x) ((x) << S_HSS1_ERR_O)
10944 #define F_HSS1_ERR_O    V_HSS1_ERR_O(1U)
10947 #define V_HSS0_ERR_O(x) ((x) << S_HSS0_ERR_O)
10948 #define F_HSS0_ERR_O    V_HSS0_ERR_O(1U)
10950 #define S_HSS1_PLL_LOCK    1
10951 #define V_HSS1_PLL_LOCK(x) ((x) << S_HSS1_PLL_LOCK)
10952 #define F_HSS1_PLL_LOCK    V_HSS1_PLL_LOCK(1U)
10955 #define V_HSS0_PLL_LOCK(x) ((x) << S_HSS0_PLL_LOCK)
10956 #define F_HSS0_PLL_LOCK    V_HSS0_PLL_LOCK(1U)
10962 #define V_T5_ARM_MAXREQCNT(x) ((x) << S_T5_ARM_MAXREQCNT)
10963 #define G_T5_ARM_MAXREQCNT(x) (((x) >> S_T5_ARM_MAXREQCNT) & M_T5_ARM_MAXREQCNT)
10967 #define V_T5_ARM_MAXRDREQSIZE(x) ((x) << S_T5_ARM_MAXRDREQSIZE)
10968 #define G_T5_ARM_MAXRDREQSIZE(x) (((x) >> S_T5_ARM_MAXRDREQSIZE) & M_T5_ARM_MAXRDREQSIZE)
10972 #define V_T5_ARM_MAXRSPCNT(x) ((x) << S_T5_ARM_MAXRSPCNT)
10973 #define G_T5_ARM_MAXRSPCNT(x) (((x) >> S_T5_ARM_MAXRSPCNT) & M_T5_ARM_MAXRSPCNT)
10979 #define V_ARM_RESPCNT(x) ((x) << S_ARM_RESPCNT)
10980 #define G_ARM_RESPCNT(x) (((x) >> S_ARM_RESPCNT) & M_ARM_RESPCNT)
10984 #define V_ARM_RDREQCNT(x) ((x) << S_ARM_RDREQCNT)
10985 #define G_ARM_RDREQCNT(x) (((x) >> S_ARM_RDREQCNT) & M_ARM_RDREQCNT)
10989 #define V_ARM_WRREQCNT(x) ((x) << S_ARM_WRREQCNT)
10990 #define G_ARM_WRREQCNT(x) (((x) >> S_ARM_WRREQCNT) & M_ARM_WRREQCNT)
10996 #define V_ARM_COOKIECNT(x) ((x) << S_ARM_COOKIECNT)
10997 #define G_ARM_COOKIECNT(x) (((x) >> S_ARM_COOKIECNT) & M_ARM_COOKIECNT)
11001 #define V_ARM_RDSEQNUMUPDCNT(x) ((x) << S_ARM_RDSEQNUMUPDCNT)
11002 #define G_ARM_RDSEQNUMUPDCNT(x) (((x) >> S_ARM_RDSEQNUMUPDCNT) & M_ARM_RDSEQNUMUPDCNT)
11006 #define V_ARM_SIREQCNT(x) ((x) << S_ARM_SIREQCNT)
11007 #define G_ARM_SIREQCNT(x) (((x) >> S_ARM_SIREQCNT) & M_ARM_SIREQCNT)
11010 #define V_ARM_WREOPMATCHSOP(x) ((x) << S_ARM_WREOPMATCHSOP)
11011 #define F_ARM_WREOPMATCHSOP    V_ARM_WREOPMATCHSOP(1U)
11015 #define V_ARM_WRSOPCNT(x) ((x) << S_ARM_WRSOPCNT)
11016 #define G_ARM_WRSOPCNT(x) (((x) >> S_ARM_WRSOPCNT) & M_ARM_WRSOPCNT)
11020 #define V_ARM_RDSOPCNT(x) ((x) << S_ARM_RDSOPCNT)
11021 #define G_ARM_RDSOPCNT(x) (((x) >> S_ARM_RDSOPCNT) & M_ARM_RDSOPCNT)
11027 #define V_ARM_ATMREQSOPCNT(x) ((x) << S_ARM_ATMREQSOPCNT)
11028 #define G_ARM_ATMREQSOPCNT(x) (((x) >> S_ARM_ATMREQSOPCNT) & M_ARM_ATMREQSOPCNT)
11031 #define V_ARM_ATMEOPMATCHSOP(x) ((x) << S_ARM_ATMEOPMATCHSOP)
11032 #define F_ARM_ATMEOPMATCHSOP    V_ARM_ATMEOPMATCHSOP(1U)
11035 #define V_ARM_RSPEOPMATCHSOP(x) ((x) << S_ARM_RSPEOPMATCHSOP)
11036 #define F_ARM_RSPEOPMATCHSOP    V_ARM_RSPEOPMATCHSOP(1U)
11040 #define V_ARM_RSPERRCNT(x) ((x) << S_ARM_RSPERRCNT)
11041 #define G_ARM_RSPERRCNT(x) (((x) >> S_ARM_RSPERRCNT) & M_ARM_RSPERRCNT)
11045 #define V_ARM_RSPSOPCNT(x) ((x) << S_ARM_RSPSOPCNT)
11046 #define G_ARM_RSPSOPCNT(x) (((x) >> S_ARM_RSPSOPCNT) & M_ARM_RSPSOPCNT)
11052 #define V_A0_RSVD1(x) ((x) << S_A0_RSVD1)
11053 #define G_A0_RSVD1(x) (((x) >> S_A0_RSVD1) & M_A0_RSVD1)
11057 #define V_A0_PRIMBUSNUMBER(x) ((x) << S_A0_PRIMBUSNUMBER)
11058 #define G_A0_PRIMBUSNUMBER(x) (((x) >> S_A0_PRIMBUSNUMBER) & M_A0_PRIMBUSNUMBER)
11062 #define V_A0_REQUESTERID(x) ((x) << S_A0_REQUESTERID)
11063 #define G_A0_REQUESTERID(x) (((x) >> S_A0_REQUESTERID) & M_A0_REQUESTERID)
11068 #define V_REQ0ENABLE(x) ((x) << S_REQ0ENABLE)
11069 #define F_REQ0ENABLE    V_REQ0ENABLE(1U)
11072 #define V_RDREQ0TYPE(x) ((x) << S_RDREQ0TYPE)
11073 #define F_RDREQ0TYPE    V_RDREQ0TYPE(1U)
11077 #define V_BYTEENABLE0(x) ((x) << S_BYTEENABLE0)
11078 #define G_BYTEENABLE0(x) (((x) >> S_BYTEENABLE0) & M_BYTEENABLE0)
11082 #define V_REGADDR0(x) ((x) << S_REGADDR0)
11083 #define G_REGADDR0(x) (((x) >> S_REGADDR0) & M_REGADDR0)
11089 #define V_REQ1ENABLE(x) ((x) << S_REQ1ENABLE)
11090 #define F_REQ1ENABLE    V_REQ1ENABLE(1U)
11094 #define V_RDREQ1TYPE(x) ((x) << S_RDREQ1TYPE)
11095 #define G_RDREQ1TYPE(x) (((x) >> S_RDREQ1TYPE) & M_RDREQ1TYPE)
11099 #define V_BYTEENABLE1(x) ((x) << S_BYTEENABLE1)
11100 #define G_BYTEENABLE1(x) (((x) >> S_BYTEENABLE1) & M_BYTEENABLE1)
11104 #define V_REGADDR1(x) ((x) << S_REGADDR1)
11105 #define G_REGADDR1(x) (((x) >> S_REGADDR1) & M_REGADDR1)
11111 #define V_REQ2ENABLE(x) ((x) << S_REQ2ENABLE)
11112 #define F_REQ2ENABLE    V_REQ2ENABLE(1U)
11116 #define V_RDREQ2TYPE(x) ((x) << S_RDREQ2TYPE)
11117 #define G_RDREQ2TYPE(x) (((x) >> S_RDREQ2TYPE) & M_RDREQ2TYPE)
11121 #define V_BYTEENABLE2(x) ((x) << S_BYTEENABLE2)
11122 #define G_BYTEENABLE2(x) (((x) >> S_BYTEENABLE2) & M_BYTEENABLE2)
11126 #define V_REGADDR2(x) ((x) << S_REGADDR2)
11127 #define G_REGADDR2(x) (((x) >> S_REGADDR2) & M_REGADDR2)
11133 #define V_REQ3ENABLE(x) ((x) << S_REQ3ENABLE)
11134 #define F_REQ3ENABLE    V_REQ3ENABLE(1U)
11138 #define V_RDREQ3TYPE(x) ((x) << S_RDREQ3TYPE)
11139 #define G_RDREQ3TYPE(x) (((x) >> S_RDREQ3TYPE) & M_RDREQ3TYPE)
11143 #define V_BYTEENABLE3(x) ((x) << S_BYTEENABLE3)
11144 #define G_BYTEENABLE3(x) (((x) >> S_BYTEENABLE3) & M_BYTEENABLE3)
11148 #define V_REGADDR3(x) ((x) << S_REGADDR3)
11149 #define G_REGADDR3(x) (((x) >> S_REGADDR3) & M_REGADDR3)
11155 #define V_REQ4ENABLE(x) ((x) << S_REQ4ENABLE)
11156 #define F_REQ4ENABLE    V_REQ4ENABLE(1U)
11160 #define V_RDREQ4TYPE(x) ((x) << S_RDREQ4TYPE)
11161 #define G_RDREQ4TYPE(x) (((x) >> S_RDREQ4TYPE) & M_RDREQ4TYPE)
11165 #define V_BYTEENABLE4(x) ((x) << S_BYTEENABLE4)
11166 #define G_BYTEENABLE4(x) (((x) >> S_BYTEENABLE4) & M_BYTEENABLE4)
11170 #define V_REGADDR4(x) ((x) << S_REGADDR4)
11171 #define G_REGADDR4(x) (((x) >> S_REGADDR4) & M_REGADDR4)
11177 #define V_REQ5ENABLE(x) ((x) << S_REQ5ENABLE)
11178 #define F_REQ5ENABLE    V_REQ5ENABLE(1U)
11182 #define V_RDREQ5TYPE(x) ((x) << S_RDREQ5TYPE)
11183 #define G_RDREQ5TYPE(x) (((x) >> S_RDREQ5TYPE) & M_RDREQ5TYPE)
11187 #define V_BYTEENABLE5(x) ((x) << S_BYTEENABLE5)
11188 #define G_BYTEENABLE5(x) (((x) >> S_BYTEENABLE5) & M_BYTEENABLE5)
11192 #define V_REGADDR5(x) ((x) << S_REGADDR5)
11193 #define G_REGADDR5(x) (((x) >> S_REGADDR5) & M_REGADDR5)
11199 #define V_REQ6ENABLE(x) ((x) << S_REQ6ENABLE)
11200 #define F_REQ6ENABLE    V_REQ6ENABLE(1U)
11204 #define V_RDREQ6TYPE(x) ((x) << S_RDREQ6TYPE)
11205 #define G_RDREQ6TYPE(x) (((x) >> S_RDREQ6TYPE) & M_RDREQ6TYPE)
11209 #define V_BYTEENABLE6(x) ((x) << S_BYTEENABLE6)
11210 #define G_BYTEENABLE6(x) (((x) >> S_BYTEENABLE6) & M_BYTEENABLE6)
11214 #define V_REGADDR6(x) ((x) << S_REGADDR6)
11215 #define G_REGADDR6(x) (((x) >> S_REGADDR6) & M_REGADDR6)
11221 #define V_REQ7ENABLE(x) ((x) << S_REQ7ENABLE)
11222 #define F_REQ7ENABLE    V_REQ7ENABLE(1U)
11226 #define V_RDREQ7TYPE(x) ((x) << S_RDREQ7TYPE)
11227 #define G_RDREQ7TYPE(x) (((x) >> S_RDREQ7TYPE) & M_RDREQ7TYPE)
11231 #define V_BYTEENABLE7(x) ((x) << S_BYTEENABLE7)
11232 #define G_BYTEENABLE7(x) (((x) >> S_BYTEENABLE7) & M_BYTEENABLE7)
11236 #define V_REGADDR7(x) ((x) << S_REGADDR7)
11237 #define G_REGADDR7(x) (((x) >> S_REGADDR7) & M_REGADDR7)
11243 #define V_REQ8ENABLE(x) ((x) << S_REQ8ENABLE)
11244 #define F_REQ8ENABLE    V_REQ8ENABLE(1U)
11248 #define V_RDREQ8TYPE(x) ((x) << S_RDREQ8TYPE)
11249 #define G_RDREQ8TYPE(x) (((x) >> S_RDREQ8TYPE) & M_RDREQ8TYPE)
11253 #define V_BYTEENABLE8(x) ((x) << S_BYTEENABLE8)
11254 #define G_BYTEENABLE8(x) (((x) >> S_BYTEENABLE8) & M_BYTEENABLE8)
11258 #define V_REGADDR8(x) ((x) << S_REGADDR8)
11259 #define G_REGADDR8(x) (((x) >> S_REGADDR8) & M_REGADDR8)
11265 #define V_REGSEL(x) ((x) << S_REGSEL)
11266 #define F_REGSEL    V_REGSEL(1U)
11269 #define V_RDENABLE(x) ((x) << S_RDENABLE)
11270 #define F_RDENABLE    V_RDENABLE(1U)
11273 #define V_WRENABLE(x) ((x) << S_WRENABLE)
11274 #define F_WRENABLE    V_WRENABLE(1U)
11278 #define V_AUTOINCRVAL(x) ((x) << S_AUTOINCRVAL)
11279 #define G_AUTOINCRVAL(x) (((x) >> S_AUTOINCRVAL) & M_AUTOINCRVAL)
11282 #define V_AUTOINCR(x) ((x) << S_AUTOINCR)
11283 #define F_AUTOINCR    V_AUTOINCR(1U)
11287 #define V_PHYSEL(x) ((x) << S_PHYSEL)
11288 #define G_PHYSEL(x) (((x) >> S_PHYSEL) & M_PHYSEL)
11292 #define V_T7_REGADDR(x) ((x) << S_T7_REGADDR)
11293 #define G_T7_REGADDR(x) (((x) >> S_T7_REGADDR) & M_T7_REGADDR)
11299 #define V_PHY3_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY3_SRAM_BOOTLOAD_BYPASS)
11300 #define F_PHY3_SRAM_BOOTLOAD_BYPASS    V_PHY3_SRAM_BOOTLOAD_BYPASS(1U)
11303 #define V_PHY3_SRAM_BYPASS(x) ((x) << S_PHY3_SRAM_BYPASS)
11304 #define F_PHY3_SRAM_BYPASS    V_PHY3_SRAM_BYPASS(1U)
11307 #define V_PHY3_SRAM_ECC_EN(x) ((x) << S_PHY3_SRAM_ECC_EN)
11308 #define F_PHY3_SRAM_ECC_EN    V_PHY3_SRAM_ECC_EN(1U)
11311 #define V_PHY3_SRAM_EXT_LD_DONE(x) ((x) << S_PHY3_SRAM_EXT_LD_DONE)
11312 #define F_PHY3_SRAM_EXT_LD_DONE    V_PHY3_SRAM_EXT_LD_DONE(1U)
11315 #define V_PHY2_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY2_SRAM_BOOTLOAD_BYPASS)
11316 #define F_PHY2_SRAM_BOOTLOAD_BYPASS    V_PHY2_SRAM_BOOTLOAD_BYPASS(1U)
11319 #define V_PHY2_SRAM_BYPASS(x) ((x) << S_PHY2_SRAM_BYPASS)
11320 #define F_PHY2_SRAM_BYPASS    V_PHY2_SRAM_BYPASS(1U)
11323 #define V_PHY2_SRAM_ECC_EN(x) ((x) << S_PHY2_SRAM_ECC_EN)
11324 #define F_PHY2_SRAM_ECC_EN    V_PHY2_SRAM_ECC_EN(1U)
11327 #define V_PHY2_SRAM_EXT_LD_DONE(x) ((x) << S_PHY2_SRAM_EXT_LD_DONE)
11328 #define F_PHY2_SRAM_EXT_LD_DONE    V_PHY2_SRAM_EXT_LD_DONE(1U)
11331 #define V_PHY1_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY1_SRAM_BOOTLOAD_BYPASS)
11332 #define F_PHY1_SRAM_BOOTLOAD_BYPASS    V_PHY1_SRAM_BOOTLOAD_BYPASS(1U)
11335 #define V_PHY1_SRAM_BYPASS(x) ((x) << S_PHY1_SRAM_BYPASS)
11336 #define F_PHY1_SRAM_BYPASS    V_PHY1_SRAM_BYPASS(1U)
11339 #define V_PHY1_SRAM_ECC_EN(x) ((x) << S_PHY1_SRAM_ECC_EN)
11340 #define F_PHY1_SRAM_ECC_EN    V_PHY1_SRAM_ECC_EN(1U)
11343 #define V_PHY1_SRAM_EXT_LD_DONE(x) ((x) << S_PHY1_SRAM_EXT_LD_DONE)
11344 #define F_PHY1_SRAM_EXT_LD_DONE    V_PHY1_SRAM_EXT_LD_DONE(1U)
11348 #define V_PHY_CR_PARA_SEL(x) ((x) << S_PHY_CR_PARA_SEL)
11349 #define G_PHY_CR_PARA_SEL(x) (((x) >> S_PHY_CR_PARA_SEL) & M_PHY_CR_PARA_SEL)
11352 #define V_PHY0_SRAM_BOOTLOAD_BYPASS(x) ((x) << S_PHY0_SRAM_BOOTLOAD_BYPASS)
11353 #define F_PHY0_SRAM_BOOTLOAD_BYPASS    V_PHY0_SRAM_BOOTLOAD_BYPASS(1U)
11356 #define V_PHY0_SRAM_BYPASS(x) ((x) << S_PHY0_SRAM_BYPASS)
11357 #define F_PHY0_SRAM_BYPASS    V_PHY0_SRAM_BYPASS(1U)
11359 #define S_PHY0_SRAM_ECC_EN    1
11360 #define V_PHY0_SRAM_ECC_EN(x) ((x) << S_PHY0_SRAM_ECC_EN)
11361 #define F_PHY0_SRAM_ECC_EN    V_PHY0_SRAM_ECC_EN(1U)
11364 #define V_PHY0_SRAM_EXT_LD_DONE(x) ((x) << S_PHY0_SRAM_EXT_LD_DONE)
11365 #define F_PHY0_SRAM_EXT_LD_DONE    V_PHY0_SRAM_EXT_LD_DONE(1U)
11370 #define V_PHY3_SRAM_INIT_DONE(x) ((x) << S_PHY3_SRAM_INIT_DONE)
11371 #define F_PHY3_SRAM_INIT_DONE    V_PHY3_SRAM_INIT_DONE(1U)
11374 #define V_PHY2_SRAM_INIT_DONE(x) ((x) << S_PHY2_SRAM_INIT_DONE)
11375 #define F_PHY2_SRAM_INIT_DONE    V_PHY2_SRAM_INIT_DONE(1U)
11377 #define S_PHY1_SRAM_INIT_DONE    1
11378 #define V_PHY1_SRAM_INIT_DONE(x) ((x) << S_PHY1_SRAM_INIT_DONE)
11379 #define F_PHY1_SRAM_INIT_DONE    V_PHY1_SRAM_INIT_DONE(1U)
11382 #define V_PHY0_SRAM_INIT_DONE(x) ((x) << S_PHY0_SRAM_INIT_DONE)
11383 #define F_PHY0_SRAM_INIT_DONE    V_PHY0_SRAM_INIT_DONE(1U)
11394 #define V_RX_TERM_OFFSET(x) ((x) << S_RX_TERM_OFFSET)
11395 #define F_RX_TERM_OFFSET    V_RX_TERM_OFFSET(1U)
11398 #define V_REFB_RAW_CLK_DIV2_EN(x) ((x) << S_REFB_RAW_CLK_DIV2_EN)
11399 #define F_REFB_RAW_CLK_DIV2_EN    V_REFB_RAW_CLK_DIV2_EN(1U)
11403 #define V_REFB_RANGE(x) ((x) << S_REFB_RANGE)
11404 #define G_REFB_RANGE(x) (((x) >> S_REFB_RANGE) & M_REFB_RANGE)
11407 #define V_REFB_LANE_CLK_EN(x) ((x) << S_REFB_LANE_CLK_EN)
11408 #define F_REFB_LANE_CLK_EN    V_REFB_LANE_CLK_EN(1U)
11411 #define V_REFB_CLK_DIV2_EN(x) ((x) << S_REFB_CLK_DIV2_EN)
11412 #define F_REFB_CLK_DIV2_EN    V_REFB_CLK_DIV2_EN(1U)
11415 #define V_REFA_RAW_CLK_DIV2_EN(x) ((x) << S_REFA_RAW_CLK_DIV2_EN)
11416 #define F_REFA_RAW_CLK_DIV2_EN    V_REFA_RAW_CLK_DIV2_EN(1U)
11420 #define V_REFA_RANGE(x) ((x) << S_REFA_RANGE)
11421 #define G_REFA_RANGE(x) (((x) >> S_REFA_RANGE) & M_REFA_RANGE)
11424 #define V_REFA_LANE_CLK_EN(x) ((x) << S_REFA_LANE_CLK_EN)
11425 #define F_REFA_LANE_CLK_EN    V_REFA_LANE_CLK_EN(1U)
11428 #define V_REFA_CLK_DIV2_EN(x) ((x) << S_REFA_CLK_DIV2_EN)
11429 #define F_REFA_CLK_DIV2_EN    V_REFA_CLK_DIV2_EN(1U)
11433 #define V_NOMINAL_VPH_SEL(x) ((x) << S_NOMINAL_VPH_SEL)
11434 #define G_NOMINAL_VPH_SEL(x) (((x) >> S_NOMINAL_VPH_SEL) & M_NOMINAL_VPH_SEL)
11438 #define V_NOMINAL_VP_SEL(x) ((x) << S_NOMINAL_VP_SEL)
11439 #define G_NOMINAL_VP_SEL(x) (((x) >> S_NOMINAL_VP_SEL) & M_NOMINAL_VP_SEL)
11442 #define V_MPLLB_WORD_CLK_EN(x) ((x) << S_MPLLB_WORD_CLK_EN)
11443 #define F_MPLLB_WORD_CLK_EN    V_MPLLB_WORD_CLK_EN(1U)
11446 #define V_MPLLB_SSC_EN(x) ((x) << S_MPLLB_SSC_EN)
11447 #define F_MPLLB_SSC_EN    V_MPLLB_SSC_EN(1U)
11450 #define V_MPLLB_SHORT_LOCK_EN(x) ((x) << S_MPLLB_SHORT_LOCK_EN)
11451 #define F_MPLLB_SHORT_LOCK_EN    V_MPLLB_SHORT_LOCK_EN(1U)
11454 #define V_MPLLB_FORCE_EN(x) ((x) << S_MPLLB_FORCE_EN)
11455 #define F_MPLLB_FORCE_EN    V_MPLLB_FORCE_EN(1U)
11458 #define V_MPLLA_WORD_CLK_EN(x) ((x) << S_MPLLA_WORD_CLK_EN)
11459 #define F_MPLLA_WORD_CLK_EN    V_MPLLA_WORD_CLK_EN(1U)
11462 #define V_MPLLA_SSC_EN(x) ((x) << S_MPLLA_SSC_EN)
11463 #define F_MPLLA_SSC_EN    V_MPLLA_SSC_EN(1U)
11465 #define S_MPLLA_SHORT_LOCK_EN    1
11466 #define V_MPLLA_SHORT_LOCK_EN(x) ((x) << S_MPLLA_SHORT_LOCK_EN)
11467 #define F_MPLLA_SHORT_LOCK_EN    V_MPLLA_SHORT_LOCK_EN(1U)
11470 #define V_MPLLA_FORCE_EN(x) ((x) << S_MPLLA_FORCE_EN)
11471 #define F_MPLLA_FORCE_EN    V_MPLLA_FORCE_EN(1U)
11476 #define V_REF_ALT1_CLK_M(x) ((x) << S_REF_ALT1_CLK_M)
11477 #define F_REF_ALT1_CLK_M    V_REF_ALT1_CLK_M(1U)
11480 #define V_REF_ALT1_CLK_P(x) ((x) << S_REF_ALT1_CLK_P)
11481 #define F_REF_ALT1_CLK_P    V_REF_ALT1_CLK_P(1U)
11489 #define V_T7_LANE3(x) ((x) << S_T7_LANE3)
11490 #define G_T7_LANE3(x) (((x) >> S_T7_LANE3) & M_T7_LANE3)
11494 #define V_T7_LANE2(x) ((x) << S_T7_LANE2)
11495 #define G_T7_LANE2(x) (((x) >> S_T7_LANE2) & M_T7_LANE2)
11499 #define V_T7_LANE1(x) ((x) << S_T7_LANE1)
11500 #define G_T7_LANE1(x) (((x) >> S_T7_LANE1) & M_T7_LANE1)
11504 #define V_T7_LANE0(x) ((x) << S_T7_LANE0)
11505 #define G_T7_LANE0(x) (((x) >> S_T7_LANE0) & M_T7_LANE0)
11514 #define V_LANE7_LANEPLL_SRC_SEL(x) ((x) << S_LANE7_LANEPLL_SRC_SEL)
11515 #define G_LANE7_LANEPLL_SRC_SEL(x) (((x) >> S_LANE7_LANEPLL_SRC_SEL) & M_LANE7_LANEPLL_SRC_SEL)
11519 #define V_LANE6_LANEPLL_SRC_SEL(x) ((x) << S_LANE6_LANEPLL_SRC_SEL)
11520 #define G_LANE6_LANEPLL_SRC_SEL(x) (((x) >> S_LANE6_LANEPLL_SRC_SEL) & M_LANE6_LANEPLL_SRC_SEL)
11524 #define V_LANE5_LANEPLL_SRC_SEL(x) ((x) << S_LANE5_LANEPLL_SRC_SEL)
11525 #define G_LANE5_LANEPLL_SRC_SEL(x) (((x) >> S_LANE5_LANEPLL_SRC_SEL) & M_LANE5_LANEPLL_SRC_SEL)
11529 #define V_LANE4_LANEPLL_SRC_SEL(x) ((x) << S_LANE4_LANEPLL_SRC_SEL)
11530 #define G_LANE4_LANEPLL_SRC_SEL(x) (((x) >> S_LANE4_LANEPLL_SRC_SEL) & M_LANE4_LANEPLL_SRC_SEL)
11534 #define V_LANE3_LANEPLL_SRC_SEL(x) ((x) << S_LANE3_LANEPLL_SRC_SEL)
11535 #define G_LANE3_LANEPLL_SRC_SEL(x) (((x) >> S_LANE3_LANEPLL_SRC_SEL) & M_LANE3_LANEPLL_SRC_SEL)
11539 #define V_LANE2_LANEPLL_SRC_SEL(x) ((x) << S_LANE2_LANEPLL_SRC_SEL)
11540 #define G_LANE2_LANEPLL_SRC_SEL(x) (((x) >> S_LANE2_LANEPLL_SRC_SEL) & M_LANE2_LANEPLL_SRC_SEL)
11544 #define V_LANE1_LANEPLL_SRC_SEL(x) ((x) << S_LANE1_LANEPLL_SRC_SEL)
11545 #define G_LANE1_LANEPLL_SRC_SEL(x) (((x) >> S_LANE1_LANEPLL_SRC_SEL) & M_LANE1_LANEPLL_SRC_SEL)
11549 #define V_LANE0_LANEPLL_SRC_SEL(x) ((x) << S_LANE0_LANEPLL_SRC_SEL)
11550 #define G_LANE0_LANEPLL_SRC_SEL(x) (((x) >> S_LANE0_LANEPLL_SRC_SEL) & M_LANE0_LANEPLL_SRC_SEL)
11557 #define V_LANE15_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE15_REC_OVRD_8B10B_DECERR)
11558 #define G_LANE15_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE15_REC_OVRD_8B10B_DECERR) & M_LANE15_REC_OVRD_8B10B_DECERR)
11562 #define V_LANE14_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE14_REC_OVRD_8B10B_DECERR)
11563 #define G_LANE14_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE14_REC_OVRD_8B10B_DECERR) & M_LANE14_REC_OVRD_8B10B_DECERR)
11567 #define V_LANE13_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE13_REC_OVRD_8B10B_DECERR)
11568 #define G_LANE13_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE13_REC_OVRD_8B10B_DECERR) & M_LANE13_REC_OVRD_8B10B_DECERR)
11572 #define V_LANE12_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE12_REC_OVRD_8B10B_DECERR)
11573 #define G_LANE12_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE12_REC_OVRD_8B10B_DECERR) & M_LANE12_REC_OVRD_8B10B_DECERR)
11577 #define V_LANE11_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE11_REC_OVRD_8B10B_DECERR)
11578 #define G_LANE11_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE11_REC_OVRD_8B10B_DECERR) & M_LANE11_REC_OVRD_8B10B_DECERR)
11582 #define V_LANE10_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE10_REC_OVRD_8B10B_DECERR)
11583 #define G_LANE10_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE10_REC_OVRD_8B10B_DECERR) & M_LANE10_REC_OVRD_8B10B_DECERR)
11587 #define V_LANE9_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE9_REC_OVRD_8B10B_DECERR)
11588 #define G_LANE9_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE9_REC_OVRD_8B10B_DECERR) & M_LANE9_REC_OVRD_8B10B_DECERR)
11592 #define V_LANE8_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE8_REC_OVRD_8B10B_DECERR)
11593 #define G_LANE8_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE8_REC_OVRD_8B10B_DECERR) & M_LANE8_REC_OVRD_8B10B_DECERR)
11597 #define V_LANE7_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE7_REC_OVRD_8B10B_DECERR)
11598 #define G_LANE7_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE7_REC_OVRD_8B10B_DECERR) & M_LANE7_REC_OVRD_8B10B_DECERR)
11602 #define V_LANE6_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE6_REC_OVRD_8B10B_DECERR)
11603 #define G_LANE6_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE6_REC_OVRD_8B10B_DECERR) & M_LANE6_REC_OVRD_8B10B_DECERR)
11607 #define V_LANE5_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE5_REC_OVRD_8B10B_DECERR)
11608 #define G_LANE5_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE5_REC_OVRD_8B10B_DECERR) & M_LANE5_REC_OVRD_8B10B_DECERR)
11612 #define V_LANE4_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE4_REC_OVRD_8B10B_DECERR)
11613 #define G_LANE4_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE4_REC_OVRD_8B10B_DECERR) & M_LANE4_REC_OVRD_8B10B_DECERR)
11617 #define V_LANE3_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE3_REC_OVRD_8B10B_DECERR)
11618 #define G_LANE3_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE3_REC_OVRD_8B10B_DECERR) & M_LANE3_REC_OVRD_8B10B_DECERR)
11622 #define V_LANE2_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE2_REC_OVRD_8B10B_DECERR)
11623 #define G_LANE2_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE2_REC_OVRD_8B10B_DECERR) & M_LANE2_REC_OVRD_8B10B_DECERR)
11627 #define V_LANE1_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE1_REC_OVRD_8B10B_DECERR)
11628 #define G_LANE1_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE1_REC_OVRD_8B10B_DECERR) & M_LANE1_REC_OVRD_8B10B_DECERR)
11632 #define V_LANE0_REC_OVRD_8B10B_DECERR(x) ((x) << S_LANE0_REC_OVRD_8B10B_DECERR)
11633 #define G_LANE0_REC_OVRD_8B10B_DECERR(x) (((x) >> S_LANE0_REC_OVRD_8B10B_DECERR) & M_LANE0_REC_OVRD_8B10B_DECERR)
11638 #define V_LANE15_REC_OVRD_EN(x) ((x) << S_LANE15_REC_OVRD_EN)
11639 #define F_LANE15_REC_OVRD_EN    V_LANE15_REC_OVRD_EN(1U)
11642 #define V_LANE14_REC_OVRD_EN(x) ((x) << S_LANE14_REC_OVRD_EN)
11643 #define F_LANE14_REC_OVRD_EN    V_LANE14_REC_OVRD_EN(1U)
11646 #define V_LANE13_REC_OVRD_EN(x) ((x) << S_LANE13_REC_OVRD_EN)
11647 #define F_LANE13_REC_OVRD_EN    V_LANE13_REC_OVRD_EN(1U)
11650 #define V_LANE11_REC_OVRD_EN(x) ((x) << S_LANE11_REC_OVRD_EN)
11651 #define F_LANE11_REC_OVRD_EN    V_LANE11_REC_OVRD_EN(1U)
11654 #define V_LANE12_REC_OVRD_EN(x) ((x) << S_LANE12_REC_OVRD_EN)
11655 #define F_LANE12_REC_OVRD_EN    V_LANE12_REC_OVRD_EN(1U)
11658 #define V_LANE10_REC_OVRD_EN(x) ((x) << S_LANE10_REC_OVRD_EN)
11659 #define F_LANE10_REC_OVRD_EN    V_LANE10_REC_OVRD_EN(1U)
11662 #define V_LANE9_REC_OVRD_EN(x) ((x) << S_LANE9_REC_OVRD_EN)
11663 #define F_LANE9_REC_OVRD_EN    V_LANE9_REC_OVRD_EN(1U)
11666 #define V_LANE8_REC_OVRD_EN(x) ((x) << S_LANE8_REC_OVRD_EN)
11667 #define F_LANE8_REC_OVRD_EN    V_LANE8_REC_OVRD_EN(1U)
11670 #define V_LANE7_REC_OVRD_EN(x) ((x) << S_LANE7_REC_OVRD_EN)
11671 #define F_LANE7_REC_OVRD_EN    V_LANE7_REC_OVRD_EN(1U)
11674 #define V_LANE6_REC_OVRD_EN(x) ((x) << S_LANE6_REC_OVRD_EN)
11675 #define F_LANE6_REC_OVRD_EN    V_LANE6_REC_OVRD_EN(1U)
11678 #define V_LANE5_REC_OVRD_EN(x) ((x) << S_LANE5_REC_OVRD_EN)
11679 #define F_LANE5_REC_OVRD_EN    V_LANE5_REC_OVRD_EN(1U)
11682 #define V_LANE4_REC_OVRD_EN(x) ((x) << S_LANE4_REC_OVRD_EN)
11683 #define F_LANE4_REC_OVRD_EN    V_LANE4_REC_OVRD_EN(1U)
11686 #define V_LANE3_REC_OVRD_EN(x) ((x) << S_LANE3_REC_OVRD_EN)
11687 #define F_LANE3_REC_OVRD_EN    V_LANE3_REC_OVRD_EN(1U)
11690 #define V_LANE2_REC_OVRD_EN(x) ((x) << S_LANE2_REC_OVRD_EN)
11691 #define F_LANE2_REC_OVRD_EN    V_LANE2_REC_OVRD_EN(1U)
11694 #define V_LANE1_REC_OVRD_EN(x) ((x) << S_LANE1_REC_OVRD_EN)
11695 #define F_LANE1_REC_OVRD_EN    V_LANE1_REC_OVRD_EN(1U)
11698 #define V_LANE0_REC_OVRD_EN(x) ((x) << S_LANE0_REC_OVRD_EN)
11699 #define F_LANE0_REC_OVRD_EN    V_LANE0_REC_OVRD_EN(1U)
11702 #define V_LANE15_TX2RX_LOOPBK(x) ((x) << S_LANE15_TX2RX_LOOPBK)
11703 #define F_LANE15_TX2RX_LOOPBK    V_LANE15_TX2RX_LOOPBK(1U)
11706 #define V_LANE14_TX2RX_LOOPBK(x) ((x) << S_LANE14_TX2RX_LOOPBK)
11707 #define F_LANE14_TX2RX_LOOPBK    V_LANE14_TX2RX_LOOPBK(1U)
11710 #define V_LANE13_TX2RX_LOOPBK(x) ((x) << S_LANE13_TX2RX_LOOPBK)
11711 #define F_LANE13_TX2RX_LOOPBK    V_LANE13_TX2RX_LOOPBK(1U)
11714 #define V_LANE12_TX2RX_LOOPBK(x) ((x) << S_LANE12_TX2RX_LOOPBK)
11715 #define F_LANE12_TX2RX_LOOPBK    V_LANE12_TX2RX_LOOPBK(1U)
11718 #define V_LANE11_TX2RX_LOOPBK(x) ((x) << S_LANE11_TX2RX_LOOPBK)
11719 #define F_LANE11_TX2RX_LOOPBK    V_LANE11_TX2RX_LOOPBK(1U)
11722 #define V_LANE10_TX2RX_LOOPBK(x) ((x) << S_LANE10_TX2RX_LOOPBK)
11723 #define F_LANE10_TX2RX_LOOPBK    V_LANE10_TX2RX_LOOPBK(1U)
11726 #define V_LANE9_TX2RX_LOOPBK(x) ((x) << S_LANE9_TX2RX_LOOPBK)
11727 #define F_LANE9_TX2RX_LOOPBK    V_LANE9_TX2RX_LOOPBK(1U)
11730 #define V_LANE8_TX2RX_LOOPBK(x) ((x) << S_LANE8_TX2RX_LOOPBK)
11731 #define F_LANE8_TX2RX_LOOPBK    V_LANE8_TX2RX_LOOPBK(1U)
11734 #define V_LANE7_TX2RX_LOOPBK(x) ((x) << S_LANE7_TX2RX_LOOPBK)
11735 #define F_LANE7_TX2RX_LOOPBK    V_LANE7_TX2RX_LOOPBK(1U)
11738 #define V_LANE6_TX2RX_LOOPBK(x) ((x) << S_LANE6_TX2RX_LOOPBK)
11739 #define F_LANE6_TX2RX_LOOPBK    V_LANE6_TX2RX_LOOPBK(1U)
11742 #define V_LANE5_TX2RX_LOOPBK(x) ((x) << S_LANE5_TX2RX_LOOPBK)
11743 #define F_LANE5_TX2RX_LOOPBK    V_LANE5_TX2RX_LOOPBK(1U)
11746 #define V_LANE4_TX2RX_LOOPBK(x) ((x) << S_LANE4_TX2RX_LOOPBK)
11747 #define F_LANE4_TX2RX_LOOPBK    V_LANE4_TX2RX_LOOPBK(1U)
11750 #define V_LANE3_TX2RX_LOOPBK(x) ((x) << S_LANE3_TX2RX_LOOPBK)
11751 #define F_LANE3_TX2RX_LOOPBK    V_LANE3_TX2RX_LOOPBK(1U)
11754 #define V_LANE2_TX2RX_LOOPBK(x) ((x) << S_LANE2_TX2RX_LOOPBK)
11755 #define F_LANE2_TX2RX_LOOPBK    V_LANE2_TX2RX_LOOPBK(1U)
11757 #define S_LANE1_TX2RX_LOOPBK    1
11758 #define V_LANE1_TX2RX_LOOPBK(x) ((x) << S_LANE1_TX2RX_LOOPBK)
11759 #define F_LANE1_TX2RX_LOOPBK    V_LANE1_TX2RX_LOOPBK(1U)
11762 #define V_LANE0_TX2RX_LOOPBK(x) ((x) << S_LANE0_TX2RX_LOOPBK)
11763 #define F_LANE0_TX2RX_LOOPBK    V_LANE0_TX2RX_LOOPBK(1U)
11769 #define V_UPCS_PIPE_CONFIG(x) ((x) << S_UPCS_PIPE_CONFIG)
11770 #define G_UPCS_PIPE_CONFIG(x) (((x) >> S_UPCS_PIPE_CONFIG) & M_UPCS_PIPE_CONFIG)
11773 #define V_TX15_DISABLE(x) ((x) << S_TX15_DISABLE)
11774 #define F_TX15_DISABLE    V_TX15_DISABLE(1U)
11777 #define V_TX14_DISABLE(x) ((x) << S_TX14_DISABLE)
11778 #define F_TX14_DISABLE    V_TX14_DISABLE(1U)
11781 #define V_TX13_DISABLE(x) ((x) << S_TX13_DISABLE)
11782 #define F_TX13_DISABLE    V_TX13_DISABLE(1U)
11785 #define V_TX12_DISABLE(x) ((x) << S_TX12_DISABLE)
11786 #define F_TX12_DISABLE    V_TX12_DISABLE(1U)
11789 #define V_TX11_DISABLE(x) ((x) << S_TX11_DISABLE)
11790 #define F_TX11_DISABLE    V_TX11_DISABLE(1U)
11793 #define V_TX10_DISABLE(x) ((x) << S_TX10_DISABLE)
11794 #define F_TX10_DISABLE    V_TX10_DISABLE(1U)
11797 #define V_TX9_DISABLE(x) ((x) << S_TX9_DISABLE)
11798 #define F_TX9_DISABLE    V_TX9_DISABLE(1U)
11801 #define V_TX8_DISABLE(x) ((x) << S_TX8_DISABLE)
11802 #define F_TX8_DISABLE    V_TX8_DISABLE(1U)
11805 #define V_TX7_DISABLE(x) ((x) << S_TX7_DISABLE)
11806 #define F_TX7_DISABLE    V_TX7_DISABLE(1U)
11809 #define V_TX6_DISABLE(x) ((x) << S_TX6_DISABLE)
11810 #define F_TX6_DISABLE    V_TX6_DISABLE(1U)
11813 #define V_TX5_DISABLE(x) ((x) << S_TX5_DISABLE)
11814 #define F_TX5_DISABLE    V_TX5_DISABLE(1U)
11817 #define V_TX4_DISABLE(x) ((x) << S_TX4_DISABLE)
11818 #define F_TX4_DISABLE    V_TX4_DISABLE(1U)
11821 #define V_TX3_DISABLE(x) ((x) << S_TX3_DISABLE)
11822 #define F_TX3_DISABLE    V_TX3_DISABLE(1U)
11825 #define V_TX2_DISABLE(x) ((x) << S_TX2_DISABLE)
11826 #define F_TX2_DISABLE    V_TX2_DISABLE(1U)
11828 #define S_TX1_DISABLE    1
11829 #define V_TX1_DISABLE(x) ((x) << S_TX1_DISABLE)
11830 #define F_TX1_DISABLE    V_TX1_DISABLE(1U)
11833 #define V_TX0_DISABLE(x) ((x) << S_TX0_DISABLE)
11834 #define F_TX0_DISABLE    V_TX0_DISABLE(1U)
11842 #define V_TAGQ_CH0_TAGS_USED(x) ((x) << S_TAGQ_CH0_TAGS_USED)
11843 #define G_TAGQ_CH0_TAGS_USED(x) (((x) >> S_TAGQ_CH0_TAGS_USED) & M_TAGQ_CH0_TAGS_USED)
11846 #define V_REQ_CH0_DATA_EMPTY(x) ((x) << S_REQ_CH0_DATA_EMPTY)
11847 #define F_REQ_CH0_DATA_EMPTY    V_REQ_CH0_DATA_EMPTY(1U)
11850 #define V_RDQ_CH0_REQ_EMPTY(x) ((x) << S_RDQ_CH0_REQ_EMPTY)
11851 #define F_RDQ_CH0_REQ_EMPTY    V_RDQ_CH0_REQ_EMPTY(1U)
11854 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ)
11855 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH0_WAIT_FOR_TAGTQ(1U)
11858 #define V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_CMD)
11859 #define F_REQ_CTL_RD_CH0_WAIT_FOR_CMD    V_REQ_CTL_RD_CH0_WAIT_FOR_CMD(1U)
11862 #define V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM)
11863 #define F_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH0_WAIT_FOR_DATA_MEM(1U)
11866 #define V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_RDQ)
11867 #define F_REQ_CTL_RD_CH0_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH0_WAIT_FOR_RDQ(1U)
11870 #define V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO)
11871 #define F_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH0_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11874 #define V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED)
11875 #define F_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_BOT_VLD_STARTED(1U)
11878 #define V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED)
11879 #define F_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH0_EXIT_TOP_VLD_STARTED(1U)
11881 #define S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    1
11882 #define V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE)
11883 #define F_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH0_WAIT_FOR_PAUSE(1U)
11886 #define V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA)
11887 #define F_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA(1U)
11893 #define V_TAGQ_CH1_TAGS_USED(x) ((x) << S_TAGQ_CH1_TAGS_USED)
11894 #define G_TAGQ_CH1_TAGS_USED(x) (((x) >> S_TAGQ_CH1_TAGS_USED) & M_TAGQ_CH1_TAGS_USED)
11897 #define V_REQ_CH1_DATA_EMPTY(x) ((x) << S_REQ_CH1_DATA_EMPTY)
11898 #define F_REQ_CH1_DATA_EMPTY    V_REQ_CH1_DATA_EMPTY(1U)
11901 #define V_RDQ_CH1_REQ_EMPTY(x) ((x) << S_RDQ_CH1_REQ_EMPTY)
11902 #define F_RDQ_CH1_REQ_EMPTY    V_RDQ_CH1_REQ_EMPTY(1U)
11905 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ)
11906 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH1_WAIT_FOR_TAGTQ(1U)
11909 #define V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_CMD)
11910 #define F_REQ_CTL_RD_CH1_WAIT_FOR_CMD    V_REQ_CTL_RD_CH1_WAIT_FOR_CMD(1U)
11913 #define V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM)
11914 #define F_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH1_WAIT_FOR_DATA_MEM(1U)
11917 #define V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_RDQ)
11918 #define F_REQ_CTL_RD_CH1_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH1_WAIT_FOR_RDQ(1U)
11921 #define V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO)
11922 #define F_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH1_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11925 #define V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED)
11926 #define F_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_BOT_VLD_STARTED(1U)
11929 #define V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED)
11930 #define F_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH1_EXIT_TOP_VLD_STARTED(1U)
11932 #define S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    1
11933 #define V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE)
11934 #define F_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH1_WAIT_FOR_PAUSE(1U)
11937 #define V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA)
11938 #define F_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA(1U)
11944 #define V_TAGQ_CH2_TAGS_USED(x) ((x) << S_TAGQ_CH2_TAGS_USED)
11945 #define G_TAGQ_CH2_TAGS_USED(x) (((x) >> S_TAGQ_CH2_TAGS_USED) & M_TAGQ_CH2_TAGS_USED)
11948 #define V_REQ_CH2_DATA_EMPTY(x) ((x) << S_REQ_CH2_DATA_EMPTY)
11949 #define F_REQ_CH2_DATA_EMPTY    V_REQ_CH2_DATA_EMPTY(1U)
11952 #define V_RDQ_CH2_REQ_EMPTY(x) ((x) << S_RDQ_CH2_REQ_EMPTY)
11953 #define F_RDQ_CH2_REQ_EMPTY    V_RDQ_CH2_REQ_EMPTY(1U)
11956 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ)
11957 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH2_WAIT_FOR_TAGTQ(1U)
11960 #define V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_CMD)
11961 #define F_REQ_CTL_RD_CH2_WAIT_FOR_CMD    V_REQ_CTL_RD_CH2_WAIT_FOR_CMD(1U)
11964 #define V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM)
11965 #define F_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH2_WAIT_FOR_DATA_MEM(1U)
11968 #define V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_RDQ)
11969 #define F_REQ_CTL_RD_CH2_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH2_WAIT_FOR_RDQ(1U)
11972 #define V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO)
11973 #define F_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH2_WAIT_FOR_TXN_DISABLE_FIFO(1U)
11976 #define V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED)
11977 #define F_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_BOT_VLD_STARTED(1U)
11980 #define V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED)
11981 #define F_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH2_EXIT_TOP_VLD_STARTED(1U)
11983 #define S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    1
11984 #define V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE)
11985 #define F_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH2_WAIT_FOR_PAUSE(1U)
11988 #define V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA)
11989 #define F_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA(1U)
11995 #define V_TAGQ_CH3_TAGS_USED(x) ((x) << S_TAGQ_CH3_TAGS_USED)
11996 #define G_TAGQ_CH3_TAGS_USED(x) (((x) >> S_TAGQ_CH3_TAGS_USED) & M_TAGQ_CH3_TAGS_USED)
11999 #define V_REQ_CH3_DATA_EMPTY(x) ((x) << S_REQ_CH3_DATA_EMPTY)
12000 #define F_REQ_CH3_DATA_EMPTY    V_REQ_CH3_DATA_EMPTY(1U)
12003 #define V_RDQ_CH3_REQ_EMPTY(x) ((x) << S_RDQ_CH3_REQ_EMPTY)
12004 #define F_RDQ_CH3_REQ_EMPTY    V_RDQ_CH3_REQ_EMPTY(1U)
12007 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ)
12008 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH3_WAIT_FOR_TAGTQ(1U)
12011 #define V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_CMD)
12012 #define F_REQ_CTL_RD_CH3_WAIT_FOR_CMD    V_REQ_CTL_RD_CH3_WAIT_FOR_CMD(1U)
12015 #define V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM)
12016 #define F_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH3_WAIT_FOR_DATA_MEM(1U)
12019 #define V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_RDQ)
12020 #define F_REQ_CTL_RD_CH3_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH3_WAIT_FOR_RDQ(1U)
12023 #define V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO)
12024 #define F_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH3_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12027 #define V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED)
12028 #define F_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_BOT_VLD_STARTED(1U)
12031 #define V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED)
12032 #define F_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH3_EXIT_TOP_VLD_STARTED(1U)
12034 #define S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    1
12035 #define V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE)
12036 #define F_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH3_WAIT_FOR_PAUSE(1U)
12039 #define V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA)
12040 #define F_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA(1U)
12046 #define V_TAGQ_CH4_TAGS_USED(x) ((x) << S_TAGQ_CH4_TAGS_USED)
12047 #define G_TAGQ_CH4_TAGS_USED(x) (((x) >> S_TAGQ_CH4_TAGS_USED) & M_TAGQ_CH4_TAGS_USED)
12050 #define V_REQ_CH4_DATA_EMPTY(x) ((x) << S_REQ_CH4_DATA_EMPTY)
12051 #define F_REQ_CH4_DATA_EMPTY    V_REQ_CH4_DATA_EMPTY(1U)
12054 #define V_RDQ_CH4_REQ_EMPTY(x) ((x) << S_RDQ_CH4_REQ_EMPTY)
12055 #define F_RDQ_CH4_REQ_EMPTY    V_RDQ_CH4_REQ_EMPTY(1U)
12058 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ)
12059 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH4_WAIT_FOR_TAGTQ(1U)
12062 #define V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_CMD)
12063 #define F_REQ_CTL_RD_CH4_WAIT_FOR_CMD    V_REQ_CTL_RD_CH4_WAIT_FOR_CMD(1U)
12066 #define V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM)
12067 #define F_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH4_WAIT_FOR_DATA_MEM(1U)
12070 #define V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_RDQ)
12071 #define F_REQ_CTL_RD_CH4_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH4_WAIT_FOR_RDQ(1U)
12074 #define V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO)
12075 #define F_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH4_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12078 #define V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED)
12079 #define F_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_BOT_VLD_STARTED(1U)
12082 #define V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED)
12083 #define F_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH4_EXIT_TOP_VLD_STARTED(1U)
12085 #define S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    1
12086 #define V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE)
12087 #define F_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH4_WAIT_FOR_PAUSE(1U)
12090 #define V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA)
12091 #define F_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA(1U)
12097 #define V_TAGQ_CH5_TAGS_USED(x) ((x) << S_TAGQ_CH5_TAGS_USED)
12098 #define G_TAGQ_CH5_TAGS_USED(x) (((x) >> S_TAGQ_CH5_TAGS_USED) & M_TAGQ_CH5_TAGS_USED)
12101 #define V_REQ_CH5_DATA_EMPTY(x) ((x) << S_REQ_CH5_DATA_EMPTY)
12102 #define F_REQ_CH5_DATA_EMPTY    V_REQ_CH5_DATA_EMPTY(1U)
12105 #define V_RDQ_CH5_REQ_EMPTY(x) ((x) << S_RDQ_CH5_REQ_EMPTY)
12106 #define F_RDQ_CH5_REQ_EMPTY    V_RDQ_CH5_REQ_EMPTY(1U)
12109 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ)
12110 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH5_WAIT_FOR_TAGTQ(1U)
12113 #define V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_CMD)
12114 #define F_REQ_CTL_RD_CH5_WAIT_FOR_CMD    V_REQ_CTL_RD_CH5_WAIT_FOR_CMD(1U)
12117 #define V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM)
12118 #define F_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH5_WAIT_FOR_DATA_MEM(1U)
12121 #define V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_RDQ)
12122 #define F_REQ_CTL_RD_CH5_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH5_WAIT_FOR_RDQ(1U)
12125 #define V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO)
12126 #define F_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH5_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12129 #define V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED)
12130 #define F_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_BOT_VLD_STARTED(1U)
12133 #define V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED)
12134 #define F_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH5_EXIT_TOP_VLD_STARTED(1U)
12136 #define S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    1
12137 #define V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE)
12138 #define F_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH5_WAIT_FOR_PAUSE(1U)
12141 #define V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA)
12142 #define F_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA(1U)
12148 #define V_TAGQ_CH6_TAGS_USED(x) ((x) << S_TAGQ_CH6_TAGS_USED)
12149 #define G_TAGQ_CH6_TAGS_USED(x) (((x) >> S_TAGQ_CH6_TAGS_USED) & M_TAGQ_CH6_TAGS_USED)
12152 #define V_REQ_CH6_DATA_EMPTY(x) ((x) << S_REQ_CH6_DATA_EMPTY)
12153 #define F_REQ_CH6_DATA_EMPTY    V_REQ_CH6_DATA_EMPTY(1U)
12156 #define V_RDQ_CH6_REQ_EMPTY(x) ((x) << S_RDQ_CH6_REQ_EMPTY)
12157 #define F_RDQ_CH6_REQ_EMPTY    V_RDQ_CH6_REQ_EMPTY(1U)
12160 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ)
12161 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH6_WAIT_FOR_TAGTQ(1U)
12164 #define V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_CMD)
12165 #define F_REQ_CTL_RD_CH6_WAIT_FOR_CMD    V_REQ_CTL_RD_CH6_WAIT_FOR_CMD(1U)
12168 #define V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM)
12169 #define F_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH6_WAIT_FOR_DATA_MEM(1U)
12172 #define V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_RDQ)
12173 #define F_REQ_CTL_RD_CH6_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH6_WAIT_FOR_RDQ(1U)
12176 #define V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO)
12177 #define F_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH6_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12180 #define V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED)
12181 #define F_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_BOT_VLD_STARTED(1U)
12184 #define V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED)
12185 #define F_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH6_EXIT_TOP_VLD_STARTED(1U)
12187 #define S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    1
12188 #define V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE)
12189 #define F_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH6_WAIT_FOR_PAUSE(1U)
12192 #define V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA)
12193 #define F_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA(1U)
12199 #define V_TAGQ_CH7_TAGS_USED(x) ((x) << S_TAGQ_CH7_TAGS_USED)
12200 #define G_TAGQ_CH7_TAGS_USED(x) (((x) >> S_TAGQ_CH7_TAGS_USED) & M_TAGQ_CH7_TAGS_USED)
12203 #define V_REQ_CH7_DATA_EMPTY(x) ((x) << S_REQ_CH7_DATA_EMPTY)
12204 #define F_REQ_CH7_DATA_EMPTY    V_REQ_CH7_DATA_EMPTY(1U)
12207 #define V_RDQ_CH7_REQ_EMPTY(x) ((x) << S_RDQ_CH7_REQ_EMPTY)
12208 #define F_RDQ_CH7_REQ_EMPTY    V_RDQ_CH7_REQ_EMPTY(1U)
12211 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ)
12212 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ    V_REQ_CTL_RD_CH7_WAIT_FOR_TAGTQ(1U)
12215 #define V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_CMD)
12216 #define F_REQ_CTL_RD_CH7_WAIT_FOR_CMD    V_REQ_CTL_RD_CH7_WAIT_FOR_CMD(1U)
12219 #define V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM)
12220 #define F_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM    V_REQ_CTL_RD_CH7_WAIT_FOR_DATA_MEM(1U)
12223 #define V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_RDQ)
12224 #define F_REQ_CTL_RD_CH7_WAIT_FOR_RDQ    V_REQ_CTL_RD_CH7_WAIT_FOR_RDQ(1U)
12227 #define V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO)
12228 #define F_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO    V_REQ_CTL_RD_CH7_WAIT_FOR_TXN_DISABLE_FIFO(1U)
12231 #define V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED)
12232 #define F_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_BOT_VLD_STARTED(1U)
12235 #define V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED)
12236 #define F_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED    V_REQ_CTL_RD_CH7_EXIT_TOP_VLD_STARTED(1U)
12238 #define S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    1
12239 #define V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE)
12240 #define F_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE    V_REQ_CTL_RD_CH7_WAIT_FOR_PAUSE(1U)
12243 #define V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA)
12244 #define F_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    V_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA(1U)
12249 #define V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM)
12250 #define F_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH0_WAIT_FOR_SEQNUM(1U)
12254 #define V_REQ_CTL_WR_CH0_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH0_SEQNUM)
12255 #define G_REQ_CTL_WR_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH0_SEQNUM) & M_REQ_CTL_WR_CH0_SEQNUM)
12259 #define V_REQ_CTL_RD_CH0_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH0_SEQNUM)
12260 #define G_REQ_CTL_RD_CH0_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH0_SEQNUM) & M_REQ_CTL_RD_CH0_SEQNUM)
12263 #define V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO)
12264 #define F_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH0_WAIT_FOR_SI_FIFO(1U)
12267 #define V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED)
12268 #define F_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_BOT_VLD_STARTED(1U)
12271 #define V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED)
12272 #define F_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH0_EXIT_TOP_VLD_STARTED(1U)
12274 #define S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    1
12275 #define V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE)
12276 #define F_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH0_WAIT_FOR_PAUSE(1U)
12279 #define V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA)
12280 #define F_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA(1U)
12285 #define V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM)
12286 #define F_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH1_WAIT_FOR_SEQNUM(1U)
12290 #define V_REQ_CTL_WR_CH1_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH1_SEQNUM)
12291 #define G_REQ_CTL_WR_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH1_SEQNUM) & M_REQ_CTL_WR_CH1_SEQNUM)
12295 #define V_REQ_CTL_RD_CH1_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH1_SEQNUM)
12296 #define G_REQ_CTL_RD_CH1_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH1_SEQNUM) & M_REQ_CTL_RD_CH1_SEQNUM)
12299 #define V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO)
12300 #define F_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH1_WAIT_FOR_SI_FIFO(1U)
12303 #define V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED)
12304 #define F_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_BOT_VLD_STARTED(1U)
12307 #define V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED)
12308 #define F_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH1_EXIT_TOP_VLD_STARTED(1U)
12310 #define S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    1
12311 #define V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE)
12312 #define F_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH1_WAIT_FOR_PAUSE(1U)
12315 #define V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA)
12316 #define F_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA(1U)
12321 #define V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM)
12322 #define F_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH2_WAIT_FOR_SEQNUM(1U)
12326 #define V_REQ_CTL_WR_CH2_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH2_SEQNUM)
12327 #define G_REQ_CTL_WR_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH2_SEQNUM) & M_REQ_CTL_WR_CH2_SEQNUM)
12331 #define V_REQ_CTL_RD_CH2_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH2_SEQNUM)
12332 #define G_REQ_CTL_RD_CH2_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH2_SEQNUM) & M_REQ_CTL_RD_CH2_SEQNUM)
12335 #define V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO)
12336 #define F_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH2_WAIT_FOR_SI_FIFO(1U)
12339 #define V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED)
12340 #define F_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_BOT_VLD_STARTED(1U)
12343 #define V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED)
12344 #define F_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH2_EXIT_TOP_VLD_STARTED(1U)
12346 #define S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    1
12347 #define V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE)
12348 #define F_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH2_WAIT_FOR_PAUSE(1U)
12351 #define V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA)
12352 #define F_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA(1U)
12357 #define V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM)
12358 #define F_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH3_WAIT_FOR_SEQNUM(1U)
12362 #define V_REQ_CTL_WR_CH3_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH3_SEQNUM)
12363 #define G_REQ_CTL_WR_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH3_SEQNUM) & M_REQ_CTL_WR_CH3_SEQNUM)
12367 #define V_REQ_CTL_RD_CH3_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH3_SEQNUM)
12368 #define G_REQ_CTL_RD_CH3_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH3_SEQNUM) & M_REQ_CTL_RD_CH3_SEQNUM)
12371 #define V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO)
12372 #define F_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH3_WAIT_FOR_SI_FIFO(1U)
12375 #define V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED)
12376 #define F_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_BOT_VLD_STARTED(1U)
12379 #define V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED)
12380 #define F_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH3_EXIT_TOP_VLD_STARTED(1U)
12382 #define S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    1
12383 #define V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE)
12384 #define F_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH3_WAIT_FOR_PAUSE(1U)
12387 #define V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA)
12388 #define F_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA(1U)
12393 #define V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM)
12394 #define F_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM    V_REQ_CTL_RD_CH4_WAIT_FOR_SEQNUM(1U)
12398 #define V_REQ_CTL_WR_CH4_SEQNUM(x) ((x) << S_REQ_CTL_WR_CH4_SEQNUM)
12399 #define G_REQ_CTL_WR_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_WR_CH4_SEQNUM) & M_REQ_CTL_WR_CH4_SEQNUM)
12403 #define V_REQ_CTL_RD_CH4_SEQNUM(x) ((x) << S_REQ_CTL_RD_CH4_SEQNUM)
12404 #define G_REQ_CTL_RD_CH4_SEQNUM(x) (((x) >> S_REQ_CTL_RD_CH4_SEQNUM) & M_REQ_CTL_RD_CH4_SEQNUM)
12407 #define V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO)
12408 #define F_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO    V_REQ_CTL_WR_CH4_WAIT_FOR_SI_FIFO(1U)
12411 #define V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED)
12412 #define F_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_BOT_VLD_STARTED(1U)
12415 #define V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(x) ((x) << S_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED)
12416 #define F_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED    V_REQ_CTL_WR_CH4_EXIT_TOP_VLD_STARTED(1U)
12418 #define S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    1
12419 #define V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE)
12420 #define F_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE    V_REQ_CTL_WR_CH4_WAIT_FOR_PAUSE(1U)
12423 #define V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(x) ((x) << S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA)
12424 #define F_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    V_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA(1U)
12430 #define V_PIPE0_TX3_DATAK_0(x) ((x) << S_PIPE0_TX3_DATAK_0)
12431 #define F_PIPE0_TX3_DATAK_0    V_PIPE0_TX3_DATAK_0(1U)
12435 #define V_PIPE0_TX3_DATA_6_0(x) ((x) << S_PIPE0_TX3_DATA_6_0)
12436 #define G_PIPE0_TX3_DATA_6_0(x) (((x) >> S_PIPE0_TX3_DATA_6_0) & M_PIPE0_TX3_DATA_6_0)
12440 #define V_PIPE0_TX2_DATA_7_0(x) ((x) << S_PIPE0_TX2_DATA_7_0)
12441 #define G_PIPE0_TX2_DATA_7_0(x) (((x) >> S_PIPE0_TX2_DATA_7_0) & M_PIPE0_TX2_DATA_7_0)
12445 #define V_PIPE0_TX1_DATA_7_0(x) ((x) << S_PIPE0_TX1_DATA_7_0)
12446 #define G_PIPE0_TX1_DATA_7_0(x) (((x) >> S_PIPE0_TX1_DATA_7_0) & M_PIPE0_TX1_DATA_7_0)
12449 #define V_PIPE0_TX0_DATAK_0(x) ((x) << S_PIPE0_TX0_DATAK_0)
12450 #define F_PIPE0_TX0_DATAK_0    V_PIPE0_TX0_DATAK_0(1U)
12454 #define V_PIPE0_TX0_DATA_6_0(x) ((x) << S_PIPE0_TX0_DATA_6_0)
12455 #define G_PIPE0_TX0_DATA_6_0(x) (((x) >> S_PIPE0_TX0_DATA_6_0) & M_PIPE0_TX0_DATA_6_0)
12460 #define V_PIPE0_TX3_DATAK_1(x) ((x) << S_PIPE0_TX3_DATAK_1)
12461 #define F_PIPE0_TX3_DATAK_1    V_PIPE0_TX3_DATAK_1(1U)
12465 #define V_PIPE0_TX3_DATA_14_8(x) ((x) << S_PIPE0_TX3_DATA_14_8)
12466 #define G_PIPE0_TX3_DATA_14_8(x) (((x) >> S_PIPE0_TX3_DATA_14_8) & M_PIPE0_TX3_DATA_14_8)
12470 #define V_PIPE0_TX2_DATA_15_8(x) ((x) << S_PIPE0_TX2_DATA_15_8)
12471 #define G_PIPE0_TX2_DATA_15_8(x) (((x) >> S_PIPE0_TX2_DATA_15_8) & M_PIPE0_TX2_DATA_15_8)
12475 #define V_PIPE0_TX1_DATA_15_8(x) ((x) << S_PIPE0_TX1_DATA_15_8)
12476 #define G_PIPE0_TX1_DATA_15_8(x) (((x) >> S_PIPE0_TX1_DATA_15_8) & M_PIPE0_TX1_DATA_15_8)
12479 #define V_PIPE0_TX0_DATAK_1(x) ((x) << S_PIPE0_TX0_DATAK_1)
12480 #define F_PIPE0_TX0_DATAK_1    V_PIPE0_TX0_DATAK_1(1U)
12484 #define V_PIPE0_TX0_DATA_14_8(x) ((x) << S_PIPE0_TX0_DATA_14_8)
12485 #define G_PIPE0_TX0_DATA_14_8(x) (((x) >> S_PIPE0_TX0_DATA_14_8) & M_PIPE0_TX0_DATA_14_8)
12490 #define V_PIPE0_TX7_DATAK_0(x) ((x) << S_PIPE0_TX7_DATAK_0)
12491 #define F_PIPE0_TX7_DATAK_0    V_PIPE0_TX7_DATAK_0(1U)
12495 #define V_PIPE0_TX7_DATA_6_0(x) ((x) << S_PIPE0_TX7_DATA_6_0)
12496 #define G_PIPE0_TX7_DATA_6_0(x) (((x) >> S_PIPE0_TX7_DATA_6_0) & M_PIPE0_TX7_DATA_6_0)
12500 #define V_PIPE0_TX6_DATA_7_0(x) ((x) << S_PIPE0_TX6_DATA_7_0)
12501 #define G_PIPE0_TX6_DATA_7_0(x) (((x) >> S_PIPE0_TX6_DATA_7_0) & M_PIPE0_TX6_DATA_7_0)
12505 #define V_PIPE0_TX5_DATA_7_0(x) ((x) << S_PIPE0_TX5_DATA_7_0)
12506 #define G_PIPE0_TX5_DATA_7_0(x) (((x) >> S_PIPE0_TX5_DATA_7_0) & M_PIPE0_TX5_DATA_7_0)
12509 #define V_PIPE0_TX4_DATAK_0(x) ((x) << S_PIPE0_TX4_DATAK_0)
12510 #define F_PIPE0_TX4_DATAK_0    V_PIPE0_TX4_DATAK_0(1U)
12514 #define V_PIPE0_TX4_DATA_6_0(x) ((x) << S_PIPE0_TX4_DATA_6_0)
12515 #define G_PIPE0_TX4_DATA_6_0(x) (((x) >> S_PIPE0_TX4_DATA_6_0) & M_PIPE0_TX4_DATA_6_0)
12520 #define V_PIPE0_TX7_DATAK_1(x) ((x) << S_PIPE0_TX7_DATAK_1)
12521 #define F_PIPE0_TX7_DATAK_1    V_PIPE0_TX7_DATAK_1(1U)
12525 #define V_PIPE0_TX7_DATA_14_8(x) ((x) << S_PIPE0_TX7_DATA_14_8)
12526 #define G_PIPE0_TX7_DATA_14_8(x) (((x) >> S_PIPE0_TX7_DATA_14_8) & M_PIPE0_TX7_DATA_14_8)
12530 #define V_PIPE0_TX6_DATA_15_8(x) ((x) << S_PIPE0_TX6_DATA_15_8)
12531 #define G_PIPE0_TX6_DATA_15_8(x) (((x) >> S_PIPE0_TX6_DATA_15_8) & M_PIPE0_TX6_DATA_15_8)
12535 #define V_PIPE0_TX5_DATA_15_8(x) ((x) << S_PIPE0_TX5_DATA_15_8)
12536 #define G_PIPE0_TX5_DATA_15_8(x) (((x) >> S_PIPE0_TX5_DATA_15_8) & M_PIPE0_TX5_DATA_15_8)
12539 #define V_PIPE0_TX4_DATAK_1(x) ((x) << S_PIPE0_TX4_DATAK_1)
12540 #define F_PIPE0_TX4_DATAK_1    V_PIPE0_TX4_DATAK_1(1U)
12544 #define V_PIPE0_TX4_DATA_14_8(x) ((x) << S_PIPE0_TX4_DATA_14_8)
12545 #define G_PIPE0_TX4_DATA_14_8(x) (((x) >> S_PIPE0_TX4_DATA_14_8) & M_PIPE0_TX4_DATA_14_8)
12550 #define V_PIPE0_RX3_VALID_14(x) ((x) << S_PIPE0_RX3_VALID_14)
12551 #define F_PIPE0_RX3_VALID_14    V_PIPE0_RX3_VALID_14(1U)
12555 #define V_PIPE0_RX3_VALID2_14(x) ((x) << S_PIPE0_RX3_VALID2_14)
12556 #define G_PIPE0_RX3_VALID2_14(x) (((x) >> S_PIPE0_RX3_VALID2_14) & M_PIPE0_RX3_VALID2_14)
12560 #define V_PIPE0_RX2_VALID_14(x) ((x) << S_PIPE0_RX2_VALID_14)
12561 #define G_PIPE0_RX2_VALID_14(x) (((x) >> S_PIPE0_RX2_VALID_14) & M_PIPE0_RX2_VALID_14)
12565 #define V_PIPE0_RX1_VALID_14(x) ((x) << S_PIPE0_RX1_VALID_14)
12566 #define G_PIPE0_RX1_VALID_14(x) (((x) >> S_PIPE0_RX1_VALID_14) & M_PIPE0_RX1_VALID_14)
12569 #define V_PIPE0_RX0_VALID_14(x) ((x) << S_PIPE0_RX0_VALID_14)
12570 #define F_PIPE0_RX0_VALID_14    V_PIPE0_RX0_VALID_14(1U)
12574 #define V_PIPE0_RX0_VALID2_14(x) ((x) << S_PIPE0_RX0_VALID2_14)
12575 #define G_PIPE0_RX0_VALID2_14(x) (((x) >> S_PIPE0_RX0_VALID2_14) & M_PIPE0_RX0_VALID2_14)
12580 #define V_PIPE0_RX3_VALID_15(x) ((x) << S_PIPE0_RX3_VALID_15)
12581 #define F_PIPE0_RX3_VALID_15    V_PIPE0_RX3_VALID_15(1U)
12585 #define V_PIPE0_RX3_VALID2_15(x) ((x) << S_PIPE0_RX3_VALID2_15)
12586 #define G_PIPE0_RX3_VALID2_15(x) (((x) >> S_PIPE0_RX3_VALID2_15) & M_PIPE0_RX3_VALID2_15)
12590 #define V_PIPE0_RX2_VALID_15(x) ((x) << S_PIPE0_RX2_VALID_15)
12591 #define G_PIPE0_RX2_VALID_15(x) (((x) >> S_PIPE0_RX2_VALID_15) & M_PIPE0_RX2_VALID_15)
12595 #define V_PIPE0_RX1_VALID_15(x) ((x) << S_PIPE0_RX1_VALID_15)
12596 #define G_PIPE0_RX1_VALID_15(x) (((x) >> S_PIPE0_RX1_VALID_15) & M_PIPE0_RX1_VALID_15)
12599 #define V_PIPE0_RX0_VALID_15(x) ((x) << S_PIPE0_RX0_VALID_15)
12600 #define F_PIPE0_RX0_VALID_15    V_PIPE0_RX0_VALID_15(1U)
12604 #define V_PIPE0_RX0_VALID2_15(x) ((x) << S_PIPE0_RX0_VALID2_15)
12605 #define G_PIPE0_RX0_VALID2_15(x) (((x) >> S_PIPE0_RX0_VALID2_15) & M_PIPE0_RX0_VALID2_15)
12610 #define V_PIPE0_RX7_VALID_16(x) ((x) << S_PIPE0_RX7_VALID_16)
12611 #define F_PIPE0_RX7_VALID_16    V_PIPE0_RX7_VALID_16(1U)
12615 #define V_PIPE0_RX7_VALID2_16(x) ((x) << S_PIPE0_RX7_VALID2_16)
12616 #define G_PIPE0_RX7_VALID2_16(x) (((x) >> S_PIPE0_RX7_VALID2_16) & M_PIPE0_RX7_VALID2_16)
12620 #define V_PIPE0_RX6_VALID_16(x) ((x) << S_PIPE0_RX6_VALID_16)
12621 #define G_PIPE0_RX6_VALID_16(x) (((x) >> S_PIPE0_RX6_VALID_16) & M_PIPE0_RX6_VALID_16)
12625 #define V_PIPE0_RX5_VALID_16(x) ((x) << S_PIPE0_RX5_VALID_16)
12626 #define G_PIPE0_RX5_VALID_16(x) (((x) >> S_PIPE0_RX5_VALID_16) & M_PIPE0_RX5_VALID_16)
12629 #define V_PIPE0_RX4_VALID_16(x) ((x) << S_PIPE0_RX4_VALID_16)
12630 #define F_PIPE0_RX4_VALID_16    V_PIPE0_RX4_VALID_16(1U)
12634 #define V_PIPE0_RX4_VALID2_16(x) ((x) << S_PIPE0_RX4_VALID2_16)
12635 #define G_PIPE0_RX4_VALID2_16(x) (((x) >> S_PIPE0_RX4_VALID2_16) & M_PIPE0_RX4_VALID2_16)
12640 #define V_PIPE0_RX7_VALID_17(x) ((x) << S_PIPE0_RX7_VALID_17)
12641 #define F_PIPE0_RX7_VALID_17    V_PIPE0_RX7_VALID_17(1U)
12645 #define V_PIPE0_RX7_VALID2_17(x) ((x) << S_PIPE0_RX7_VALID2_17)
12646 #define G_PIPE0_RX7_VALID2_17(x) (((x) >> S_PIPE0_RX7_VALID2_17) & M_PIPE0_RX7_VALID2_17)
12650 #define V_PIPE0_RX6_VALID_17(x) ((x) << S_PIPE0_RX6_VALID_17)
12651 #define G_PIPE0_RX6_VALID_17(x) (((x) >> S_PIPE0_RX6_VALID_17) & M_PIPE0_RX6_VALID_17)
12655 #define V_PIPE0_RX5_VALID_17(x) ((x) << S_PIPE0_RX5_VALID_17)
12656 #define G_PIPE0_RX5_VALID_17(x) (((x) >> S_PIPE0_RX5_VALID_17) & M_PIPE0_RX5_VALID_17)
12659 #define V_PIPE0_RX4_VALID_17(x) ((x) << S_PIPE0_RX4_VALID_17)
12660 #define F_PIPE0_RX4_VALID_17    V_PIPE0_RX4_VALID_17(1U)
12664 #define V_PIPE0_RX4_VALID2_17(x) ((x) << S_PIPE0_RX4_VALID2_17)
12665 #define G_PIPE0_RX4_VALID2_17(x) (((x) >> S_PIPE0_RX4_VALID2_17) & M_PIPE0_RX4_VALID2_17)
12670 #define V_PIPE0_RX7_POLARITY(x) ((x) << S_PIPE0_RX7_POLARITY)
12671 #define F_PIPE0_RX7_POLARITY    V_PIPE0_RX7_POLARITY(1U)
12675 #define V_PIPE0_RX7_STATUS(x) ((x) << S_PIPE0_RX7_STATUS)
12676 #define G_PIPE0_RX7_STATUS(x) (((x) >> S_PIPE0_RX7_STATUS) & M_PIPE0_RX7_STATUS)
12679 #define V_PIPE0_RX6_POLARITY(x) ((x) << S_PIPE0_RX6_POLARITY)
12680 #define F_PIPE0_RX6_POLARITY    V_PIPE0_RX6_POLARITY(1U)
12684 #define V_PIPE0_RX6_STATUS(x) ((x) << S_PIPE0_RX6_STATUS)
12685 #define G_PIPE0_RX6_STATUS(x) (((x) >> S_PIPE0_RX6_STATUS) & M_PIPE0_RX6_STATUS)
12688 #define V_PIPE0_RX5_POLARITY(x) ((x) << S_PIPE0_RX5_POLARITY)
12689 #define F_PIPE0_RX5_POLARITY    V_PIPE0_RX5_POLARITY(1U)
12693 #define V_PIPE0_RX5_STATUS(x) ((x) << S_PIPE0_RX5_STATUS)
12694 #define G_PIPE0_RX5_STATUS(x) (((x) >> S_PIPE0_RX5_STATUS) & M_PIPE0_RX5_STATUS)
12697 #define V_PIPE0_RX4_POLARITY(x) ((x) << S_PIPE0_RX4_POLARITY)
12698 #define F_PIPE0_RX4_POLARITY    V_PIPE0_RX4_POLARITY(1U)
12702 #define V_PIPE0_RX4_STATUS(x) ((x) << S_PIPE0_RX4_STATUS)
12703 #define G_PIPE0_RX4_STATUS(x) (((x) >> S_PIPE0_RX4_STATUS) & M_PIPE0_RX4_STATUS)
12706 #define V_PIPE0_RX3_POLARITY(x) ((x) << S_PIPE0_RX3_POLARITY)
12707 #define F_PIPE0_RX3_POLARITY    V_PIPE0_RX3_POLARITY(1U)
12711 #define V_PIPE0_RX3_STATUS(x) ((x) << S_PIPE0_RX3_STATUS)
12712 #define G_PIPE0_RX3_STATUS(x) (((x) >> S_PIPE0_RX3_STATUS) & M_PIPE0_RX3_STATUS)
12715 #define V_PIPE0_RX2_POLARITY(x) ((x) << S_PIPE0_RX2_POLARITY)
12716 #define F_PIPE0_RX2_POLARITY    V_PIPE0_RX2_POLARITY(1U)
12720 #define V_PIPE0_RX2_STATUS(x) ((x) << S_PIPE0_RX2_STATUS)
12721 #define G_PIPE0_RX2_STATUS(x) (((x) >> S_PIPE0_RX2_STATUS) & M_PIPE0_RX2_STATUS)
12724 #define V_PIPE0_RX1_POLARITY(x) ((x) << S_PIPE0_RX1_POLARITY)
12725 #define F_PIPE0_RX1_POLARITY    V_PIPE0_RX1_POLARITY(1U)
12729 #define V_PIPE0_RX1_STATUS(x) ((x) << S_PIPE0_RX1_STATUS)
12730 #define G_PIPE0_RX1_STATUS(x) (((x) >> S_PIPE0_RX1_STATUS) & M_PIPE0_RX1_STATUS)
12733 #define V_PIPE0_RX0_POLARITY(x) ((x) << S_PIPE0_RX0_POLARITY)
12734 #define F_PIPE0_RX0_POLARITY    V_PIPE0_RX0_POLARITY(1U)
12738 #define V_PIPE0_RX0_STATUS(x) ((x) << S_PIPE0_RX0_STATUS)
12739 #define G_PIPE0_RX0_STATUS(x) (((x) >> S_PIPE0_RX0_STATUS) & M_PIPE0_RX0_STATUS)
12744 #define V_PIPE0_TX7_COMPLIANCE(x) ((x) << S_PIPE0_TX7_COMPLIANCE)
12745 #define F_PIPE0_TX7_COMPLIANCE    V_PIPE0_TX7_COMPLIANCE(1U)
12748 #define V_PIPE0_TX6_COMPLIANCE(x) ((x) << S_PIPE0_TX6_COMPLIANCE)
12749 #define F_PIPE0_TX6_COMPLIANCE    V_PIPE0_TX6_COMPLIANCE(1U)
12752 #define V_PIPE0_TX5_COMPLIANCE(x) ((x) << S_PIPE0_TX5_COMPLIANCE)
12753 #define F_PIPE0_TX5_COMPLIANCE    V_PIPE0_TX5_COMPLIANCE(1U)
12756 #define V_PIPE0_TX4_COMPLIANCE(x) ((x) << S_PIPE0_TX4_COMPLIANCE)
12757 #define F_PIPE0_TX4_COMPLIANCE    V_PIPE0_TX4_COMPLIANCE(1U)
12760 #define V_PIPE0_TX3_COMPLIANCE(x) ((x) << S_PIPE0_TX3_COMPLIANCE)
12761 #define F_PIPE0_TX3_COMPLIANCE    V_PIPE0_TX3_COMPLIANCE(1U)
12764 #define V_PIPE0_TX2_COMPLIANCE(x) ((x) << S_PIPE0_TX2_COMPLIANCE)
12765 #define F_PIPE0_TX2_COMPLIANCE    V_PIPE0_TX2_COMPLIANCE(1U)
12768 #define V_PIPE0_TX1_COMPLIANCE(x) ((x) << S_PIPE0_TX1_COMPLIANCE)
12769 #define F_PIPE0_TX1_COMPLIANCE    V_PIPE0_TX1_COMPLIANCE(1U)
12772 #define V_PIPE0_TX0_COMPLIANCE(x) ((x) << S_PIPE0_TX0_COMPLIANCE)
12773 #define F_PIPE0_TX0_COMPLIANCE    V_PIPE0_TX0_COMPLIANCE(1U)
12776 #define V_PIPE0_TX7_ELECIDLE(x) ((x) << S_PIPE0_TX7_ELECIDLE)
12777 #define F_PIPE0_TX7_ELECIDLE    V_PIPE0_TX7_ELECIDLE(1U)
12780 #define V_PIPE0_TX6_ELECIDLE(x) ((x) << S_PIPE0_TX6_ELECIDLE)
12781 #define F_PIPE0_TX6_ELECIDLE    V_PIPE0_TX6_ELECIDLE(1U)
12784 #define V_PIPE0_TX5_ELECIDLE(x) ((x) << S_PIPE0_TX5_ELECIDLE)
12785 #define F_PIPE0_TX5_ELECIDLE    V_PIPE0_TX5_ELECIDLE(1U)
12788 #define V_PIPE0_TX4_ELECIDLE(x) ((x) << S_PIPE0_TX4_ELECIDLE)
12789 #define F_PIPE0_TX4_ELECIDLE    V_PIPE0_TX4_ELECIDLE(1U)
12792 #define V_PIPE0_TX3_ELECIDLE(x) ((x) << S_PIPE0_TX3_ELECIDLE)
12793 #define F_PIPE0_TX3_ELECIDLE    V_PIPE0_TX3_ELECIDLE(1U)
12796 #define V_PIPE0_TX2_ELECIDLE(x) ((x) << S_PIPE0_TX2_ELECIDLE)
12797 #define F_PIPE0_TX2_ELECIDLE    V_PIPE0_TX2_ELECIDLE(1U)
12800 #define V_PIPE0_TX1_ELECIDLE(x) ((x) << S_PIPE0_TX1_ELECIDLE)
12801 #define F_PIPE0_TX1_ELECIDLE    V_PIPE0_TX1_ELECIDLE(1U)
12804 #define V_PIPE0_TX0_ELECIDLE(x) ((x) << S_PIPE0_TX0_ELECIDLE)
12805 #define F_PIPE0_TX0_ELECIDLE    V_PIPE0_TX0_ELECIDLE(1U)
12808 #define V_PIPE0_RX7_POLARITY_19(x) ((x) << S_PIPE0_RX7_POLARITY_19)
12809 #define F_PIPE0_RX7_POLARITY_19    V_PIPE0_RX7_POLARITY_19(1U)
12812 #define V_PIPE0_RX6_POLARITY_19(x) ((x) << S_PIPE0_RX6_POLARITY_19)
12813 #define F_PIPE0_RX6_POLARITY_19    V_PIPE0_RX6_POLARITY_19(1U)
12816 #define V_PIPE0_RX5_POLARITY_19(x) ((x) << S_PIPE0_RX5_POLARITY_19)
12817 #define F_PIPE0_RX5_POLARITY_19    V_PIPE0_RX5_POLARITY_19(1U)
12820 #define V_PIPE0_RX4_POLARITY_19(x) ((x) << S_PIPE0_RX4_POLARITY_19)
12821 #define F_PIPE0_RX4_POLARITY_19    V_PIPE0_RX4_POLARITY_19(1U)
12824 #define V_PIPE0_RX3_POLARITY_19(x) ((x) << S_PIPE0_RX3_POLARITY_19)
12825 #define F_PIPE0_RX3_POLARITY_19    V_PIPE0_RX3_POLARITY_19(1U)
12828 #define V_PIPE0_RX2_POLARITY_19(x) ((x) << S_PIPE0_RX2_POLARITY_19)
12829 #define F_PIPE0_RX2_POLARITY_19    V_PIPE0_RX2_POLARITY_19(1U)
12832 #define V_PIPE0_RX1_POLARITY_19(x) ((x) << S_PIPE0_RX1_POLARITY_19)
12833 #define F_PIPE0_RX1_POLARITY_19    V_PIPE0_RX1_POLARITY_19(1U)
12836 #define V_PIPE0_RX0_POLARITY_19(x) ((x) << S_PIPE0_RX0_POLARITY_19)
12837 #define F_PIPE0_RX0_POLARITY_19    V_PIPE0_RX0_POLARITY_19(1U)
12840 #define V_PIPE0_RX7_ELECIDLE(x) ((x) << S_PIPE0_RX7_ELECIDLE)
12841 #define F_PIPE0_RX7_ELECIDLE    V_PIPE0_RX7_ELECIDLE(1U)
12844 #define V_PIPE0_RX6_ELECIDLE(x) ((x) << S_PIPE0_RX6_ELECIDLE)
12845 #define F_PIPE0_RX6_ELECIDLE    V_PIPE0_RX6_ELECIDLE(1U)
12848 #define V_PIPE0_RX5_ELECIDLE(x) ((x) << S_PIPE0_RX5_ELECIDLE)
12849 #define F_PIPE0_RX5_ELECIDLE    V_PIPE0_RX5_ELECIDLE(1U)
12852 #define V_PIPE0_RX4_ELECIDLE(x) ((x) << S_PIPE0_RX4_ELECIDLE)
12853 #define F_PIPE0_RX4_ELECIDLE    V_PIPE0_RX4_ELECIDLE(1U)
12856 #define V_PIPE0_RX3_ELECIDLE(x) ((x) << S_PIPE0_RX3_ELECIDLE)
12857 #define F_PIPE0_RX3_ELECIDLE    V_PIPE0_RX3_ELECIDLE(1U)
12860 #define V_PIPE0_RX2_ELECIDLE(x) ((x) << S_PIPE0_RX2_ELECIDLE)
12861 #define F_PIPE0_RX2_ELECIDLE    V_PIPE0_RX2_ELECIDLE(1U)
12863 #define S_PIPE0_RX1_ELECIDLE    1
12864 #define V_PIPE0_RX1_ELECIDLE(x) ((x) << S_PIPE0_RX1_ELECIDLE)
12865 #define F_PIPE0_RX1_ELECIDLE    V_PIPE0_RX1_ELECIDLE(1U)
12868 #define V_PIPE0_RX0_ELECIDLE(x) ((x) << S_PIPE0_RX0_ELECIDLE)
12869 #define F_PIPE0_RX0_ELECIDLE    V_PIPE0_RX0_ELECIDLE(1U)
12874 #define V_PIPE0_RESET_N(x) ((x) << S_PIPE0_RESET_N)
12875 #define F_PIPE0_RESET_N    V_PIPE0_RESET_N(1U)
12878 #define V_PCS_COMMON_CLOCKS(x) ((x) << S_PCS_COMMON_CLOCKS)
12879 #define F_PCS_COMMON_CLOCKS    V_PCS_COMMON_CLOCKS(1U)
12882 #define V_PCS_CLK_REQ(x) ((x) << S_PCS_CLK_REQ)
12883 #define F_PCS_CLK_REQ    V_PCS_CLK_REQ(1U)
12886 #define V_PIPE_CLKREQ_N(x) ((x) << S_PIPE_CLKREQ_N)
12887 #define F_PIPE_CLKREQ_N    V_PIPE_CLKREQ_N(1U)
12890 #define V_MAC_CLKREQ_N_TO_MUX(x) ((x) << S_MAC_CLKREQ_N_TO_MUX)
12891 #define F_MAC_CLKREQ_N_TO_MUX    V_MAC_CLKREQ_N_TO_MUX(1U)
12894 #define V_PIPE0_TX2RX_LOOPBK(x) ((x) << S_PIPE0_TX2RX_LOOPBK)
12895 #define F_PIPE0_TX2RX_LOOPBK    V_PIPE0_TX2RX_LOOPBK(1U)
12898 #define V_PIPE0_TX_SWING(x) ((x) << S_PIPE0_TX_SWING)
12899 #define F_PIPE0_TX_SWING    V_PIPE0_TX_SWING(1U)
12903 #define V_PIPE0_TX_MARGIN(x) ((x) << S_PIPE0_TX_MARGIN)
12904 #define G_PIPE0_TX_MARGIN(x) (((x) >> S_PIPE0_TX_MARGIN) & M_PIPE0_TX_MARGIN)
12907 #define V_PIPE0_TX_DEEMPH(x) ((x) << S_PIPE0_TX_DEEMPH)
12908 #define F_PIPE0_TX_DEEMPH    V_PIPE0_TX_DEEMPH(1U)
12911 #define V_PIPE0_TX_DETECTRX(x) ((x) << S_PIPE0_TX_DETECTRX)
12912 #define F_PIPE0_TX_DETECTRX    V_PIPE0_TX_DETECTRX(1U)
12916 #define V_PIPE0_POWERDOWN(x) ((x) << S_PIPE0_POWERDOWN)
12917 #define G_PIPE0_POWERDOWN(x) (((x) >> S_PIPE0_POWERDOWN) & M_PIPE0_POWERDOWN)
12921 #define V_PHY_MAC_PHYSTATUS(x) ((x) << S_PHY_MAC_PHYSTATUS)
12922 #define G_PHY_MAC_PHYSTATUS(x) (((x) >> S_PHY_MAC_PHYSTATUS) & M_PHY_MAC_PHYSTATUS)
12927 #define V_PIPE0_RX7_EQ_IN_PROG(x) ((x) << S_PIPE0_RX7_EQ_IN_PROG)
12928 #define F_PIPE0_RX7_EQ_IN_PROG    V_PIPE0_RX7_EQ_IN_PROG(1U)
12931 #define V_PIPE0_RX7_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX7_EQ_INVLD_REQ)
12932 #define F_PIPE0_RX7_EQ_INVLD_REQ    V_PIPE0_RX7_EQ_INVLD_REQ(1U)
12936 #define V_PIPE0_RX7_SYNCHEADER(x) ((x) << S_PIPE0_RX7_SYNCHEADER)
12937 #define G_PIPE0_RX7_SYNCHEADER(x) (((x) >> S_PIPE0_RX7_SYNCHEADER) & M_PIPE0_RX7_SYNCHEADER)
12940 #define V_PIPE0_RX6_EQ_IN_PROG(x) ((x) << S_PIPE0_RX6_EQ_IN_PROG)
12941 #define F_PIPE0_RX6_EQ_IN_PROG    V_PIPE0_RX6_EQ_IN_PROG(1U)
12944 #define V_PIPE0_RX6_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX6_EQ_INVLD_REQ)
12945 #define F_PIPE0_RX6_EQ_INVLD_REQ    V_PIPE0_RX6_EQ_INVLD_REQ(1U)
12949 #define V_PIPE0_RX6_SYNCHEADER(x) ((x) << S_PIPE0_RX6_SYNCHEADER)
12950 #define G_PIPE0_RX6_SYNCHEADER(x) (((x) >> S_PIPE0_RX6_SYNCHEADER) & M_PIPE0_RX6_SYNCHEADER)
12953 #define V_PIPE0_RX5_EQ_IN_PROG(x) ((x) << S_PIPE0_RX5_EQ_IN_PROG)
12954 #define F_PIPE0_RX5_EQ_IN_PROG    V_PIPE0_RX5_EQ_IN_PROG(1U)
12957 #define V_PIPE0_RX5_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX5_EQ_INVLD_REQ)
12958 #define F_PIPE0_RX5_EQ_INVLD_REQ    V_PIPE0_RX5_EQ_INVLD_REQ(1U)
12962 #define V_PIPE0_RX5_SYNCHEADER(x) ((x) << S_PIPE0_RX5_SYNCHEADER)
12963 #define G_PIPE0_RX5_SYNCHEADER(x) (((x) >> S_PIPE0_RX5_SYNCHEADER) & M_PIPE0_RX5_SYNCHEADER)
12966 #define V_PIPE0_RX4_EQ_IN_PROG(x) ((x) << S_PIPE0_RX4_EQ_IN_PROG)
12967 #define F_PIPE0_RX4_EQ_IN_PROG    V_PIPE0_RX4_EQ_IN_PROG(1U)
12970 #define V_PIPE0_RX4_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX4_EQ_INVLD_REQ)
12971 #define F_PIPE0_RX4_EQ_INVLD_REQ    V_PIPE0_RX4_EQ_INVLD_REQ(1U)
12975 #define V_PIPE0_RX4_SYNCHEADER(x) ((x) << S_PIPE0_RX4_SYNCHEADER)
12976 #define G_PIPE0_RX4_SYNCHEADER(x) (((x) >> S_PIPE0_RX4_SYNCHEADER) & M_PIPE0_RX4_SYNCHEADER)
12979 #define V_PIPE0_RX3_EQ_IN_PROG(x) ((x) << S_PIPE0_RX3_EQ_IN_PROG)
12980 #define F_PIPE0_RX3_EQ_IN_PROG    V_PIPE0_RX3_EQ_IN_PROG(1U)
12983 #define V_PIPE0_RX3_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX3_EQ_INVLD_REQ)
12984 #define F_PIPE0_RX3_EQ_INVLD_REQ    V_PIPE0_RX3_EQ_INVLD_REQ(1U)
12988 #define V_PIPE0_RX3_SYNCHEADER(x) ((x) << S_PIPE0_RX3_SYNCHEADER)
12989 #define G_PIPE0_RX3_SYNCHEADER(x) (((x) >> S_PIPE0_RX3_SYNCHEADER) & M_PIPE0_RX3_SYNCHEADER)
12992 #define V_PIPE0_RX2_EQ_IN_PROG(x) ((x) << S_PIPE0_RX2_EQ_IN_PROG)
12993 #define F_PIPE0_RX2_EQ_IN_PROG    V_PIPE0_RX2_EQ_IN_PROG(1U)
12996 #define V_PIPE0_RX2_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX2_EQ_INVLD_REQ)
12997 #define F_PIPE0_RX2_EQ_INVLD_REQ    V_PIPE0_RX2_EQ_INVLD_REQ(1U)
13001 #define V_PIPE0_RX2_SYNCHEADER(x) ((x) << S_PIPE0_RX2_SYNCHEADER)
13002 #define G_PIPE0_RX2_SYNCHEADER(x) (((x) >> S_PIPE0_RX2_SYNCHEADER) & M_PIPE0_RX2_SYNCHEADER)
13005 #define V_PIPE0_RX1_EQ_IN_PROG(x) ((x) << S_PIPE0_RX1_EQ_IN_PROG)
13006 #define F_PIPE0_RX1_EQ_IN_PROG    V_PIPE0_RX1_EQ_IN_PROG(1U)
13009 #define V_PIPE0_RX1_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX1_EQ_INVLD_REQ)
13010 #define F_PIPE0_RX1_EQ_INVLD_REQ    V_PIPE0_RX1_EQ_INVLD_REQ(1U)
13014 #define V_PIPE0_RX1_SYNCHEADER(x) ((x) << S_PIPE0_RX1_SYNCHEADER)
13015 #define G_PIPE0_RX1_SYNCHEADER(x) (((x) >> S_PIPE0_RX1_SYNCHEADER) & M_PIPE0_RX1_SYNCHEADER)
13018 #define V_PIPE0_RX0_EQ_IN_PROG(x) ((x) << S_PIPE0_RX0_EQ_IN_PROG)
13019 #define F_PIPE0_RX0_EQ_IN_PROG    V_PIPE0_RX0_EQ_IN_PROG(1U)
13022 #define V_PIPE0_RX0_EQ_INVLD_REQ(x) ((x) << S_PIPE0_RX0_EQ_INVLD_REQ)
13023 #define F_PIPE0_RX0_EQ_INVLD_REQ    V_PIPE0_RX0_EQ_INVLD_REQ(1U)
13027 #define V_PIPE0_RX0_SYNCHEADER(x) ((x) << S_PIPE0_RX0_SYNCHEADER)
13028 #define G_PIPE0_RX0_SYNCHEADER(x) (((x) >> S_PIPE0_RX0_SYNCHEADER) & M_PIPE0_RX0_SYNCHEADER)
13034 #define V_SI_REQVFID(x) ((x) << S_SI_REQVFID)
13035 #define G_SI_REQVFID(x) (((x) >> S_SI_REQVFID) & M_SI_REQVFID)
13039 #define V_SI_REQVEC(x) ((x) << S_SI_REQVEC)
13040 #define G_SI_REQVEC(x) (((x) >> S_SI_REQVEC) & M_SI_REQVEC)
13044 #define V_SI_REQTCVAL(x) ((x) << S_SI_REQTCVAL)
13045 #define G_SI_REQTCVAL(x) (((x) >> S_SI_REQTCVAL) & M_SI_REQTCVAL)
13048 #define V_SI_REQRDY(x) ((x) << S_SI_REQRDY)
13049 #define F_SI_REQRDY    V_SI_REQRDY(1U)
13052 #define V_SI_REQVLD(x) ((x) << S_SI_REQVLD)
13053 #define F_SI_REQVLD    V_SI_REQVLD(1U)
13057 #define V_T5_AI(x) ((x) << S_T5_AI)
13058 #define G_T5_AI(x) (((x) >> S_T5_AI) & M_T5_AI)
13063 #define V_GNTSI(x) ((x) << S_GNTSI)
13064 #define F_GNTSI    V_GNTSI(1U)
13067 #define V_DROPINTFORFLR(x) ((x) << S_DROPINTFORFLR)
13068 #define F_DROPINTFORFLR    V_DROPINTFORFLR(1U)
13072 #define V_SMARB(x) ((x) << S_SMARB)
13073 #define G_SMARB(x) (((x) >> S_SMARB) & M_SMARB)
13077 #define V_SMDEFR(x) ((x) << S_SMDEFR)
13078 #define G_SMDEFR(x) (((x) >> S_SMDEFR) & M_SMDEFR)
13082 #define V_SYS_INT(x) ((x) << S_SYS_INT)
13083 #define G_SYS_INT(x) (((x) >> S_SYS_INT) & M_SYS_INT)
13087 #define V_CFG_INTXCLR(x) ((x) << S_CFG_INTXCLR)
13088 #define G_CFG_INTXCLR(x) (((x) >> S_CFG_INTXCLR) & M_CFG_INTXCLR)
13092 #define V_PIO_INTXCLR(x) ((x) << S_PIO_INTXCLR)
13093 #define G_PIO_INTXCLR(x) (((x) >> S_PIO_INTXCLR) & M_PIO_INTXCLR)
13098 #define V_PLI_TABDATWREN(x) ((x) << S_PLI_TABDATWREN)
13099 #define F_PLI_TABDATWREN    V_PLI_TABDATWREN(1U)
13102 #define V_TAB_RDENA(x) ((x) << S_TAB_RDENA)
13103 #define F_TAB_RDENA    V_TAB_RDENA(1U)
13107 #define V_TAB_RDENA2(x) ((x) << S_TAB_RDENA2)
13108 #define G_TAB_RDENA2(x) (((x) >> S_TAB_RDENA2) & M_TAB_RDENA2)
13112 #define V_PLI_REQADDR(x) ((x) << S_PLI_REQADDR)
13113 #define G_PLI_REQADDR(x) (((x) >> S_PLI_REQADDR) & M_PLI_REQADDR)
13117 #define V_PLI_REQVFID(x) ((x) << S_PLI_REQVFID)
13118 #define G_PLI_REQVFID(x) (((x) >> S_PLI_REQVFID) & M_PLI_REQVFID)
13120 #define S_PLI_REQTABHIT    1
13121 #define V_PLI_REQTABHIT(x) ((x) << S_PLI_REQTABHIT)
13122 #define F_PLI_REQTABHIT    V_PLI_REQTABHIT(1U)
13125 #define V_PLI_REQRDVLD(x) ((x) << S_PLI_REQRDVLD)
13126 #define F_PLI_REQRDVLD    V_PLI_REQRDVLD(1U)
13134 #define V_PLI_REQPBASTART(x) ((x) << S_PLI_REQPBASTART)
13135 #define G_PLI_REQPBASTART(x) (((x) >> S_PLI_REQPBASTART) & M_PLI_REQPBASTART)
13139 #define V_PLI_REQPBAEND(x) ((x) << S_PLI_REQPBAEND)
13140 #define G_PLI_REQPBAEND(x) (((x) >> S_PLI_REQPBAEND) & M_PLI_REQPBAEND)
13144 #define V_T5_PLI_REQVFID(x) ((x) << S_T5_PLI_REQVFID)
13145 #define G_T5_PLI_REQVFID(x) (((x) >> S_T5_PLI_REQVFID) & M_T5_PLI_REQVFID)
13147 #define S_PLI_REQPBAHIT    1
13148 #define V_PLI_REQPBAHIT(x) ((x) << S_PLI_REQPBAHIT)
13149 #define F_PLI_REQPBAHIT    V_PLI_REQPBAHIT(1U)
13154 #define V_GNTSI1(x) ((x) << S_GNTSI1)
13155 #define F_GNTSI1    V_GNTSI1(1U)
13158 #define V_GNTSI2(x) ((x) << S_GNTSI2)
13159 #define F_GNTSI2    V_GNTSI2(1U)
13163 #define V_GNTSI3(x) ((x) << S_GNTSI3)
13164 #define G_GNTSI3(x) (((x) >> S_GNTSI3) & M_GNTSI3)
13168 #define V_GNTSI4(x) ((x) << S_GNTSI4)
13169 #define G_GNTSI4(x) (((x) >> S_GNTSI4) & M_GNTSI4)
13173 #define V_GNTSI5(x) ((x) << S_GNTSI5)
13174 #define G_GNTSI5(x) (((x) >> S_GNTSI5) & M_GNTSI5)
13177 #define V_GNTSI6(x) ((x) << S_GNTSI6)
13178 #define F_GNTSI6    V_GNTSI6(1U)
13181 #define V_GNTSI7(x) ((x) << S_GNTSI7)
13182 #define F_GNTSI7    V_GNTSI7(1U)
13185 #define V_GNTSI8(x) ((x) << S_GNTSI8)
13186 #define F_GNTSI8    V_GNTSI8(1U)
13189 #define V_GNTSI9(x) ((x) << S_GNTSI9)
13190 #define F_GNTSI9    V_GNTSI9(1U)
13193 #define V_GNTSIA(x) ((x) << S_GNTSIA)
13194 #define F_GNTSIA    V_GNTSIA(1U)
13197 #define V_GNTAI(x) ((x) << S_GNTAI)
13198 #define F_GNTAI    V_GNTAI(1U)
13200 #define S_GNTDB    1
13201 #define V_GNTDB(x) ((x) << S_GNTDB)
13202 #define F_GNTDB    V_GNTDB(1U)
13205 #define V_GNTDI(x) ((x) << S_GNTDI)
13206 #define F_GNTDI    V_GNTDI(1U)
13211 #define V_DI_REQVLD(x) ((x) << S_DI_REQVLD)
13212 #define F_DI_REQVLD    V_DI_REQVLD(1U)
13215 #define V_DI_REQRDY(x) ((x) << S_DI_REQRDY)
13216 #define F_DI_REQRDY    V_DI_REQRDY(1U)
13220 #define V_DI_REQWREN(x) ((x) << S_DI_REQWREN)
13221 #define G_DI_REQWREN(x) (((x) >> S_DI_REQWREN) & M_DI_REQWREN)
13224 #define V_DI_REQMSIEN(x) ((x) << S_DI_REQMSIEN)
13225 #define F_DI_REQMSIEN    V_DI_REQMSIEN(1U)
13228 #define V_DI_REQMSXEN(x) ((x) << S_DI_REQMSXEN)
13229 #define F_DI_REQMSXEN    V_DI_REQMSXEN(1U)
13232 #define V_DI_REQMSXVFIDMSK(x) ((x) << S_DI_REQMSXVFIDMSK)
13233 #define F_DI_REQMSXVFIDMSK    V_DI_REQMSXVFIDMSK(1U)
13237 #define V_DI_REQWREN2(x) ((x) << S_DI_REQWREN2)
13238 #define G_DI_REQWREN2(x) (((x) >> S_DI_REQWREN2) & M_DI_REQWREN2)
13240 #define S_DI_REQRDEN    1
13241 #define V_DI_REQRDEN(x) ((x) << S_DI_REQRDEN)
13242 #define F_DI_REQRDEN    V_DI_REQRDEN(1U)
13245 #define V_DI_REQWREN3(x) ((x) << S_DI_REQWREN3)
13246 #define F_DI_REQWREN3    V_DI_REQWREN3(1U)
13254 #define V_FID_STI_RSPVLD(x) ((x) << S_FID_STI_RSPVLD)
13255 #define F_FID_STI_RSPVLD    V_FID_STI_RSPVLD(1U)
13258 #define V_TAB_STIRDENA(x) ((x) << S_TAB_STIRDENA)
13259 #define F_TAB_STIRDENA    V_TAB_STIRDENA(1U)
13262 #define V_TAB_STIWRENA(x) ((x) << S_TAB_STIWRENA)
13263 #define F_TAB_STIWRENA    V_TAB_STIWRENA(1U)
13267 #define V_TAB_STIRDENA2(x) ((x) << S_TAB_STIRDENA2)
13268 #define G_TAB_STIRDENA2(x) (((x) >> S_TAB_STIRDENA2) & M_TAB_STIRDENA2)
13272 #define V_T5_PLI_REQTABHIT(x) ((x) << S_T5_PLI_REQTABHIT)
13273 #define G_T5_PLI_REQTABHIT(x) (((x) >> S_T5_PLI_REQTABHIT) & M_T5_PLI_REQTABHIT)
13277 #define V_T5_GNTSI(x) ((x) << S_T5_GNTSI)
13278 #define G_T5_GNTSI(x) (((x) >> S_T5_GNTSI) & M_T5_GNTSI)
13283 #define V_PLI_REQWRVLD(x) ((x) << S_PLI_REQWRVLD)
13284 #define F_PLI_REQWRVLD    V_PLI_REQWRVLD(1U)
13287 #define V_T5_PLI_REQPBAHIT(x) ((x) << S_T5_PLI_REQPBAHIT)
13288 #define F_T5_PLI_REQPBAHIT    V_T5_PLI_REQPBAHIT(1U)
13291 #define V_PLI_TABADDRLWREN(x) ((x) << S_PLI_TABADDRLWREN)
13292 #define F_PLI_TABADDRLWREN    V_PLI_TABADDRLWREN(1U)
13295 #define V_PLI_TABADDRHWREN(x) ((x) << S_PLI_TABADDRHWREN)
13296 #define F_PLI_TABADDRHWREN    V_PLI_TABADDRHWREN(1U)
13299 #define V_T5_PLI_TABDATWREN(x) ((x) << S_T5_PLI_TABDATWREN)
13300 #define F_T5_PLI_TABDATWREN    V_T5_PLI_TABDATWREN(1U)
13303 #define V_PLI_TABMSKWREN(x) ((x) << S_PLI_TABMSKWREN)
13304 #define F_PLI_TABMSKWREN    V_PLI_TABMSKWREN(1U)
13308 #define V_AI_REQVLD(x) ((x) << S_AI_REQVLD)
13309 #define G_AI_REQVLD(x) (((x) >> S_AI_REQVLD) & M_AI_REQVLD)
13312 #define V_AI_REQVLD2(x) ((x) << S_AI_REQVLD2)
13313 #define F_AI_REQVLD2    V_AI_REQVLD2(1U)
13316 #define V_AI_REQRDY(x) ((x) << S_AI_REQRDY)
13317 #define F_AI_REQRDY    V_AI_REQRDY(1U)
13321 #define V_VEN_MSI_REQ_28(x) ((x) << S_VEN_MSI_REQ_28)
13322 #define G_VEN_MSI_REQ_28(x) (((x) >> S_VEN_MSI_REQ_28) & M_VEN_MSI_REQ_28)
13326 #define V_VEN_MSI_REQ2(x) ((x) << S_VEN_MSI_REQ2)
13327 #define G_VEN_MSI_REQ2(x) (((x) >> S_VEN_MSI_REQ2) & M_VEN_MSI_REQ2)
13331 #define V_VEN_MSI_REQ3(x) ((x) << S_VEN_MSI_REQ3)
13332 #define G_VEN_MSI_REQ3(x) (((x) >> S_VEN_MSI_REQ3) & M_VEN_MSI_REQ3)
13336 #define V_VEN_MSI_REQ4(x) ((x) << S_VEN_MSI_REQ4)
13337 #define G_VEN_MSI_REQ4(x) (((x) >> S_VEN_MSI_REQ4) & M_VEN_MSI_REQ4)
13340 #define V_VEN_MSI_REQ5(x) ((x) << S_VEN_MSI_REQ5)
13341 #define F_VEN_MSI_REQ5    V_VEN_MSI_REQ5(1U)
13343 #define S_VEN_MSI_GRANT    1
13344 #define V_VEN_MSI_GRANT(x) ((x) << S_VEN_MSI_GRANT)
13345 #define F_VEN_MSI_GRANT    V_VEN_MSI_GRANT(1U)
13348 #define V_VEN_MSI_REQ6(x) ((x) << S_VEN_MSI_REQ6)
13349 #define F_VEN_MSI_REQ6    V_VEN_MSI_REQ6(1U)
13355 #define V_TRGT1_REQDATAVLD(x) ((x) << S_TRGT1_REQDATAVLD)
13356 #define G_TRGT1_REQDATAVLD(x) (((x) >> S_TRGT1_REQDATAVLD) & M_TRGT1_REQDATAVLD)
13360 #define V_TRGT1_REQDATAVLD2(x) ((x) << S_TRGT1_REQDATAVLD2)
13361 #define G_TRGT1_REQDATAVLD2(x) (((x) >> S_TRGT1_REQDATAVLD2) & M_TRGT1_REQDATAVLD2)
13364 #define V_TRGT1_REQDATAVLD3(x) ((x) << S_TRGT1_REQDATAVLD3)
13365 #define F_TRGT1_REQDATAVLD3    V_TRGT1_REQDATAVLD3(1U)
13368 #define V_TRGT1_REQDATAVLD4(x) ((x) << S_TRGT1_REQDATAVLD4)
13369 #define F_TRGT1_REQDATAVLD4    V_TRGT1_REQDATAVLD4(1U)
13372 #define V_TRGT1_REQDATAVLD5(x) ((x) << S_TRGT1_REQDATAVLD5)
13373 #define F_TRGT1_REQDATAVLD5    V_TRGT1_REQDATAVLD5(1U)
13376 #define V_TRGT1_REQDATAVLD6(x) ((x) << S_TRGT1_REQDATAVLD6)
13377 #define F_TRGT1_REQDATAVLD6    V_TRGT1_REQDATAVLD6(1U)
13381 #define V_TRGT1_REQDATAVLD7(x) ((x) << S_TRGT1_REQDATAVLD7)
13382 #define G_TRGT1_REQDATAVLD7(x) (((x) >> S_TRGT1_REQDATAVLD7) & M_TRGT1_REQDATAVLD7)
13386 #define V_TRGT1_REQDATAVLD8(x) ((x) << S_TRGT1_REQDATAVLD8)
13387 #define G_TRGT1_REQDATAVLD8(x) (((x) >> S_TRGT1_REQDATAVLD8) & M_TRGT1_REQDATAVLD8)
13389 #define S_TRGT1_REQDATARDY    1
13390 #define V_TRGT1_REQDATARDY(x) ((x) << S_TRGT1_REQDATARDY)
13391 #define F_TRGT1_REQDATARDY    V_TRGT1_REQDATARDY(1U)
13394 #define V_TRGT1_REQDATAVLD0(x) ((x) << S_TRGT1_REQDATAVLD0)
13395 #define F_TRGT1_REQDATAVLD0    V_TRGT1_REQDATAVLD0(1U)
13402 #define V_RADM_TRGT1_ADDR(x) ((x) << S_RADM_TRGT1_ADDR)
13403 #define G_RADM_TRGT1_ADDR(x) (((x) >> S_RADM_TRGT1_ADDR) & M_RADM_TRGT1_ADDR)
13407 #define V_RADM_TRGT1_DWEN(x) ((x) << S_RADM_TRGT1_DWEN)
13408 #define G_RADM_TRGT1_DWEN(x) (((x) >> S_RADM_TRGT1_DWEN) & M_RADM_TRGT1_DWEN)
13412 #define V_RADM_TRGT1_FMT(x) ((x) << S_RADM_TRGT1_FMT)
13413 #define G_RADM_TRGT1_FMT(x) (((x) >> S_RADM_TRGT1_FMT) & M_RADM_TRGT1_FMT)
13417 #define V_RADM_TRGT1_TYPE(x) ((x) << S_RADM_TRGT1_TYPE)
13418 #define G_RADM_TRGT1_TYPE(x) (((x) >> S_RADM_TRGT1_TYPE) & M_RADM_TRGT1_TYPE)
13422 #define V_RADM_TRGT1_IN_MEMBAR_RANGE(x) ((x) << S_RADM_TRGT1_IN_MEMBAR_RANGE)
13423 #define G_RADM_TRGT1_IN_MEMBAR_RANGE(x) (((x) >> S_RADM_TRGT1_IN_MEMBAR_RANGE) & M_RADM_TRGT1_IN_MEMBAR_RANGE)
13426 #define V_RADM_TRGT1_ECRC_ERR(x) ((x) << S_RADM_TRGT1_ECRC_ERR)
13427 #define F_RADM_TRGT1_ECRC_ERR    V_RADM_TRGT1_ECRC_ERR(1U)
13430 #define V_RADM_TRGT1_DLLP_ABORT(x) ((x) << S_RADM_TRGT1_DLLP_ABORT)
13431 #define F_RADM_TRGT1_DLLP_ABORT    V_RADM_TRGT1_DLLP_ABORT(1U)
13434 #define V_RADM_TRGT1_TLP_ABORT(x) ((x) << S_RADM_TRGT1_TLP_ABORT)
13435 #define F_RADM_TRGT1_TLP_ABORT    V_RADM_TRGT1_TLP_ABORT(1U)
13438 #define V_RADM_TRGT1_EOT(x) ((x) << S_RADM_TRGT1_EOT)
13439 #define F_RADM_TRGT1_EOT    V_RADM_TRGT1_EOT(1U)
13441 #define S_RADM_TRGT1_DV_2B    1
13442 #define V_RADM_TRGT1_DV_2B(x) ((x) << S_RADM_TRGT1_DV_2B)
13443 #define F_RADM_TRGT1_DV_2B    V_RADM_TRGT1_DV_2B(1U)
13446 #define V_RADM_TRGT1_HV_2B(x) ((x) << S_RADM_TRGT1_HV_2B)
13447 #define F_RADM_TRGT1_HV_2B    V_RADM_TRGT1_HV_2B(1U)
13453 #define V_STATEMPIO(x) ((x) << S_STATEMPIO)
13454 #define G_STATEMPIO(x) (((x) >> S_STATEMPIO) & M_STATEMPIO)
13458 #define V_STATECPL(x) ((x) << S_STATECPL)
13459 #define G_STATECPL(x) (((x) >> S_STATECPL) & M_STATECPL)
13463 #define V_STATEALIN(x) ((x) << S_STATEALIN)
13464 #define G_STATEALIN(x) (((x) >> S_STATEALIN) & M_STATEALIN)
13468 #define V_STATEPL(x) ((x) << S_STATEPL)
13469 #define G_STATEPL(x) (((x) >> S_STATEPL) & M_STATEPL)
13472 #define V_STATEMARSP(x) ((x) << S_STATEMARSP)
13473 #define F_STATEMARSP    V_STATEMARSP(1U)
13477 #define V_MA_TAGSINUSE(x) ((x) << S_MA_TAGSINUSE)
13478 #define G_MA_TAGSINUSE(x) (((x) >> S_MA_TAGSINUSE) & M_MA_TAGSINUSE)
13481 #define V_RADM_TRGT1_HSRDY(x) ((x) << S_RADM_TRGT1_HSRDY)
13482 #define F_RADM_TRGT1_HSRDY    V_RADM_TRGT1_HSRDY(1U)
13485 #define V_RADM_TRGT1_DSRDY(x) ((x) << S_RADM_TRGT1_DSRDY)
13486 #define F_RADM_TRGT1_DSRDY    V_RADM_TRGT1_DSRDY(1U)
13489 #define V_ALIND_REQWRDATAVLD(x) ((x) << S_ALIND_REQWRDATAVLD)
13490 #define F_ALIND_REQWRDATAVLD    V_ALIND_REQWRDATAVLD(1U)
13493 #define V_FID_LKUPWRHDRVLD(x) ((x) << S_FID_LKUPWRHDRVLD)
13494 #define F_FID_LKUPWRHDRVLD    V_FID_LKUPWRHDRVLD(1U)
13497 #define V_MPIO_WRVLD(x) ((x) << S_MPIO_WRVLD)
13498 #define F_MPIO_WRVLD    V_MPIO_WRVLD(1U)
13501 #define V_TRGT1_RADM_HALT(x) ((x) << S_TRGT1_RADM_HALT)
13502 #define F_TRGT1_RADM_HALT    V_TRGT1_RADM_HALT(1U)
13505 #define V_RADM_TRGT1_DV_2C(x) ((x) << S_RADM_TRGT1_DV_2C)
13506 #define F_RADM_TRGT1_DV_2C    V_RADM_TRGT1_DV_2C(1U)
13509 #define V_RADM_TRGT1_DV_2C_2(x) ((x) << S_RADM_TRGT1_DV_2C_2)
13510 #define F_RADM_TRGT1_DV_2C_2    V_RADM_TRGT1_DV_2C_2(1U)
13513 #define V_RADM_TRGT1_TLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_TLP_ABORT_2C)
13514 #define F_RADM_TRGT1_TLP_ABORT_2C    V_RADM_TRGT1_TLP_ABORT_2C(1U)
13516 #define S_RADM_TRGT1_DLLP_ABORT_2C    1
13517 #define V_RADM_TRGT1_DLLP_ABORT_2C(x) ((x) << S_RADM_TRGT1_DLLP_ABORT_2C)
13518 #define F_RADM_TRGT1_DLLP_ABORT_2C    V_RADM_TRGT1_DLLP_ABORT_2C(1U)
13521 #define V_RADM_TRGT1_ECRC_ERR_2C(x) ((x) << S_RADM_TRGT1_ECRC_ERR_2C)
13522 #define F_RADM_TRGT1_ECRC_ERR_2C    V_RADM_TRGT1_ECRC_ERR_2C(1U)
13527 #define V_RADM_TRGT1_HV_2D(x) ((x) << S_RADM_TRGT1_HV_2D)
13528 #define F_RADM_TRGT1_HV_2D    V_RADM_TRGT1_HV_2D(1U)
13531 #define V_RADM_TRGT1_DV_2D(x) ((x) << S_RADM_TRGT1_DV_2D)
13532 #define F_RADM_TRGT1_DV_2D    V_RADM_TRGT1_DV_2D(1U)
13536 #define V_RADM_TRGT1_HV2(x) ((x) << S_RADM_TRGT1_HV2)
13537 #define G_RADM_TRGT1_HV2(x) (((x) >> S_RADM_TRGT1_HV2) & M_RADM_TRGT1_HV2)
13541 #define V_RADM_TRGT1_HV3(x) ((x) << S_RADM_TRGT1_HV3)
13542 #define G_RADM_TRGT1_HV3(x) (((x) >> S_RADM_TRGT1_HV3) & M_RADM_TRGT1_HV3)
13546 #define V_RADM_TRGT1_HV4(x) ((x) << S_RADM_TRGT1_HV4)
13547 #define G_RADM_TRGT1_HV4(x) (((x) >> S_RADM_TRGT1_HV4) & M_RADM_TRGT1_HV4)
13551 #define V_RADM_TRGT1_HV5(x) ((x) << S_RADM_TRGT1_HV5)
13552 #define G_RADM_TRGT1_HV5(x) (((x) >> S_RADM_TRGT1_HV5) & M_RADM_TRGT1_HV5)
13555 #define V_RADM_TRGT1_HV6(x) ((x) << S_RADM_TRGT1_HV6)
13556 #define F_RADM_TRGT1_HV6    V_RADM_TRGT1_HV6(1U)
13559 #define V_RADM_TRGT1_HV7(x) ((x) << S_RADM_TRGT1_HV7)
13560 #define F_RADM_TRGT1_HV7    V_RADM_TRGT1_HV7(1U)
13564 #define V_RADM_TRGT1_HV8(x) ((x) << S_RADM_TRGT1_HV8)
13565 #define G_RADM_TRGT1_HV8(x) (((x) >> S_RADM_TRGT1_HV8) & M_RADM_TRGT1_HV8)
13568 #define V_RADM_TRGT1_HV9(x) ((x) << S_RADM_TRGT1_HV9)
13569 #define F_RADM_TRGT1_HV9    V_RADM_TRGT1_HV9(1U)
13572 #define V_RADM_TRGT1_HVA(x) ((x) << S_RADM_TRGT1_HVA)
13573 #define F_RADM_TRGT1_HVA    V_RADM_TRGT1_HVA(1U)
13576 #define V_RADM_TRGT1_DSRDY_2D(x) ((x) << S_RADM_TRGT1_DSRDY_2D)
13577 #define F_RADM_TRGT1_DSRDY_2D    V_RADM_TRGT1_DSRDY_2D(1U)
13581 #define V_RADM_TRGT1_WRCNT(x) ((x) << S_RADM_TRGT1_WRCNT)
13582 #define G_RADM_TRGT1_WRCNT(x) (((x) >> S_RADM_TRGT1_WRCNT) & M_RADM_TRGT1_WRCNT)
13588 #define V_RADM_TRGT1_HV_2E(x) ((x) << S_RADM_TRGT1_HV_2E)
13589 #define G_RADM_TRGT1_HV_2E(x) (((x) >> S_RADM_TRGT1_HV_2E) & M_RADM_TRGT1_HV_2E)
13593 #define V_RADM_TRGT1_HV_2E_2(x) ((x) << S_RADM_TRGT1_HV_2E_2)
13594 #define G_RADM_TRGT1_HV_2E_2(x) (((x) >> S_RADM_TRGT1_HV_2E_2) & M_RADM_TRGT1_HV_2E_2)
13598 #define V_RADM_TRGT1_HV_WE_3(x) ((x) << S_RADM_TRGT1_HV_WE_3)
13599 #define G_RADM_TRGT1_HV_WE_3(x) (((x) >> S_RADM_TRGT1_HV_WE_3) & M_RADM_TRGT1_HV_WE_3)
13603 #define V_ALIN_REQDATAVLD4(x) ((x) << S_ALIN_REQDATAVLD4)
13604 #define G_ALIN_REQDATAVLD4(x) (((x) >> S_ALIN_REQDATAVLD4) & M_ALIN_REQDATAVLD4)
13607 #define V_ALIN_REQDATAVLD5(x) ((x) << S_ALIN_REQDATAVLD5)
13608 #define F_ALIN_REQDATAVLD5    V_ALIN_REQDATAVLD5(1U)
13611 #define V_ALIN_REQDATAVLD6(x) ((x) << S_ALIN_REQDATAVLD6)
13612 #define F_ALIN_REQDATAVLD6    V_ALIN_REQDATAVLD6(1U)
13616 #define V_ALIN_REQDATAVLD7(x) ((x) << S_ALIN_REQDATAVLD7)
13617 #define G_ALIN_REQDATAVLD7(x) (((x) >> S_ALIN_REQDATAVLD7) & M_ALIN_REQDATAVLD7)
13620 #define V_ALIN_REQDATAVLD8(x) ((x) << S_ALIN_REQDATAVLD8)
13621 #define F_ALIN_REQDATAVLD8    V_ALIN_REQDATAVLD8(1U)
13624 #define V_ALIN_REQDATAVLD9(x) ((x) << S_ALIN_REQDATAVLD9)
13625 #define F_ALIN_REQDATAVLD9    V_ALIN_REQDATAVLD9(1U)
13627 #define S_ALIN_REQDATARDY    1
13628 #define V_ALIN_REQDATARDY(x) ((x) << S_ALIN_REQDATARDY)
13629 #define F_ALIN_REQDATARDY    V_ALIN_REQDATARDY(1U)
13632 #define V_ALIN_REQDATAVLDA(x) ((x) << S_ALIN_REQDATAVLDA)
13633 #define F_ALIN_REQDATAVLDA    V_ALIN_REQDATAVLDA(1U)
13640 #define V_RADM_TRGT1_HV_30(x) ((x) << S_RADM_TRGT1_HV_30)
13641 #define G_RADM_TRGT1_HV_30(x) (((x) >> S_RADM_TRGT1_HV_30) & M_RADM_TRGT1_HV_30)
13645 #define V_PIO_WRCNT(x) ((x) << S_PIO_WRCNT)
13646 #define G_PIO_WRCNT(x) (((x) >> S_PIO_WRCNT) & M_PIO_WRCNT)
13650 #define V_ALIND_REQWRCNT(x) ((x) << S_ALIND_REQWRCNT)
13651 #define G_ALIND_REQWRCNT(x) (((x) >> S_ALIND_REQWRCNT) & M_ALIND_REQWRCNT)
13655 #define V_FID_LKUPWRCNT(x) ((x) << S_FID_LKUPWRCNT)
13656 #define G_FID_LKUPWRCNT(x) (((x) >> S_FID_LKUPWRCNT) & M_FID_LKUPWRCNT)
13659 #define V_ALIND_REQRDDATAVLD(x) ((x) << S_ALIND_REQRDDATAVLD)
13660 #define F_ALIND_REQRDDATAVLD    V_ALIND_REQRDDATAVLD(1U)
13663 #define V_ALIND_REQRDDATARDY(x) ((x) << S_ALIND_REQRDDATARDY)
13664 #define F_ALIND_REQRDDATARDY    V_ALIND_REQRDDATARDY(1U)
13667 #define V_ALIND_REQRDDATAVLD2(x) ((x) << S_ALIND_REQRDDATAVLD2)
13668 #define F_ALIND_REQRDDATAVLD2    V_ALIND_REQRDDATAVLD2(1U)
13672 #define V_ALIND_REQWRDATAVLD3(x) ((x) << S_ALIND_REQWRDATAVLD3)
13673 #define G_ALIND_REQWRDATAVLD3(x) (((x) >> S_ALIND_REQWRDATAVLD3) & M_ALIND_REQWRDATAVLD3)
13676 #define V_ALIND_REQWRDATAVLD4(x) ((x) << S_ALIND_REQWRDATAVLD4)
13677 #define F_ALIND_REQWRDATAVLD4    V_ALIND_REQWRDATAVLD4(1U)
13679 #define S_ALIND_REQWRDATARDYOPEN    1
13680 #define V_ALIND_REQWRDATARDYOPEN(x) ((x) << S_ALIND_REQWRDATARDYOPEN)
13681 #define F_ALIND_REQWRDATARDYOPEN    V_ALIND_REQWRDATARDYOPEN(1U)
13684 #define V_ALIND_REQWRDATAVLD5(x) ((x) << S_ALIND_REQWRDATAVLD5)
13685 #define F_ALIND_REQWRDATAVLD5    V_ALIND_REQWRDATAVLD5(1U)
13695 #define V_T5_MPIO_WRVLD(x) ((x) << S_T5_MPIO_WRVLD)
13696 #define G_T5_MPIO_WRVLD(x) (((x) >> S_T5_MPIO_WRVLD) & M_T5_MPIO_WRVLD)
13699 #define V_FID_LKUPRDHDRVLD(x) ((x) << S_FID_LKUPRDHDRVLD)
13700 #define F_FID_LKUPRDHDRVLD    V_FID_LKUPRDHDRVLD(1U)
13703 #define V_FID_LKUPRDHDRVLD2(x) ((x) << S_FID_LKUPRDHDRVLD2)
13704 #define F_FID_LKUPRDHDRVLD2    V_FID_LKUPRDHDRVLD2(1U)
13707 #define V_FID_LKUPRDHDRVLD3(x) ((x) << S_FID_LKUPRDHDRVLD3)
13708 #define F_FID_LKUPRDHDRVLD3    V_FID_LKUPRDHDRVLD3(1U)
13711 #define V_FID_LKUPRDHDRVLD4(x) ((x) << S_FID_LKUPRDHDRVLD4)
13712 #define F_FID_LKUPRDHDRVLD4    V_FID_LKUPRDHDRVLD4(1U)
13715 #define V_FID_LKUPRDHDRVLD5(x) ((x) << S_FID_LKUPRDHDRVLD5)
13716 #define F_FID_LKUPRDHDRVLD5    V_FID_LKUPRDHDRVLD5(1U)
13719 #define V_FID_LKUPRDHDRVLD6(x) ((x) << S_FID_LKUPRDHDRVLD6)
13720 #define F_FID_LKUPRDHDRVLD6    V_FID_LKUPRDHDRVLD6(1U)
13723 #define V_FID_LKUPRDHDRVLD7(x) ((x) << S_FID_LKUPRDHDRVLD7)
13724 #define F_FID_LKUPRDHDRVLD7    V_FID_LKUPRDHDRVLD7(1U)
13727 #define V_FID_LKUPRDHDRVLD8(x) ((x) << S_FID_LKUPRDHDRVLD8)
13728 #define F_FID_LKUPRDHDRVLD8    V_FID_LKUPRDHDRVLD8(1U)
13731 #define V_FID_LKUPRDHDRVLD9(x) ((x) << S_FID_LKUPRDHDRVLD9)
13732 #define F_FID_LKUPRDHDRVLD9    V_FID_LKUPRDHDRVLD9(1U)
13735 #define V_FID_LKUPRDHDRVLDA(x) ((x) << S_FID_LKUPRDHDRVLDA)
13736 #define F_FID_LKUPRDHDRVLDA    V_FID_LKUPRDHDRVLDA(1U)
13739 #define V_FID_LKUPRDHDRVLDB(x) ((x) << S_FID_LKUPRDHDRVLDB)
13740 #define F_FID_LKUPRDHDRVLDB    V_FID_LKUPRDHDRVLDB(1U)
13743 #define V_FID_LKUPRDHDRVLDC(x) ((x) << S_FID_LKUPRDHDRVLDC)
13744 #define F_FID_LKUPRDHDRVLDC    V_FID_LKUPRDHDRVLDC(1U)
13747 #define V_MPIO_WRVLD1(x) ((x) << S_MPIO_WRVLD1)
13748 #define F_MPIO_WRVLD1    V_MPIO_WRVLD1(1U)
13751 #define V_MPIO_WRVLD2(x) ((x) << S_MPIO_WRVLD2)
13752 #define F_MPIO_WRVLD2    V_MPIO_WRVLD2(1U)
13755 #define V_MPIO_WRVLD3(x) ((x) << S_MPIO_WRVLD3)
13756 #define F_MPIO_WRVLD3    V_MPIO_WRVLD3(1U)
13760 #define V_MPIO_WRVLD4(x) ((x) << S_MPIO_WRVLD4)
13761 #define G_MPIO_WRVLD4(x) (((x) >> S_MPIO_WRVLD4) & M_MPIO_WRVLD4)
13770 #define V_CLIENT0_TLP_VFUNC_ACTIVE(x) ((x) << S_CLIENT0_TLP_VFUNC_ACTIVE)
13771 #define F_CLIENT0_TLP_VFUNC_ACTIVE    V_CLIENT0_TLP_VFUNC_ACTIVE(1U)
13775 #define V_CLIENT0_TLP_VFUNC_NUM(x) ((x) << S_CLIENT0_TLP_VFUNC_NUM)
13776 #define G_CLIENT0_TLP_VFUNC_NUM(x) (((x) >> S_CLIENT0_TLP_VFUNC_NUM) & M_CLIENT0_TLP_VFUNC_NUM)
13780 #define V_CLIENT0_TLP_FUNC_NUM(x) ((x) << S_CLIENT0_TLP_FUNC_NUM)
13781 #define G_CLIENT0_TLP_FUNC_NUM(x) (((x) >> S_CLIENT0_TLP_FUNC_NUM) & M_CLIENT0_TLP_FUNC_NUM)
13785 #define V_CLIENT0_TLP_BYTE_EN(x) ((x) << S_CLIENT0_TLP_BYTE_EN)
13786 #define G_CLIENT0_TLP_BYTE_EN(x) (((x) >> S_CLIENT0_TLP_BYTE_EN) & M_CLIENT0_TLP_BYTE_EN)
13790 #define V_CLIENT0_TLP_BYTE_LEN(x) ((x) << S_CLIENT0_TLP_BYTE_LEN)
13791 #define G_CLIENT0_TLP_BYTE_LEN(x) (((x) >> S_CLIENT0_TLP_BYTE_LEN) & M_CLIENT0_TLP_BYTE_LEN)
13796 #define V_XADM_CLIENT0_HALT(x) ((x) << S_XADM_CLIENT0_HALT)
13797 #define F_XADM_CLIENT0_HALT    V_XADM_CLIENT0_HALT(1U)
13800 #define V_CLIENT0_TLP_DV(x) ((x) << S_CLIENT0_TLP_DV)
13801 #define F_CLIENT0_TLP_DV    V_CLIENT0_TLP_DV(1U)
13804 #define V_CLIENT0_ADDR_ALIGN_EN(x) ((x) << S_CLIENT0_ADDR_ALIGN_EN)
13805 #define F_CLIENT0_ADDR_ALIGN_EN    V_CLIENT0_ADDR_ALIGN_EN(1U)
13808 #define V_CLIENT0_CPL_BCM(x) ((x) << S_CLIENT0_CPL_BCM)
13809 #define F_CLIENT0_CPL_BCM    V_CLIENT0_CPL_BCM(1U)
13812 #define V_CLIENT0_TLP_EP(x) ((x) << S_CLIENT0_TLP_EP)
13813 #define F_CLIENT0_TLP_EP    V_CLIENT0_TLP_EP(1U)
13817 #define V_CLIENT0_CPL_STATUS(x) ((x) << S_CLIENT0_CPL_STATUS)
13818 #define G_CLIENT0_CPL_STATUS(x) (((x) >> S_CLIENT0_CPL_STATUS) & M_CLIENT0_CPL_STATUS)
13821 #define V_CLIENT0_TLP_TD(x) ((x) << S_CLIENT0_TLP_TD)
13822 #define F_CLIENT0_TLP_TD    V_CLIENT0_TLP_TD(1U)
13826 #define V_CLIENT0_TLP_TYPE(x) ((x) << S_CLIENT0_TLP_TYPE)
13827 #define G_CLIENT0_TLP_TYPE(x) (((x) >> S_CLIENT0_TLP_TYPE) & M_CLIENT0_TLP_TYPE)
13831 #define V_CLIENT0_TLP_FMT(x) ((x) << S_CLIENT0_TLP_FMT)
13832 #define G_CLIENT0_TLP_FMT(x) (((x) >> S_CLIENT0_TLP_FMT) & M_CLIENT0_TLP_FMT)
13835 #define V_CLIENT0_TLP_BAD_EOT(x) ((x) << S_CLIENT0_TLP_BAD_EOT)
13836 #define F_CLIENT0_TLP_BAD_EOT    V_CLIENT0_TLP_BAD_EOT(1U)
13839 #define V_CLIENT0_TLP_EOT(x) ((x) << S_CLIENT0_TLP_EOT)
13840 #define F_CLIENT0_TLP_EOT    V_CLIENT0_TLP_EOT(1U)
13844 #define V_CLIENT0_TLP_ATTR(x) ((x) << S_CLIENT0_TLP_ATTR)
13845 #define G_CLIENT0_TLP_ATTR(x) (((x) >> S_CLIENT0_TLP_ATTR) & M_CLIENT0_TLP_ATTR)
13849 #define V_CLIENT0_TLP_TC(x) ((x) << S_CLIENT0_TLP_TC)
13850 #define G_CLIENT0_TLP_TC(x) (((x) >> S_CLIENT0_TLP_TC) & M_CLIENT0_TLP_TC)
13854 #define V_CLIENT0_TLP_TID(x) ((x) << S_CLIENT0_TLP_TID)
13855 #define G_CLIENT0_TLP_TID(x) (((x) >> S_CLIENT0_TLP_TID) & M_CLIENT0_TLP_TID)
13860 #define V_MEM_RSPRRAVLD(x) ((x) << S_MEM_RSPRRAVLD)
13861 #define F_MEM_RSPRRAVLD    V_MEM_RSPRRAVLD(1U)
13864 #define V_MEM_RSPRRARDY(x) ((x) << S_MEM_RSPRRARDY)
13865 #define F_MEM_RSPRRARDY    V_MEM_RSPRRARDY(1U)
13868 #define V_PIO_RSPRRAVLD(x) ((x) << S_PIO_RSPRRAVLD)
13869 #define F_PIO_RSPRRAVLD    V_PIO_RSPRRAVLD(1U)
13872 #define V_PIO_RSPRRARDY(x) ((x) << S_PIO_RSPRRARDY)
13873 #define F_PIO_RSPRRARDY    V_PIO_RSPRRARDY(1U)
13876 #define V_MEM_RSPRDVLD(x) ((x) << S_MEM_RSPRDVLD)
13877 #define F_MEM_RSPRDVLD    V_MEM_RSPRDVLD(1U)
13880 #define V_MEM_RSPRDRRARDY(x) ((x) << S_MEM_RSPRDRRARDY)
13881 #define F_MEM_RSPRDRRARDY    V_MEM_RSPRDRRARDY(1U)
13884 #define V_PIO_RSPRDVLD(x) ((x) << S_PIO_RSPRDVLD)
13885 #define F_PIO_RSPRDVLD    V_PIO_RSPRDVLD(1U)
13888 #define V_PIO_RSPRDRRARDY(x) ((x) << S_PIO_RSPRDRRARDY)
13889 #define F_PIO_RSPRDRRARDY    V_PIO_RSPRDRRARDY(1U)
13893 #define V_TGT_TAGQ_RDVLD(x) ((x) << S_TGT_TAGQ_RDVLD)
13894 #define G_TGT_TAGQ_RDVLD(x) (((x) >> S_TGT_TAGQ_RDVLD) & M_TGT_TAGQ_RDVLD)
13898 #define V_CPLTXNDISABLE(x) ((x) << S_CPLTXNDISABLE)
13899 #define G_CPLTXNDISABLE(x) (((x) >> S_CPLTXNDISABLE) & M_CPLTXNDISABLE)
13902 #define V_CPLTXNDISABLE2(x) ((x) << S_CPLTXNDISABLE2)
13903 #define F_CPLTXNDISABLE2    V_CPLTXNDISABLE2(1U)
13907 #define V_CLIENT0_TLP_HV(x) ((x) << S_CLIENT0_TLP_HV)
13908 #define G_CLIENT0_TLP_HV(x) (((x) >> S_CLIENT0_TLP_HV) & M_CLIENT0_TLP_HV)
13935 #define V_FLR_REQVLD(x) ((x) << S_FLR_REQVLD)
13936 #define F_FLR_REQVLD    V_FLR_REQVLD(1U)
13940 #define V_D_RSPVLD(x) ((x) << S_D_RSPVLD)
13941 #define G_D_RSPVLD(x) (((x) >> S_D_RSPVLD) & M_D_RSPVLD)
13944 #define V_D_RSPVLD2(x) ((x) << S_D_RSPVLD2)
13945 #define F_D_RSPVLD2    V_D_RSPVLD2(1U)
13948 #define V_D_RSPVLD3(x) ((x) << S_D_RSPVLD3)
13949 #define F_D_RSPVLD3    V_D_RSPVLD3(1U)
13952 #define V_D_RSPVLD4(x) ((x) << S_D_RSPVLD4)
13953 #define F_D_RSPVLD4    V_D_RSPVLD4(1U)
13956 #define V_D_RSPVLD5(x) ((x) << S_D_RSPVLD5)
13957 #define F_D_RSPVLD5    V_D_RSPVLD5(1U)
13961 #define V_D_RSPVLD6(x) ((x) << S_D_RSPVLD6)
13962 #define G_D_RSPVLD6(x) (((x) >> S_D_RSPVLD6) & M_D_RSPVLD6)
13966 #define V_D_RSPAFULL(x) ((x) << S_D_RSPAFULL)
13967 #define G_D_RSPAFULL(x) (((x) >> S_D_RSPAFULL) & M_D_RSPAFULL)
13971 #define V_D_RDREQVLD(x) ((x) << S_D_RDREQVLD)
13972 #define G_D_RDREQVLD(x) (((x) >> S_D_RDREQVLD) & M_D_RDREQVLD)
13976 #define V_D_RDREQAFULL(x) ((x) << S_D_RDREQAFULL)
13977 #define G_D_RDREQAFULL(x) (((x) >> S_D_RDREQAFULL) & M_D_RDREQAFULL)
13981 #define V_D_WRREQVLD(x) ((x) << S_D_WRREQVLD)
13982 #define G_D_WRREQVLD(x) (((x) >> S_D_WRREQVLD) & M_D_WRREQVLD)
13986 #define V_D_WRREQAFULL(x) ((x) << S_D_WRREQAFULL)
13987 #define G_D_WRREQAFULL(x) (((x) >> S_D_WRREQAFULL) & M_D_WRREQAFULL)
13993 #define V_C_REQVLD(x) ((x) << S_C_REQVLD)
13994 #define G_C_REQVLD(x) (((x) >> S_C_REQVLD) & M_C_REQVLD)
13998 #define V_C_RSPVLD2(x) ((x) << S_C_RSPVLD2)
13999 #define G_C_RSPVLD2(x) (((x) >> S_C_RSPVLD2) & M_C_RSPVLD2)
14002 #define V_C_RSPVLD3(x) ((x) << S_C_RSPVLD3)
14003 #define F_C_RSPVLD3    V_C_RSPVLD3(1U)
14006 #define V_C_RSPVLD4(x) ((x) << S_C_RSPVLD4)
14007 #define F_C_RSPVLD4    V_C_RSPVLD4(1U)
14010 #define V_C_RSPVLD5(x) ((x) << S_C_RSPVLD5)
14011 #define F_C_RSPVLD5    V_C_RSPVLD5(1U)
14014 #define V_C_RSPVLD6(x) ((x) << S_C_RSPVLD6)
14015 #define F_C_RSPVLD6    V_C_RSPVLD6(1U)
14019 #define V_C_RSPVLD7(x) ((x) << S_C_RSPVLD7)
14020 #define G_C_RSPVLD7(x) (((x) >> S_C_RSPVLD7) & M_C_RSPVLD7)
14024 #define V_C_RSPAFULL(x) ((x) << S_C_RSPAFULL)
14025 #define G_C_RSPAFULL(x) (((x) >> S_C_RSPAFULL) & M_C_RSPAFULL)
14029 #define V_C_REQVLD8(x) ((x) << S_C_REQVLD8)
14030 #define G_C_REQVLD8(x) (((x) >> S_C_REQVLD8) & M_C_REQVLD8)
14034 #define V_C_REQAFULL(x) ((x) << S_C_REQAFULL)
14035 #define G_C_REQAFULL(x) (((x) >> S_C_REQAFULL) & M_C_REQAFULL)
14041 #define V_H_REQVLD(x) ((x) << S_H_REQVLD)
14042 #define G_H_REQVLD(x) (((x) >> S_H_REQVLD) & M_H_REQVLD)
14045 #define V_H_RSPVLD(x) ((x) << S_H_RSPVLD)
14046 #define F_H_RSPVLD    V_H_RSPVLD(1U)
14049 #define V_H_RSPVLD2(x) ((x) << S_H_RSPVLD2)
14050 #define F_H_RSPVLD2    V_H_RSPVLD2(1U)
14053 #define V_H_RSPVLD3(x) ((x) << S_H_RSPVLD3)
14054 #define F_H_RSPVLD3    V_H_RSPVLD3(1U)
14057 #define V_H_RSPVLD4(x) ((x) << S_H_RSPVLD4)
14058 #define F_H_RSPVLD4    V_H_RSPVLD4(1U)
14061 #define V_H_RSPAFULL(x) ((x) << S_H_RSPAFULL)
14062 #define F_H_RSPAFULL    V_H_RSPAFULL(1U)
14064 #define S_H_REQVLD2    1
14065 #define V_H_REQVLD2(x) ((x) << S_H_REQVLD2)
14066 #define F_H_REQVLD2    V_H_REQVLD2(1U)
14069 #define V_H_REQAFULL(x) ((x) << S_H_REQAFULL)
14070 #define F_H_REQAFULL    V_H_REQAFULL(1U)
14076 #define V_ER_RSPVLD(x) ((x) << S_ER_RSPVLD)
14077 #define G_ER_RSPVLD(x) (((x) >> S_ER_RSPVLD) & M_ER_RSPVLD)
14081 #define V_ER_REQVLD2(x) ((x) << S_ER_REQVLD2)
14082 #define G_ER_REQVLD2(x) (((x) >> S_ER_REQVLD2) & M_ER_REQVLD2)
14086 #define V_ER_REQVLD3(x) ((x) << S_ER_REQVLD3)
14087 #define G_ER_REQVLD3(x) (((x) >> S_ER_REQVLD3) & M_ER_REQVLD3)
14089 #define S_ER_RSPVLD4    1
14090 #define V_ER_RSPVLD4(x) ((x) << S_ER_RSPVLD4)
14091 #define F_ER_RSPVLD4    V_ER_RSPVLD4(1U)
14094 #define V_ER_REQVLD5(x) ((x) << S_ER_REQVLD5)
14095 #define F_ER_REQVLD5    V_ER_REQVLD5(1U)
14101 #define V_PL_BAR2_REQVLD(x) ((x) << S_PL_BAR2_REQVLD)
14102 #define G_PL_BAR2_REQVLD(x) (((x) >> S_PL_BAR2_REQVLD) & M_PL_BAR2_REQVLD)
14105 #define V_PL_BAR2_REQVLD2(x) ((x) << S_PL_BAR2_REQVLD2)
14106 #define F_PL_BAR2_REQVLD2    V_PL_BAR2_REQVLD2(1U)
14109 #define V_PL_BAR2_REQVLDE(x) ((x) << S_PL_BAR2_REQVLDE)
14110 #define F_PL_BAR2_REQVLDE    V_PL_BAR2_REQVLDE(1U)
14112 #define S_PL_BAR2_REQFULL    1
14113 #define V_PL_BAR2_REQFULL(x) ((x) << S_PL_BAR2_REQFULL)
14114 #define F_PL_BAR2_REQFULL    V_PL_BAR2_REQFULL(1U)
14117 #define V_PL_BAR2_REQVLD4(x) ((x) << S_PL_BAR2_REQVLD4)
14118 #define F_PL_BAR2_REQVLD4    V_PL_BAR2_REQVLD4(1U)
14127 #define V_VPD_RSPVLD(x) ((x) << S_VPD_RSPVLD)
14128 #define G_VPD_RSPVLD(x) (((x) >> S_VPD_RSPVLD) & M_VPD_RSPVLD)
14132 #define V_VPD_REQVLD2(x) ((x) << S_VPD_REQVLD2)
14133 #define G_VPD_REQVLD2(x) (((x) >> S_VPD_REQVLD2) & M_VPD_REQVLD2)
14137 #define V_VPD_REQVLD3(x) ((x) << S_VPD_REQVLD3)
14138 #define G_VPD_REQVLD3(x) (((x) >> S_VPD_REQVLD3) & M_VPD_REQVLD3)
14141 #define V_VPD_REQVLD4(x) ((x) << S_VPD_REQVLD4)
14142 #define F_VPD_REQVLD4    V_VPD_REQVLD4(1U)
14146 #define V_VPD_REQVLD5(x) ((x) << S_VPD_REQVLD5)
14147 #define G_VPD_REQVLD5(x) (((x) >> S_VPD_REQVLD5) & M_VPD_REQVLD5)
14150 #define V_VPD_RSPVLD2(x) ((x) << S_VPD_RSPVLD2)
14151 #define F_VPD_RSPVLD2    V_VPD_RSPVLD2(1U)
14153 #define S_VPD_RSPVLD3    1
14154 #define V_VPD_RSPVLD3(x) ((x) << S_VPD_RSPVLD3)
14155 #define F_VPD_RSPVLD3    V_VPD_RSPVLD3(1U)
14158 #define V_VPD_REQVLD6(x) ((x) << S_VPD_REQVLD6)
14159 #define F_VPD_REQVLD6    V_VPD_REQVLD6(1U)
14165 #define V_MA_REQDATAVLD(x) ((x) << S_MA_REQDATAVLD)
14166 #define G_MA_REQDATAVLD(x) (((x) >> S_MA_REQDATAVLD) & M_MA_REQDATAVLD)
14169 #define V_MA_REQADDRVLD(x) ((x) << S_MA_REQADDRVLD)
14170 #define F_MA_REQADDRVLD    V_MA_REQADDRVLD(1U)
14173 #define V_MA_REQADDRVLD2(x) ((x) << S_MA_REQADDRVLD2)
14174 #define F_MA_REQADDRVLD2    V_MA_REQADDRVLD2(1U)
14178 #define V_MA_RSPDATAVLD2(x) ((x) << S_MA_RSPDATAVLD2)
14179 #define G_MA_RSPDATAVLD2(x) (((x) >> S_MA_RSPDATAVLD2) & M_MA_RSPDATAVLD2)
14183 #define V_MA_REQADDRVLD3(x) ((x) << S_MA_REQADDRVLD3)
14184 #define G_MA_REQADDRVLD3(x) (((x) >> S_MA_REQADDRVLD3) & M_MA_REQADDRVLD3)
14188 #define V_MA_REQADDRVLD4(x) ((x) << S_MA_REQADDRVLD4)
14189 #define G_MA_REQADDRVLD4(x) (((x) >> S_MA_REQADDRVLD4) & M_MA_REQADDRVLD4)
14192 #define V_MA_REQADDRVLD5(x) ((x) << S_MA_REQADDRVLD5)
14193 #define F_MA_REQADDRVLD5    V_MA_REQADDRVLD5(1U)
14196 #define V_MA_REQADDRVLD6(x) ((x) << S_MA_REQADDRVLD6)
14197 #define F_MA_REQADDRVLD6    V_MA_REQADDRVLD6(1U)
14199 #define S_MA_REQADDRRDY    1
14200 #define V_MA_REQADDRRDY(x) ((x) << S_MA_REQADDRRDY)
14201 #define F_MA_REQADDRRDY    V_MA_REQADDRRDY(1U)
14204 #define V_MA_REQADDRVLD7(x) ((x) << S_MA_REQADDRVLD7)
14205 #define F_MA_REQADDRVLD7    V_MA_REQADDRVLD7(1U)
14220 #define V_PLM_REQVLD(x) ((x) << S_PLM_REQVLD)
14221 #define G_PLM_REQVLD(x) (((x) >> S_PLM_REQVLD) & M_PLM_REQVLD)
14224 #define V_PLM_REQVLD2(x) ((x) << S_PLM_REQVLD2)
14225 #define F_PLM_REQVLD2    V_PLM_REQVLD2(1U)
14228 #define V_PLM_RSPVLD3(x) ((x) << S_PLM_RSPVLD3)
14229 #define F_PLM_RSPVLD3    V_PLM_RSPVLD3(1U)
14232 #define V_PLM_REQVLD4(x) ((x) << S_PLM_REQVLD4)
14233 #define F_PLM_REQVLD4    V_PLM_REQVLD4(1U)
14236 #define V_PLM_REQVLD5(x) ((x) << S_PLM_REQVLD5)
14237 #define F_PLM_REQVLD5    V_PLM_REQVLD5(1U)
14240 #define V_PLM_REQVLD6(x) ((x) << S_PLM_REQVLD6)
14241 #define F_PLM_REQVLD6    V_PLM_REQVLD6(1U)
14244 #define V_PLM_REQVLD7(x) ((x) << S_PLM_REQVLD7)
14245 #define F_PLM_REQVLD7    V_PLM_REQVLD7(1U)
14248 #define V_PLM_REQVLD8(x) ((x) << S_PLM_REQVLD8)
14249 #define F_PLM_REQVLD8    V_PLM_REQVLD8(1U)
14253 #define V_PLM_REQVLD9(x) ((x) << S_PLM_REQVLD9)
14254 #define G_PLM_REQVLD9(x) (((x) >> S_PLM_REQVLD9) & M_PLM_REQVLD9)
14256 #define S_PLM_REQVLDA    1
14258 #define V_PLM_REQVLDA(x) ((x) << S_PLM_REQVLDA)
14259 #define G_PLM_REQVLDA(x) (((x) >> S_PLM_REQVLDA) & M_PLM_REQVLDA)
14262 #define V_PLM_REQVLDB(x) ((x) << S_PLM_REQVLDB)
14263 #define F_PLM_REQVLDB    V_PLM_REQVLDB(1U)
14307 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
14308 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
14312 #define V_REGSELECT(x) ((x) << S_REGSELECT)
14313 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
14317 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
14318 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
14323 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
14324 #define F_PORTEN_PONR    V_PORTEN_PONR(1U)
14327 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
14328 #define F_PORTEN_POND    V_PORTEN_POND(1U)
14331 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
14332 #define F_SDRHALFWORD0    V_SDRHALFWORD0(1U)
14335 #define V_DDREN(x) ((x) << S_DDREN)
14336 #define F_DDREN    V_DDREN(1U)
14339 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
14340 #define F_DBG_PORTEN    V_DBG_PORTEN(1U)
14346 #define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
14347 #define F_CLK_EN_ON_DBG1    V_CLK_EN_ON_DBG1(1U)
14352 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
14353 #define F_GPIO15_OEN    V_GPIO15_OEN(1U)
14356 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
14357 #define F_GPIO14_OEN    V_GPIO14_OEN(1U)
14360 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
14361 #define F_GPIO13_OEN    V_GPIO13_OEN(1U)
14364 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
14365 #define F_GPIO12_OEN    V_GPIO12_OEN(1U)
14368 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
14369 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
14372 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
14373 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
14376 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
14377 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
14380 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
14381 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
14384 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
14385 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
14388 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
14389 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
14392 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
14393 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
14396 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
14397 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
14400 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
14401 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
14404 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
14405 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
14408 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
14409 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
14412 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
14413 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
14416 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
14417 #define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)
14420 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
14421 #define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)
14424 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
14425 #define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)
14428 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
14429 #define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)
14432 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
14433 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
14436 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
14437 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
14440 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
14441 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
14444 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
14445 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
14448 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
14449 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
14452 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
14453 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
14456 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
14457 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
14460 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
14461 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
14464 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
14465 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
14468 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
14469 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
14471 #define S_GPIO1_OUT_VAL    1
14472 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
14473 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
14476 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
14477 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
14482 #define V_GPIO23_OUT_VAL(x) ((x) << S_GPIO23_OUT_VAL)
14483 #define F_GPIO23_OUT_VAL    V_GPIO23_OUT_VAL(1U)
14486 #define V_GPIO22_OUT_VAL(x) ((x) << S_GPIO22_OUT_VAL)
14487 #define F_GPIO22_OUT_VAL    V_GPIO22_OUT_VAL(1U)
14490 #define V_GPIO21_OUT_VAL(x) ((x) << S_GPIO21_OUT_VAL)
14491 #define F_GPIO21_OUT_VAL    V_GPIO21_OUT_VAL(1U)
14494 #define V_GPIO20_OUT_VAL(x) ((x) << S_GPIO20_OUT_VAL)
14495 #define F_GPIO20_OUT_VAL    V_GPIO20_OUT_VAL(1U)
14498 #define V_T7_GPIO19_OUT_VAL(x) ((x) << S_T7_GPIO19_OUT_VAL)
14499 #define F_T7_GPIO19_OUT_VAL    V_T7_GPIO19_OUT_VAL(1U)
14502 #define V_T7_GPIO18_OUT_VAL(x) ((x) << S_T7_GPIO18_OUT_VAL)
14503 #define F_T7_GPIO18_OUT_VAL    V_T7_GPIO18_OUT_VAL(1U)
14506 #define V_T7_GPIO17_OUT_VAL(x) ((x) << S_T7_GPIO17_OUT_VAL)
14507 #define F_T7_GPIO17_OUT_VAL    V_T7_GPIO17_OUT_VAL(1U)
14510 #define V_T7_GPIO16_OUT_VAL(x) ((x) << S_T7_GPIO16_OUT_VAL)
14511 #define F_T7_GPIO16_OUT_VAL    V_T7_GPIO16_OUT_VAL(1U)
14516 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
14517 #define F_GPIO15_CHG_DET    V_GPIO15_CHG_DET(1U)
14520 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
14521 #define F_GPIO14_CHG_DET    V_GPIO14_CHG_DET(1U)
14524 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
14525 #define F_GPIO13_CHG_DET    V_GPIO13_CHG_DET(1U)
14528 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
14529 #define F_GPIO12_CHG_DET    V_GPIO12_CHG_DET(1U)
14532 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
14533 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
14536 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
14537 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
14540 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
14541 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
14544 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
14545 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
14548 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
14549 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
14552 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
14553 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
14556 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
14557 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
14560 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
14561 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
14564 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
14565 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
14568 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
14569 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
14572 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
14573 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
14576 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
14577 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
14580 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
14581 #define F_GPIO15_IN    V_GPIO15_IN(1U)
14584 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
14585 #define F_GPIO14_IN    V_GPIO14_IN(1U)
14588 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
14589 #define F_GPIO13_IN    V_GPIO13_IN(1U)
14592 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
14593 #define F_GPIO12_IN    V_GPIO12_IN(1U)
14596 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
14597 #define F_GPIO11_IN    V_GPIO11_IN(1U)
14600 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
14601 #define F_GPIO10_IN    V_GPIO10_IN(1U)
14604 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
14605 #define F_GPIO9_IN    V_GPIO9_IN(1U)
14608 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
14609 #define F_GPIO8_IN    V_GPIO8_IN(1U)
14612 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
14613 #define F_GPIO7_IN    V_GPIO7_IN(1U)
14616 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
14617 #define F_GPIO6_IN    V_GPIO6_IN(1U)
14620 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
14621 #define F_GPIO5_IN    V_GPIO5_IN(1U)
14624 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
14625 #define F_GPIO4_IN    V_GPIO4_IN(1U)
14628 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
14629 #define F_GPIO3_IN    V_GPIO3_IN(1U)
14632 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
14633 #define F_GPIO2_IN    V_GPIO2_IN(1U)
14635 #define S_GPIO1_IN    1
14636 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
14637 #define F_GPIO1_IN    V_GPIO1_IN(1U)
14640 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
14641 #define F_GPIO0_IN    V_GPIO0_IN(1U)
14644 #define V_GPIO23_IN(x) ((x) << S_GPIO23_IN)
14645 #define F_GPIO23_IN    V_GPIO23_IN(1U)
14648 #define V_GPIO22_IN(x) ((x) << S_GPIO22_IN)
14649 #define F_GPIO22_IN    V_GPIO22_IN(1U)
14652 #define V_GPIO21_IN(x) ((x) << S_GPIO21_IN)
14653 #define F_GPIO21_IN    V_GPIO21_IN(1U)
14656 #define V_GPIO20_IN(x) ((x) << S_GPIO20_IN)
14657 #define F_GPIO20_IN    V_GPIO20_IN(1U)
14660 #define V_T7_GPIO19_IN(x) ((x) << S_T7_GPIO19_IN)
14661 #define F_T7_GPIO19_IN    V_T7_GPIO19_IN(1U)
14664 #define V_T7_GPIO18_IN(x) ((x) << S_T7_GPIO18_IN)
14665 #define F_T7_GPIO18_IN    V_T7_GPIO18_IN(1U)
14668 #define V_T7_GPIO17_IN(x) ((x) << S_T7_GPIO17_IN)
14669 #define F_T7_GPIO17_IN    V_T7_GPIO17_IN(1U)
14672 #define V_T7_GPIO16_IN(x) ((x) << S_T7_GPIO16_IN)
14673 #define F_T7_GPIO16_IN    V_T7_GPIO16_IN(1U)
14678 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
14679 #define F_IBM_FDL_FAIL_INT_ENBL    V_IBM_FDL_FAIL_INT_ENBL(1U)
14682 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
14683 #define F_ARM_FAIL_INT_ENBL    V_ARM_FAIL_INT_ENBL(1U)
14686 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
14687 #define F_ARM_ERROR_OUT_INT_ENBL    V_ARM_ERROR_OUT_INT_ENBL(1U)
14690 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
14691 #define F_PLL_LOCK_LOST_INT_ENBL    V_PLL_LOCK_LOST_INT_ENBL(1U)
14694 #define V_C_LOCK(x) ((x) << S_C_LOCK)
14695 #define F_C_LOCK    V_C_LOCK(1U)
14698 #define V_M_LOCK(x) ((x) << S_M_LOCK)
14699 #define F_M_LOCK    V_M_LOCK(1U)
14702 #define V_U_LOCK(x) ((x) << S_U_LOCK)
14703 #define F_U_LOCK    V_U_LOCK(1U)
14706 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
14707 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
14710 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
14711 #define F_KX_LOCK    V_KX_LOCK(1U)
14714 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
14715 #define F_KR_LOCK    V_KR_LOCK(1U)
14718 #define V_GPIO15(x) ((x) << S_GPIO15)
14719 #define F_GPIO15    V_GPIO15(1U)
14722 #define V_GPIO14(x) ((x) << S_GPIO14)
14723 #define F_GPIO14    V_GPIO14(1U)
14726 #define V_GPIO13(x) ((x) << S_GPIO13)
14727 #define F_GPIO13    V_GPIO13(1U)
14730 #define V_GPIO12(x) ((x) << S_GPIO12)
14731 #define F_GPIO12    V_GPIO12(1U)
14734 #define V_GPIO11(x) ((x) << S_GPIO11)
14735 #define F_GPIO11    V_GPIO11(1U)
14738 #define V_GPIO10(x) ((x) << S_GPIO10)
14739 #define F_GPIO10    V_GPIO10(1U)
14742 #define V_GPIO9(x) ((x) << S_GPIO9)
14743 #define F_GPIO9    V_GPIO9(1U)
14746 #define V_GPIO8(x) ((x) << S_GPIO8)
14747 #define F_GPIO8    V_GPIO8(1U)
14750 #define V_GPIO7(x) ((x) << S_GPIO7)
14751 #define F_GPIO7    V_GPIO7(1U)
14754 #define V_GPIO6(x) ((x) << S_GPIO6)
14755 #define F_GPIO6    V_GPIO6(1U)
14758 #define V_GPIO5(x) ((x) << S_GPIO5)
14759 #define F_GPIO5    V_GPIO5(1U)
14762 #define V_GPIO4(x) ((x) << S_GPIO4)
14763 #define F_GPIO4    V_GPIO4(1U)
14766 #define V_GPIO3(x) ((x) << S_GPIO3)
14767 #define F_GPIO3    V_GPIO3(1U)
14770 #define V_GPIO2(x) ((x) << S_GPIO2)
14771 #define F_GPIO2    V_GPIO2(1U)
14773 #define S_GPIO1    1
14774 #define V_GPIO1(x) ((x) << S_GPIO1)
14775 #define F_GPIO1    V_GPIO1(1U)
14778 #define V_GPIO0(x) ((x) << S_GPIO0)
14779 #define F_GPIO0    V_GPIO0(1U)
14782 #define V_GPIO19(x) ((x) << S_GPIO19)
14783 #define F_GPIO19    V_GPIO19(1U)
14786 #define V_GPIO18(x) ((x) << S_GPIO18)
14787 #define F_GPIO18    V_GPIO18(1U)
14790 #define V_GPIO17(x) ((x) << S_GPIO17)
14791 #define F_GPIO17    V_GPIO17(1U)
14794 #define V_GPIO16(x) ((x) << S_GPIO16)
14795 #define F_GPIO16    V_GPIO16(1U)
14798 #define V_USBFIFOPARERR(x) ((x) << S_USBFIFOPARERR)
14799 #define F_USBFIFOPARERR    V_USBFIFOPARERR(1U)
14802 #define V_T7_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_T7_IBM_FDL_FAIL_INT_ENBL)
14803 #define F_T7_IBM_FDL_FAIL_INT_ENBL    V_T7_IBM_FDL_FAIL_INT_ENBL(1U)
14806 #define V_T7_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_T7_PLL_LOCK_LOST_INT_ENBL)
14807 #define F_T7_PLL_LOCK_LOST_INT_ENBL    V_T7_PLL_LOCK_LOST_INT_ENBL(1U)
14810 #define V_M1_LOCK(x) ((x) << S_M1_LOCK)
14811 #define F_M1_LOCK    V_M1_LOCK(1U)
14814 #define V_T7_PCIE_LOCK(x) ((x) << S_T7_PCIE_LOCK)
14815 #define F_T7_PCIE_LOCK    V_T7_PCIE_LOCK(1U)
14818 #define V_T7_U_LOCK(x) ((x) << S_T7_U_LOCK)
14819 #define F_T7_U_LOCK    V_T7_U_LOCK(1U)
14822 #define V_MAC_LOCK(x) ((x) << S_MAC_LOCK)
14823 #define F_MAC_LOCK    V_MAC_LOCK(1U)
14826 #define V_ARM_LOCK(x) ((x) << S_ARM_LOCK)
14827 #define F_ARM_LOCK    V_ARM_LOCK(1U)
14830 #define V_M0_LOCK(x) ((x) << S_M0_LOCK)
14831 #define F_M0_LOCK    V_M0_LOCK(1U)
14834 #define V_XGPBUS_LOCK(x) ((x) << S_XGPBUS_LOCK)
14835 #define F_XGPBUS_LOCK    V_XGPBUS_LOCK(1U)
14838 #define V_XGPHY_LOCK(x) ((x) << S_XGPHY_LOCK)
14839 #define F_XGPHY_LOCK    V_XGPHY_LOCK(1U)
14841 #define S_USB_LOCK    1
14842 #define V_USB_LOCK(x) ((x) << S_USB_LOCK)
14843 #define F_USB_LOCK    V_USB_LOCK(1U)
14846 #define V_T7_C_LOCK(x) ((x) << S_T7_C_LOCK)
14847 #define F_T7_C_LOCK    V_T7_C_LOCK(1U)
14852 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
14853 #define F_IBM_FDL_FAIL_INT_CAUSE    V_IBM_FDL_FAIL_INT_CAUSE(1U)
14856 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
14857 #define F_ARM_FAIL_INT_CAUSE    V_ARM_FAIL_INT_CAUSE(1U)
14860 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
14861 #define F_ARM_ERROR_OUT_INT_CAUSE    V_ARM_ERROR_OUT_INT_CAUSE(1U)
14864 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
14865 #define F_PLL_LOCK_LOST_INT_CAUSE    V_PLL_LOCK_LOST_INT_CAUSE(1U)
14868 #define V_T7_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_T7_IBM_FDL_FAIL_INT_CAUSE)
14869 #define F_T7_IBM_FDL_FAIL_INT_CAUSE    V_T7_IBM_FDL_FAIL_INT_CAUSE(1U)
14872 #define V_T7_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_T7_PLL_LOCK_LOST_INT_CAUSE)
14873 #define F_T7_PLL_LOCK_LOST_INT_CAUSE    V_T7_PLL_LOCK_LOST_INT_CAUSE(1U)
14879 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
14880 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
14885 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
14886 #define F_OVERWRSERCFG_EN    V_OVERWRSERCFG_EN(1U)
14891 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
14892 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
14895 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
14896 #define F_KX_OCLK_EN    V_KX_OCLK_EN(1U)
14899 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
14900 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
14903 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
14904 #define F_KR_OCLK_EN    V_KR_OCLK_EN(1U)
14907 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
14908 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
14911 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
14912 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
14915 #define V_INIC_MODE_EN(x) ((x) << S_INIC_MODE_EN)
14916 #define F_INIC_MODE_EN    V_INIC_MODE_EN(1U)
14921 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
14922 #define F_PLL_P_LOCK    V_PLL_P_LOCK(1U)
14925 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
14926 #define F_PLL_KX_LOCK    V_PLL_KX_LOCK(1U)
14929 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
14930 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
14933 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
14934 #define F_PLL_KR_LOCK    V_PLL_KR_LOCK(1U)
14937 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
14938 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
14941 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
14942 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
14945 #define V_T7_PLL_M_LOCK(x) ((x) << S_T7_PLL_M_LOCK)
14946 #define F_T7_PLL_M_LOCK    V_T7_PLL_M_LOCK(1U)
14949 #define V_PLL_PCIE_LOCK(x) ((x) << S_PLL_PCIE_LOCK)
14950 #define F_PLL_PCIE_LOCK    V_PLL_PCIE_LOCK(1U)
14953 #define V_T7_PLL_U_LOCK(x) ((x) << S_T7_PLL_U_LOCK)
14954 #define F_T7_PLL_U_LOCK    V_T7_PLL_U_LOCK(1U)
14957 #define V_PLL_MAC_LOCK(x) ((x) << S_PLL_MAC_LOCK)
14958 #define F_PLL_MAC_LOCK    V_PLL_MAC_LOCK(1U)
14961 #define V_PLL_ARM_LOCK(x) ((x) << S_PLL_ARM_LOCK)
14962 #define F_PLL_ARM_LOCK    V_PLL_ARM_LOCK(1U)
14965 #define V_PLL_XGPBUS_LOCK(x) ((x) << S_PLL_XGPBUS_LOCK)
14966 #define F_PLL_XGPBUS_LOCK    V_PLL_XGPBUS_LOCK(1U)
14969 #define V_PLL_XGPHY_LOCK(x) ((x) << S_PLL_XGPHY_LOCK)
14970 #define F_PLL_XGPHY_LOCK    V_PLL_XGPHY_LOCK(1U)
14972 #define S_PLL_USB_LOCK    1
14973 #define V_PLL_USB_LOCK(x) ((x) << S_PLL_USB_LOCK)
14974 #define F_PLL_USB_LOCK    V_PLL_USB_LOCK(1U)
14979 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
14980 #define F_P_LOCK_ACT_LOW    V_P_LOCK_ACT_LOW(1U)
14983 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
14984 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
14987 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
14988 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
14991 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
14992 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
14995 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
14996 #define F_KR_LOCK_ACT_LOW    V_KR_LOCK_ACT_LOW(1U)
14999 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
15000 #define F_KX_LOCK_ACT_LOW    V_KX_LOCK_ACT_LOW(1U)
15003 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
15004 #define F_GPIO15_ACT_LOW    V_GPIO15_ACT_LOW(1U)
15007 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
15008 #define F_GPIO14_ACT_LOW    V_GPIO14_ACT_LOW(1U)
15011 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
15012 #define F_GPIO13_ACT_LOW    V_GPIO13_ACT_LOW(1U)
15015 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
15016 #define F_GPIO12_ACT_LOW    V_GPIO12_ACT_LOW(1U)
15019 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
15020 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
15023 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
15024 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
15027 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
15028 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
15031 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
15032 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
15035 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
15036 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
15039 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
15040 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
15043 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
15044 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
15047 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
15048 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
15051 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
15052 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
15055 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
15056 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
15058 #define S_GPIO1_ACT_LOW    1
15059 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
15060 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
15063 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
15064 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
15067 #define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
15068 #define F_GPIO19_ACT_LOW    V_GPIO19_ACT_LOW(1U)
15071 #define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
15072 #define F_GPIO18_ACT_LOW    V_GPIO18_ACT_LOW(1U)
15075 #define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
15076 #define F_GPIO17_ACT_LOW    V_GPIO17_ACT_LOW(1U)
15079 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
15080 #define F_GPIO16_ACT_LOW    V_GPIO16_ACT_LOW(1U)
15085 #define V_M1_LOCK_ACT_LOW(x) ((x) << S_M1_LOCK_ACT_LOW)
15086 #define F_M1_LOCK_ACT_LOW    V_M1_LOCK_ACT_LOW(1U)
15089 #define V_PCIE_LOCK_ACT_LOW(x) ((x) << S_PCIE_LOCK_ACT_LOW)
15090 #define F_PCIE_LOCK_ACT_LOW    V_PCIE_LOCK_ACT_LOW(1U)
15093 #define V_T7_U_LOCK_ACT_LOW(x) ((x) << S_T7_U_LOCK_ACT_LOW)
15094 #define F_T7_U_LOCK_ACT_LOW    V_T7_U_LOCK_ACT_LOW(1U)
15097 #define V_MAC_LOCK_ACT_LOW(x) ((x) << S_MAC_LOCK_ACT_LOW)
15098 #define F_MAC_LOCK_ACT_LOW    V_MAC_LOCK_ACT_LOW(1U)
15101 #define V_ARM_LOCK_ACT_LOW(x) ((x) << S_ARM_LOCK_ACT_LOW)
15102 #define F_ARM_LOCK_ACT_LOW    V_ARM_LOCK_ACT_LOW(1U)
15105 #define V_M0_LOCK_ACT_LOW(x) ((x) << S_M0_LOCK_ACT_LOW)
15106 #define F_M0_LOCK_ACT_LOW    V_M0_LOCK_ACT_LOW(1U)
15109 #define V_XGPBUS_LOCK_ACT_LOW(x) ((x) << S_XGPBUS_LOCK_ACT_LOW)
15110 #define F_XGPBUS_LOCK_ACT_LOW    V_XGPBUS_LOCK_ACT_LOW(1U)
15113 #define V_XGPHY_LOCK_ACT_LOW(x) ((x) << S_XGPHY_LOCK_ACT_LOW)
15114 #define F_XGPHY_LOCK_ACT_LOW    V_XGPHY_LOCK_ACT_LOW(1U)
15116 #define S_USB_LOCK_ACT_LOW    1
15117 #define V_USB_LOCK_ACT_LOW(x) ((x) << S_USB_LOCK_ACT_LOW)
15118 #define F_USB_LOCK_ACT_LOW    V_USB_LOCK_ACT_LOW(1U)
15121 #define V_T7_C_LOCK_ACT_LOW(x) ((x) << S_T7_C_LOCK_ACT_LOW)
15122 #define F_T7_C_LOCK_ACT_LOW    V_T7_C_LOCK_ACT_LOW(1U)
15132 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
15133 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
15137 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
15138 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
15142 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
15143 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
15147 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
15148 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
15152 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
15153 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
15159 #define V_STATIC_U_PLL_RANGE(x) ((x) << S_STATIC_U_PLL_RANGE)
15160 #define G_STATIC_U_PLL_RANGE(x) (((x) >> S_STATIC_U_PLL_RANGE) & M_STATIC_U_PLL_RANGE)
15164 #define V_STATIC_U_PLL_DIVQ(x) ((x) << S_STATIC_U_PLL_DIVQ)
15165 #define G_STATIC_U_PLL_DIVQ(x) (((x) >> S_STATIC_U_PLL_DIVQ) & M_STATIC_U_PLL_DIVQ)
15169 #define V_STATIC_U_PLL_DIVFI(x) ((x) << S_STATIC_U_PLL_DIVFI)
15170 #define G_STATIC_U_PLL_DIVFI(x) (((x) >> S_STATIC_U_PLL_DIVFI) & M_STATIC_U_PLL_DIVFI)
15174 #define V_STATIC_U_PLL_DIVR(x) ((x) << S_STATIC_U_PLL_DIVR)
15175 #define G_STATIC_U_PLL_DIVR(x) (((x) >> S_STATIC_U_PLL_DIVR) & M_STATIC_U_PLL_DIVR)
15177 #define S_T7_1_STATIC_U_PLL_BYPASS    1
15178 #define V_T7_1_STATIC_U_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_U_PLL_BYPASS)
15179 #define F_T7_1_STATIC_U_PLL_BYPASS    V_T7_1_STATIC_U_PLL_BYPASS(1U)
15185 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
15186 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
15190 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
15191 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
15195 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
15196 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
15200 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
15201 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
15205 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
15206 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
15212 #define V_STATIC_U_PLL_SSMF(x) ((x) << S_STATIC_U_PLL_SSMF)
15213 #define G_STATIC_U_PLL_SSMF(x) (((x) >> S_STATIC_U_PLL_SSMF) & M_STATIC_U_PLL_SSMF)
15217 #define V_STATIC_U_PLL_SSMD(x) ((x) << S_STATIC_U_PLL_SSMD)
15218 #define G_STATIC_U_PLL_SSMD(x) (((x) >> S_STATIC_U_PLL_SSMD) & M_STATIC_U_PLL_SSMD)
15220 #define S_STATIC_U_PLL_SSDS    1
15221 #define V_STATIC_U_PLL_SSDS(x) ((x) << S_STATIC_U_PLL_SSDS)
15222 #define F_STATIC_U_PLL_SSDS    V_STATIC_U_PLL_SSDS(1U)
15225 #define V_STATIC_U_PLL_SSE(x) ((x) << S_STATIC_U_PLL_SSE)
15226 #define F_STATIC_U_PLL_SSE    V_STATIC_U_PLL_SSE(1U)
15232 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
15233 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
15237 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
15238 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
15242 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
15243 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
15247 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
15248 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
15252 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
15253 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
15259 #define V_STATIC_C_PLL_RANGE(x) ((x) << S_STATIC_C_PLL_RANGE)
15260 #define G_STATIC_C_PLL_RANGE(x) (((x) >> S_STATIC_C_PLL_RANGE) & M_STATIC_C_PLL_RANGE)
15264 #define V_STATIC_C_PLL_DIVQ(x) ((x) << S_STATIC_C_PLL_DIVQ)
15265 #define G_STATIC_C_PLL_DIVQ(x) (((x) >> S_STATIC_C_PLL_DIVQ) & M_STATIC_C_PLL_DIVQ)
15269 #define V_STATIC_C_PLL_DIVFI(x) ((x) << S_STATIC_C_PLL_DIVFI)
15270 #define G_STATIC_C_PLL_DIVFI(x) (((x) >> S_STATIC_C_PLL_DIVFI) & M_STATIC_C_PLL_DIVFI)
15274 #define V_STATIC_C_PLL_DIVR(x) ((x) << S_STATIC_C_PLL_DIVR)
15275 #define G_STATIC_C_PLL_DIVR(x) (((x) >> S_STATIC_C_PLL_DIVR) & M_STATIC_C_PLL_DIVR)
15277 #define S_T7_1_STATIC_C_PLL_BYPASS    1
15278 #define V_T7_1_STATIC_C_PLL_BYPASS(x) ((x) << S_T7_1_STATIC_C_PLL_BYPASS)
15279 #define F_T7_1_STATIC_C_PLL_BYPASS    V_T7_1_STATIC_C_PLL_BYPASS(1U)
15285 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
15286 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
15290 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
15291 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
15295 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
15296 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
15300 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
15301 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
15305 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
15306 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
15310 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
15311 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
15317 #define V_STATIC_C_PLL_SSMF(x) ((x) << S_STATIC_C_PLL_SSMF)
15318 #define G_STATIC_C_PLL_SSMF(x) (((x) >> S_STATIC_C_PLL_SSMF) & M_STATIC_C_PLL_SSMF)
15322 #define V_STATIC_C_PLL_SSMD(x) ((x) << S_STATIC_C_PLL_SSMD)
15323 #define G_STATIC_C_PLL_SSMD(x) (((x) >> S_STATIC_C_PLL_SSMD) & M_STATIC_C_PLL_SSMD)
15325 #define S_STATIC_C_PLL_SSDS    1
15326 #define V_STATIC_C_PLL_SSDS(x) ((x) << S_STATIC_C_PLL_SSDS)
15327 #define F_STATIC_C_PLL_SSDS    V_STATIC_C_PLL_SSDS(1U)
15330 #define V_STATIC_C_PLL_SSE(x) ((x) << S_STATIC_C_PLL_SSE)
15331 #define F_STATIC_C_PLL_SSE    V_STATIC_C_PLL_SSE(1U)
15337 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
15338 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
15342 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
15343 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
15347 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
15348 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
15352 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
15353 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
15357 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
15358 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
15362 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
15363 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
15368 #define V_STATIC_U_DFS_ACK(x) ((x) << S_STATIC_U_DFS_ACK)
15369 #define F_STATIC_U_DFS_ACK    V_STATIC_U_DFS_ACK(1U)
15372 #define V_STATIC_C_DFS_ACK(x) ((x) << S_STATIC_C_DFS_ACK)
15373 #define F_STATIC_C_DFS_ACK    V_STATIC_C_DFS_ACK(1U)
15377 #define V_STATIC_U_DFS_DIVFI(x) ((x) << S_STATIC_U_DFS_DIVFI)
15378 #define G_STATIC_U_DFS_DIVFI(x) (((x) >> S_STATIC_U_DFS_DIVFI) & M_STATIC_U_DFS_DIVFI)
15381 #define V_STATIC_U_DFS_NEWDIV(x) ((x) << S_STATIC_U_DFS_NEWDIV)
15382 #define F_STATIC_U_DFS_NEWDIV    V_STATIC_U_DFS_NEWDIV(1U)
15385 #define V_T7_STATIC_U_DFS_ENABLE(x) ((x) << S_T7_STATIC_U_DFS_ENABLE)
15386 #define F_T7_STATIC_U_DFS_ENABLE    V_T7_STATIC_U_DFS_ENABLE(1U)
15390 #define V_STATIC_C_DFS_DIVFI(x) ((x) << S_STATIC_C_DFS_DIVFI)
15391 #define G_STATIC_C_DFS_DIVFI(x) (((x) >> S_STATIC_C_DFS_DIVFI) & M_STATIC_C_DFS_DIVFI)
15393 #define S_STATIC_C_DFS_NEWDIV    1
15394 #define V_STATIC_C_DFS_NEWDIV(x) ((x) << S_STATIC_C_DFS_NEWDIV)
15395 #define F_STATIC_C_DFS_NEWDIV    V_STATIC_C_DFS_NEWDIV(1U)
15400 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
15401 #define F_STATIC_M_PLL_RESET    V_STATIC_M_PLL_RESET(1U)
15404 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
15405 #define F_STATIC_M_PLL_SLEEP    V_STATIC_M_PLL_SLEEP(1U)
15408 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
15409 #define F_STATIC_M_PLL_BYPASS    V_STATIC_M_PLL_BYPASS(1U)
15412 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
15413 #define F_STATIC_MPLL_CLK_SEL    V_STATIC_MPLL_CLK_SEL(1U)
15416 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
15417 #define F_STATIC_U_PLL_SLEEP    V_STATIC_U_PLL_SLEEP(1U)
15420 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
15421 #define F_STATIC_C_PLL_SLEEP    V_STATIC_C_PLL_SLEEP(1U)
15425 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
15426 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
15429 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
15430 #define F_STATIC_LVDS_CLKOUT_EN    V_STATIC_LVDS_CLKOUT_EN(1U)
15434 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
15435 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
15439 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
15440 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
15443 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
15444 #define F_EXPHYCLK_SEL_EN    V_EXPHYCLK_SEL_EN(1U)
15448 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
15449 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
15452 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
15453 #define F_STATIC_U_PLL_BYPASS    V_STATIC_U_PLL_BYPASS(1U)
15456 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
15457 #define F_STATIC_C_PLL_BYPASS    V_STATIC_C_PLL_BYPASS(1U)
15460 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
15461 #define F_STATIC_KR_PLL_BYPASS    V_STATIC_KR_PLL_BYPASS(1U)
15464 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
15465 #define F_STATIC_KX_PLL_BYPASS    V_STATIC_KX_PLL_BYPASS(1U)
15469 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
15470 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
15474 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
15475 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
15479 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
15480 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
15483 #define V_T7_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_T7_STATIC_LVDS_CLKOUT_EN)
15484 #define F_T7_STATIC_LVDS_CLKOUT_EN    V_T7_STATIC_LVDS_CLKOUT_EN(1U)
15487 #define V_T7_EXPHYCLK_SEL_EN(x) ((x) << S_T7_EXPHYCLK_SEL_EN)
15488 #define F_T7_EXPHYCLK_SEL_EN    V_T7_EXPHYCLK_SEL_EN(1U)
15493 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
15494 #define F_M_OCLK_MUXSEL    V_M_OCLK_MUXSEL(1U)
15498 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
15499 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
15503 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
15504 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
15508 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
15509 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
15513 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
15514 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
15518 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
15519 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
15523 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
15524 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
15528 #define V_T6_P_OCLK_MUXSEL(x) ((x) << S_T6_P_OCLK_MUXSEL)
15529 #define G_T6_P_OCLK_MUXSEL(x) (((x) >> S_T6_P_OCLK_MUXSEL) & M_T6_P_OCLK_MUXSEL)
15543 #define V_COUNTER1(x) ((x) << S_COUNTER1)
15544 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
15548 #define V_COUNTER0(x) ((x) << S_COUNTER0)
15549 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
15555 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
15556 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
15561 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
15562 #define F_DBG_TRACE_OPERATE_WITH_TRG    V_DBG_TRACE_OPERATE_WITH_TRG(1U)
15565 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
15566 #define F_DBG_TRACE_OPERATE_EN    V_DBG_TRACE_OPERATE_EN(1U)
15569 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
15570 #define F_DBG_OPERATE_INDV_COMBINED    V_DBG_OPERATE_INDV_COMBINED(1U)
15573 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
15574 #define F_DBG_OPERATE_ORDER_OF_TRIGGER    V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
15576 #define S_DBG_OPERATE_SGL_DBL_TRIGGER    1
15577 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
15578 #define F_DBG_OPERATE_SGL_DBL_TRIGGER    V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
15581 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
15582 #define F_DBG_OPERATE0_OR_1    V_DBG_OPERATE0_OR_1(1U)
15588 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
15589 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
15593 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
15594 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
15596 #define S_RD_EN1    1
15597 #define V_RD_EN1(x) ((x) << S_RD_EN1)
15598 #define F_RD_EN1    V_RD_EN1(1U)
15601 #define V_RD_EN0(x) ((x) << S_RD_EN0)
15602 #define F_RD_EN0    V_RD_EN0(1U)
15606 #define V_T5_RD_ADDR1(x) ((x) << S_T5_RD_ADDR1)
15607 #define G_T5_RD_ADDR1(x) (((x) >> S_T5_RD_ADDR1) & M_T5_RD_ADDR1)
15611 #define V_T5_RD_ADDR0(x) ((x) << S_T5_RD_ADDR0)
15612 #define G_T5_RD_ADDR0(x) (((x) >> S_T5_RD_ADDR0) & M_T5_RD_ADDR0)
15618 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
15619 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
15623 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
15624 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
15628 #define V_T5_WR_POINTER_ADDR1(x) ((x) << S_T5_WR_POINTER_ADDR1)
15629 #define G_T5_WR_POINTER_ADDR1(x) (((x) >> S_T5_WR_POINTER_ADDR1) & M_T5_WR_POINTER_ADDR1)
15633 #define V_T5_WR_POINTER_ADDR0(x) ((x) << S_T5_WR_POINTER_ADDR0)
15634 #define G_T5_WR_POINTER_ADDR0(x) (((x) >> S_T5_WR_POINTER_ADDR0) & M_T5_WR_POINTER_ADDR0)
15642 #define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
15643 #define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
15645 #define S_UNQ0    1
15647 #define V_UNQ0(x) ((x) << S_UNQ0)
15648 #define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
15651 #define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
15652 #define F_FUSE_DONE_SENSE    V_FUSE_DONE_SENSE(1U)
15657 #define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
15658 #define F_MCIMPED1_OUT    V_MCIMPED1_OUT(1U)
15661 #define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
15662 #define F_MCIMPED2_OUT    V_MCIMPED2_OUT(1U)
15666 #define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
15667 #define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
15670 #define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
15671 #define F_TVSENSE_OUTPUTVALID    V_TVSENSE_OUTPUTVALID(1U)
15674 #define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
15675 #define F_TVSENSE_SLEEP    V_TVSENSE_SLEEP(1U)
15678 #define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
15679 #define F_TVSENSE_SENSV    V_TVSENSE_SENSV(1U)
15682 #define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
15683 #define F_TVSENSE_RST    V_TVSENSE_RST(1U)
15687 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
15688 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
15691 #define V_T6_TVSENSE_SLEEP(x) ((x) << S_T6_TVSENSE_SLEEP)
15692 #define F_T6_TVSENSE_SLEEP    V_T6_TVSENSE_SLEEP(1U)
15695 #define V_T6_TVSENSE_SENSV(x) ((x) << S_T6_TVSENSE_SENSV)
15696 #define F_T6_TVSENSE_SENSV    V_T6_TVSENSE_SENSV(1U)
15699 #define V_T6_TVSENSE_RST(x) ((x) << S_T6_TVSENSE_RST)
15700 #define F_T6_TVSENSE_RST    V_T6_TVSENSE_RST(1U)
15706 #define V_PVT_TRIMO(x) ((x) << S_PVT_TRIMO)
15707 #define G_PVT_TRIMO(x) (((x) >> S_PVT_TRIMO) & M_PVT_TRIMO)
15711 #define V_PVT_TRIMG(x) ((x) << S_PVT_TRIMG)
15712 #define G_PVT_TRIMG(x) (((x) >> S_PVT_TRIMG) & M_PVT_TRIMG)
15715 #define V_PVT_VSAMPLE(x) ((x) << S_PVT_VSAMPLE)
15716 #define F_PVT_VSAMPLE    V_PVT_VSAMPLE(1U)
15720 #define V_PVT_PSAMPLE(x) ((x) << S_PVT_PSAMPLE)
15721 #define G_PVT_PSAMPLE(x) (((x) >> S_PVT_PSAMPLE) & M_PVT_PSAMPLE)
15724 #define V_PVT_ENA(x) ((x) << S_PVT_ENA)
15725 #define F_PVT_ENA    V_PVT_ENA(1U)
15728 #define V_PVT_RESET(x) ((x) << S_PVT_RESET)
15729 #define F_PVT_RESET    V_PVT_RESET(1U)
15733 #define V_PVT_DIV(x) ((x) << S_PVT_DIV)
15734 #define G_PVT_DIV(x) (((x) >> S_PVT_DIV) & M_PVT_DIV)
15739 #define S_PVT_DATA_OUT    1
15741 #define V_PVT_DATA_OUT(x) ((x) << S_PVT_DATA_OUT)
15742 #define G_PVT_DATA_OUT(x) (((x) >> S_PVT_DATA_OUT) & M_PVT_DATA_OUT)
15745 #define V_PVT_DATA_VALID(x) ((x) << S_PVT_DATA_VALID)
15746 #define F_PVT_DATA_VALID    V_PVT_DATA_VALID(1U)
15752 #define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
15753 #define F_DBG_FEENABLE    V_DBG_FEENABLE(1U)
15757 #define V_DBG_FEF(x) ((x) << S_DBG_FEF)
15758 #define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
15761 #define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
15762 #define F_DBG_FEMIMICN    V_DBG_FEMIMICN(1U)
15765 #define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
15766 #define F_DBG_FEGATEC    V_DBG_FEGATEC(1U)
15769 #define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
15770 #define F_DBG_FEPROGP    V_DBG_FEPROGP(1U)
15773 #define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
15774 #define F_DBG_FEREADCLK    V_DBG_FEREADCLK(1U)
15778 #define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
15779 #define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
15783 #define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
15784 #define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
15790 #define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
15791 #define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
15795 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
15796 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
15802 #define V_STATIC_M_PLL_MULTFRAC(x) ((x) << S_STATIC_M_PLL_MULTFRAC)
15803 #define G_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_STATIC_M_PLL_MULTFRAC) & M_STATIC_M_PLL_MULTFRAC)
15807 #define V_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_STATIC_M_PLL_FFSLEWRATE)
15808 #define G_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_M_PLL_FFSLEWRATE) & M_STATIC_M_PLL_FFSLEWRATE)
15814 #define V_STATIC_M0_PLL_RANGE(x) ((x) << S_STATIC_M0_PLL_RANGE)
15815 #define G_STATIC_M0_PLL_RANGE(x) (((x) >> S_STATIC_M0_PLL_RANGE) & M_STATIC_M0_PLL_RANGE)
15819 #define V_STATIC_M0_PLL_DIVQ(x) ((x) << S_STATIC_M0_PLL_DIVQ)
15820 #define G_STATIC_M0_PLL_DIVQ(x) (((x) >> S_STATIC_M0_PLL_DIVQ) & M_STATIC_M0_PLL_DIVQ)
15824 #define V_STATIC_M0_PLL_DIVFI(x) ((x) << S_STATIC_M0_PLL_DIVFI)
15825 #define G_STATIC_M0_PLL_DIVFI(x) (((x) >> S_STATIC_M0_PLL_DIVFI) & M_STATIC_M0_PLL_DIVFI)
15829 #define V_STATIC_M0_PLL_DIVR(x) ((x) << S_STATIC_M0_PLL_DIVR)
15830 #define G_STATIC_M0_PLL_DIVR(x) (((x) >> S_STATIC_M0_PLL_DIVR) & M_STATIC_M0_PLL_DIVR)
15832 #define S_STATIC_M0_PLL_BYPASS    1
15833 #define V_STATIC_M0_PLL_BYPASS(x) ((x) << S_STATIC_M0_PLL_BYPASS)
15834 #define F_STATIC_M0_PLL_BYPASS    V_STATIC_M0_PLL_BYPASS(1U)
15837 #define V_STATIC_M0_PLL_RESET(x) ((x) << S_STATIC_M0_PLL_RESET)
15838 #define F_STATIC_M0_PLL_RESET    V_STATIC_M0_PLL_RESET(1U)
15843 #define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
15844 #define F_T5_STATIC_M_PLL_DCO_BYPASS    V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
15848 #define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
15849 #define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
15852 #define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
15853 #define F_T5_STATIC_M_PLL_FFENABLE    V_T5_STATIC_M_PLL_FFENABLE(1U)
15856 #define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
15857 #define F_T5_STATIC_M_PLL_STOPCLKB    V_T5_STATIC_M_PLL_STOPCLKB(1U)
15860 #define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
15861 #define F_T5_STATIC_M_PLL_STOPCLKA    V_T5_STATIC_M_PLL_STOPCLKA(1U)
15864 #define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
15865 #define F_T5_STATIC_M_PLL_SLEEP    V_T5_STATIC_M_PLL_SLEEP(1U)
15868 #define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
15869 #define F_T5_STATIC_M_PLL_BYPASS    V_T5_STATIC_M_PLL_BYPASS(1U)
15873 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
15874 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
15880 #define V_T6_STATIC_M_PLL_PREDIV(x) ((x) << S_T6_STATIC_M_PLL_PREDIV)
15881 #define G_T6_STATIC_M_PLL_PREDIV(x) (((x) >> S_T6_STATIC_M_PLL_PREDIV) & M_T6_STATIC_M_PLL_PREDIV)
15884 #define V_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_STATIC_M_PLL_DCO_BYPASS)
15885 #define F_STATIC_M_PLL_DCO_BYPASS    V_STATIC_M_PLL_DCO_BYPASS(1U)
15889 #define V_STATIC_M_PLL_SDORDER(x) ((x) << S_STATIC_M_PLL_SDORDER)
15890 #define G_STATIC_M_PLL_SDORDER(x) (((x) >> S_STATIC_M_PLL_SDORDER) & M_STATIC_M_PLL_SDORDER)
15893 #define V_STATIC_M_PLL_FFENABLE(x) ((x) << S_STATIC_M_PLL_FFENABLE)
15894 #define F_STATIC_M_PLL_FFENABLE    V_STATIC_M_PLL_FFENABLE(1U)
15897 #define V_STATIC_M_PLL_STOPCLKB(x) ((x) << S_STATIC_M_PLL_STOPCLKB)
15898 #define F_STATIC_M_PLL_STOPCLKB    V_STATIC_M_PLL_STOPCLKB(1U)
15901 #define V_STATIC_M_PLL_STOPCLKA(x) ((x) << S_STATIC_M_PLL_STOPCLKA)
15902 #define F_STATIC_M_PLL_STOPCLKA    V_STATIC_M_PLL_STOPCLKA(1U)
15905 #define V_T6_STATIC_M_PLL_SLEEP(x) ((x) << S_T6_STATIC_M_PLL_SLEEP)
15906 #define F_T6_STATIC_M_PLL_SLEEP    V_T6_STATIC_M_PLL_SLEEP(1U)
15909 #define V_T6_STATIC_M_PLL_BYPASS(x) ((x) << S_T6_STATIC_M_PLL_BYPASS)
15910 #define F_T6_STATIC_M_PLL_BYPASS    V_T6_STATIC_M_PLL_BYPASS(1U)
15914 #define V_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_STATIC_M_PLL_LOCKTUNE)
15915 #define G_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_STATIC_M_PLL_LOCKTUNE) & M_STATIC_M_PLL_LOCKTUNE)
15920 #define V_T7_STATIC_SWMC1RST_(x) ((x) << S_T7_STATIC_SWMC1RST_)
15921 #define F_T7_STATIC_SWMC1RST_    V_T7_STATIC_SWMC1RST_(1U)
15924 #define V_T7_STATIC_SWMC1CFGRST_(x) ((x) << S_T7_STATIC_SWMC1CFGRST_)
15925 #define F_T7_STATIC_SWMC1CFGRST_    V_T7_STATIC_SWMC1CFGRST_(1U)
15928 #define V_T7_STATIC_PHY0RECRST_(x) ((x) << S_T7_STATIC_PHY0RECRST_)
15929 #define F_T7_STATIC_PHY0RECRST_    V_T7_STATIC_PHY0RECRST_(1U)
15932 #define V_T7_STATIC_PHY1RECRST_(x) ((x) << S_T7_STATIC_PHY1RECRST_)
15933 #define F_T7_STATIC_PHY1RECRST_    V_T7_STATIC_PHY1RECRST_(1U)
15936 #define V_T7_STATIC_SWMC0RST_(x) ((x) << S_T7_STATIC_SWMC0RST_)
15937 #define F_T7_STATIC_SWMC0RST_    V_T7_STATIC_SWMC0RST_(1U)
15940 #define V_T7_STATIC_SWMC0CFGRST_(x) ((x) << S_T7_STATIC_SWMC0CFGRST_)
15941 #define F_T7_STATIC_SWMC0CFGRST_    V_T7_STATIC_SWMC0CFGRST_(1U)
15945 #define V_STATIC_M0_PLL_SSMF(x) ((x) << S_STATIC_M0_PLL_SSMF)
15946 #define G_STATIC_M0_PLL_SSMF(x) (((x) >> S_STATIC_M0_PLL_SSMF) & M_STATIC_M0_PLL_SSMF)
15950 #define V_STATIC_M0_PLL_SSMD(x) ((x) << S_STATIC_M0_PLL_SSMD)
15951 #define G_STATIC_M0_PLL_SSMD(x) (((x) >> S_STATIC_M0_PLL_SSMD) & M_STATIC_M0_PLL_SSMD)
15953 #define S_STATIC_M0_PLL_SSDS    1
15954 #define V_STATIC_M0_PLL_SSDS(x) ((x) << S_STATIC_M0_PLL_SSDS)
15955 #define F_STATIC_M0_PLL_SSDS    V_STATIC_M0_PLL_SSDS(1U)
15958 #define V_STATIC_M0_PLL_SSE(x) ((x) << S_STATIC_M0_PLL_SSE)
15959 #define F_STATIC_M0_PLL_SSE    V_STATIC_M0_PLL_SSE(1U)
15965 #define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
15966 #define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
15970 #define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
15971 #define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
15975 #define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
15976 #define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
15980 #define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
15981 #define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
15985 #define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
15986 #define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
15990 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
15991 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
15997 #define V_STATIC_M_PLL_MULTPRE(x) ((x) << S_STATIC_M_PLL_MULTPRE)
15998 #define G_STATIC_M_PLL_MULTPRE(x) (((x) >> S_STATIC_M_PLL_MULTPRE) & M_STATIC_M_PLL_MULTPRE)
16001 #define V_STATIC_M_PLL_LOCKSEL(x) ((x) << S_STATIC_M_PLL_LOCKSEL)
16002 #define F_STATIC_M_PLL_LOCKSEL    V_STATIC_M_PLL_LOCKSEL(1U)
16006 #define V_STATIC_M_PLL_FFTUNE(x) ((x) << S_STATIC_M_PLL_FFTUNE)
16007 #define G_STATIC_M_PLL_FFTUNE(x) (((x) >> S_STATIC_M_PLL_FFTUNE) & M_STATIC_M_PLL_FFTUNE)
16011 #define V_STATIC_M_PLL_RANGEPRE(x) ((x) << S_STATIC_M_PLL_RANGEPRE)
16012 #define G_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_STATIC_M_PLL_RANGEPRE) & M_STATIC_M_PLL_RANGEPRE)
16016 #define V_T6_STATIC_M_PLL_RANGEB(x) ((x) << S_T6_STATIC_M_PLL_RANGEB)
16017 #define G_T6_STATIC_M_PLL_RANGEB(x) (((x) >> S_T6_STATIC_M_PLL_RANGEB) & M_T6_STATIC_M_PLL_RANGEB)
16021 #define V_T6_STATIC_M_PLL_RANGEA(x) ((x) << S_T6_STATIC_M_PLL_RANGEA)
16022 #define G_T6_STATIC_M_PLL_RANGEA(x) (((x) >> S_T6_STATIC_M_PLL_RANGEA) & M_T6_STATIC_M_PLL_RANGEA)
16028 #define V_STATIC_MAC_PLL_RANGE(x) ((x) << S_STATIC_MAC_PLL_RANGE)
16029 #define G_STATIC_MAC_PLL_RANGE(x) (((x) >> S_STATIC_MAC_PLL_RANGE) & M_STATIC_MAC_PLL_RANGE)
16033 #define V_STATIC_MAC_PLL_DIVQ(x) ((x) << S_STATIC_MAC_PLL_DIVQ)
16034 #define G_STATIC_MAC_PLL_DIVQ(x) (((x) >> S_STATIC_MAC_PLL_DIVQ) & M_STATIC_MAC_PLL_DIVQ)
16038 #define V_STATIC_MAC_PLL_DIVFI(x) ((x) << S_STATIC_MAC_PLL_DIVFI)
16039 #define G_STATIC_MAC_PLL_DIVFI(x) (((x) >> S_STATIC_MAC_PLL_DIVFI) & M_STATIC_MAC_PLL_DIVFI)
16043 #define V_STATIC_MAC_PLL_DIVR(x) ((x) << S_STATIC_MAC_PLL_DIVR)
16044 #define G_STATIC_MAC_PLL_DIVR(x) (((x) >> S_STATIC_MAC_PLL_DIVR) & M_STATIC_MAC_PLL_DIVR)
16046 #define S_STATIC_MAC_PLL_BYPASS    1
16047 #define V_STATIC_MAC_PLL_BYPASS(x) ((x) << S_STATIC_MAC_PLL_BYPASS)
16048 #define F_STATIC_MAC_PLL_BYPASS    V_STATIC_MAC_PLL_BYPASS(1U)
16051 #define V_STATIC_MAC_PLL_RESET(x) ((x) << S_STATIC_MAC_PLL_RESET)
16052 #define F_STATIC_MAC_PLL_RESET    V_STATIC_MAC_PLL_RESET(1U)
16060 #define V_STATIC_MAC_PLL_SSMF(x) ((x) << S_STATIC_MAC_PLL_SSMF)
16061 #define G_STATIC_MAC_PLL_SSMF(x) (((x) >> S_STATIC_MAC_PLL_SSMF) & M_STATIC_MAC_PLL_SSMF)
16065 #define V_STATIC_MAC_PLL_SSMD(x) ((x) << S_STATIC_MAC_PLL_SSMD)
16066 #define G_STATIC_MAC_PLL_SSMD(x) (((x) >> S_STATIC_MAC_PLL_SSMD) & M_STATIC_MAC_PLL_SSMD)
16068 #define S_STATIC_MAC_PLL_SSDS    1
16069 #define V_STATIC_MAC_PLL_SSDS(x) ((x) << S_STATIC_MAC_PLL_SSDS)
16070 #define F_STATIC_MAC_PLL_SSDS    V_STATIC_MAC_PLL_SSDS(1U)
16073 #define V_STATIC_MAC_PLL_SSE(x) ((x) << S_STATIC_MAC_PLL_SSE)
16074 #define F_STATIC_MAC_PLL_SSE    V_STATIC_MAC_PLL_SSE(1U)
16080 #define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
16081 #define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
16084 #define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
16085 #define F_T5_STATIC_M_PLL_RESET    V_T5_STATIC_M_PLL_RESET(1U)
16088 #define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
16089 #define F_T5_STATIC_MPLL_REFCLK_SEL    V_T5_STATIC_MPLL_REFCLK_SEL(1U)
16093 #define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
16094 #define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
16098 #define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
16099 #define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
16103 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
16104 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
16110 #define V_STATIC_M_PLL_VCVTUNE(x) ((x) << S_STATIC_M_PLL_VCVTUNE)
16111 #define G_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_STATIC_M_PLL_VCVTUNE) & M_STATIC_M_PLL_VCVTUNE)
16114 #define V_T6_STATIC_M_PLL_RESET(x) ((x) << S_T6_STATIC_M_PLL_RESET)
16115 #define F_T6_STATIC_M_PLL_RESET    V_T6_STATIC_M_PLL_RESET(1U)
16118 #define V_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_STATIC_MPLL_REFCLK_SEL)
16119 #define F_STATIC_MPLL_REFCLK_SEL    V_STATIC_MPLL_REFCLK_SEL(1U)
16123 #define V_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_M_PLL_LFTUNE_32_40)
16124 #define G_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_M_PLL_LFTUNE_32_40) & M_STATIC_M_PLL_LFTUNE_32_40)
16128 #define V_T6_STATIC_M_PLL_MULT(x) ((x) << S_T6_STATIC_M_PLL_MULT)
16129 #define G_T6_STATIC_M_PLL_MULT(x) (((x) >> S_T6_STATIC_M_PLL_MULT) & M_T6_STATIC_M_PLL_MULT)
16135 #define V_STATIC_ARM_PLL_RANGE(x) ((x) << S_STATIC_ARM_PLL_RANGE)
16136 #define G_STATIC_ARM_PLL_RANGE(x) (((x) >> S_STATIC_ARM_PLL_RANGE) & M_STATIC_ARM_PLL_RANGE)
16140 #define V_STATIC_ARM_PLL_DIVQ(x) ((x) << S_STATIC_ARM_PLL_DIVQ)
16141 #define G_STATIC_ARM_PLL_DIVQ(x) (((x) >> S_STATIC_ARM_PLL_DIVQ) & M_STATIC_ARM_PLL_DIVQ)
16145 #define V_STATIC_ARM_PLL_DIVFI(x) ((x) << S_STATIC_ARM_PLL_DIVFI)
16146 #define G_STATIC_ARM_PLL_DIVFI(x) (((x) >> S_STATIC_ARM_PLL_DIVFI) & M_STATIC_ARM_PLL_DIVFI)
16150 #define V_STATIC_ARM_PLL_DIVR(x) ((x) << S_STATIC_ARM_PLL_DIVR)
16151 #define G_STATIC_ARM_PLL_DIVR(x) (((x) >> S_STATIC_ARM_PLL_DIVR) & M_STATIC_ARM_PLL_DIVR)
16153 #define S_STATIC_ARM_PLL_BYPASS    1
16154 #define V_STATIC_ARM_PLL_BYPASS(x) ((x) << S_STATIC_ARM_PLL_BYPASS)
16155 #define F_STATIC_ARM_PLL_BYPASS    V_STATIC_ARM_PLL_BYPASS(1U)
16158 #define V_STATIC_ARM_PLL_RESET(x) ((x) << S_STATIC_ARM_PLL_RESET)
16159 #define F_STATIC_ARM_PLL_RESET    V_STATIC_ARM_PLL_RESET(1U)
16164 #define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
16165 #define F_T5_STATIC_PHY0RECRST_    V_T5_STATIC_PHY0RECRST_(1U)
16168 #define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
16169 #define F_T5_STATIC_PHY1RECRST_    V_T5_STATIC_PHY1RECRST_(1U)
16172 #define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
16173 #define F_T5_STATIC_SWMC0RST_    V_T5_STATIC_SWMC0RST_(1U)
16176 #define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
16177 #define F_T5_STATIC_SWMC0CFGRST_    V_T5_STATIC_SWMC0CFGRST_(1U)
16179 #define S_T5_STATIC_SWMC1RST_    1
16180 #define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
16181 #define F_T5_STATIC_SWMC1RST_    V_T5_STATIC_SWMC1RST_(1U)
16184 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
16185 #define F_T5_STATIC_SWMC1CFGRST_    V_T5_STATIC_SWMC1CFGRST_(1U)
16190 #define V_STATIC_M_PLL_DIVCHANGE(x) ((x) << S_STATIC_M_PLL_DIVCHANGE)
16191 #define F_STATIC_M_PLL_DIVCHANGE    V_STATIC_M_PLL_DIVCHANGE(1U)
16194 #define V_STATIC_M_PLL_FRAMESTOP(x) ((x) << S_STATIC_M_PLL_FRAMESTOP)
16195 #define F_STATIC_M_PLL_FRAMESTOP    V_STATIC_M_PLL_FRAMESTOP(1U)
16198 #define V_STATIC_M_PLL_FASTSTOP(x) ((x) << S_STATIC_M_PLL_FASTSTOP)
16199 #define F_STATIC_M_PLL_FASTSTOP    V_STATIC_M_PLL_FASTSTOP(1U)
16202 #define V_STATIC_M_PLL_FFBYPASS(x) ((x) << S_STATIC_M_PLL_FFBYPASS)
16203 #define F_STATIC_M_PLL_FFBYPASS    V_STATIC_M_PLL_FFBYPASS(1U)
16207 #define V_STATIC_M_PLL_STARTUP(x) ((x) << S_STATIC_M_PLL_STARTUP)
16208 #define G_STATIC_M_PLL_STARTUP(x) (((x) >> S_STATIC_M_PLL_STARTUP) & M_STATIC_M_PLL_STARTUP)
16212 #define V_STATIC_M_PLL_VREGTUNE(x) ((x) << S_STATIC_M_PLL_VREGTUNE)
16213 #define G_STATIC_M_PLL_VREGTUNE(x) (((x) >> S_STATIC_M_PLL_VREGTUNE) & M_STATIC_M_PLL_VREGTUNE)
16216 #define V_STATIC_PHY0RECRST_(x) ((x) << S_STATIC_PHY0RECRST_)
16217 #define F_STATIC_PHY0RECRST_    V_STATIC_PHY0RECRST_(1U)
16220 #define V_STATIC_PHY1RECRST_(x) ((x) << S_STATIC_PHY1RECRST_)
16221 #define F_STATIC_PHY1RECRST_    V_STATIC_PHY1RECRST_(1U)
16224 #define V_STATIC_SWMC0RST_(x) ((x) << S_STATIC_SWMC0RST_)
16225 #define F_STATIC_SWMC0RST_    V_STATIC_SWMC0RST_(1U)
16228 #define V_STATIC_SWMC0CFGRST_(x) ((x) << S_STATIC_SWMC0CFGRST_)
16229 #define F_STATIC_SWMC0CFGRST_    V_STATIC_SWMC0CFGRST_(1U)
16231 #define S_STATIC_SWMC1RST_    1
16232 #define V_STATIC_SWMC1RST_(x) ((x) << S_STATIC_SWMC1RST_)
16233 #define F_STATIC_SWMC1RST_    V_STATIC_SWMC1RST_(1U)
16236 #define V_STATIC_SWMC1CFGRST_(x) ((x) << S_STATIC_SWMC1CFGRST_)
16237 #define F_STATIC_SWMC1CFGRST_    V_STATIC_SWMC1CFGRST_(1U)
16243 #define V_STATIC_ARM_PLL_SSMF(x) ((x) << S_STATIC_ARM_PLL_SSMF)
16244 #define G_STATIC_ARM_PLL_SSMF(x) (((x) >> S_STATIC_ARM_PLL_SSMF) & M_STATIC_ARM_PLL_SSMF)
16248 #define V_STATIC_ARM_PLL_SSMD(x) ((x) << S_STATIC_ARM_PLL_SSMD)
16249 #define G_STATIC_ARM_PLL_SSMD(x) (((x) >> S_STATIC_ARM_PLL_SSMD) & M_STATIC_ARM_PLL_SSMD)
16251 #define S_STATIC_ARM_PLL_SSDS    1
16252 #define V_STATIC_ARM_PLL_SSDS(x) ((x) << S_STATIC_ARM_PLL_SSDS)
16253 #define F_STATIC_ARM_PLL_SSDS    V_STATIC_ARM_PLL_SSDS(1U)
16256 #define V_STATIC_ARM_PLL_SSE(x) ((x) << S_STATIC_ARM_PLL_SSE)
16257 #define F_STATIC_ARM_PLL_SSE    V_STATIC_ARM_PLL_SSE(1U)
16263 #define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
16264 #define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
16268 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
16269 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
16275 #define V_STATIC_C_PLL_MULTFRAC(x) ((x) << S_STATIC_C_PLL_MULTFRAC)
16276 #define G_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_STATIC_C_PLL_MULTFRAC) & M_STATIC_C_PLL_MULTFRAC)
16280 #define V_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_STATIC_C_PLL_FFSLEWRATE)
16281 #define G_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_C_PLL_FFSLEWRATE) & M_STATIC_C_PLL_FFSLEWRATE)
16287 #define V_STATIC_USB_PLL_RANGE(x) ((x) << S_STATIC_USB_PLL_RANGE)
16288 #define G_STATIC_USB_PLL_RANGE(x) (((x) >> S_STATIC_USB_PLL_RANGE) & M_STATIC_USB_PLL_RANGE)
16292 #define V_STATIC_USB_PLL_DIVQ(x) ((x) << S_STATIC_USB_PLL_DIVQ)
16293 #define G_STATIC_USB_PLL_DIVQ(x) (((x) >> S_STATIC_USB_PLL_DIVQ) & M_STATIC_USB_PLL_DIVQ)
16297 #define V_STATIC_USB_PLL_DIVFI(x) ((x) << S_STATIC_USB_PLL_DIVFI)
16298 #define G_STATIC_USB_PLL_DIVFI(x) (((x) >> S_STATIC_USB_PLL_DIVFI) & M_STATIC_USB_PLL_DIVFI)
16302 #define V_STATIC_USB_PLL_DIVR(x) ((x) << S_STATIC_USB_PLL_DIVR)
16303 #define G_STATIC_USB_PLL_DIVR(x) (((x) >> S_STATIC_USB_PLL_DIVR) & M_STATIC_USB_PLL_DIVR)
16305 #define S_STATIC_USB_PLL_BYPASS    1
16306 #define V_STATIC_USB_PLL_BYPASS(x) ((x) << S_STATIC_USB_PLL_BYPASS)
16307 #define F_STATIC_USB_PLL_BYPASS    V_STATIC_USB_PLL_BYPASS(1U)
16310 #define V_STATIC_USB_PLL_RESET(x) ((x) << S_STATIC_USB_PLL_RESET)
16311 #define F_STATIC_USB_PLL_RESET    V_STATIC_USB_PLL_RESET(1U)
16316 #define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
16317 #define F_T5_STATIC_C_PLL_DCO_BYPASS    V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
16321 #define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
16322 #define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
16325 #define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
16326 #define F_T5_STATIC_C_PLL_FFENABLE    V_T5_STATIC_C_PLL_FFENABLE(1U)
16329 #define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
16330 #define F_T5_STATIC_C_PLL_STOPCLKB    V_T5_STATIC_C_PLL_STOPCLKB(1U)
16333 #define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
16334 #define F_T5_STATIC_C_PLL_STOPCLKA    V_T5_STATIC_C_PLL_STOPCLKA(1U)
16337 #define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
16338 #define F_T5_STATIC_C_PLL_SLEEP    V_T5_STATIC_C_PLL_SLEEP(1U)
16341 #define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
16342 #define F_T5_STATIC_C_PLL_BYPASS    V_T5_STATIC_C_PLL_BYPASS(1U)
16346 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
16347 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
16353 #define V_T6_STATIC_C_PLL_PREDIV(x) ((x) << S_T6_STATIC_C_PLL_PREDIV)
16354 #define G_T6_STATIC_C_PLL_PREDIV(x) (((x) >> S_T6_STATIC_C_PLL_PREDIV) & M_T6_STATIC_C_PLL_PREDIV)
16358 #define V_STATIC_C_PLL_STARTUP(x) ((x) << S_STATIC_C_PLL_STARTUP)
16359 #define G_STATIC_C_PLL_STARTUP(x) (((x) >> S_STATIC_C_PLL_STARTUP) & M_STATIC_C_PLL_STARTUP)
16362 #define V_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_STATIC_C_PLL_DCO_BYPASS)
16363 #define F_STATIC_C_PLL_DCO_BYPASS    V_STATIC_C_PLL_DCO_BYPASS(1U)
16367 #define V_STATIC_C_PLL_SDORDER(x) ((x) << S_STATIC_C_PLL_SDORDER)
16368 #define G_STATIC_C_PLL_SDORDER(x) (((x) >> S_STATIC_C_PLL_SDORDER) & M_STATIC_C_PLL_SDORDER)
16371 #define V_STATIC_C_PLL_DIVCHANGE(x) ((x) << S_STATIC_C_PLL_DIVCHANGE)
16372 #define F_STATIC_C_PLL_DIVCHANGE    V_STATIC_C_PLL_DIVCHANGE(1U)
16375 #define V_STATIC_C_PLL_STOPCLKB(x) ((x) << S_STATIC_C_PLL_STOPCLKB)
16376 #define F_STATIC_C_PLL_STOPCLKB    V_STATIC_C_PLL_STOPCLKB(1U)
16379 #define V_STATIC_C_PLL_STOPCLKA(x) ((x) << S_STATIC_C_PLL_STOPCLKA)
16380 #define F_STATIC_C_PLL_STOPCLKA    V_STATIC_C_PLL_STOPCLKA(1U)
16383 #define V_T6_STATIC_C_PLL_SLEEP(x) ((x) << S_T6_STATIC_C_PLL_SLEEP)
16384 #define F_T6_STATIC_C_PLL_SLEEP    V_T6_STATIC_C_PLL_SLEEP(1U)
16387 #define V_T6_STATIC_C_PLL_BYPASS(x) ((x) << S_T6_STATIC_C_PLL_BYPASS)
16388 #define F_T6_STATIC_C_PLL_BYPASS    V_T6_STATIC_C_PLL_BYPASS(1U)
16392 #define V_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_STATIC_C_PLL_LOCKTUNE)
16393 #define G_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_STATIC_C_PLL_LOCKTUNE) & M_STATIC_C_PLL_LOCKTUNE)
16399 #define V_STATIC_USB_PLL_SSMF(x) ((x) << S_STATIC_USB_PLL_SSMF)
16400 #define G_STATIC_USB_PLL_SSMF(x) (((x) >> S_STATIC_USB_PLL_SSMF) & M_STATIC_USB_PLL_SSMF)
16404 #define V_STATIC_USB_PLL_SSMD(x) ((x) << S_STATIC_USB_PLL_SSMD)
16405 #define G_STATIC_USB_PLL_SSMD(x) (((x) >> S_STATIC_USB_PLL_SSMD) & M_STATIC_USB_PLL_SSMD)
16407 #define S_STATIC_USB_PLL_SSDS    1
16408 #define V_STATIC_USB_PLL_SSDS(x) ((x) << S_STATIC_USB_PLL_SSDS)
16409 #define F_STATIC_USB_PLL_SSDS    V_STATIC_USB_PLL_SSDS(1U)
16412 #define V_STATIC_USB_PLL_SSE(x) ((x) << S_STATIC_USB_PLL_SSE)
16413 #define F_STATIC_USB_PLL_SSE    V_STATIC_USB_PLL_SSE(1U)
16419 #define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
16420 #define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
16424 #define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
16425 #define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
16429 #define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
16430 #define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
16434 #define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
16435 #define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
16439 #define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
16440 #define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
16444 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
16445 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
16451 #define V_STATIC_C_PLL_MULTPRE(x) ((x) << S_STATIC_C_PLL_MULTPRE)
16452 #define G_STATIC_C_PLL_MULTPRE(x) (((x) >> S_STATIC_C_PLL_MULTPRE) & M_STATIC_C_PLL_MULTPRE)
16455 #define V_STATIC_C_PLL_LOCKSEL(x) ((x) << S_STATIC_C_PLL_LOCKSEL)
16456 #define F_STATIC_C_PLL_LOCKSEL    V_STATIC_C_PLL_LOCKSEL(1U)
16460 #define V_STATIC_C_PLL_FFTUNE(x) ((x) << S_STATIC_C_PLL_FFTUNE)
16461 #define G_STATIC_C_PLL_FFTUNE(x) (((x) >> S_STATIC_C_PLL_FFTUNE) & M_STATIC_C_PLL_FFTUNE)
16465 #define V_STATIC_C_PLL_RANGEPRE(x) ((x) << S_STATIC_C_PLL_RANGEPRE)
16466 #define G_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_STATIC_C_PLL_RANGEPRE) & M_STATIC_C_PLL_RANGEPRE)
16470 #define V_T6_STATIC_C_PLL_RANGEB(x) ((x) << S_T6_STATIC_C_PLL_RANGEB)
16471 #define G_T6_STATIC_C_PLL_RANGEB(x) (((x) >> S_T6_STATIC_C_PLL_RANGEB) & M_T6_STATIC_C_PLL_RANGEB)
16475 #define V_T6_STATIC_C_PLL_RANGEA(x) ((x) << S_T6_STATIC_C_PLL_RANGEA)
16476 #define G_T6_STATIC_C_PLL_RANGEA(x) (((x) >> S_T6_STATIC_C_PLL_RANGEA) & M_T6_STATIC_C_PLL_RANGEA)
16482 #define V_STATIC_XGPHY_PLL_RANGE(x) ((x) << S_STATIC_XGPHY_PLL_RANGE)
16483 #define G_STATIC_XGPHY_PLL_RANGE(x) (((x) >> S_STATIC_XGPHY_PLL_RANGE) & M_STATIC_XGPHY_PLL_RANGE)
16487 #define V_STATIC_XGPHY_PLL_DIVQ(x) ((x) << S_STATIC_XGPHY_PLL_DIVQ)
16488 #define G_STATIC_XGPHY_PLL_DIVQ(x) (((x) >> S_STATIC_XGPHY_PLL_DIVQ) & M_STATIC_XGPHY_PLL_DIVQ)
16492 #define V_STATIC_XGPHY_PLL_DIVFI(x) ((x) << S_STATIC_XGPHY_PLL_DIVFI)
16493 #define G_STATIC_XGPHY_PLL_DIVFI(x) (((x) >> S_STATIC_XGPHY_PLL_DIVFI) & M_STATIC_XGPHY_PLL_DIVFI)
16497 #define V_STATIC_XGPHY_PLL_DIVR(x) ((x) << S_STATIC_XGPHY_PLL_DIVR)
16498 #define G_STATIC_XGPHY_PLL_DIVR(x) (((x) >> S_STATIC_XGPHY_PLL_DIVR) & M_STATIC_XGPHY_PLL_DIVR)
16500 #define S_STATIC_XGPHY_PLL_BYPASS    1
16501 #define V_STATIC_XGPHY_PLL_BYPASS(x) ((x) << S_STATIC_XGPHY_PLL_BYPASS)
16502 #define F_STATIC_XGPHY_PLL_BYPASS    V_STATIC_XGPHY_PLL_BYPASS(1U)
16505 #define V_STATIC_XGPHY_PLL_RESET(x) ((x) << S_STATIC_XGPHY_PLL_RESET)
16506 #define F_STATIC_XGPHY_PLL_RESET    V_STATIC_XGPHY_PLL_RESET(1U)
16514 #define V_STATIC_XGPHY_PLL_SSMF(x) ((x) << S_STATIC_XGPHY_PLL_SSMF)
16515 #define G_STATIC_XGPHY_PLL_SSMF(x) (((x) >> S_STATIC_XGPHY_PLL_SSMF) & M_STATIC_XGPHY_PLL_SSMF)
16519 #define V_STATIC_XGPHY_PLL_SSMD(x) ((x) << S_STATIC_XGPHY_PLL_SSMD)
16520 #define G_STATIC_XGPHY_PLL_SSMD(x) (((x) >> S_STATIC_XGPHY_PLL_SSMD) & M_STATIC_XGPHY_PLL_SSMD)
16522 #define S_STATIC_XGPHY_PLL_SSDS    1
16523 #define V_STATIC_XGPHY_PLL_SSDS(x) ((x) << S_STATIC_XGPHY_PLL_SSDS)
16524 #define F_STATIC_XGPHY_PLL_SSDS    V_STATIC_XGPHY_PLL_SSDS(1U)
16527 #define V_STATIC_XGPHY_PLL_SSE(x) ((x) << S_STATIC_XGPHY_PLL_SSE)
16528 #define F_STATIC_XGPHY_PLL_SSE    V_STATIC_XGPHY_PLL_SSE(1U)
16534 #define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
16535 #define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
16539 #define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
16540 #define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
16544 #define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
16545 #define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
16549 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
16550 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
16555 #define V_STATIC_C_PLL_FFBYPASS(x) ((x) << S_STATIC_C_PLL_FFBYPASS)
16556 #define F_STATIC_C_PLL_FFBYPASS    V_STATIC_C_PLL_FFBYPASS(1U)
16559 #define V_STATIC_C_PLL_FASTSTOP(x) ((x) << S_STATIC_C_PLL_FASTSTOP)
16560 #define F_STATIC_C_PLL_FASTSTOP    V_STATIC_C_PLL_FASTSTOP(1U)
16563 #define V_STATIC_C_PLL_FRAMESTOP(x) ((x) << S_STATIC_C_PLL_FRAMESTOP)
16564 #define F_STATIC_C_PLL_FRAMESTOP    V_STATIC_C_PLL_FRAMESTOP(1U)
16568 #define V_STATIC_C_PLL_VCVTUNE(x) ((x) << S_STATIC_C_PLL_VCVTUNE)
16569 #define G_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_STATIC_C_PLL_VCVTUNE) & M_STATIC_C_PLL_VCVTUNE)
16573 #define V_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_C_PLL_LFTUNE_32_40)
16574 #define G_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_C_PLL_LFTUNE_32_40) & M_STATIC_C_PLL_LFTUNE_32_40)
16578 #define V_STATIC_C_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_C_PLL_PREDIV_CNF5)
16579 #define G_STATIC_C_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_C_PLL_PREDIV_CNF5) & M_STATIC_C_PLL_PREDIV_CNF5)
16583 #define V_T6_STATIC_C_PLL_MULT(x) ((x) << S_T6_STATIC_C_PLL_MULT)
16584 #define G_T6_STATIC_C_PLL_MULT(x) (((x) >> S_T6_STATIC_C_PLL_MULT) & M_T6_STATIC_C_PLL_MULT)
16589 #define V_STATIC_XGPBUS_SWRST_(x) ((x) << S_STATIC_XGPBUS_SWRST_)
16590 #define F_STATIC_XGPBUS_SWRST_    V_STATIC_XGPBUS_SWRST_(1U)
16594 #define V_STATIC_XGPBUS_PLL_RANGE(x) ((x) << S_STATIC_XGPBUS_PLL_RANGE)
16595 #define G_STATIC_XGPBUS_PLL_RANGE(x) (((x) >> S_STATIC_XGPBUS_PLL_RANGE) & M_STATIC_XGPBUS_PLL_RANGE)
16599 #define V_STATIC_XGPBUS_PLL_DIVQ(x) ((x) << S_STATIC_XGPBUS_PLL_DIVQ)
16600 #define G_STATIC_XGPBUS_PLL_DIVQ(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVQ) & M_STATIC_XGPBUS_PLL_DIVQ)
16604 #define V_STATIC_XGPBUS_PLL_DIVFI(x) ((x) << S_STATIC_XGPBUS_PLL_DIVFI)
16605 #define G_STATIC_XGPBUS_PLL_DIVFI(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVFI) & M_STATIC_XGPBUS_PLL_DIVFI)
16609 #define V_STATIC_XGPBUS_PLL_DIVR(x) ((x) << S_STATIC_XGPBUS_PLL_DIVR)
16610 #define G_STATIC_XGPBUS_PLL_DIVR(x) (((x) >> S_STATIC_XGPBUS_PLL_DIVR) & M_STATIC_XGPBUS_PLL_DIVR)
16612 #define S_STATIC_XGPBUS_PLL_BYPASS    1
16613 #define V_STATIC_XGPBUS_PLL_BYPASS(x) ((x) << S_STATIC_XGPBUS_PLL_BYPASS)
16614 #define F_STATIC_XGPBUS_PLL_BYPASS    V_STATIC_XGPBUS_PLL_BYPASS(1U)
16617 #define V_STATIC_XGPBUS_PLL_RESET(x) ((x) << S_STATIC_XGPBUS_PLL_RESET)
16618 #define F_STATIC_XGPBUS_PLL_RESET    V_STATIC_XGPBUS_PLL_RESET(1U)
16624 #define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
16625 #define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
16629 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
16630 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
16636 #define V_STATIC_U_PLL_MULTFRAC(x) ((x) << S_STATIC_U_PLL_MULTFRAC)
16637 #define G_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_STATIC_U_PLL_MULTFRAC) & M_STATIC_U_PLL_MULTFRAC)
16641 #define V_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_STATIC_U_PLL_FFSLEWRATE)
16642 #define G_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_STATIC_U_PLL_FFSLEWRATE) & M_STATIC_U_PLL_FFSLEWRATE)
16648 #define V_STATIC_XGPBUS_PLL_SSMF(x) ((x) << S_STATIC_XGPBUS_PLL_SSMF)
16649 #define G_STATIC_XGPBUS_PLL_SSMF(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMF) & M_STATIC_XGPBUS_PLL_SSMF)
16653 #define V_STATIC_XGPBUS_PLL_SSMD(x) ((x) << S_STATIC_XGPBUS_PLL_SSMD)
16654 #define G_STATIC_XGPBUS_PLL_SSMD(x) (((x) >> S_STATIC_XGPBUS_PLL_SSMD) & M_STATIC_XGPBUS_PLL_SSMD)
16656 #define S_STATIC_XGPBUS_PLL_SSDS    1
16657 #define V_STATIC_XGPBUS_PLL_SSDS(x) ((x) << S_STATIC_XGPBUS_PLL_SSDS)
16658 #define F_STATIC_XGPBUS_PLL_SSDS    V_STATIC_XGPBUS_PLL_SSDS(1U)
16661 #define V_STATIC_XGPBUS_PLL_SSE(x) ((x) << S_STATIC_XGPBUS_PLL_SSE)
16662 #define F_STATIC_XGPBUS_PLL_SSE    V_STATIC_XGPBUS_PLL_SSE(1U)
16667 #define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
16668 #define F_T5_STATIC_U_PLL_DCO_BYPASS    V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
16672 #define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
16673 #define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
16676 #define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
16677 #define F_T5_STATIC_U_PLL_FFENABLE    V_T5_STATIC_U_PLL_FFENABLE(1U)
16680 #define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
16681 #define F_T5_STATIC_U_PLL_STOPCLKB    V_T5_STATIC_U_PLL_STOPCLKB(1U)
16684 #define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
16685 #define F_T5_STATIC_U_PLL_STOPCLKA    V_T5_STATIC_U_PLL_STOPCLKA(1U)
16688 #define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
16689 #define F_T5_STATIC_U_PLL_SLEEP    V_T5_STATIC_U_PLL_SLEEP(1U)
16692 #define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
16693 #define F_T5_STATIC_U_PLL_BYPASS    V_T5_STATIC_U_PLL_BYPASS(1U)
16697 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
16698 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
16704 #define V_T6_STATIC_U_PLL_PREDIV(x) ((x) << S_T6_STATIC_U_PLL_PREDIV)
16705 #define G_T6_STATIC_U_PLL_PREDIV(x) (((x) >> S_T6_STATIC_U_PLL_PREDIV) & M_T6_STATIC_U_PLL_PREDIV)
16709 #define V_STATIC_U_PLL_STARTUP(x) ((x) << S_STATIC_U_PLL_STARTUP)
16710 #define G_STATIC_U_PLL_STARTUP(x) (((x) >> S_STATIC_U_PLL_STARTUP) & M_STATIC_U_PLL_STARTUP)
16713 #define V_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_STATIC_U_PLL_DCO_BYPASS)
16714 #define F_STATIC_U_PLL_DCO_BYPASS    V_STATIC_U_PLL_DCO_BYPASS(1U)
16718 #define V_STATIC_U_PLL_SDORDER(x) ((x) << S_STATIC_U_PLL_SDORDER)
16719 #define G_STATIC_U_PLL_SDORDER(x) (((x) >> S_STATIC_U_PLL_SDORDER) & M_STATIC_U_PLL_SDORDER)
16722 #define V_STATIC_U_PLL_DIVCHANGE(x) ((x) << S_STATIC_U_PLL_DIVCHANGE)
16723 #define F_STATIC_U_PLL_DIVCHANGE    V_STATIC_U_PLL_DIVCHANGE(1U)
16726 #define V_STATIC_U_PLL_STOPCLKB(x) ((x) << S_STATIC_U_PLL_STOPCLKB)
16727 #define F_STATIC_U_PLL_STOPCLKB    V_STATIC_U_PLL_STOPCLKB(1U)
16730 #define V_STATIC_U_PLL_STOPCLKA(x) ((x) << S_STATIC_U_PLL_STOPCLKA)
16731 #define F_STATIC_U_PLL_STOPCLKA    V_STATIC_U_PLL_STOPCLKA(1U)
16734 #define V_T6_STATIC_U_PLL_SLEEP(x) ((x) << S_T6_STATIC_U_PLL_SLEEP)
16735 #define F_T6_STATIC_U_PLL_SLEEP    V_T6_STATIC_U_PLL_SLEEP(1U)
16738 #define V_T6_STATIC_U_PLL_BYPASS(x) ((x) << S_T6_STATIC_U_PLL_BYPASS)
16739 #define F_T6_STATIC_U_PLL_BYPASS    V_T6_STATIC_U_PLL_BYPASS(1U)
16743 #define V_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_STATIC_U_PLL_LOCKTUNE)
16744 #define G_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_STATIC_U_PLL_LOCKTUNE) & M_STATIC_U_PLL_LOCKTUNE)
16750 #define V_STATIC_M1_PLL_RANGE(x) ((x) << S_STATIC_M1_PLL_RANGE)
16751 #define G_STATIC_M1_PLL_RANGE(x) (((x) >> S_STATIC_M1_PLL_RANGE) & M_STATIC_M1_PLL_RANGE)
16755 #define V_STATIC_M1_PLL_DIVQ(x) ((x) << S_STATIC_M1_PLL_DIVQ)
16756 #define G_STATIC_M1_PLL_DIVQ(x) (((x) >> S_STATIC_M1_PLL_DIVQ) & M_STATIC_M1_PLL_DIVQ)
16760 #define V_STATIC_M1_PLL_DIVFI(x) ((x) << S_STATIC_M1_PLL_DIVFI)
16761 #define G_STATIC_M1_PLL_DIVFI(x) (((x) >> S_STATIC_M1_PLL_DIVFI) & M_STATIC_M1_PLL_DIVFI)
16765 #define V_STATIC_M1_PLL_DIVR(x) ((x) << S_STATIC_M1_PLL_DIVR)
16766 #define G_STATIC_M1_PLL_DIVR(x) (((x) >> S_STATIC_M1_PLL_DIVR) & M_STATIC_M1_PLL_DIVR)
16768 #define S_STATIC_M1_PLL_BYPASS    1
16769 #define V_STATIC_M1_PLL_BYPASS(x) ((x) << S_STATIC_M1_PLL_BYPASS)
16770 #define F_STATIC_M1_PLL_BYPASS    V_STATIC_M1_PLL_BYPASS(1U)
16773 #define V_STATIC_M1_PLL_RESET(x) ((x) << S_STATIC_M1_PLL_RESET)
16774 #define F_STATIC_M1_PLL_RESET    V_STATIC_M1_PLL_RESET(1U)
16780 #define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
16781 #define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
16785 #define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
16786 #define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
16790 #define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
16791 #define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
16795 #define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
16796 #define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
16800 #define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
16801 #define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
16805 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
16806 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
16812 #define V_STATIC_U_PLL_MULTPRE(x) ((x) << S_STATIC_U_PLL_MULTPRE)
16813 #define G_STATIC_U_PLL_MULTPRE(x) (((x) >> S_STATIC_U_PLL_MULTPRE) & M_STATIC_U_PLL_MULTPRE)
16816 #define V_STATIC_U_PLL_LOCKSEL(x) ((x) << S_STATIC_U_PLL_LOCKSEL)
16817 #define F_STATIC_U_PLL_LOCKSEL    V_STATIC_U_PLL_LOCKSEL(1U)
16821 #define V_STATIC_U_PLL_FFTUNE(x) ((x) << S_STATIC_U_PLL_FFTUNE)
16822 #define G_STATIC_U_PLL_FFTUNE(x) (((x) >> S_STATIC_U_PLL_FFTUNE) & M_STATIC_U_PLL_FFTUNE)
16826 #define V_STATIC_U_PLL_RANGEPRE(x) ((x) << S_STATIC_U_PLL_RANGEPRE)
16827 #define G_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_STATIC_U_PLL_RANGEPRE) & M_STATIC_U_PLL_RANGEPRE)
16831 #define V_T6_STATIC_U_PLL_RANGEB(x) ((x) << S_T6_STATIC_U_PLL_RANGEB)
16832 #define G_T6_STATIC_U_PLL_RANGEB(x) (((x) >> S_T6_STATIC_U_PLL_RANGEB) & M_T6_STATIC_U_PLL_RANGEB)
16836 #define V_T6_STATIC_U_PLL_RANGEA(x) ((x) << S_T6_STATIC_U_PLL_RANGEA)
16837 #define G_T6_STATIC_U_PLL_RANGEA(x) (((x) >> S_T6_STATIC_U_PLL_RANGEA) & M_T6_STATIC_U_PLL_RANGEA)
16843 #define V_STATIC_M1_PLL_SSMF(x) ((x) << S_STATIC_M1_PLL_SSMF)
16844 #define G_STATIC_M1_PLL_SSMF(x) (((x) >> S_STATIC_M1_PLL_SSMF) & M_STATIC_M1_PLL_SSMF)
16848 #define V_STATIC_M1_PLL_SSMD(x) ((x) << S_STATIC_M1_PLL_SSMD)
16849 #define G_STATIC_M1_PLL_SSMD(x) (((x) >> S_STATIC_M1_PLL_SSMD) & M_STATIC_M1_PLL_SSMD)
16851 #define S_STATIC_M1_PLL_SSDS    1
16852 #define V_STATIC_M1_PLL_SSDS(x) ((x) << S_STATIC_M1_PLL_SSDS)
16853 #define F_STATIC_M1_PLL_SSDS    V_STATIC_M1_PLL_SSDS(1U)
16856 #define V_STATIC_M1_PLL_SSE(x) ((x) << S_STATIC_M1_PLL_SSE)
16857 #define F_STATIC_M1_PLL_SSE    V_STATIC_M1_PLL_SSE(1U)
16865 #define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
16866 #define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
16870 #define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
16871 #define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
16875 #define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
16876 #define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
16880 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
16881 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
16886 #define V_STATIC_U_PLL_FFBYPASS(x) ((x) << S_STATIC_U_PLL_FFBYPASS)
16887 #define F_STATIC_U_PLL_FFBYPASS    V_STATIC_U_PLL_FFBYPASS(1U)
16890 #define V_STATIC_U_PLL_FASTSTOP(x) ((x) << S_STATIC_U_PLL_FASTSTOP)
16891 #define F_STATIC_U_PLL_FASTSTOP    V_STATIC_U_PLL_FASTSTOP(1U)
16894 #define V_STATIC_U_PLL_FRAMESTOP(x) ((x) << S_STATIC_U_PLL_FRAMESTOP)
16895 #define F_STATIC_U_PLL_FRAMESTOP    V_STATIC_U_PLL_FRAMESTOP(1U)
16899 #define V_STATIC_U_PLL_VCVTUNE(x) ((x) << S_STATIC_U_PLL_VCVTUNE)
16900 #define G_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_STATIC_U_PLL_VCVTUNE) & M_STATIC_U_PLL_VCVTUNE)
16904 #define V_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_STATIC_U_PLL_LFTUNE_32_40)
16905 #define G_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_STATIC_U_PLL_LFTUNE_32_40) & M_STATIC_U_PLL_LFTUNE_32_40)
16909 #define V_STATIC_U_PLL_PREDIV_CNF5(x) ((x) << S_STATIC_U_PLL_PREDIV_CNF5)
16910 #define G_STATIC_U_PLL_PREDIV_CNF5(x) (((x) >> S_STATIC_U_PLL_PREDIV_CNF5) & M_STATIC_U_PLL_PREDIV_CNF5)
16914 #define V_T6_STATIC_U_PLL_MULT(x) ((x) << S_T6_STATIC_U_PLL_MULT)
16915 #define G_T6_STATIC_U_PLL_MULT(x) (((x) >> S_T6_STATIC_U_PLL_MULT) & M_T6_STATIC_U_PLL_MULT)
16920 #define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
16921 #define F_T5_STATIC_KR_PLL_BYPASS    V_T5_STATIC_KR_PLL_BYPASS(1U)
16925 #define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
16926 #define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
16930 #define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
16931 #define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
16934 #define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
16935 #define F_T5_STATIC_KR_PLL_CCALMETHOD    V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
16938 #define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
16939 #define F_T5_STATIC_KR_PLL_CCALLOAD    V_T5_STATIC_KR_PLL_CCALLOAD(1U)
16942 #define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
16943 #define F_T5_STATIC_KR_PLL_CCALFMIN    V_T5_STATIC_KR_PLL_CCALFMIN(1U)
16946 #define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
16947 #define F_T5_STATIC_KR_PLL_CCALFMAX    V_T5_STATIC_KR_PLL_CCALFMAX(1U)
16950 #define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
16951 #define F_T5_STATIC_KR_PLL_CCALCVHOLD    V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
16955 #define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
16956 #define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
16960 #define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
16961 #define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
16965 #define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
16966 #define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
16970 #define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
16971 #define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
16975 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
16976 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
16981 #define V_T6_STATIC_KR_PLL_BYPASS(x) ((x) << S_T6_STATIC_KR_PLL_BYPASS)
16982 #define F_T6_STATIC_KR_PLL_BYPASS    V_T6_STATIC_KR_PLL_BYPASS(1U)
16986 #define V_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KR_PLL_VBOOSTDIV)
16987 #define G_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KR_PLL_VBOOSTDIV) & M_STATIC_KR_PLL_VBOOSTDIV)
16991 #define V_STATIC_KR_PLL_CPISEL(x) ((x) << S_STATIC_KR_PLL_CPISEL)
16992 #define G_STATIC_KR_PLL_CPISEL(x) (((x) >> S_STATIC_KR_PLL_CPISEL) & M_STATIC_KR_PLL_CPISEL)
16995 #define V_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_STATIC_KR_PLL_CCALMETHOD)
16996 #define F_STATIC_KR_PLL_CCALMETHOD    V_STATIC_KR_PLL_CCALMETHOD(1U)
16999 #define V_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_STATIC_KR_PLL_CCALLOAD)
17000 #define F_STATIC_KR_PLL_CCALLOAD    V_STATIC_KR_PLL_CCALLOAD(1U)
17003 #define V_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_STATIC_KR_PLL_CCALFMIN)
17004 #define F_STATIC_KR_PLL_CCALFMIN    V_STATIC_KR_PLL_CCALFMIN(1U)
17007 #define V_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_STATIC_KR_PLL_CCALFMAX)
17008 #define F_STATIC_KR_PLL_CCALFMAX    V_STATIC_KR_PLL_CCALFMAX(1U)
17011 #define V_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KR_PLL_CCALCVHOLD)
17012 #define F_STATIC_KR_PLL_CCALCVHOLD    V_STATIC_KR_PLL_CCALCVHOLD(1U)
17016 #define V_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KR_PLL_CCALBANDSEL)
17017 #define G_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KR_PLL_CCALBANDSEL) & M_STATIC_KR_PLL_CCALBANDSEL)
17021 #define V_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_STATIC_KR_PLL_BGOFFSET)
17022 #define G_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_STATIC_KR_PLL_BGOFFSET) & M_STATIC_KR_PLL_BGOFFSET)
17026 #define V_T6_STATIC_KR_PLL_P(x) ((x) << S_T6_STATIC_KR_PLL_P)
17027 #define G_T6_STATIC_KR_PLL_P(x) (((x) >> S_T6_STATIC_KR_PLL_P) & M_T6_STATIC_KR_PLL_P)
17031 #define V_T6_STATIC_KR_PLL_N2(x) ((x) << S_T6_STATIC_KR_PLL_N2)
17032 #define G_T6_STATIC_KR_PLL_N2(x) (((x) >> S_T6_STATIC_KR_PLL_N2) & M_T6_STATIC_KR_PLL_N2)
17036 #define V_T6_STATIC_KR_PLL_N1(x) ((x) << S_T6_STATIC_KR_PLL_N1)
17037 #define G_T6_STATIC_KR_PLL_N1(x) (((x) >> S_T6_STATIC_KR_PLL_N1) & M_T6_STATIC_KR_PLL_N1)
17043 #define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
17044 #define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
17048 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
17049 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
17055 #define V_T6_STATIC_KR_PLL_M(x) ((x) << S_T6_STATIC_KR_PLL_M)
17056 #define G_T6_STATIC_KR_PLL_M(x) (((x) >> S_T6_STATIC_KR_PLL_M) & M_T6_STATIC_KR_PLL_M)
17060 #define V_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KR_PLL_ANALOGTUNE)
17061 #define G_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KR_PLL_ANALOGTUNE) & M_STATIC_KR_PLL_ANALOGTUNE)
17065 #define S_HALT_CALIBRATE    1
17066 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
17067 #define F_HALT_CALIBRATE    V_HALT_CALIBRATE(1U)
17070 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
17071 #define F_RESET_CALIBRATE    V_RESET_CALIBRATE(1U)
17076 #define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
17077 #define F_GPIO16_OEN    V_GPIO16_OEN(1U)
17080 #define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
17081 #define F_GPIO17_OEN    V_GPIO17_OEN(1U)
17084 #define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
17085 #define F_GPIO18_OEN    V_GPIO18_OEN(1U)
17088 #define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
17089 #define F_GPIO19_OEN    V_GPIO19_OEN(1U)
17092 #define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
17093 #define F_GPIO16_OUT_VAL    V_GPIO16_OUT_VAL(1U)
17096 #define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
17097 #define F_GPIO17_OUT_VAL    V_GPIO17_OUT_VAL(1U)
17099 #define S_GPIO18_OUT_VAL    1
17100 #define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
17101 #define F_GPIO18_OUT_VAL    V_GPIO18_OUT_VAL(1U)
17104 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
17105 #define F_GPIO19_OUT_VAL    V_GPIO19_OUT_VAL(1U)
17110 #define V_GPIO23_OEN(x) ((x) << S_GPIO23_OEN)
17111 #define F_GPIO23_OEN    V_GPIO23_OEN(1U)
17114 #define V_GPIO22_OEN(x) ((x) << S_GPIO22_OEN)
17115 #define F_GPIO22_OEN    V_GPIO22_OEN(1U)
17118 #define V_GPIO21_OEN(x) ((x) << S_GPIO21_OEN)
17119 #define F_GPIO21_OEN    V_GPIO21_OEN(1U)
17122 #define V_GPIO20_OEN(x) ((x) << S_GPIO20_OEN)
17123 #define F_GPIO20_OEN    V_GPIO20_OEN(1U)
17126 #define V_T7_GPIO19_OEN(x) ((x) << S_T7_GPIO19_OEN)
17127 #define F_T7_GPIO19_OEN    V_T7_GPIO19_OEN(1U)
17130 #define V_T7_GPIO18_OEN(x) ((x) << S_T7_GPIO18_OEN)
17131 #define F_T7_GPIO18_OEN    V_T7_GPIO18_OEN(1U)
17134 #define V_T7_GPIO17_OEN(x) ((x) << S_T7_GPIO17_OEN)
17135 #define F_T7_GPIO17_OEN    V_T7_GPIO17_OEN(1U)
17138 #define V_T7_GPIO16_OEN(x) ((x) << S_T7_GPIO16_OEN)
17139 #define F_T7_GPIO16_OEN    V_T7_GPIO16_OEN(1U)
17142 #define V_T7_GPIO15_OEN(x) ((x) << S_T7_GPIO15_OEN)
17143 #define F_T7_GPIO15_OEN    V_T7_GPIO15_OEN(1U)
17146 #define V_T7_GPIO14_OEN(x) ((x) << S_T7_GPIO14_OEN)
17147 #define F_T7_GPIO14_OEN    V_T7_GPIO14_OEN(1U)
17150 #define V_T7_GPIO13_OEN(x) ((x) << S_T7_GPIO13_OEN)
17151 #define F_T7_GPIO13_OEN    V_T7_GPIO13_OEN(1U)
17154 #define V_T7_GPIO12_OEN(x) ((x) << S_T7_GPIO12_OEN)
17155 #define F_T7_GPIO12_OEN    V_T7_GPIO12_OEN(1U)
17158 #define V_T7_GPIO11_OEN(x) ((x) << S_T7_GPIO11_OEN)
17159 #define F_T7_GPIO11_OEN    V_T7_GPIO11_OEN(1U)
17162 #define V_T7_GPIO10_OEN(x) ((x) << S_T7_GPIO10_OEN)
17163 #define F_T7_GPIO10_OEN    V_T7_GPIO10_OEN(1U)
17166 #define V_T7_GPIO9_OEN(x) ((x) << S_T7_GPIO9_OEN)
17167 #define F_T7_GPIO9_OEN    V_T7_GPIO9_OEN(1U)
17170 #define V_T7_GPIO8_OEN(x) ((x) << S_T7_GPIO8_OEN)
17171 #define F_T7_GPIO8_OEN    V_T7_GPIO8_OEN(1U)
17174 #define V_T7_GPIO7_OEN(x) ((x) << S_T7_GPIO7_OEN)
17175 #define F_T7_GPIO7_OEN    V_T7_GPIO7_OEN(1U)
17178 #define V_T7_GPIO6_OEN(x) ((x) << S_T7_GPIO6_OEN)
17179 #define F_T7_GPIO6_OEN    V_T7_GPIO6_OEN(1U)
17182 #define V_T7_GPIO5_OEN(x) ((x) << S_T7_GPIO5_OEN)
17183 #define F_T7_GPIO5_OEN    V_T7_GPIO5_OEN(1U)
17186 #define V_T7_GPIO4_OEN(x) ((x) << S_T7_GPIO4_OEN)
17187 #define F_T7_GPIO4_OEN    V_T7_GPIO4_OEN(1U)
17190 #define V_T7_GPIO3_OEN(x) ((x) << S_T7_GPIO3_OEN)
17191 #define F_T7_GPIO3_OEN    V_T7_GPIO3_OEN(1U)
17194 #define V_T7_GPIO2_OEN(x) ((x) << S_T7_GPIO2_OEN)
17195 #define F_T7_GPIO2_OEN    V_T7_GPIO2_OEN(1U)
17197 #define S_T7_GPIO1_OEN    1
17198 #define V_T7_GPIO1_OEN(x) ((x) << S_T7_GPIO1_OEN)
17199 #define F_T7_GPIO1_OEN    V_T7_GPIO1_OEN(1U)
17202 #define V_T7_GPIO0_OEN(x) ((x) << S_T7_GPIO0_OEN)
17203 #define F_T7_GPIO0_OEN    V_T7_GPIO0_OEN(1U)
17208 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
17209 #define F_FAST_UPDATE    V_FAST_UPDATE(1U)
17212 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
17213 #define F_FORCE_REG_IN_VALUE    V_FORCE_REG_IN_VALUE(1U)
17215 #define S_HALT_UPDATE    1
17216 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
17217 #define F_HALT_UPDATE    V_HALT_UPDATE(1U)
17222 #define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
17223 #define F_GPIO16_CHG_DET    V_GPIO16_CHG_DET(1U)
17226 #define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
17227 #define F_GPIO17_CHG_DET    V_GPIO17_CHG_DET(1U)
17230 #define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
17231 #define F_GPIO18_CHG_DET    V_GPIO18_CHG_DET(1U)
17234 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
17235 #define F_GPIO19_CHG_DET    V_GPIO19_CHG_DET(1U)
17238 #define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
17239 #define F_GPIO19_IN    V_GPIO19_IN(1U)
17242 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
17243 #define F_GPIO18_IN    V_GPIO18_IN(1U)
17245 #define S_GPIO17_IN    1
17246 #define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
17247 #define F_GPIO17_IN    V_GPIO17_IN(1U)
17250 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
17251 #define F_GPIO16_IN    V_GPIO16_IN(1U)
17256 #define V_GPIO23_CHG_DET(x) ((x) << S_GPIO23_CHG_DET)
17257 #define F_GPIO23_CHG_DET    V_GPIO23_CHG_DET(1U)
17260 #define V_GPIO22_CHG_DET(x) ((x) << S_GPIO22_CHG_DET)
17261 #define F_GPIO22_CHG_DET    V_GPIO22_CHG_DET(1U)
17264 #define V_GPIO21_CHG_DET(x) ((x) << S_GPIO21_CHG_DET)
17265 #define F_GPIO21_CHG_DET    V_GPIO21_CHG_DET(1U)
17268 #define V_GPIO20_CHG_DET(x) ((x) << S_GPIO20_CHG_DET)
17269 #define F_GPIO20_CHG_DET    V_GPIO20_CHG_DET(1U)
17272 #define V_T7_GPIO19_CHG_DET(x) ((x) << S_T7_GPIO19_CHG_DET)
17273 #define F_T7_GPIO19_CHG_DET    V_T7_GPIO19_CHG_DET(1U)
17276 #define V_T7_GPIO18_CHG_DET(x) ((x) << S_T7_GPIO18_CHG_DET)
17277 #define F_T7_GPIO18_CHG_DET    V_T7_GPIO18_CHG_DET(1U)
17280 #define V_T7_GPIO17_CHG_DET(x) ((x) << S_T7_GPIO17_CHG_DET)
17281 #define F_T7_GPIO17_CHG_DET    V_T7_GPIO17_CHG_DET(1U)
17284 #define V_T7_GPIO16_CHG_DET(x) ((x) << S_T7_GPIO16_CHG_DET)
17285 #define F_T7_GPIO16_CHG_DET    V_T7_GPIO16_CHG_DET(1U)
17288 #define V_T7_GPIO15_CHG_DET(x) ((x) << S_T7_GPIO15_CHG_DET)
17289 #define F_T7_GPIO15_CHG_DET    V_T7_GPIO15_CHG_DET(1U)
17292 #define V_T7_GPIO14_CHG_DET(x) ((x) << S_T7_GPIO14_CHG_DET)
17293 #define F_T7_GPIO14_CHG_DET    V_T7_GPIO14_CHG_DET(1U)
17296 #define V_T7_GPIO13_CHG_DET(x) ((x) << S_T7_GPIO13_CHG_DET)
17297 #define F_T7_GPIO13_CHG_DET    V_T7_GPIO13_CHG_DET(1U)
17300 #define V_T7_GPIO12_CHG_DET(x) ((x) << S_T7_GPIO12_CHG_DET)
17301 #define F_T7_GPIO12_CHG_DET    V_T7_GPIO12_CHG_DET(1U)
17304 #define V_T7_GPIO11_CHG_DET(x) ((x) << S_T7_GPIO11_CHG_DET)
17305 #define F_T7_GPIO11_CHG_DET    V_T7_GPIO11_CHG_DET(1U)
17308 #define V_T7_GPIO10_CHG_DET(x) ((x) << S_T7_GPIO10_CHG_DET)
17309 #define F_T7_GPIO10_CHG_DET    V_T7_GPIO10_CHG_DET(1U)
17312 #define V_T7_GPIO9_CHG_DET(x) ((x) << S_T7_GPIO9_CHG_DET)
17313 #define F_T7_GPIO9_CHG_DET    V_T7_GPIO9_CHG_DET(1U)
17316 #define V_T7_GPIO8_CHG_DET(x) ((x) << S_T7_GPIO8_CHG_DET)
17317 #define F_T7_GPIO8_CHG_DET    V_T7_GPIO8_CHG_DET(1U)
17320 #define V_T7_GPIO7_CHG_DET(x) ((x) << S_T7_GPIO7_CHG_DET)
17321 #define F_T7_GPIO7_CHG_DET    V_T7_GPIO7_CHG_DET(1U)
17324 #define V_T7_GPIO6_CHG_DET(x) ((x) << S_T7_GPIO6_CHG_DET)
17325 #define F_T7_GPIO6_CHG_DET    V_T7_GPIO6_CHG_DET(1U)
17328 #define V_T7_GPIO5_CHG_DET(x) ((x) << S_T7_GPIO5_CHG_DET)
17329 #define F_T7_GPIO5_CHG_DET    V_T7_GPIO5_CHG_DET(1U)
17332 #define V_T7_GPIO4_CHG_DET(x) ((x) << S_T7_GPIO4_CHG_DET)
17333 #define F_T7_GPIO4_CHG_DET    V_T7_GPIO4_CHG_DET(1U)
17336 #define V_T7_GPIO3_CHG_DET(x) ((x) << S_T7_GPIO3_CHG_DET)
17337 #define F_T7_GPIO3_CHG_DET    V_T7_GPIO3_CHG_DET(1U)
17340 #define V_T7_GPIO2_CHG_DET(x) ((x) << S_T7_GPIO2_CHG_DET)
17341 #define F_T7_GPIO2_CHG_DET    V_T7_GPIO2_CHG_DET(1U)
17343 #define S_T7_GPIO1_CHG_DET    1
17344 #define V_T7_GPIO1_CHG_DET(x) ((x) << S_T7_GPIO1_CHG_DET)
17345 #define F_T7_GPIO1_CHG_DET    V_T7_GPIO1_CHG_DET(1U)
17348 #define V_T7_GPIO0_CHG_DET(x) ((x) << S_T7_GPIO0_CHG_DET)
17349 #define F_T7_GPIO0_CHG_DET    V_T7_GPIO0_CHG_DET(1U)
17355 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
17356 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
17360 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
17361 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
17365 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
17366 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
17371 #define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
17372 #define F_T5_STATIC_KX_PLL_BYPASS    V_T5_STATIC_KX_PLL_BYPASS(1U)
17376 #define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
17377 #define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
17381 #define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
17382 #define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
17385 #define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
17386 #define F_T5_STATIC_KX_PLL_CCALMETHOD    V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
17389 #define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
17390 #define F_T5_STATIC_KX_PLL_CCALLOAD    V_T5_STATIC_KX_PLL_CCALLOAD(1U)
17393 #define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
17394 #define F_T5_STATIC_KX_PLL_CCALFMIN    V_T5_STATIC_KX_PLL_CCALFMIN(1U)
17397 #define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
17398 #define F_T5_STATIC_KX_PLL_CCALFMAX    V_T5_STATIC_KX_PLL_CCALFMAX(1U)
17401 #define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
17402 #define F_T5_STATIC_KX_PLL_CCALCVHOLD    V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
17406 #define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
17407 #define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
17411 #define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
17412 #define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
17416 #define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
17417 #define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
17421 #define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
17422 #define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
17426 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
17427 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
17432 #define V_T6_STATIC_KX_PLL_BYPASS(x) ((x) << S_T6_STATIC_KX_PLL_BYPASS)
17433 #define F_T6_STATIC_KX_PLL_BYPASS    V_T6_STATIC_KX_PLL_BYPASS(1U)
17437 #define V_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_STATIC_KX_PLL_VBOOSTDIV)
17438 #define G_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_STATIC_KX_PLL_VBOOSTDIV) & M_STATIC_KX_PLL_VBOOSTDIV)
17442 #define V_STATIC_KX_PLL_CPISEL(x) ((x) << S_STATIC_KX_PLL_CPISEL)
17443 #define G_STATIC_KX_PLL_CPISEL(x) (((x) >> S_STATIC_KX_PLL_CPISEL) & M_STATIC_KX_PLL_CPISEL)
17446 #define V_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_STATIC_KX_PLL_CCALMETHOD)
17447 #define F_STATIC_KX_PLL_CCALMETHOD    V_STATIC_KX_PLL_CCALMETHOD(1U)
17450 #define V_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_STATIC_KX_PLL_CCALLOAD)
17451 #define F_STATIC_KX_PLL_CCALLOAD    V_STATIC_KX_PLL_CCALLOAD(1U)
17454 #define V_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_STATIC_KX_PLL_CCALFMIN)
17455 #define F_STATIC_KX_PLL_CCALFMIN    V_STATIC_KX_PLL_CCALFMIN(1U)
17458 #define V_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_STATIC_KX_PLL_CCALFMAX)
17459 #define F_STATIC_KX_PLL_CCALFMAX    V_STATIC_KX_PLL_CCALFMAX(1U)
17462 #define V_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_STATIC_KX_PLL_CCALCVHOLD)
17463 #define F_STATIC_KX_PLL_CCALCVHOLD    V_STATIC_KX_PLL_CCALCVHOLD(1U)
17467 #define V_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_STATIC_KX_PLL_CCALBANDSEL)
17468 #define G_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_STATIC_KX_PLL_CCALBANDSEL) & M_STATIC_KX_PLL_CCALBANDSEL)
17472 #define V_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_STATIC_KX_PLL_BGOFFSET)
17473 #define G_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_STATIC_KX_PLL_BGOFFSET) & M_STATIC_KX_PLL_BGOFFSET)
17477 #define V_T6_STATIC_KX_PLL_P(x) ((x) << S_T6_STATIC_KX_PLL_P)
17478 #define G_T6_STATIC_KX_PLL_P(x) (((x) >> S_T6_STATIC_KX_PLL_P) & M_T6_STATIC_KX_PLL_P)
17482 #define V_T6_STATIC_KX_PLL_N2(x) ((x) << S_T6_STATIC_KX_PLL_N2)
17483 #define G_T6_STATIC_KX_PLL_N2(x) (((x) >> S_T6_STATIC_KX_PLL_N2) & M_T6_STATIC_KX_PLL_N2)
17487 #define V_T6_STATIC_KX_PLL_N1(x) ((x) << S_T6_STATIC_KX_PLL_N1)
17488 #define G_T6_STATIC_KX_PLL_N1(x) (((x) >> S_T6_STATIC_KX_PLL_N1) & M_T6_STATIC_KX_PLL_N1)
17493 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
17494 #define F_PVT_REG_DRVN_EN    V_PVT_REG_DRVN_EN(1U)
17498 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
17499 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
17503 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
17504 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
17510 #define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
17511 #define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
17515 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
17516 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
17522 #define V_T6_STATIC_KX_PLL_M(x) ((x) << S_T6_STATIC_KX_PLL_M)
17523 #define G_T6_STATIC_KX_PLL_M(x) (((x) >> S_T6_STATIC_KX_PLL_M) & M_T6_STATIC_KX_PLL_M)
17527 #define V_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_STATIC_KX_PLL_ANALOGTUNE)
17528 #define G_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_STATIC_KX_PLL_ANALOGTUNE) & M_STATIC_KX_PLL_ANALOGTUNE)
17533 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
17534 #define F_PVT_REG_DRVP_EN    V_PVT_REG_DRVP_EN(1U)
17538 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
17539 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
17543 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
17544 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
17550 #define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
17551 #define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
17555 #define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
17556 #define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
17559 #define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
17560 #define F_STATIC_C_DFS_FFTUNE4    V_STATIC_C_DFS_FFTUNE4(1U)
17562 #define S_STATIC_C_DFS_FFTUNE5    1
17563 #define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
17564 #define F_STATIC_C_DFS_FFTUNE5    V_STATIC_C_DFS_FFTUNE5(1U)
17567 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
17568 #define F_STATIC_C_DFS_ENABLE    V_STATIC_C_DFS_ENABLE(1U)
17574 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
17575 #define F_PVT_REG_TERMN_EN    V_PVT_REG_TERMN_EN(1U)
17579 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
17580 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
17584 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
17585 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
17591 #define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
17592 #define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
17596 #define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
17597 #define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
17600 #define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
17601 #define F_STATIC_U_DFS_FFTUNE4    V_STATIC_U_DFS_FFTUNE4(1U)
17603 #define S_STATIC_U_DFS_FFTUNE5    1
17604 #define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
17605 #define F_STATIC_U_DFS_FFTUNE5    V_STATIC_U_DFS_FFTUNE5(1U)
17608 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
17609 #define F_STATIC_U_DFS_ENABLE    V_STATIC_U_DFS_ENABLE(1U)
17615 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
17616 #define F_PVT_REG_TERMP_EN    V_PVT_REG_TERMP_EN(1U)
17620 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
17621 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
17625 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
17626 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
17631 #define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
17632 #define F_GPIO19_PE_EN    V_GPIO19_PE_EN(1U)
17635 #define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
17636 #define F_GPIO18_PE_EN    V_GPIO18_PE_EN(1U)
17639 #define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
17640 #define F_GPIO17_PE_EN    V_GPIO17_PE_EN(1U)
17643 #define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
17644 #define F_GPIO16_PE_EN    V_GPIO16_PE_EN(1U)
17647 #define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
17648 #define F_GPIO15_PE_EN    V_GPIO15_PE_EN(1U)
17651 #define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
17652 #define F_GPIO14_PE_EN    V_GPIO14_PE_EN(1U)
17655 #define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
17656 #define F_GPIO13_PE_EN    V_GPIO13_PE_EN(1U)
17659 #define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
17660 #define F_GPIO12_PE_EN    V_GPIO12_PE_EN(1U)
17663 #define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
17664 #define F_GPIO11_PE_EN    V_GPIO11_PE_EN(1U)
17667 #define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
17668 #define F_GPIO10_PE_EN    V_GPIO10_PE_EN(1U)
17671 #define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
17672 #define F_GPIO9_PE_EN    V_GPIO9_PE_EN(1U)
17675 #define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
17676 #define F_GPIO8_PE_EN    V_GPIO8_PE_EN(1U)
17679 #define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
17680 #define F_GPIO7_PE_EN    V_GPIO7_PE_EN(1U)
17683 #define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
17684 #define F_GPIO6_PE_EN    V_GPIO6_PE_EN(1U)
17687 #define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
17688 #define F_GPIO5_PE_EN    V_GPIO5_PE_EN(1U)
17691 #define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
17692 #define F_GPIO4_PE_EN    V_GPIO4_PE_EN(1U)
17695 #define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
17696 #define F_GPIO3_PE_EN    V_GPIO3_PE_EN(1U)
17699 #define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
17700 #define F_GPIO2_PE_EN    V_GPIO2_PE_EN(1U)
17702 #define S_GPIO1_PE_EN    1
17703 #define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
17704 #define F_GPIO1_PE_EN    V_GPIO1_PE_EN(1U)
17707 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
17708 #define F_GPIO0_PE_EN    V_GPIO0_PE_EN(1U)
17711 #define V_GPIO23_PE_EN(x) ((x) << S_GPIO23_PE_EN)
17712 #define F_GPIO23_PE_EN    V_GPIO23_PE_EN(1U)
17715 #define V_GPIO22_PE_EN(x) ((x) << S_GPIO22_PE_EN)
17716 #define F_GPIO22_PE_EN    V_GPIO22_PE_EN(1U)
17719 #define V_GPIO21_PE_EN(x) ((x) << S_GPIO21_PE_EN)
17720 #define F_GPIO21_PE_EN    V_GPIO21_PE_EN(1U)
17723 #define V_GPIO20_PE_EN(x) ((x) << S_GPIO20_PE_EN)
17724 #define F_GPIO20_PE_EN    V_GPIO20_PE_EN(1U)
17729 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
17730 #define F_PVT_CALIBRATION_DONE    V_PVT_CALIBRATION_DONE(1U)
17733 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
17734 #define F_THRESHOLD_TERMP_MAX_SYNC    V_THRESHOLD_TERMP_MAX_SYNC(1U)
17737 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
17738 #define F_THRESHOLD_TERMP_MIN_SYNC    V_THRESHOLD_TERMP_MIN_SYNC(1U)
17741 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
17742 #define F_THRESHOLD_TERMN_MAX_SYNC    V_THRESHOLD_TERMN_MAX_SYNC(1U)
17745 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
17746 #define F_THRESHOLD_TERMN_MIN_SYNC    V_THRESHOLD_TERMN_MIN_SYNC(1U)
17749 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
17750 #define F_THRESHOLD_DRVP_MAX_SYNC    V_THRESHOLD_DRVP_MAX_SYNC(1U)
17753 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
17754 #define F_THRESHOLD_DRVP_MIN_SYNC    V_THRESHOLD_DRVP_MIN_SYNC(1U)
17756 #define S_THRESHOLD_DRVN_MAX_SYNC    1
17757 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
17758 #define F_THRESHOLD_DRVN_MAX_SYNC    V_THRESHOLD_DRVN_MAX_SYNC(1U)
17761 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
17762 #define F_THRESHOLD_DRVN_MIN_SYNC    V_THRESHOLD_DRVN_MIN_SYNC(1U)
17767 #define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
17768 #define F_GPIO19_PS_EN    V_GPIO19_PS_EN(1U)
17771 #define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
17772 #define F_GPIO18_PS_EN    V_GPIO18_PS_EN(1U)
17775 #define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
17776 #define F_GPIO17_PS_EN    V_GPIO17_PS_EN(1U)
17779 #define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
17780 #define F_GPIO16_PS_EN    V_GPIO16_PS_EN(1U)
17783 #define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
17784 #define F_GPIO15_PS_EN    V_GPIO15_PS_EN(1U)
17787 #define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
17788 #define F_GPIO14_PS_EN    V_GPIO14_PS_EN(1U)
17791 #define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
17792 #define F_GPIO13_PS_EN    V_GPIO13_PS_EN(1U)
17795 #define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
17796 #define F_GPIO12_PS_EN    V_GPIO12_PS_EN(1U)
17799 #define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
17800 #define F_GPIO11_PS_EN    V_GPIO11_PS_EN(1U)
17803 #define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
17804 #define F_GPIO10_PS_EN    V_GPIO10_PS_EN(1U)
17807 #define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
17808 #define F_GPIO9_PS_EN    V_GPIO9_PS_EN(1U)
17811 #define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
17812 #define F_GPIO8_PS_EN    V_GPIO8_PS_EN(1U)
17815 #define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
17816 #define F_GPIO7_PS_EN    V_GPIO7_PS_EN(1U)
17819 #define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
17820 #define F_GPIO6_PS_EN    V_GPIO6_PS_EN(1U)
17823 #define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
17824 #define F_GPIO5_PS_EN    V_GPIO5_PS_EN(1U)
17827 #define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
17828 #define F_GPIO4_PS_EN    V_GPIO4_PS_EN(1U)
17831 #define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
17832 #define F_GPIO3_PS_EN    V_GPIO3_PS_EN(1U)
17835 #define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
17836 #define F_GPIO2_PS_EN    V_GPIO2_PS_EN(1U)
17838 #define S_GPIO1_PS_EN    1
17839 #define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
17840 #define F_GPIO1_PS_EN    V_GPIO1_PS_EN(1U)
17843 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
17844 #define F_GPIO0_PS_EN    V_GPIO0_PS_EN(1U)
17847 #define V_GPIO23_PS_EN(x) ((x) << S_GPIO23_PS_EN)
17848 #define F_GPIO23_PS_EN    V_GPIO23_PS_EN(1U)
17851 #define V_GPIO22_PS_EN(x) ((x) << S_GPIO22_PS_EN)
17852 #define F_GPIO22_PS_EN    V_GPIO22_PS_EN(1U)
17855 #define V_GPIO21_PS_EN(x) ((x) << S_GPIO21_PS_EN)
17856 #define F_GPIO21_PS_EN    V_GPIO21_PS_EN(1U)
17859 #define V_GPIO20_PS_EN(x) ((x) << S_GPIO20_PS_EN)
17860 #define F_GPIO20_PS_EN    V_GPIO20_PS_EN(1U)
17866 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
17867 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
17871 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
17872 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
17879 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
17880 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
17884 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
17885 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
17892 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
17893 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
17897 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
17898 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
17905 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
17906 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
17910 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
17911 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
17918 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
17919 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
17923 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
17924 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
17931 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
17932 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
17936 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
17937 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
17944 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
17945 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
17949 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
17950 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
17957 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
17958 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
17962 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
17963 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
17970 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
17971 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
17975 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
17976 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
17983 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
17984 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
17988 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
17989 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
17996 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
17997 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
18001 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
18002 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
18009 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
18010 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
18014 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
18015 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
18022 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
18023 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
18029 #define V_STATIC_U_PLL_VREGTUNE(x) ((x) << S_STATIC_U_PLL_VREGTUNE)
18030 #define G_STATIC_U_PLL_VREGTUNE(x) (((x) >> S_STATIC_U_PLL_VREGTUNE) & M_STATIC_U_PLL_VREGTUNE)
18035 #define V_STATIC_WAIT_LOCK(x) ((x) << S_STATIC_WAIT_LOCK)
18036 #define F_STATIC_WAIT_LOCK    V_STATIC_WAIT_LOCK(1U)
18040 #define V_STATIC_LOCK_WAIT_TIME(x) ((x) << S_STATIC_LOCK_WAIT_TIME)
18041 #define G_STATIC_LOCK_WAIT_TIME(x) (((x) >> S_STATIC_LOCK_WAIT_TIME) & M_STATIC_LOCK_WAIT_TIME)
18047 #define V_STATIC_C_PLL_VREGTUNE(x) ((x) << S_STATIC_C_PLL_VREGTUNE)
18048 #define G_STATIC_C_PLL_VREGTUNE(x) (((x) >> S_STATIC_C_PLL_VREGTUNE) & M_STATIC_C_PLL_VREGTUNE)
18054 #define V_EFUSE_PROG_PERIOD(x) ((x) << S_EFUSE_PROG_PERIOD)
18055 #define G_EFUSE_PROG_PERIOD(x) (((x) >> S_EFUSE_PROG_PERIOD) & M_EFUSE_PROG_PERIOD)
18059 #define V_EFUSE_OPER_TYP(x) ((x) << S_EFUSE_OPER_TYP)
18060 #define G_EFUSE_OPER_TYP(x) (((x) >> S_EFUSE_OPER_TYP) & M_EFUSE_OPER_TYP)
18064 #define V_EFUSE_ADDR(x) ((x) << S_EFUSE_ADDR)
18065 #define G_EFUSE_ADDR(x) (((x) >> S_EFUSE_ADDR) & M_EFUSE_ADDR)
18069 #define V_EFUSE_DIN(x) ((x) << S_EFUSE_DIN)
18070 #define G_EFUSE_DIN(x) (((x) >> S_EFUSE_DIN) & M_EFUSE_DIN)
18075 #define V_EFUSE_OPER_DONE(x) ((x) << S_EFUSE_OPER_DONE)
18076 #define F_EFUSE_OPER_DONE    V_EFUSE_OPER_DONE(1U)
18080 #define V_EFUSE_DOUT(x) ((x) << S_EFUSE_DOUT)
18081 #define G_EFUSE_DOUT(x) (((x) >> S_EFUSE_DOUT) & M_EFUSE_DOUT)
18095 #define V_GPIO23(x) ((x) << S_GPIO23)
18096 #define F_GPIO23    V_GPIO23(1U)
18099 #define V_GPIO22(x) ((x) << S_GPIO22)
18100 #define F_GPIO22    V_GPIO22(1U)
18103 #define V_GPIO21(x) ((x) << S_GPIO21)
18104 #define F_GPIO21    V_GPIO21(1U)
18107 #define V_GPIO20(x) ((x) << S_GPIO20)
18108 #define F_GPIO20    V_GPIO20(1U)
18111 #define V_T7_GPIO19(x) ((x) << S_T7_GPIO19)
18112 #define F_T7_GPIO19    V_T7_GPIO19(1U)
18115 #define V_T7_GPIO18(x) ((x) << S_T7_GPIO18)
18116 #define F_T7_GPIO18    V_T7_GPIO18(1U)
18119 #define V_T7_GPIO17(x) ((x) << S_T7_GPIO17)
18120 #define F_T7_GPIO17    V_T7_GPIO17(1U)
18123 #define V_T7_GPIO16(x) ((x) << S_T7_GPIO16)
18124 #define F_T7_GPIO16    V_T7_GPIO16(1U)
18132 #define V_GPIO23_ACT_LOW(x) ((x) << S_GPIO23_ACT_LOW)
18133 #define F_GPIO23_ACT_LOW    V_GPIO23_ACT_LOW(1U)
18136 #define V_GPIO22_ACT_LOW(x) ((x) << S_GPIO22_ACT_LOW)
18137 #define F_GPIO22_ACT_LOW    V_GPIO22_ACT_LOW(1U)
18140 #define V_GPIO21_ACT_LOW(x) ((x) << S_GPIO21_ACT_LOW)
18141 #define F_GPIO21_ACT_LOW    V_GPIO21_ACT_LOW(1U)
18144 #define V_GPIO20_ACT_LOW(x) ((x) << S_GPIO20_ACT_LOW)
18145 #define F_GPIO20_ACT_LOW    V_GPIO20_ACT_LOW(1U)
18148 #define V_T7_GPIO19_ACT_LOW(x) ((x) << S_T7_GPIO19_ACT_LOW)
18149 #define F_T7_GPIO19_ACT_LOW    V_T7_GPIO19_ACT_LOW(1U)
18152 #define V_T7_GPIO18_ACT_LOW(x) ((x) << S_T7_GPIO18_ACT_LOW)
18153 #define F_T7_GPIO18_ACT_LOW    V_T7_GPIO18_ACT_LOW(1U)
18156 #define V_T7_GPIO17_ACT_LOW(x) ((x) << S_T7_GPIO17_ACT_LOW)
18157 #define F_T7_GPIO17_ACT_LOW    V_T7_GPIO17_ACT_LOW(1U)
18160 #define V_T7_GPIO16_ACT_LOW(x) ((x) << S_T7_GPIO16_ACT_LOW)
18161 #define F_T7_GPIO16_ACT_LOW    V_T7_GPIO16_ACT_LOW(1U)
18167 #define V_CAL_ENDC(x) ((x) << S_CAL_ENDC)
18168 #define F_CAL_ENDC    V_CAL_ENDC(1U)
18171 #define V_CAL_MODE(x) ((x) << S_CAL_MODE)
18172 #define F_CAL_MODE    V_CAL_MODE(1U)
18175 #define V_CAL_REFSEL(x) ((x) << S_CAL_REFSEL)
18176 #define F_CAL_REFSEL    V_CAL_REFSEL(1U)
18179 #define V_PD(x) ((x) << S_PD)
18180 #define F_PD    V_PD(1U)
18183 #define V_CAL_RST(x) ((x) << S_CAL_RST)
18184 #define F_CAL_RST    V_CAL_RST(1U)
18187 #define V_CAL_READ(x) ((x) << S_CAL_READ)
18188 #define F_CAL_READ    V_CAL_READ(1U)
18191 #define V_CAL_SC(x) ((x) << S_CAL_SC)
18192 #define F_CAL_SC    V_CAL_SC(1U)
18195 #define V_CAL_LC(x) ((x) << S_CAL_LC)
18196 #define F_CAL_LC    V_CAL_LC(1U)
18198 #define S_CAL_CCAL    1
18199 #define V_CAL_CCAL(x) ((x) << S_CAL_CCAL)
18200 #define F_CAL_CCAL    V_CAL_CCAL(1U)
18203 #define V_CAL_RES(x) ((x) << S_CAL_RES)
18204 #define F_CAL_RES    V_CAL_RES(1U)
18210 #define V_EFUSE_CSB(x) ((x) << S_EFUSE_CSB)
18211 #define F_EFUSE_CSB    V_EFUSE_CSB(1U)
18214 #define V_EFUSE_STROBE(x) ((x) << S_EFUSE_STROBE)
18215 #define F_EFUSE_STROBE    V_EFUSE_STROBE(1U)
18218 #define V_EFUSE_LOAD(x) ((x) << S_EFUSE_LOAD)
18219 #define F_EFUSE_LOAD    V_EFUSE_LOAD(1U)
18222 #define V_EFUSE_PGENB(x) ((x) << S_EFUSE_PGENB)
18223 #define F_EFUSE_PGENB    V_EFUSE_PGENB(1U)
18226 #define V_EFUSE_PS(x) ((x) << S_EFUSE_PS)
18227 #define F_EFUSE_PS    V_EFUSE_PS(1U)
18230 #define V_EFUSE_MR(x) ((x) << S_EFUSE_MR)
18231 #define F_EFUSE_MR    V_EFUSE_MR(1U)
18234 #define V_EFUSE_PD(x) ((x) << S_EFUSE_PD)
18235 #define F_EFUSE_PD    V_EFUSE_PD(1U)
18238 #define V_EFUSE_RWL(x) ((x) << S_EFUSE_RWL)
18239 #define F_EFUSE_RWL    V_EFUSE_RWL(1U)
18242 #define V_EFUSE_RSB(x) ((x) << S_EFUSE_RSB)
18243 #define F_EFUSE_RSB    V_EFUSE_RSB(1U)
18246 #define V_EFUSE_TRCS(x) ((x) << S_EFUSE_TRCS)
18247 #define F_EFUSE_TRCS    V_EFUSE_TRCS(1U)
18251 #define V_EFUSE_AT(x) ((x) << S_EFUSE_AT)
18252 #define G_EFUSE_AT(x) (((x) >> S_EFUSE_AT) & M_EFUSE_AT)
18256 #define V_EFUSE_RD_STATE(x) ((x) << S_EFUSE_RD_STATE)
18257 #define G_EFUSE_RD_STATE(x) (((x) >> S_EFUSE_RD_STATE) & M_EFUSE_RD_STATE)
18260 #define V_EFUSE_BUSY(x) ((x) << S_EFUSE_BUSY)
18261 #define F_EFUSE_BUSY    V_EFUSE_BUSY(1U)
18265 #define V_EFUSE_WR_RD(x) ((x) << S_EFUSE_WR_RD)
18266 #define G_EFUSE_WR_RD(x) (((x) >> S_EFUSE_WR_RD) & M_EFUSE_WR_RD)
18270 #define V_EFUSE_A(x) ((x) << S_EFUSE_A)
18271 #define G_EFUSE_A(x) (((x) >> S_EFUSE_A) & M_EFUSE_A)
18280 #define V_EFUSE_RD_ID(x) ((x) << S_EFUSE_RD_ID)
18281 #define G_EFUSE_RD_ID(x) (((x) >> S_EFUSE_RD_ID) & M_EFUSE_RD_ID)
18285 #define V_EFUSE_RD_ADDR(x) ((x) << S_EFUSE_RD_ADDR)
18286 #define G_EFUSE_RD_ADDR(x) (((x) >> S_EFUSE_RD_ADDR) & M_EFUSE_RD_ADDR)
18294 #define V_EFUSE_TIME_1(x) ((x) << S_EFUSE_TIME_1)
18295 #define G_EFUSE_TIME_1(x) (((x) >> S_EFUSE_TIME_1) & M_EFUSE_TIME_1)
18299 #define V_EFUSE_TIME_0(x) ((x) << S_EFUSE_TIME_0)
18300 #define G_EFUSE_TIME_0(x) (((x) >> S_EFUSE_TIME_0) & M_EFUSE_TIME_0)
18306 #define V_EFUSE_TIME_3(x) ((x) << S_EFUSE_TIME_3)
18307 #define G_EFUSE_TIME_3(x) (((x) >> S_EFUSE_TIME_3) & M_EFUSE_TIME_3)
18311 #define V_EFUSE_TIME_2(x) ((x) << S_EFUSE_TIME_2)
18312 #define G_EFUSE_TIME_2(x) (((x) >> S_EFUSE_TIME_2) & M_EFUSE_TIME_2)
18318 #define V_EFUSE_TIME_5(x) ((x) << S_EFUSE_TIME_5)
18319 #define G_EFUSE_TIME_5(x) (((x) >> S_EFUSE_TIME_5) & M_EFUSE_TIME_5)
18323 #define V_EFUSE_TIME_4(x) ((x) << S_EFUSE_TIME_4)
18324 #define G_EFUSE_TIME_4(x) (((x) >> S_EFUSE_TIME_4) & M_EFUSE_TIME_4)
18330 #define V_EFUSE_TIME_7(x) ((x) << S_EFUSE_TIME_7)
18331 #define G_EFUSE_TIME_7(x) (((x) >> S_EFUSE_TIME_7) & M_EFUSE_TIME_7)
18335 #define V_EFUSE_TIME_6(x) ((x) << S_EFUSE_TIME_6)
18336 #define G_EFUSE_TIME_6(x) (((x) >> S_EFUSE_TIME_6) & M_EFUSE_TIME_6)
18341 #define V_VREF_SEL_1(x) ((x) << S_VREF_SEL_1)
18342 #define F_VREF_SEL_1    V_VREF_SEL_1(1U)
18346 #define V_VREF_R_1(x) ((x) << S_VREF_R_1)
18347 #define G_VREF_R_1(x) (((x) >> S_VREF_R_1) & M_VREF_R_1)
18350 #define V_VREF_SEL_0(x) ((x) << S_VREF_SEL_0)
18351 #define F_VREF_SEL_0    V_VREF_SEL_0(1U)
18355 #define V_VREF_R_0(x) ((x) << S_VREF_R_0)
18356 #define G_VREF_R_0(x) (((x) >> S_VREF_R_0) & M_VREF_R_0)
18367 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
18368 #define F_RKINF_EN    V_RKINF_EN(1U)
18371 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
18372 #define F_DUAL_PCTL_EN    V_DUAL_PCTL_EN(1U)
18375 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
18376 #define F_SLAVE_MODE    V_SLAVE_MODE(1U)
18378 #define S_LOOPBACK_EN    1
18379 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
18380 #define F_LOOPBACK_EN    V_LOOPBACK_EN(1U)
18383 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
18384 #define F_HW_LOW_POWER_EN    V_HW_LOW_POWER_EN(1U)
18390 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
18391 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
18397 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
18398 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
18403 #define V_START_CMD(x) ((x) << S_START_CMD)
18404 #define F_START_CMD    V_START_CMD(1U)
18408 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
18409 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
18413 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
18414 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
18418 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
18419 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
18423 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
18424 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
18428 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
18429 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
18434 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
18435 #define F_POWER_UP_START    V_POWER_UP_START(1U)
18439 #define S_PHY_CALIBDONE    1
18440 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
18441 #define F_PHY_CALIBDONE    V_PHY_CALIBDONE(1U)
18444 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
18445 #define F_POWER_UP_DONE    V_POWER_UP_DONE(1U)
18451 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
18452 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
18455 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
18456 #define F_PD_EXIT_MODE    V_PD_EXIT_MODE(1U)
18459 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
18460 #define F_PD_TYPE    V_PD_TYPE(1U)
18464 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
18465 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
18469 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
18470 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
18473 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
18474 #define F_DDR3_EN    V_DDR3_EN(1U)
18477 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
18478 #define F_TWO_T_EN    V_TWO_T_EN(1U)
18481 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
18482 #define F_BL8INT_EN    V_BL8INT_EN(1U)
18485 #define V_MEM_BL(x) ((x) << S_MEM_BL)
18486 #define F_MEM_BL    V_MEM_BL(1U)
18490 #define S_RPMEM_DIS    1
18492 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
18493 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
18496 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
18497 #define F_PPMEM_EN    V_PPMEM_EN(1U)
18502 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
18503 #define F_POWER_DOWN    V_POWER_DOWN(1U)
18508 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
18509 #define F_RANK3_ODT_DEFAULT    V_RANK3_ODT_DEFAULT(1U)
18512 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
18513 #define F_RANK3_ODT_WRITE_SEL    V_RANK3_ODT_WRITE_SEL(1U)
18516 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
18517 #define F_RANK3_ODT_WRITE_NSE    V_RANK3_ODT_WRITE_NSE(1U)
18520 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
18521 #define F_RANK3_ODT_READ_SEL    V_RANK3_ODT_READ_SEL(1U)
18524 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
18525 #define F_RANK3_ODT_READ_NSEL    V_RANK3_ODT_READ_NSEL(1U)
18528 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
18529 #define F_RANK2_ODT_DEFAULT    V_RANK2_ODT_DEFAULT(1U)
18532 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
18533 #define F_RANK2_ODT_WRITE_SEL    V_RANK2_ODT_WRITE_SEL(1U)
18536 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
18537 #define F_RANK2_ODT_WRITE_NSEL    V_RANK2_ODT_WRITE_NSEL(1U)
18540 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
18541 #define F_RANK2_ODT_READ_SEL    V_RANK2_ODT_READ_SEL(1U)
18544 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
18545 #define F_RANK2_ODT_READ_NSEL    V_RANK2_ODT_READ_NSEL(1U)
18548 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
18549 #define F_RANK1_ODT_DEFAULT    V_RANK1_ODT_DEFAULT(1U)
18552 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
18553 #define F_RANK1_ODT_WRITE_SEL    V_RANK1_ODT_WRITE_SEL(1U)
18556 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
18557 #define F_RANK1_ODT_WRITE_NSEL    V_RANK1_ODT_WRITE_NSEL(1U)
18560 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
18561 #define F_RANK1_ODT_READ_SEL    V_RANK1_ODT_READ_SEL(1U)
18564 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
18565 #define F_RANK1_ODT_READ_NSEL    V_RANK1_ODT_READ_NSEL(1U)
18568 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
18569 #define F_RANK0_ODT_DEFAULT    V_RANK0_ODT_DEFAULT(1U)
18572 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
18573 #define F_RANK0_ODT_WRITE_SEL    V_RANK0_ODT_WRITE_SEL(1U)
18576 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
18577 #define F_RANK0_ODT_WRITE_NSEL    V_RANK0_ODT_WRITE_NSEL(1U)
18579 #define S_RANK0_ODT_READ_SEL    1
18580 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
18581 #define F_RANK0_ODT_READ_SEL    V_RANK0_ODT_READ_SEL(1U)
18584 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
18585 #define F_RANK0_ODT_READ_NSEL    V_RANK0_ODT_READ_NSEL(1U)
18591 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
18592 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
18596 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
18597 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
18601 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
18602 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
18606 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
18607 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
18611 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
18612 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
18616 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
18617 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
18622 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
18623 #define F_DTU_RD_MISSING    V_DTU_RD_MISSING(1U)
18627 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
18628 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
18631 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
18632 #define F_DTU_RANDOM_ERROR    V_DTU_RANDOM_ERROR(1U)
18635 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
18636 #define F_DTU_ERROR_B7    V_DTU_ERROR_B7(1U)
18639 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
18640 #define F_DTU_ERR_B6    V_DTU_ERR_B6(1U)
18643 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
18644 #define F_DTU_ERR_B5    V_DTU_ERR_B5(1U)
18647 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
18648 #define F_DTU_ERR_B4    V_DTU_ERR_B4(1U)
18651 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
18652 #define F_DTU_ERR_B3    V_DTU_ERR_B3(1U)
18655 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
18656 #define F_DTU_ERR_B2    V_DTU_ERR_B2(1U)
18658 #define S_DTU_ERR_B1    1
18659 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
18660 #define F_DTU_ERR_B1    V_DTU_ERR_B1(1U)
18663 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
18664 #define F_DTU_ERR_B0    V_DTU_ERR_B0(1U)
18672 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
18673 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
18677 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
18678 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
18684 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
18685 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
18689 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
18690 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
18696 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
18697 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
18701 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
18702 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
18708 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
18709 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
18713 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
18714 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
18720 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
18721 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
18725 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
18726 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
18730 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
18731 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
18735 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
18736 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
18742 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
18743 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
18749 #define V_T_INIT(x) ((x) << S_T_INIT)
18750 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
18756 #define V_T_RSTH(x) ((x) << S_T_RSTH)
18757 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
18763 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
18764 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
18770 #define V_T_REFI(x) ((x) << S_T_REFI)
18771 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
18777 #define V_T_MRD(x) ((x) << S_T_MRD)
18778 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
18784 #define V_T_RFC(x) ((x) << S_T_RFC)
18785 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
18791 #define V_T_RP(x) ((x) << S_T_RP)
18792 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
18798 #define V_T_RTW(x) ((x) << S_T_RTW)
18799 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
18805 #define V_T_AL(x) ((x) << S_T_AL)
18806 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
18812 #define V_T_CL(x) ((x) << S_T_CL)
18813 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
18819 #define V_T_CWL(x) ((x) << S_T_CWL)
18820 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
18826 #define V_T_RAS(x) ((x) << S_T_RAS)
18827 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
18833 #define V_T_RC(x) ((x) << S_T_RC)
18834 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
18840 #define V_T_RCD(x) ((x) << S_T_RCD)
18841 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
18847 #define V_T_RRD(x) ((x) << S_T_RRD)
18848 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
18854 #define V_T_RTP(x) ((x) << S_T_RTP)
18855 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
18861 #define V_T_WR(x) ((x) << S_T_WR)
18862 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
18868 #define V_T_WTR(x) ((x) << S_T_WTR)
18869 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
18875 #define V_T_EXSR(x) ((x) << S_T_EXSR)
18876 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
18882 #define V_T_XP(x) ((x) << S_T_XP)
18883 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
18889 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
18890 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
18896 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
18897 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
18903 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
18904 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
18910 #define V_T_DQS(x) ((x) << S_T_DQS)
18911 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
18917 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
18918 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
18924 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
18925 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
18931 #define V_T_CKE(x) ((x) << S_T_CKE)
18932 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
18938 #define V_T_MOD(x) ((x) << S_T_MOD)
18939 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
18945 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
18946 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
18952 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
18953 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
18959 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
18960 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
18968 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
18969 #define F_INLINE_SYN_EN    V_INLINE_SYN_EN(1U)
18972 #define V_ECC_EN(x) ((x) << S_ECC_EN)
18973 #define F_ECC_EN    V_ECC_EN(1U)
18976 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
18977 #define F_ECC_INTR_EN    V_ECC_INTR_EN(1U)
18983 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
18984 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
18988 #define S_CLR_ECC_LOG    1
18989 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
18990 #define F_CLR_ECC_LOG    V_CLR_ECC_LOG(1U)
18993 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
18994 #define F_CLR_ECC_INTR    V_CLR_ECC_INTR(1U)
19001 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
19002 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
19006 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
19007 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
19011 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
19012 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
19016 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
19017 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
19023 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
19024 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
19028 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
19029 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
19033 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
19034 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
19038 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
19039 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
19045 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
19046 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
19049 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
19050 #define F_DTU_WR_MULTI_RD    V_DTU_WR_MULTI_RD(1U)
19053 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
19054 #define F_DTU_DATA_MASK_EN    V_DTU_DATA_MASK_EN(1U)
19058 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
19059 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
19062 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
19063 #define F_DTU_GENERATE_RANDOM    V_DTU_GENERATE_RANDOM(1U)
19066 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
19067 #define F_DTU_INCR_BANKS    V_DTU_INCR_BANKS(1U)
19070 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
19071 #define F_DTU_INCR_COLS    V_DTU_INCR_COLS(1U)
19073 #define S_DTU_NALEN    1
19075 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
19076 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
19079 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
19080 #define F_DTU_ENABLE    V_DTU_ENABLE(1U)
19085 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
19086 #define F_WR_MULTI_RD_RST    V_WR_MULTI_RD_RST(1U)
19088 #define S_RUN_ERROR_REPORTS    1
19089 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
19090 #define F_RUN_ERROR_REPORTS    V_RUN_ERROR_REPORTS(1U)
19093 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
19094 #define F_RUN_DTU    V_RUN_DTU(1U)
19100 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
19101 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
19105 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
19106 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
19110 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
19111 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
19115 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
19116 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
19122 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
19123 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
19127 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
19128 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
19132 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
19133 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
19137 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
19138 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
19144 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
19145 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
19149 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
19150 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
19154 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
19155 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
19159 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
19160 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
19166 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
19167 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
19171 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
19172 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
19176 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
19177 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
19181 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
19182 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
19188 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
19189 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
19195 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
19196 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
19200 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
19201 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
19205 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
19206 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
19210 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
19211 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
19217 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
19218 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
19222 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
19223 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
19227 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
19228 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
19232 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
19233 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
19239 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
19240 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
19244 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
19245 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
19249 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
19250 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
19254 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
19255 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
19261 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
19262 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
19266 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
19267 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
19271 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
19272 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
19276 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
19277 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
19285 #define V_EA_RANK(x) ((x) << S_EA_RANK)
19286 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
19290 #define V_EA_ROW(x) ((x) << S_EA_ROW)
19291 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
19295 #define V_EA_BANK(x) ((x) << S_EA_BANK)
19296 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
19300 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
19301 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
19306 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
19307 #define F_PVT_UPD_REQ_EN    V_PVT_UPD_REQ_EN(1U)
19310 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
19311 #define F_PVT_UPD_TRIG_POL    V_PVT_UPD_TRIG_POL(1U)
19314 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
19315 #define F_PVT_UPD_TRIG_TYPE    V_PVT_UPD_TRIG_TYPE(1U)
19318 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
19319 #define F_PVT_UPD_DONE_POL    V_PVT_UPD_DONE_POL(1U)
19323 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
19324 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
19327 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
19328 #define F_PHY_UPD_REQ_EN    V_PHY_UPD_REQ_EN(1U)
19331 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
19332 #define F_PHY_UPD_TRIG_POL    V_PHY_UPD_TRIG_POL(1U)
19335 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
19336 #define F_PHY_UPD_TRIG_TYPE    V_PHY_UPD_TRIG_TYPE(1U)
19339 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
19340 #define F_PHY_UPD_DONE_POL    V_PHY_UPD_DONE_POL(1U)
19344 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
19345 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
19350 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
19351 #define F_I_PVT_UPD_TRIG    V_I_PVT_UPD_TRIG(1U)
19354 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
19355 #define F_I_PVT_UPD_DONE    V_I_PVT_UPD_DONE(1U)
19357 #define S_I_PHY_UPD_TRIG    1
19358 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
19359 #define F_I_PHY_UPD_TRIG    V_I_PHY_UPD_TRIG(1U)
19362 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
19363 #define F_I_PHY_UPD_DONE    V_I_PHY_UPD_DONE(1U)
19369 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
19370 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
19376 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
19377 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
19383 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
19384 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
19390 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
19391 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
19397 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
19398 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
19404 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
19405 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
19409 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
19410 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
19414 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
19415 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
19418 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
19419 #define F_DYN_SOC_ODT    V_DYN_SOC_ODT(1U)
19422 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
19423 #define F_SOC_ODT_EN    V_SOC_ODT_EN(1U)
19429 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
19430 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
19436 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
19437 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
19443 #define V_WLRANK(x) ((x) << S_WLRANK)
19444 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
19448 #define V_FDEPTH(x) ((x) << S_FDEPTH)
19449 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
19453 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
19454 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
19457 #define V_LPFEN(x) ((x) << S_LPFEN)
19458 #define F_LPFEN    V_LPFEN(1U)
19461 #define V_WL(x) ((x) << S_WL)
19462 #define F_WL    V_WL(1U)
19464 #define S_CAL    1
19465 #define V_CAL(x) ((x) << S_CAL)
19466 #define F_CAL    V_CAL(1U)
19469 #define V_MDLEN(x) ((x) << S_MDLEN)
19470 #define F_MDLEN    V_MDLEN(1U)
19475 #define V_OCPONR(x) ((x) << S_OCPONR)
19476 #define F_OCPONR    V_OCPONR(1U)
19479 #define V_OCPOND(x) ((x) << S_OCPOND)
19480 #define F_OCPOND    V_OCPOND(1U)
19483 #define V_OCOEN(x) ((x) << S_OCOEN)
19484 #define F_OCOEN    V_OCOEN(1U)
19487 #define V_CKEPONR(x) ((x) << S_CKEPONR)
19488 #define F_CKEPONR    V_CKEPONR(1U)
19491 #define V_CKEPOND(x) ((x) << S_CKEPOND)
19492 #define F_CKEPOND    V_CKEPOND(1U)
19495 #define V_CKEOEN(x) ((x) << S_CKEOEN)
19496 #define F_CKEOEN    V_CKEOEN(1U)
19499 #define V_CKPONR(x) ((x) << S_CKPONR)
19500 #define F_CKPONR    V_CKPONR(1U)
19502 #define S_CKPOND    1
19503 #define V_CKPOND(x) ((x) << S_CKPOND)
19504 #define F_CKPOND    V_CKPOND(1U)
19507 #define V_CKOEN(x) ((x) << S_CKOEN)
19508 #define F_CKOEN    V_CKOEN(1U)
19513 #define V_ACPONR(x) ((x) << S_ACPONR)
19514 #define F_ACPONR    V_ACPONR(1U)
19517 #define V_ACPOND(x) ((x) << S_ACPOND)
19518 #define F_ACPOND    V_ACPOND(1U)
19521 #define V_ACOEN(x) ((x) << S_ACOEN)
19522 #define F_ACOEN    V_ACOEN(1U)
19525 #define V_CK5PONR(x) ((x) << S_CK5PONR)
19526 #define F_CK5PONR    V_CK5PONR(1U)
19529 #define V_CK5POND(x) ((x) << S_CK5POND)
19530 #define F_CK5POND    V_CK5POND(1U)
19533 #define V_CK5OEN(x) ((x) << S_CK5OEN)
19534 #define F_CK5OEN    V_CK5OEN(1U)
19537 #define V_CK4PONR(x) ((x) << S_CK4PONR)
19538 #define F_CK4PONR    V_CK4PONR(1U)
19540 #define S_CK4POND    1
19541 #define V_CK4POND(x) ((x) << S_CK4POND)
19542 #define F_CK4POND    V_CK4POND(1U)
19545 #define V_CK4OEN(x) ((x) << S_CK4OEN)
19546 #define F_CK4OEN    V_CK4OEN(1U)
19551 #define V_WLERR(x) ((x) << S_WLERR)
19552 #define F_WLERR    V_WLERR(1U)
19555 #define V_INIT(x) ((x) << S_INIT)
19556 #define F_INIT    V_INIT(1U)
19559 #define V_ACCAL(x) ((x) << S_ACCAL)
19560 #define F_ACCAL    V_ACCAL(1U)
19564 #define S_WLDEC    1
19565 #define V_WLDEC(x) ((x) << S_WLDEC)
19566 #define F_WLDEC    V_WLDEC(1U)
19569 #define V_WLINC(x) ((x) << S_WLINC)
19570 #define F_WLINC    V_WLINC(1U)
19577 #define V_PRD(x) ((x) << S_PRD)
19578 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
19587 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
19588 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
19594 #define V_TSEL(x) ((x) << S_TSEL)
19595 #define F_TSEL    V_TSEL(1U)
19599 #define V_ISEL(x) ((x) << S_ISEL)
19600 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
19603 #define V_CALBYP(x) ((x) << S_CALBYP)
19604 #define F_CALBYP    V_CALBYP(1U)
19606 #define S_SDRSELINV    1
19607 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
19608 #define F_SDRSELINV    V_SDRSELINV(1U)
19611 #define V_CKINV(x) ((x) << S_CKINV)
19612 #define F_CKINV    V_CKINV(1U)
19618 #define V_PSCALE(x) ((x) << S_PSCALE)
19619 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
19624 #define V_PHYINIT(x) ((x) << S_PHYINIT)
19625 #define F_PHYINIT    V_PHYINIT(1U)
19628 #define V_PHYHRST(x) ((x) << S_PHYHRST)
19629 #define F_PHYHRST    V_PHYHRST(1U)
19633 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
19634 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
19637 #define V_PLLPD(x) ((x) << S_PLLPD)
19638 #define F_PLLPD    V_PLLPD(1U)
19640 #define S_PLLRST    1
19641 #define V_PLLRST(x) ((x) << S_PLLRST)
19642 #define F_PLLRST    V_PLLRST(1U)
19645 #define V_PHYRST(x) ((x) << S_PHYRST)
19646 #define F_PHYRST    V_PHYRST(1U)
19652 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
19653 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
19656 #define V_ICPSEL(x) ((x) << S_ICPSEL)
19657 #define F_ICPSEL    V_ICPSEL(1U)
19661 #define V_TESTA(x) ((x) << S_TESTA)
19662 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
19667 #define V_BYPASS(x) ((x) << S_BYPASS)
19668 #define F_BYPASS    V_BYPASS(1U)
19672 #define V_BDIV(x) ((x) << S_BDIV)
19673 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
19677 #define V_TESTD(x) ((x) << S_TESTD)
19678 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
19684 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
19685 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
19688 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
19689 #define F_HDRCLKEN    V_HDRCLKEN(1U)
19691 #define S_SDRCLKEN    1
19692 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
19693 #define F_SDRCLKEN    V_SDRCLKEN(1U)
19696 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
19697 #define F_DDRCLKEN    V_DDRCLKEN(1U)
19702 #define V_PONR(x) ((x) << S_PONR)
19703 #define F_PONR    V_PONR(1U)
19706 #define V_POND(x) ((x) << S_POND)
19707 #define F_POND    V_POND(1U)
19710 #define V_RDBDVT(x) ((x) << S_RDBDVT)
19711 #define F_RDBDVT    V_RDBDVT(1U)
19714 #define V_WDBDVT(x) ((x) << S_WDBDVT)
19715 #define F_WDBDVT    V_WDBDVT(1U)
19718 #define V_RDSDVT(x) ((x) << S_RDSDVT)
19719 #define F_RDSDVT    V_RDSDVT(1U)
19721 #define S_WDSDVT    1
19722 #define V_WDSDVT(x) ((x) << S_WDSDVT)
19723 #define F_WDSDVT    V_WDSDVT(1U)
19726 #define V_WLSDVT(x) ((x) << S_WLSDVT)
19727 #define F_WLSDVT    V_WLSDVT(1U)
19733 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
19734 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
19741 #define V_WL_DLY(x) ((x) << S_WL_DLY)
19742 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
19748 #define V_DLY(x) ((x) << S_DLY)
19749 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
19763 #define V_MAXDLY(x) ((x) << S_MAXDLY)
19764 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
19770 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
19771 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
19790 #define V_DP_DLY(x) ((x) << S_DP_DLY)
19791 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
19797 #define V_WLDONE(x) ((x) << S_WLDONE)
19798 #define F_WLDONE    V_WLDONE(1U)
19801 #define V_WLCAL(x) ((x) << S_WLCAL)
19802 #define F_WLCAL    V_WLCAL(1U)
19804 #define S_READ    1
19805 #define V_READ(x) ((x) << S_READ)
19806 #define F_READ    V_READ(1U)
19809 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
19810 #define F_RDQSCAL    V_RDQSCAL(1U)
19815 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
19816 #define F_PHYHSRST    V_PHYHSRST(1U)
19819 #define V_WLSTEP(x) ((x) << S_WLSTEP)
19820 #define F_WLSTEP    V_WLSTEP(1U)
19823 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
19824 #define F_SDR_SEL_INV    V_SDR_SEL_INV(1U)
19826 #define S_DDRSELINV    1
19827 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
19828 #define F_DDRSELINV    V_DDRSELINV(1U)
19831 #define V_DSINV(x) ((x) << S_DSINV)
19832 #define F_DSINV    V_DSINV(1U)
19837 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
19838 #define F_WLRANKSEL    V_WLRANKSEL(1U)
19842 #define V_RANK(x) ((x) << S_RANK)
19843 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
19849 #define V_DTOSEL(x) ((x) << S_DTOSEL)
19850 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
19875 #define S_DDRIO_ENABLE    1
19876 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
19877 #define F_DDRIO_ENABLE    V_DDRIO_ENABLE(1U)
19880 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
19881 #define F_PHY_RST_N    V_PHY_RST_N(1U)
19886 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
19887 #define F_STALL_CHK_BIT    V_STALL_CHK_BIT(1U)
19889 #define S_DDR3_BRC_MODE    1
19890 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
19891 #define F_DDR3_BRC_MODE    V_DDR3_BRC_MODE(1U)
19894 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
19895 #define F_RMW_PERF_CTRL    V_RMW_PERF_CTRL(1U)
19899 #define S_ECC_BYPASS_BIST    1
19900 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
19901 #define F_ECC_BYPASS_BIST    V_ECC_BYPASS_BIST(1U)
19904 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
19905 #define F_ECC_DISABLE    V_ECC_DISABLE(1U)
19910 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
19911 #define F_ECC_UE_PAR_ENABLE    V_ECC_UE_PAR_ENABLE(1U)
19914 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
19915 #define F_ECC_CE_PAR_ENABLE    V_ECC_CE_PAR_ENABLE(1U)
19917 #define S_PERR_REG_INT_ENABLE    1
19918 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
19919 #define F_PERR_REG_INT_ENABLE    V_PERR_REG_INT_ENABLE(1U)
19922 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
19923 #define F_PERR_BLK_INT_ENABLE    V_PERR_BLK_INT_ENABLE(1U)
19928 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
19929 #define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)
19932 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
19933 #define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)
19935 #define S_FIFOR_PAR_CAUSE    1
19936 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
19937 #define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)
19940 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
19941 #define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)
19946 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
19947 #define F_ECC_UE_INT_ENABLE    V_ECC_UE_INT_ENABLE(1U)
19949 #define S_ECC_CE_INT_ENABLE    1
19950 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
19951 #define F_ECC_CE_INT_ENABLE    V_ECC_CE_INT_ENABLE(1U)
19954 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
19955 #define F_PERR_INT_ENABLE    V_PERR_INT_ENABLE(1U)
19960 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
19961 #define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)
19963 #define S_ECC_CE_INT_CAUSE    1
19964 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
19965 #define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)
19968 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
19969 #define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)
19975 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
19976 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
19980 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
19981 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
19986 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
19987 #define F_CTLPHYRR    V_CTLPHYRR(1U)
19992 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
19993 #define F_STATIC_MODE    V_STATIC_MODE(1U)
19997 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
19998 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
20001 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
20002 #define F_STATIC_ORG    V_STATIC_ORG(1U)
20005 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
20006 #define F_STATIC_RKS    V_STATIC_RKS(1U)
20008 #define S_STATIC_WIDTH    1
20010 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
20011 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
20014 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
20015 #define F_STATIC_SLOW    V_STATIC_SLOW(1U)
20021 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
20022 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
20028 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
20029 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
20033 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
20034 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
20040 #define V_START_BIST(x) ((x) << S_START_BIST)
20041 #define F_START_BIST    V_START_BIST(1U)
20045 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
20046 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
20050 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
20051 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
20059 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
20060 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
20068 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
20069 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
20082 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
20083 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
20086 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
20087 #define F_THRESHOLD1_EN    V_THRESHOLD1_EN(1U)
20089 #define S_THRESHOLD0    1
20091 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
20092 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
20095 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
20096 #define F_THRESHOLD0_EN    V_THRESHOLD0_EN(1U)
20101 #define V_T7_THRESHOLD1_EN(x) ((x) << S_T7_THRESHOLD1_EN)
20102 #define F_T7_THRESHOLD1_EN    V_T7_THRESHOLD1_EN(1U)
20106 #define V_T7_THRESHOLD1(x) ((x) << S_T7_THRESHOLD1)
20107 #define G_T7_THRESHOLD1(x) (((x) >> S_T7_THRESHOLD1) & M_T7_THRESHOLD1)
20110 #define V_T7_THRESHOLD0_EN(x) ((x) << S_T7_THRESHOLD0_EN)
20111 #define F_T7_THRESHOLD0_EN    V_T7_THRESHOLD0_EN(1U)
20115 #define V_T7_THRESHOLD0(x) ((x) << S_T7_THRESHOLD0)
20116 #define G_T7_THRESHOLD0(x) (((x) >> S_T7_THRESHOLD0) & M_T7_THRESHOLD0)
20122 #define V_CREDITSHAPER_EN(x) ((x) << S_CREDITSHAPER_EN)
20123 #define F_CREDITSHAPER_EN    V_CREDITSHAPER_EN(1U)
20127 #define V_CREDIT_MAX(x) ((x) << S_CREDIT_MAX)
20128 #define G_CREDIT_MAX(x) (((x) >> S_CREDIT_MAX) & M_CREDIT_MAX)
20132 #define V_CREDIT_VAL(x) ((x) << S_CREDIT_VAL)
20133 #define G_CREDIT_VAL(x) (((x) >> S_CREDIT_VAL) & M_CREDIT_VAL)
20187 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
20188 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
20192 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
20193 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
20197 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
20198 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
20202 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
20203 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
20221 #define V_ARB4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR_EN)
20222 #define F_ARB4_COR_WRQUEUE_ERROR_EN    V_ARB4_COR_WRQUEUE_ERROR_EN(1U)
20225 #define V_ARB3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR_EN)
20226 #define F_ARB3_COR_WRQUEUE_ERROR_EN    V_ARB3_COR_WRQUEUE_ERROR_EN(1U)
20229 #define V_ARB2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR_EN)
20230 #define F_ARB2_COR_WRQUEUE_ERROR_EN    V_ARB2_COR_WRQUEUE_ERROR_EN(1U)
20233 #define V_ARB1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR_EN)
20234 #define F_ARB1_COR_WRQUEUE_ERROR_EN    V_ARB1_COR_WRQUEUE_ERROR_EN(1U)
20237 #define V_ARB0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR_EN)
20238 #define F_ARB0_COR_WRQUEUE_ERROR_EN    V_ARB0_COR_WRQUEUE_ERROR_EN(1U)
20241 #define V_ARB4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR_EN)
20242 #define F_ARB4_COR_RDQUEUE_ERROR_EN    V_ARB4_COR_RDQUEUE_ERROR_EN(1U)
20245 #define V_ARB3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR_EN)
20246 #define F_ARB3_COR_RDQUEUE_ERROR_EN    V_ARB3_COR_RDQUEUE_ERROR_EN(1U)
20249 #define V_ARB2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR_EN)
20250 #define F_ARB2_COR_RDQUEUE_ERROR_EN    V_ARB2_COR_RDQUEUE_ERROR_EN(1U)
20252 #define S_ARB1_COR_RDQUEUE_ERROR_EN    1
20253 #define V_ARB1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR_EN)
20254 #define F_ARB1_COR_RDQUEUE_ERROR_EN    V_ARB1_COR_RDQUEUE_ERROR_EN(1U)
20257 #define V_ARB0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR_EN)
20258 #define F_ARB0_COR_RDQUEUE_ERROR_EN    V_ARB0_COR_RDQUEUE_ERROR_EN(1U)
20263 #define V_ARB4_COR_WRQUEUE_ERROR(x) ((x) << S_ARB4_COR_WRQUEUE_ERROR)
20264 #define F_ARB4_COR_WRQUEUE_ERROR    V_ARB4_COR_WRQUEUE_ERROR(1U)
20267 #define V_ARB3_COR_WRQUEUE_ERROR(x) ((x) << S_ARB3_COR_WRQUEUE_ERROR)
20268 #define F_ARB3_COR_WRQUEUE_ERROR    V_ARB3_COR_WRQUEUE_ERROR(1U)
20271 #define V_ARB2_COR_WRQUEUE_ERROR(x) ((x) << S_ARB2_COR_WRQUEUE_ERROR)
20272 #define F_ARB2_COR_WRQUEUE_ERROR    V_ARB2_COR_WRQUEUE_ERROR(1U)
20275 #define V_ARB1_COR_WRQUEUE_ERROR(x) ((x) << S_ARB1_COR_WRQUEUE_ERROR)
20276 #define F_ARB1_COR_WRQUEUE_ERROR    V_ARB1_COR_WRQUEUE_ERROR(1U)
20279 #define V_ARB0_COR_WRQUEUE_ERROR(x) ((x) << S_ARB0_COR_WRQUEUE_ERROR)
20280 #define F_ARB0_COR_WRQUEUE_ERROR    V_ARB0_COR_WRQUEUE_ERROR(1U)
20283 #define V_ARB4_COR_RDQUEUE_ERROR(x) ((x) << S_ARB4_COR_RDQUEUE_ERROR)
20284 #define F_ARB4_COR_RDQUEUE_ERROR    V_ARB4_COR_RDQUEUE_ERROR(1U)
20287 #define V_ARB3_COR_RDQUEUE_ERROR(x) ((x) << S_ARB3_COR_RDQUEUE_ERROR)
20288 #define F_ARB3_COR_RDQUEUE_ERROR    V_ARB3_COR_RDQUEUE_ERROR(1U)
20291 #define V_ARB2_COR_RDQUEUE_ERROR(x) ((x) << S_ARB2_COR_RDQUEUE_ERROR)
20292 #define F_ARB2_COR_RDQUEUE_ERROR    V_ARB2_COR_RDQUEUE_ERROR(1U)
20294 #define S_ARB1_COR_RDQUEUE_ERROR    1
20295 #define V_ARB1_COR_RDQUEUE_ERROR(x) ((x) << S_ARB1_COR_RDQUEUE_ERROR)
20296 #define F_ARB1_COR_RDQUEUE_ERROR    V_ARB1_COR_RDQUEUE_ERROR(1U)
20299 #define V_ARB0_COR_RDQUEUE_ERROR(x) ((x) << S_ARB0_COR_RDQUEUE_ERROR)
20300 #define F_ARB0_COR_RDQUEUE_ERROR    V_ARB0_COR_RDQUEUE_ERROR(1U)
20305 #define V_DATAH_SEL(x) ((x) << S_DATAH_SEL)
20306 #define F_DATAH_SEL    V_DATAH_SEL(1U)
20309 #define V_EN_DBG(x) ((x) << S_EN_DBG)
20310 #define F_EN_DBG    V_EN_DBG(1U)
20314 #define V_T7_SEL(x) ((x) << S_T7_SEL)
20315 #define G_T7_SEL(x) (((x) >> S_T7_SEL) & M_T7_SEL)
20321 #define V_CL14_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_WRQUEUE_ERROR_EN)
20322 #define F_CL14_COR_WRQUEUE_ERROR_EN    V_CL14_COR_WRQUEUE_ERROR_EN(1U)
20325 #define V_CL13_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_WRQUEUE_ERROR_EN)
20326 #define F_CL13_COR_WRQUEUE_ERROR_EN    V_CL13_COR_WRQUEUE_ERROR_EN(1U)
20329 #define V_CL12_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_WRQUEUE_ERROR_EN)
20330 #define F_CL12_COR_WRQUEUE_ERROR_EN    V_CL12_COR_WRQUEUE_ERROR_EN(1U)
20333 #define V_CL11_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_WRQUEUE_ERROR_EN)
20334 #define F_CL11_COR_WRQUEUE_ERROR_EN    V_CL11_COR_WRQUEUE_ERROR_EN(1U)
20337 #define V_CL10_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_WRQUEUE_ERROR_EN)
20338 #define F_CL10_COR_WRQUEUE_ERROR_EN    V_CL10_COR_WRQUEUE_ERROR_EN(1U)
20341 #define V_CL9_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_WRQUEUE_ERROR_EN)
20342 #define F_CL9_COR_WRQUEUE_ERROR_EN    V_CL9_COR_WRQUEUE_ERROR_EN(1U)
20345 #define V_CL8_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_WRQUEUE_ERROR_EN)
20346 #define F_CL8_COR_WRQUEUE_ERROR_EN    V_CL8_COR_WRQUEUE_ERROR_EN(1U)
20349 #define V_CL7_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_WRQUEUE_ERROR_EN)
20350 #define F_CL7_COR_WRQUEUE_ERROR_EN    V_CL7_COR_WRQUEUE_ERROR_EN(1U)
20353 #define V_CL6_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_WRQUEUE_ERROR_EN)
20354 #define F_CL6_COR_WRQUEUE_ERROR_EN    V_CL6_COR_WRQUEUE_ERROR_EN(1U)
20357 #define V_CL5_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_WRQUEUE_ERROR_EN)
20358 #define F_CL5_COR_WRQUEUE_ERROR_EN    V_CL5_COR_WRQUEUE_ERROR_EN(1U)
20361 #define V_CL4_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_WRQUEUE_ERROR_EN)
20362 #define F_CL4_COR_WRQUEUE_ERROR_EN    V_CL4_COR_WRQUEUE_ERROR_EN(1U)
20365 #define V_CL3_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_WRQUEUE_ERROR_EN)
20366 #define F_CL3_COR_WRQUEUE_ERROR_EN    V_CL3_COR_WRQUEUE_ERROR_EN(1U)
20369 #define V_CL2_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_WRQUEUE_ERROR_EN)
20370 #define F_CL2_COR_WRQUEUE_ERROR_EN    V_CL2_COR_WRQUEUE_ERROR_EN(1U)
20372 #define S_CL1_COR_WRQUEUE_ERROR_EN    1
20373 #define V_CL1_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_WRQUEUE_ERROR_EN)
20374 #define F_CL1_COR_WRQUEUE_ERROR_EN    V_CL1_COR_WRQUEUE_ERROR_EN(1U)
20377 #define V_CL0_COR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_WRQUEUE_ERROR_EN)
20378 #define F_CL0_COR_WRQUEUE_ERROR_EN    V_CL0_COR_WRQUEUE_ERROR_EN(1U)
20383 #define V_CL14_COR_WRQUEUE_ERROR(x) ((x) << S_CL14_COR_WRQUEUE_ERROR)
20384 #define F_CL14_COR_WRQUEUE_ERROR    V_CL14_COR_WRQUEUE_ERROR(1U)
20387 #define V_CL13_COR_WRQUEUE_ERROR(x) ((x) << S_CL13_COR_WRQUEUE_ERROR)
20388 #define F_CL13_COR_WRQUEUE_ERROR    V_CL13_COR_WRQUEUE_ERROR(1U)
20391 #define V_CL12_COR_WRQUEUE_ERROR(x) ((x) << S_CL12_COR_WRQUEUE_ERROR)
20392 #define F_CL12_COR_WRQUEUE_ERROR    V_CL12_COR_WRQUEUE_ERROR(1U)
20395 #define V_CL11_COR_WRQUEUE_ERROR(x) ((x) << S_CL11_COR_WRQUEUE_ERROR)
20396 #define F_CL11_COR_WRQUEUE_ERROR    V_CL11_COR_WRQUEUE_ERROR(1U)
20399 #define V_CL10_COR_WRQUEUE_ERROR(x) ((x) << S_CL10_COR_WRQUEUE_ERROR)
20400 #define F_CL10_COR_WRQUEUE_ERROR    V_CL10_COR_WRQUEUE_ERROR(1U)
20403 #define V_CL9_COR_WRQUEUE_ERROR(x) ((x) << S_CL9_COR_WRQUEUE_ERROR)
20404 #define F_CL9_COR_WRQUEUE_ERROR    V_CL9_COR_WRQUEUE_ERROR(1U)
20407 #define V_CL8_COR_WRQUEUE_ERROR(x) ((x) << S_CL8_COR_WRQUEUE_ERROR)
20408 #define F_CL8_COR_WRQUEUE_ERROR    V_CL8_COR_WRQUEUE_ERROR(1U)
20411 #define V_CL7_COR_WRQUEUE_ERROR(x) ((x) << S_CL7_COR_WRQUEUE_ERROR)
20412 #define F_CL7_COR_WRQUEUE_ERROR    V_CL7_COR_WRQUEUE_ERROR(1U)
20415 #define V_CL6_COR_WRQUEUE_ERROR(x) ((x) << S_CL6_COR_WRQUEUE_ERROR)
20416 #define F_CL6_COR_WRQUEUE_ERROR    V_CL6_COR_WRQUEUE_ERROR(1U)
20419 #define V_CL5_COR_WRQUEUE_ERROR(x) ((x) << S_CL5_COR_WRQUEUE_ERROR)
20420 #define F_CL5_COR_WRQUEUE_ERROR    V_CL5_COR_WRQUEUE_ERROR(1U)
20423 #define V_CL4_COR_WRQUEUE_ERROR(x) ((x) << S_CL4_COR_WRQUEUE_ERROR)
20424 #define F_CL4_COR_WRQUEUE_ERROR    V_CL4_COR_WRQUEUE_ERROR(1U)
20427 #define V_CL3_COR_WRQUEUE_ERROR(x) ((x) << S_CL3_COR_WRQUEUE_ERROR)
20428 #define F_CL3_COR_WRQUEUE_ERROR    V_CL3_COR_WRQUEUE_ERROR(1U)
20431 #define V_CL2_COR_WRQUEUE_ERROR(x) ((x) << S_CL2_COR_WRQUEUE_ERROR)
20432 #define F_CL2_COR_WRQUEUE_ERROR    V_CL2_COR_WRQUEUE_ERROR(1U)
20434 #define S_CL1_COR_WRQUEUE_ERROR    1
20435 #define V_CL1_COR_WRQUEUE_ERROR(x) ((x) << S_CL1_COR_WRQUEUE_ERROR)
20436 #define F_CL1_COR_WRQUEUE_ERROR    V_CL1_COR_WRQUEUE_ERROR(1U)
20439 #define V_CL0_COR_WRQUEUE_ERROR(x) ((x) << S_CL0_COR_WRQUEUE_ERROR)
20440 #define F_CL0_COR_WRQUEUE_ERROR    V_CL0_COR_WRQUEUE_ERROR(1U)
20445 #define V_CL14_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_COR_RDQUEUE_ERROR_EN)
20446 #define F_CL14_COR_RDQUEUE_ERROR_EN    V_CL14_COR_RDQUEUE_ERROR_EN(1U)
20449 #define V_CL13_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_COR_RDQUEUE_ERROR_EN)
20450 #define F_CL13_COR_RDQUEUE_ERROR_EN    V_CL13_COR_RDQUEUE_ERROR_EN(1U)
20453 #define V_CL12_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_COR_RDQUEUE_ERROR_EN)
20454 #define F_CL12_COR_RDQUEUE_ERROR_EN    V_CL12_COR_RDQUEUE_ERROR_EN(1U)
20457 #define V_CL11_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_COR_RDQUEUE_ERROR_EN)
20458 #define F_CL11_COR_RDQUEUE_ERROR_EN    V_CL11_COR_RDQUEUE_ERROR_EN(1U)
20461 #define V_CL10_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_COR_RDQUEUE_ERROR_EN)
20462 #define F_CL10_COR_RDQUEUE_ERROR_EN    V_CL10_COR_RDQUEUE_ERROR_EN(1U)
20465 #define V_CL9_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_COR_RDQUEUE_ERROR_EN)
20466 #define F_CL9_COR_RDQUEUE_ERROR_EN    V_CL9_COR_RDQUEUE_ERROR_EN(1U)
20469 #define V_CL8_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_COR_RDQUEUE_ERROR_EN)
20470 #define F_CL8_COR_RDQUEUE_ERROR_EN    V_CL8_COR_RDQUEUE_ERROR_EN(1U)
20473 #define V_CL7_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_COR_RDQUEUE_ERROR_EN)
20474 #define F_CL7_COR_RDQUEUE_ERROR_EN    V_CL7_COR_RDQUEUE_ERROR_EN(1U)
20477 #define V_CL6_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_COR_RDQUEUE_ERROR_EN)
20478 #define F_CL6_COR_RDQUEUE_ERROR_EN    V_CL6_COR_RDQUEUE_ERROR_EN(1U)
20481 #define V_CL5_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_COR_RDQUEUE_ERROR_EN)
20482 #define F_CL5_COR_RDQUEUE_ERROR_EN    V_CL5_COR_RDQUEUE_ERROR_EN(1U)
20485 #define V_CL4_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_COR_RDQUEUE_ERROR_EN)
20486 #define F_CL4_COR_RDQUEUE_ERROR_EN    V_CL4_COR_RDQUEUE_ERROR_EN(1U)
20489 #define V_CL3_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_COR_RDQUEUE_ERROR_EN)
20490 #define F_CL3_COR_RDQUEUE_ERROR_EN    V_CL3_COR_RDQUEUE_ERROR_EN(1U)
20493 #define V_CL2_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_COR_RDQUEUE_ERROR_EN)
20494 #define F_CL2_COR_RDQUEUE_ERROR_EN    V_CL2_COR_RDQUEUE_ERROR_EN(1U)
20496 #define S_CL1_COR_RDQUEUE_ERROR_EN    1
20497 #define V_CL1_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_COR_RDQUEUE_ERROR_EN)
20498 #define F_CL1_COR_RDQUEUE_ERROR_EN    V_CL1_COR_RDQUEUE_ERROR_EN(1U)
20501 #define V_CL0_COR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_COR_RDQUEUE_ERROR_EN)
20502 #define F_CL0_COR_RDQUEUE_ERROR_EN    V_CL0_COR_RDQUEUE_ERROR_EN(1U)
20507 #define V_CL14_COR_RDQUEUE_ERROR(x) ((x) << S_CL14_COR_RDQUEUE_ERROR)
20508 #define F_CL14_COR_RDQUEUE_ERROR    V_CL14_COR_RDQUEUE_ERROR(1U)
20511 #define V_CL13_COR_RDQUEUE_ERROR(x) ((x) << S_CL13_COR_RDQUEUE_ERROR)
20512 #define F_CL13_COR_RDQUEUE_ERROR    V_CL13_COR_RDQUEUE_ERROR(1U)
20515 #define V_CL12_COR_RDQUEUE_ERROR(x) ((x) << S_CL12_COR_RDQUEUE_ERROR)
20516 #define F_CL12_COR_RDQUEUE_ERROR    V_CL12_COR_RDQUEUE_ERROR(1U)
20519 #define V_CL11_COR_RDQUEUE_ERROR(x) ((x) << S_CL11_COR_RDQUEUE_ERROR)
20520 #define F_CL11_COR_RDQUEUE_ERROR    V_CL11_COR_RDQUEUE_ERROR(1U)
20523 #define V_CL10_COR_RDQUEUE_ERROR(x) ((x) << S_CL10_COR_RDQUEUE_ERROR)
20524 #define F_CL10_COR_RDQUEUE_ERROR    V_CL10_COR_RDQUEUE_ERROR(1U)
20527 #define V_CL9_COR_RDQUEUE_ERROR(x) ((x) << S_CL9_COR_RDQUEUE_ERROR)
20528 #define F_CL9_COR_RDQUEUE_ERROR    V_CL9_COR_RDQUEUE_ERROR(1U)
20531 #define V_CL8_COR_RDQUEUE_ERROR(x) ((x) << S_CL8_COR_RDQUEUE_ERROR)
20532 #define F_CL8_COR_RDQUEUE_ERROR    V_CL8_COR_RDQUEUE_ERROR(1U)
20535 #define V_CL7_COR_RDQUEUE_ERROR(x) ((x) << S_CL7_COR_RDQUEUE_ERROR)
20536 #define F_CL7_COR_RDQUEUE_ERROR    V_CL7_COR_RDQUEUE_ERROR(1U)
20539 #define V_CL6_COR_RDQUEUE_ERROR(x) ((x) << S_CL6_COR_RDQUEUE_ERROR)
20540 #define F_CL6_COR_RDQUEUE_ERROR    V_CL6_COR_RDQUEUE_ERROR(1U)
20543 #define V_CL5_COR_RDQUEUE_ERROR(x) ((x) << S_CL5_COR_RDQUEUE_ERROR)
20544 #define F_CL5_COR_RDQUEUE_ERROR    V_CL5_COR_RDQUEUE_ERROR(1U)
20547 #define V_CL4_COR_RDQUEUE_ERROR(x) ((x) << S_CL4_COR_RDQUEUE_ERROR)
20548 #define F_CL4_COR_RDQUEUE_ERROR    V_CL4_COR_RDQUEUE_ERROR(1U)
20551 #define V_CL3_COR_RDQUEUE_ERROR(x) ((x) << S_CL3_COR_RDQUEUE_ERROR)
20552 #define F_CL3_COR_RDQUEUE_ERROR    V_CL3_COR_RDQUEUE_ERROR(1U)
20555 #define V_CL2_COR_RDQUEUE_ERROR(x) ((x) << S_CL2_COR_RDQUEUE_ERROR)
20556 #define F_CL2_COR_RDQUEUE_ERROR    V_CL2_COR_RDQUEUE_ERROR(1U)
20558 #define S_CL1_COR_RDQUEUE_ERROR    1
20559 #define V_CL1_COR_RDQUEUE_ERROR(x) ((x) << S_CL1_COR_RDQUEUE_ERROR)
20560 #define F_CL1_COR_RDQUEUE_ERROR    V_CL1_COR_RDQUEUE_ERROR(1U)
20563 #define V_CL0_COR_RDQUEUE_ERROR(x) ((x) << S_CL0_COR_RDQUEUE_ERROR)
20564 #define F_CL0_COR_RDQUEUE_ERROR    V_CL0_COR_RDQUEUE_ERROR(1U)
20570 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
20571 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
20575 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
20576 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
20580 #define V_T7_EDRAM0_BASE(x) ((x) << S_T7_EDRAM0_BASE)
20581 #define G_T7_EDRAM0_BASE(x) (((x) >> S_T7_EDRAM0_BASE) & M_T7_EDRAM0_BASE)
20585 #define V_T7_EDRAM0_SIZE(x) ((x) << S_T7_EDRAM0_SIZE)
20586 #define G_T7_EDRAM0_SIZE(x) (((x) >> S_T7_EDRAM0_SIZE) & M_T7_EDRAM0_SIZE)
20592 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
20593 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
20597 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
20598 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
20602 #define V_T7_EDRAM1_BASE(x) ((x) << S_T7_EDRAM1_BASE)
20603 #define G_T7_EDRAM1_BASE(x) (((x) >> S_T7_EDRAM1_BASE) & M_T7_EDRAM1_BASE)
20607 #define V_T7_EDRAM1_SIZE(x) ((x) << S_T7_EDRAM1_SIZE)
20608 #define G_T7_EDRAM1_SIZE(x) (((x) >> S_T7_EDRAM1_SIZE) & M_T7_EDRAM1_SIZE)
20614 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
20615 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
20619 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
20620 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
20626 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
20627 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
20631 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
20632 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
20636 #define V_T7_EXT_MEM0_BASE(x) ((x) << S_T7_EXT_MEM0_BASE)
20637 #define G_T7_EXT_MEM0_BASE(x) (((x) >> S_T7_EXT_MEM0_BASE) & M_T7_EXT_MEM0_BASE)
20641 #define V_T7_EXT_MEM0_SIZE(x) ((x) << S_T7_EXT_MEM0_SIZE)
20642 #define G_T7_EXT_MEM0_SIZE(x) (((x) >> S_T7_EXT_MEM0_SIZE) & M_T7_EXT_MEM0_SIZE)
20648 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
20649 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
20653 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
20654 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
20658 #define V_HMATARGETBASE(x) ((x) << S_HMATARGETBASE)
20659 #define G_HMATARGETBASE(x) (((x) >> S_HMATARGETBASE) & M_HMATARGETBASE)
20663 #define V_T7_HMA_SIZE(x) ((x) << S_T7_HMA_SIZE)
20664 #define G_T7_HMA_SIZE(x) (((x) >> S_T7_HMA_SIZE) & M_T7_HMA_SIZE)
20669 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
20670 #define F_BRC_MODE    V_BRC_MODE(1U)
20674 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
20675 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
20678 #define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
20679 #define F_BRC_MODE1    V_BRC_MODE1(1U)
20683 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
20684 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
20687 #define V_BRBC_MODE(x) ((x) << S_BRBC_MODE)
20688 #define F_BRBC_MODE    V_BRBC_MODE(1U)
20691 #define V_T6_BRC_MODE(x) ((x) << S_T6_BRC_MODE)
20692 #define F_T6_BRC_MODE    V_T6_BRC_MODE(1U)
20696 #define V_T6_EXT_MEM_PAGE_SIZE(x) ((x) << S_T6_EXT_MEM_PAGE_SIZE)
20697 #define G_T6_EXT_MEM_PAGE_SIZE(x) (((x) >> S_T6_EXT_MEM_PAGE_SIZE) & M_T6_EXT_MEM_PAGE_SIZE)
20701 #define S_DIS_PAGE_HINT    1
20702 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
20703 #define F_DIS_PAGE_HINT    V_DIS_PAGE_HINT(1U)
20706 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
20707 #define F_DIS_ADV_ARB    V_DIS_ADV_ARB(1U)
20710 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
20711 #define F_DIS_BANK_FAIR    V_DIS_BANK_FAIR(1U)
20714 #define V_HMA_WRT_EN(x) ((x) << S_HMA_WRT_EN)
20715 #define F_HMA_WRT_EN    V_HMA_WRT_EN(1U)
20719 #define V_HMA_NUM_PG_128B_FDBK(x) ((x) << S_HMA_NUM_PG_128B_FDBK)
20720 #define G_HMA_NUM_PG_128B_FDBK(x) (((x) >> S_HMA_NUM_PG_128B_FDBK) & M_HMA_NUM_PG_128B_FDBK)
20723 #define V_HMA_DIS_128B_PG_CNT_FDBK(x) ((x) << S_HMA_DIS_128B_PG_CNT_FDBK)
20724 #define F_HMA_DIS_128B_PG_CNT_FDBK    V_HMA_DIS_128B_PG_CNT_FDBK(1U)
20727 #define V_HMA_DIS_BG_ARB(x) ((x) << S_HMA_DIS_BG_ARB)
20728 #define F_HMA_DIS_BG_ARB    V_HMA_DIS_BG_ARB(1U)
20731 #define V_HMA_DIS_BANK_FAIR(x) ((x) << S_HMA_DIS_BANK_FAIR)
20732 #define F_HMA_DIS_BANK_FAIR    V_HMA_DIS_BANK_FAIR(1U)
20735 #define V_HMA_DIS_PAGE_HINT(x) ((x) << S_HMA_DIS_PAGE_HINT)
20736 #define F_HMA_DIS_PAGE_HINT    V_HMA_DIS_PAGE_HINT(1U)
20739 #define V_HMA_DIS_ADV_ARB(x) ((x) << S_HMA_DIS_ADV_ARB)
20740 #define F_HMA_DIS_ADV_ARB    V_HMA_DIS_ADV_ARB(1U)
20744 #define V_NUM_PG_128B_FDBK(x) ((x) << S_NUM_PG_128B_FDBK)
20745 #define G_NUM_PG_128B_FDBK(x) (((x) >> S_NUM_PG_128B_FDBK) & M_NUM_PG_128B_FDBK)
20748 #define V_DIS_128B_PG_CNT_FDBK(x) ((x) << S_DIS_128B_PG_CNT_FDBK)
20749 #define F_DIS_128B_PG_CNT_FDBK    V_DIS_128B_PG_CNT_FDBK(1U)
20752 #define V_DIS_BG_ARB(x) ((x) << S_DIS_BG_ARB)
20753 #define F_DIS_BG_ARB    V_DIS_BG_ARB(1U)
20758 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
20759 #define F_HMA_ENABLE    V_HMA_ENABLE(1U)
20762 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
20763 #define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)
20765 #define S_EDRAM1_ENABLE    1
20766 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
20767 #define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)
20770 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
20771 #define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)
20774 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
20775 #define F_HMA_MUX    V_HMA_MUX(1U)
20778 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
20779 #define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)
20782 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
20783 #define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
20786 #define V_MC_SPLIT(x) ((x) << S_MC_SPLIT)
20787 #define F_MC_SPLIT    V_MC_SPLIT(1U)
20790 #define V_EDC512(x) ((x) << S_EDC512)
20791 #define F_EDC512    V_EDC512(1U)
20794 #define V_MC_SPLIT_BOUNDARY(x) ((x) << S_MC_SPLIT_BOUNDARY)
20795 #define F_MC_SPLIT_BOUNDARY    V_MC_SPLIT_BOUNDARY(1U)
20799 #define S_MEM_PERR_INT_ENABLE    1
20800 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
20801 #define F_MEM_PERR_INT_ENABLE    V_MEM_PERR_INT_ENABLE(1U)
20804 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
20805 #define F_MEM_WRAP_INT_ENABLE    V_MEM_WRAP_INT_ENABLE(1U)
20808 #define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
20809 #define F_MEM_TO_INT_ENABLE    V_MEM_TO_INT_ENABLE(1U)
20813 #define S_MEM_PERR_INT_CAUSE    1
20814 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
20815 #define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)
20818 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
20819 #define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)
20822 #define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
20823 #define F_MEM_TO_INT_CAUSE    V_MEM_TO_INT_CAUSE(1U)
20829 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
20830 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
20834 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
20835 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
20841 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
20842 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
20848 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
20849 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
20854 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
20855 #define F_TP_DMARBT_PAR_ERROR_EN    V_TP_DMARBT_PAR_ERROR_EN(1U)
20858 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
20859 #define F_LOGIC_FIFO_PAR_ERROR_EN    V_LOGIC_FIFO_PAR_ERROR_EN(1U)
20862 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
20863 #define F_ARB3_PAR_WRQUEUE_ERROR_EN    V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
20866 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
20867 #define F_ARB2_PAR_WRQUEUE_ERROR_EN    V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
20870 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
20871 #define F_ARB1_PAR_WRQUEUE_ERROR_EN    V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
20874 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
20875 #define F_ARB0_PAR_WRQUEUE_ERROR_EN    V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
20878 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
20879 #define F_ARB3_PAR_RDQUEUE_ERROR_EN    V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
20882 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
20883 #define F_ARB2_PAR_RDQUEUE_ERROR_EN    V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
20886 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
20887 #define F_ARB1_PAR_RDQUEUE_ERROR_EN    V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
20890 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
20891 #define F_ARB0_PAR_RDQUEUE_ERROR_EN    V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
20894 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
20895 #define F_CL10_PAR_WRQUEUE_ERROR_EN    V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
20898 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
20899 #define F_CL9_PAR_WRQUEUE_ERROR_EN    V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
20902 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
20903 #define F_CL8_PAR_WRQUEUE_ERROR_EN    V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
20906 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
20907 #define F_CL7_PAR_WRQUEUE_ERROR_EN    V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
20910 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
20911 #define F_CL6_PAR_WRQUEUE_ERROR_EN    V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
20914 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
20915 #define F_CL5_PAR_WRQUEUE_ERROR_EN    V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
20918 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
20919 #define F_CL4_PAR_WRQUEUE_ERROR_EN    V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
20922 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
20923 #define F_CL3_PAR_WRQUEUE_ERROR_EN    V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
20926 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
20927 #define F_CL2_PAR_WRQUEUE_ERROR_EN    V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
20930 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
20931 #define F_CL1_PAR_WRQUEUE_ERROR_EN    V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
20934 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
20935 #define F_CL0_PAR_WRQUEUE_ERROR_EN    V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
20938 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
20939 #define F_CL10_PAR_RDQUEUE_ERROR_EN    V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
20942 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
20943 #define F_CL9_PAR_RDQUEUE_ERROR_EN    V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
20946 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
20947 #define F_CL8_PAR_RDQUEUE_ERROR_EN    V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
20950 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
20951 #define F_CL7_PAR_RDQUEUE_ERROR_EN    V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
20954 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
20955 #define F_CL6_PAR_RDQUEUE_ERROR_EN    V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
20958 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
20959 #define F_CL5_PAR_RDQUEUE_ERROR_EN    V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
20962 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
20963 #define F_CL4_PAR_RDQUEUE_ERROR_EN    V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
20966 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
20967 #define F_CL3_PAR_RDQUEUE_ERROR_EN    V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
20970 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
20971 #define F_CL2_PAR_RDQUEUE_ERROR_EN    V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
20973 #define S_CL1_PAR_RDQUEUE_ERROR_EN    1
20974 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
20975 #define F_CL1_PAR_RDQUEUE_ERROR_EN    V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
20978 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
20979 #define F_CL0_PAR_RDQUEUE_ERROR_EN    V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
20984 #define V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR_EN)
20985 #define F_T7_ARB4_PAR_WRQUEUE_ERROR_EN    V_T7_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
20988 #define V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR_EN)
20989 #define F_T7_ARB3_PAR_WRQUEUE_ERROR_EN    V_T7_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
20992 #define V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR_EN)
20993 #define F_T7_ARB2_PAR_WRQUEUE_ERROR_EN    V_T7_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
20996 #define V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR_EN)
20997 #define F_T7_ARB1_PAR_WRQUEUE_ERROR_EN    V_T7_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
21000 #define V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR_EN)
21001 #define F_T7_ARB0_PAR_WRQUEUE_ERROR_EN    V_T7_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
21004 #define V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR_EN)
21005 #define F_T7_ARB4_PAR_RDQUEUE_ERROR_EN    V_T7_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
21008 #define V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR_EN)
21009 #define F_T7_ARB3_PAR_RDQUEUE_ERROR_EN    V_T7_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
21012 #define V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR_EN)
21013 #define F_T7_ARB2_PAR_RDQUEUE_ERROR_EN    V_T7_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
21016 #define V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR_EN)
21017 #define F_T7_ARB1_PAR_RDQUEUE_ERROR_EN    V_T7_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
21020 #define V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR_EN)
21021 #define F_T7_ARB0_PAR_RDQUEUE_ERROR_EN    V_T7_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
21023 #define S_T7_TP_DMARBT_PAR_ERROR_EN    1
21024 #define V_T7_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR_EN)
21025 #define F_T7_TP_DMARBT_PAR_ERROR_EN    V_T7_TP_DMARBT_PAR_ERROR_EN(1U)
21028 #define V_T7_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR_EN)
21029 #define F_T7_LOGIC_FIFO_PAR_ERROR_EN    V_T7_LOGIC_FIFO_PAR_ERROR_EN(1U)
21034 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
21035 #define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)
21038 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
21039 #define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)
21042 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
21043 #define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)
21046 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
21047 #define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)
21050 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
21051 #define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)
21054 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
21055 #define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)
21058 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
21059 #define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)
21062 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
21063 #define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)
21066 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
21067 #define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)
21070 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
21071 #define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)
21074 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
21075 #define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)
21078 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
21079 #define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)
21082 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
21083 #define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)
21086 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
21087 #define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)
21090 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
21091 #define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)
21094 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
21095 #define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)
21098 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
21099 #define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)
21102 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
21103 #define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)
21106 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
21107 #define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)
21110 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
21111 #define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)
21114 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
21115 #define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)
21118 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
21119 #define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)
21122 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
21123 #define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)
21126 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
21127 #define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)
21130 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
21131 #define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)
21134 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
21135 #define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)
21138 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
21139 #define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)
21142 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
21143 #define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)
21146 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
21147 #define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)
21150 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
21151 #define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)
21153 #define S_CL1_PAR_RDQUEUE_ERROR    1
21154 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
21155 #define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)
21158 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
21159 #define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
21164 #define V_T7_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_WRQUEUE_ERROR)
21165 #define F_T7_ARB4_PAR_WRQUEUE_ERROR    V_T7_ARB4_PAR_WRQUEUE_ERROR(1U)
21168 #define V_T7_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_WRQUEUE_ERROR)
21169 #define F_T7_ARB3_PAR_WRQUEUE_ERROR    V_T7_ARB3_PAR_WRQUEUE_ERROR(1U)
21172 #define V_T7_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_WRQUEUE_ERROR)
21173 #define F_T7_ARB2_PAR_WRQUEUE_ERROR    V_T7_ARB2_PAR_WRQUEUE_ERROR(1U)
21176 #define V_T7_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_WRQUEUE_ERROR)
21177 #define F_T7_ARB1_PAR_WRQUEUE_ERROR    V_T7_ARB1_PAR_WRQUEUE_ERROR(1U)
21180 #define V_T7_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_WRQUEUE_ERROR)
21181 #define F_T7_ARB0_PAR_WRQUEUE_ERROR    V_T7_ARB0_PAR_WRQUEUE_ERROR(1U)
21184 #define V_T7_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB4_PAR_RDQUEUE_ERROR)
21185 #define F_T7_ARB4_PAR_RDQUEUE_ERROR    V_T7_ARB4_PAR_RDQUEUE_ERROR(1U)
21188 #define V_T7_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB3_PAR_RDQUEUE_ERROR)
21189 #define F_T7_ARB3_PAR_RDQUEUE_ERROR    V_T7_ARB3_PAR_RDQUEUE_ERROR(1U)
21192 #define V_T7_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB2_PAR_RDQUEUE_ERROR)
21193 #define F_T7_ARB2_PAR_RDQUEUE_ERROR    V_T7_ARB2_PAR_RDQUEUE_ERROR(1U)
21196 #define V_T7_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB1_PAR_RDQUEUE_ERROR)
21197 #define F_T7_ARB1_PAR_RDQUEUE_ERROR    V_T7_ARB1_PAR_RDQUEUE_ERROR(1U)
21200 #define V_T7_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_T7_ARB0_PAR_RDQUEUE_ERROR)
21201 #define F_T7_ARB0_PAR_RDQUEUE_ERROR    V_T7_ARB0_PAR_RDQUEUE_ERROR(1U)
21203 #define S_T7_TP_DMARBT_PAR_ERROR    1
21204 #define V_T7_TP_DMARBT_PAR_ERROR(x) ((x) << S_T7_TP_DMARBT_PAR_ERROR)
21205 #define F_T7_TP_DMARBT_PAR_ERROR    V_T7_TP_DMARBT_PAR_ERROR(1U)
21208 #define V_T7_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_T7_LOGIC_FIFO_PAR_ERROR)
21209 #define F_T7_LOGIC_FIFO_PAR_ERROR    V_T7_LOGIC_FIFO_PAR_ERROR(1U)
21215 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
21216 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
21220 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
21221 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
21223 #define S_COHERANCY_THREAD_NUM    1
21225 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
21226 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
21229 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
21230 #define F_COHERANCY_ENABLE    V_COHERANCY_ENABLE(1U)
21235 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
21236 #define F_UE_ENABLE    V_UE_ENABLE(1U)
21238 #define S_FUTURE_EXPANSION    1
21240 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
21241 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
21243 #define S_FUTURE_EXPANSION_EE    1
21245 #define V_FUTURE_EXPANSION_EE(x) ((x) << S_FUTURE_EXPANSION_EE)
21246 #define G_FUTURE_EXPANSION_EE(x) (((x) >> S_FUTURE_EXPANSION_EE) & M_FUTURE_EXPANSION_EE)
21250 #define S_ARB4_PAR_WRQUEUE_ERROR_EN    1
21251 #define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
21252 #define F_ARB4_PAR_WRQUEUE_ERROR_EN    V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
21255 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
21256 #define F_ARB4_PAR_RDQUEUE_ERROR_EN    V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
21259 #define V_CL14_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR_EN)
21260 #define F_CL14_PAR_WRQUEUE_ERROR_EN    V_CL14_PAR_WRQUEUE_ERROR_EN(1U)
21263 #define V_CL13_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR_EN)
21264 #define F_CL13_PAR_WRQUEUE_ERROR_EN    V_CL13_PAR_WRQUEUE_ERROR_EN(1U)
21267 #define V_CL12_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR_EN)
21268 #define F_CL12_PAR_WRQUEUE_ERROR_EN    V_CL12_PAR_WRQUEUE_ERROR_EN(1U)
21271 #define V_CL11_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR_EN)
21272 #define F_CL11_PAR_WRQUEUE_ERROR_EN    V_CL11_PAR_WRQUEUE_ERROR_EN(1U)
21275 #define V_T7_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR_EN)
21276 #define F_T7_CL10_PAR_WRQUEUE_ERROR_EN    V_T7_CL10_PAR_WRQUEUE_ERROR_EN(1U)
21279 #define V_T7_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR_EN)
21280 #define F_T7_CL9_PAR_WRQUEUE_ERROR_EN    V_T7_CL9_PAR_WRQUEUE_ERROR_EN(1U)
21283 #define V_T7_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR_EN)
21284 #define F_T7_CL8_PAR_WRQUEUE_ERROR_EN    V_T7_CL8_PAR_WRQUEUE_ERROR_EN(1U)
21287 #define V_T7_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR_EN)
21288 #define F_T7_CL7_PAR_WRQUEUE_ERROR_EN    V_T7_CL7_PAR_WRQUEUE_ERROR_EN(1U)
21291 #define V_T7_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR_EN)
21292 #define F_T7_CL6_PAR_WRQUEUE_ERROR_EN    V_T7_CL6_PAR_WRQUEUE_ERROR_EN(1U)
21295 #define V_T7_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR_EN)
21296 #define F_T7_CL5_PAR_WRQUEUE_ERROR_EN    V_T7_CL5_PAR_WRQUEUE_ERROR_EN(1U)
21299 #define V_T7_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR_EN)
21300 #define F_T7_CL4_PAR_WRQUEUE_ERROR_EN    V_T7_CL4_PAR_WRQUEUE_ERROR_EN(1U)
21303 #define V_T7_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR_EN)
21304 #define F_T7_CL3_PAR_WRQUEUE_ERROR_EN    V_T7_CL3_PAR_WRQUEUE_ERROR_EN(1U)
21307 #define V_T7_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR_EN)
21308 #define F_T7_CL2_PAR_WRQUEUE_ERROR_EN    V_T7_CL2_PAR_WRQUEUE_ERROR_EN(1U)
21310 #define S_T7_CL1_PAR_WRQUEUE_ERROR_EN    1
21311 #define V_T7_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR_EN)
21312 #define F_T7_CL1_PAR_WRQUEUE_ERROR_EN    V_T7_CL1_PAR_WRQUEUE_ERROR_EN(1U)
21315 #define V_T7_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR_EN)
21316 #define F_T7_CL0_PAR_WRQUEUE_ERROR_EN    V_T7_CL0_PAR_WRQUEUE_ERROR_EN(1U)
21320 #define S_ARB4_PAR_WRQUEUE_ERROR    1
21321 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
21322 #define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)
21325 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
21326 #define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
21329 #define V_CL14_PAR_WRQUEUE_ERROR(x) ((x) << S_CL14_PAR_WRQUEUE_ERROR)
21330 #define F_CL14_PAR_WRQUEUE_ERROR    V_CL14_PAR_WRQUEUE_ERROR(1U)
21333 #define V_CL13_PAR_WRQUEUE_ERROR(x) ((x) << S_CL13_PAR_WRQUEUE_ERROR)
21334 #define F_CL13_PAR_WRQUEUE_ERROR    V_CL13_PAR_WRQUEUE_ERROR(1U)
21337 #define V_CL12_PAR_WRQUEUE_ERROR(x) ((x) << S_CL12_PAR_WRQUEUE_ERROR)
21338 #define F_CL12_PAR_WRQUEUE_ERROR    V_CL12_PAR_WRQUEUE_ERROR(1U)
21341 #define V_CL11_PAR_WRQUEUE_ERROR(x) ((x) << S_CL11_PAR_WRQUEUE_ERROR)
21342 #define F_CL11_PAR_WRQUEUE_ERROR    V_CL11_PAR_WRQUEUE_ERROR(1U)
21345 #define V_T7_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL10_PAR_WRQUEUE_ERROR)
21346 #define F_T7_CL10_PAR_WRQUEUE_ERROR    V_T7_CL10_PAR_WRQUEUE_ERROR(1U)
21349 #define V_T7_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL9_PAR_WRQUEUE_ERROR)
21350 #define F_T7_CL9_PAR_WRQUEUE_ERROR    V_T7_CL9_PAR_WRQUEUE_ERROR(1U)
21353 #define V_T7_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL8_PAR_WRQUEUE_ERROR)
21354 #define F_T7_CL8_PAR_WRQUEUE_ERROR    V_T7_CL8_PAR_WRQUEUE_ERROR(1U)
21357 #define V_T7_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL7_PAR_WRQUEUE_ERROR)
21358 #define F_T7_CL7_PAR_WRQUEUE_ERROR    V_T7_CL7_PAR_WRQUEUE_ERROR(1U)
21361 #define V_T7_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL6_PAR_WRQUEUE_ERROR)
21362 #define F_T7_CL6_PAR_WRQUEUE_ERROR    V_T7_CL6_PAR_WRQUEUE_ERROR(1U)
21365 #define V_T7_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL5_PAR_WRQUEUE_ERROR)
21366 #define F_T7_CL5_PAR_WRQUEUE_ERROR    V_T7_CL5_PAR_WRQUEUE_ERROR(1U)
21369 #define V_T7_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL4_PAR_WRQUEUE_ERROR)
21370 #define F_T7_CL4_PAR_WRQUEUE_ERROR    V_T7_CL4_PAR_WRQUEUE_ERROR(1U)
21373 #define V_T7_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL3_PAR_WRQUEUE_ERROR)
21374 #define F_T7_CL3_PAR_WRQUEUE_ERROR    V_T7_CL3_PAR_WRQUEUE_ERROR(1U)
21377 #define V_T7_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL2_PAR_WRQUEUE_ERROR)
21378 #define F_T7_CL2_PAR_WRQUEUE_ERROR    V_T7_CL2_PAR_WRQUEUE_ERROR(1U)
21380 #define S_T7_CL1_PAR_WRQUEUE_ERROR    1
21381 #define V_T7_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL1_PAR_WRQUEUE_ERROR)
21382 #define F_T7_CL1_PAR_WRQUEUE_ERROR    V_T7_CL1_PAR_WRQUEUE_ERROR(1U)
21385 #define V_T7_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_T7_CL0_PAR_WRQUEUE_ERROR)
21386 #define F_T7_CL0_PAR_WRQUEUE_ERROR    V_T7_CL0_PAR_WRQUEUE_ERROR(1U)
21392 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
21393 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
21397 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
21398 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
21402 #define V_T7_EXT_MEM1_BASE(x) ((x) << S_T7_EXT_MEM1_BASE)
21403 #define G_T7_EXT_MEM1_BASE(x) (((x) >> S_T7_EXT_MEM1_BASE) & M_T7_EXT_MEM1_BASE)
21407 #define V_T7_EXT_MEM1_SIZE(x) ((x) << S_T7_EXT_MEM1_SIZE)
21408 #define G_T7_EXT_MEM1_SIZE(x) (((x) >> S_T7_EXT_MEM1_SIZE) & M_T7_EXT_MEM1_SIZE)
21413 #define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
21414 #define F_FL_ENABLE    V_FL_ENABLE(1U)
21418 #define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
21419 #define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
21454 #define V_EXIT_ADDR_FAULT(x) ((x) << S_EXIT_ADDR_FAULT)
21455 #define F_EXIT_ADDR_FAULT    V_EXIT_ADDR_FAULT(1U)
21460 #define S_MEM_WIDTH    1
21462 #define V_MEM_WIDTH(x) ((x) << S_MEM_WIDTH)
21463 #define G_MEM_WIDTH(x) (((x) >> S_MEM_WIDTH) & M_MEM_WIDTH)
21466 #define V_DDR_MODE(x) ((x) << S_DDR_MODE)
21467 #define F_DDR_MODE    V_DDR_MODE(1U)
21473 #define V_CL14_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR_EN)
21474 #define F_CL14_PAR_RDQUEUE_ERROR_EN    V_CL14_PAR_RDQUEUE_ERROR_EN(1U)
21477 #define V_CL13_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR_EN)
21478 #define F_CL13_PAR_RDQUEUE_ERROR_EN    V_CL13_PAR_RDQUEUE_ERROR_EN(1U)
21481 #define V_CL12_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR_EN)
21482 #define F_CL12_PAR_RDQUEUE_ERROR_EN    V_CL12_PAR_RDQUEUE_ERROR_EN(1U)
21485 #define V_CL11_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR_EN)
21486 #define F_CL11_PAR_RDQUEUE_ERROR_EN    V_CL11_PAR_RDQUEUE_ERROR_EN(1U)
21492 #define V_CL14_PAR_RDQUEUE_ERROR(x) ((x) << S_CL14_PAR_RDQUEUE_ERROR)
21493 #define F_CL14_PAR_RDQUEUE_ERROR    V_CL14_PAR_RDQUEUE_ERROR(1U)
21496 #define V_CL13_PAR_RDQUEUE_ERROR(x) ((x) << S_CL13_PAR_RDQUEUE_ERROR)
21497 #define F_CL13_PAR_RDQUEUE_ERROR    V_CL13_PAR_RDQUEUE_ERROR(1U)
21500 #define V_CL12_PAR_RDQUEUE_ERROR(x) ((x) << S_CL12_PAR_RDQUEUE_ERROR)
21501 #define F_CL12_PAR_RDQUEUE_ERROR    V_CL12_PAR_RDQUEUE_ERROR(1U)
21504 #define V_CL11_PAR_RDQUEUE_ERROR(x) ((x) << S_CL11_PAR_RDQUEUE_ERROR)
21505 #define F_CL11_PAR_RDQUEUE_ERROR    V_CL11_PAR_RDQUEUE_ERROR(1U)
21526 #define V_CLR(x) ((x) << S_CLR)
21527 #define F_CLR    V_CLR(1U)
21530 #define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
21531 #define F_CNT_LOCK    V_CNT_LOCK(1U)
21534 #define V_WRN(x) ((x) << S_WRN)
21535 #define F_WRN    V_WRN(1U)
21538 #define V_DIR(x) ((x) << S_DIR)
21539 #define F_DIR    V_DIR(1U)
21542 #define V_TO_BUS(x) ((x) << S_TO_BUS)
21543 #define F_TO_BUS    V_TO_BUS(1U)
21547 #define V_CLIENT(x) ((x) << S_CLIENT)
21548 #define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
21552 #define V_DELAY(x) ((x) << S_DELAY)
21553 #define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
21559 #define V_CNT_VAL(x) ((x) << S_CNT_VAL)
21560 #define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
21566 #define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
21567 #define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
21570 #define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
21571 #define F_CL12_WR_CMD_TO_EN    V_CL12_WR_CMD_TO_EN(1U)
21574 #define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
21575 #define F_CL11_WR_CMD_TO_EN    V_CL11_WR_CMD_TO_EN(1U)
21578 #define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
21579 #define F_CL10_WR_CMD_TO_EN    V_CL10_WR_CMD_TO_EN(1U)
21582 #define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
21583 #define F_CL9_WR_CMD_TO_EN    V_CL9_WR_CMD_TO_EN(1U)
21586 #define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
21587 #define F_CL8_WR_CMD_TO_EN    V_CL8_WR_CMD_TO_EN(1U)
21590 #define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
21591 #define F_CL7_WR_CMD_TO_EN    V_CL7_WR_CMD_TO_EN(1U)
21594 #define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
21595 #define F_CL6_WR_CMD_TO_EN    V_CL6_WR_CMD_TO_EN(1U)
21598 #define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
21599 #define F_CL5_WR_CMD_TO_EN    V_CL5_WR_CMD_TO_EN(1U)
21602 #define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
21603 #define F_CL4_WR_CMD_TO_EN    V_CL4_WR_CMD_TO_EN(1U)
21606 #define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
21607 #define F_CL3_WR_CMD_TO_EN    V_CL3_WR_CMD_TO_EN(1U)
21610 #define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
21611 #define F_CL2_WR_CMD_TO_EN    V_CL2_WR_CMD_TO_EN(1U)
21614 #define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
21615 #define F_CL1_WR_CMD_TO_EN    V_CL1_WR_CMD_TO_EN(1U)
21618 #define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
21619 #define F_CL0_WR_CMD_TO_EN    V_CL0_WR_CMD_TO_EN(1U)
21623 #define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
21624 #define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
21627 #define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
21628 #define F_CL12_WR_DATA_TO_EN    V_CL12_WR_DATA_TO_EN(1U)
21631 #define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
21632 #define F_CL11_WR_DATA_TO_EN    V_CL11_WR_DATA_TO_EN(1U)
21635 #define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
21636 #define F_CL10_WR_DATA_TO_EN    V_CL10_WR_DATA_TO_EN(1U)
21639 #define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
21640 #define F_CL9_WR_DATA_TO_EN    V_CL9_WR_DATA_TO_EN(1U)
21643 #define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
21644 #define F_CL8_WR_DATA_TO_EN    V_CL8_WR_DATA_TO_EN(1U)
21647 #define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
21648 #define F_CL7_WR_DATA_TO_EN    V_CL7_WR_DATA_TO_EN(1U)
21651 #define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
21652 #define F_CL6_WR_DATA_TO_EN    V_CL6_WR_DATA_TO_EN(1U)
21655 #define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
21656 #define F_CL5_WR_DATA_TO_EN    V_CL5_WR_DATA_TO_EN(1U)
21659 #define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
21660 #define F_CL4_WR_DATA_TO_EN    V_CL4_WR_DATA_TO_EN(1U)
21663 #define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
21664 #define F_CL3_WR_DATA_TO_EN    V_CL3_WR_DATA_TO_EN(1U)
21667 #define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
21668 #define F_CL2_WR_DATA_TO_EN    V_CL2_WR_DATA_TO_EN(1U)
21670 #define S_CL1_WR_DATA_TO_EN    1
21671 #define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
21672 #define F_CL1_WR_DATA_TO_EN    V_CL1_WR_DATA_TO_EN(1U)
21675 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
21676 #define F_CL0_WR_DATA_TO_EN    V_CL0_WR_DATA_TO_EN(1U)
21680 #define V_FUTURE_CEXPANSION_WTE(x) ((x) << S_FUTURE_CEXPANSION_WTE)
21681 #define G_FUTURE_CEXPANSION_WTE(x) (((x) >> S_FUTURE_CEXPANSION_WTE) & M_FUTURE_CEXPANSION_WTE)
21685 #define V_FUTURE_DEXPANSION_WTE(x) ((x) << S_FUTURE_DEXPANSION_WTE)
21686 #define G_FUTURE_DEXPANSION_WTE(x) (((x) >> S_FUTURE_DEXPANSION_WTE) & M_FUTURE_DEXPANSION_WTE)
21689 #define V_T7_FUTURE_CEXPANSION_WTE(x) ((x) << S_T7_FUTURE_CEXPANSION_WTE)
21690 #define F_T7_FUTURE_CEXPANSION_WTE    V_T7_FUTURE_CEXPANSION_WTE(1U)
21693 #define V_CL14_WR_CMD_TO_EN(x) ((x) << S_CL14_WR_CMD_TO_EN)
21694 #define F_CL14_WR_CMD_TO_EN    V_CL14_WR_CMD_TO_EN(1U)
21697 #define V_CL13_WR_CMD_TO_EN(x) ((x) << S_CL13_WR_CMD_TO_EN)
21698 #define F_CL13_WR_CMD_TO_EN    V_CL13_WR_CMD_TO_EN(1U)
21701 #define V_T7_FUTURE_DEXPANSION_WTE(x) ((x) << S_T7_FUTURE_DEXPANSION_WTE)
21702 #define F_T7_FUTURE_DEXPANSION_WTE    V_T7_FUTURE_DEXPANSION_WTE(1U)
21705 #define V_CL14_WR_DATA_TO_EN(x) ((x) << S_CL14_WR_DATA_TO_EN)
21706 #define F_CL14_WR_DATA_TO_EN    V_CL14_WR_DATA_TO_EN(1U)
21709 #define V_CL13_WR_DATA_TO_EN(x) ((x) << S_CL13_WR_DATA_TO_EN)
21710 #define F_CL13_WR_DATA_TO_EN    V_CL13_WR_DATA_TO_EN(1U)
21715 #define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
21716 #define F_CL12_WR_CMD_TO_ERROR    V_CL12_WR_CMD_TO_ERROR(1U)
21719 #define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
21720 #define F_CL11_WR_CMD_TO_ERROR    V_CL11_WR_CMD_TO_ERROR(1U)
21723 #define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
21724 #define F_CL10_WR_CMD_TO_ERROR    V_CL10_WR_CMD_TO_ERROR(1U)
21727 #define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
21728 #define F_CL9_WR_CMD_TO_ERROR    V_CL9_WR_CMD_TO_ERROR(1U)
21731 #define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
21732 #define F_CL8_WR_CMD_TO_ERROR    V_CL8_WR_CMD_TO_ERROR(1U)
21735 #define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
21736 #define F_CL7_WR_CMD_TO_ERROR    V_CL7_WR_CMD_TO_ERROR(1U)
21739 #define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
21740 #define F_CL6_WR_CMD_TO_ERROR    V_CL6_WR_CMD_TO_ERROR(1U)
21743 #define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
21744 #define F_CL5_WR_CMD_TO_ERROR    V_CL5_WR_CMD_TO_ERROR(1U)
21747 #define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
21748 #define F_CL4_WR_CMD_TO_ERROR    V_CL4_WR_CMD_TO_ERROR(1U)
21751 #define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
21752 #define F_CL3_WR_CMD_TO_ERROR    V_CL3_WR_CMD_TO_ERROR(1U)
21755 #define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
21756 #define F_CL2_WR_CMD_TO_ERROR    V_CL2_WR_CMD_TO_ERROR(1U)
21759 #define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
21760 #define F_CL1_WR_CMD_TO_ERROR    V_CL1_WR_CMD_TO_ERROR(1U)
21763 #define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
21764 #define F_CL0_WR_CMD_TO_ERROR    V_CL0_WR_CMD_TO_ERROR(1U)
21767 #define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
21768 #define F_CL12_WR_DATA_TO_ERROR    V_CL12_WR_DATA_TO_ERROR(1U)
21771 #define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
21772 #define F_CL11_WR_DATA_TO_ERROR    V_CL11_WR_DATA_TO_ERROR(1U)
21775 #define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
21776 #define F_CL10_WR_DATA_TO_ERROR    V_CL10_WR_DATA_TO_ERROR(1U)
21779 #define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
21780 #define F_CL9_WR_DATA_TO_ERROR    V_CL9_WR_DATA_TO_ERROR(1U)
21783 #define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
21784 #define F_CL8_WR_DATA_TO_ERROR    V_CL8_WR_DATA_TO_ERROR(1U)
21787 #define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
21788 #define F_CL7_WR_DATA_TO_ERROR    V_CL7_WR_DATA_TO_ERROR(1U)
21791 #define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
21792 #define F_CL6_WR_DATA_TO_ERROR    V_CL6_WR_DATA_TO_ERROR(1U)
21795 #define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
21796 #define F_CL5_WR_DATA_TO_ERROR    V_CL5_WR_DATA_TO_ERROR(1U)
21799 #define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
21800 #define F_CL4_WR_DATA_TO_ERROR    V_CL4_WR_DATA_TO_ERROR(1U)
21803 #define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
21804 #define F_CL3_WR_DATA_TO_ERROR    V_CL3_WR_DATA_TO_ERROR(1U)
21807 #define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
21808 #define F_CL2_WR_DATA_TO_ERROR    V_CL2_WR_DATA_TO_ERROR(1U)
21810 #define S_CL1_WR_DATA_TO_ERROR    1
21811 #define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
21812 #define F_CL1_WR_DATA_TO_ERROR    V_CL1_WR_DATA_TO_ERROR(1U)
21815 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
21816 #define F_CL0_WR_DATA_TO_ERROR    V_CL0_WR_DATA_TO_ERROR(1U)
21820 #define V_FUTURE_CEXPANSION_WTS(x) ((x) << S_FUTURE_CEXPANSION_WTS)
21821 #define G_FUTURE_CEXPANSION_WTS(x) (((x) >> S_FUTURE_CEXPANSION_WTS) & M_FUTURE_CEXPANSION_WTS)
21825 #define V_FUTURE_DEXPANSION_WTS(x) ((x) << S_FUTURE_DEXPANSION_WTS)
21826 #define G_FUTURE_DEXPANSION_WTS(x) (((x) >> S_FUTURE_DEXPANSION_WTS) & M_FUTURE_DEXPANSION_WTS)
21829 #define V_T7_FUTURE_CEXPANSION_WTS(x) ((x) << S_T7_FUTURE_CEXPANSION_WTS)
21830 #define F_T7_FUTURE_CEXPANSION_WTS    V_T7_FUTURE_CEXPANSION_WTS(1U)
21833 #define V_CL14_WR_CMD_TO_ERROR(x) ((x) << S_CL14_WR_CMD_TO_ERROR)
21834 #define F_CL14_WR_CMD_TO_ERROR    V_CL14_WR_CMD_TO_ERROR(1U)
21837 #define V_CL13_WR_CMD_TO_ERROR(x) ((x) << S_CL13_WR_CMD_TO_ERROR)
21838 #define F_CL13_WR_CMD_TO_ERROR    V_CL13_WR_CMD_TO_ERROR(1U)
21841 #define V_T7_FUTURE_DEXPANSION_WTS(x) ((x) << S_T7_FUTURE_DEXPANSION_WTS)
21842 #define F_T7_FUTURE_DEXPANSION_WTS    V_T7_FUTURE_DEXPANSION_WTS(1U)
21845 #define V_CL14_WR_DATA_TO_ERROR(x) ((x) << S_CL14_WR_DATA_TO_ERROR)
21846 #define F_CL14_WR_DATA_TO_ERROR    V_CL14_WR_DATA_TO_ERROR(1U)
21849 #define V_CL13_WR_DATA_TO_ERROR(x) ((x) << S_CL13_WR_DATA_TO_ERROR)
21850 #define F_CL13_WR_DATA_TO_ERROR    V_CL13_WR_DATA_TO_ERROR(1U)
21855 #define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
21856 #define F_CL12_RD_CMD_TO_EN    V_CL12_RD_CMD_TO_EN(1U)
21859 #define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
21860 #define F_CL11_RD_CMD_TO_EN    V_CL11_RD_CMD_TO_EN(1U)
21863 #define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
21864 #define F_CL10_RD_CMD_TO_EN    V_CL10_RD_CMD_TO_EN(1U)
21867 #define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
21868 #define F_CL9_RD_CMD_TO_EN    V_CL9_RD_CMD_TO_EN(1U)
21871 #define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
21872 #define F_CL8_RD_CMD_TO_EN    V_CL8_RD_CMD_TO_EN(1U)
21875 #define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
21876 #define F_CL7_RD_CMD_TO_EN    V_CL7_RD_CMD_TO_EN(1U)
21879 #define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
21880 #define F_CL6_RD_CMD_TO_EN    V_CL6_RD_CMD_TO_EN(1U)
21883 #define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
21884 #define F_CL5_RD_CMD_TO_EN    V_CL5_RD_CMD_TO_EN(1U)
21887 #define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
21888 #define F_CL4_RD_CMD_TO_EN    V_CL4_RD_CMD_TO_EN(1U)
21891 #define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
21892 #define F_CL3_RD_CMD_TO_EN    V_CL3_RD_CMD_TO_EN(1U)
21895 #define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
21896 #define F_CL2_RD_CMD_TO_EN    V_CL2_RD_CMD_TO_EN(1U)
21899 #define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
21900 #define F_CL1_RD_CMD_TO_EN    V_CL1_RD_CMD_TO_EN(1U)
21903 #define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
21904 #define F_CL0_RD_CMD_TO_EN    V_CL0_RD_CMD_TO_EN(1U)
21907 #define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
21908 #define F_CL12_RD_DATA_TO_EN    V_CL12_RD_DATA_TO_EN(1U)
21911 #define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
21912 #define F_CL11_RD_DATA_TO_EN    V_CL11_RD_DATA_TO_EN(1U)
21915 #define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
21916 #define F_CL10_RD_DATA_TO_EN    V_CL10_RD_DATA_TO_EN(1U)
21919 #define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
21920 #define F_CL9_RD_DATA_TO_EN    V_CL9_RD_DATA_TO_EN(1U)
21923 #define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
21924 #define F_CL8_RD_DATA_TO_EN    V_CL8_RD_DATA_TO_EN(1U)
21927 #define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
21928 #define F_CL7_RD_DATA_TO_EN    V_CL7_RD_DATA_TO_EN(1U)
21931 #define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
21932 #define F_CL6_RD_DATA_TO_EN    V_CL6_RD_DATA_TO_EN(1U)
21935 #define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
21936 #define F_CL5_RD_DATA_TO_EN    V_CL5_RD_DATA_TO_EN(1U)
21939 #define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
21940 #define F_CL4_RD_DATA_TO_EN    V_CL4_RD_DATA_TO_EN(1U)
21943 #define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
21944 #define F_CL3_RD_DATA_TO_EN    V_CL3_RD_DATA_TO_EN(1U)
21947 #define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
21948 #define F_CL2_RD_DATA_TO_EN    V_CL2_RD_DATA_TO_EN(1U)
21950 #define S_CL1_RD_DATA_TO_EN    1
21951 #define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
21952 #define F_CL1_RD_DATA_TO_EN    V_CL1_RD_DATA_TO_EN(1U)
21955 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
21956 #define F_CL0_RD_DATA_TO_EN    V_CL0_RD_DATA_TO_EN(1U)
21960 #define V_FUTURE_CEXPANSION_RTE(x) ((x) << S_FUTURE_CEXPANSION_RTE)
21961 #define G_FUTURE_CEXPANSION_RTE(x) (((x) >> S_FUTURE_CEXPANSION_RTE) & M_FUTURE_CEXPANSION_RTE)
21965 #define V_FUTURE_DEXPANSION_RTE(x) ((x) << S_FUTURE_DEXPANSION_RTE)
21966 #define G_FUTURE_DEXPANSION_RTE(x) (((x) >> S_FUTURE_DEXPANSION_RTE) & M_FUTURE_DEXPANSION_RTE)
21969 #define V_T7_FUTURE_CEXPANSION_RTE(x) ((x) << S_T7_FUTURE_CEXPANSION_RTE)
21970 #define F_T7_FUTURE_CEXPANSION_RTE    V_T7_FUTURE_CEXPANSION_RTE(1U)
21973 #define V_CL14_RD_CMD_TO_EN(x) ((x) << S_CL14_RD_CMD_TO_EN)
21974 #define F_CL14_RD_CMD_TO_EN    V_CL14_RD_CMD_TO_EN(1U)
21977 #define V_CL13_RD_CMD_TO_EN(x) ((x) << S_CL13_RD_CMD_TO_EN)
21978 #define F_CL13_RD_CMD_TO_EN    V_CL13_RD_CMD_TO_EN(1U)
21981 #define V_T7_FUTURE_DEXPANSION_RTE(x) ((x) << S_T7_FUTURE_DEXPANSION_RTE)
21982 #define F_T7_FUTURE_DEXPANSION_RTE    V_T7_FUTURE_DEXPANSION_RTE(1U)
21985 #define V_CL14_RD_DATA_TO_EN(x) ((x) << S_CL14_RD_DATA_TO_EN)
21986 #define F_CL14_RD_DATA_TO_EN    V_CL14_RD_DATA_TO_EN(1U)
21989 #define V_CL13_RD_DATA_TO_EN(x) ((x) << S_CL13_RD_DATA_TO_EN)
21990 #define F_CL13_RD_DATA_TO_EN    V_CL13_RD_DATA_TO_EN(1U)
21995 #define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
21996 #define F_CL12_RD_CMD_TO_ERROR    V_CL12_RD_CMD_TO_ERROR(1U)
21999 #define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
22000 #define F_CL11_RD_CMD_TO_ERROR    V_CL11_RD_CMD_TO_ERROR(1U)
22003 #define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
22004 #define F_CL10_RD_CMD_TO_ERROR    V_CL10_RD_CMD_TO_ERROR(1U)
22007 #define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
22008 #define F_CL9_RD_CMD_TO_ERROR    V_CL9_RD_CMD_TO_ERROR(1U)
22011 #define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
22012 #define F_CL8_RD_CMD_TO_ERROR    V_CL8_RD_CMD_TO_ERROR(1U)
22015 #define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
22016 #define F_CL7_RD_CMD_TO_ERROR    V_CL7_RD_CMD_TO_ERROR(1U)
22019 #define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
22020 #define F_CL6_RD_CMD_TO_ERROR    V_CL6_RD_CMD_TO_ERROR(1U)
22023 #define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
22024 #define F_CL5_RD_CMD_TO_ERROR    V_CL5_RD_CMD_TO_ERROR(1U)
22027 #define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
22028 #define F_CL4_RD_CMD_TO_ERROR    V_CL4_RD_CMD_TO_ERROR(1U)
22031 #define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
22032 #define F_CL3_RD_CMD_TO_ERROR    V_CL3_RD_CMD_TO_ERROR(1U)
22035 #define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
22036 #define F_CL2_RD_CMD_TO_ERROR    V_CL2_RD_CMD_TO_ERROR(1U)
22039 #define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
22040 #define F_CL1_RD_CMD_TO_ERROR    V_CL1_RD_CMD_TO_ERROR(1U)
22043 #define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
22044 #define F_CL0_RD_CMD_TO_ERROR    V_CL0_RD_CMD_TO_ERROR(1U)
22047 #define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
22048 #define F_CL12_RD_DATA_TO_ERROR    V_CL12_RD_DATA_TO_ERROR(1U)
22051 #define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
22052 #define F_CL11_RD_DATA_TO_ERROR    V_CL11_RD_DATA_TO_ERROR(1U)
22055 #define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
22056 #define F_CL10_RD_DATA_TO_ERROR    V_CL10_RD_DATA_TO_ERROR(1U)
22059 #define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
22060 #define F_CL9_RD_DATA_TO_ERROR    V_CL9_RD_DATA_TO_ERROR(1U)
22063 #define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
22064 #define F_CL8_RD_DATA_TO_ERROR    V_CL8_RD_DATA_TO_ERROR(1U)
22067 #define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
22068 #define F_CL7_RD_DATA_TO_ERROR    V_CL7_RD_DATA_TO_ERROR(1U)
22071 #define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
22072 #define F_CL6_RD_DATA_TO_ERROR    V_CL6_RD_DATA_TO_ERROR(1U)
22075 #define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
22076 #define F_CL5_RD_DATA_TO_ERROR    V_CL5_RD_DATA_TO_ERROR(1U)
22079 #define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
22080 #define F_CL4_RD_DATA_TO_ERROR    V_CL4_RD_DATA_TO_ERROR(1U)
22083 #define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
22084 #define F_CL3_RD_DATA_TO_ERROR    V_CL3_RD_DATA_TO_ERROR(1U)
22087 #define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
22088 #define F_CL2_RD_DATA_TO_ERROR    V_CL2_RD_DATA_TO_ERROR(1U)
22090 #define S_CL1_RD_DATA_TO_ERROR    1
22091 #define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
22092 #define F_CL1_RD_DATA_TO_ERROR    V_CL1_RD_DATA_TO_ERROR(1U)
22095 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
22096 #define F_CL0_RD_DATA_TO_ERROR    V_CL0_RD_DATA_TO_ERROR(1U)
22100 #define V_FUTURE_CEXPANSION_RTS(x) ((x) << S_FUTURE_CEXPANSION_RTS)
22101 #define G_FUTURE_CEXPANSION_RTS(x) (((x) >> S_FUTURE_CEXPANSION_RTS) & M_FUTURE_CEXPANSION_RTS)
22105 #define V_FUTURE_DEXPANSION_RTS(x) ((x) << S_FUTURE_DEXPANSION_RTS)
22106 #define G_FUTURE_DEXPANSION_RTS(x) (((x) >> S_FUTURE_DEXPANSION_RTS) & M_FUTURE_DEXPANSION_RTS)
22109 #define V_T7_FUTURE_CEXPANSION_RTS(x) ((x) << S_T7_FUTURE_CEXPANSION_RTS)
22110 #define F_T7_FUTURE_CEXPANSION_RTS    V_T7_FUTURE_CEXPANSION_RTS(1U)
22113 #define V_CL14_RD_CMD_TO_ERROR(x) ((x) << S_CL14_RD_CMD_TO_ERROR)
22114 #define F_CL14_RD_CMD_TO_ERROR    V_CL14_RD_CMD_TO_ERROR(1U)
22117 #define V_CL13_RD_CMD_TO_ERROR(x) ((x) << S_CL13_RD_CMD_TO_ERROR)
22118 #define F_CL13_RD_CMD_TO_ERROR    V_CL13_RD_CMD_TO_ERROR(1U)
22122 #define V_T7_FUTURE_DEXPANSION_RTS(x) ((x) << S_T7_FUTURE_DEXPANSION_RTS)
22123 #define G_T7_FUTURE_DEXPANSION_RTS(x) (((x) >> S_T7_FUTURE_DEXPANSION_RTS) & M_T7_FUTURE_DEXPANSION_RTS)
22126 #define V_CL13_RD_DATA_TO_ERROR(x) ((x) << S_CL13_RD_DATA_TO_ERROR)
22127 #define F_CL13_RD_DATA_TO_ERROR    V_CL13_RD_DATA_TO_ERROR(1U)
22133 #define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
22134 #define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
22138 #define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
22139 #define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
22145 #define V_WRT_EN(x) ((x) << S_WRT_EN)
22146 #define F_WRT_EN    V_WRT_EN(1U)
22150 #define V_WR_TIM(x) ((x) << S_WR_TIM)
22151 #define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
22155 #define V_RD_WIN(x) ((x) << S_RD_WIN)
22156 #define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
22160 #define V_WR_WIN(x) ((x) << S_WR_WIN)
22161 #define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
22167 #define V_T5_FUTURE_DEXPANSION(x) ((x) << S_T5_FUTURE_DEXPANSION)
22168 #define G_T5_FUTURE_DEXPANSION(x) (((x) >> S_T5_FUTURE_DEXPANSION) & M_T5_FUTURE_DEXPANSION)
22171 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
22172 #define F_CL12_IF_PAR_EN    V_CL12_IF_PAR_EN(1U)
22175 #define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
22176 #define F_CL11_IF_PAR_EN    V_CL11_IF_PAR_EN(1U)
22179 #define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
22180 #define F_CL10_IF_PAR_EN    V_CL10_IF_PAR_EN(1U)
22183 #define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
22184 #define F_CL9_IF_PAR_EN    V_CL9_IF_PAR_EN(1U)
22187 #define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
22188 #define F_CL8_IF_PAR_EN    V_CL8_IF_PAR_EN(1U)
22191 #define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
22192 #define F_CL7_IF_PAR_EN    V_CL7_IF_PAR_EN(1U)
22195 #define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
22196 #define F_CL6_IF_PAR_EN    V_CL6_IF_PAR_EN(1U)
22199 #define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
22200 #define F_CL5_IF_PAR_EN    V_CL5_IF_PAR_EN(1U)
22203 #define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
22204 #define F_CL4_IF_PAR_EN    V_CL4_IF_PAR_EN(1U)
22207 #define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
22208 #define F_CL3_IF_PAR_EN    V_CL3_IF_PAR_EN(1U)
22211 #define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
22212 #define F_CL2_IF_PAR_EN    V_CL2_IF_PAR_EN(1U)
22214 #define S_CL1_IF_PAR_EN    1
22215 #define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
22216 #define F_CL1_IF_PAR_EN    V_CL1_IF_PAR_EN(1U)
22219 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
22220 #define F_CL0_IF_PAR_EN    V_CL0_IF_PAR_EN(1U)
22224 #define V_FUTURE_DEXPANSION_IPE(x) ((x) << S_FUTURE_DEXPANSION_IPE)
22225 #define G_FUTURE_DEXPANSION_IPE(x) (((x) >> S_FUTURE_DEXPANSION_IPE) & M_FUTURE_DEXPANSION_IPE)
22229 #define V_T7_FUTURE_DEXPANSION_IPE(x) ((x) << S_T7_FUTURE_DEXPANSION_IPE)
22230 #define G_T7_FUTURE_DEXPANSION_IPE(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPE) & M_T7_FUTURE_DEXPANSION_IPE)
22233 #define V_CL13_IF_PAR_EN(x) ((x) << S_CL13_IF_PAR_EN)
22234 #define F_CL13_IF_PAR_EN    V_CL13_IF_PAR_EN(1U)
22239 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
22240 #define F_CL12_IF_PAR_ERROR    V_CL12_IF_PAR_ERROR(1U)
22243 #define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
22244 #define F_CL11_IF_PAR_ERROR    V_CL11_IF_PAR_ERROR(1U)
22247 #define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
22248 #define F_CL10_IF_PAR_ERROR    V_CL10_IF_PAR_ERROR(1U)
22251 #define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
22252 #define F_CL9_IF_PAR_ERROR    V_CL9_IF_PAR_ERROR(1U)
22255 #define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
22256 #define F_CL8_IF_PAR_ERROR    V_CL8_IF_PAR_ERROR(1U)
22259 #define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
22260 #define F_CL7_IF_PAR_ERROR    V_CL7_IF_PAR_ERROR(1U)
22263 #define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
22264 #define F_CL6_IF_PAR_ERROR    V_CL6_IF_PAR_ERROR(1U)
22267 #define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
22268 #define F_CL5_IF_PAR_ERROR    V_CL5_IF_PAR_ERROR(1U)
22271 #define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
22272 #define F_CL4_IF_PAR_ERROR    V_CL4_IF_PAR_ERROR(1U)
22275 #define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
22276 #define F_CL3_IF_PAR_ERROR    V_CL3_IF_PAR_ERROR(1U)
22279 #define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
22280 #define F_CL2_IF_PAR_ERROR    V_CL2_IF_PAR_ERROR(1U)
22282 #define S_CL1_IF_PAR_ERROR    1
22283 #define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
22284 #define F_CL1_IF_PAR_ERROR    V_CL1_IF_PAR_ERROR(1U)
22287 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
22288 #define F_CL0_IF_PAR_ERROR    V_CL0_IF_PAR_ERROR(1U)
22292 #define V_FUTURE_DEXPANSION_IPS(x) ((x) << S_FUTURE_DEXPANSION_IPS)
22293 #define G_FUTURE_DEXPANSION_IPS(x) (((x) >> S_FUTURE_DEXPANSION_IPS) & M_FUTURE_DEXPANSION_IPS)
22297 #define V_T7_FUTURE_DEXPANSION_IPS(x) ((x) << S_T7_FUTURE_DEXPANSION_IPS)
22298 #define G_T7_FUTURE_DEXPANSION_IPS(x) (((x) >> S_T7_FUTURE_DEXPANSION_IPS) & M_T7_FUTURE_DEXPANSION_IPS)
22301 #define V_CL13_IF_PAR_ERROR(x) ((x) << S_CL13_IF_PAR_ERROR)
22302 #define F_CL13_IF_PAR_ERROR    V_CL13_IF_PAR_ERROR(1U)
22307 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
22308 #define F_DEBUG_OR    V_DEBUG_OR(1U)
22311 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
22312 #define F_DEBUG_HI    V_DEBUG_HI(1U)
22315 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
22316 #define F_DEBUG_RPT    V_DEBUG_RPT(1U)
22320 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
22321 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
22341 #define V_CIM_THREAD1_EN(x) ((x) << S_CIM_THREAD1_EN)
22342 #define G_CIM_THREAD1_EN(x) (((x) >> S_CIM_THREAD1_EN) & M_CIM_THREAD1_EN)
22348 #define V_SGE_TH0_BASE(x) ((x) << S_SGE_TH0_BASE)
22349 #define G_SGE_TH0_BASE(x) (((x) >> S_SGE_TH0_BASE) & M_SGE_TH0_BASE)
22355 #define V_SGE_TH1_BASE(x) ((x) << S_SGE_TH1_BASE)
22356 #define G_SGE_TH1_BASE(x) (((x) >> S_SGE_TH1_BASE) & M_SGE_TH1_BASE)
22362 #define V_ULPTX_BASE(x) ((x) << S_ULPTX_BASE)
22363 #define G_ULPTX_BASE(x) (((x) >> S_ULPTX_BASE) & M_ULPTX_BASE)
22369 #define V_ULPRX_BASE(x) ((x) << S_ULPRX_BASE)
22370 #define G_ULPRX_BASE(x) (((x) >> S_ULPRX_BASE) & M_ULPRX_BASE)
22376 #define V_ULPTXRX_BASE(x) ((x) << S_ULPTXRX_BASE)
22377 #define G_ULPTXRX_BASE(x) (((x) >> S_ULPTXRX_BASE) & M_ULPTXRX_BASE)
22383 #define V_TP_TH0_BASE(x) ((x) << S_TP_TH0_BASE)
22384 #define G_TP_TH0_BASE(x) (((x) >> S_TP_TH0_BASE) & M_TP_TH0_BASE)
22390 #define V_TP_TH1_BASE(x) ((x) << S_TP_TH1_BASE)
22391 #define G_TP_TH1_BASE(x) (((x) >> S_TP_TH1_BASE) & M_TP_TH1_BASE)
22397 #define V_LE_BASE(x) ((x) << S_LE_BASE)
22398 #define G_LE_BASE(x) (((x) >> S_LE_BASE) & M_LE_BASE)
22404 #define V_CIM_TH0_BASE(x) ((x) << S_CIM_TH0_BASE)
22405 #define G_CIM_TH0_BASE(x) (((x) >> S_CIM_TH0_BASE) & M_CIM_TH0_BASE)
22411 #define V_PCIE_BASE(x) ((x) << S_PCIE_BASE)
22412 #define G_PCIE_BASE(x) (((x) >> S_PCIE_BASE) & M_PCIE_BASE)
22418 #define V_PMTX_BASE(x) ((x) << S_PMTX_BASE)
22419 #define G_PMTX_BASE(x) (((x) >> S_PMTX_BASE) & M_PMTX_BASE)
22425 #define V_PMRX_BASE(x) ((x) << S_PMRX_BASE)
22426 #define G_PMRX_BASE(x) (((x) >> S_PMRX_BASE) & M_PMRX_BASE)
22432 #define V_HMACLIENTBASE(x) ((x) << S_HMACLIENTBASE)
22433 #define G_HMACLIENTBASE(x) (((x) >> S_HMACLIENTBASE) & M_HMACLIENTBASE)
22439 #define V_CRYPTO_BASE(x) ((x) << S_CRYPTO_BASE)
22440 #define G_CRYPTO_BASE(x) (((x) >> S_CRYPTO_BASE) & M_CRYPTO_BASE)
22446 #define V_CIM_TH1_BASE(x) ((x) << S_CIM_TH1_BASE)
22447 #define G_CIM_TH1_BASE(x) (((x) >> S_CIM_TH1_BASE) & M_CIM_TH1_BASE)
22452 #define V_CMDVLD0(x) ((x) << S_CMDVLD0)
22453 #define F_CMDVLD0    V_CMDVLD0(1U)
22456 #define V_CMDRDY0(x) ((x) << S_CMDRDY0)
22457 #define F_CMDRDY0    V_CMDRDY0(1U)
22460 #define V_CMDTYPE0(x) ((x) << S_CMDTYPE0)
22461 #define F_CMDTYPE0    V_CMDTYPE0(1U)
22465 #define V_CMDLEN0(x) ((x) << S_CMDLEN0)
22466 #define G_CMDLEN0(x) (((x) >> S_CMDLEN0) & M_CMDLEN0)
22470 #define V_CMDADDR0(x) ((x) << S_CMDADDR0)
22471 #define G_CMDADDR0(x) (((x) >> S_CMDADDR0) & M_CMDADDR0)
22474 #define V_WRDATAVLD0(x) ((x) << S_WRDATAVLD0)
22475 #define F_WRDATAVLD0    V_WRDATAVLD0(1U)
22478 #define V_WRDATARDY0(x) ((x) << S_WRDATARDY0)
22479 #define F_WRDATARDY0    V_WRDATARDY0(1U)
22482 #define V_RDDATARDY0(x) ((x) << S_RDDATARDY0)
22483 #define F_RDDATARDY0    V_RDDATARDY0(1U)
22486 #define V_RDDATAVLD0(x) ((x) << S_RDDATAVLD0)
22487 #define F_RDDATAVLD0    V_RDDATAVLD0(1U)
22491 #define V_RDDATA0(x) ((x) << S_RDDATA0)
22492 #define G_RDDATA0(x) (((x) >> S_RDDATA0) & M_RDDATA0)
22497 #define V_CMDVLD1(x) ((x) << S_CMDVLD1)
22498 #define F_CMDVLD1    V_CMDVLD1(1U)
22501 #define V_CMDRDY1(x) ((x) << S_CMDRDY1)
22502 #define F_CMDRDY1    V_CMDRDY1(1U)
22505 #define V_CMDTYPE1(x) ((x) << S_CMDTYPE1)
22506 #define F_CMDTYPE1    V_CMDTYPE1(1U)
22510 #define V_CMDLEN1(x) ((x) << S_CMDLEN1)
22511 #define G_CMDLEN1(x) (((x) >> S_CMDLEN1) & M_CMDLEN1)
22515 #define V_CMDADDR1(x) ((x) << S_CMDADDR1)
22516 #define G_CMDADDR1(x) (((x) >> S_CMDADDR1) & M_CMDADDR1)
22519 #define V_WRDATAVLD1(x) ((x) << S_WRDATAVLD1)
22520 #define F_WRDATAVLD1    V_WRDATAVLD1(1U)
22523 #define V_WRDATARDY1(x) ((x) << S_WRDATARDY1)
22524 #define F_WRDATARDY1    V_WRDATARDY1(1U)
22527 #define V_RDDATARDY1(x) ((x) << S_RDDATARDY1)
22528 #define F_RDDATARDY1    V_RDDATARDY1(1U)
22531 #define V_RDDATAVLD1(x) ((x) << S_RDDATAVLD1)
22532 #define F_RDDATAVLD1    V_RDDATAVLD1(1U)
22536 #define V_RDDATA1(x) ((x) << S_RDDATA1)
22537 #define G_RDDATA1(x) (((x) >> S_RDDATA1) & M_RDDATA1)
22542 #define V_CMDVLD2(x) ((x) << S_CMDVLD2)
22543 #define F_CMDVLD2    V_CMDVLD2(1U)
22546 #define V_CMDRDY2(x) ((x) << S_CMDRDY2)
22547 #define F_CMDRDY2    V_CMDRDY2(1U)
22550 #define V_CMDTYPE2(x) ((x) << S_CMDTYPE2)
22551 #define F_CMDTYPE2    V_CMDTYPE2(1U)
22555 #define V_CMDLEN2(x) ((x) << S_CMDLEN2)
22556 #define G_CMDLEN2(x) (((x) >> S_CMDLEN2) & M_CMDLEN2)
22560 #define V_CMDADDR2(x) ((x) << S_CMDADDR2)
22561 #define G_CMDADDR2(x) (((x) >> S_CMDADDR2) & M_CMDADDR2)
22564 #define V_WRDATAVLD2(x) ((x) << S_WRDATAVLD2)
22565 #define F_WRDATAVLD2    V_WRDATAVLD2(1U)
22568 #define V_WRDATARDY2(x) ((x) << S_WRDATARDY2)
22569 #define F_WRDATARDY2    V_WRDATARDY2(1U)
22572 #define V_RDDATARDY2(x) ((x) << S_RDDATARDY2)
22573 #define F_RDDATARDY2    V_RDDATARDY2(1U)
22576 #define V_RDDATAVLD2(x) ((x) << S_RDDATAVLD2)
22577 #define F_RDDATAVLD2    V_RDDATAVLD2(1U)
22581 #define V_RDDATA2(x) ((x) << S_RDDATA2)
22582 #define G_RDDATA2(x) (((x) >> S_RDDATA2) & M_RDDATA2)
22587 #define V_CMDVLD3(x) ((x) << S_CMDVLD3)
22588 #define F_CMDVLD3    V_CMDVLD3(1U)
22591 #define V_CMDRDY3(x) ((x) << S_CMDRDY3)
22592 #define F_CMDRDY3    V_CMDRDY3(1U)
22595 #define V_CMDTYPE3(x) ((x) << S_CMDTYPE3)
22596 #define F_CMDTYPE3    V_CMDTYPE3(1U)
22600 #define V_CMDLEN3(x) ((x) << S_CMDLEN3)
22601 #define G_CMDLEN3(x) (((x) >> S_CMDLEN3) & M_CMDLEN3)
22605 #define V_CMDADDR3(x) ((x) << S_CMDADDR3)
22606 #define G_CMDADDR3(x) (((x) >> S_CMDADDR3) & M_CMDADDR3)
22609 #define V_WRDATAVLD3(x) ((x) << S_WRDATAVLD3)
22610 #define F_WRDATAVLD3    V_WRDATAVLD3(1U)
22613 #define V_WRDATARDY3(x) ((x) << S_WRDATARDY3)
22614 #define F_WRDATARDY3    V_WRDATARDY3(1U)
22617 #define V_RDDATARDY3(x) ((x) << S_RDDATARDY3)
22618 #define F_RDDATARDY3    V_RDDATARDY3(1U)
22621 #define V_RDDATAVLD3(x) ((x) << S_RDDATAVLD3)
22622 #define F_RDDATAVLD3    V_RDDATAVLD3(1U)
22626 #define V_RDDATA3(x) ((x) << S_RDDATA3)
22627 #define G_RDDATA3(x) (((x) >> S_RDDATA3) & M_RDDATA3)
22632 #define V_CMDVLD4(x) ((x) << S_CMDVLD4)
22633 #define F_CMDVLD4    V_CMDVLD4(1U)
22636 #define V_CMDRDY4(x) ((x) << S_CMDRDY4)
22637 #define F_CMDRDY4    V_CMDRDY4(1U)
22640 #define V_CMDTYPE4(x) ((x) << S_CMDTYPE4)
22641 #define F_CMDTYPE4    V_CMDTYPE4(1U)
22645 #define V_CMDLEN4(x) ((x) << S_CMDLEN4)
22646 #define G_CMDLEN4(x) (((x) >> S_CMDLEN4) & M_CMDLEN4)
22650 #define V_CMDADDR4(x) ((x) << S_CMDADDR4)
22651 #define G_CMDADDR4(x) (((x) >> S_CMDADDR4) & M_CMDADDR4)
22654 #define V_WRDATAVLD4(x) ((x) << S_WRDATAVLD4)
22655 #define F_WRDATAVLD4    V_WRDATAVLD4(1U)
22658 #define V_WRDATARDY4(x) ((x) << S_WRDATARDY4)
22659 #define F_WRDATARDY4    V_WRDATARDY4(1U)
22662 #define V_RDDATARDY4(x) ((x) << S_RDDATARDY4)
22663 #define F_RDDATARDY4    V_RDDATARDY4(1U)
22666 #define V_RDDATAVLD4(x) ((x) << S_RDDATAVLD4)
22667 #define F_RDDATAVLD4    V_RDDATAVLD4(1U)
22671 #define V_RDDATA4(x) ((x) << S_RDDATA4)
22672 #define G_RDDATA4(x) (((x) >> S_RDDATA4) & M_RDDATA4)
22677 #define V_CMDVLD5(x) ((x) << S_CMDVLD5)
22678 #define F_CMDVLD5    V_CMDVLD5(1U)
22681 #define V_CMDRDY5(x) ((x) << S_CMDRDY5)
22682 #define F_CMDRDY5    V_CMDRDY5(1U)
22685 #define V_CMDTYPE5(x) ((x) << S_CMDTYPE5)
22686 #define F_CMDTYPE5    V_CMDTYPE5(1U)
22690 #define V_CMDLEN5(x) ((x) << S_CMDLEN5)
22691 #define G_CMDLEN5(x) (((x) >> S_CMDLEN5) & M_CMDLEN5)
22695 #define V_CMDADDR5(x) ((x) << S_CMDADDR5)
22696 #define G_CMDADDR5(x) (((x) >> S_CMDADDR5) & M_CMDADDR5)
22699 #define V_WRDATAVLD5(x) ((x) << S_WRDATAVLD5)
22700 #define F_WRDATAVLD5    V_WRDATAVLD5(1U)
22703 #define V_WRDATARDY5(x) ((x) << S_WRDATARDY5)
22704 #define F_WRDATARDY5    V_WRDATARDY5(1U)
22707 #define V_RDDATARDY5(x) ((x) << S_RDDATARDY5)
22708 #define F_RDDATARDY5    V_RDDATARDY5(1U)
22711 #define V_RDDATAVLD5(x) ((x) << S_RDDATAVLD5)
22712 #define F_RDDATAVLD5    V_RDDATAVLD5(1U)
22716 #define V_RDDATA5(x) ((x) << S_RDDATA5)
22717 #define G_RDDATA5(x) (((x) >> S_RDDATA5) & M_RDDATA5)
22722 #define V_CMDVLD6(x) ((x) << S_CMDVLD6)
22723 #define F_CMDVLD6    V_CMDVLD6(1U)
22726 #define V_CMDRDY6(x) ((x) << S_CMDRDY6)
22727 #define F_CMDRDY6    V_CMDRDY6(1U)
22730 #define V_CMDTYPE6(x) ((x) << S_CMDTYPE6)
22731 #define F_CMDTYPE6    V_CMDTYPE6(1U)
22735 #define V_CMDLEN6(x) ((x) << S_CMDLEN6)
22736 #define G_CMDLEN6(x) (((x) >> S_CMDLEN6) & M_CMDLEN6)
22740 #define V_CMDADDR6(x) ((x) << S_CMDADDR6)
22741 #define G_CMDADDR6(x) (((x) >> S_CMDADDR6) & M_CMDADDR6)
22744 #define V_WRDATAVLD6(x) ((x) << S_WRDATAVLD6)
22745 #define F_WRDATAVLD6    V_WRDATAVLD6(1U)
22748 #define V_WRDATARDY6(x) ((x) << S_WRDATARDY6)
22749 #define F_WRDATARDY6    V_WRDATARDY6(1U)
22752 #define V_RDDATARDY6(x) ((x) << S_RDDATARDY6)
22753 #define F_RDDATARDY6    V_RDDATARDY6(1U)
22756 #define V_RDDATAVLD6(x) ((x) << S_RDDATAVLD6)
22757 #define F_RDDATAVLD6    V_RDDATAVLD6(1U)
22761 #define V_RDDATA6(x) ((x) << S_RDDATA6)
22762 #define G_RDDATA6(x) (((x) >> S_RDDATA6) & M_RDDATA6)
22767 #define V_CMDVLD7(x) ((x) << S_CMDVLD7)
22768 #define F_CMDVLD7    V_CMDVLD7(1U)
22771 #define V_CMDRDY7(x) ((x) << S_CMDRDY7)
22772 #define F_CMDRDY7    V_CMDRDY7(1U)
22775 #define V_CMDTYPE7(x) ((x) << S_CMDTYPE7)
22776 #define F_CMDTYPE7    V_CMDTYPE7(1U)
22780 #define V_CMDLEN7(x) ((x) << S_CMDLEN7)
22781 #define G_CMDLEN7(x) (((x) >> S_CMDLEN7) & M_CMDLEN7)
22785 #define V_CMDADDR7(x) ((x) << S_CMDADDR7)
22786 #define G_CMDADDR7(x) (((x) >> S_CMDADDR7) & M_CMDADDR7)
22789 #define V_WRDATAVLD7(x) ((x) << S_WRDATAVLD7)
22790 #define F_WRDATAVLD7    V_WRDATAVLD7(1U)
22793 #define V_WRDATARDY7(x) ((x) << S_WRDATARDY7)
22794 #define F_WRDATARDY7    V_WRDATARDY7(1U)
22797 #define V_RDDATARDY7(x) ((x) << S_RDDATARDY7)
22798 #define F_RDDATARDY7    V_RDDATARDY7(1U)
22801 #define V_RDDATAVLD7(x) ((x) << S_RDDATAVLD7)
22802 #define F_RDDATAVLD7    V_RDDATAVLD7(1U)
22806 #define V_RDDATA7(x) ((x) << S_RDDATA7)
22807 #define G_RDDATA7(x) (((x) >> S_RDDATA7) & M_RDDATA7)
22812 #define V_CMDVLD8(x) ((x) << S_CMDVLD8)
22813 #define F_CMDVLD8    V_CMDVLD8(1U)
22816 #define V_CMDRDY8(x) ((x) << S_CMDRDY8)
22817 #define F_CMDRDY8    V_CMDRDY8(1U)
22820 #define V_CMDTYPE8(x) ((x) << S_CMDTYPE8)
22821 #define F_CMDTYPE8    V_CMDTYPE8(1U)
22825 #define V_CMDLEN8(x) ((x) << S_CMDLEN8)
22826 #define G_CMDLEN8(x) (((x) >> S_CMDLEN8) & M_CMDLEN8)
22830 #define V_CMDADDR8(x) ((x) << S_CMDADDR8)
22831 #define G_CMDADDR8(x) (((x) >> S_CMDADDR8) & M_CMDADDR8)
22834 #define V_WRDATAVLD8(x) ((x) << S_WRDATAVLD8)
22835 #define F_WRDATAVLD8    V_WRDATAVLD8(1U)
22838 #define V_WRDATARDY8(x) ((x) << S_WRDATARDY8)
22839 #define F_WRDATARDY8    V_WRDATARDY8(1U)
22842 #define V_RDDATARDY8(x) ((x) << S_RDDATARDY8)
22843 #define F_RDDATARDY8    V_RDDATARDY8(1U)
22846 #define V_RDDATAVLD8(x) ((x) << S_RDDATAVLD8)
22847 #define F_RDDATAVLD8    V_RDDATAVLD8(1U)
22851 #define V_RDDATA8(x) ((x) << S_RDDATA8)
22852 #define G_RDDATA8(x) (((x) >> S_RDDATA8) & M_RDDATA8)
22857 #define V_CMDVLD9(x) ((x) << S_CMDVLD9)
22858 #define F_CMDVLD9    V_CMDVLD9(1U)
22861 #define V_CMDRDY9(x) ((x) << S_CMDRDY9)
22862 #define F_CMDRDY9    V_CMDRDY9(1U)
22865 #define V_CMDTYPE9(x) ((x) << S_CMDTYPE9)
22866 #define F_CMDTYPE9    V_CMDTYPE9(1U)
22870 #define V_CMDLEN9(x) ((x) << S_CMDLEN9)
22871 #define G_CMDLEN9(x) (((x) >> S_CMDLEN9) & M_CMDLEN9)
22875 #define V_CMDADDR9(x) ((x) << S_CMDADDR9)
22876 #define G_CMDADDR9(x) (((x) >> S_CMDADDR9) & M_CMDADDR9)
22879 #define V_WRDATAVLD9(x) ((x) << S_WRDATAVLD9)
22880 #define F_WRDATAVLD9    V_WRDATAVLD9(1U)
22883 #define V_WRDATARDY9(x) ((x) << S_WRDATARDY9)
22884 #define F_WRDATARDY9    V_WRDATARDY9(1U)
22887 #define V_RDDATARDY9(x) ((x) << S_RDDATARDY9)
22888 #define F_RDDATARDY9    V_RDDATARDY9(1U)
22891 #define V_RDDATAVLD9(x) ((x) << S_RDDATAVLD9)
22892 #define F_RDDATAVLD9    V_RDDATAVLD9(1U)
22896 #define V_RDDATA9(x) ((x) << S_RDDATA9)
22897 #define G_RDDATA9(x) (((x) >> S_RDDATA9) & M_RDDATA9)
22902 #define V_CMDVLD10(x) ((x) << S_CMDVLD10)
22903 #define F_CMDVLD10    V_CMDVLD10(1U)
22906 #define V_CMDRDY10(x) ((x) << S_CMDRDY10)
22907 #define F_CMDRDY10    V_CMDRDY10(1U)
22910 #define V_CMDTYPE10(x) ((x) << S_CMDTYPE10)
22911 #define F_CMDTYPE10    V_CMDTYPE10(1U)
22915 #define V_CMDLEN10(x) ((x) << S_CMDLEN10)
22916 #define G_CMDLEN10(x) (((x) >> S_CMDLEN10) & M_CMDLEN10)
22920 #define V_CMDADDR10(x) ((x) << S_CMDADDR10)
22921 #define G_CMDADDR10(x) (((x) >> S_CMDADDR10) & M_CMDADDR10)
22924 #define V_WRDATAVLD10(x) ((x) << S_WRDATAVLD10)
22925 #define F_WRDATAVLD10    V_WRDATAVLD10(1U)
22928 #define V_WRDATARDY10(x) ((x) << S_WRDATARDY10)
22929 #define F_WRDATARDY10    V_WRDATARDY10(1U)
22932 #define V_RDDATARDY10(x) ((x) << S_RDDATARDY10)
22933 #define F_RDDATARDY10    V_RDDATARDY10(1U)
22936 #define V_RDDATAVLD10(x) ((x) << S_RDDATAVLD10)
22937 #define F_RDDATAVLD10    V_RDDATAVLD10(1U)
22941 #define V_RDDATA10(x) ((x) << S_RDDATA10)
22942 #define G_RDDATA10(x) (((x) >> S_RDDATA10) & M_RDDATA10)
22947 #define V_CMDVLD11(x) ((x) << S_CMDVLD11)
22948 #define F_CMDVLD11    V_CMDVLD11(1U)
22951 #define V_CMDRDY11(x) ((x) << S_CMDRDY11)
22952 #define F_CMDRDY11    V_CMDRDY11(1U)
22955 #define V_CMDTYPE11(x) ((x) << S_CMDTYPE11)
22956 #define F_CMDTYPE11    V_CMDTYPE11(1U)
22960 #define V_CMDLEN11(x) ((x) << S_CMDLEN11)
22961 #define G_CMDLEN11(x) (((x) >> S_CMDLEN11) & M_CMDLEN11)
22965 #define V_CMDADDR11(x) ((x) << S_CMDADDR11)
22966 #define G_CMDADDR11(x) (((x) >> S_CMDADDR11) & M_CMDADDR11)
22969 #define V_WRDATAVLD11(x) ((x) << S_WRDATAVLD11)
22970 #define F_WRDATAVLD11    V_WRDATAVLD11(1U)
22973 #define V_WRDATARDY11(x) ((x) << S_WRDATARDY11)
22974 #define F_WRDATARDY11    V_WRDATARDY11(1U)
22977 #define V_RDDATARDY11(x) ((x) << S_RDDATARDY11)
22978 #define F_RDDATARDY11    V_RDDATARDY11(1U)
22981 #define V_RDDATAVLD11(x) ((x) << S_RDDATAVLD11)
22982 #define F_RDDATAVLD11    V_RDDATAVLD11(1U)
22986 #define V_RDDATA11(x) ((x) << S_RDDATA11)
22987 #define G_RDDATA11(x) (((x) >> S_RDDATA11) & M_RDDATA11)
22992 #define V_CMDVLD12(x) ((x) << S_CMDVLD12)
22993 #define F_CMDVLD12    V_CMDVLD12(1U)
22996 #define V_CMDRDY12(x) ((x) << S_CMDRDY12)
22997 #define F_CMDRDY12    V_CMDRDY12(1U)
23000 #define V_CMDTYPE12(x) ((x) << S_CMDTYPE12)
23001 #define F_CMDTYPE12    V_CMDTYPE12(1U)
23005 #define V_CMDLEN12(x) ((x) << S_CMDLEN12)
23006 #define G_CMDLEN12(x) (((x) >> S_CMDLEN12) & M_CMDLEN12)
23010 #define V_CMDADDR12(x) ((x) << S_CMDADDR12)
23011 #define G_CMDADDR12(x) (((x) >> S_CMDADDR12) & M_CMDADDR12)
23014 #define V_WRDATAVLD12(x) ((x) << S_WRDATAVLD12)
23015 #define F_WRDATAVLD12    V_WRDATAVLD12(1U)
23018 #define V_WRDATARDY12(x) ((x) << S_WRDATARDY12)
23019 #define F_WRDATARDY12    V_WRDATARDY12(1U)
23022 #define V_RDDATARDY12(x) ((x) << S_RDDATARDY12)
23023 #define F_RDDATARDY12    V_RDDATARDY12(1U)
23026 #define V_RDDATAVLD12(x) ((x) << S_RDDATAVLD12)
23027 #define F_RDDATAVLD12    V_RDDATAVLD12(1U)
23031 #define V_RDDATA12(x) ((x) << S_RDDATA12)
23032 #define G_RDDATA12(x) (((x) >> S_RDDATA12) & M_RDDATA12)
23037 #define V_CI0_ARB0_REQ(x) ((x) << S_CI0_ARB0_REQ)
23038 #define F_CI0_ARB0_REQ    V_CI0_ARB0_REQ(1U)
23041 #define V_ARB0_CI0_GNT(x) ((x) << S_ARB0_CI0_GNT)
23042 #define F_ARB0_CI0_GNT    V_ARB0_CI0_GNT(1U)
23045 #define V_CI0_DM0_WDATA_VLD(x) ((x) << S_CI0_DM0_WDATA_VLD)
23046 #define F_CI0_DM0_WDATA_VLD    V_CI0_DM0_WDATA_VLD(1U)
23049 #define V_DM0_CI0_RDATA_VLD(x) ((x) << S_DM0_CI0_RDATA_VLD)
23050 #define F_DM0_CI0_RDATA_VLD    V_DM0_CI0_RDATA_VLD(1U)
23053 #define V_CI1_ARB0_REQ(x) ((x) << S_CI1_ARB0_REQ)
23054 #define F_CI1_ARB0_REQ    V_CI1_ARB0_REQ(1U)
23057 #define V_ARB0_CI1_GNT(x) ((x) << S_ARB0_CI1_GNT)
23058 #define F_ARB0_CI1_GNT    V_ARB0_CI1_GNT(1U)
23061 #define V_CI1_DM0_WDATA_VLD(x) ((x) << S_CI1_DM0_WDATA_VLD)
23062 #define F_CI1_DM0_WDATA_VLD    V_CI1_DM0_WDATA_VLD(1U)
23065 #define V_DM0_CI1_RDATA_VLD(x) ((x) << S_DM0_CI1_RDATA_VLD)
23066 #define F_DM0_CI1_RDATA_VLD    V_DM0_CI1_RDATA_VLD(1U)
23069 #define V_CI2_ARB0_REQ(x) ((x) << S_CI2_ARB0_REQ)
23070 #define F_CI2_ARB0_REQ    V_CI2_ARB0_REQ(1U)
23073 #define V_ARB0_CI2_GNT(x) ((x) << S_ARB0_CI2_GNT)
23074 #define F_ARB0_CI2_GNT    V_ARB0_CI2_GNT(1U)
23077 #define V_CI2_DM0_WDATA_VLD(x) ((x) << S_CI2_DM0_WDATA_VLD)
23078 #define F_CI2_DM0_WDATA_VLD    V_CI2_DM0_WDATA_VLD(1U)
23081 #define V_DM0_CI2_RDATA_VLD(x) ((x) << S_DM0_CI2_RDATA_VLD)
23082 #define F_DM0_CI2_RDATA_VLD    V_DM0_CI2_RDATA_VLD(1U)
23085 #define V_CI3_ARB0_REQ(x) ((x) << S_CI3_ARB0_REQ)
23086 #define F_CI3_ARB0_REQ    V_CI3_ARB0_REQ(1U)
23089 #define V_ARB0_CI3_GNT(x) ((x) << S_ARB0_CI3_GNT)
23090 #define F_ARB0_CI3_GNT    V_ARB0_CI3_GNT(1U)
23093 #define V_CI3_DM0_WDATA_VLD(x) ((x) << S_CI3_DM0_WDATA_VLD)
23094 #define F_CI3_DM0_WDATA_VLD    V_CI3_DM0_WDATA_VLD(1U)
23097 #define V_DM0_CI3_RDATA_VLD(x) ((x) << S_DM0_CI3_RDATA_VLD)
23098 #define F_DM0_CI3_RDATA_VLD    V_DM0_CI3_RDATA_VLD(1U)
23101 #define V_CI4_ARB0_REQ(x) ((x) << S_CI4_ARB0_REQ)
23102 #define F_CI4_ARB0_REQ    V_CI4_ARB0_REQ(1U)
23105 #define V_ARB0_CI4_GNT(x) ((x) << S_ARB0_CI4_GNT)
23106 #define F_ARB0_CI4_GNT    V_ARB0_CI4_GNT(1U)
23109 #define V_CI4_DM0_WDATA_VLD(x) ((x) << S_CI4_DM0_WDATA_VLD)
23110 #define F_CI4_DM0_WDATA_VLD    V_CI4_DM0_WDATA_VLD(1U)
23113 #define V_DM0_CI4_RDATA_VLD(x) ((x) << S_DM0_CI4_RDATA_VLD)
23114 #define F_DM0_CI4_RDATA_VLD    V_DM0_CI4_RDATA_VLD(1U)
23117 #define V_CI5_ARB0_REQ(x) ((x) << S_CI5_ARB0_REQ)
23118 #define F_CI5_ARB0_REQ    V_CI5_ARB0_REQ(1U)
23121 #define V_ARB0_CI5_GNT(x) ((x) << S_ARB0_CI5_GNT)
23122 #define F_ARB0_CI5_GNT    V_ARB0_CI5_GNT(1U)
23125 #define V_CI5_DM0_WDATA_VLD(x) ((x) << S_CI5_DM0_WDATA_VLD)
23126 #define F_CI5_DM0_WDATA_VLD    V_CI5_DM0_WDATA_VLD(1U)
23129 #define V_DM0_CI5_RDATA_VLD(x) ((x) << S_DM0_CI5_RDATA_VLD)
23130 #define F_DM0_CI5_RDATA_VLD    V_DM0_CI5_RDATA_VLD(1U)
23133 #define V_CI6_ARB0_REQ(x) ((x) << S_CI6_ARB0_REQ)
23134 #define F_CI6_ARB0_REQ    V_CI6_ARB0_REQ(1U)
23137 #define V_ARB0_CI6_GNT(x) ((x) << S_ARB0_CI6_GNT)
23138 #define F_ARB0_CI6_GNT    V_ARB0_CI6_GNT(1U)
23141 #define V_CI6_DM0_WDATA_VLD(x) ((x) << S_CI6_DM0_WDATA_VLD)
23142 #define F_CI6_DM0_WDATA_VLD    V_CI6_DM0_WDATA_VLD(1U)
23145 #define V_DM0_CI6_RDATA_VLD(x) ((x) << S_DM0_CI6_RDATA_VLD)
23146 #define F_DM0_CI6_RDATA_VLD    V_DM0_CI6_RDATA_VLD(1U)
23149 #define V_CI7_ARB0_REQ(x) ((x) << S_CI7_ARB0_REQ)
23150 #define F_CI7_ARB0_REQ    V_CI7_ARB0_REQ(1U)
23153 #define V_ARB0_CI7_GNT(x) ((x) << S_ARB0_CI7_GNT)
23154 #define F_ARB0_CI7_GNT    V_ARB0_CI7_GNT(1U)
23156 #define S_CI7_DM0_WDATA_VLD    1
23157 #define V_CI7_DM0_WDATA_VLD(x) ((x) << S_CI7_DM0_WDATA_VLD)
23158 #define F_CI7_DM0_WDATA_VLD    V_CI7_DM0_WDATA_VLD(1U)
23161 #define V_DM0_CI7_RDATA_VLD(x) ((x) << S_DM0_CI7_RDATA_VLD)
23162 #define F_DM0_CI7_RDATA_VLD    V_DM0_CI7_RDATA_VLD(1U)
23167 #define V_CI0_ARB1_REQ(x) ((x) << S_CI0_ARB1_REQ)
23168 #define F_CI0_ARB1_REQ    V_CI0_ARB1_REQ(1U)
23171 #define V_ARB1_CI0_GNT(x) ((x) << S_ARB1_CI0_GNT)
23172 #define F_ARB1_CI0_GNT    V_ARB1_CI0_GNT(1U)
23175 #define V_CI0_DM1_WDATA_VLD(x) ((x) << S_CI0_DM1_WDATA_VLD)
23176 #define F_CI0_DM1_WDATA_VLD    V_CI0_DM1_WDATA_VLD(1U)
23179 #define V_DM1_CI0_RDATA_VLD(x) ((x) << S_DM1_CI0_RDATA_VLD)
23180 #define F_DM1_CI0_RDATA_VLD    V_DM1_CI0_RDATA_VLD(1U)
23183 #define V_CI1_ARB1_REQ(x) ((x) << S_CI1_ARB1_REQ)
23184 #define F_CI1_ARB1_REQ    V_CI1_ARB1_REQ(1U)
23187 #define V_ARB1_CI1_GNT(x) ((x) << S_ARB1_CI1_GNT)
23188 #define F_ARB1_CI1_GNT    V_ARB1_CI1_GNT(1U)
23191 #define V_CI1_DM1_WDATA_VLD(x) ((x) << S_CI1_DM1_WDATA_VLD)
23192 #define F_CI1_DM1_WDATA_VLD    V_CI1_DM1_WDATA_VLD(1U)
23195 #define V_DM1_CI1_RDATA_VLD(x) ((x) << S_DM1_CI1_RDATA_VLD)
23196 #define F_DM1_CI1_RDATA_VLD    V_DM1_CI1_RDATA_VLD(1U)
23199 #define V_CI2_ARB1_REQ(x) ((x) << S_CI2_ARB1_REQ)
23200 #define F_CI2_ARB1_REQ    V_CI2_ARB1_REQ(1U)
23203 #define V_ARB1_CI2_GNT(x) ((x) << S_ARB1_CI2_GNT)
23204 #define F_ARB1_CI2_GNT    V_ARB1_CI2_GNT(1U)
23207 #define V_CI2_DM1_WDATA_VLD(x) ((x) << S_CI2_DM1_WDATA_VLD)
23208 #define F_CI2_DM1_WDATA_VLD    V_CI2_DM1_WDATA_VLD(1U)
23211 #define V_DM1_CI2_RDATA_VLD(x) ((x) << S_DM1_CI2_RDATA_VLD)
23212 #define F_DM1_CI2_RDATA_VLD    V_DM1_CI2_RDATA_VLD(1U)
23215 #define V_CI3_ARB1_REQ(x) ((x) << S_CI3_ARB1_REQ)
23216 #define F_CI3_ARB1_REQ    V_CI3_ARB1_REQ(1U)
23219 #define V_ARB1_CI3_GNT(x) ((x) << S_ARB1_CI3_GNT)
23220 #define F_ARB1_CI3_GNT    V_ARB1_CI3_GNT(1U)
23223 #define V_CI3_DM1_WDATA_VLD(x) ((x) << S_CI3_DM1_WDATA_VLD)
23224 #define F_CI3_DM1_WDATA_VLD    V_CI3_DM1_WDATA_VLD(1U)
23227 #define V_DM1_CI3_RDATA_VLD(x) ((x) << S_DM1_CI3_RDATA_VLD)
23228 #define F_DM1_CI3_RDATA_VLD    V_DM1_CI3_RDATA_VLD(1U)
23231 #define V_CI4_ARB1_REQ(x) ((x) << S_CI4_ARB1_REQ)
23232 #define F_CI4_ARB1_REQ    V_CI4_ARB1_REQ(1U)
23235 #define V_ARB1_CI4_GNT(x) ((x) << S_ARB1_CI4_GNT)
23236 #define F_ARB1_CI4_GNT    V_ARB1_CI4_GNT(1U)
23239 #define V_CI4_DM1_WDATA_VLD(x) ((x) << S_CI4_DM1_WDATA_VLD)
23240 #define F_CI4_DM1_WDATA_VLD    V_CI4_DM1_WDATA_VLD(1U)
23243 #define V_DM1_CI4_RDATA_VLD(x) ((x) << S_DM1_CI4_RDATA_VLD)
23244 #define F_DM1_CI4_RDATA_VLD    V_DM1_CI4_RDATA_VLD(1U)
23247 #define V_CI5_ARB1_REQ(x) ((x) << S_CI5_ARB1_REQ)
23248 #define F_CI5_ARB1_REQ    V_CI5_ARB1_REQ(1U)
23251 #define V_ARB1_CI5_GNT(x) ((x) << S_ARB1_CI5_GNT)
23252 #define F_ARB1_CI5_GNT    V_ARB1_CI5_GNT(1U)
23255 #define V_CI5_DM1_WDATA_VLD(x) ((x) << S_CI5_DM1_WDATA_VLD)
23256 #define F_CI5_DM1_WDATA_VLD    V_CI5_DM1_WDATA_VLD(1U)
23259 #define V_DM1_CI5_RDATA_VLD(x) ((x) << S_DM1_CI5_RDATA_VLD)
23260 #define F_DM1_CI5_RDATA_VLD    V_DM1_CI5_RDATA_VLD(1U)
23263 #define V_CI6_ARB1_REQ(x) ((x) << S_CI6_ARB1_REQ)
23264 #define F_CI6_ARB1_REQ    V_CI6_ARB1_REQ(1U)
23267 #define V_ARB1_CI6_GNT(x) ((x) << S_ARB1_CI6_GNT)
23268 #define F_ARB1_CI6_GNT    V_ARB1_CI6_GNT(1U)
23271 #define V_CI6_DM1_WDATA_VLD(x) ((x) << S_CI6_DM1_WDATA_VLD)
23272 #define F_CI6_DM1_WDATA_VLD    V_CI6_DM1_WDATA_VLD(1U)
23275 #define V_DM1_CI6_RDATA_VLD(x) ((x) << S_DM1_CI6_RDATA_VLD)
23276 #define F_DM1_CI6_RDATA_VLD    V_DM1_CI6_RDATA_VLD(1U)
23279 #define V_CI7_ARB1_REQ(x) ((x) << S_CI7_ARB1_REQ)
23280 #define F_CI7_ARB1_REQ    V_CI7_ARB1_REQ(1U)
23283 #define V_ARB1_CI7_GNT(x) ((x) << S_ARB1_CI7_GNT)
23284 #define F_ARB1_CI7_GNT    V_ARB1_CI7_GNT(1U)
23286 #define S_CI7_DM1_WDATA_VLD    1
23287 #define V_CI7_DM1_WDATA_VLD(x) ((x) << S_CI7_DM1_WDATA_VLD)
23288 #define F_CI7_DM1_WDATA_VLD    V_CI7_DM1_WDATA_VLD(1U)
23291 #define V_DM1_CI7_RDATA_VLD(x) ((x) << S_DM1_CI7_RDATA_VLD)
23292 #define F_DM1_CI7_RDATA_VLD    V_DM1_CI7_RDATA_VLD(1U)
23297 #define V_CI0_ARB2_REQ(x) ((x) << S_CI0_ARB2_REQ)
23298 #define F_CI0_ARB2_REQ    V_CI0_ARB2_REQ(1U)
23301 #define V_ARB2_CI0_GNT(x) ((x) << S_ARB2_CI0_GNT)
23302 #define F_ARB2_CI0_GNT    V_ARB2_CI0_GNT(1U)
23305 #define V_CI0_DM2_WDATA_VLD(x) ((x) << S_CI0_DM2_WDATA_VLD)
23306 #define F_CI0_DM2_WDATA_VLD    V_CI0_DM2_WDATA_VLD(1U)
23309 #define V_DM2_CI0_RDATA_VLD(x) ((x) << S_DM2_CI0_RDATA_VLD)
23310 #define F_DM2_CI0_RDATA_VLD    V_DM2_CI0_RDATA_VLD(1U)
23313 #define V_CI1_ARB2_REQ(x) ((x) << S_CI1_ARB2_REQ)
23314 #define F_CI1_ARB2_REQ    V_CI1_ARB2_REQ(1U)
23317 #define V_ARB2_CI1_GNT(x) ((x) << S_ARB2_CI1_GNT)
23318 #define F_ARB2_CI1_GNT    V_ARB2_CI1_GNT(1U)
23321 #define V_CI1_DM2_WDATA_VLD(x) ((x) << S_CI1_DM2_WDATA_VLD)
23322 #define F_CI1_DM2_WDATA_VLD    V_CI1_DM2_WDATA_VLD(1U)
23325 #define V_DM2_CI1_RDATA_VLD(x) ((x) << S_DM2_CI1_RDATA_VLD)
23326 #define F_DM2_CI1_RDATA_VLD    V_DM2_CI1_RDATA_VLD(1U)
23329 #define V_CI2_ARB2_REQ(x) ((x) << S_CI2_ARB2_REQ)
23330 #define F_CI2_ARB2_REQ    V_CI2_ARB2_REQ(1U)
23333 #define V_ARB2_CI2_GNT(x) ((x) << S_ARB2_CI2_GNT)
23334 #define F_ARB2_CI2_GNT    V_ARB2_CI2_GNT(1U)
23337 #define V_CI2_DM2_WDATA_VLD(x) ((x) << S_CI2_DM2_WDATA_VLD)
23338 #define F_CI2_DM2_WDATA_VLD    V_CI2_DM2_WDATA_VLD(1U)
23341 #define V_DM2_CI2_RDATA_VLD(x) ((x) << S_DM2_CI2_RDATA_VLD)
23342 #define F_DM2_CI2_RDATA_VLD    V_DM2_CI2_RDATA_VLD(1U)
23345 #define V_CI3_ARB2_REQ(x) ((x) << S_CI3_ARB2_REQ)
23346 #define F_CI3_ARB2_REQ    V_CI3_ARB2_REQ(1U)
23349 #define V_ARB2_CI3_GNT(x) ((x) << S_ARB2_CI3_GNT)
23350 #define F_ARB2_CI3_GNT    V_ARB2_CI3_GNT(1U)
23353 #define V_CI3_DM2_WDATA_VLD(x) ((x) << S_CI3_DM2_WDATA_VLD)
23354 #define F_CI3_DM2_WDATA_VLD    V_CI3_DM2_WDATA_VLD(1U)
23357 #define V_DM2_CI3_RDATA_VLD(x) ((x) << S_DM2_CI3_RDATA_VLD)
23358 #define F_DM2_CI3_RDATA_VLD    V_DM2_CI3_RDATA_VLD(1U)
23361 #define V_CI4_ARB2_REQ(x) ((x) << S_CI4_ARB2_REQ)
23362 #define F_CI4_ARB2_REQ    V_CI4_ARB2_REQ(1U)
23365 #define V_ARB2_CI4_GNT(x) ((x) << S_ARB2_CI4_GNT)
23366 #define F_ARB2_CI4_GNT    V_ARB2_CI4_GNT(1U)
23369 #define V_CI4_DM2_WDATA_VLD(x) ((x) << S_CI4_DM2_WDATA_VLD)
23370 #define F_CI4_DM2_WDATA_VLD    V_CI4_DM2_WDATA_VLD(1U)
23373 #define V_DM2_CI4_RDATA_VLD(x) ((x) << S_DM2_CI4_RDATA_VLD)
23374 #define F_DM2_CI4_RDATA_VLD    V_DM2_CI4_RDATA_VLD(1U)
23377 #define V_CI5_ARB2_REQ(x) ((x) << S_CI5_ARB2_REQ)
23378 #define F_CI5_ARB2_REQ    V_CI5_ARB2_REQ(1U)
23381 #define V_ARB2_CI5_GNT(x) ((x) << S_ARB2_CI5_GNT)
23382 #define F_ARB2_CI5_GNT    V_ARB2_CI5_GNT(1U)
23385 #define V_CI5_DM2_WDATA_VLD(x) ((x) << S_CI5_DM2_WDATA_VLD)
23386 #define F_CI5_DM2_WDATA_VLD    V_CI5_DM2_WDATA_VLD(1U)
23389 #define V_DM2_CI5_RDATA_VLD(x) ((x) << S_DM2_CI5_RDATA_VLD)
23390 #define F_DM2_CI5_RDATA_VLD    V_DM2_CI5_RDATA_VLD(1U)
23393 #define V_CI6_ARB2_REQ(x) ((x) << S_CI6_ARB2_REQ)
23394 #define F_CI6_ARB2_REQ    V_CI6_ARB2_REQ(1U)
23397 #define V_ARB2_CI6_GNT(x) ((x) << S_ARB2_CI6_GNT)
23398 #define F_ARB2_CI6_GNT    V_ARB2_CI6_GNT(1U)
23401 #define V_CI6_DM2_WDATA_VLD(x) ((x) << S_CI6_DM2_WDATA_VLD)
23402 #define F_CI6_DM2_WDATA_VLD    V_CI6_DM2_WDATA_VLD(1U)
23405 #define V_DM2_CI6_RDATA_VLD(x) ((x) << S_DM2_CI6_RDATA_VLD)
23406 #define F_DM2_CI6_RDATA_VLD    V_DM2_CI6_RDATA_VLD(1U)
23409 #define V_CI7_ARB2_REQ(x) ((x) << S_CI7_ARB2_REQ)
23410 #define F_CI7_ARB2_REQ    V_CI7_ARB2_REQ(1U)
23413 #define V_ARB2_CI7_GNT(x) ((x) << S_ARB2_CI7_GNT)
23414 #define F_ARB2_CI7_GNT    V_ARB2_CI7_GNT(1U)
23416 #define S_CI7_DM2_WDATA_VLD    1
23417 #define V_CI7_DM2_WDATA_VLD(x) ((x) << S_CI7_DM2_WDATA_VLD)
23418 #define F_CI7_DM2_WDATA_VLD    V_CI7_DM2_WDATA_VLD(1U)
23421 #define V_DM2_CI7_RDATA_VLD(x) ((x) << S_DM2_CI7_RDATA_VLD)
23422 #define F_DM2_CI7_RDATA_VLD    V_DM2_CI7_RDATA_VLD(1U)
23427 #define V_CI0_ARB3_REQ(x) ((x) << S_CI0_ARB3_REQ)
23428 #define F_CI0_ARB3_REQ    V_CI0_ARB3_REQ(1U)
23431 #define V_ARB3_CI0_GNT(x) ((x) << S_ARB3_CI0_GNT)
23432 #define F_ARB3_CI0_GNT    V_ARB3_CI0_GNT(1U)
23435 #define V_CI0_DM3_WDATA_VLD(x) ((x) << S_CI0_DM3_WDATA_VLD)
23436 #define F_CI0_DM3_WDATA_VLD    V_CI0_DM3_WDATA_VLD(1U)
23439 #define V_DM3_CI0_RDATA_VLD(x) ((x) << S_DM3_CI0_RDATA_VLD)
23440 #define F_DM3_CI0_RDATA_VLD    V_DM3_CI0_RDATA_VLD(1U)
23443 #define V_CI1_ARB3_REQ(x) ((x) << S_CI1_ARB3_REQ)
23444 #define F_CI1_ARB3_REQ    V_CI1_ARB3_REQ(1U)
23447 #define V_ARB3_CI1_GNT(x) ((x) << S_ARB3_CI1_GNT)
23448 #define F_ARB3_CI1_GNT    V_ARB3_CI1_GNT(1U)
23451 #define V_CI1_DM3_WDATA_VLD(x) ((x) << S_CI1_DM3_WDATA_VLD)
23452 #define F_CI1_DM3_WDATA_VLD    V_CI1_DM3_WDATA_VLD(1U)
23455 #define V_DM3_CI1_RDATA_VLD(x) ((x) << S_DM3_CI1_RDATA_VLD)
23456 #define F_DM3_CI1_RDATA_VLD    V_DM3_CI1_RDATA_VLD(1U)
23459 #define V_CI2_ARB3_REQ(x) ((x) << S_CI2_ARB3_REQ)
23460 #define F_CI2_ARB3_REQ    V_CI2_ARB3_REQ(1U)
23463 #define V_ARB3_CI2_GNT(x) ((x) << S_ARB3_CI2_GNT)
23464 #define F_ARB3_CI2_GNT    V_ARB3_CI2_GNT(1U)
23467 #define V_CI2_DM3_WDATA_VLD(x) ((x) << S_CI2_DM3_WDATA_VLD)
23468 #define F_CI2_DM3_WDATA_VLD    V_CI2_DM3_WDATA_VLD(1U)
23471 #define V_DM3_CI2_RDATA_VLD(x) ((x) << S_DM3_CI2_RDATA_VLD)
23472 #define F_DM3_CI2_RDATA_VLD    V_DM3_CI2_RDATA_VLD(1U)
23475 #define V_CI3_ARB3_REQ(x) ((x) << S_CI3_ARB3_REQ)
23476 #define F_CI3_ARB3_REQ    V_CI3_ARB3_REQ(1U)
23479 #define V_ARB3_CI3_GNT(x) ((x) << S_ARB3_CI3_GNT)
23480 #define F_ARB3_CI3_GNT    V_ARB3_CI3_GNT(1U)
23483 #define V_CI3_DM3_WDATA_VLD(x) ((x) << S_CI3_DM3_WDATA_VLD)
23484 #define F_CI3_DM3_WDATA_VLD    V_CI3_DM3_WDATA_VLD(1U)
23487 #define V_DM3_CI3_RDATA_VLD(x) ((x) << S_DM3_CI3_RDATA_VLD)
23488 #define F_DM3_CI3_RDATA_VLD    V_DM3_CI3_RDATA_VLD(1U)
23491 #define V_CI4_ARB3_REQ(x) ((x) << S_CI4_ARB3_REQ)
23492 #define F_CI4_ARB3_REQ    V_CI4_ARB3_REQ(1U)
23495 #define V_ARB3_CI4_GNT(x) ((x) << S_ARB3_CI4_GNT)
23496 #define F_ARB3_CI4_GNT    V_ARB3_CI4_GNT(1U)
23499 #define V_CI4_DM3_WDATA_VLD(x) ((x) << S_CI4_DM3_WDATA_VLD)
23500 #define F_CI4_DM3_WDATA_VLD    V_CI4_DM3_WDATA_VLD(1U)
23503 #define V_DM3_CI4_RDATA_VLD(x) ((x) << S_DM3_CI4_RDATA_VLD)
23504 #define F_DM3_CI4_RDATA_VLD    V_DM3_CI4_RDATA_VLD(1U)
23507 #define V_CI5_ARB3_REQ(x) ((x) << S_CI5_ARB3_REQ)
23508 #define F_CI5_ARB3_REQ    V_CI5_ARB3_REQ(1U)
23511 #define V_ARB3_CI5_GNT(x) ((x) << S_ARB3_CI5_GNT)
23512 #define F_ARB3_CI5_GNT    V_ARB3_CI5_GNT(1U)
23515 #define V_CI5_DM3_WDATA_VLD(x) ((x) << S_CI5_DM3_WDATA_VLD)
23516 #define F_CI5_DM3_WDATA_VLD    V_CI5_DM3_WDATA_VLD(1U)
23519 #define V_DM3_CI5_RDATA_VLD(x) ((x) << S_DM3_CI5_RDATA_VLD)
23520 #define F_DM3_CI5_RDATA_VLD    V_DM3_CI5_RDATA_VLD(1U)
23523 #define V_CI6_ARB3_REQ(x) ((x) << S_CI6_ARB3_REQ)
23524 #define F_CI6_ARB3_REQ    V_CI6_ARB3_REQ(1U)
23527 #define V_ARB3_CI6_GNT(x) ((x) << S_ARB3_CI6_GNT)
23528 #define F_ARB3_CI6_GNT    V_ARB3_CI6_GNT(1U)
23531 #define V_CI6_DM3_WDATA_VLD(x) ((x) << S_CI6_DM3_WDATA_VLD)
23532 #define F_CI6_DM3_WDATA_VLD    V_CI6_DM3_WDATA_VLD(1U)
23535 #define V_DM3_CI6_RDATA_VLD(x) ((x) << S_DM3_CI6_RDATA_VLD)
23536 #define F_DM3_CI6_RDATA_VLD    V_DM3_CI6_RDATA_VLD(1U)
23539 #define V_CI7_ARB3_REQ(x) ((x) << S_CI7_ARB3_REQ)
23540 #define F_CI7_ARB3_REQ    V_CI7_ARB3_REQ(1U)
23543 #define V_ARB3_CI7_GNT(x) ((x) << S_ARB3_CI7_GNT)
23544 #define F_ARB3_CI7_GNT    V_ARB3_CI7_GNT(1U)
23546 #define S_CI7_DM3_WDATA_VLD    1
23547 #define V_CI7_DM3_WDATA_VLD(x) ((x) << S_CI7_DM3_WDATA_VLD)
23548 #define F_CI7_DM3_WDATA_VLD    V_CI7_DM3_WDATA_VLD(1U)
23551 #define V_DM3_CI7_RDATA_VLD(x) ((x) << S_DM3_CI7_RDATA_VLD)
23552 #define F_DM3_CI7_RDATA_VLD    V_DM3_CI7_RDATA_VLD(1U)
23559 #define V_CI8_ARB0_REQ(x) ((x) << S_CI8_ARB0_REQ)
23560 #define F_CI8_ARB0_REQ    V_CI8_ARB0_REQ(1U)
23563 #define V_ARB0_CI8_GNT(x) ((x) << S_ARB0_CI8_GNT)
23564 #define F_ARB0_CI8_GNT    V_ARB0_CI8_GNT(1U)
23567 #define V_CI8_DM0_WDATA_VLD(x) ((x) << S_CI8_DM0_WDATA_VLD)
23568 #define F_CI8_DM0_WDATA_VLD    V_CI8_DM0_WDATA_VLD(1U)
23571 #define V_DM0_CI8_RDATA_VLD(x) ((x) << S_DM0_CI8_RDATA_VLD)
23572 #define F_DM0_CI8_RDATA_VLD    V_DM0_CI8_RDATA_VLD(1U)
23575 #define V_CI9_ARB0_REQ(x) ((x) << S_CI9_ARB0_REQ)
23576 #define F_CI9_ARB0_REQ    V_CI9_ARB0_REQ(1U)
23579 #define V_ARB0_CI9_GNT(x) ((x) << S_ARB0_CI9_GNT)
23580 #define F_ARB0_CI9_GNT    V_ARB0_CI9_GNT(1U)
23583 #define V_CI9_DM0_WDATA_VLD(x) ((x) << S_CI9_DM0_WDATA_VLD)
23584 #define F_CI9_DM0_WDATA_VLD    V_CI9_DM0_WDATA_VLD(1U)
23587 #define V_DM0_CI9_RDATA_VLD(x) ((x) << S_DM0_CI9_RDATA_VLD)
23588 #define F_DM0_CI9_RDATA_VLD    V_DM0_CI9_RDATA_VLD(1U)
23591 #define V_CI10_ARB0_REQ(x) ((x) << S_CI10_ARB0_REQ)
23592 #define F_CI10_ARB0_REQ    V_CI10_ARB0_REQ(1U)
23595 #define V_ARB0_CI10_GNT(x) ((x) << S_ARB0_CI10_GNT)
23596 #define F_ARB0_CI10_GNT    V_ARB0_CI10_GNT(1U)
23599 #define V_CI10_DM0_WDATA_VLD(x) ((x) << S_CI10_DM0_WDATA_VLD)
23600 #define F_CI10_DM0_WDATA_VLD    V_CI10_DM0_WDATA_VLD(1U)
23603 #define V_DM0_CI10_RDATA_VLD(x) ((x) << S_DM0_CI10_RDATA_VLD)
23604 #define F_DM0_CI10_RDATA_VLD    V_DM0_CI10_RDATA_VLD(1U)
23607 #define V_CI11_ARB0_REQ(x) ((x) << S_CI11_ARB0_REQ)
23608 #define F_CI11_ARB0_REQ    V_CI11_ARB0_REQ(1U)
23611 #define V_ARB0_CI11_GNT(x) ((x) << S_ARB0_CI11_GNT)
23612 #define F_ARB0_CI11_GNT    V_ARB0_CI11_GNT(1U)
23615 #define V_CI11_DM0_WDATA_VLD(x) ((x) << S_CI11_DM0_WDATA_VLD)
23616 #define F_CI11_DM0_WDATA_VLD    V_CI11_DM0_WDATA_VLD(1U)
23619 #define V_DM0_CI11_RDATA_VLD(x) ((x) << S_DM0_CI11_RDATA_VLD)
23620 #define F_DM0_CI11_RDATA_VLD    V_DM0_CI11_RDATA_VLD(1U)
23623 #define V_CI12_ARB0_REQ(x) ((x) << S_CI12_ARB0_REQ)
23624 #define F_CI12_ARB0_REQ    V_CI12_ARB0_REQ(1U)
23627 #define V_ARB0_CI12_GNT(x) ((x) << S_ARB0_CI12_GNT)
23628 #define F_ARB0_CI12_GNT    V_ARB0_CI12_GNT(1U)
23631 #define V_CI12_DM0_WDATA_VLD(x) ((x) << S_CI12_DM0_WDATA_VLD)
23632 #define F_CI12_DM0_WDATA_VLD    V_CI12_DM0_WDATA_VLD(1U)
23635 #define V_DM0_CI12_RDATA_VLD(x) ((x) << S_DM0_CI12_RDATA_VLD)
23636 #define F_DM0_CI12_RDATA_VLD    V_DM0_CI12_RDATA_VLD(1U)
23641 #define V_CI8_ARB1_REQ(x) ((x) << S_CI8_ARB1_REQ)
23642 #define F_CI8_ARB1_REQ    V_CI8_ARB1_REQ(1U)
23645 #define V_ARB1_CI8_GNT(x) ((x) << S_ARB1_CI8_GNT)
23646 #define F_ARB1_CI8_GNT    V_ARB1_CI8_GNT(1U)
23649 #define V_CI8_DM1_WDATA_VLD(x) ((x) << S_CI8_DM1_WDATA_VLD)
23650 #define F_CI8_DM1_WDATA_VLD    V_CI8_DM1_WDATA_VLD(1U)
23653 #define V_DM1_CI8_RDATA_VLD(x) ((x) << S_DM1_CI8_RDATA_VLD)
23654 #define F_DM1_CI8_RDATA_VLD    V_DM1_CI8_RDATA_VLD(1U)
23657 #define V_CI9_ARB1_REQ(x) ((x) << S_CI9_ARB1_REQ)
23658 #define F_CI9_ARB1_REQ    V_CI9_ARB1_REQ(1U)
23661 #define V_ARB1_CI9_GNT(x) ((x) << S_ARB1_CI9_GNT)
23662 #define F_ARB1_CI9_GNT    V_ARB1_CI9_GNT(1U)
23665 #define V_CI9_DM1_WDATA_VLD(x) ((x) << S_CI9_DM1_WDATA_VLD)
23666 #define F_CI9_DM1_WDATA_VLD    V_CI9_DM1_WDATA_VLD(1U)
23669 #define V_DM1_CI9_RDATA_VLD(x) ((x) << S_DM1_CI9_RDATA_VLD)
23670 #define F_DM1_CI9_RDATA_VLD    V_DM1_CI9_RDATA_VLD(1U)
23673 #define V_CI10_ARB1_REQ(x) ((x) << S_CI10_ARB1_REQ)
23674 #define F_CI10_ARB1_REQ    V_CI10_ARB1_REQ(1U)
23677 #define V_ARB1_CI10_GNT(x) ((x) << S_ARB1_CI10_GNT)
23678 #define F_ARB1_CI10_GNT    V_ARB1_CI10_GNT(1U)
23681 #define V_CI10_DM1_WDATA_VLD(x) ((x) << S_CI10_DM1_WDATA_VLD)
23682 #define F_CI10_DM1_WDATA_VLD    V_CI10_DM1_WDATA_VLD(1U)
23685 #define V_DM1_CI10_RDATA_VLD(x) ((x) << S_DM1_CI10_RDATA_VLD)
23686 #define F_DM1_CI10_RDATA_VLD    V_DM1_CI10_RDATA_VLD(1U)
23689 #define V_CI11_ARB1_REQ(x) ((x) << S_CI11_ARB1_REQ)
23690 #define F_CI11_ARB1_REQ    V_CI11_ARB1_REQ(1U)
23693 #define V_ARB1_CI11_GNT(x) ((x) << S_ARB1_CI11_GNT)
23694 #define F_ARB1_CI11_GNT    V_ARB1_CI11_GNT(1U)
23697 #define V_CI11_DM1_WDATA_VLD(x) ((x) << S_CI11_DM1_WDATA_VLD)
23698 #define F_CI11_DM1_WDATA_VLD    V_CI11_DM1_WDATA_VLD(1U)
23701 #define V_DM1_CI11_RDATA_VLD(x) ((x) << S_DM1_CI11_RDATA_VLD)
23702 #define F_DM1_CI11_RDATA_VLD    V_DM1_CI11_RDATA_VLD(1U)
23705 #define V_CI12_ARB1_REQ(x) ((x) << S_CI12_ARB1_REQ)
23706 #define F_CI12_ARB1_REQ    V_CI12_ARB1_REQ(1U)
23709 #define V_ARB1_CI12_GNT(x) ((x) << S_ARB1_CI12_GNT)
23710 #define F_ARB1_CI12_GNT    V_ARB1_CI12_GNT(1U)
23713 #define V_CI12_DM1_WDATA_VLD(x) ((x) << S_CI12_DM1_WDATA_VLD)
23714 #define F_CI12_DM1_WDATA_VLD    V_CI12_DM1_WDATA_VLD(1U)
23717 #define V_DM1_CI12_RDATA_VLD(x) ((x) << S_DM1_CI12_RDATA_VLD)
23718 #define F_DM1_CI12_RDATA_VLD    V_DM1_CI12_RDATA_VLD(1U)
23723 #define V_CI8_ARB2_REQ(x) ((x) << S_CI8_ARB2_REQ)
23724 #define F_CI8_ARB2_REQ    V_CI8_ARB2_REQ(1U)
23727 #define V_ARB2_CI8_GNT(x) ((x) << S_ARB2_CI8_GNT)
23728 #define F_ARB2_CI8_GNT    V_ARB2_CI8_GNT(1U)
23731 #define V_CI8_DM2_WDATA_VLD(x) ((x) << S_CI8_DM2_WDATA_VLD)
23732 #define F_CI8_DM2_WDATA_VLD    V_CI8_DM2_WDATA_VLD(1U)
23735 #define V_DM2_CI8_RDATA_VLD(x) ((x) << S_DM2_CI8_RDATA_VLD)
23736 #define F_DM2_CI8_RDATA_VLD    V_DM2_CI8_RDATA_VLD(1U)
23739 #define V_CI9_ARB2_REQ(x) ((x) << S_CI9_ARB2_REQ)
23740 #define F_CI9_ARB2_REQ    V_CI9_ARB2_REQ(1U)
23743 #define V_ARB2_CI9_GNT(x) ((x) << S_ARB2_CI9_GNT)
23744 #define F_ARB2_CI9_GNT    V_ARB2_CI9_GNT(1U)
23747 #define V_CI9_DM2_WDATA_VLD(x) ((x) << S_CI9_DM2_WDATA_VLD)
23748 #define F_CI9_DM2_WDATA_VLD    V_CI9_DM2_WDATA_VLD(1U)
23751 #define V_DM2_CI9_RDATA_VLD(x) ((x) << S_DM2_CI9_RDATA_VLD)
23752 #define F_DM2_CI9_RDATA_VLD    V_DM2_CI9_RDATA_VLD(1U)
23755 #define V_CI10_ARB2_REQ(x) ((x) << S_CI10_ARB2_REQ)
23756 #define F_CI10_ARB2_REQ    V_CI10_ARB2_REQ(1U)
23759 #define V_ARB2_CI10_GNT(x) ((x) << S_ARB2_CI10_GNT)
23760 #define F_ARB2_CI10_GNT    V_ARB2_CI10_GNT(1U)
23763 #define V_CI10_DM2_WDATA_VLD(x) ((x) << S_CI10_DM2_WDATA_VLD)
23764 #define F_CI10_DM2_WDATA_VLD    V_CI10_DM2_WDATA_VLD(1U)
23767 #define V_DM2_CI10_RDATA_VLD(x) ((x) << S_DM2_CI10_RDATA_VLD)
23768 #define F_DM2_CI10_RDATA_VLD    V_DM2_CI10_RDATA_VLD(1U)
23771 #define V_CI11_ARB2_REQ(x) ((x) << S_CI11_ARB2_REQ)
23772 #define F_CI11_ARB2_REQ    V_CI11_ARB2_REQ(1U)
23775 #define V_ARB2_CI11_GNT(x) ((x) << S_ARB2_CI11_GNT)
23776 #define F_ARB2_CI11_GNT    V_ARB2_CI11_GNT(1U)
23779 #define V_CI11_DM2_WDATA_VLD(x) ((x) << S_CI11_DM2_WDATA_VLD)
23780 #define F_CI11_DM2_WDATA_VLD    V_CI11_DM2_WDATA_VLD(1U)
23783 #define V_DM2_CI11_RDATA_VLD(x) ((x) << S_DM2_CI11_RDATA_VLD)
23784 #define F_DM2_CI11_RDATA_VLD    V_DM2_CI11_RDATA_VLD(1U)
23787 #define V_CI12_ARB2_REQ(x) ((x) << S_CI12_ARB2_REQ)
23788 #define F_CI12_ARB2_REQ    V_CI12_ARB2_REQ(1U)
23791 #define V_ARB2_CI12_GNT(x) ((x) << S_ARB2_CI12_GNT)
23792 #define F_ARB2_CI12_GNT    V_ARB2_CI12_GNT(1U)
23795 #define V_CI12_DM2_WDATA_VLD(x) ((x) << S_CI12_DM2_WDATA_VLD)
23796 #define F_CI12_DM2_WDATA_VLD    V_CI12_DM2_WDATA_VLD(1U)
23799 #define V_DM2_CI12_RDATA_VLD(x) ((x) << S_DM2_CI12_RDATA_VLD)
23800 #define F_DM2_CI12_RDATA_VLD    V_DM2_CI12_RDATA_VLD(1U)
23805 #define V_CI8_ARB3_REQ(x) ((x) << S_CI8_ARB3_REQ)
23806 #define F_CI8_ARB3_REQ    V_CI8_ARB3_REQ(1U)
23809 #define V_ARB3_CI8_GNT(x) ((x) << S_ARB3_CI8_GNT)
23810 #define F_ARB3_CI8_GNT    V_ARB3_CI8_GNT(1U)
23813 #define V_CI8_DM3_WDATA_VLD(x) ((x) << S_CI8_DM3_WDATA_VLD)
23814 #define F_CI8_DM3_WDATA_VLD    V_CI8_DM3_WDATA_VLD(1U)
23817 #define V_DM3_CI8_RDATA_VLD(x) ((x) << S_DM3_CI8_RDATA_VLD)
23818 #define F_DM3_CI8_RDATA_VLD    V_DM3_CI8_RDATA_VLD(1U)
23821 #define V_CI9_ARB3_REQ(x) ((x) << S_CI9_ARB3_REQ)
23822 #define F_CI9_ARB3_REQ    V_CI9_ARB3_REQ(1U)
23825 #define V_ARB3_CI9_GNT(x) ((x) << S_ARB3_CI9_GNT)
23826 #define F_ARB3_CI9_GNT    V_ARB3_CI9_GNT(1U)
23829 #define V_CI9_DM3_WDATA_VLD(x) ((x) << S_CI9_DM3_WDATA_VLD)
23830 #define F_CI9_DM3_WDATA_VLD    V_CI9_DM3_WDATA_VLD(1U)
23833 #define V_DM3_CI9_RDATA_VLD(x) ((x) << S_DM3_CI9_RDATA_VLD)
23834 #define F_DM3_CI9_RDATA_VLD    V_DM3_CI9_RDATA_VLD(1U)
23837 #define V_CI10_ARB3_REQ(x) ((x) << S_CI10_ARB3_REQ)
23838 #define F_CI10_ARB3_REQ    V_CI10_ARB3_REQ(1U)
23841 #define V_ARB3_CI10_GNT(x) ((x) << S_ARB3_CI10_GNT)
23842 #define F_ARB3_CI10_GNT    V_ARB3_CI10_GNT(1U)
23845 #define V_CI10_DM3_WDATA_VLD(x) ((x) << S_CI10_DM3_WDATA_VLD)
23846 #define F_CI10_DM3_WDATA_VLD    V_CI10_DM3_WDATA_VLD(1U)
23849 #define V_DM3_CI10_RDATA_VLD(x) ((x) << S_DM3_CI10_RDATA_VLD)
23850 #define F_DM3_CI10_RDATA_VLD    V_DM3_CI10_RDATA_VLD(1U)
23853 #define V_CI11_ARB3_REQ(x) ((x) << S_CI11_ARB3_REQ)
23854 #define F_CI11_ARB3_REQ    V_CI11_ARB3_REQ(1U)
23857 #define V_ARB3_CI11_GNT(x) ((x) << S_ARB3_CI11_GNT)
23858 #define F_ARB3_CI11_GNT    V_ARB3_CI11_GNT(1U)
23861 #define V_CI11_DM3_WDATA_VLD(x) ((x) << S_CI11_DM3_WDATA_VLD)
23862 #define F_CI11_DM3_WDATA_VLD    V_CI11_DM3_WDATA_VLD(1U)
23865 #define V_DM3_CI11_RDATA_VLD(x) ((x) << S_DM3_CI11_RDATA_VLD)
23866 #define F_DM3_CI11_RDATA_VLD    V_DM3_CI11_RDATA_VLD(1U)
23869 #define V_CI12_ARB3_REQ(x) ((x) << S_CI12_ARB3_REQ)
23870 #define F_CI12_ARB3_REQ    V_CI12_ARB3_REQ(1U)
23873 #define V_ARB3_CI12_GNT(x) ((x) << S_ARB3_CI12_GNT)
23874 #define F_ARB3_CI12_GNT    V_ARB3_CI12_GNT(1U)
23877 #define V_CI12_DM3_WDATA_VLD(x) ((x) << S_CI12_DM3_WDATA_VLD)
23878 #define F_CI12_DM3_WDATA_VLD    V_CI12_DM3_WDATA_VLD(1U)
23881 #define V_DM3_CI12_RDATA_VLD(x) ((x) << S_DM3_CI12_RDATA_VLD)
23882 #define F_DM3_CI12_RDATA_VLD    V_DM3_CI12_RDATA_VLD(1U)
23888 #define V_CMD_IN_FIFO_CNT0(x) ((x) << S_CMD_IN_FIFO_CNT0)
23889 #define G_CMD_IN_FIFO_CNT0(x) (((x) >> S_CMD_IN_FIFO_CNT0) & M_CMD_IN_FIFO_CNT0)
23893 #define V_CMD_SPLIT_FIFO_CNT0(x) ((x) << S_CMD_SPLIT_FIFO_CNT0)
23894 #define G_CMD_SPLIT_FIFO_CNT0(x) (((x) >> S_CMD_SPLIT_FIFO_CNT0) & M_CMD_SPLIT_FIFO_CNT0)
23898 #define V_CMD_THROTTLE_FIFO_CNT0(x) ((x) << S_CMD_THROTTLE_FIFO_CNT0)
23899 #define G_CMD_THROTTLE_FIFO_CNT0(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT0) & M_CMD_THROTTLE_FIFO_CNT0)
23903 #define V_RD_CHNL_FIFO_CNT0(x) ((x) << S_RD_CHNL_FIFO_CNT0)
23904 #define G_RD_CHNL_FIFO_CNT0(x) (((x) >> S_RD_CHNL_FIFO_CNT0) & M_RD_CHNL_FIFO_CNT0)
23908 #define V_RD_DATA_EXT_FIFO_CNT0(x) ((x) << S_RD_DATA_EXT_FIFO_CNT0)
23909 #define G_RD_DATA_EXT_FIFO_CNT0(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT0) & M_RD_DATA_EXT_FIFO_CNT0)
23913 #define V_RD_DATA_512B_FIFO_CNT0(x) ((x) << S_RD_DATA_512B_FIFO_CNT0)
23914 #define G_RD_DATA_512B_FIFO_CNT0(x) (((x) >> S_RD_DATA_512B_FIFO_CNT0) & M_RD_DATA_512B_FIFO_CNT0)
23916 #define S_RD_REQ_TAG_FIFO_CNT0    1
23918 #define V_RD_REQ_TAG_FIFO_CNT0(x) ((x) << S_RD_REQ_TAG_FIFO_CNT0)
23919 #define G_RD_REQ_TAG_FIFO_CNT0(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT0) & M_RD_REQ_TAG_FIFO_CNT0)
23925 #define V_CMD_IN_FIFO_CNT1(x) ((x) << S_CMD_IN_FIFO_CNT1)
23926 #define G_CMD_IN_FIFO_CNT1(x) (((x) >> S_CMD_IN_FIFO_CNT1) & M_CMD_IN_FIFO_CNT1)
23930 #define V_CMD_SPLIT_FIFO_CNT1(x) ((x) << S_CMD_SPLIT_FIFO_CNT1)
23931 #define G_CMD_SPLIT_FIFO_CNT1(x) (((x) >> S_CMD_SPLIT_FIFO_CNT1) & M_CMD_SPLIT_FIFO_CNT1)
23935 #define V_CMD_THROTTLE_FIFO_CNT1(x) ((x) << S_CMD_THROTTLE_FIFO_CNT1)
23936 #define G_CMD_THROTTLE_FIFO_CNT1(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT1) & M_CMD_THROTTLE_FIFO_CNT1)
23940 #define V_RD_CHNL_FIFO_CNT1(x) ((x) << S_RD_CHNL_FIFO_CNT1)
23941 #define G_RD_CHNL_FIFO_CNT1(x) (((x) >> S_RD_CHNL_FIFO_CNT1) & M_RD_CHNL_FIFO_CNT1)
23945 #define V_RD_DATA_EXT_FIFO_CNT1(x) ((x) << S_RD_DATA_EXT_FIFO_CNT1)
23946 #define G_RD_DATA_EXT_FIFO_CNT1(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT1) & M_RD_DATA_EXT_FIFO_CNT1)
23950 #define V_RD_DATA_512B_FIFO_CNT1(x) ((x) << S_RD_DATA_512B_FIFO_CNT1)
23951 #define G_RD_DATA_512B_FIFO_CNT1(x) (((x) >> S_RD_DATA_512B_FIFO_CNT1) & M_RD_DATA_512B_FIFO_CNT1)
23953 #define S_RD_REQ_TAG_FIFO_CNT1    1
23955 #define V_RD_REQ_TAG_FIFO_CNT1(x) ((x) << S_RD_REQ_TAG_FIFO_CNT1)
23956 #define G_RD_REQ_TAG_FIFO_CNT1(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT1) & M_RD_REQ_TAG_FIFO_CNT1)
23962 #define V_CMD_IN_FIFO_CNT2(x) ((x) << S_CMD_IN_FIFO_CNT2)
23963 #define G_CMD_IN_FIFO_CNT2(x) (((x) >> S_CMD_IN_FIFO_CNT2) & M_CMD_IN_FIFO_CNT2)
23967 #define V_CMD_SPLIT_FIFO_CNT2(x) ((x) << S_CMD_SPLIT_FIFO_CNT2)
23968 #define G_CMD_SPLIT_FIFO_CNT2(x) (((x) >> S_CMD_SPLIT_FIFO_CNT2) & M_CMD_SPLIT_FIFO_CNT2)
23972 #define V_CMD_THROTTLE_FIFO_CNT2(x) ((x) << S_CMD_THROTTLE_FIFO_CNT2)
23973 #define G_CMD_THROTTLE_FIFO_CNT2(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT2) & M_CMD_THROTTLE_FIFO_CNT2)
23977 #define V_RD_CHNL_FIFO_CNT2(x) ((x) << S_RD_CHNL_FIFO_CNT2)
23978 #define G_RD_CHNL_FIFO_CNT2(x) (((x) >> S_RD_CHNL_FIFO_CNT2) & M_RD_CHNL_FIFO_CNT2)
23982 #define V_RD_DATA_EXT_FIFO_CNT2(x) ((x) << S_RD_DATA_EXT_FIFO_CNT2)
23983 #define G_RD_DATA_EXT_FIFO_CNT2(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT2) & M_RD_DATA_EXT_FIFO_CNT2)
23987 #define V_RD_DATA_512B_FIFO_CNT2(x) ((x) << S_RD_DATA_512B_FIFO_CNT2)
23988 #define G_RD_DATA_512B_FIFO_CNT2(x) (((x) >> S_RD_DATA_512B_FIFO_CNT2) & M_RD_DATA_512B_FIFO_CNT2)
23990 #define S_RD_REQ_TAG_FIFO_CNT2    1
23992 #define V_RD_REQ_TAG_FIFO_CNT2(x) ((x) << S_RD_REQ_TAG_FIFO_CNT2)
23993 #define G_RD_REQ_TAG_FIFO_CNT2(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT2) & M_RD_REQ_TAG_FIFO_CNT2)
23999 #define V_CMD_IN_FIFO_CNT3(x) ((x) << S_CMD_IN_FIFO_CNT3)
24000 #define G_CMD_IN_FIFO_CNT3(x) (((x) >> S_CMD_IN_FIFO_CNT3) & M_CMD_IN_FIFO_CNT3)
24004 #define V_CMD_SPLIT_FIFO_CNT3(x) ((x) << S_CMD_SPLIT_FIFO_CNT3)
24005 #define G_CMD_SPLIT_FIFO_CNT3(x) (((x) >> S_CMD_SPLIT_FIFO_CNT3) & M_CMD_SPLIT_FIFO_CNT3)
24009 #define V_CMD_THROTTLE_FIFO_CNT3(x) ((x) << S_CMD_THROTTLE_FIFO_CNT3)
24010 #define G_CMD_THROTTLE_FIFO_CNT3(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT3) & M_CMD_THROTTLE_FIFO_CNT3)
24014 #define V_RD_CHNL_FIFO_CNT3(x) ((x) << S_RD_CHNL_FIFO_CNT3)
24015 #define G_RD_CHNL_FIFO_CNT3(x) (((x) >> S_RD_CHNL_FIFO_CNT3) & M_RD_CHNL_FIFO_CNT3)
24019 #define V_RD_DATA_EXT_FIFO_CNT3(x) ((x) << S_RD_DATA_EXT_FIFO_CNT3)
24020 #define G_RD_DATA_EXT_FIFO_CNT3(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT3) & M_RD_DATA_EXT_FIFO_CNT3)
24024 #define V_RD_DATA_512B_FIFO_CNT3(x) ((x) << S_RD_DATA_512B_FIFO_CNT3)
24025 #define G_RD_DATA_512B_FIFO_CNT3(x) (((x) >> S_RD_DATA_512B_FIFO_CNT3) & M_RD_DATA_512B_FIFO_CNT3)
24027 #define S_RD_REQ_TAG_FIFO_CNT3    1
24029 #define V_RD_REQ_TAG_FIFO_CNT3(x) ((x) << S_RD_REQ_TAG_FIFO_CNT3)
24030 #define G_RD_REQ_TAG_FIFO_CNT3(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT3) & M_RD_REQ_TAG_FIFO_CNT3)
24036 #define V_CMD_IN_FIFO_CNT4(x) ((x) << S_CMD_IN_FIFO_CNT4)
24037 #define G_CMD_IN_FIFO_CNT4(x) (((x) >> S_CMD_IN_FIFO_CNT4) & M_CMD_IN_FIFO_CNT4)
24041 #define V_CMD_SPLIT_FIFO_CNT4(x) ((x) << S_CMD_SPLIT_FIFO_CNT4)
24042 #define G_CMD_SPLIT_FIFO_CNT4(x) (((x) >> S_CMD_SPLIT_FIFO_CNT4) & M_CMD_SPLIT_FIFO_CNT4)
24046 #define V_CMD_THROTTLE_FIFO_CNT4(x) ((x) << S_CMD_THROTTLE_FIFO_CNT4)
24047 #define G_CMD_THROTTLE_FIFO_CNT4(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT4) & M_CMD_THROTTLE_FIFO_CNT4)
24051 #define V_RD_CHNL_FIFO_CNT4(x) ((x) << S_RD_CHNL_FIFO_CNT4)
24052 #define G_RD_CHNL_FIFO_CNT4(x) (((x) >> S_RD_CHNL_FIFO_CNT4) & M_RD_CHNL_FIFO_CNT4)
24056 #define V_RD_DATA_EXT_FIFO_CNT4(x) ((x) << S_RD_DATA_EXT_FIFO_CNT4)
24057 #define G_RD_DATA_EXT_FIFO_CNT4(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT4) & M_RD_DATA_EXT_FIFO_CNT4)
24061 #define V_RD_DATA_512B_FIFO_CNT4(x) ((x) << S_RD_DATA_512B_FIFO_CNT4)
24062 #define G_RD_DATA_512B_FIFO_CNT4(x) (((x) >> S_RD_DATA_512B_FIFO_CNT4) & M_RD_DATA_512B_FIFO_CNT4)
24064 #define S_RD_REQ_TAG_FIFO_CNT4    1
24066 #define V_RD_REQ_TAG_FIFO_CNT4(x) ((x) << S_RD_REQ_TAG_FIFO_CNT4)
24067 #define G_RD_REQ_TAG_FIFO_CNT4(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT4) & M_RD_REQ_TAG_FIFO_CNT4)
24073 #define V_CMD_IN_FIFO_CNT5(x) ((x) << S_CMD_IN_FIFO_CNT5)
24074 #define G_CMD_IN_FIFO_CNT5(x) (((x) >> S_CMD_IN_FIFO_CNT5) & M_CMD_IN_FIFO_CNT5)
24078 #define V_CMD_SPLIT_FIFO_CNT5(x) ((x) << S_CMD_SPLIT_FIFO_CNT5)
24079 #define G_CMD_SPLIT_FIFO_CNT5(x) (((x) >> S_CMD_SPLIT_FIFO_CNT5) & M_CMD_SPLIT_FIFO_CNT5)
24083 #define V_CMD_THROTTLE_FIFO_CNT5(x) ((x) << S_CMD_THROTTLE_FIFO_CNT5)
24084 #define G_CMD_THROTTLE_FIFO_CNT5(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT5) & M_CMD_THROTTLE_FIFO_CNT5)
24088 #define V_RD_CHNL_FIFO_CNT5(x) ((x) << S_RD_CHNL_FIFO_CNT5)
24089 #define G_RD_CHNL_FIFO_CNT5(x) (((x) >> S_RD_CHNL_FIFO_CNT5) & M_RD_CHNL_FIFO_CNT5)
24093 #define V_RD_DATA_EXT_FIFO_CNT5(x) ((x) << S_RD_DATA_EXT_FIFO_CNT5)
24094 #define G_RD_DATA_EXT_FIFO_CNT5(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT5) & M_RD_DATA_EXT_FIFO_CNT5)
24098 #define V_RD_DATA_512B_FIFO_CNT5(x) ((x) << S_RD_DATA_512B_FIFO_CNT5)
24099 #define G_RD_DATA_512B_FIFO_CNT5(x) (((x) >> S_RD_DATA_512B_FIFO_CNT5) & M_RD_DATA_512B_FIFO_CNT5)
24101 #define S_RD_REQ_TAG_FIFO_CNT5    1
24103 #define V_RD_REQ_TAG_FIFO_CNT5(x) ((x) << S_RD_REQ_TAG_FIFO_CNT5)
24104 #define G_RD_REQ_TAG_FIFO_CNT5(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT5) & M_RD_REQ_TAG_FIFO_CNT5)
24110 #define V_CMD_IN_FIFO_CNT6(x) ((x) << S_CMD_IN_FIFO_CNT6)
24111 #define G_CMD_IN_FIFO_CNT6(x) (((x) >> S_CMD_IN_FIFO_CNT6) & M_CMD_IN_FIFO_CNT6)
24115 #define V_CMD_SPLIT_FIFO_CNT6(x) ((x) << S_CMD_SPLIT_FIFO_CNT6)
24116 #define G_CMD_SPLIT_FIFO_CNT6(x) (((x) >> S_CMD_SPLIT_FIFO_CNT6) & M_CMD_SPLIT_FIFO_CNT6)
24120 #define V_CMD_THROTTLE_FIFO_CNT6(x) ((x) << S_CMD_THROTTLE_FIFO_CNT6)
24121 #define G_CMD_THROTTLE_FIFO_CNT6(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT6) & M_CMD_THROTTLE_FIFO_CNT6)
24125 #define V_RD_CHNL_FIFO_CNT6(x) ((x) << S_RD_CHNL_FIFO_CNT6)
24126 #define G_RD_CHNL_FIFO_CNT6(x) (((x) >> S_RD_CHNL_FIFO_CNT6) & M_RD_CHNL_FIFO_CNT6)
24130 #define V_RD_DATA_EXT_FIFO_CNT6(x) ((x) << S_RD_DATA_EXT_FIFO_CNT6)
24131 #define G_RD_DATA_EXT_FIFO_CNT6(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT6) & M_RD_DATA_EXT_FIFO_CNT6)
24135 #define V_RD_DATA_512B_FIFO_CNT6(x) ((x) << S_RD_DATA_512B_FIFO_CNT6)
24136 #define G_RD_DATA_512B_FIFO_CNT6(x) (((x) >> S_RD_DATA_512B_FIFO_CNT6) & M_RD_DATA_512B_FIFO_CNT6)
24138 #define S_RD_REQ_TAG_FIFO_CNT6    1
24140 #define V_RD_REQ_TAG_FIFO_CNT6(x) ((x) << S_RD_REQ_TAG_FIFO_CNT6)
24141 #define G_RD_REQ_TAG_FIFO_CNT6(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT6) & M_RD_REQ_TAG_FIFO_CNT6)
24147 #define V_CMD_IN_FIFO_CNT7(x) ((x) << S_CMD_IN_FIFO_CNT7)
24148 #define G_CMD_IN_FIFO_CNT7(x) (((x) >> S_CMD_IN_FIFO_CNT7) & M_CMD_IN_FIFO_CNT7)
24152 #define V_CMD_SPLIT_FIFO_CNT7(x) ((x) << S_CMD_SPLIT_FIFO_CNT7)
24153 #define G_CMD_SPLIT_FIFO_CNT7(x) (((x) >> S_CMD_SPLIT_FIFO_CNT7) & M_CMD_SPLIT_FIFO_CNT7)
24157 #define V_CMD_THROTTLE_FIFO_CNT7(x) ((x) << S_CMD_THROTTLE_FIFO_CNT7)
24158 #define G_CMD_THROTTLE_FIFO_CNT7(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT7) & M_CMD_THROTTLE_FIFO_CNT7)
24162 #define V_RD_CHNL_FIFO_CNT7(x) ((x) << S_RD_CHNL_FIFO_CNT7)
24163 #define G_RD_CHNL_FIFO_CNT7(x) (((x) >> S_RD_CHNL_FIFO_CNT7) & M_RD_CHNL_FIFO_CNT7)
24167 #define V_RD_DATA_EXT_FIFO_CNT7(x) ((x) << S_RD_DATA_EXT_FIFO_CNT7)
24168 #define G_RD_DATA_EXT_FIFO_CNT7(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT7) & M_RD_DATA_EXT_FIFO_CNT7)
24172 #define V_RD_DATA_512B_FIFO_CNT7(x) ((x) << S_RD_DATA_512B_FIFO_CNT7)
24173 #define G_RD_DATA_512B_FIFO_CNT7(x) (((x) >> S_RD_DATA_512B_FIFO_CNT7) & M_RD_DATA_512B_FIFO_CNT7)
24175 #define S_RD_REQ_TAG_FIFO_CNT7    1
24177 #define V_RD_REQ_TAG_FIFO_CNT7(x) ((x) << S_RD_REQ_TAG_FIFO_CNT7)
24178 #define G_RD_REQ_TAG_FIFO_CNT7(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT7) & M_RD_REQ_TAG_FIFO_CNT7)
24184 #define V_CMD_IN_FIFO_CNT8(x) ((x) << S_CMD_IN_FIFO_CNT8)
24185 #define G_CMD_IN_FIFO_CNT8(x) (((x) >> S_CMD_IN_FIFO_CNT8) & M_CMD_IN_FIFO_CNT8)
24189 #define V_CMD_SPLIT_FIFO_CNT8(x) ((x) << S_CMD_SPLIT_FIFO_CNT8)
24190 #define G_CMD_SPLIT_FIFO_CNT8(x) (((x) >> S_CMD_SPLIT_FIFO_CNT8) & M_CMD_SPLIT_FIFO_CNT8)
24194 #define V_CMD_THROTTLE_FIFO_CNT8(x) ((x) << S_CMD_THROTTLE_FIFO_CNT8)
24195 #define G_CMD_THROTTLE_FIFO_CNT8(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT8) & M_CMD_THROTTLE_FIFO_CNT8)
24199 #define V_RD_CHNL_FIFO_CNT8(x) ((x) << S_RD_CHNL_FIFO_CNT8)
24200 #define G_RD_CHNL_FIFO_CNT8(x) (((x) >> S_RD_CHNL_FIFO_CNT8) & M_RD_CHNL_FIFO_CNT8)
24204 #define V_RD_DATA_EXT_FIFO_CNT8(x) ((x) << S_RD_DATA_EXT_FIFO_CNT8)
24205 #define G_RD_DATA_EXT_FIFO_CNT8(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT8) & M_RD_DATA_EXT_FIFO_CNT8)
24209 #define V_RD_DATA_512B_FIFO_CNT8(x) ((x) << S_RD_DATA_512B_FIFO_CNT8)
24210 #define G_RD_DATA_512B_FIFO_CNT8(x) (((x) >> S_RD_DATA_512B_FIFO_CNT8) & M_RD_DATA_512B_FIFO_CNT8)
24212 #define S_RD_REQ_TAG_FIFO_CNT8    1
24214 #define V_RD_REQ_TAG_FIFO_CNT8(x) ((x) << S_RD_REQ_TAG_FIFO_CNT8)
24215 #define G_RD_REQ_TAG_FIFO_CNT8(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT8) & M_RD_REQ_TAG_FIFO_CNT8)
24221 #define V_CMD_IN_FIFO_CNT9(x) ((x) << S_CMD_IN_FIFO_CNT9)
24222 #define G_CMD_IN_FIFO_CNT9(x) (((x) >> S_CMD_IN_FIFO_CNT9) & M_CMD_IN_FIFO_CNT9)
24226 #define V_CMD_SPLIT_FIFO_CNT9(x) ((x) << S_CMD_SPLIT_FIFO_CNT9)
24227 #define G_CMD_SPLIT_FIFO_CNT9(x) (((x) >> S_CMD_SPLIT_FIFO_CNT9) & M_CMD_SPLIT_FIFO_CNT9)
24231 #define V_CMD_THROTTLE_FIFO_CNT9(x) ((x) << S_CMD_THROTTLE_FIFO_CNT9)
24232 #define G_CMD_THROTTLE_FIFO_CNT9(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT9) & M_CMD_THROTTLE_FIFO_CNT9)
24236 #define V_RD_CHNL_FIFO_CNT9(x) ((x) << S_RD_CHNL_FIFO_CNT9)
24237 #define G_RD_CHNL_FIFO_CNT9(x) (((x) >> S_RD_CHNL_FIFO_CNT9) & M_RD_CHNL_FIFO_CNT9)
24241 #define V_RD_DATA_EXT_FIFO_CNT9(x) ((x) << S_RD_DATA_EXT_FIFO_CNT9)
24242 #define G_RD_DATA_EXT_FIFO_CNT9(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT9) & M_RD_DATA_EXT_FIFO_CNT9)
24246 #define V_RD_DATA_512B_FIFO_CNT9(x) ((x) << S_RD_DATA_512B_FIFO_CNT9)
24247 #define G_RD_DATA_512B_FIFO_CNT9(x) (((x) >> S_RD_DATA_512B_FIFO_CNT9) & M_RD_DATA_512B_FIFO_CNT9)
24249 #define S_RD_REQ_TAG_FIFO_CNT9    1
24251 #define V_RD_REQ_TAG_FIFO_CNT9(x) ((x) << S_RD_REQ_TAG_FIFO_CNT9)
24252 #define G_RD_REQ_TAG_FIFO_CNT9(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT9) & M_RD_REQ_TAG_FIFO_CNT9)
24258 #define V_CMD_IN_FIFO_CNT10(x) ((x) << S_CMD_IN_FIFO_CNT10)
24259 #define G_CMD_IN_FIFO_CNT10(x) (((x) >> S_CMD_IN_FIFO_CNT10) & M_CMD_IN_FIFO_CNT10)
24263 #define V_CMD_SPLIT_FIFO_CNT10(x) ((x) << S_CMD_SPLIT_FIFO_CNT10)
24264 #define G_CMD_SPLIT_FIFO_CNT10(x) (((x) >> S_CMD_SPLIT_FIFO_CNT10) & M_CMD_SPLIT_FIFO_CNT10)
24268 #define V_CMD_THROTTLE_FIFO_CNT10(x) ((x) << S_CMD_THROTTLE_FIFO_CNT10)
24269 #define G_CMD_THROTTLE_FIFO_CNT10(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT10) & M_CMD_THROTTLE_FIFO_CNT10)
24273 #define V_RD_CHNL_FIFO_CNT10(x) ((x) << S_RD_CHNL_FIFO_CNT10)
24274 #define G_RD_CHNL_FIFO_CNT10(x) (((x) >> S_RD_CHNL_FIFO_CNT10) & M_RD_CHNL_FIFO_CNT10)
24278 #define V_RD_DATA_EXT_FIFO_CNT10(x) ((x) << S_RD_DATA_EXT_FIFO_CNT10)
24279 #define G_RD_DATA_EXT_FIFO_CNT10(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT10) & M_RD_DATA_EXT_FIFO_CNT10)
24283 #define V_RD_DATA_512B_FIFO_CNT10(x) ((x) << S_RD_DATA_512B_FIFO_CNT10)
24284 #define G_RD_DATA_512B_FIFO_CNT10(x) (((x) >> S_RD_DATA_512B_FIFO_CNT10) & M_RD_DATA_512B_FIFO_CNT10)
24286 #define S_RD_REQ_TAG_FIFO_CNT10    1
24288 #define V_RD_REQ_TAG_FIFO_CNT10(x) ((x) << S_RD_REQ_TAG_FIFO_CNT10)
24289 #define G_RD_REQ_TAG_FIFO_CNT10(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT10) & M_RD_REQ_TAG_FIFO_CNT10)
24295 #define V_CMD_IN_FIFO_CNT11(x) ((x) << S_CMD_IN_FIFO_CNT11)
24296 #define G_CMD_IN_FIFO_CNT11(x) (((x) >> S_CMD_IN_FIFO_CNT11) & M_CMD_IN_FIFO_CNT11)
24300 #define V_CMD_SPLIT_FIFO_CNT11(x) ((x) << S_CMD_SPLIT_FIFO_CNT11)
24301 #define G_CMD_SPLIT_FIFO_CNT11(x) (((x) >> S_CMD_SPLIT_FIFO_CNT11) & M_CMD_SPLIT_FIFO_CNT11)
24305 #define V_CMD_THROTTLE_FIFO_CNT11(x) ((x) << S_CMD_THROTTLE_FIFO_CNT11)
24306 #define G_CMD_THROTTLE_FIFO_CNT11(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT11) & M_CMD_THROTTLE_FIFO_CNT11)
24310 #define V_RD_CHNL_FIFO_CNT11(x) ((x) << S_RD_CHNL_FIFO_CNT11)
24311 #define G_RD_CHNL_FIFO_CNT11(x) (((x) >> S_RD_CHNL_FIFO_CNT11) & M_RD_CHNL_FIFO_CNT11)
24315 #define V_RD_DATA_EXT_FIFO_CNT11(x) ((x) << S_RD_DATA_EXT_FIFO_CNT11)
24316 #define G_RD_DATA_EXT_FIFO_CNT11(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT11) & M_RD_DATA_EXT_FIFO_CNT11)
24320 #define V_RD_DATA_512B_FIFO_CNT11(x) ((x) << S_RD_DATA_512B_FIFO_CNT11)
24321 #define G_RD_DATA_512B_FIFO_CNT11(x) (((x) >> S_RD_DATA_512B_FIFO_CNT11) & M_RD_DATA_512B_FIFO_CNT11)
24323 #define S_RD_REQ_TAG_FIFO_CNT11    1
24325 #define V_RD_REQ_TAG_FIFO_CNT11(x) ((x) << S_RD_REQ_TAG_FIFO_CNT11)
24326 #define G_RD_REQ_TAG_FIFO_CNT11(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT11) & M_RD_REQ_TAG_FIFO_CNT11)
24332 #define V_CMD_IN_FIFO_CNT12(x) ((x) << S_CMD_IN_FIFO_CNT12)
24333 #define G_CMD_IN_FIFO_CNT12(x) (((x) >> S_CMD_IN_FIFO_CNT12) & M_CMD_IN_FIFO_CNT12)
24337 #define V_CMD_SPLIT_FIFO_CNT12(x) ((x) << S_CMD_SPLIT_FIFO_CNT12)
24338 #define G_CMD_SPLIT_FIFO_CNT12(x) (((x) >> S_CMD_SPLIT_FIFO_CNT12) & M_CMD_SPLIT_FIFO_CNT12)
24342 #define V_CMD_THROTTLE_FIFO_CNT12(x) ((x) << S_CMD_THROTTLE_FIFO_CNT12)
24343 #define G_CMD_THROTTLE_FIFO_CNT12(x) (((x) >> S_CMD_THROTTLE_FIFO_CNT12) & M_CMD_THROTTLE_FIFO_CNT12)
24347 #define V_RD_CHNL_FIFO_CNT12(x) ((x) << S_RD_CHNL_FIFO_CNT12)
24348 #define G_RD_CHNL_FIFO_CNT12(x) (((x) >> S_RD_CHNL_FIFO_CNT12) & M_RD_CHNL_FIFO_CNT12)
24352 #define V_RD_DATA_EXT_FIFO_CNT12(x) ((x) << S_RD_DATA_EXT_FIFO_CNT12)
24353 #define G_RD_DATA_EXT_FIFO_CNT12(x) (((x) >> S_RD_DATA_EXT_FIFO_CNT12) & M_RD_DATA_EXT_FIFO_CNT12)
24357 #define V_RD_DATA_512B_FIFO_CNT12(x) ((x) << S_RD_DATA_512B_FIFO_CNT12)
24358 #define G_RD_DATA_512B_FIFO_CNT12(x) (((x) >> S_RD_DATA_512B_FIFO_CNT12) & M_RD_DATA_512B_FIFO_CNT12)
24360 #define S_RD_REQ_TAG_FIFO_CNT12    1
24362 #define V_RD_REQ_TAG_FIFO_CNT12(x) ((x) << S_RD_REQ_TAG_FIFO_CNT12)
24363 #define G_RD_REQ_TAG_FIFO_CNT12(x) (((x) >> S_RD_REQ_TAG_FIFO_CNT12) & M_RD_REQ_TAG_FIFO_CNT12)
24368 #define V_WR_DATA_FSM0(x) ((x) << S_WR_DATA_FSM0)
24369 #define F_WR_DATA_FSM0    V_WR_DATA_FSM0(1U)
24372 #define V_RD_DATA_FSM0(x) ((x) << S_RD_DATA_FSM0)
24373 #define F_RD_DATA_FSM0    V_RD_DATA_FSM0(1U)
24377 #define V_TGT_CMD_FIFO_CNT0(x) ((x) << S_TGT_CMD_FIFO_CNT0)
24378 #define G_TGT_CMD_FIFO_CNT0(x) (((x) >> S_TGT_CMD_FIFO_CNT0) & M_TGT_CMD_FIFO_CNT0)
24382 #define V_CLNT_NUM_FIFO_CNT0(x) ((x) << S_CLNT_NUM_FIFO_CNT0)
24383 #define G_CLNT_NUM_FIFO_CNT0(x) (((x) >> S_CLNT_NUM_FIFO_CNT0) & M_CLNT_NUM_FIFO_CNT0)
24387 #define V_WR_CMD_TAG_FIFO_CNT_TGT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT0)
24388 #define G_WR_CMD_TAG_FIFO_CNT_TGT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT0) & M_WR_CMD_TAG_FIFO_CNT_TGT0)
24392 #define V_WR_DATA_512B_FIFO_CNT_TGT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT0)
24393 #define G_WR_DATA_512B_FIFO_CNT_TGT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT0) & M_WR_DATA_512B_FIFO_CNT_TGT0)
24398 #define V_WR_DATA_FSM1(x) ((x) << S_WR_DATA_FSM1)
24399 #define F_WR_DATA_FSM1    V_WR_DATA_FSM1(1U)
24402 #define V_RD_DATA_FSM1(x) ((x) << S_RD_DATA_FSM1)
24403 #define F_RD_DATA_FSM1    V_RD_DATA_FSM1(1U)
24407 #define V_TGT_CMD_FIFO_CNT1(x) ((x) << S_TGT_CMD_FIFO_CNT1)
24408 #define G_TGT_CMD_FIFO_CNT1(x) (((x) >> S_TGT_CMD_FIFO_CNT1) & M_TGT_CMD_FIFO_CNT1)
24412 #define V_CLNT_NUM_FIFO_CNT1(x) ((x) << S_CLNT_NUM_FIFO_CNT1)
24413 #define G_CLNT_NUM_FIFO_CNT1(x) (((x) >> S_CLNT_NUM_FIFO_CNT1) & M_CLNT_NUM_FIFO_CNT1)
24417 #define V_WR_CMD_TAG_FIFO_CNT_TGT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT1)
24418 #define G_WR_CMD_TAG_FIFO_CNT_TGT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT1) & M_WR_CMD_TAG_FIFO_CNT_TGT1)
24422 #define V_WR_DATA_512B_FIFO_CNT_TGT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT1)
24423 #define G_WR_DATA_512B_FIFO_CNT_TGT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT1) & M_WR_DATA_512B_FIFO_CNT_TGT1)
24428 #define V_WR_DATA_FSM2(x) ((x) << S_WR_DATA_FSM2)
24429 #define F_WR_DATA_FSM2    V_WR_DATA_FSM2(1U)
24432 #define V_RD_DATA_FSM2(x) ((x) << S_RD_DATA_FSM2)
24433 #define F_RD_DATA_FSM2    V_RD_DATA_FSM2(1U)
24437 #define V_TGT_CMD_FIFO_CNT2(x) ((x) << S_TGT_CMD_FIFO_CNT2)
24438 #define G_TGT_CMD_FIFO_CNT2(x) (((x) >> S_TGT_CMD_FIFO_CNT2) & M_TGT_CMD_FIFO_CNT2)
24442 #define V_CLNT_NUM_FIFO_CNT2(x) ((x) << S_CLNT_NUM_FIFO_CNT2)
24443 #define G_CLNT_NUM_FIFO_CNT2(x) (((x) >> S_CLNT_NUM_FIFO_CNT2) & M_CLNT_NUM_FIFO_CNT2)
24447 #define V_WR_CMD_TAG_FIFO_CNT_TGT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT2)
24448 #define G_WR_CMD_TAG_FIFO_CNT_TGT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT2) & M_WR_CMD_TAG_FIFO_CNT_TGT2)
24452 #define V_WR_DATA_512B_FIFO_CNT_TGT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT2)
24453 #define G_WR_DATA_512B_FIFO_CNT_TGT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT2) & M_WR_DATA_512B_FIFO_CNT_TGT2)
24458 #define V_WR_DATA_FSM3(x) ((x) << S_WR_DATA_FSM3)
24459 #define F_WR_DATA_FSM3    V_WR_DATA_FSM3(1U)
24462 #define V_RD_DATA_FSM3(x) ((x) << S_RD_DATA_FSM3)
24463 #define F_RD_DATA_FSM3    V_RD_DATA_FSM3(1U)
24467 #define V_TGT_CMD_FIFO_CNT3(x) ((x) << S_TGT_CMD_FIFO_CNT3)
24468 #define G_TGT_CMD_FIFO_CNT3(x) (((x) >> S_TGT_CMD_FIFO_CNT3) & M_TGT_CMD_FIFO_CNT3)
24472 #define V_CLNT_NUM_FIFO_CNT3(x) ((x) << S_CLNT_NUM_FIFO_CNT3)
24473 #define G_CLNT_NUM_FIFO_CNT3(x) (((x) >> S_CLNT_NUM_FIFO_CNT3) & M_CLNT_NUM_FIFO_CNT3)
24477 #define V_WR_CMD_TAG_FIFO_CNT_TGT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT_TGT3)
24478 #define G_WR_CMD_TAG_FIFO_CNT_TGT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT_TGT3) & M_WR_CMD_TAG_FIFO_CNT_TGT3)
24482 #define V_WR_DATA_512B_FIFO_CNT_TGT(x) ((x) << S_WR_DATA_512B_FIFO_CNT_TGT)
24483 #define G_WR_DATA_512B_FIFO_CNT_TGT(x) (((x) >> S_WR_DATA_512B_FIFO_CNT_TGT) & M_WR_DATA_512B_FIFO_CNT_TGT)
24600 #define V_WR_DATA_EXT_FIFO_CNT0(x) ((x) << S_WR_DATA_EXT_FIFO_CNT0)
24601 #define G_WR_DATA_EXT_FIFO_CNT0(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT0) & M_WR_DATA_EXT_FIFO_CNT0)
24605 #define V_WR_CMD_TAG_FIFO_CNT0(x) ((x) << S_WR_CMD_TAG_FIFO_CNT0)
24606 #define G_WR_CMD_TAG_FIFO_CNT0(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT0) & M_WR_CMD_TAG_FIFO_CNT0)
24610 #define V_WR_DATA_512B_FIFO_CNT0(x) ((x) << S_WR_DATA_512B_FIFO_CNT0)
24611 #define G_WR_DATA_512B_FIFO_CNT0(x) (((x) >> S_WR_DATA_512B_FIFO_CNT0) & M_WR_DATA_512B_FIFO_CNT0)
24614 #define V_RD_DATA_ALIGN_FSM0(x) ((x) << S_RD_DATA_ALIGN_FSM0)
24615 #define F_RD_DATA_ALIGN_FSM0    V_RD_DATA_ALIGN_FSM0(1U)
24618 #define V_RD_DATA_FETCH_FSM0(x) ((x) << S_RD_DATA_FETCH_FSM0)
24619 #define F_RD_DATA_FETCH_FSM0    V_RD_DATA_FETCH_FSM0(1U)
24622 #define V_COHERENCY_TX_FSM0(x) ((x) << S_COHERENCY_TX_FSM0)
24623 #define F_COHERENCY_TX_FSM0    V_COHERENCY_TX_FSM0(1U)
24626 #define V_COHERENCY_RX_FSM0(x) ((x) << S_COHERENCY_RX_FSM0)
24627 #define F_COHERENCY_RX_FSM0    V_COHERENCY_RX_FSM0(1U)
24630 #define V_ARB_REQ_FSM0(x) ((x) << S_ARB_REQ_FSM0)
24631 #define F_ARB_REQ_FSM0    V_ARB_REQ_FSM0(1U)
24635 #define V_CMD_SPLIT_FSM0(x) ((x) << S_CMD_SPLIT_FSM0)
24636 #define G_CMD_SPLIT_FSM0(x) (((x) >> S_CMD_SPLIT_FSM0) & M_CMD_SPLIT_FSM0)
24642 #define V_WR_DATA_EXT_FIFO_CNT1(x) ((x) << S_WR_DATA_EXT_FIFO_CNT1)
24643 #define G_WR_DATA_EXT_FIFO_CNT1(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT1) & M_WR_DATA_EXT_FIFO_CNT1)
24647 #define V_WR_CMD_TAG_FIFO_CNT1(x) ((x) << S_WR_CMD_TAG_FIFO_CNT1)
24648 #define G_WR_CMD_TAG_FIFO_CNT1(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT1) & M_WR_CMD_TAG_FIFO_CNT1)
24652 #define V_WR_DATA_512B_FIFO_CNT1(x) ((x) << S_WR_DATA_512B_FIFO_CNT1)
24653 #define G_WR_DATA_512B_FIFO_CNT1(x) (((x) >> S_WR_DATA_512B_FIFO_CNT1) & M_WR_DATA_512B_FIFO_CNT1)
24656 #define V_RD_DATA_ALIGN_FSM1(x) ((x) << S_RD_DATA_ALIGN_FSM1)
24657 #define F_RD_DATA_ALIGN_FSM1    V_RD_DATA_ALIGN_FSM1(1U)
24660 #define V_RD_DATA_FETCH_FSM1(x) ((x) << S_RD_DATA_FETCH_FSM1)
24661 #define F_RD_DATA_FETCH_FSM1    V_RD_DATA_FETCH_FSM1(1U)
24664 #define V_COHERENCY_TX_FSM1(x) ((x) << S_COHERENCY_TX_FSM1)
24665 #define F_COHERENCY_TX_FSM1    V_COHERENCY_TX_FSM1(1U)
24668 #define V_COHERENCY_RX_FSM1(x) ((x) << S_COHERENCY_RX_FSM1)
24669 #define F_COHERENCY_RX_FSM1    V_COHERENCY_RX_FSM1(1U)
24672 #define V_ARB_REQ_FSM1(x) ((x) << S_ARB_REQ_FSM1)
24673 #define F_ARB_REQ_FSM1    V_ARB_REQ_FSM1(1U)
24677 #define V_CMD_SPLIT_FSM1(x) ((x) << S_CMD_SPLIT_FSM1)
24678 #define G_CMD_SPLIT_FSM1(x) (((x) >> S_CMD_SPLIT_FSM1) & M_CMD_SPLIT_FSM1)
24684 #define V_WR_DATA_EXT_FIFO_CNT2(x) ((x) << S_WR_DATA_EXT_FIFO_CNT2)
24685 #define G_WR_DATA_EXT_FIFO_CNT2(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT2) & M_WR_DATA_EXT_FIFO_CNT2)
24689 #define V_WR_CMD_TAG_FIFO_CNT2(x) ((x) << S_WR_CMD_TAG_FIFO_CNT2)
24690 #define G_WR_CMD_TAG_FIFO_CNT2(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT2) & M_WR_CMD_TAG_FIFO_CNT2)
24694 #define V_WR_DATA_512B_FIFO_CNT2(x) ((x) << S_WR_DATA_512B_FIFO_CNT2)
24695 #define G_WR_DATA_512B_FIFO_CNT2(x) (((x) >> S_WR_DATA_512B_FIFO_CNT2) & M_WR_DATA_512B_FIFO_CNT2)
24698 #define V_RD_DATA_ALIGN_FSM2(x) ((x) << S_RD_DATA_ALIGN_FSM2)
24699 #define F_RD_DATA_ALIGN_FSM2    V_RD_DATA_ALIGN_FSM2(1U)
24702 #define V_RD_DATA_FETCH_FSM2(x) ((x) << S_RD_DATA_FETCH_FSM2)
24703 #define F_RD_DATA_FETCH_FSM2    V_RD_DATA_FETCH_FSM2(1U)
24706 #define V_COHERENCY_TX_FSM2(x) ((x) << S_COHERENCY_TX_FSM2)
24707 #define F_COHERENCY_TX_FSM2    V_COHERENCY_TX_FSM2(1U)
24710 #define V_COHERENCY_RX_FSM2(x) ((x) << S_COHERENCY_RX_FSM2)
24711 #define F_COHERENCY_RX_FSM2    V_COHERENCY_RX_FSM2(1U)
24714 #define V_ARB_REQ_FSM2(x) ((x) << S_ARB_REQ_FSM2)
24715 #define F_ARB_REQ_FSM2    V_ARB_REQ_FSM2(1U)
24719 #define V_CMD_SPLIT_FSM2(x) ((x) << S_CMD_SPLIT_FSM2)
24720 #define G_CMD_SPLIT_FSM2(x) (((x) >> S_CMD_SPLIT_FSM2) & M_CMD_SPLIT_FSM2)
24726 #define V_WR_DATA_EXT_FIFO_CNT3(x) ((x) << S_WR_DATA_EXT_FIFO_CNT3)
24727 #define G_WR_DATA_EXT_FIFO_CNT3(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT3) & M_WR_DATA_EXT_FIFO_CNT3)
24731 #define V_WR_CMD_TAG_FIFO_CNT3(x) ((x) << S_WR_CMD_TAG_FIFO_CNT3)
24732 #define G_WR_CMD_TAG_FIFO_CNT3(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT3) & M_WR_CMD_TAG_FIFO_CNT3)
24736 #define V_WR_DATA_512B_FIFO_CNT3(x) ((x) << S_WR_DATA_512B_FIFO_CNT3)
24737 #define G_WR_DATA_512B_FIFO_CNT3(x) (((x) >> S_WR_DATA_512B_FIFO_CNT3) & M_WR_DATA_512B_FIFO_CNT3)
24740 #define V_RD_DATA_ALIGN_FSM3(x) ((x) << S_RD_DATA_ALIGN_FSM3)
24741 #define F_RD_DATA_ALIGN_FSM3    V_RD_DATA_ALIGN_FSM3(1U)
24744 #define V_RD_DATA_FETCH_FSM3(x) ((x) << S_RD_DATA_FETCH_FSM3)
24745 #define F_RD_DATA_FETCH_FSM3    V_RD_DATA_FETCH_FSM3(1U)
24748 #define V_COHERENCY_TX_FSM3(x) ((x) << S_COHERENCY_TX_FSM3)
24749 #define F_COHERENCY_TX_FSM3    V_COHERENCY_TX_FSM3(1U)
24752 #define V_COHERENCY_RX_FSM3(x) ((x) << S_COHERENCY_RX_FSM3)
24753 #define F_COHERENCY_RX_FSM3    V_COHERENCY_RX_FSM3(1U)
24756 #define V_ARB_REQ_FSM3(x) ((x) << S_ARB_REQ_FSM3)
24757 #define F_ARB_REQ_FSM3    V_ARB_REQ_FSM3(1U)
24761 #define V_CMD_SPLIT_FSM3(x) ((x) << S_CMD_SPLIT_FSM3)
24762 #define G_CMD_SPLIT_FSM3(x) (((x) >> S_CMD_SPLIT_FSM3) & M_CMD_SPLIT_FSM3)
24768 #define V_WR_DATA_EXT_FIFO_CNT4(x) ((x) << S_WR_DATA_EXT_FIFO_CNT4)
24769 #define G_WR_DATA_EXT_FIFO_CNT4(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT4) & M_WR_DATA_EXT_FIFO_CNT4)
24773 #define V_WR_CMD_TAG_FIFO_CNT4(x) ((x) << S_WR_CMD_TAG_FIFO_CNT4)
24774 #define G_WR_CMD_TAG_FIFO_CNT4(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT4) & M_WR_CMD_TAG_FIFO_CNT4)
24778 #define V_WR_DATA_512B_FIFO_CNT4(x) ((x) << S_WR_DATA_512B_FIFO_CNT4)
24779 #define G_WR_DATA_512B_FIFO_CNT4(x) (((x) >> S_WR_DATA_512B_FIFO_CNT4) & M_WR_DATA_512B_FIFO_CNT4)
24782 #define V_RD_DATA_ALIGN_FSM4(x) ((x) << S_RD_DATA_ALIGN_FSM4)
24783 #define F_RD_DATA_ALIGN_FSM4    V_RD_DATA_ALIGN_FSM4(1U)
24786 #define V_RD_DATA_FETCH_FSM4(x) ((x) << S_RD_DATA_FETCH_FSM4)
24787 #define F_RD_DATA_FETCH_FSM4    V_RD_DATA_FETCH_FSM4(1U)
24790 #define V_COHERENCY_TX_FSM4(x) ((x) << S_COHERENCY_TX_FSM4)
24791 #define F_COHERENCY_TX_FSM4    V_COHERENCY_TX_FSM4(1U)
24794 #define V_COHERENCY_RX_FSM4(x) ((x) << S_COHERENCY_RX_FSM4)
24795 #define F_COHERENCY_RX_FSM4    V_COHERENCY_RX_FSM4(1U)
24798 #define V_ARB_REQ_FSM4(x) ((x) << S_ARB_REQ_FSM4)
24799 #define F_ARB_REQ_FSM4    V_ARB_REQ_FSM4(1U)
24803 #define V_CMD_SPLIT_FSM4(x) ((x) << S_CMD_SPLIT_FSM4)
24804 #define G_CMD_SPLIT_FSM4(x) (((x) >> S_CMD_SPLIT_FSM4) & M_CMD_SPLIT_FSM4)
24810 #define V_WR_DATA_EXT_FIFO_CNT5(x) ((x) << S_WR_DATA_EXT_FIFO_CNT5)
24811 #define G_WR_DATA_EXT_FIFO_CNT5(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT5) & M_WR_DATA_EXT_FIFO_CNT5)
24815 #define V_WR_CMD_TAG_FIFO_CNT5(x) ((x) << S_WR_CMD_TAG_FIFO_CNT5)
24816 #define G_WR_CMD_TAG_FIFO_CNT5(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT5) & M_WR_CMD_TAG_FIFO_CNT5)
24820 #define V_WR_DATA_512B_FIFO_CNT5(x) ((x) << S_WR_DATA_512B_FIFO_CNT5)
24821 #define G_WR_DATA_512B_FIFO_CNT5(x) (((x) >> S_WR_DATA_512B_FIFO_CNT5) & M_WR_DATA_512B_FIFO_CNT5)
24824 #define V_RD_DATA_ALIGN_FSM5(x) ((x) << S_RD_DATA_ALIGN_FSM5)
24825 #define F_RD_DATA_ALIGN_FSM5    V_RD_DATA_ALIGN_FSM5(1U)
24828 #define V_RD_DATA_FETCH_FSM5(x) ((x) << S_RD_DATA_FETCH_FSM5)
24829 #define F_RD_DATA_FETCH_FSM5    V_RD_DATA_FETCH_FSM5(1U)
24832 #define V_COHERENCY_TX_FSM5(x) ((x) << S_COHERENCY_TX_FSM5)
24833 #define F_COHERENCY_TX_FSM5    V_COHERENCY_TX_FSM5(1U)
24836 #define V_COHERENCY_RX_FSM5(x) ((x) << S_COHERENCY_RX_FSM5)
24837 #define F_COHERENCY_RX_FSM5    V_COHERENCY_RX_FSM5(1U)
24840 #define V_ARB_REQ_FSM5(x) ((x) << S_ARB_REQ_FSM5)
24841 #define F_ARB_REQ_FSM5    V_ARB_REQ_FSM5(1U)
24845 #define V_CMD_SPLIT_FSM5(x) ((x) << S_CMD_SPLIT_FSM5)
24846 #define G_CMD_SPLIT_FSM5(x) (((x) >> S_CMD_SPLIT_FSM5) & M_CMD_SPLIT_FSM5)
24852 #define V_WR_DATA_EXT_FIFO_CNT6(x) ((x) << S_WR_DATA_EXT_FIFO_CNT6)
24853 #define G_WR_DATA_EXT_FIFO_CNT6(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT6) & M_WR_DATA_EXT_FIFO_CNT6)
24857 #define V_WR_CMD_TAG_FIFO_CNT6(x) ((x) << S_WR_CMD_TAG_FIFO_CNT6)
24858 #define G_WR_CMD_TAG_FIFO_CNT6(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT6) & M_WR_CMD_TAG_FIFO_CNT6)
24862 #define V_WR_DATA_512B_FIFO_CNT6(x) ((x) << S_WR_DATA_512B_FIFO_CNT6)
24863 #define G_WR_DATA_512B_FIFO_CNT6(x) (((x) >> S_WR_DATA_512B_FIFO_CNT6) & M_WR_DATA_512B_FIFO_CNT6)
24866 #define V_RD_DATA_ALIGN_FSM6(x) ((x) << S_RD_DATA_ALIGN_FSM6)
24867 #define F_RD_DATA_ALIGN_FSM6    V_RD_DATA_ALIGN_FSM6(1U)
24870 #define V_RD_DATA_FETCH_FSM6(x) ((x) << S_RD_DATA_FETCH_FSM6)
24871 #define F_RD_DATA_FETCH_FSM6    V_RD_DATA_FETCH_FSM6(1U)
24874 #define V_COHERENCY_TX_FSM6(x) ((x) << S_COHERENCY_TX_FSM6)
24875 #define F_COHERENCY_TX_FSM6    V_COHERENCY_TX_FSM6(1U)
24878 #define V_COHERENCY_RX_FSM6(x) ((x) << S_COHERENCY_RX_FSM6)
24879 #define F_COHERENCY_RX_FSM6    V_COHERENCY_RX_FSM6(1U)
24882 #define V_ARB_REQ_FSM6(x) ((x) << S_ARB_REQ_FSM6)
24883 #define F_ARB_REQ_FSM6    V_ARB_REQ_FSM6(1U)
24887 #define V_CMD_SPLIT_FSM6(x) ((x) << S_CMD_SPLIT_FSM6)
24888 #define G_CMD_SPLIT_FSM6(x) (((x) >> S_CMD_SPLIT_FSM6) & M_CMD_SPLIT_FSM6)
24894 #define V_WR_DATA_EXT_FIFO_CNT7(x) ((x) << S_WR_DATA_EXT_FIFO_CNT7)
24895 #define G_WR_DATA_EXT_FIFO_CNT7(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT7) & M_WR_DATA_EXT_FIFO_CNT7)
24899 #define V_WR_CMD_TAG_FIFO_CNT7(x) ((x) << S_WR_CMD_TAG_FIFO_CNT7)
24900 #define G_WR_CMD_TAG_FIFO_CNT7(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT7) & M_WR_CMD_TAG_FIFO_CNT7)
24904 #define V_WR_DATA_512B_FIFO_CNT7(x) ((x) << S_WR_DATA_512B_FIFO_CNT7)
24905 #define G_WR_DATA_512B_FIFO_CNT7(x) (((x) >> S_WR_DATA_512B_FIFO_CNT7) & M_WR_DATA_512B_FIFO_CNT7)
24908 #define V_RD_DATA_ALIGN_FSM7(x) ((x) << S_RD_DATA_ALIGN_FSM7)
24909 #define F_RD_DATA_ALIGN_FSM7    V_RD_DATA_ALIGN_FSM7(1U)
24912 #define V_RD_DATA_FETCH_FSM7(x) ((x) << S_RD_DATA_FETCH_FSM7)
24913 #define F_RD_DATA_FETCH_FSM7    V_RD_DATA_FETCH_FSM7(1U)
24916 #define V_COHERENCY_TX_FSM7(x) ((x) << S_COHERENCY_TX_FSM7)
24917 #define F_COHERENCY_TX_FSM7    V_COHERENCY_TX_FSM7(1U)
24920 #define V_COHERENCY_RX_FSM7(x) ((x) << S_COHERENCY_RX_FSM7)
24921 #define F_COHERENCY_RX_FSM7    V_COHERENCY_RX_FSM7(1U)
24924 #define V_ARB_REQ_FSM7(x) ((x) << S_ARB_REQ_FSM7)
24925 #define F_ARB_REQ_FSM7    V_ARB_REQ_FSM7(1U)
24929 #define V_CMD_SPLIT_FSM7(x) ((x) << S_CMD_SPLIT_FSM7)
24930 #define G_CMD_SPLIT_FSM7(x) (((x) >> S_CMD_SPLIT_FSM7) & M_CMD_SPLIT_FSM7)
24936 #define V_WR_DATA_EXT_FIFO_CNT8(x) ((x) << S_WR_DATA_EXT_FIFO_CNT8)
24937 #define G_WR_DATA_EXT_FIFO_CNT8(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT8) & M_WR_DATA_EXT_FIFO_CNT8)
24941 #define V_WR_CMD_TAG_FIFO_CNT8(x) ((x) << S_WR_CMD_TAG_FIFO_CNT8)
24942 #define G_WR_CMD_TAG_FIFO_CNT8(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT8) & M_WR_CMD_TAG_FIFO_CNT8)
24946 #define V_WR_DATA_512B_FIFO_CNT8(x) ((x) << S_WR_DATA_512B_FIFO_CNT8)
24947 #define G_WR_DATA_512B_FIFO_CNT8(x) (((x) >> S_WR_DATA_512B_FIFO_CNT8) & M_WR_DATA_512B_FIFO_CNT8)
24950 #define V_RD_DATA_ALIGN_FSM8(x) ((x) << S_RD_DATA_ALIGN_FSM8)
24951 #define F_RD_DATA_ALIGN_FSM8    V_RD_DATA_ALIGN_FSM8(1U)
24954 #define V_RD_DATA_FETCH_FSM8(x) ((x) << S_RD_DATA_FETCH_FSM8)
24955 #define F_RD_DATA_FETCH_FSM8    V_RD_DATA_FETCH_FSM8(1U)
24958 #define V_COHERENCY_TX_FSM8(x) ((x) << S_COHERENCY_TX_FSM8)
24959 #define F_COHERENCY_TX_FSM8    V_COHERENCY_TX_FSM8(1U)
24962 #define V_COHERENCY_RX_FSM8(x) ((x) << S_COHERENCY_RX_FSM8)
24963 #define F_COHERENCY_RX_FSM8    V_COHERENCY_RX_FSM8(1U)
24966 #define V_ARB_REQ_FSM8(x) ((x) << S_ARB_REQ_FSM8)
24967 #define F_ARB_REQ_FSM8    V_ARB_REQ_FSM8(1U)
24971 #define V_CMD_SPLIT_FSM8(x) ((x) << S_CMD_SPLIT_FSM8)
24972 #define G_CMD_SPLIT_FSM8(x) (((x) >> S_CMD_SPLIT_FSM8) & M_CMD_SPLIT_FSM8)
24978 #define V_WR_DATA_EXT_FIFO_CNT9(x) ((x) << S_WR_DATA_EXT_FIFO_CNT9)
24979 #define G_WR_DATA_EXT_FIFO_CNT9(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT9) & M_WR_DATA_EXT_FIFO_CNT9)
24983 #define V_WR_CMD_TAG_FIFO_CNT9(x) ((x) << S_WR_CMD_TAG_FIFO_CNT9)
24984 #define G_WR_CMD_TAG_FIFO_CNT9(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT9) & M_WR_CMD_TAG_FIFO_CNT9)
24988 #define V_WR_DATA_512B_FIFO_CNT9(x) ((x) << S_WR_DATA_512B_FIFO_CNT9)
24989 #define G_WR_DATA_512B_FIFO_CNT9(x) (((x) >> S_WR_DATA_512B_FIFO_CNT9) & M_WR_DATA_512B_FIFO_CNT9)
24992 #define V_RD_DATA_ALIGN_FSM9(x) ((x) << S_RD_DATA_ALIGN_FSM9)
24993 #define F_RD_DATA_ALIGN_FSM9    V_RD_DATA_ALIGN_FSM9(1U)
24996 #define V_RD_DATA_FETCH_FSM9(x) ((x) << S_RD_DATA_FETCH_FSM9)
24997 #define F_RD_DATA_FETCH_FSM9    V_RD_DATA_FETCH_FSM9(1U)
25000 #define V_COHERENCY_TX_FSM9(x) ((x) << S_COHERENCY_TX_FSM9)
25001 #define F_COHERENCY_TX_FSM9    V_COHERENCY_TX_FSM9(1U)
25004 #define V_COHERENCY_RX_FSM9(x) ((x) << S_COHERENCY_RX_FSM9)
25005 #define F_COHERENCY_RX_FSM9    V_COHERENCY_RX_FSM9(1U)
25008 #define V_ARB_REQ_FSM9(x) ((x) << S_ARB_REQ_FSM9)
25009 #define F_ARB_REQ_FSM9    V_ARB_REQ_FSM9(1U)
25013 #define V_CMD_SPLIT_FSM9(x) ((x) << S_CMD_SPLIT_FSM9)
25014 #define G_CMD_SPLIT_FSM9(x) (((x) >> S_CMD_SPLIT_FSM9) & M_CMD_SPLIT_FSM9)
25020 #define V_WR_DATA_EXT_FIFO_CNT10(x) ((x) << S_WR_DATA_EXT_FIFO_CNT10)
25021 #define G_WR_DATA_EXT_FIFO_CNT10(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT10) & M_WR_DATA_EXT_FIFO_CNT10)
25025 #define V_WR_CMD_TAG_FIFO_CNT10(x) ((x) << S_WR_CMD_TAG_FIFO_CNT10)
25026 #define G_WR_CMD_TAG_FIFO_CNT10(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT10) & M_WR_CMD_TAG_FIFO_CNT10)
25030 #define V_WR_DATA_512B_FIFO_CNT10(x) ((x) << S_WR_DATA_512B_FIFO_CNT10)
25031 #define G_WR_DATA_512B_FIFO_CNT10(x) (((x) >> S_WR_DATA_512B_FIFO_CNT10) & M_WR_DATA_512B_FIFO_CNT10)
25034 #define V_RD_DATA_ALIGN_FSM10(x) ((x) << S_RD_DATA_ALIGN_FSM10)
25035 #define F_RD_DATA_ALIGN_FSM10    V_RD_DATA_ALIGN_FSM10(1U)
25038 #define V_RD_DATA_FETCH_FSM10(x) ((x) << S_RD_DATA_FETCH_FSM10)
25039 #define F_RD_DATA_FETCH_FSM10    V_RD_DATA_FETCH_FSM10(1U)
25042 #define V_COHERENCY_TX_FSM10(x) ((x) << S_COHERENCY_TX_FSM10)
25043 #define F_COHERENCY_TX_FSM10    V_COHERENCY_TX_FSM10(1U)
25046 #define V_COHERENCY_RX_FSM10(x) ((x) << S_COHERENCY_RX_FSM10)
25047 #define F_COHERENCY_RX_FSM10    V_COHERENCY_RX_FSM10(1U)
25050 #define V_ARB_REQ_FSM10(x) ((x) << S_ARB_REQ_FSM10)
25051 #define F_ARB_REQ_FSM10    V_ARB_REQ_FSM10(1U)
25055 #define V_CMD_SPLIT_FSM10(x) ((x) << S_CMD_SPLIT_FSM10)
25056 #define G_CMD_SPLIT_FSM10(x) (((x) >> S_CMD_SPLIT_FSM10) & M_CMD_SPLIT_FSM10)
25062 #define V_WR_DATA_EXT_FIFO_CNT11(x) ((x) << S_WR_DATA_EXT_FIFO_CNT11)
25063 #define G_WR_DATA_EXT_FIFO_CNT11(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT11) & M_WR_DATA_EXT_FIFO_CNT11)
25067 #define V_WR_CMD_TAG_FIFO_CNT11(x) ((x) << S_WR_CMD_TAG_FIFO_CNT11)
25068 #define G_WR_CMD_TAG_FIFO_CNT11(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT11) & M_WR_CMD_TAG_FIFO_CNT11)
25072 #define V_WR_DATA_512B_FIFO_CNT11(x) ((x) << S_WR_DATA_512B_FIFO_CNT11)
25073 #define G_WR_DATA_512B_FIFO_CNT11(x) (((x) >> S_WR_DATA_512B_FIFO_CNT11) & M_WR_DATA_512B_FIFO_CNT11)
25076 #define V_RD_DATA_ALIGN_FSM11(x) ((x) << S_RD_DATA_ALIGN_FSM11)
25077 #define F_RD_DATA_ALIGN_FSM11    V_RD_DATA_ALIGN_FSM11(1U)
25080 #define V_RD_DATA_FETCH_FSM11(x) ((x) << S_RD_DATA_FETCH_FSM11)
25081 #define F_RD_DATA_FETCH_FSM11    V_RD_DATA_FETCH_FSM11(1U)
25084 #define V_COHERENCY_TX_FSM11(x) ((x) << S_COHERENCY_TX_FSM11)
25085 #define F_COHERENCY_TX_FSM11    V_COHERENCY_TX_FSM11(1U)
25088 #define V_COHERENCY_RX_FSM11(x) ((x) << S_COHERENCY_RX_FSM11)
25089 #define F_COHERENCY_RX_FSM11    V_COHERENCY_RX_FSM11(1U)
25092 #define V_ARB_REQ_FSM11(x) ((x) << S_ARB_REQ_FSM11)
25093 #define F_ARB_REQ_FSM11    V_ARB_REQ_FSM11(1U)
25097 #define V_CMD_SPLIT_FSM11(x) ((x) << S_CMD_SPLIT_FSM11)
25098 #define G_CMD_SPLIT_FSM11(x) (((x) >> S_CMD_SPLIT_FSM11) & M_CMD_SPLIT_FSM11)
25104 #define V_WR_DATA_EXT_FIFO_CNT12(x) ((x) << S_WR_DATA_EXT_FIFO_CNT12)
25105 #define G_WR_DATA_EXT_FIFO_CNT12(x) (((x) >> S_WR_DATA_EXT_FIFO_CNT12) & M_WR_DATA_EXT_FIFO_CNT12)
25109 #define V_WR_CMD_TAG_FIFO_CNT12(x) ((x) << S_WR_CMD_TAG_FIFO_CNT12)
25110 #define G_WR_CMD_TAG_FIFO_CNT12(x) (((x) >> S_WR_CMD_TAG_FIFO_CNT12) & M_WR_CMD_TAG_FIFO_CNT12)
25114 #define V_WR_DATA_512B_FIFO_CNT12(x) ((x) << S_WR_DATA_512B_FIFO_CNT12)
25115 #define G_WR_DATA_512B_FIFO_CNT12(x) (((x) >> S_WR_DATA_512B_FIFO_CNT12) & M_WR_DATA_512B_FIFO_CNT12)
25118 #define V_RD_DATA_ALIGN_FSM12(x) ((x) << S_RD_DATA_ALIGN_FSM12)
25119 #define F_RD_DATA_ALIGN_FSM12    V_RD_DATA_ALIGN_FSM12(1U)
25122 #define V_RD_DATA_FETCH_FSM12(x) ((x) << S_RD_DATA_FETCH_FSM12)
25123 #define F_RD_DATA_FETCH_FSM12    V_RD_DATA_FETCH_FSM12(1U)
25126 #define V_COHERENCY_TX_FSM12(x) ((x) << S_COHERENCY_TX_FSM12)
25127 #define F_COHERENCY_TX_FSM12    V_COHERENCY_TX_FSM12(1U)
25130 #define V_COHERENCY_RX_FSM12(x) ((x) << S_COHERENCY_RX_FSM12)
25131 #define F_COHERENCY_RX_FSM12    V_COHERENCY_RX_FSM12(1U)
25134 #define V_ARB_REQ_FSM12(x) ((x) << S_ARB_REQ_FSM12)
25135 #define F_ARB_REQ_FSM12    V_ARB_REQ_FSM12(1U)
25139 #define V_CMD_SPLIT_FSM12(x) ((x) << S_CMD_SPLIT_FSM12)
25140 #define G_CMD_SPLIT_FSM12(x) (((x) >> S_CMD_SPLIT_FSM12) & M_CMD_SPLIT_FSM12)
25146 #define V_RD_CMD_TAG_FIFO_CNT0(x) ((x) << S_RD_CMD_TAG_FIFO_CNT0)
25147 #define G_RD_CMD_TAG_FIFO_CNT0(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT0) & M_RD_CMD_TAG_FIFO_CNT0)
25151 #define V_RD_DATA_FIFO_CNT0(x) ((x) << S_RD_DATA_FIFO_CNT0)
25152 #define G_RD_DATA_FIFO_CNT0(x) (((x) >> S_RD_DATA_FIFO_CNT0) & M_RD_DATA_FIFO_CNT0)
25158 #define V_RD_CMD_TAG_FIFO_CNT1(x) ((x) << S_RD_CMD_TAG_FIFO_CNT1)
25159 #define G_RD_CMD_TAG_FIFO_CNT1(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT1) & M_RD_CMD_TAG_FIFO_CNT1)
25163 #define V_RD_DATA_FIFO_CNT1(x) ((x) << S_RD_DATA_FIFO_CNT1)
25164 #define G_RD_DATA_FIFO_CNT1(x) (((x) >> S_RD_DATA_FIFO_CNT1) & M_RD_DATA_FIFO_CNT1)
25170 #define V_RD_CMD_TAG_FIFO_CNT2(x) ((x) << S_RD_CMD_TAG_FIFO_CNT2)
25171 #define G_RD_CMD_TAG_FIFO_CNT2(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT2) & M_RD_CMD_TAG_FIFO_CNT2)
25175 #define V_RD_DATA_FIFO_CNT2(x) ((x) << S_RD_DATA_FIFO_CNT2)
25176 #define G_RD_DATA_FIFO_CNT2(x) (((x) >> S_RD_DATA_FIFO_CNT2) & M_RD_DATA_FIFO_CNT2)
25182 #define V_RD_CMD_TAG_FIFO_CNT3(x) ((x) << S_RD_CMD_TAG_FIFO_CNT3)
25183 #define G_RD_CMD_TAG_FIFO_CNT3(x) (((x) >> S_RD_CMD_TAG_FIFO_CNT3) & M_RD_CMD_TAG_FIFO_CNT3)
25187 #define V_RD_DATA_FIFO_CNT3(x) ((x) << S_RD_DATA_FIFO_CNT3)
25188 #define G_RD_DATA_FIFO_CNT3(x) (((x) >> S_RD_DATA_FIFO_CNT3) & M_RD_DATA_FIFO_CNT3)
25248 #define V_PTMAXTRANS(x) ((x) << S_PTMAXTRANS)
25249 #define F_PTMAXTRANS    V_PTMAXTRANS(1U)
25253 #define V_PTFLITCNT(x) ((x) << S_PTFLITCNT)
25254 #define G_PTFLITCNT(x) (((x) >> S_PTFLITCNT) & M_PTFLITCNT)
25259 #define V_PRMAXTRANS(x) ((x) << S_PRMAXTRANS)
25260 #define F_PRMAXTRANS    V_PRMAXTRANS(1U)
25264 #define V_PRFLITCNT(x) ((x) << S_PRFLITCNT)
25265 #define G_PRFLITCNT(x) (((x) >> S_PRFLITCNT) & M_PRFLITCNT)
25273 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
25274 #define F_EDC_INST_NUM    V_EDC_INST_NUM(1U)
25277 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
25278 #define F_ENABLE_PERF    V_ENABLE_PERF(1U)
25281 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
25282 #define F_ECC_BYPASS    V_ECC_BYPASS(1U)
25286 #define V_REFFREQ(x) ((x) << S_REFFREQ)
25287 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
25302 #define V_ECC_UE(x) ((x) << S_ECC_UE)
25303 #define F_ECC_UE    V_ECC_UE(1U)
25305 #define S_ECC_CE    1
25306 #define V_ECC_CE(x) ((x) << S_ECC_CE)
25307 #define F_ECC_CE    V_ECC_CE(1U)
25313 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
25314 #define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)
25317 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
25318 #define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)
25321 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
25322 #define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)
25339 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
25340 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
25345 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
25346 #define F_MBVFREADY    V_MBVFREADY(1U)
25353 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
25354 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
25357 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
25358 #define F_MBMSGVALID    V_MBMSGVALID(1U)
25361 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
25362 #define F_MBINTREQ    V_MBINTREQ(1U)
25366 #define V_MBOWNER(x) ((x) << S_MBOWNER)
25367 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
25372 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
25373 #define F_MBWRBUSY    V_MBWRBUSY(1U)
25378 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
25379 #define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)
25384 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
25385 #define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)
25392 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
25393 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
25397 #define V_UPGEN(x) ((x) << S_UPGEN)
25398 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
25400 #define S_BOOTSDRAM    1
25401 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
25402 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
25405 #define V_UPCRST(x) ((x) << S_UPCRST)
25406 #define F_UPCRST    V_UPCRST(1U)
25412 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
25413 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
25419 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
25420 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
25425 #define V_T7_MA_CIM_INTFPERR(x) ((x) << S_T7_MA_CIM_INTFPERR)
25426 #define F_T7_MA_CIM_INTFPERR    V_T7_MA_CIM_INTFPERR(1U)
25429 #define V_T7_MBHOSTPARERR(x) ((x) << S_T7_MBHOSTPARERR)
25430 #define F_T7_MBHOSTPARERR    V_T7_MBHOSTPARERR(1U)
25433 #define V_MAARBINVRSPTAG(x) ((x) << S_MAARBINVRSPTAG)
25434 #define F_MAARBINVRSPTAG    V_MAARBINVRSPTAG(1U)
25437 #define V_MAARBFIFOPARERR(x) ((x) << S_MAARBFIFOPARERR)
25438 #define F_MAARBFIFOPARERR    V_MAARBFIFOPARERR(1U)
25441 #define V_SEMSRAMPARERR(x) ((x) << S_SEMSRAMPARERR)
25442 #define F_SEMSRAMPARERR    V_SEMSRAMPARERR(1U)
25445 #define V_RSACPARERR(x) ((x) << S_RSACPARERR)
25446 #define F_RSACPARERR    V_RSACPARERR(1U)
25449 #define V_RSADPARERR(x) ((x) << S_RSADPARERR)
25450 #define F_RSADPARERR    V_RSADPARERR(1U)
25453 #define V_T7_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_T7_PLCIM_MSTRSPDATAPARERR)
25454 #define F_T7_PLCIM_MSTRSPDATAPARERR    V_T7_PLCIM_MSTRSPDATAPARERR(1U)
25457 #define V_T7_PCIE2CIMINTFPARERR(x) ((x) << S_T7_PCIE2CIMINTFPARERR)
25458 #define F_T7_PCIE2CIMINTFPARERR    V_T7_PCIE2CIMINTFPARERR(1U)
25461 #define V_T7_NCSI2CIMINTFPARERR(x) ((x) << S_T7_NCSI2CIMINTFPARERR)
25462 #define F_T7_NCSI2CIMINTFPARERR    V_T7_NCSI2CIMINTFPARERR(1U)
25465 #define V_T7_SGE2CIMINTFPARERR(x) ((x) << S_T7_SGE2CIMINTFPARERR)
25466 #define F_T7_SGE2CIMINTFPARERR    V_T7_SGE2CIMINTFPARERR(1U)
25469 #define V_T7_ULP2CIMINTFPARERR(x) ((x) << S_T7_ULP2CIMINTFPARERR)
25470 #define F_T7_ULP2CIMINTFPARERR    V_T7_ULP2CIMINTFPARERR(1U)
25473 #define V_T7_TP2CIMINTFPARERR(x) ((x) << S_T7_TP2CIMINTFPARERR)
25474 #define F_T7_TP2CIMINTFPARERR    V_T7_TP2CIMINTFPARERR(1U)
25477 #define V_CORE7PARERR(x) ((x) << S_CORE7PARERR)
25478 #define F_CORE7PARERR    V_CORE7PARERR(1U)
25481 #define V_CORE6PARERR(x) ((x) << S_CORE6PARERR)
25482 #define F_CORE6PARERR    V_CORE6PARERR(1U)
25485 #define V_CORE5PARERR(x) ((x) << S_CORE5PARERR)
25486 #define F_CORE5PARERR    V_CORE5PARERR(1U)
25489 #define V_CORE4PARERR(x) ((x) << S_CORE4PARERR)
25490 #define F_CORE4PARERR    V_CORE4PARERR(1U)
25493 #define V_CORE3PARERR(x) ((x) << S_CORE3PARERR)
25494 #define F_CORE3PARERR    V_CORE3PARERR(1U)
25497 #define V_CORE2PARERR(x) ((x) << S_CORE2PARERR)
25498 #define F_CORE2PARERR    V_CORE2PARERR(1U)
25501 #define V_CORE1PARERR(x) ((x) << S_CORE1PARERR)
25502 #define F_CORE1PARERR    V_CORE1PARERR(1U)
25505 #define V_GFTPARERR(x) ((x) << S_GFTPARERR)
25506 #define F_GFTPARERR    V_GFTPARERR(1U)
25509 #define V_MPSRSPDATAPARERR(x) ((x) << S_MPSRSPDATAPARERR)
25510 #define F_MPSRSPDATAPARERR    V_MPSRSPDATAPARERR(1U)
25513 #define V_ER_RSPDATAPARERR(x) ((x) << S_ER_RSPDATAPARERR)
25514 #define F_ER_RSPDATAPARERR    V_ER_RSPDATAPARERR(1U)
25517 #define V_FLOWFIFOPARERR(x) ((x) << S_FLOWFIFOPARERR)
25518 #define F_FLOWFIFOPARERR    V_FLOWFIFOPARERR(1U)
25521 #define V_OBQSRAMPARERR(x) ((x) << S_OBQSRAMPARERR)
25522 #define F_OBQSRAMPARERR    V_OBQSRAMPARERR(1U)
25525 #define V_TIEQOUTPARERR(x) ((x) << S_TIEQOUTPARERR)
25526 #define F_TIEQOUTPARERR    V_TIEQOUTPARERR(1U)
25529 #define V_TIEQINPARERR(x) ((x) << S_TIEQINPARERR)
25530 #define F_TIEQINPARERR    V_TIEQINPARERR(1U)
25532 #define S_PIFRSPPARERR    1
25533 #define V_PIFRSPPARERR(x) ((x) << S_PIFRSPPARERR)
25534 #define F_PIFRSPPARERR    V_PIFRSPPARERR(1U)
25537 #define V_PIFREQPARERR(x) ((x) << S_PIFREQPARERR)
25538 #define F_PIFREQPARERR    V_PIFREQPARERR(1U)
25544 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
25545 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
25552 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
25553 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
25559 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
25560 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
25566 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
25567 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
25573 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
25574 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
25580 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
25581 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
25586 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
25587 #define F_TDEBUGINT    V_TDEBUGINT(1U)
25590 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
25591 #define F_BOOTVECSEL    V_BOOTVECSEL(1U)
25595 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
25596 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
25601 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
25602 #define F_TIEQOUTPARERRINTEN    V_TIEQOUTPARERRINTEN(1U)
25605 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
25606 #define F_TIEQINPARERRINTEN    V_TIEQINPARERRINTEN(1U)
25609 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
25610 #define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)
25613 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
25614 #define F_MBUPPARERR    V_MBUPPARERR(1U)
25617 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
25618 #define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)
25621 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
25622 #define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)
25625 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
25626 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
25629 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
25630 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
25633 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
25634 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
25637 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
25638 #define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)
25641 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
25642 #define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)
25645 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
25646 #define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)
25649 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
25650 #define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)
25653 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
25654 #define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)
25657 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
25658 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
25661 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
25662 #define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)
25665 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
25666 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
25669 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
25670 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
25672 #define S_PREFDROPINTEN    1
25673 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
25674 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
25677 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
25678 #define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)
25681 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
25682 #define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)
25685 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
25686 #define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)
25689 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
25690 #define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)
25693 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
25694 #define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)
25697 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
25698 #define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)
25701 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
25702 #define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)
25705 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
25706 #define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
25709 #define V_PCIE2CIMINTFPARERR(x) ((x) << S_PCIE2CIMINTFPARERR)
25710 #define F_PCIE2CIMINTFPARERR    V_PCIE2CIMINTFPARERR(1U)
25713 #define V_IBQPCIEPARERR(x) ((x) << S_IBQPCIEPARERR)
25714 #define F_IBQPCIEPARERR    V_IBQPCIEPARERR(1U)
25717 #define V_CORE7ACCINT(x) ((x) << S_CORE7ACCINT)
25718 #define F_CORE7ACCINT    V_CORE7ACCINT(1U)
25721 #define V_CORE6ACCINT(x) ((x) << S_CORE6ACCINT)
25722 #define F_CORE6ACCINT    V_CORE6ACCINT(1U)
25725 #define V_CORE5ACCINT(x) ((x) << S_CORE5ACCINT)
25726 #define F_CORE5ACCINT    V_CORE5ACCINT(1U)
25729 #define V_CORE4ACCINT(x) ((x) << S_CORE4ACCINT)
25730 #define F_CORE4ACCINT    V_CORE4ACCINT(1U)
25733 #define V_CORE3ACCINT(x) ((x) << S_CORE3ACCINT)
25734 #define F_CORE3ACCINT    V_CORE3ACCINT(1U)
25737 #define V_CORE2ACCINT(x) ((x) << S_CORE2ACCINT)
25738 #define F_CORE2ACCINT    V_CORE2ACCINT(1U)
25741 #define V_CORE1ACCINT(x) ((x) << S_CORE1ACCINT)
25742 #define F_CORE1ACCINT    V_CORE1ACCINT(1U)
25744 #define S_PERRNONZERO    1
25745 #define V_PERRNONZERO(x) ((x) << S_PERRNONZERO)
25746 #define F_PERRNONZERO    V_PERRNONZERO(1U)
25751 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
25752 #define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)
25755 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
25756 #define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)
25759 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
25760 #define F_TIMER1INT    V_TIMER1INT(1U)
25763 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
25764 #define F_TIMER0INT    V_TIMER0INT(1U)
25766 #define S_PREFDROPINT    1
25767 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
25768 #define F_PREFDROPINT    V_PREFDROPINT(1U)
25771 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
25772 #define F_UPACCNONZERO    V_UPACCNONZERO(1U)
25777 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
25778 #define F_EEPROMWRINTEN    V_EEPROMWRINTEN(1U)
25781 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
25782 #define F_TIMEOUTMAINTEN    V_TIMEOUTMAINTEN(1U)
25785 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
25786 #define F_TIMEOUTINTEN    V_TIMEOUTINTEN(1U)
25789 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
25790 #define F_RSPOVRLOOKUPINTEN    V_RSPOVRLOOKUPINTEN(1U)
25793 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
25794 #define F_REQOVRLOOKUPINTEN    V_REQOVRLOOKUPINTEN(1U)
25797 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
25798 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
25801 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
25802 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
25805 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
25806 #define F_SGLWRPLINTEN    V_SGLWRPLINTEN(1U)
25809 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
25810 #define F_SGLRDPLINTEN    V_SGLRDPLINTEN(1U)
25813 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
25814 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
25817 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
25818 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
25821 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
25822 #define F_SGLWRCTLINTEN    V_SGLWRCTLINTEN(1U)
25825 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
25826 #define F_SGLRDCTLINTEN    V_SGLRDCTLINTEN(1U)
25829 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
25830 #define F_BLKWREEPROMINTEN    V_BLKWREEPROMINTEN(1U)
25833 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
25834 #define F_BLKRDEEPROMINTEN    V_BLKRDEEPROMINTEN(1U)
25837 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
25838 #define F_SGLWREEPROMINTEN    V_SGLWREEPROMINTEN(1U)
25841 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
25842 #define F_SGLRDEEPROMINTEN    V_SGLRDEEPROMINTEN(1U)
25845 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
25846 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
25849 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
25850 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
25853 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
25854 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
25857 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
25858 #define F_SGLRDFLASHINTEN    V_SGLRDFLASHINTEN(1U)
25861 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
25862 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
25865 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
25866 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
25869 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
25870 #define F_SGLWRBOOTINTEN    V_SGLWRBOOTINTEN(1U)
25873 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
25874 #define F_SGLRDBOOTINTEN    V_SGLRDBOOTINTEN(1U)
25877 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
25878 #define F_ILLWRBEINTEN    V_ILLWRBEINTEN(1U)
25881 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
25882 #define F_ILLRDBEINTEN    V_ILLRDBEINTEN(1U)
25885 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
25886 #define F_ILLRDINTEN    V_ILLRDINTEN(1U)
25889 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
25890 #define F_ILLWRINTEN    V_ILLWRINTEN(1U)
25892 #define S_ILLTRANSINTEN    1
25893 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
25894 #define F_ILLTRANSINTEN    V_ILLTRANSINTEN(1U)
25897 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
25898 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
25901 #define V_CONWRERRINTEN(x) ((x) << S_CONWRERRINTEN)
25902 #define F_CONWRERRINTEN    V_CONWRERRINTEN(1U)
25907 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
25908 #define F_EEPROMWRINT    V_EEPROMWRINT(1U)
25911 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
25912 #define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)
25915 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
25916 #define F_TIMEOUTINT    V_TIMEOUTINT(1U)
25919 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
25920 #define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)
25923 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
25924 #define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)
25927 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
25928 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
25931 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
25932 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
25935 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
25936 #define F_SGLWRPLINT    V_SGLWRPLINT(1U)
25939 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
25940 #define F_SGLRDPLINT    V_SGLRDPLINT(1U)
25943 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
25944 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
25947 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
25948 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
25951 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
25952 #define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)
25955 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
25956 #define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)
25959 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
25960 #define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)
25963 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
25964 #define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)
25967 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
25968 #define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)
25971 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
25972 #define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)
25975 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
25976 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
25979 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
25980 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
25983 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
25984 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
25987 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
25988 #define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)
25991 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
25992 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
25995 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
25996 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
25999 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
26000 #define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)
26003 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
26004 #define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)
26007 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
26008 #define F_ILLWRBEINT    V_ILLWRBEINT(1U)
26011 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
26012 #define F_ILLRDBEINT    V_ILLRDBEINT(1U)
26015 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
26016 #define F_ILLRDINT    V_ILLRDINT(1U)
26019 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
26020 #define F_ILLWRINT    V_ILLWRINT(1U)
26022 #define S_ILLTRANSINT    1
26023 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
26024 #define F_ILLTRANSINT    V_ILLTRANSINT(1U)
26027 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
26028 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
26031 #define V_CONWRERRINT(x) ((x) << S_CONWRERRINT)
26032 #define F_CONWRERRINT    V_CONWRERRINT(1U)
26037 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
26038 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
26041 #define V_SEMINT(x) ((x) << S_SEMINT)
26042 #define F_SEMINT    V_SEMINT(1U)
26045 #define V_RSAINT(x) ((x) << S_RSAINT)
26046 #define F_RSAINT    V_RSAINT(1U)
26049 #define V_TRNGINT(x) ((x) << S_TRNGINT)
26050 #define F_TRNGINT    V_TRNGINT(1U)
26053 #define V_PEERHALTINT(x) ((x) << S_PEERHALTINT)
26054 #define F_PEERHALTINT    V_PEERHALTINT(1U)
26059 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
26060 #define F_MSTPLINT    V_MSTPLINT(1U)
26067 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
26068 #define F_OBQSELECT    V_OBQSELECT(1U)
26071 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
26072 #define F_IBQSELECT    V_IBQSELECT(1U)
26076 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
26077 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
26081 #define V_MAPOFFSET(x) ((x) << S_MAPOFFSET)
26082 #define G_MAPOFFSET(x) (((x) >> S_MAPOFFSET) & M_MAPOFFSET)
26085 #define V_MAPSELECT(x) ((x) << S_MAPSELECT)
26086 #define F_MAPSELECT    V_MAPSELECT(1U)
26090 #define V_CORESELECT(x) ((x) << S_CORESELECT)
26091 #define G_CORESELECT(x) (((x) >> S_CORESELECT) & M_CORESELECT)
26094 #define V_T7_OBQSELECT(x) ((x) << S_T7_OBQSELECT)
26095 #define F_T7_OBQSELECT    V_T7_OBQSELECT(1U)
26098 #define V_T7_IBQSELECT(x) ((x) << S_T7_IBQSELECT)
26099 #define F_T7_IBQSELECT    V_T7_IBQSELECT(1U)
26103 #define V_T7_QUENUMSELECT(x) ((x) << S_T7_QUENUMSELECT)
26104 #define G_T7_QUENUMSELECT(x) (((x) >> S_T7_QUENUMSELECT) & M_T7_QUENUMSELECT)
26110 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
26111 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
26115 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
26116 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
26119 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
26120 #define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)
26124 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
26125 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
26128 #define V_CIMQ1KEN(x) ((x) << S_CIMQ1KEN)
26129 #define F_CIMQ1KEN    V_CIMQ1KEN(1U)
26134 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
26135 #define F_HOSTBUSY    V_HOSTBUSY(1U)
26138 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
26139 #define F_HOSTWRITE    V_HOSTWRITE(1U)
26143 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
26144 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
26147 #define V_T7_HOSTBUSY(x) ((x) << S_T7_HOSTBUSY)
26148 #define F_T7_HOSTBUSY    V_T7_HOSTBUSY(1U)
26151 #define V_T7_HOSTWRITE(x) ((x) << S_T7_HOSTWRITE)
26152 #define F_T7_HOSTWRITE    V_T7_HOSTWRITE(1U)
26156 #define V_HOSTGRPSEL(x) ((x) << S_HOSTGRPSEL)
26157 #define G_HOSTGRPSEL(x) (((x) >> S_HOSTGRPSEL) & M_HOSTGRPSEL)
26161 #define V_HOSTCORESEL(x) ((x) << S_HOSTCORESEL)
26162 #define G_HOSTCORESEL(x) (((x) >> S_HOSTCORESEL) & M_HOSTCORESEL)
26166 #define V_T7_HOSTADDR(x) ((x) << S_T7_HOSTADDR)
26167 #define G_T7_HOSTADDR(x) (((x) >> S_T7_HOSTADDR) & M_T7_HOSTADDR)
26174 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
26175 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
26179 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
26180 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
26185 #define V_OR_EN(x) ((x) << S_OR_EN)
26186 #define F_OR_EN    V_OR_EN(1U)
26189 #define V_USEL(x) ((x) << S_USEL)
26190 #define F_USEL    V_USEL(1U)
26193 #define V_HI(x) ((x) << S_HI)
26194 #define F_HI    V_HI(1U)
26198 #define V_SELH(x) ((x) << S_SELH)
26199 #define G_SELH(x) (((x) >> S_SELH) & M_SELH)
26203 #define V_SELL(x) ((x) << S_SELL)
26204 #define G_SELL(x) (((x) >> S_SELL) & M_SELL)
26211 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
26212 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
26215 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
26216 #define F_IBQDBGWR    V_IBQDBGWR(1U)
26218 #define S_IBQDBGBUSY    1
26219 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
26220 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
26223 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
26224 #define F_IBQDBGEN    V_IBQDBGEN(1U)
26228 #define V_IBQDBGCORE(x) ((x) << S_IBQDBGCORE)
26229 #define G_IBQDBGCORE(x) (((x) >> S_IBQDBGCORE) & M_IBQDBGCORE)
26233 #define V_T7_IBQDBGADDR(x) ((x) << S_T7_IBQDBGADDR)
26234 #define G_T7_IBQDBGADDR(x) (((x) >> S_T7_IBQDBGADDR) & M_T7_IBQDBGADDR)
26238 #define V_IBQDBGSTATE(x) ((x) << S_IBQDBGSTATE)
26239 #define G_IBQDBGSTATE(x) (((x) >> S_IBQDBGSTATE) & M_IBQDBGSTATE)
26242 #define V_PERRADDRCLR(x) ((x) << S_PERRADDRCLR)
26243 #define F_PERRADDRCLR    V_PERRADDRCLR(1U)
26249 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
26250 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
26253 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
26254 #define F_OBQDBGWR    V_OBQDBGWR(1U)
26256 #define S_OBQDBGBUSY    1
26257 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
26258 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
26261 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
26262 #define F_OBQDBGEN    V_OBQDBGEN(1U)
26266 #define V_OBQDBGCORE(x) ((x) << S_OBQDBGCORE)
26267 #define G_OBQDBGCORE(x) (((x) >> S_OBQDBGCORE) & M_OBQDBGCORE)
26271 #define V_T7_OBQDBGADDR(x) ((x) << S_T7_OBQDBGADDR)
26272 #define G_T7_OBQDBGADDR(x) (((x) >> S_T7_OBQDBGADDR) & M_T7_OBQDBGADDR)
26276 #define V_OBQDBGSTATE(x) ((x) << S_OBQDBGSTATE)
26277 #define G_OBQDBGSTATE(x) (((x) >> S_OBQDBGSTATE) & M_OBQDBGSTATE)
26285 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
26286 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
26290 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
26291 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
26294 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
26295 #define F_LAMASKTRIG    V_LAMASKTRIG(1U)
26298 #define V_LADBGEN(x) ((x) << S_LADBGEN)
26299 #define F_LADBGEN    V_LADBGEN(1U)
26302 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
26303 #define F_LAFILLONCE    V_LAFILLONCE(1U)
26306 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
26307 #define F_LAMASKSTOP    V_LAMASKSTOP(1U)
26311 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
26312 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
26316 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
26317 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
26322 #define V_LARESET(x) ((x) << S_LARESET)
26323 #define F_LARESET    V_LARESET(1U)
26327 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
26328 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
26332 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
26333 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
26344 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
26345 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
26351 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
26352 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
26355 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
26356 #define F_PBT_ENABLE    V_PBT_ENABLE(1U)
26360 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
26361 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
26365 #define V_THREAD_ID(x) ((x) << S_THREAD_ID)
26366 #define G_THREAD_ID(x) (((x) >> S_THREAD_ID) & M_THREAD_ID)
26372 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
26373 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
26400 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
26401 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
26406 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
26407 #define F_TIMER1EN    V_TIMER1EN(1U)
26410 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
26411 #define F_TIMER0EN    V_TIMER0EN(1U)
26413 #define S_TIMEREN    1
26414 #define V_TIMEREN(x) ((x) << S_TIMEREN)
26415 #define F_TIMEREN    V_TIMEREN(1U)
26422 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
26423 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
26431 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
26432 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
26436 #define V_DADDRTIMEOUTTYPE(x) ((x) << S_DADDRTIMEOUTTYPE)
26437 #define G_DADDRTIMEOUTTYPE(x) (((x) >> S_DADDRTIMEOUTTYPE) & M_DADDRTIMEOUTTYPE)
26443 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
26444 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
26448 #define V_DADDRILLEGALTYPE(x) ((x) << S_DADDRILLEGALTYPE)
26449 #define G_DADDRILLEGALTYPE(x) (((x) >> S_DADDRILLEGALTYPE) & M_DADDRILLEGALTYPE)
26455 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
26456 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
26460 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
26461 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
26465 #define V_T6_T5_DPIFHOSTMASK(x) ((x) << S_T6_T5_DPIFHOSTMASK)
26466 #define G_T6_T5_DPIFHOSTMASK(x) (((x) >> S_T6_T5_DPIFHOSTMASK) & M_T6_T5_DPIFHOSTMASK)
26472 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
26473 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
26479 #define V_DUPMASK(x) ((x) << S_DUPMASK)
26480 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
26484 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
26485 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
26489 #define V_T6_T5_DUPMASK(x) ((x) << S_T6_T5_DUPMASK)
26490 #define G_T6_T5_DUPMASK(x) (((x) >> S_T6_T5_DUPMASK) & M_T6_T5_DUPMASK)
26496 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
26497 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
26505 #define V_PERREN(x) ((x) << S_PERREN)
26506 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
26510 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
26511 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
26515 #define V_T6_T5_PERREN(x) ((x) << S_T6_T5_PERREN)
26516 #define G_T6_T5_PERREN(x) (((x) >> S_T6_T5_PERREN) & M_T6_T5_PERREN)
26522 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
26523 #define F_EEPROMBUSY    V_EEPROMBUSY(1U)
26528 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
26529 #define F_MA_TIMER_ENABLE    V_MA_TIMER_ENABLE(1U)
26531 #define S_SLOW_TIMER_ENABLE    1
26532 #define V_SLOW_TIMER_ENABLE(x) ((x) << S_SLOW_TIMER_ENABLE)
26533 #define F_SLOW_TIMER_ENABLE    V_SLOW_TIMER_ENABLE(1U)
26536 #define V_FLASHWRPAGEMORE(x) ((x) << S_FLASHWRPAGEMORE)
26537 #define F_FLASHWRPAGEMORE    V_FLASHWRPAGEMORE(1U)
26540 #define V_FLASHWRENABLE(x) ((x) << S_FLASHWRENABLE)
26541 #define F_FLASHWRENABLE    V_FLASHWRENABLE(1U)
26544 #define V_FLASHMOREENABLE(x) ((x) << S_FLASHMOREENABLE)
26545 #define F_FLASHMOREENABLE    V_FLASHMOREENABLE(1U)
26548 #define V_WR_RESP_ENABLE(x) ((x) << S_WR_RESP_ENABLE)
26549 #define F_WR_RESP_ENABLE    V_WR_RESP_ENABLE(1U)
26554 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
26555 #define F_UP_PO_SINGLE_OUTSTANDING    V_UP_PO_SINGLE_OUTSTANDING(1U)
26563 #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
26564 #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
26568 #define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
26569 #define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
26573 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
26574 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
26578 #define V_CIM_PCIE_PKT_ERR_CODE(x) ((x) << S_CIM_PCIE_PKT_ERR_CODE)
26579 #define G_CIM_PCIE_PKT_ERR_CODE(x) (((x) >> S_CIM_PCIE_PKT_ERR_CODE) & M_CIM_PCIE_PKT_ERR_CODE)
26586 #define V_IBQPERRADDR(x) ((x) << S_IBQPERRADDR)
26587 #define G_IBQPERRADDR(x) (((x) >> S_IBQPERRADDR) & M_IBQPERRADDR)
26591 #define V_OBQPERRADDR(x) ((x) << S_OBQPERRADDR)
26592 #define G_OBQPERRADDR(x) (((x) >> S_OBQPERRADDR) & M_OBQPERRADDR)
26597 #define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
26598 #define F_PIO_UP_MST_CFG_SEL    V_PIO_UP_MST_CFG_SEL(1U)
26603 #define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
26604 #define F_TSCH_CGEN    V_TSCH_CGEN(1U)
26609 #define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
26610 #define F_OBQ_THROUTTLE_ON_EOP    V_OBQ_THROUTTLE_ON_EOP(1U)
26613 #define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
26614 #define F_OBQ_READ_CTL_PERF_MODE_DISABLE    V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
26617 #define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
26618 #define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
26620 #define S_IBQ_RRA_DSBL    1
26621 #define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
26622 #define F_IBQ_RRA_DSBL    V_IBQ_RRA_DSBL(1U)
26625 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
26626 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL    V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
26629 #define V_PCIE_OBQ_IF_DISABLE(x) ((x) << S_PCIE_OBQ_IF_DISABLE)
26630 #define F_PCIE_OBQ_IF_DISABLE    V_PCIE_OBQ_IF_DISABLE(1U)
26634 #define V_ULP_OBQ_SIZE(x) ((x) << S_ULP_OBQ_SIZE)
26635 #define G_ULP_OBQ_SIZE(x) (((x) >> S_ULP_OBQ_SIZE) & M_ULP_OBQ_SIZE)
26639 #define V_TP_IBQ_SIZE(x) ((x) << S_TP_IBQ_SIZE)
26640 #define G_TP_IBQ_SIZE(x) (((x) >> S_TP_IBQ_SIZE) & M_TP_IBQ_SIZE)
26643 #define V_OBQ_EOM_ENABLE(x) ((x) << S_OBQ_EOM_ENABLE)
26644 #define F_OBQ_EOM_ENABLE    V_OBQ_EOM_ENABLE(1U)
26649 #define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
26650 #define F_CGEN_GLOBAL    V_CGEN_GLOBAL(1U)
26655 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
26656 #define F_PIFDBGLA_DPSLP_EN    V_PIFDBGLA_DPSLP_EN(1U)
26661 #define V_GLFL(x) ((x) << S_GLFL)
26662 #define F_GLFL    V_GLFL(1U)
26666 #define V_T7_WRCNTIDLE(x) ((x) << S_T7_WRCNTIDLE)
26667 #define G_T7_WRCNTIDLE(x) (((x) >> S_T7_WRCNTIDLE) & M_T7_WRCNTIDLE)
26673 #define V_GFTMABASE(x) ((x) << S_GFTMABASE)
26674 #define G_GFTMABASE(x) (((x) >> S_GFTMABASE) & M_GFTMABASE)
26678 #define V_GFTHASHTBLSIZE(x) ((x) << S_GFTHASHTBLSIZE)
26679 #define G_GFTHASHTBLSIZE(x) (((x) >> S_GFTHASHTBLSIZE) & M_GFTHASHTBLSIZE)
26682 #define V_GFTTCAMPRIORITY(x) ((x) << S_GFTTCAMPRIORITY)
26683 #define F_GFTTCAMPRIORITY    V_GFTTCAMPRIORITY(1U)
26687 #define V_GFTMATHREADID(x) ((x) << S_GFTMATHREADID)
26688 #define G_GFTMATHREADID(x) (((x) >> S_GFTMATHREADID) & M_GFTMATHREADID)
26691 #define V_GFTTCAMINIT(x) ((x) << S_GFTTCAMINIT)
26692 #define F_GFTTCAMINIT    V_GFTTCAMINIT(1U)
26695 #define V_GFTTCAMINITDONE(x) ((x) << S_GFTTCAMINITDONE)
26696 #define F_GFTTCAMINITDONE    V_GFTTCAMINITDONE(1U)
26699 #define V_GFTTBLMODEEN(x) ((x) << S_GFTTBLMODEEN)
26700 #define F_GFTTBLMODEEN    V_GFTTBLMODEEN(1U)
26705 #define V_RST_CB(x) ((x) << S_RST_CB)
26706 #define F_RST_CB    V_RST_CB(1U)
26710 #define V_CB_START(x) ((x) << S_CB_START)
26711 #define G_CB_START(x) (((x) >> S_CB_START) & M_CB_START)
26717 #define V_CB_PASS(x) ((x) << S_CB_PASS)
26718 #define G_CB_PASS(x) (((x) >> S_CB_PASS) & M_CB_PASS)
26724 #define V_CB_BUSY(x) ((x) << S_CB_BUSY)
26725 #define G_CB_BUSY(x) (((x) >> S_CB_BUSY) & M_CB_BUSY)
26735 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
26736 #define F_TCPOPTPARSERDISCH3    V_TCPOPTPARSERDISCH3(1U)
26739 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
26740 #define F_TCPOPTPARSERDISCH2    V_TCPOPTPARSERDISCH2(1U)
26743 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
26744 #define F_TCPOPTPARSERDISCH1    V_TCPOPTPARSERDISCH1(1U)
26747 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
26748 #define F_TCPOPTPARSERDISCH0    V_TCPOPTPARSERDISCH0(1U)
26751 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
26752 #define F_CRCPASSPRT3    V_CRCPASSPRT3(1U)
26755 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
26756 #define F_CRCPASSPRT2    V_CRCPASSPRT2(1U)
26759 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
26760 #define F_CRCPASSPRT1    V_CRCPASSPRT1(1U)
26763 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
26764 #define F_CRCPASSPRT0    V_CRCPASSPRT0(1U)
26767 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
26768 #define F_VEPAMODE    V_VEPAMODE(1U)
26771 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
26772 #define F_FIPUPEN    V_FIPUPEN(1U)
26775 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
26776 #define F_FCOEUPEN    V_FCOEUPEN(1U)
26779 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
26780 #define F_FCOEENABLE    V_FCOEENABLE(1U)
26783 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
26784 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
26787 #define V_NICMODE(x) ((x) << S_NICMODE)
26788 #define F_NICMODE    V_NICMODE(1U)
26791 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
26792 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
26795 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
26796 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
26799 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
26800 #define F_EREPORTUDPHDRLEN    V_EREPORTUDPHDRLEN(1U)
26803 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
26804 #define F_IN_ECPL    V_IN_ECPL(1U)
26807 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
26808 #define F_VNTAGENABLE    V_VNTAGENABLE(1U)
26811 #define V_IN_EETH(x) ((x) << S_IN_EETH)
26812 #define F_IN_EETH    V_IN_EETH(1U)
26815 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
26816 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
26819 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
26820 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
26823 #define V_CTAG(x) ((x) << S_CTAG)
26824 #define F_CTAG    V_CTAG(1U)
26827 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
26828 #define F_IN_CCPL    V_IN_CCPL(1U)
26830 #define S_IN_CETH    1
26831 #define V_IN_CETH(x) ((x) << S_IN_CETH)
26832 #define F_IN_CETH    V_IN_CETH(1U)
26835 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
26836 #define F_CTUNNEL    V_CTUNNEL(1U)
26839 #define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
26840 #define F_VLANEXTENPORT3    V_VLANEXTENPORT3(1U)
26843 #define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
26844 #define F_VLANEXTENPORT2    V_VLANEXTENPORT2(1U)
26847 #define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
26848 #define F_VLANEXTENPORT1    V_VLANEXTENPORT1(1U)
26851 #define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
26852 #define F_VLANEXTENPORT0    V_VLANEXTENPORT0(1U)
26855 #define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
26856 #define F_VNTAGDEFAULTVAL    V_VNTAGDEFAULTVAL(1U)
26859 #define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
26860 #define F_ECHECKUDPLEN    V_ECHECKUDPLEN(1U)
26863 #define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
26864 #define F_FCOEFPMA    V_FCOEFPMA(1U)
26867 #define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
26868 #define F_VNTAGETHENABLE    V_VNTAGETHENABLE(1U)
26871 #define V_IP_CCSM(x) ((x) << S_IP_CCSM)
26872 #define F_IP_CCSM    V_IP_CCSM(1U)
26875 #define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
26876 #define F_CCHECKSUMCHECKUDP    V_CCHECKSUMCHECKUDP(1U)
26879 #define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
26880 #define F_TCP_CCSM    V_TCP_CCSM(1U)
26883 #define V_CDEMUX(x) ((x) << S_CDEMUX)
26884 #define F_CDEMUX    V_CDEMUX(1U)
26887 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
26888 #define F_ETHUPEN    V_ETHUPEN(1U)
26891 #define V_CXOFFOVERRIDE(x) ((x) << S_CXOFFOVERRIDE)
26892 #define F_CXOFFOVERRIDE    V_CXOFFOVERRIDE(1U)
26894 #define S_EGREDROPEN    1
26895 #define V_EGREDROPEN(x) ((x) << S_EGREDROPEN)
26896 #define F_EGREDROPEN    V_EGREDROPEN(1U)
26899 #define V_CFASTDEMUXEN(x) ((x) << S_CFASTDEMUXEN)
26900 #define F_CFASTDEMUXEN    V_CFASTDEMUXEN(1U)
26906 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
26907 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
26910 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
26911 #define F_EPKTDISTCHN3    V_EPKTDISTCHN3(1U)
26914 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
26915 #define F_EPKTDISTCHN2    V_EPKTDISTCHN2(1U)
26918 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
26919 #define F_EPKTDISTCHN1    V_EPKTDISTCHN1(1U)
26922 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
26923 #define F_EPKTDISTCHN0    V_EPKTDISTCHN0(1U)
26926 #define V_TTLMODE(x) ((x) << S_TTLMODE)
26927 #define F_TTLMODE    V_TTLMODE(1U)
26930 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
26931 #define F_EQFCDMAC    V_EQFCDMAC(1U)
26934 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
26935 #define F_ELPBKINCMPSSTAT    V_ELPBKINCMPSSTAT(1U)
26938 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
26939 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
26942 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
26943 #define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)
26946 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
26947 #define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)
26950 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
26951 #define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)
26954 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
26955 #define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)
26958 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
26959 #define F_ECHECKSUMINSERTTCP    V_ECHECKSUMINSERTTCP(1U)
26962 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
26963 #define F_ECHECKSUMINSERTIP    V_ECHECKSUMINSERTIP(1U)
26966 #define V_ECPL(x) ((x) << S_ECPL)
26967 #define F_ECPL    V_ECPL(1U)
26970 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
26971 #define F_EPRIORITY    V_EPRIORITY(1U)
26974 #define V_EETHERNET(x) ((x) << S_EETHERNET)
26975 #define F_EETHERNET    V_EETHERNET(1U)
26978 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
26979 #define F_CCHECKSUMINSERTTCP    V_CCHECKSUMINSERTTCP(1U)
26982 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
26983 #define F_CCHECKSUMINSERTIP    V_CCHECKSUMINSERTIP(1U)
26986 #define V_CCPL(x) ((x) << S_CCPL)
26987 #define F_CCPL    V_CCPL(1U)
26990 #define V_CETHERNET(x) ((x) << S_CETHERNET)
26991 #define F_CETHERNET    V_CETHERNET(1U)
26994 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
26995 #define F_EVNTAGEN    V_EVNTAGEN(1U)
26998 #define V_CCPLACKMODE(x) ((x) << S_CCPLACKMODE)
26999 #define F_CCPLACKMODE    V_CCPLACKMODE(1U)
27002 #define V_RMWHINTENABLE(x) ((x) << S_RMWHINTENABLE)
27003 #define F_RMWHINTENABLE    V_RMWHINTENABLE(1U)
27006 #define V_EV6FLWEN(x) ((x) << S_EV6FLWEN)
27007 #define F_EV6FLWEN    V_EV6FLWEN(1U)
27010 #define V_EVLANPRIO(x) ((x) << S_EVLANPRIO)
27011 #define F_EVLANPRIO    V_EVLANPRIO(1U)
27014 #define V_CRXPKTENC(x) ((x) << S_CRXPKTENC)
27015 #define F_CRXPKTENC    V_CRXPKTENC(1U)
27017 #define S_CRXPKTXT    1
27018 #define V_CRXPKTXT(x) ((x) << S_CRXPKTXT)
27019 #define F_CRXPKTXT    V_CRXPKTXT(1U)
27022 #define V_ETOEBYPCSUMNOWAIT(x) ((x) << S_ETOEBYPCSUMNOWAIT)
27023 #define F_ETOEBYPCSUMNOWAIT    V_ETOEBYPCSUMNOWAIT(1U)
27026 #define V_ENICCSUMNOWAIT(x) ((x) << S_ENICCSUMNOWAIT)
27027 #define F_ENICCSUMNOWAIT    V_ENICCSUMNOWAIT(1U)
27033 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
27034 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
27037 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
27038 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
27041 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
27042 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
27045 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
27046 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
27049 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
27050 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
27053 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
27054 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
27057 #define V_PINGDROP(x) ((x) << S_PINGDROP)
27058 #define F_PINGDROP    V_PINGDROP(1U)
27061 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
27062 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
27066 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
27067 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
27070 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
27071 #define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)
27074 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
27075 #define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)
27078 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
27079 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
27082 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
27083 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
27086 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
27087 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
27090 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
27091 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
27094 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
27095 #define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)
27099 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
27100 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
27104 #define V_IPTTL(x) ((x) << S_IPTTL)
27105 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
27108 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
27109 #define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)
27112 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
27113 #define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
27116 #define V_ACTIVEFILTERCOUNTS(x) ((x) << S_ACTIVEFILTERCOUNTS)
27117 #define F_ACTIVEFILTERCOUNTS    V_ACTIVEFILTERCOUNTS(1U)
27120 #define V_RXSACKPARSE(x) ((x) << S_RXSACKPARSE)
27121 #define F_RXSACKPARSE    V_RXSACKPARSE(1U)
27125 #define V_RXSACKFWDMODE(x) ((x) << S_RXSACKFWDMODE)
27126 #define G_RXSACKFWDMODE(x) (((x) >> S_RXSACKFWDMODE) & M_RXSACKFWDMODE)
27129 #define V_SRVRCHRSSEN(x) ((x) << S_SRVRCHRSSEN)
27130 #define F_SRVRCHRSSEN    V_SRVRCHRSSEN(1U)
27133 #define V_LBCHNDISTEN(x) ((x) << S_LBCHNDISTEN)
27134 #define F_LBCHNDISTEN    V_LBCHNDISTEN(1U)
27137 #define V_ETHTNLLEN2X(x) ((x) << S_ETHTNLLEN2X)
27138 #define F_ETHTNLLEN2X    V_ETHTNLLEN2X(1U)
27141 #define V_EGLBCHNDISTEN(x) ((x) << S_EGLBCHNDISTEN)
27142 #define F_EGLBCHNDISTEN    V_EGLBCHNDISTEN(1U)
27148 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
27149 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
27152 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
27153 #define F_CXMAXOPCNTDISABLE    V_CXMAXOPCNTDISABLE(1U)
27157 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
27158 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
27161 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
27162 #define F_TXMAXOPCNTDISABLE    V_TXMAXOPCNTDISABLE(1U)
27166 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
27167 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
27170 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
27171 #define F_RXMAXOPCNTDISABLE    V_RXMAXOPCNTDISABLE(1U)
27175 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
27176 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
27185 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
27186 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
27190 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
27191 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
27200 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
27201 #define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)
27205 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
27206 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
27210 #define V_T7_PMRXNUMCHN(x) ((x) << S_T7_PMRXNUMCHN)
27211 #define G_T7_PMRXNUMCHN(x) (((x) >> S_T7_PMRXNUMCHN) & M_T7_PMRXNUMCHN)
27218 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
27219 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
27223 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
27224 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
27228 #define V_T7_PMTXNUMCHN(x) ((x) << S_T7_PMTXNUMCHN)
27229 #define G_T7_PMTXNUMCHN(x) (((x) >> S_T7_PMTXNUMCHN) & M_T7_PMTXNUMCHN)
27234 #define V_TNLERRORIPSECARW(x) ((x) << S_TNLERRORIPSECARW)
27235 #define F_TNLERRORIPSECARW    V_TNLERRORIPSECARW(1U)
27238 #define V_TNLERRORIPSECICV(x) ((x) << S_TNLERRORIPSECICV)
27239 #define F_TNLERRORIPSECICV    V_TNLERRORIPSECICV(1U)
27242 #define V_DROPERRORIPSECARW(x) ((x) << S_DROPERRORIPSECARW)
27243 #define F_DROPERRORIPSECARW    V_DROPERRORIPSECARW(1U)
27246 #define V_DROPERRORIPSECICV(x) ((x) << S_DROPERRORIPSECICV)
27247 #define F_DROPERRORIPSECICV    V_DROPERRORIPSECICV(1U)
27250 #define V_MIBRDMAROCEEN(x) ((x) << S_MIBRDMAROCEEN)
27251 #define F_MIBRDMAROCEEN    V_MIBRDMAROCEEN(1U)
27254 #define V_MIBRDMAIWARPEN(x) ((x) << S_MIBRDMAIWARPEN)
27255 #define F_MIBRDMAIWARPEN    V_MIBRDMAIWARPEN(1U)
27258 #define V_BYPTXDATAACKALLEN(x) ((x) << S_BYPTXDATAACKALLEN)
27259 #define F_BYPTXDATAACKALLEN    V_BYPTXDATAACKALLEN(1U)
27262 #define V_DATAACKEXTEN(x) ((x) << S_DATAACKEXTEN)
27263 #define F_DATAACKEXTEN    V_DATAACKEXTEN(1U)
27266 #define V_MACMATCH11FWD(x) ((x) << S_MACMATCH11FWD)
27267 #define F_MACMATCH11FWD    V_MACMATCH11FWD(1U)
27270 #define V_USERTMSTPEN(x) ((x) << S_USERTMSTPEN)
27271 #define F_USERTMSTPEN    V_USERTMSTPEN(1U)
27274 #define V_MMGRCACHEDIS(x) ((x) << S_MMGRCACHEDIS)
27275 #define F_MMGRCACHEDIS    V_MMGRCACHEDIS(1U)
27278 #define V_TXPKTPACKOUTUDPEN(x) ((x) << S_TXPKTPACKOUTUDPEN)
27279 #define F_TXPKTPACKOUTUDPEN    V_TXPKTPACKOUTUDPEN(1U)
27283 #define V_IPSECROCECRCMODE(x) ((x) << S_IPSECROCECRCMODE)
27284 #define G_IPSECROCECRCMODE(x) (((x) >> S_IPSECROCECRCMODE) & M_IPSECROCECRCMODE)
27287 #define V_IPSECIDXLOC(x) ((x) << S_IPSECIDXLOC)
27288 #define F_IPSECIDXLOC    V_IPSECIDXLOC(1U)
27291 #define V_IPSECIDXCAPEN(x) ((x) << S_IPSECIDXCAPEN)
27292 #define F_IPSECIDXCAPEN    V_IPSECIDXCAPEN(1U)
27295 #define V_IPSECOFEN(x) ((x) << S_IPSECOFEN)
27296 #define F_IPSECOFEN    V_IPSECOFEN(1U)
27300 #define V_IPSECCFG(x) ((x) << S_IPSECCFG)
27301 #define G_IPSECCFG(x) (((x) >> S_IPSECCFG) & M_IPSECCFG)
27307 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
27308 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
27311 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
27312 #define F_MTUENABLE    V_MTUENABLE(1U)
27315 #define V_SACKTX(x) ((x) << S_SACKTX)
27316 #define F_SACKTX    V_SACKTX(1U)
27319 #define V_SACKRX(x) ((x) << S_SACKRX)
27320 #define F_SACKRX    V_SACKRX(1U)
27324 #define V_SACKMODE(x) ((x) << S_SACKMODE)
27325 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
27329 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
27330 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
27334 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
27335 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
27341 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
27342 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
27346 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
27347 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
27351 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
27352 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
27356 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
27357 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
27361 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
27362 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
27365 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
27366 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
27368 #define S_AUTOENABLE    1
27369 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
27370 #define F_AUTOENABLE    V_AUTOENABLE(1U)
27373 #define V_MODE(x) ((x) << S_MODE)
27374 #define F_MODE    V_MODE(1U)
27379 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
27380 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
27383 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
27384 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
27387 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
27388 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
27391 #define V_LOCKTID(x) ((x) << S_LOCKTID)
27392 #define F_LOCKTID    V_LOCKTID(1U)
27395 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
27396 #define F_DISABLEINVPEND    V_DISABLEINVPEND(1U)
27399 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
27400 #define F_ENABLEFILTERCOUNT    V_ENABLEFILTERCOUNT(1U)
27403 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
27404 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
27407 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
27408 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
27411 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
27412 #define F_ENABLEMINRCVWND    V_ENABLEMINRCVWND(1U)
27415 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
27416 #define F_ENABLEMAXRCVWND    V_ENABLEMAXRCVWND(1U)
27419 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
27420 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
27423 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
27424 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
27427 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
27428 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
27431 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
27432 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
27435 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
27436 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
27439 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
27440 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
27443 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
27444 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
27447 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
27448 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
27451 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
27452 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
27455 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
27456 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
27459 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
27460 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
27463 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
27464 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
27467 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
27468 #define F_ENABLEOPTMTU    V_ENABLEOPTMTU(1U)
27471 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
27472 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
27475 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
27476 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
27479 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
27480 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
27483 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
27484 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
27487 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
27488 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
27491 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
27492 #define F_ENABLEOFDOVLAN    V_ENABLEOFDOVLAN(1U)
27495 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
27496 #define F_DISABLETIMEWAIT    V_DISABLETIMEWAIT(1U)
27498 #define S_ENABLEVLANCHECK    1
27499 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
27500 #define F_ENABLEVLANCHECK    V_ENABLEVLANCHECK(1U)
27503 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
27504 #define F_TXDATAACKPAGEENABLE    V_TXDATAACKPAGEENABLE(1U)
27507 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
27508 #define F_ENABLEFILTERNAT    V_ENABLEFILTERNAT(1U)
27511 #define V_ENABLEFINCHECK(x) ((x) << S_ENABLEFINCHECK)
27512 #define F_ENABLEFINCHECK    V_ENABLEFINCHECK(1U)
27515 #define V_ENABLEMIBVFPLD(x) ((x) << S_ENABLEMIBVFPLD)
27516 #define F_ENABLEMIBVFPLD    V_ENABLEMIBVFPLD(1U)
27519 #define V_DISABLESEPPSHFLAG(x) ((x) << S_DISABLESEPPSHFLAG)
27520 #define F_DISABLESEPPSHFLAG    V_DISABLESEPPSHFLAG(1U)
27525 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
27526 #define F_ENABLEMTUVFMODE    V_ENABLEMTUVFMODE(1U)
27529 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
27530 #define F_ENABLEMIBVFMODE    V_ENABLEMIBVFMODE(1U)
27533 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
27534 #define F_DISABLELBKCHECK    V_DISABLELBKCHECK(1U)
27537 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
27538 #define F_ENABLEURGDDPOFF    V_ENABLEURGDDPOFF(1U)
27541 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
27542 #define F_ENABLEFILTERLPBK    V_ENABLEFILTERLPBK(1U)
27545 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
27546 #define F_DISABLETBLMMGR    V_DISABLETBLMMGR(1U)
27549 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
27550 #define F_CNGRECSNDNXT    V_CNGRECSNDNXT(1U)
27553 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
27554 #define F_ENABLELBKCHN    V_ENABLELBKCHN(1U)
27557 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
27558 #define F_ENABLELROECN    V_ENABLELROECN(1U)
27561 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
27562 #define F_ENABLEPCMDCHECK    V_ENABLEPCMDCHECK(1U)
27565 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
27566 #define F_ENABLEELBKAFULL    V_ENABLEELBKAFULL(1U)
27569 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
27570 #define F_ENABLECLBKAFULL    V_ENABLECLBKAFULL(1U)
27573 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
27574 #define F_ENABLEOESPIFULL    V_ENABLEOESPIFULL(1U)
27577 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
27578 #define F_DISABLEHITCHECK    V_DISABLEHITCHECK(1U)
27581 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
27582 #define F_ENABLERSSERRCHECK    V_ENABLERSSERRCHECK(1U)
27585 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
27586 #define F_DISABLENEWPSHFLAG    V_DISABLENEWPSHFLAG(1U)
27589 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
27590 #define F_ENABLERDDPRCVADVCLR    V_ENABLERDDPRCVADVCLR(1U)
27593 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
27594 #define F_ENABLETXDATAARPMISS    V_ENABLETXDATAARPMISS(1U)
27597 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
27598 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
27601 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
27602 #define F_ENABLERSTPAWS    V_ENABLERSTPAWS(1U)
27605 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
27606 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
27609 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
27610 #define F_ENABLENONOFDHYBRSS    V_ENABLENONOFDHYBRSS(1U)
27613 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
27614 #define F_ENABLEUDP4TUPRSS    V_ENABLEUDP4TUPRSS(1U)
27617 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
27618 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
27621 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
27622 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
27625 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
27626 #define F_ENABLECPCMDAFULL    V_ENABLECPCMDAFULL(1U)
27629 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
27630 #define F_ENABLEEHDRAFULL    V_ENABLEEHDRAFULL(1U)
27633 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
27634 #define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
27637 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
27638 #define F_ENABLEEMACAFULL    V_ENABLEEMACAFULL(1U)
27641 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
27642 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
27644 #define S_ENABLENONOFDTCBRSS    1
27645 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
27646 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
27649 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
27650 #define F_ENABLETNLOFDCLOSED    V_ENABLETNLOFDCLOSED(1U)
27653 #define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
27654 #define F_ENABLEFINDDPOFF    V_ENABLEFINDDPOFF(1U)
27660 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
27661 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
27665 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
27666 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
27670 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
27671 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
27675 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
27676 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
27682 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
27683 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
27687 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
27688 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
27692 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
27693 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
27697 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
27698 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
27704 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
27705 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
27709 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
27710 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
27714 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
27715 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
27719 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
27720 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
27726 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
27727 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
27731 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
27732 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
27736 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
27737 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
27741 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
27742 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
27747 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
27748 #define F_INITCWNDIDLE    V_INITCWNDIDLE(1U)
27752 #define V_INITCWND(x) ((x) << S_INITCWND)
27753 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
27757 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
27758 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
27761 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
27762 #define F_CPLERRENABLE    V_CPLERRENABLE(1U)
27765 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
27766 #define F_FASTTNLCNT    V_FASTTNLCNT(1U)
27769 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
27770 #define F_FASTTBLCNT    V_FASTTBLCNT(1U)
27773 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
27774 #define F_TPTCAMKEY    V_TPTCAMKEY(1U)
27777 #define V_SWSMODE(x) ((x) << S_SWSMODE)
27778 #define F_SWSMODE    V_SWSMODE(1U)
27782 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
27783 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
27787 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
27788 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
27791 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
27792 #define F_SWSSHOVE    V_SWSSHOVE(1U)
27795 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
27796 #define F_TBLTIMER    V_TBLTIMER(1U)
27798 #define S_RXTPACE    1
27799 #define V_RXTPACE(x) ((x) << S_RXTPACE)
27800 #define F_RXTPACE    V_RXTPACE(1U)
27803 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
27804 #define F_SWSTIMER    V_SWSTIMER(1U)
27808 #define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
27809 #define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
27812 #define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
27813 #define F_CHNERRENABLE    V_CHNERRENABLE(1U)
27816 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
27817 #define F_SETTIMEENABLE    V_SETTIMEENABLE(1U)
27820 #define V_ECNCNGFIFO(x) ((x) << S_ECNCNGFIFO)
27821 #define F_ECNCNGFIFO    V_ECNCNGFIFO(1U)
27824 #define V_ECNSYNACK(x) ((x) << S_ECNSYNACK)
27825 #define F_ECNSYNACK    V_ECNSYNACK(1U)
27829 #define V_ECNTHRESH(x) ((x) << S_ECNTHRESH)
27830 #define G_ECNTHRESH(x) (((x) >> S_ECNTHRESH) & M_ECNTHRESH)
27833 #define V_ECNMODE(x) ((x) << S_ECNMODE)
27834 #define F_ECNMODE    V_ECNMODE(1U)
27837 #define V_ECNMODECWR(x) ((x) << S_ECNMODECWR)
27838 #define F_ECNMODECWR    V_ECNMODECWR(1U)
27841 #define V_FORCESHOVE(x) ((x) << S_FORCESHOVE)
27842 #define F_FORCESHOVE    V_FORCESHOVE(1U)
27848 #define V_INITRWND(x) ((x) << S_INITRWND)
27849 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
27853 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
27854 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
27860 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
27861 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
27865 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
27866 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
27871 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
27872 #define F_ENABLETNLCNGLPBK    V_ENABLETNLCNGLPBK(1U)
27875 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
27876 #define F_ENABLETNLCNGFIFO    V_ENABLETNLCNGFIFO(1U)
27879 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
27880 #define F_ENABLETNLCNGHDR    V_ENABLETNLCNGHDR(1U)
27883 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
27884 #define F_ENABLETNLCNGSGE    V_ENABLETNLCNGSGE(1U)
27887 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
27888 #define F_RXMACCHECK    V_RXMACCHECK(1U)
27891 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
27892 #define F_RXSYNFILTER    V_RXSYNFILTER(1U)
27895 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
27896 #define F_CNGCTRLECN    V_CNGCTRLECN(1U)
27899 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
27900 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
27903 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
27904 #define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)
27907 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
27908 #define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)
27911 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
27912 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
27915 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
27916 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
27920 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
27921 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
27925 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
27926 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
27929 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
27930 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
27933 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
27934 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
27937 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
27938 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
27941 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
27942 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
27945 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
27946 #define F_RXCHNTUNNEL    V_RXCHNTUNNEL(1U)
27949 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
27950 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
27953 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
27954 #define F_RXURGMODE    V_RXURGMODE(1U)
27957 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
27958 #define F_TXURGMODE    V_TXURGMODE(1U)
27962 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
27963 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
27965 #define S_RXCOALESCEENABLE    1
27966 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
27967 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
27970 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
27971 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
27977 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
27978 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
27982 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
27983 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
27987 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
27988 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
27992 #define V_RENOCFG(x) ((x) << S_RENOCFG)
27993 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
27996 #define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
27997 #define F_IDLECWNDHIGHSPEED    V_IDLECWNDHIGHSPEED(1U)
28000 #define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
28001 #define F_RXMTCWNDHIGHSPEED    V_RXMTCWNDHIGHSPEED(1U)
28005 #define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
28006 #define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
28009 #define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
28010 #define F_BYTECOUNTHIGHSPEED    V_BYTECOUNTHIGHSPEED(1U)
28013 #define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
28014 #define F_IDLECWNDNEWRENO    V_IDLECWNDNEWRENO(1U)
28017 #define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
28018 #define F_RXMTCWNDNEWRENO    V_RXMTCWNDNEWRENO(1U)
28022 #define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
28023 #define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
28026 #define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
28027 #define F_BYTECOUNTNEWRENO    V_BYTECOUNTNEWRENO(1U)
28030 #define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
28031 #define F_IDLECWNDTAHOE    V_IDLECWNDTAHOE(1U)
28034 #define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
28035 #define F_RXMTCWNDTAHOE    V_RXMTCWNDTAHOE(1U)
28039 #define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
28040 #define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
28043 #define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
28044 #define F_BYTECOUNTTAHOE    V_BYTECOUNTTAHOE(1U)
28047 #define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
28048 #define F_IDLECWNDRENO    V_IDLECWNDRENO(1U)
28051 #define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
28052 #define F_RXMTCWNDRENO    V_RXMTCWNDRENO(1U)
28054 #define S_OVERDRIVERENO    1
28056 #define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
28057 #define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
28060 #define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
28061 #define F_BYTECOUNTRENO    V_BYTECOUNTRENO(1U)
28067 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
28068 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
28072 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
28073 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
28076 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
28077 #define F_ENABLEREADPDU    V_ENABLEREADPDU(1U)
28080 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
28081 #define F_RXREADAHEAD    V_RXREADAHEAD(1U)
28084 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
28085 #define F_EMPTYRQENABLE    V_EMPTYRQENABLE(1U)
28088 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
28089 #define F_SCHDENABLE    V_SCHDENABLE(1U)
28092 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
28093 #define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)
28096 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
28097 #define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)
28100 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
28101 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
28103 #define S_DACKTIMERSPIN    1
28104 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
28105 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
28108 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
28109 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
28112 #define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
28113 #define F_ENABLEXOFFPDU    V_ENABLEXOFFPDU(1U)
28116 #define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
28117 #define F_ENABLENEWFAR    V_ENABLENEWFAR(1U)
28120 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
28121 #define F_ENABLEFRAGCHECK    V_ENABLEFRAGCHECK(1U)
28124 #define V_ENABLEFCOECHECK(x) ((x) << S_ENABLEFCOECHECK)
28125 #define F_ENABLEFCOECHECK    V_ENABLEFCOECHECK(1U)
28127 #define S_ENABLERDMAFIX    1
28128 #define V_ENABLERDMAFIX(x) ((x) << S_ENABLERDMAFIX)
28129 #define F_ENABLERDMAFIX    V_ENABLERDMAFIX(1U)
28135 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
28136 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
28140 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
28141 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
28144 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
28145 #define F_ENABLECSAV    V_ENABLECSAV(1U)
28148 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
28149 #define F_ENABLEDEFERPDU    V_ENABLEDEFERPDU(1U)
28152 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
28153 #define F_ENABLEFLUSH    V_ENABLEFLUSH(1U)
28156 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
28157 #define F_ENABLEBYTEPERSIST    V_ENABLEBYTEPERSIST(1U)
28160 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
28161 #define F_DISABLETMOCNG    V_DISABLETMOCNG(1U)
28164 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
28165 #define F_TXREADAHEAD    V_TXREADAHEAD(1U)
28168 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
28169 #define F_ALLOWEXEPTION    V_ALLOWEXEPTION(1U)
28172 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
28173 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
28176 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
28177 #define F_ENABLEESND    V_ENABLEESND(1U)
28180 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
28181 #define F_ENABLECSND    V_ENABLECSND(1U)
28184 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
28185 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
28188 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
28189 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
28192 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
28193 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
28196 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
28197 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
28200 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
28201 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
28204 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
28205 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
28208 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
28209 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
28212 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
28213 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
28215 #define S_DISABLEPDURXMT    1
28216 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
28217 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
28220 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
28221 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
28224 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
28225 #define F_DISABLEPDUACK    V_DISABLEPDUACK(1U)
28228 #define V_TXTCAMKEY(x) ((x) << S_TXTCAMKEY)
28229 #define F_TXTCAMKEY    V_TXTCAMKEY(1U)
28232 #define V_ENABLECBYP(x) ((x) << S_ENABLECBYP)
28233 #define F_ENABLECBYP    V_ENABLECBYP(1U)
28239 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
28240 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
28244 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
28245 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
28251 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
28252 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
28256 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
28257 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
28261 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
28262 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
28266 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
28267 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
28271 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
28272 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
28276 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
28277 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
28281 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
28282 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
28287 #define V_ECNACKECT(x) ((x) << S_ECNACKECT)
28288 #define F_ECNACKECT    V_ECNACKECT(1U)
28290 #define S_ECNFINECT    1
28291 #define V_ECNFINECT(x) ((x) << S_ECNFINECT)
28292 #define F_ECNFINECT    V_ECNFINECT(1U)
28295 #define V_ECNSYNECT(x) ((x) << S_ECNSYNECT)
28296 #define F_ECNSYNECT    V_ECNSYNECT(1U)
28302 #define V_PMMAXXFERLEN3(x) ((x) << S_PMMAXXFERLEN3)
28303 #define G_PMMAXXFERLEN3(x) (((x) >> S_PMMAXXFERLEN3) & M_PMMAXXFERLEN3)
28307 #define V_PMMAXXFERLEN2(x) ((x) << S_PMMAXXFERLEN2)
28308 #define G_PMMAXXFERLEN2(x) (((x) >> S_PMMAXXFERLEN2) & M_PMMAXXFERLEN2)
28313 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
28314 #define F_TNLERRORPING    V_TNLERRORPING(1U)
28317 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
28318 #define F_TNLERRORCSUM    V_TNLERRORCSUM(1U)
28321 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
28322 #define F_TNLERRORCSUMIP    V_TNLERRORCSUMIP(1U)
28325 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
28326 #define F_TNLERRORTCPOPT    V_TNLERRORTCPOPT(1U)
28329 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
28330 #define F_TNLERRORPKTLEN    V_TNLERRORPKTLEN(1U)
28333 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
28334 #define F_TNLERRORTCPHDRLEN    V_TNLERRORTCPHDRLEN(1U)
28337 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
28338 #define F_TNLERRORIPHDRLEN    V_TNLERRORIPHDRLEN(1U)
28341 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
28342 #define F_TNLERRORETHHDRLEN    V_TNLERRORETHHDRLEN(1U)
28345 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
28346 #define F_TNLERRORATTACK    V_TNLERRORATTACK(1U)
28349 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
28350 #define F_TNLERRORFRAG    V_TNLERRORFRAG(1U)
28353 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
28354 #define F_TNLERRORIPVER    V_TNLERRORIPVER(1U)
28357 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
28358 #define F_TNLERRORMAC    V_TNLERRORMAC(1U)
28361 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
28362 #define F_TNLERRORANY    V_TNLERRORANY(1U)
28365 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
28366 #define F_DROPERRORPING    V_DROPERRORPING(1U)
28369 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
28370 #define F_DROPERRORCSUM    V_DROPERRORCSUM(1U)
28373 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
28374 #define F_DROPERRORCSUMIP    V_DROPERRORCSUMIP(1U)
28377 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
28378 #define F_DROPERRORTCPOPT    V_DROPERRORTCPOPT(1U)
28381 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
28382 #define F_DROPERRORPKTLEN    V_DROPERRORPKTLEN(1U)
28385 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
28386 #define F_DROPERRORTCPHDRLEN    V_DROPERRORTCPHDRLEN(1U)
28389 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
28390 #define F_DROPERRORIPHDRLEN    V_DROPERRORIPHDRLEN(1U)
28393 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
28394 #define F_DROPERRORETHHDRLEN    V_DROPERRORETHHDRLEN(1U)
28397 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
28398 #define F_DROPERRORATTACK    V_DROPERRORATTACK(1U)
28401 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
28402 #define F_DROPERRORFRAG    V_DROPERRORFRAG(1U)
28405 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
28406 #define F_DROPERRORIPVER    V_DROPERRORIPVER(1U)
28408 #define S_DROPERRORMAC    1
28409 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
28410 #define F_DROPERRORMAC    V_DROPERRORMAC(1U)
28413 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
28414 #define F_DROPERRORANY    V_DROPERRORANY(1U)
28417 #define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
28418 #define F_TNLERRORFPMA    V_TNLERRORFPMA(1U)
28421 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
28422 #define F_DROPERRORFPMA    V_DROPERRORFPMA(1U)
28425 #define V_TNLERROROPAQUE(x) ((x) << S_TNLERROROPAQUE)
28426 #define F_TNLERROROPAQUE    V_TNLERROROPAQUE(1U)
28429 #define V_TNLERRORIP6OPT(x) ((x) << S_TNLERRORIP6OPT)
28430 #define F_TNLERRORIP6OPT    V_TNLERRORIP6OPT(1U)
28433 #define V_DROPERROROPAQUE(x) ((x) << S_DROPERROROPAQUE)
28434 #define F_DROPERROROPAQUE    V_DROPERROROPAQUE(1U)
28437 #define V_DROPERRORIP6OPT(x) ((x) << S_DROPERRORIP6OPT)
28438 #define F_DROPERRORIP6OPT    V_DROPERRORIP6OPT(1U)
28444 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
28445 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
28449 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
28450 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
28454 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
28455 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
28459 #define V_ROCETIMERRESOLUTION(x) ((x) << S_ROCETIMERRESOLUTION)
28460 #define G_ROCETIMERRESOLUTION(x) (((x) >> S_ROCETIMERRESOLUTION) & M_ROCETIMERRESOLUTION)
28466 #define V_MSL(x) ((x) << S_MSL)
28467 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
28473 #define V_RXTMIN(x) ((x) << S_RXTMIN)
28474 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
28480 #define V_RXTMAX(x) ((x) << S_RXTMAX)
28481 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
28487 #define V_PERSMIN(x) ((x) << S_PERSMIN)
28488 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
28494 #define V_PERSMAX(x) ((x) << S_PERSMAX)
28495 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
28501 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
28502 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
28508 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
28509 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
28515 #define V_MAXRTT(x) ((x) << S_MAXRTT)
28516 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
28520 #define V_INITSRTT(x) ((x) << S_INITSRTT)
28521 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
28527 #define V_DACKTIME(x) ((x) << S_DACKTIME)
28528 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
28534 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
28535 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
28541 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
28542 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
28548 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
28549 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
28553 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
28554 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
28558 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
28559 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
28563 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
28564 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
28568 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
28569 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
28573 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
28574 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
28578 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
28579 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
28583 #define V_T6_SYNSHIFTMAX(x) ((x) << S_T6_SYNSHIFTMAX)
28584 #define G_T6_SYNSHIFTMAX(x) (((x) >> S_T6_SYNSHIFTMAX) & M_T6_SYNSHIFTMAX)
28590 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
28591 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
28599 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
28600 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
28604 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
28605 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
28611 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
28612 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
28616 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
28617 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
28624 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
28625 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
28629 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
28630 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
28636 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
28637 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
28641 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
28642 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
28646 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
28647 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
28653 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
28654 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
28658 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
28659 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
28663 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
28664 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
28668 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
28669 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
28673 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
28674 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
28678 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
28679 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
28683 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
28684 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
28688 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
28689 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
28692 #define V_ULPTYPE7LENGTH(x) ((x) << S_ULPTYPE7LENGTH)
28693 #define F_ULPTYPE7LENGTH    V_ULPTYPE7LENGTH(1U)
28697 #define V_ULPTYPE7OFFSET(x) ((x) << S_ULPTYPE7OFFSET)
28698 #define G_ULPTYPE7OFFSET(x) (((x) >> S_ULPTYPE7OFFSET) & M_ULPTYPE7OFFSET)
28701 #define V_ULPTYPE6LENGTH(x) ((x) << S_ULPTYPE6LENGTH)
28702 #define F_ULPTYPE6LENGTH    V_ULPTYPE6LENGTH(1U)
28706 #define V_ULPTYPE6OFFSET(x) ((x) << S_ULPTYPE6OFFSET)
28707 #define G_ULPTYPE6OFFSET(x) (((x) >> S_ULPTYPE6OFFSET) & M_ULPTYPE6OFFSET)
28710 #define V_ULPTYPE5LENGTH(x) ((x) << S_ULPTYPE5LENGTH)
28711 #define F_ULPTYPE5LENGTH    V_ULPTYPE5LENGTH(1U)
28715 #define V_ULPTYPE5OFFSET(x) ((x) << S_ULPTYPE5OFFSET)
28716 #define G_ULPTYPE5OFFSET(x) (((x) >> S_ULPTYPE5OFFSET) & M_ULPTYPE5OFFSET)
28719 #define V_ULPTYPE4LENGTH(x) ((x) << S_ULPTYPE4LENGTH)
28720 #define F_ULPTYPE4LENGTH    V_ULPTYPE4LENGTH(1U)
28724 #define V_ULPTYPE4OFFSET(x) ((x) << S_ULPTYPE4OFFSET)
28725 #define G_ULPTYPE4OFFSET(x) (((x) >> S_ULPTYPE4OFFSET) & M_ULPTYPE4OFFSET)
28728 #define V_ULPTYPE3LENGTH(x) ((x) << S_ULPTYPE3LENGTH)
28729 #define F_ULPTYPE3LENGTH    V_ULPTYPE3LENGTH(1U)
28733 #define V_ULPTYPE3OFFSET(x) ((x) << S_ULPTYPE3OFFSET)
28734 #define G_ULPTYPE3OFFSET(x) (((x) >> S_ULPTYPE3OFFSET) & M_ULPTYPE3OFFSET)
28737 #define V_ULPTYPE2LENGTH(x) ((x) << S_ULPTYPE2LENGTH)
28738 #define F_ULPTYPE2LENGTH    V_ULPTYPE2LENGTH(1U)
28742 #define V_ULPTYPE2OFFSET(x) ((x) << S_ULPTYPE2OFFSET)
28743 #define G_ULPTYPE2OFFSET(x) (((x) >> S_ULPTYPE2OFFSET) & M_ULPTYPE2OFFSET)
28746 #define V_ULPTYPE1LENGTH(x) ((x) << S_ULPTYPE1LENGTH)
28747 #define F_ULPTYPE1LENGTH    V_ULPTYPE1LENGTH(1U)
28751 #define V_ULPTYPE1OFFSET(x) ((x) << S_ULPTYPE1OFFSET)
28752 #define G_ULPTYPE1OFFSET(x) (((x) >> S_ULPTYPE1OFFSET) & M_ULPTYPE1OFFSET)
28755 #define V_ULPTYPE0LENGTH(x) ((x) << S_ULPTYPE0LENGTH)
28756 #define F_ULPTYPE0LENGTH    V_ULPTYPE0LENGTH(1U)
28760 #define V_ULPTYPE0OFFSET(x) ((x) << S_ULPTYPE0OFFSET)
28761 #define G_ULPTYPE0OFFSET(x) (((x) >> S_ULPTYPE0OFFSET) & M_ULPTYPE0OFFSET)
28766 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
28767 #define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)
28771 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
28772 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
28776 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
28777 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
28781 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
28782 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
28786 #define V_T6_LKPTBLROWIDX(x) ((x) << S_T6_LKPTBLROWIDX)
28787 #define G_T6_LKPTBLROWIDX(x) (((x) >> S_T6_LKPTBLROWIDX) & M_T6_LKPTBLROWIDX)
28792 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
28793 #define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)
28796 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
28797 #define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)
28800 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
28801 #define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)
28804 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
28805 #define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)
28808 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
28809 #define F_TNLTCPSEL    V_TNLTCPSEL(1U)
28812 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
28813 #define F_TNLIP6SEL    V_TNLIP6SEL(1U)
28816 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
28817 #define F_TNLVRTSEL    V_TNLVRTSEL(1U)
28820 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
28821 #define F_TNLMAPEN    V_TNLMAPEN(1U)
28824 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
28825 #define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)
28828 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
28829 #define F_OFDVRTSEL    V_OFDVRTSEL(1U)
28832 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
28833 #define F_OFDMAPEN    V_OFDMAPEN(1U)
28836 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
28837 #define F_OFDLKPEN    V_OFDLKPEN(1U)
28840 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
28841 #define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)
28844 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
28845 #define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)
28848 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
28849 #define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)
28852 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
28853 #define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)
28856 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
28857 #define F_SYNIP6SEL    V_SYNIP6SEL(1U)
28860 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
28861 #define F_SYNVRTSEL    V_SYNVRTSEL(1U)
28864 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
28865 #define F_SYNMAPEN    V_SYNMAPEN(1U)
28868 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
28869 #define F_SYNLKPEN    V_SYNLKPEN(1U)
28872 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
28873 #define F_CHANNELENABLE    V_CHANNELENABLE(1U)
28876 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
28877 #define F_PORTENABLE    V_PORTENABLE(1U)
28880 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
28881 #define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)
28884 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
28885 #define F_VIRTENABLE    V_VIRTENABLE(1U)
28888 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
28889 #define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)
28892 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
28893 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
28895 #define S_UDPENABLE    1
28896 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
28897 #define F_UDPENABLE    V_UDPENABLE(1U)
28900 #define V_DISABLE(x) ((x) << S_DISABLE)
28901 #define F_DISABLE    V_DISABLE(1U)
28904 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
28905 #define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)
28908 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
28909 #define F_TNLFCOEEN    V_TNLFCOEEN(1U)
28912 #define V_HASHXOR(x) ((x) << S_HASHXOR)
28913 #define F_HASHXOR    V_HASHXOR(1U)
28916 #define V_TNLFCOESID(x) ((x) << S_TNLFCOESID)
28917 #define F_TNLFCOESID    V_TNLFCOESID(1U)
28923 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
28924 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
28928 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
28929 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
28932 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
28933 #define F_USEWIRECH    V_USEWIRECH(1U)
28936 #define V_HASHALL(x) ((x) << S_HASHALL)
28937 #define F_HASHALL    V_HASHALL(1U)
28939 #define S_HASHETH    1
28940 #define V_HASHETH(x) ((x) << S_HASHETH)
28941 #define F_HASHETH    V_HASHETH(1U)
28946 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
28947 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
28951 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
28952 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
28956 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
28957 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
28960 #define V_RRCPLOPT1SMSELEN(x) ((x) << S_RRCPLOPT1SMSELEN)
28961 #define F_RRCPLOPT1SMSELEN    V_RRCPLOPT1SMSELEN(1U)
28964 #define V_RRCPLOPT1BQEN(x) ((x) << S_RRCPLOPT1BQEN)
28965 #define F_RRCPLOPT1BQEN    V_RRCPLOPT1BQEN(1U)
28971 #define V_VFRDRG(x) ((x) << S_VFRDRG)
28972 #define F_VFRDRG    V_VFRDRG(1U)
28975 #define V_VFRDEN(x) ((x) << S_VFRDEN)
28976 #define F_VFRDEN    V_VFRDEN(1U)
28979 #define V_VFPERREN(x) ((x) << S_VFPERREN)
28980 #define F_VFPERREN    V_VFPERREN(1U)
28983 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
28984 #define F_KEYPERREN    V_KEYPERREN(1U)
28987 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
28988 #define F_DISABLEVLAN    V_DISABLEVLAN(1U)
28991 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
28992 #define F_ENABLEUP0    V_ENABLEUP0(1U)
28996 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
28997 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
29001 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
29002 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
29006 #define V_KEYMODE(x) ((x) << S_KEYMODE)
29007 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
29010 #define V_VFWREN(x) ((x) << S_VFWREN)
29011 #define F_VFWREN    V_VFWREN(1U)
29014 #define V_KEYWREN(x) ((x) << S_KEYWREN)
29015 #define F_KEYWREN    V_KEYWREN(1U)
29019 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
29020 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
29023 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
29024 #define F_VFVLANEN    V_VFVLANEN(1U)
29027 #define V_VFFWEN(x) ((x) << S_VFFWEN)
29028 #define F_VFFWEN    V_VFFWEN(1U)
29032 #define V_KEYWRADDRX(x) ((x) << S_KEYWRADDRX)
29033 #define G_KEYWRADDRX(x) (((x) >> S_KEYWRADDRX) & M_KEYWRADDRX)
29036 #define V_KEYEXTEND(x) ((x) << S_KEYEXTEND)
29037 #define F_KEYEXTEND    V_KEYEXTEND(1U)
29041 #define V_T6_VFWRADDR(x) ((x) << S_T6_VFWRADDR)
29042 #define G_T6_VFWRADDR(x) (((x) >> S_T6_VFWRADDR) & M_T6_VFWRADDR)
29047 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
29048 #define F_CHNCOUNT3    V_CHNCOUNT3(1U)
29051 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
29052 #define F_CHNCOUNT2    V_CHNCOUNT2(1U)
29055 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
29056 #define F_CHNCOUNT1    V_CHNCOUNT1(1U)
29059 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
29060 #define F_CHNCOUNT0    V_CHNCOUNT0(1U)
29063 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
29064 #define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)
29067 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
29068 #define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)
29071 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
29072 #define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)
29075 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
29076 #define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)
29079 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
29080 #define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)
29083 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
29084 #define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)
29087 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
29088 #define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)
29091 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
29092 #define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)
29095 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
29096 #define F_RSTCHN3    V_RSTCHN3(1U)
29099 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
29100 #define F_RSTCHN2    V_RSTCHN2(1U)
29103 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
29104 #define F_RSTCHN1    V_RSTCHN1(1U)
29107 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
29108 #define F_RSTCHN0    V_RSTCHN0(1U)
29111 #define V_UPDVLD(x) ((x) << S_UPDVLD)
29112 #define F_UPDVLD    V_UPDVLD(1U)
29115 #define V_XOFF(x) ((x) << S_XOFF)
29116 #define F_XOFF    V_XOFF(1U)
29119 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
29120 #define F_UPDCHN3    V_UPDCHN3(1U)
29123 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
29124 #define F_UPDCHN2    V_UPDCHN2(1U)
29127 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
29128 #define F_UPDCHN1    V_UPDCHN1(1U)
29131 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
29132 #define F_UPDCHN0    V_UPDCHN0(1U)
29136 #define V_QUEUE(x) ((x) << S_QUEUE)
29137 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
29140 #define V_T7_UPDVLD(x) ((x) << S_T7_UPDVLD)
29141 #define F_T7_UPDVLD    V_T7_UPDVLD(1U)
29144 #define V_T7_XOFF(x) ((x) << S_T7_XOFF)
29145 #define F_T7_XOFF    V_T7_XOFF(1U)
29148 #define V_T7_UPDCHN3(x) ((x) << S_T7_UPDCHN3)
29149 #define F_T7_UPDCHN3    V_T7_UPDCHN3(1U)
29152 #define V_T7_UPDCHN2(x) ((x) << S_T7_UPDCHN2)
29153 #define F_T7_UPDCHN2    V_T7_UPDCHN2(1U)
29156 #define V_T7_UPDCHN1(x) ((x) << S_T7_UPDCHN1)
29157 #define F_T7_UPDCHN1    V_T7_UPDCHN1(1U)
29160 #define V_T7_UPDCHN0(x) ((x) << S_T7_UPDCHN0)
29161 #define F_T7_UPDCHN0    V_T7_UPDCHN0(1U)
29165 #define V_T7_QUEUE(x) ((x) << S_T7_QUEUE)
29166 #define G_T7_QUEUE(x) (((x) >> S_T7_QUEUE) & M_T7_QUEUE)
29170 #define S_BASEQIDEN    1
29171 #define V_BASEQIDEN(x) ((x) << S_BASEQIDEN)
29172 #define F_BASEQIDEN    V_BASEQIDEN(1U)
29175 #define V_200GMODE(x) ((x) << S_200GMODE)
29176 #define F_200GMODE    V_200GMODE(1U)
29181 #define V_SRAMRDDIS(x) ((x) << S_SRAMRDDIS)
29182 #define F_SRAMRDDIS    V_SRAMRDDIS(1U)
29185 #define V_SRAMSTART(x) ((x) << S_SRAMSTART)
29186 #define F_SRAMSTART    V_SRAMSTART(1U)
29189 #define V_SRAMWRITE(x) ((x) << S_SRAMWRITE)
29190 #define F_SRAMWRITE    V_SRAMWRITE(1U)
29194 #define V_SRAMSEL(x) ((x) << S_SRAMSEL)
29195 #define G_SRAMSEL(x) (((x) >> S_SRAMSEL) & M_SRAMSEL)
29199 #define V_SRAMADDR(x) ((x) << S_SRAMADDR)
29200 #define G_SRAMADDR(x) (((x) >> S_SRAMADDR) & M_SRAMADDR)
29206 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
29207 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
29211 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
29212 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
29218 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
29219 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
29223 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
29224 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
29232 #define V_RXCHANNELWEIGHT3(x) ((x) << S_RXCHANNELWEIGHT3)
29233 #define G_RXCHANNELWEIGHT3(x) (((x) >> S_RXCHANNELWEIGHT3) & M_RXCHANNELWEIGHT3)
29237 #define V_RXCHANNELWEIGHT2(x) ((x) << S_RXCHANNELWEIGHT2)
29238 #define G_RXCHANNELWEIGHT2(x) (((x) >> S_RXCHANNELWEIGHT2) & M_RXCHANNELWEIGHT2)
29244 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
29245 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
29249 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
29250 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
29254 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
29255 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
29259 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
29260 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
29266 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
29267 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
29271 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
29272 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
29276 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
29277 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
29283 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
29284 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
29288 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
29289 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
29293 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
29294 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
29298 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
29299 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
29305 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
29306 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
29310 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
29311 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
29315 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
29316 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
29320 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
29321 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
29328 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
29329 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
29333 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
29334 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
29338 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
29339 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
29343 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
29344 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
29350 #define S_FLSTINITENABLE    1
29351 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
29352 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
29355 #define V_TPRESET(x) ((x) << S_TPRESET)
29356 #define F_TPRESET    V_TPRESET(1U)
29369 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
29370 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
29375 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
29376 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
29379 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
29380 #define F_RSSLKPPERR    V_RSSLKPPERR(1U)
29383 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
29384 #define F_FLMPERRSET    V_FLMPERRSET(1U)
29387 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
29388 #define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
29391 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
29392 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
29395 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
29396 #define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
29399 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
29400 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
29403 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
29404 #define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
29407 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
29408 #define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
29411 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
29412 #define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
29415 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
29416 #define F_DBEXTPERR    V_DBEXTPERR(1U)
29419 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
29420 #define F_DBOPPERR    V_DBOPPERR(1U)
29423 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
29424 #define F_TMCACHEPERR    V_TMCACHEPERR(1U)
29427 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
29428 #define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
29431 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
29432 #define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
29435 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
29436 #define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
29439 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
29440 #define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
29443 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
29444 #define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
29447 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
29448 #define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
29451 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
29452 #define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
29455 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
29456 #define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
29459 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
29460 #define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
29463 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
29464 #define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
29467 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
29468 #define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
29471 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
29472 #define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
29475 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
29476 #define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
29479 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
29480 #define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
29483 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
29484 #define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
29487 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
29488 #define F_PDUFBKFIFOPERR    V_PDUFBKFIFOPERR(1U)
29490 #define S_CMOPEXTFIFOPERR    1
29491 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
29492 #define F_CMOPEXTFIFOPERR    V_CMOPEXTFIFOPERR(1U)
29495 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
29496 #define F_DELINVFIFOPERR    V_DELINVFIFOPERR(1U)
29499 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
29500 #define F_CTPOUTPLDFIFOPERR    V_CTPOUTPLDFIFOPERR(1U)
29502 #define S_SRQTABLEPERR    1
29503 #define V_SRQTABLEPERR(x) ((x) << S_SRQTABLEPERR)
29504 #define F_SRQTABLEPERR    V_SRQTABLEPERR(1U)
29507 #define V_TPCERR(x) ((x) << S_TPCERR)
29508 #define F_TPCERR    V_TPCERR(1U)
29511 #define V_OTHERPERR(x) ((x) << S_OTHERPERR)
29512 #define F_OTHERPERR    V_OTHERPERR(1U)
29515 #define V_TPEING1PERR(x) ((x) << S_TPEING1PERR)
29516 #define F_TPEING1PERR    V_TPEING1PERR(1U)
29519 #define V_TPEING0PERR(x) ((x) << S_TPEING0PERR)
29520 #define F_TPEING0PERR    V_TPEING0PERR(1U)
29522 #define S_TPEEGPERR    1
29523 #define V_TPEEGPERR(x) ((x) << S_TPEEGPERR)
29524 #define F_TPEEGPERR    V_TPEEGPERR(1U)
29527 #define V_TPCPERR(x) ((x) << S_TPCPERR)
29528 #define F_TPCPERR    V_TPCPERR(1U)
29536 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
29537 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
29542 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
29543 #define F_FREERXPAGECHN    V_FREERXPAGECHN(1U)
29547 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
29548 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
29552 #define V_T7_FREERXPAGECHN(x) ((x) << S_T7_FREERXPAGECHN)
29553 #define G_T7_FREERXPAGECHN(x) (((x) >> S_T7_FREERXPAGECHN) & M_T7_FREERXPAGECHN)
29559 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
29560 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
29564 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
29565 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
29569 #define V_T7_FREETXPAGECHN(x) ((x) << S_T7_FREETXPAGECHN)
29570 #define G_T7_FREETXPAGECHN(x) (((x) >> S_T7_FREETXPAGECHN) & M_T7_FREETXPAGECHN)
29582 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
29583 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
29586 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
29587 #define F_DISABLETIMEFREEZE    V_DISABLETIMEFREEZE(1U)
29593 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
29594 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
29597 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
29598 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
29601 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
29602 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
29605 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
29606 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
29609 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
29610 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
29613 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
29614 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
29617 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
29618 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
29621 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
29622 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
29625 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
29626 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
29629 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
29630 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
29633 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
29634 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
29637 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
29638 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
29641 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
29642 #define F_TXRXMURG    V_TXRXMURG(1U)
29645 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
29646 #define F_TXRXMFIN    V_TXRXMFIN(1U)
29649 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
29650 #define F_TXRXMSYN    V_TXRXMSYN(1U)
29653 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
29654 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
29657 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
29658 #define F_TXRXMFAST    V_TXRXMFAST(1U)
29661 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
29662 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
29665 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
29666 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
29669 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
29670 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
29673 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
29674 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
29676 #define S_TXRCVADVZERO    1
29677 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
29678 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
29681 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
29682 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
29685 #define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
29686 #define F_RXTIMERCOMPBUFFER    V_RXTIMERCOMPBUFFER(1U)
29689 #define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
29690 #define F_TXDFRFAST    V_TXDFRFAST(1U)
29693 #define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
29694 #define F_TXRXMMISC    V_TXRXMMISC(1U)
29699 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
29700 #define F_RXCOMMITRESET1    V_RXCOMMITRESET1(1U)
29703 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
29704 #define F_RXCOMMITRESET0    V_RXCOMMITRESET0(1U)
29707 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
29708 #define F_RXFORCECONG1    V_RXFORCECONG1(1U)
29711 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
29712 #define F_RXFORCECONG0    V_RXFORCECONG0(1U)
29716 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
29717 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
29721 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
29722 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
29726 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
29727 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
29731 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
29732 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
29736 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
29737 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
29741 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
29742 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
29746 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
29747 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
29751 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
29752 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
29756 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
29757 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
29761 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
29762 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
29765 #define V_RXCOMMITRESET3(x) ((x) << S_RXCOMMITRESET3)
29766 #define F_RXCOMMITRESET3    V_RXCOMMITRESET3(1U)
29769 #define V_RXCOMMITRESET2(x) ((x) << S_RXCOMMITRESET2)
29770 #define F_RXCOMMITRESET2    V_RXCOMMITRESET2(1U)
29773 #define V_T7_RXCOMMITRESET1(x) ((x) << S_T7_RXCOMMITRESET1)
29774 #define F_T7_RXCOMMITRESET1    V_T7_RXCOMMITRESET1(1U)
29777 #define V_T7_RXCOMMITRESET0(x) ((x) << S_T7_RXCOMMITRESET0)
29778 #define F_T7_RXCOMMITRESET0    V_T7_RXCOMMITRESET0(1U)
29781 #define V_RXFORCECONG3(x) ((x) << S_RXFORCECONG3)
29782 #define F_RXFORCECONG3    V_RXFORCECONG3(1U)
29785 #define V_RXFORCECONG2(x) ((x) << S_RXFORCECONG2)
29786 #define F_RXFORCECONG2    V_RXFORCECONG2(1U)
29788 #define S_T7_RXFORCECONG1    1
29789 #define V_T7_RXFORCECONG1(x) ((x) << S_T7_RXFORCECONG1)
29790 #define F_T7_RXFORCECONG1    V_T7_RXFORCECONG1(1U)
29793 #define V_T7_RXFORCECONG0(x) ((x) << S_T7_RXFORCECONG0)
29794 #define F_T7_RXFORCECONG0    V_T7_RXFORCECONG0(1U)
29799 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
29800 #define F_COMMITRESET3    V_COMMITRESET3(1U)
29803 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
29804 #define F_COMMITRESET2    V_COMMITRESET2(1U)
29807 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
29808 #define F_COMMITRESET1    V_COMMITRESET1(1U)
29811 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
29812 #define F_COMMITRESET0    V_COMMITRESET0(1U)
29815 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
29816 #define F_FORCECONG3    V_FORCECONG3(1U)
29819 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
29820 #define F_FORCECONG2    V_FORCECONG2(1U)
29823 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
29824 #define F_FORCECONG1    V_FORCECONG1(1U)
29827 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
29828 #define F_FORCECONG0    V_FORCECONG0(1U)
29832 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
29833 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
29837 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
29838 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
29843 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
29844 #define F_TXCHNXOFF3    V_TXCHNXOFF3(1U)
29847 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
29848 #define F_TXCHNXOFF2    V_TXCHNXOFF2(1U)
29851 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
29852 #define F_TXCHNXOFF1    V_TXCHNXOFF1(1U)
29855 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
29856 #define F_TXCHNXOFF0    V_TXCHNXOFF0(1U)
29859 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
29860 #define F_TXMODXOFF7    V_TXMODXOFF7(1U)
29863 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
29864 #define F_TXMODXOFF6    V_TXMODXOFF6(1U)
29867 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
29868 #define F_TXMODXOFF5    V_TXMODXOFF5(1U)
29871 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
29872 #define F_TXMODXOFF4    V_TXMODXOFF4(1U)
29875 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
29876 #define F_TXMODXOFF3    V_TXMODXOFF3(1U)
29879 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
29880 #define F_TXMODXOFF2    V_TXMODXOFF2(1U)
29883 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
29884 #define F_TXMODXOFF1    V_TXMODXOFF1(1U)
29887 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
29888 #define F_TXMODXOFF0    V_TXMODXOFF0(1U)
29891 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
29892 #define F_RXCHNXOFF3    V_RXCHNXOFF3(1U)
29895 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
29896 #define F_RXCHNXOFF2    V_RXCHNXOFF2(1U)
29899 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
29900 #define F_RXCHNXOFF1    V_RXCHNXOFF1(1U)
29903 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
29904 #define F_RXCHNXOFF0    V_RXCHNXOFF0(1U)
29906 #define S_RXMODXOFF1    1
29907 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
29908 #define F_RXMODXOFF1    V_RXMODXOFF1(1U)
29911 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
29912 #define F_RXMODXOFF0    V_RXMODXOFF0(1U)
29915 #define V_RXMODXOFF3(x) ((x) << S_RXMODXOFF3)
29916 #define F_RXMODXOFF3    V_RXMODXOFF3(1U)
29919 #define V_RXMODXOFF2(x) ((x) << S_RXMODXOFF2)
29920 #define F_RXMODXOFF2    V_RXMODXOFF2(1U)
29926 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
29927 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
29931 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
29932 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
29936 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
29937 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
29941 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
29942 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
29952 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
29953 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
29957 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
29958 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
29962 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
29963 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
29967 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
29968 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
29974 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
29975 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
29978 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
29979 #define F_DBGLAWHLF    V_DBGLAWHLF(1U)
29983 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
29984 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
29988 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
29989 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
29992 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
29993 #define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)
29996 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
29997 #define F_DBGLAENABLE    V_DBGLAENABLE(1U)
30001 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
30002 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
30010 #define V_FILTERTID(x) ((x) << S_FILTERTID)
30011 #define G_FILTERTID(x) (((x) >> S_FILTERTID) & M_FILTERTID)
30014 #define V_ENTIDFILTER(x) ((x) << S_ENTIDFILTER)
30015 #define F_ENTIDFILTER    V_ENTIDFILTER(1U)
30018 #define V_ENOFFLOAD(x) ((x) << S_ENOFFLOAD)
30019 #define F_ENOFFLOAD    V_ENOFFLOAD(1U)
30022 #define V_ENTUNNEL(x) ((x) << S_ENTUNNEL)
30023 #define F_ENTUNNEL    V_ENTUNNEL(1U)
30026 #define V_ENI(x) ((x) << S_ENI)
30027 #define F_ENI    V_ENI(1U)
30029 #define S_ENC    1
30030 #define V_ENC(x) ((x) << S_ENC)
30031 #define F_ENC    V_ENC(1U)
30034 #define V_ENE(x) ((x) << S_ENE)
30035 #define F_ENE    V_ENE(1U)
30040 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
30041 #define F_WRITEENABLE    V_WRITEENABLE(1U)
30044 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
30045 #define F_TCAMENABLE    V_TCAMENABLE(1U)
30049 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
30050 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
30052 #define S_LINEADDRESS    1
30054 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
30055 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
30058 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
30059 #define F_REQUESTDONE    V_REQUESTDONE(1U)
30069 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
30070 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
30078 #define V_INICMAC1_ERR(x) ((x) << S_INICMAC1_ERR)
30079 #define G_INICMAC1_ERR(x) (((x) >> S_INICMAC1_ERR) & M_INICMAC1_ERR)
30083 #define V_INICMAC0_ERR(x) ((x) << S_INICMAC0_ERR)
30084 #define G_INICMAC0_ERR(x) (((x) >> S_INICMAC0_ERR) & M_INICMAC0_ERR)
30090 #define V_DIS39320FIX(x) ((x) << S_DIS39320FIX)
30091 #define F_DIS39320FIX    V_DIS39320FIX(1U)
30095 #define V_IWARPMAXPDULEN(x) ((x) << S_IWARPMAXPDULEN)
30096 #define G_IWARPMAXPDULEN(x) (((x) >> S_IWARPMAXPDULEN) & M_IWARPMAXPDULEN)
30100 #define V_TLSMAXRXDATA(x) ((x) << S_TLSMAXRXDATA)
30101 #define G_TLSMAXRXDATA(x) (((x) >> S_TLSMAXRXDATA) & M_TLSMAXRXDATA)
30109 #define V_DMXFIFOOVFL(x) ((x) << S_DMXFIFOOVFL)
30110 #define F_DMXFIFOOVFL    V_DMXFIFOOVFL(1U)
30113 #define V_URX2TPCDDPINTF(x) ((x) << S_URX2TPCDDPINTF)
30114 #define F_URX2TPCDDPINTF    V_URX2TPCDDPINTF(1U)
30117 #define V_TPCDISPTOKENFIFO(x) ((x) << S_TPCDISPTOKENFIFO)
30118 #define F_TPCDISPTOKENFIFO    V_TPCDISPTOKENFIFO(1U)
30121 #define V_TPCDISPCPLFIFO3(x) ((x) << S_TPCDISPCPLFIFO3)
30122 #define F_TPCDISPCPLFIFO3    V_TPCDISPCPLFIFO3(1U)
30125 #define V_TPCDISPCPLFIFO2(x) ((x) << S_TPCDISPCPLFIFO2)
30126 #define F_TPCDISPCPLFIFO2    V_TPCDISPCPLFIFO2(1U)
30129 #define V_TPCDISPCPLFIFO1(x) ((x) << S_TPCDISPCPLFIFO1)
30130 #define F_TPCDISPCPLFIFO1    V_TPCDISPCPLFIFO1(1U)
30133 #define V_TPCDISPCPLFIFO0(x) ((x) << S_TPCDISPCPLFIFO0)
30134 #define F_TPCDISPCPLFIFO0    V_TPCDISPCPLFIFO0(1U)
30137 #define V_URXPLDINTFCRC3(x) ((x) << S_URXPLDINTFCRC3)
30138 #define F_URXPLDINTFCRC3    V_URXPLDINTFCRC3(1U)
30141 #define V_URXPLDINTFCRC2(x) ((x) << S_URXPLDINTFCRC2)
30142 #define F_URXPLDINTFCRC2    V_URXPLDINTFCRC2(1U)
30145 #define V_URXPLDINTFCRC1(x) ((x) << S_URXPLDINTFCRC1)
30146 #define F_URXPLDINTFCRC1    V_URXPLDINTFCRC1(1U)
30149 #define V_URXPLDINTFCRC0(x) ((x) << S_URXPLDINTFCRC0)
30150 #define F_URXPLDINTFCRC0    V_URXPLDINTFCRC0(1U)
30153 #define V_DMXDBFIFO(x) ((x) << S_DMXDBFIFO)
30154 #define F_DMXDBFIFO    V_DMXDBFIFO(1U)
30157 #define V_DMXDBSRAM(x) ((x) << S_DMXDBSRAM)
30158 #define F_DMXDBSRAM    V_DMXDBSRAM(1U)
30161 #define V_DMXCPLFIFO(x) ((x) << S_DMXCPLFIFO)
30162 #define F_DMXCPLFIFO    V_DMXCPLFIFO(1U)
30165 #define V_DMXCPLSRAM(x) ((x) << S_DMXCPLSRAM)
30166 #define F_DMXCPLSRAM    V_DMXCPLSRAM(1U)
30169 #define V_DMXCSUMFIFO(x) ((x) << S_DMXCSUMFIFO)
30170 #define F_DMXCSUMFIFO    V_DMXCSUMFIFO(1U)
30173 #define V_DMXLENFIFO(x) ((x) << S_DMXLENFIFO)
30174 #define F_DMXLENFIFO    V_DMXLENFIFO(1U)
30177 #define V_DMXCHECKFIFO(x) ((x) << S_DMXCHECKFIFO)
30178 #define F_DMXCHECKFIFO    V_DMXCHECKFIFO(1U)
30181 #define V_DMXWINFIFO(x) ((x) << S_DMXWINFIFO)
30182 #define F_DMXWINFIFO    V_DMXWINFIFO(1U)
30185 #define V_EGTOKENFIFO(x) ((x) << S_EGTOKENFIFO)
30186 #define F_EGTOKENFIFO    V_EGTOKENFIFO(1U)
30189 #define V_EGDATAFIFO(x) ((x) << S_EGDATAFIFO)
30190 #define F_EGDATAFIFO    V_EGDATAFIFO(1U)
30193 #define V_UTX2TPCINTF3(x) ((x) << S_UTX2TPCINTF3)
30194 #define F_UTX2TPCINTF3    V_UTX2TPCINTF3(1U)
30197 #define V_UTX2TPCINTF2(x) ((x) << S_UTX2TPCINTF2)
30198 #define F_UTX2TPCINTF2    V_UTX2TPCINTF2(1U)
30201 #define V_UTX2TPCINTF1(x) ((x) << S_UTX2TPCINTF1)
30202 #define F_UTX2TPCINTF1    V_UTX2TPCINTF1(1U)
30205 #define V_UTX2TPCINTF0(x) ((x) << S_UTX2TPCINTF0)
30206 #define F_UTX2TPCINTF0    V_UTX2TPCINTF0(1U)
30208 #define S_LBKTOKENFIFO    1
30209 #define V_LBKTOKENFIFO(x) ((x) << S_LBKTOKENFIFO)
30210 #define F_LBKTOKENFIFO    V_LBKTOKENFIFO(1U)
30213 #define V_LBKDATAFIFO(x) ((x) << S_LBKDATAFIFO)
30214 #define F_LBKDATAFIFO    V_LBKDATAFIFO(1U)
30220 #define V_MPSLPBKTOKENFIFO(x) ((x) << S_MPSLPBKTOKENFIFO)
30221 #define F_MPSLPBKTOKENFIFO    V_MPSLPBKTOKENFIFO(1U)
30224 #define V_MPSMACTOKENFIFO(x) ((x) << S_MPSMACTOKENFIFO)
30225 #define F_MPSMACTOKENFIFO    V_MPSMACTOKENFIFO(1U)
30228 #define V_DISPIPSECFIFO3(x) ((x) << S_DISPIPSECFIFO3)
30229 #define F_DISPIPSECFIFO3    V_DISPIPSECFIFO3(1U)
30232 #define V_DISPTCPFIFO3(x) ((x) << S_DISPTCPFIFO3)
30233 #define F_DISPTCPFIFO3    V_DISPTCPFIFO3(1U)
30236 #define V_DISPIPFIFO3(x) ((x) << S_DISPIPFIFO3)
30237 #define F_DISPIPFIFO3    V_DISPIPFIFO3(1U)
30240 #define V_DISPETHFIFO3(x) ((x) << S_DISPETHFIFO3)
30241 #define F_DISPETHFIFO3    V_DISPETHFIFO3(1U)
30244 #define V_DISPGREFIFO3(x) ((x) << S_DISPGREFIFO3)
30245 #define F_DISPGREFIFO3    V_DISPGREFIFO3(1U)
30248 #define V_DISPCPL5FIFO3(x) ((x) << S_DISPCPL5FIFO3)
30249 #define F_DISPCPL5FIFO3    V_DISPCPL5FIFO3(1U)
30252 #define V_DISPIPSECFIFO2(x) ((x) << S_DISPIPSECFIFO2)
30253 #define F_DISPIPSECFIFO2    V_DISPIPSECFIFO2(1U)
30256 #define V_DISPTCPFIFO2(x) ((x) << S_DISPTCPFIFO2)
30257 #define F_DISPTCPFIFO2    V_DISPTCPFIFO2(1U)
30260 #define V_DISPIPFIFO2(x) ((x) << S_DISPIPFIFO2)
30261 #define F_DISPIPFIFO2    V_DISPIPFIFO2(1U)
30264 #define V_DISPETHFIFO2(x) ((x) << S_DISPETHFIFO2)
30265 #define F_DISPETHFIFO2    V_DISPETHFIFO2(1U)
30268 #define V_DISPGREFIFO2(x) ((x) << S_DISPGREFIFO2)
30269 #define F_DISPGREFIFO2    V_DISPGREFIFO2(1U)
30272 #define V_DISPCPL5FIFO2(x) ((x) << S_DISPCPL5FIFO2)
30273 #define F_DISPCPL5FIFO2    V_DISPCPL5FIFO2(1U)
30276 #define V_DISPIPSECFIFO1(x) ((x) << S_DISPIPSECFIFO1)
30277 #define F_DISPIPSECFIFO1    V_DISPIPSECFIFO1(1U)
30280 #define V_DISPTCPFIFO1(x) ((x) << S_DISPTCPFIFO1)
30281 #define F_DISPTCPFIFO1    V_DISPTCPFIFO1(1U)
30284 #define V_DISPIPFIFO1(x) ((x) << S_DISPIPFIFO1)
30285 #define F_DISPIPFIFO1    V_DISPIPFIFO1(1U)
30288 #define V_DISPETHFIFO1(x) ((x) << S_DISPETHFIFO1)
30289 #define F_DISPETHFIFO1    V_DISPETHFIFO1(1U)
30292 #define V_DISPGREFIFO1(x) ((x) << S_DISPGREFIFO1)
30293 #define F_DISPGREFIFO1    V_DISPGREFIFO1(1U)
30296 #define V_DISPCPL5FIFO1(x) ((x) << S_DISPCPL5FIFO1)
30297 #define F_DISPCPL5FIFO1    V_DISPCPL5FIFO1(1U)
30300 #define V_DISPIPSECFIFO0(x) ((x) << S_DISPIPSECFIFO0)
30301 #define F_DISPIPSECFIFO0    V_DISPIPSECFIFO0(1U)
30304 #define V_DISPTCPFIFO0(x) ((x) << S_DISPTCPFIFO0)
30305 #define F_DISPTCPFIFO0    V_DISPTCPFIFO0(1U)
30308 #define V_DISPIPFIFO0(x) ((x) << S_DISPIPFIFO0)
30309 #define F_DISPIPFIFO0    V_DISPIPFIFO0(1U)
30312 #define V_DISPETHFIFO0(x) ((x) << S_DISPETHFIFO0)
30313 #define F_DISPETHFIFO0    V_DISPETHFIFO0(1U)
30315 #define S_DISPGREFIFO0    1
30316 #define V_DISPGREFIFO0(x) ((x) << S_DISPGREFIFO0)
30317 #define F_DISPGREFIFO0    V_DISPGREFIFO0(1U)
30320 #define V_DISPCPL5FIFO0(x) ((x) << S_DISPCPL5FIFO0)
30321 #define F_DISPCPL5FIFO0    V_DISPCPL5FIFO0(1U)
30327 #define V_DMXISSFIFO(x) ((x) << S_DMXISSFIFO)
30328 #define F_DMXISSFIFO    V_DMXISSFIFO(1U)
30331 #define V_DMXERRFIFO(x) ((x) << S_DMXERRFIFO)
30332 #define F_DMXERRFIFO    V_DMXERRFIFO(1U)
30335 #define V_DMXATTFIFO(x) ((x) << S_DMXATTFIFO)
30336 #define F_DMXATTFIFO    V_DMXATTFIFO(1U)
30339 #define V_DMXTCPFIFO(x) ((x) << S_DMXTCPFIFO)
30340 #define F_DMXTCPFIFO    V_DMXTCPFIFO(1U)
30343 #define V_DMXMPAFIFO(x) ((x) << S_DMXMPAFIFO)
30344 #define F_DMXMPAFIFO    V_DMXMPAFIFO(1U)
30347 #define V_DMXOPTFIFO(x) ((x) << S_DMXOPTFIFO)
30348 #define F_DMXOPTFIFO    V_DMXOPTFIFO(1U)
30351 #define V_INGTOKENFIFO(x) ((x) << S_INGTOKENFIFO)
30352 #define F_INGTOKENFIFO    V_INGTOKENFIFO(1U)
30355 #define V_DMXPLDCHKOVFL1(x) ((x) << S_DMXPLDCHKOVFL1)
30356 #define F_DMXPLDCHKOVFL1    V_DMXPLDCHKOVFL1(1U)
30359 #define V_DMXPLDCHKFIFO1(x) ((x) << S_DMXPLDCHKFIFO1)
30360 #define F_DMXPLDCHKFIFO1    V_DMXPLDCHKFIFO1(1U)
30363 #define V_DMXOPTFIFO1(x) ((x) << S_DMXOPTFIFO1)
30364 #define F_DMXOPTFIFO1    V_DMXOPTFIFO1(1U)
30367 #define V_DMXMPAFIFO1(x) ((x) << S_DMXMPAFIFO1)
30368 #define F_DMXMPAFIFO1    V_DMXMPAFIFO1(1U)
30371 #define V_DMXDBFIFO1(x) ((x) << S_DMXDBFIFO1)
30372 #define F_DMXDBFIFO1    V_DMXDBFIFO1(1U)
30375 #define V_DMXATTFIFO1(x) ((x) << S_DMXATTFIFO1)
30376 #define F_DMXATTFIFO1    V_DMXATTFIFO1(1U)
30379 #define V_DMXISSFIFO1(x) ((x) << S_DMXISSFIFO1)
30380 #define F_DMXISSFIFO1    V_DMXISSFIFO1(1U)
30383 #define V_DMXTCPFIFO1(x) ((x) << S_DMXTCPFIFO1)
30384 #define F_DMXTCPFIFO1    V_DMXTCPFIFO1(1U)
30387 #define V_DMXERRFIFO1(x) ((x) << S_DMXERRFIFO1)
30388 #define F_DMXERRFIFO1    V_DMXERRFIFO1(1U)
30391 #define V_MPS2TPINTF1(x) ((x) << S_MPS2TPINTF1)
30392 #define F_MPS2TPINTF1    V_MPS2TPINTF1(1U)
30395 #define V_DMXPLDCHKOVFL0(x) ((x) << S_DMXPLDCHKOVFL0)
30396 #define F_DMXPLDCHKOVFL0    V_DMXPLDCHKOVFL0(1U)
30399 #define V_DMXPLDCHKFIFO0(x) ((x) << S_DMXPLDCHKFIFO0)
30400 #define F_DMXPLDCHKFIFO0    V_DMXPLDCHKFIFO0(1U)
30403 #define V_DMXOPTFIFO0(x) ((x) << S_DMXOPTFIFO0)
30404 #define F_DMXOPTFIFO0    V_DMXOPTFIFO0(1U)
30407 #define V_DMXMPAFIFO0(x) ((x) << S_DMXMPAFIFO0)
30408 #define F_DMXMPAFIFO0    V_DMXMPAFIFO0(1U)
30411 #define V_DMXDBFIFO0(x) ((x) << S_DMXDBFIFO0)
30412 #define F_DMXDBFIFO0    V_DMXDBFIFO0(1U)
30415 #define V_DMXATTFIFO0(x) ((x) << S_DMXATTFIFO0)
30416 #define F_DMXATTFIFO0    V_DMXATTFIFO0(1U)
30419 #define V_DMXISSFIFO0(x) ((x) << S_DMXISSFIFO0)
30420 #define F_DMXISSFIFO0    V_DMXISSFIFO0(1U)
30423 #define V_DMXTCPFIFO0(x) ((x) << S_DMXTCPFIFO0)
30424 #define F_DMXTCPFIFO0    V_DMXTCPFIFO0(1U)
30426 #define S_DMXERRFIFO0    1
30427 #define V_DMXERRFIFO0(x) ((x) << S_DMXERRFIFO0)
30428 #define F_DMXERRFIFO0    V_DMXERRFIFO0(1U)
30431 #define V_MPS2TPINTF0(x) ((x) << S_MPS2TPINTF0)
30432 #define F_MPS2TPINTF0    V_MPS2TPINTF0(1U)
30438 #define V_DMXPLDCHKOVFL3(x) ((x) << S_DMXPLDCHKOVFL3)
30439 #define F_DMXPLDCHKOVFL3    V_DMXPLDCHKOVFL3(1U)
30442 #define V_DMXPLDCHKFIFO3(x) ((x) << S_DMXPLDCHKFIFO3)
30443 #define F_DMXPLDCHKFIFO3    V_DMXPLDCHKFIFO3(1U)
30446 #define V_DMXOPTFIFO3(x) ((x) << S_DMXOPTFIFO3)
30447 #define F_DMXOPTFIFO3    V_DMXOPTFIFO3(1U)
30450 #define V_DMXMPAFIFO3(x) ((x) << S_DMXMPAFIFO3)
30451 #define F_DMXMPAFIFO3    V_DMXMPAFIFO3(1U)
30454 #define V_DMXDBFIFO3(x) ((x) << S_DMXDBFIFO3)
30455 #define F_DMXDBFIFO3    V_DMXDBFIFO3(1U)
30458 #define V_DMXATTFIFO3(x) ((x) << S_DMXATTFIFO3)
30459 #define F_DMXATTFIFO3    V_DMXATTFIFO3(1U)
30462 #define V_DMXISSFIFO3(x) ((x) << S_DMXISSFIFO3)
30463 #define F_DMXISSFIFO3    V_DMXISSFIFO3(1U)
30466 #define V_DMXTCPFIFO3(x) ((x) << S_DMXTCPFIFO3)
30467 #define F_DMXTCPFIFO3    V_DMXTCPFIFO3(1U)
30470 #define V_DMXERRFIFO3(x) ((x) << S_DMXERRFIFO3)
30471 #define F_DMXERRFIFO3    V_DMXERRFIFO3(1U)
30474 #define V_MPS2TPINTF3(x) ((x) << S_MPS2TPINTF3)
30475 #define F_MPS2TPINTF3    V_MPS2TPINTF3(1U)
30478 #define V_DMXPLDCHKOVFL2(x) ((x) << S_DMXPLDCHKOVFL2)
30479 #define F_DMXPLDCHKOVFL2    V_DMXPLDCHKOVFL2(1U)
30482 #define V_DMXPLDCHKFIFO2(x) ((x) << S_DMXPLDCHKFIFO2)
30483 #define F_DMXPLDCHKFIFO2    V_DMXPLDCHKFIFO2(1U)
30486 #define V_DMXOPTFIFO2(x) ((x) << S_DMXOPTFIFO2)
30487 #define F_DMXOPTFIFO2    V_DMXOPTFIFO2(1U)
30490 #define V_DMXMPAFIFO2(x) ((x) << S_DMXMPAFIFO2)
30491 #define F_DMXMPAFIFO2    V_DMXMPAFIFO2(1U)
30494 #define V_DMXDBFIFO2(x) ((x) << S_DMXDBFIFO2)
30495 #define F_DMXDBFIFO2    V_DMXDBFIFO2(1U)
30498 #define V_DMXATTFIFO2(x) ((x) << S_DMXATTFIFO2)
30499 #define F_DMXATTFIFO2    V_DMXATTFIFO2(1U)
30502 #define V_DMXISSFIFO2(x) ((x) << S_DMXISSFIFO2)
30503 #define F_DMXISSFIFO2    V_DMXISSFIFO2(1U)
30506 #define V_DMXTCPFIFO2(x) ((x) << S_DMXTCPFIFO2)
30507 #define F_DMXTCPFIFO2    V_DMXTCPFIFO2(1U)
30509 #define S_DMXERRFIFO2    1
30510 #define V_DMXERRFIFO2(x) ((x) << S_DMXERRFIFO2)
30511 #define F_DMXERRFIFO2    V_DMXERRFIFO2(1U)
30514 #define V_MPS2TPINTF2(x) ((x) << S_MPS2TPINTF2)
30515 #define F_MPS2TPINTF2    V_MPS2TPINTF2(1U)
30521 #define V_DMARBTPERR(x) ((x) << S_DMARBTPERR)
30522 #define F_DMARBTPERR    V_DMARBTPERR(1U)
30525 #define V_MMGRCACHEDATASRAM(x) ((x) << S_MMGRCACHEDATASRAM)
30526 #define F_MMGRCACHEDATASRAM    V_MMGRCACHEDATASRAM(1U)
30529 #define V_MMGRCACHETAGFIFO(x) ((x) << S_MMGRCACHETAGFIFO)
30530 #define F_MMGRCACHETAGFIFO    V_MMGRCACHETAGFIFO(1U)
30533 #define V_TPPROTOSRAM(x) ((x) << S_TPPROTOSRAM)
30534 #define F_TPPROTOSRAM    V_TPPROTOSRAM(1U)
30537 #define V_HSPSRAM(x) ((x) << S_HSPSRAM)
30538 #define F_HSPSRAM    V_HSPSRAM(1U)
30541 #define V_RATEGRPSRAM(x) ((x) << S_RATEGRPSRAM)
30542 #define F_RATEGRPSRAM    V_RATEGRPSRAM(1U)
30545 #define V_TXFBSEQFIFO(x) ((x) << S_TXFBSEQFIFO)
30546 #define F_TXFBSEQFIFO    V_TXFBSEQFIFO(1U)
30549 #define V_CMDATASRAM(x) ((x) << S_CMDATASRAM)
30550 #define F_CMDATASRAM    V_CMDATASRAM(1U)
30553 #define V_CMTAGFIFO(x) ((x) << S_CMTAGFIFO)
30554 #define F_CMTAGFIFO    V_CMTAGFIFO(1U)
30557 #define V_RFCOPFIFO(x) ((x) << S_RFCOPFIFO)
30558 #define F_RFCOPFIFO    V_RFCOPFIFO(1U)
30561 #define V_DELINVFIFO(x) ((x) << S_DELINVFIFO)
30562 #define F_DELINVFIFO    V_DELINVFIFO(1U)
30565 #define V_RSSCFGSRAM(x) ((x) << S_RSSCFGSRAM)
30566 #define F_RSSCFGSRAM    V_RSSCFGSRAM(1U)
30569 #define V_RSSKEYSRAM(x) ((x) << S_RSSKEYSRAM)
30570 #define F_RSSKEYSRAM    V_RSSKEYSRAM(1U)
30573 #define V_RSSLKPSRAM(x) ((x) << S_RSSLKPSRAM)
30574 #define F_RSSLKPSRAM    V_RSSLKPSRAM(1U)
30577 #define V_SRQSRAM(x) ((x) << S_SRQSRAM)
30578 #define F_SRQSRAM    V_SRQSRAM(1U)
30581 #define V_ARPDASRAM(x) ((x) << S_ARPDASRAM)
30582 #define F_ARPDASRAM    V_ARPDASRAM(1U)
30585 #define V_ARPSASRAM(x) ((x) << S_ARPSASRAM)
30586 #define F_ARPSASRAM    V_ARPSASRAM(1U)
30589 #define V_ARPGRESRAM(x) ((x) << S_ARPGRESRAM)
30590 #define F_ARPGRESRAM    V_ARPGRESRAM(1U)
30592 #define S_ARPIPSECSRAM1    1
30593 #define V_ARPIPSECSRAM1(x) ((x) << S_ARPIPSECSRAM1)
30594 #define F_ARPIPSECSRAM1    V_ARPIPSECSRAM1(1U)
30597 #define V_ARPIPSECSRAM0(x) ((x) << S_ARPIPSECSRAM0)
30598 #define F_ARPIPSECSRAM0    V_ARPIPSECSRAM0(1U)
30604 #define V_TPCEGDATAFIFO(x) ((x) << S_TPCEGDATAFIFO)
30605 #define F_TPCEGDATAFIFO    V_TPCEGDATAFIFO(1U)
30608 #define V_TPCLBKDATAFIFO(x) ((x) << S_TPCLBKDATAFIFO)
30609 #define F_TPCLBKDATAFIFO    V_TPCLBKDATAFIFO(1U)
30616 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
30617 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
30621 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
30622 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
30628 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
30629 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
30633 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
30634 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
30640 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
30641 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
30645 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
30646 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
30652 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
30653 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
30657 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
30658 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
30664 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
30665 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
30669 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
30670 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
30676 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
30677 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
30681 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
30682 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
30686 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
30687 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
30691 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
30692 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
30698 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
30699 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
30703 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
30704 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
30708 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
30709 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
30713 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
30714 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
30720 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
30721 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
30725 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
30726 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
30730 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
30731 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
30735 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
30736 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
30742 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
30743 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
30747 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
30748 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
30752 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
30753 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
30757 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
30758 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
30764 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
30765 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
30769 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
30770 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
30774 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
30775 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
30779 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
30780 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
30788 #define V_RXTIMERSEPQ3(x) ((x) << S_RXTIMERSEPQ3)
30789 #define G_RXTIMERSEPQ3(x) (((x) >> S_RXTIMERSEPQ3) & M_RXTIMERSEPQ3)
30793 #define V_RXTIMERSEPQ2(x) ((x) << S_RXTIMERSEPQ2)
30794 #define G_RXTIMERSEPQ2(x) (((x) >> S_RXTIMERSEPQ2) & M_RXTIMERSEPQ2)
30800 #define V_RXRATEINCQ3(x) ((x) << S_RXRATEINCQ3)
30801 #define G_RXRATEINCQ3(x) (((x) >> S_RXRATEINCQ3) & M_RXRATEINCQ3)
30805 #define V_RXRATETCKQ3(x) ((x) << S_RXRATETCKQ3)
30806 #define G_RXRATETCKQ3(x) (((x) >> S_RXRATETCKQ3) & M_RXRATETCKQ3)
30810 #define V_RXRATEINCQ2(x) ((x) << S_RXRATEINCQ2)
30811 #define G_RXRATEINCQ2(x) (((x) >> S_RXRATEINCQ2) & M_RXRATEINCQ2)
30815 #define V_RXRATETCKQ2(x) ((x) << S_RXRATETCKQ2)
30816 #define G_RXRATETCKQ2(x) (((x) >> S_RXRATETCKQ2) & M_RXRATETCKQ2)
30823 #define V_T7_ENABLELPBKFULL1(x) ((x) << S_T7_ENABLELPBKFULL1)
30824 #define G_T7_ENABLELPBKFULL1(x) (((x) >> S_T7_ENABLELPBKFULL1) & M_T7_ENABLELPBKFULL1)
30828 #define V_T7_ENABLEFIFOFULL1(x) ((x) << S_T7_ENABLEFIFOFULL1)
30829 #define G_T7_ENABLEFIFOFULL1(x) (((x) >> S_T7_ENABLEFIFOFULL1) & M_T7_ENABLEFIFOFULL1)
30833 #define V_T7_ENABLEPCMDFULL1(x) ((x) << S_T7_ENABLEPCMDFULL1)
30834 #define G_T7_ENABLEPCMDFULL1(x) (((x) >> S_T7_ENABLEPCMDFULL1) & M_T7_ENABLEPCMDFULL1)
30838 #define V_T7_ENABLEHDRFULL1(x) ((x) << S_T7_ENABLEHDRFULL1)
30839 #define G_T7_ENABLEHDRFULL1(x) (((x) >> S_T7_ENABLEHDRFULL1) & M_T7_ENABLEHDRFULL1)
30843 #define V_T7_ENABLELPBKFULL0(x) ((x) << S_T7_ENABLELPBKFULL0)
30844 #define G_T7_ENABLELPBKFULL0(x) (((x) >> S_T7_ENABLELPBKFULL0) & M_T7_ENABLELPBKFULL0)
30848 #define V_T7_ENABLEFIFOFULL0(x) ((x) << S_T7_ENABLEFIFOFULL0)
30849 #define G_T7_ENABLEFIFOFULL0(x) (((x) >> S_T7_ENABLEFIFOFULL0) & M_T7_ENABLEFIFOFULL0)
30853 #define V_T7_ENABLEPCMDFULL0(x) ((x) << S_T7_ENABLEPCMDFULL0)
30854 #define G_T7_ENABLEPCMDFULL0(x) (((x) >> S_T7_ENABLEPCMDFULL0) & M_T7_ENABLEPCMDFULL0)
30858 #define V_T7_ENABLEHDRFULL0(x) ((x) << S_T7_ENABLEHDRFULL0)
30859 #define G_T7_ENABLEHDRFULL0(x) (((x) >> S_T7_ENABLEHDRFULL0) & M_T7_ENABLEHDRFULL0)
30865 #define V_ENABLELPBKFULL3(x) ((x) << S_ENABLELPBKFULL3)
30866 #define G_ENABLELPBKFULL3(x) (((x) >> S_ENABLELPBKFULL3) & M_ENABLELPBKFULL3)
30870 #define V_ENABLEFIFOFULL3(x) ((x) << S_ENABLEFIFOFULL3)
30871 #define G_ENABLEFIFOFULL3(x) (((x) >> S_ENABLEFIFOFULL3) & M_ENABLEFIFOFULL3)
30875 #define V_ENABLEPCMDFULL3(x) ((x) << S_ENABLEPCMDFULL3)
30876 #define G_ENABLEPCMDFULL3(x) (((x) >> S_ENABLEPCMDFULL3) & M_ENABLEPCMDFULL3)
30880 #define V_ENABLEHDRFULL3(x) ((x) << S_ENABLEHDRFULL3)
30881 #define G_ENABLEHDRFULL3(x) (((x) >> S_ENABLEHDRFULL3) & M_ENABLEHDRFULL3)
30885 #define V_ENABLELPBKFULL2(x) ((x) << S_ENABLELPBKFULL2)
30886 #define G_ENABLELPBKFULL2(x) (((x) >> S_ENABLELPBKFULL2) & M_ENABLELPBKFULL2)
30890 #define V_ENABLEFIFOFULL2(x) ((x) << S_ENABLEFIFOFULL2)
30891 #define G_ENABLEFIFOFULL2(x) (((x) >> S_ENABLEFIFOFULL2) & M_ENABLEFIFOFULL2)
30895 #define V_ENABLEPCMDFULL2(x) ((x) << S_ENABLEPCMDFULL2)
30896 #define G_ENABLEPCMDFULL2(x) (((x) >> S_ENABLEPCMDFULL2) & M_ENABLEPCMDFULL2)
30900 #define V_ENABLEHDRFULL2(x) ((x) << S_ENABLEHDRFULL2)
30901 #define G_ENABLEHDRFULL2(x) (((x) >> S_ENABLEHDRFULL2) & M_ENABLEHDRFULL2)
30907 #define V_T7_RXMAPCHANNEL3(x) ((x) << S_T7_RXMAPCHANNEL3)
30908 #define G_T7_RXMAPCHANNEL3(x) (((x) >> S_T7_RXMAPCHANNEL3) & M_T7_RXMAPCHANNEL3)
30912 #define V_T7_RXMAPCHANNEL2(x) ((x) << S_T7_RXMAPCHANNEL2)
30913 #define G_T7_RXMAPCHANNEL2(x) (((x) >> S_T7_RXMAPCHANNEL2) & M_T7_RXMAPCHANNEL2)
30919 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
30920 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
30924 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
30925 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
30929 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
30930 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
30934 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
30935 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
30939 #define V_T7_RXMAPCHANNEL1(x) ((x) << S_T7_RXMAPCHANNEL1)
30940 #define G_T7_RXMAPCHANNEL1(x) (((x) >> S_T7_RXMAPCHANNEL1) & M_T7_RXMAPCHANNEL1)
30944 #define V_T7_RXMAPCHANNEL0(x) ((x) << S_T7_RXMAPCHANNEL0)
30945 #define G_T7_RXMAPCHANNEL0(x) (((x) >> S_T7_RXMAPCHANNEL0) & M_T7_RXMAPCHANNEL0)
30951 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
30952 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
30956 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
30957 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
30960 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
30961 #define F_RXSGECHANNEL3    V_RXSGECHANNEL3(1U)
30964 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
30965 #define F_RXSGECHANNEL2    V_RXSGECHANNEL2(1U)
30967 #define S_RXSGECHANNEL1    1
30968 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
30969 #define F_RXSGECHANNEL1    V_RXSGECHANNEL1(1U)
30972 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
30973 #define F_RXSGECHANNEL0    V_RXSGECHANNEL0(1U)
30977 #define V_RXSGEMOD3(x) ((x) << S_RXSGEMOD3)
30978 #define G_RXSGEMOD3(x) (((x) >> S_RXSGEMOD3) & M_RXSGEMOD3)
30982 #define V_RXSGEMOD2(x) ((x) << S_RXSGEMOD2)
30983 #define G_RXSGEMOD2(x) (((x) >> S_RXSGEMOD2) & M_RXSGEMOD2)
30989 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
30990 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
30994 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
30995 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
30999 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
31000 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
31004 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
31005 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
31008 #define V_TXLPKCHANNEL1(x) ((x) << S_TXLPKCHANNEL1)
31009 #define F_TXLPKCHANNEL1    V_TXLPKCHANNEL1(1U)
31012 #define V_TXLPKCHANNEL0(x) ((x) << S_TXLPKCHANNEL0)
31013 #define F_TXLPKCHANNEL0    V_TXLPKCHANNEL0(1U)
31016 #define V_TXLPKCHANNEL3(x) ((x) << S_TXLPKCHANNEL3)
31017 #define F_TXLPKCHANNEL3    V_TXLPKCHANNEL3(1U)
31020 #define V_TXLPKCHANNEL2(x) ((x) << S_TXLPKCHANNEL2)
31021 #define F_TXLPKCHANNEL2    V_TXLPKCHANNEL2(1U)
31027 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
31028 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
31032 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
31033 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
31037 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
31038 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
31042 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
31043 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
31047 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
31048 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
31052 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
31053 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
31057 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
31058 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
31062 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
31063 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
31069 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
31070 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
31074 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
31075 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
31079 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
31080 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
31084 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
31085 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
31089 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
31090 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
31094 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
31095 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
31099 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
31100 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
31104 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
31105 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
31111 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
31112 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
31116 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
31117 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
31121 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
31122 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
31126 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
31127 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
31131 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
31132 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
31136 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
31137 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
31141 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
31142 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
31146 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
31147 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
31153 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
31154 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
31158 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
31159 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
31163 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
31164 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
31168 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
31169 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
31173 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
31174 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
31178 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
31179 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
31183 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
31184 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
31188 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
31189 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
31195 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
31196 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
31200 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
31201 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
31205 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
31206 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
31210 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
31211 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
31215 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
31216 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
31219 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
31220 #define F_RXMAPC2CCHANNEL3    V_RXMAPC2CCHANNEL3(1U)
31223 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
31224 #define F_RXMAPC2CCHANNEL2    V_RXMAPC2CCHANNEL2(1U)
31227 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
31228 #define F_RXMAPC2CCHANNEL1    V_RXMAPC2CCHANNEL1(1U)
31231 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
31232 #define F_RXMAPC2CCHANNEL0    V_RXMAPC2CCHANNEL0(1U)
31235 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
31236 #define F_RXMAPE2CCHANNEL3    V_RXMAPE2CCHANNEL3(1U)
31239 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
31240 #define F_RXMAPE2CCHANNEL2    V_RXMAPE2CCHANNEL2(1U)
31242 #define S_RXMAPE2CCHANNEL1    1
31243 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
31244 #define F_RXMAPE2CCHANNEL1    V_RXMAPE2CCHANNEL1(1U)
31247 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
31248 #define F_RXMAPE2CCHANNEL0    V_RXMAPE2CCHANNEL0(1U)
31252 #define V_T7_LB_MODE(x) ((x) << S_T7_LB_MODE)
31253 #define G_T7_LB_MODE(x) (((x) >> S_T7_LB_MODE) & M_T7_LB_MODE)
31257 #define V_ING_LB_MODE(x) ((x) << S_ING_LB_MODE)
31258 #define G_ING_LB_MODE(x) (((x) >> S_ING_LB_MODE) & M_ING_LB_MODE)
31262 #define V_RXC_LB_MODE(x) ((x) << S_RXC_LB_MODE)
31263 #define G_RXC_LB_MODE(x) (((x) >> S_RXC_LB_MODE) & M_RXC_LB_MODE)
31266 #define V_SINGLERXCHANNEL(x) ((x) << S_SINGLERXCHANNEL)
31267 #define F_SINGLERXCHANNEL    V_SINGLERXCHANNEL(1U)
31270 #define V_RXCHANNELCHECK(x) ((x) << S_RXCHANNELCHECK)
31271 #define F_RXCHANNELCHECK    V_RXCHANNELCHECK(1U)
31275 #define V_T7_RXMAPC2CCHANNEL3(x) ((x) << S_T7_RXMAPC2CCHANNEL3)
31276 #define G_T7_RXMAPC2CCHANNEL3(x) (((x) >> S_T7_RXMAPC2CCHANNEL3) & M_T7_RXMAPC2CCHANNEL3)
31280 #define V_T7_RXMAPC2CCHANNEL2(x) ((x) << S_T7_RXMAPC2CCHANNEL2)
31281 #define G_T7_RXMAPC2CCHANNEL2(x) (((x) >> S_T7_RXMAPC2CCHANNEL2) & M_T7_RXMAPC2CCHANNEL2)
31285 #define V_T7_RXMAPC2CCHANNEL1(x) ((x) << S_T7_RXMAPC2CCHANNEL1)
31286 #define G_T7_RXMAPC2CCHANNEL1(x) (((x) >> S_T7_RXMAPC2CCHANNEL1) & M_T7_RXMAPC2CCHANNEL1)
31290 #define V_T7_RXMAPC2CCHANNEL0(x) ((x) << S_T7_RXMAPC2CCHANNEL0)
31291 #define G_T7_RXMAPC2CCHANNEL0(x) (((x) >> S_T7_RXMAPC2CCHANNEL0) & M_T7_RXMAPC2CCHANNEL0)
31295 #define V_T7_RXMAPE2CCHANNEL3(x) ((x) << S_T7_RXMAPE2CCHANNEL3)
31296 #define G_T7_RXMAPE2CCHANNEL3(x) (((x) >> S_T7_RXMAPE2CCHANNEL3) & M_T7_RXMAPE2CCHANNEL3)
31300 #define V_T7_RXMAPE2CCHANNEL2(x) ((x) << S_T7_RXMAPE2CCHANNEL2)
31301 #define G_T7_RXMAPE2CCHANNEL2(x) (((x) >> S_T7_RXMAPE2CCHANNEL2) & M_T7_RXMAPE2CCHANNEL2)
31305 #define V_T7_RXMAPE2CCHANNEL1(x) ((x) << S_T7_RXMAPE2CCHANNEL1)
31306 #define G_T7_RXMAPE2CCHANNEL1(x) (((x) >> S_T7_RXMAPE2CCHANNEL1) & M_T7_RXMAPE2CCHANNEL1)
31310 #define V_T7_RXMAPE2CCHANNEL0(x) ((x) << S_T7_RXMAPE2CCHANNEL0)
31311 #define G_T7_RXMAPE2CCHANNEL0(x) (((x) >> S_T7_RXMAPE2CCHANNEL0) & M_T7_RXMAPE2CCHANNEL0)
31319 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
31320 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
31324 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
31325 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
31329 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
31330 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
31334 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
31335 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
31341 #define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
31342 #define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
31346 #define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
31347 #define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
31351 #define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
31352 #define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
31356 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
31357 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
31363 #define V_COMMITLIMIT3H(x) ((x) << S_COMMITLIMIT3H)
31364 #define G_COMMITLIMIT3H(x) (((x) >> S_COMMITLIMIT3H) & M_COMMITLIMIT3H)
31368 #define V_COMMITLIMIT3L(x) ((x) << S_COMMITLIMIT3L)
31369 #define G_COMMITLIMIT3L(x) (((x) >> S_COMMITLIMIT3L) & M_COMMITLIMIT3L)
31373 #define V_COMMITLIMIT2H(x) ((x) << S_COMMITLIMIT2H)
31374 #define G_COMMITLIMIT2H(x) (((x) >> S_COMMITLIMIT2H) & M_COMMITLIMIT2H)
31378 #define V_COMMITLIMIT2L(x) ((x) << S_COMMITLIMIT2L)
31379 #define G_COMMITLIMIT2L(x) (((x) >> S_COMMITLIMIT2L) & M_COMMITLIMIT2L)
31385 #define V_T7_RXMAPCHANNELELN(x) ((x) << S_T7_RXMAPCHANNELELN)
31386 #define G_T7_RXMAPCHANNELELN(x) (((x) >> S_T7_RXMAPCHANNELELN) & M_T7_RXMAPCHANNELELN)
31390 #define V_T7_RXMAPE2LCHANNEL3(x) ((x) << S_T7_RXMAPE2LCHANNEL3)
31391 #define G_T7_RXMAPE2LCHANNEL3(x) (((x) >> S_T7_RXMAPE2LCHANNEL3) & M_T7_RXMAPE2LCHANNEL3)
31395 #define V_T7_RXMAPE2LCHANNEL2(x) ((x) << S_T7_RXMAPE2LCHANNEL2)
31396 #define G_T7_RXMAPE2LCHANNEL2(x) (((x) >> S_T7_RXMAPE2LCHANNEL2) & M_T7_RXMAPE2LCHANNEL2)
31400 #define V_T7_RXMAPE2LCHANNEL1(x) ((x) << S_T7_RXMAPE2LCHANNEL1)
31401 #define G_T7_RXMAPE2LCHANNEL1(x) (((x) >> S_T7_RXMAPE2LCHANNEL1) & M_T7_RXMAPE2LCHANNEL1)
31405 #define V_T7_RXMAPE2LCHANNEL0(x) ((x) << S_T7_RXMAPE2LCHANNEL0)
31406 #define G_T7_RXMAPE2LCHANNEL0(x) (((x) >> S_T7_RXMAPE2LCHANNEL0) & M_T7_RXMAPE2LCHANNEL0)
31411 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
31412 #define F_VLANENABLE    V_VLANENABLE(1U)
31415 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
31416 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
31419 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
31420 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
31423 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
31424 #define F_ARPENABLE    V_ARPENABLE(1U)
31428 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
31429 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
31435 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
31436 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
31440 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
31441 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
31446 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
31447 #define F_MAPENABLE    V_MAPENABLE(1U)
31450 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
31451 #define F_CHNENABLE    V_CHNENABLE(1U)
31454 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
31455 #define F_PRTENABLE    V_PRTENABLE(1U)
31458 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
31459 #define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)
31462 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
31463 #define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)
31466 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
31467 #define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)
31470 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
31471 #define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)
31474 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
31475 #define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)
31479 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
31480 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
31484 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
31485 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
31489 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
31490 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
31493 #define V_PRIENABLE(x) ((x) << S_PRIENABLE)
31494 #define F_PRIENABLE    V_PRIENABLE(1U)
31497 #define V_T6_CHNENABLE(x) ((x) << S_T6_CHNENABLE)
31498 #define F_T6_CHNENABLE    V_T6_CHNENABLE(1U)
31511 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
31512 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
31516 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
31517 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
31521 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
31522 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
31526 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
31527 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
31531 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
31532 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
31536 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
31537 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
31541 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
31542 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
31546 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
31547 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
31551 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
31552 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
31558 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
31559 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
31563 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
31564 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
31568 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
31569 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
31573 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
31574 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
31578 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
31579 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
31583 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
31584 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
31588 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
31589 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
31593 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
31594 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
31600 #define V_BASEQID(x) ((x) << S_BASEQID)
31601 #define G_BASEQID(x) (((x) >> S_BASEQID) & M_BASEQID)
31605 #define V_MAXRRQID(x) ((x) << S_MAXRRQID)
31606 #define G_MAXRRQID(x) (((x) >> S_MAXRRQID) & M_MAXRRQID)
31610 #define V_RRCOUNTER(x) ((x) << S_RRCOUNTER)
31611 #define G_RRCOUNTER(x) (((x) >> S_RRCOUNTER) & M_RRCOUNTER)
31616 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
31617 #define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)
31620 #define V_VFUPEN(x) ((x) << S_VFUPEN)
31621 #define F_VFUPEN    V_VFUPEN(1U)
31624 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
31625 #define F_VFVLNEX    V_VFVLNEX(1U)
31628 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
31629 #define F_VFPRTEN    V_VFPRTEN(1U)
31632 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
31633 #define F_VFCHNEN    V_VFCHNEN(1U)
31637 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
31638 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
31642 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
31643 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
31646 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
31647 #define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)
31650 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
31651 #define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)
31654 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
31655 #define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)
31658 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
31659 #define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)
31663 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
31664 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
31667 #define V_ROUNDROBINEN(x) ((x) << S_ROUNDROBINEN)
31668 #define F_ROUNDROBINEN    V_ROUNDROBINEN(1U)
31684 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
31685 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
31689 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
31690 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
31696 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
31697 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
31701 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
31702 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
31708 #define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
31709 #define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
31713 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
31714 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
31720 #define V_VXLANPORT(x) ((x) << S_VXLANPORT)
31721 #define G_VXLANPORT(x) (((x) >> S_VXLANPORT) & M_VXLANPORT)
31726 #define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
31727 #define F_SLEEPRDYVNT    V_SLEEPRDYVNT(1U)
31730 #define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
31731 #define F_SLEEPRDYTBL    V_SLEEPRDYTBL(1U)
31734 #define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
31735 #define F_SLEEPRDYMIB    V_SLEEPRDYMIB(1U)
31738 #define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
31739 #define F_SLEEPRDYARP    V_SLEEPRDYARP(1U)
31742 #define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
31743 #define F_SLEEPRDYRSS    V_SLEEPRDYRSS(1U)
31746 #define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
31747 #define F_SLEEPREQVNT    V_SLEEPREQVNT(1U)
31750 #define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
31751 #define F_SLEEPREQTBL    V_SLEEPREQTBL(1U)
31754 #define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
31755 #define F_SLEEPREQMIB    V_SLEEPREQMIB(1U)
31757 #define S_SLEEPREQARP    1
31758 #define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
31759 #define F_SLEEPREQARP    V_SLEEPREQARP(1U)
31762 #define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
31763 #define F_SLEEPREQRSS    V_SLEEPREQRSS(1U)
31769 #define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
31770 #define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
31774 #define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
31775 #define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
31779 #define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
31780 #define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
31784 #define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
31785 #define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
31787 #define S_IMMEDIASEEN    1
31788 #define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
31789 #define F_IMMEDIASEEN    V_IMMEDIASEEN(1U)
31792 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
31793 #define F_IMMEDIATEEN    V_IMMEDIATEEN(1U)
31796 #define V_SHAREDRQEN(x) ((x) << S_SHAREDRQEN)
31797 #define F_SHAREDRQEN    V_SHAREDRQEN(1U)
31800 #define V_SHAREDXRC(x) ((x) << S_SHAREDXRC)
31801 #define F_SHAREDXRC    V_SHAREDXRC(1U)
31805 #define V_VERIFYRSPOP(x) ((x) << S_VERIFYRSPOP)
31806 #define G_VERIFYRSPOP(x) (((x) >> S_VERIFYRSPOP) & M_VERIFYRSPOP)
31810 #define V_VERIFYREQOP(x) ((x) << S_VERIFYREQOP)
31811 #define G_VERIFYREQOP(x) (((x) >> S_VERIFYREQOP) & M_VERIFYREQOP)
31815 #define V_AWRITERSPOP(x) ((x) << S_AWRITERSPOP)
31816 #define G_AWRITERSPOP(x) (((x) >> S_AWRITERSPOP) & M_AWRITERSPOP)
31820 #define V_AWRITEREQOP(x) ((x) << S_AWRITEREQOP)
31821 #define G_AWRITEREQOP(x) (((x) >> S_AWRITEREQOP) & M_AWRITEREQOP)
31825 #define V_FLUSHRSPOP(x) ((x) << S_FLUSHRSPOP)
31826 #define G_FLUSHRSPOP(x) (((x) >> S_FLUSHRSPOP) & M_FLUSHRSPOP)
31830 #define V_FLUSHREQOP(x) ((x) << S_FLUSHREQOP)
31831 #define G_FLUSHREQOP(x) (((x) >> S_FLUSHREQOP) & M_FLUSHREQOP)
31837 #define V_TLSMODE(x) ((x) << S_TLSMODE)
31838 #define G_TLSMODE(x) (((x) >> S_TLSMODE) & M_TLSMODE)
31842 #define V_USERMODE(x) ((x) << S_USERMODE)
31843 #define G_USERMODE(x) (((x) >> S_USERMODE) & M_USERMODE)
31847 #define V_FCOEMODE(x) ((x) << S_FCOEMODE)
31848 #define G_FCOEMODE(x) (((x) >> S_FCOEMODE) & M_FCOEMODE)
31852 #define V_IANDPMODE(x) ((x) << S_IANDPMODE)
31853 #define G_IANDPMODE(x) (((x) >> S_IANDPMODE) & M_IANDPMODE)
31857 #define V_RDDPMODE(x) ((x) << S_RDDPMODE)
31858 #define G_RDDPMODE(x) (((x) >> S_RDDPMODE) & M_RDDPMODE)
31862 #define V_IWARPMODE(x) ((x) << S_IWARPMODE)
31863 #define G_IWARPMODE(x) (((x) >> S_IWARPMODE) & M_IWARPMODE)
31867 #define V_ISCSIMODE(x) ((x) << S_ISCSIMODE)
31868 #define G_ISCSIMODE(x) (((x) >> S_ISCSIMODE) & M_ISCSIMODE)
31872 #define V_DDPMODE(x) ((x) << S_DDPMODE)
31873 #define G_DDPMODE(x) (((x) >> S_DDPMODE) & M_DDPMODE)
31877 #define V_PASSMODE(x) ((x) << S_PASSMODE)
31878 #define G_PASSMODE(x) (((x) >> S_PASSMODE) & M_PASSMODE)
31882 #define V_NVMTMODE(x) ((x) << S_NVMTMODE)
31883 #define G_NVMTMODE(x) (((x) >> S_NVMTMODE) & M_NVMTMODE)
31887 #define V_ROCEMODE(x) ((x) << S_ROCEMODE)
31888 #define G_ROCEMODE(x) (((x) >> S_ROCEMODE) & M_ROCEMODE)
31892 #define V_DTLSMODE(x) ((x) << S_DTLSMODE)
31893 #define G_DTLSMODE(x) (((x) >> S_DTLSMODE) & M_DTLSMODE)
31899 #define V_WRCNTIDLE(x) ((x) << S_WRCNTIDLE)
31900 #define G_WRCNTIDLE(x) (((x) >> S_WRCNTIDLE) & M_WRCNTIDLE)
31904 #define V_RDTHRESHOLD(x) ((x) << S_RDTHRESHOLD)
31905 #define G_RDTHRESHOLD(x) (((x) >> S_RDTHRESHOLD) & M_RDTHRESHOLD)
31908 #define V_WRTHRLEVEL2(x) ((x) << S_WRTHRLEVEL2)
31909 #define F_WRTHRLEVEL2    V_WRTHRLEVEL2(1U)
31912 #define V_WRTHRLEVEL1(x) ((x) << S_WRTHRLEVEL1)
31913 #define F_WRTHRLEVEL1    V_WRTHRLEVEL1(1U)
31916 #define V_WRTHRTHRESHEN(x) ((x) << S_WRTHRTHRESHEN)
31917 #define F_WRTHRTHRESHEN    V_WRTHRTHRESHEN(1U)
31921 #define V_WRTHRTHRESH(x) ((x) << S_WRTHRTHRESH)
31922 #define G_WRTHRTHRESH(x) (((x) >> S_WRTHRTHRESH) & M_WRTHRTHRESH)
31928 #define V_VXLANFLAGS(x) ((x) << S_VXLANFLAGS)
31929 #define G_VXLANFLAGS(x) (((x) >> S_VXLANFLAGS) & M_VXLANFLAGS)
31933 #define V_VXLANTYPE(x) ((x) << S_VXLANTYPE)
31934 #define G_VXLANTYPE(x) (((x) >> S_VXLANTYPE) & M_VXLANTYPE)
31940 #define V_GREFLAGS(x) ((x) << S_GREFLAGS)
31941 #define G_GREFLAGS(x) (((x) >> S_GREFLAGS) & M_GREFLAGS)
31945 #define V_GRETYPE(x) ((x) << S_GRETYPE)
31946 #define G_GRETYPE(x) (((x) >> S_GRETYPE) & M_GRETYPE)
31953 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
31954 #define F_E_TCP_OP_SRDY    V_E_TCP_OP_SRDY(1U)
31957 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
31958 #define F_E_PLD_TXZEROP_SRDY    V_E_PLD_TXZEROP_SRDY(1U)
31961 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
31962 #define F_E_PLD_RX_SRDY    V_E_PLD_RX_SRDY(1U)
31965 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
31966 #define F_E_RX_ERROR_SRDY    V_E_RX_ERROR_SRDY(1U)
31969 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
31970 #define F_E_RX_ISS_SRDY    V_E_RX_ISS_SRDY(1U)
31973 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
31974 #define F_C_TCP_OP_SRDY    V_C_TCP_OP_SRDY(1U)
31977 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
31978 #define F_C_PLD_TXZEROP_SRDY    V_C_PLD_TXZEROP_SRDY(1U)
31981 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
31982 #define F_C_PLD_RX_SRDY    V_C_PLD_RX_SRDY(1U)
31985 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
31986 #define F_C_RX_ERROR_SRDY    V_C_RX_ERROR_SRDY(1U)
31989 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
31990 #define F_C_RX_ISS_SRDY    V_C_RX_ISS_SRDY(1U)
31993 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
31994 #define F_E_CPL5_TXVALID    V_E_CPL5_TXVALID(1U)
31997 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
31998 #define F_E_ETH_TXVALID    V_E_ETH_TXVALID(1U)
32001 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
32002 #define F_E_IP_TXVALID    V_E_IP_TXVALID(1U)
32005 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
32006 #define F_E_TCP_TXVALID    V_E_TCP_TXVALID(1U)
32009 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
32010 #define F_C_CPL5_RXVALID    V_C_CPL5_RXVALID(1U)
32012 #define S_C_CPL5_TXVALID    1
32013 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
32014 #define F_C_CPL5_TXVALID    V_C_CPL5_TXVALID(1U)
32017 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
32018 #define F_E_TCP_OPT_RXVALID    V_E_TCP_OPT_RXVALID(1U)
32023 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
32024 #define F_E_CPL5_TXFULL    V_E_CPL5_TXFULL(1U)
32027 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
32028 #define F_E_ETH_TXFULL    V_E_ETH_TXFULL(1U)
32031 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
32032 #define F_E_IP_TXFULL    V_E_IP_TXFULL(1U)
32035 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
32036 #define F_E_TCP_TXFULL    V_E_TCP_TXFULL(1U)
32039 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
32040 #define F_C_CPL5_RXFULL    V_C_CPL5_RXFULL(1U)
32042 #define S_C_CPL5_TXFULL    1
32043 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
32044 #define F_C_CPL5_TXFULL    V_C_CPL5_TXFULL(1U)
32047 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
32048 #define F_E_TCP_OPT_RXFULL    V_E_TCP_OPT_RXFULL(1U)
32053 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
32054 #define F_EMSGFATAL    V_EMSGFATAL(1U)
32057 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
32058 #define F_CMSGFATAL    V_CMSGFATAL(1U)
32061 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
32062 #define F_PAWSFATAL    V_PAWSFATAL(1U)
32065 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
32066 #define F_SRAMFATAL    V_SRAMFATAL(1U)
32070 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
32071 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
32075 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
32076 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
32079 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
32080 #define F_CPCMDLENFATAL    V_CPCMDLENFATAL(1U)
32083 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
32084 #define F_EPCMDLENFATAL    V_EPCMDLENFATAL(1U)
32088 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
32089 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
32093 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
32094 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
32098 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
32099 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
32103 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
32104 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
32107 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
32108 #define F_CPCMDEOIFATAL    V_CPCMDEOIFATAL(1U)
32111 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
32112 #define F_CMDBRQFATAL    V_CMDBRQFATAL(1U)
32116 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
32117 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
32121 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
32122 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
32125 #define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
32126 #define F_CPCMDTTLFATAL    V_CPCMDTTLFATAL(1U)
32129 #define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
32130 #define F_CDATACHNFATAL    V_CDATACHNFATAL(1U)
32135 #define V_CCPLENC(x) ((x) << S_CCPLENC)
32136 #define F_CCPLENC    V_CCPLENC(1U)
32139 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
32140 #define F_CWRCPLPKT    V_CWRCPLPKT(1U)
32143 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
32144 #define F_CWRETHPKT    V_CWRETHPKT(1U)
32147 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
32148 #define F_CWRIPPKT    V_CWRIPPKT(1U)
32151 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
32152 #define F_CWRTCPPKT    V_CWRTCPPKT(1U)
32155 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
32156 #define F_CWRZEROP    V_CWRZEROP(1U)
32159 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
32160 #define F_CCPLTXFULL    V_CCPLTXFULL(1U)
32163 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
32164 #define F_CETHTXFULL    V_CETHTXFULL(1U)
32167 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
32168 #define F_CIPTXFULL    V_CIPTXFULL(1U)
32171 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
32172 #define F_CTCPTXFULL    V_CTCPTXFULL(1U)
32175 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
32176 #define F_CPLDTXZEROPDRDY    V_CPLDTXZEROPDRDY(1U)
32179 #define V_ECPLENC(x) ((x) << S_ECPLENC)
32180 #define F_ECPLENC    V_ECPLENC(1U)
32183 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
32184 #define F_EWRCPLPKT    V_EWRCPLPKT(1U)
32187 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
32188 #define F_EWRETHPKT    V_EWRETHPKT(1U)
32191 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
32192 #define F_EWRIPPKT    V_EWRIPPKT(1U)
32195 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
32196 #define F_EWRTCPPKT    V_EWRTCPPKT(1U)
32199 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
32200 #define F_EWRZEROP    V_EWRZEROP(1U)
32203 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
32204 #define F_ECPLTXFULL    V_ECPLTXFULL(1U)
32207 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
32208 #define F_EETHTXFULL    V_EETHTXFULL(1U)
32211 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
32212 #define F_EIPTXFULL    V_EIPTXFULL(1U)
32214 #define S_ETCPTXFULL    1
32215 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
32216 #define F_ETCPTXFULL    V_ETCPTXFULL(1U)
32219 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
32220 #define F_EPLDTXZEROPDRDY    V_EPLDTXZEROPDRDY(1U)
32223 #define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
32224 #define F_CRXBUSYOUT    V_CRXBUSYOUT(1U)
32227 #define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
32228 #define F_CTXBUSYOUT    V_CTXBUSYOUT(1U)
32231 #define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
32232 #define F_CRDCPLPKT    V_CRDCPLPKT(1U)
32235 #define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
32236 #define F_CRDTCPPKT    V_CRDTCPPKT(1U)
32239 #define V_CNEWMSG(x) ((x) << S_CNEWMSG)
32240 #define F_CNEWMSG    V_CNEWMSG(1U)
32243 #define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
32244 #define F_ERXBUSYOUT    V_ERXBUSYOUT(1U)
32247 #define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
32248 #define F_ETXBUSYOUT    V_ETXBUSYOUT(1U)
32251 #define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
32252 #define F_ERDCPLPKT    V_ERDCPLPKT(1U)
32255 #define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
32256 #define F_ERDTCPPKT    V_ERDTCPPKT(1U)
32259 #define V_ENEWMSG(x) ((x) << S_ENEWMSG)
32260 #define F_ENEWMSG    V_ENEWMSG(1U)
32266 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
32267 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
32270 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
32271 #define F_SPURIOUSMSG    V_SPURIOUSMSG(1U)
32274 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
32275 #define F_SYNLEARNED    V_SYNLEARNED(1U)
32279 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
32280 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
32284 #define V_SRC(x) ((x) << S_SRC)
32285 #define G_SRC(x) (((x) >> S_SRC) & M_SRC)
32290 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
32291 #define F_RESOURCESREADY    V_RESOURCESREADY(1U)
32294 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
32295 #define F_RCFOPCODEOUTSRDY    V_RCFOPCODEOUTSRDY(1U)
32298 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
32299 #define F_RCFDATAOUTSRDY    V_RCFDATAOUTSRDY(1U)
32302 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
32303 #define F_FLUSHINPUTMSG    V_FLUSHINPUTMSG(1U)
32307 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
32308 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
32311 #define V_C_MSG(x) ((x) << S_C_MSG)
32312 #define F_C_MSG    V_C_MSG(1U)
32315 #define V_E_MSG(x) ((x) << S_E_MSG)
32316 #define F_E_MSG    V_E_MSG(1U)
32320 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
32321 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
32325 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
32326 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
32329 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
32330 #define F_SEENRESOURCESREADY    V_SEENRESOURCESREADY(1U)
32333 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
32334 #define F_RESOURCESREADYCOPY    V_RESOURCESREADYCOPY(1U)
32337 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
32338 #define F_OPCODEWAITSFORDATA    V_OPCODEWAITSFORDATA(1U)
32341 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
32342 #define F_CPLDRXSRDY    V_CPLDRXSRDY(1U)
32345 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
32346 #define F_CPLDRXZEROPSRDY    V_CPLDRXZEROPSRDY(1U)
32349 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
32350 #define F_EPLDRXZEROPSRDY    V_EPLDRXZEROPSRDY(1U)
32353 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
32354 #define F_ERXERRORSRDY    V_ERXERRORSRDY(1U)
32357 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
32358 #define F_EPLDRXSRDY    V_EPLDRXSRDY(1U)
32361 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
32362 #define F_CRXBUSY    V_CRXBUSY(1U)
32365 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
32366 #define F_ERXBUSY    V_ERXBUSY(1U)
32369 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
32370 #define F_TIMERINSERTBUSY    V_TIMERINSERTBUSY(1U)
32373 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
32374 #define F_WCFBUSY    V_WCFBUSY(1U)
32377 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
32378 #define F_CTXBUSY    V_CTXBUSY(1U)
32381 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
32382 #define F_CPCMDBUSY    V_CPCMDBUSY(1U)
32384 #define S_EPCMDBUSY    1
32385 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
32386 #define F_EPCMDBUSY    V_EPCMDBUSY(1U)
32389 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
32390 #define F_ETXBUSY    V_ETXBUSY(1U)
32394 #define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
32395 #define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
32398 #define V_DELDRDY(x) ((x) << S_DELDRDY)
32399 #define F_DELDRDY    V_DELDRDY(1U)
32401 #define S_T5_ETXBUSY    1
32402 #define V_T5_ETXBUSY(x) ((x) << S_T5_ETXBUSY)
32403 #define F_T5_ETXBUSY    V_T5_ETXBUSY(1U)
32406 #define V_T5_EPCMDBUSY(x) ((x) << S_T5_EPCMDBUSY)
32407 #define F_T5_EPCMDBUSY    V_T5_EPCMDBUSY(1U)
32412 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
32413 #define F_RXCPLSRDY    V_RXCPLSRDY(1U)
32416 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
32417 #define F_RXOPTSRDY    V_RXOPTSRDY(1U)
32420 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
32421 #define F_RXPLDLENSRDY    V_RXPLDLENSRDY(1U)
32424 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
32425 #define F_RXNOTBUSY    V_RXNOTBUSY(1U)
32429 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
32430 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
32433 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
32434 #define F_RCFPTIDSRDY    V_RCFPTIDSRDY(1U)
32437 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
32438 #define F_EPDUHDRSRDY    V_EPDUHDRSRDY(1U)
32441 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
32442 #define F_TUNNELPKTREG    V_TUNNELPKTREG(1U)
32445 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
32446 #define F_TXPKTCSUMSRDY    V_TXPKTCSUMSRDY(1U)
32450 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
32451 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
32454 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
32455 #define F_MMGRDONE    V_MMGRDONE(1U)
32458 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
32459 #define F_SEENMMGRDONE    V_SEENMMGRDONE(1U)
32462 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
32463 #define F_RXERRORSRDY    V_RXERRORSRDY(1U)
32466 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
32467 #define F_RCFOPTIONSTCPSRDY    V_RCFOPTIONSTCPSRDY(1U)
32471 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
32472 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
32475 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
32476 #define F_TABLEACCESINCREMENT    V_TABLEACCESINCREMENT(1U)
32479 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
32480 #define F_TABLEACCESCOMPLETE    V_TABLEACCESCOMPLETE(1U)
32483 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
32484 #define F_RCFOPCODEOUTUSABLE    V_RCFOPCODEOUTUSABLE(1U)
32487 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
32488 #define F_RCFDATAOUTUSABLE    V_RCFDATAOUTUSABLE(1U)
32490 #define S_RCFDATAWAITAFTERRD    1
32491 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
32492 #define F_RCFDATAWAITAFTERRD    V_RCFDATAWAITAFTERRD(1U)
32495 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
32496 #define F_RCFDATACMRDY    V_RCFDATACMRDY(1U)
32499 #define V_RXISSSRDY(x) ((x) << S_RXISSSRDY)
32500 #define F_RXISSSRDY    V_RXISSSRDY(1U)
32506 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
32507 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
32511 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
32512 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
32516 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
32517 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
32521 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
32522 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
32525 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
32526 #define F_CDATAOUT    V_CDATAOUT(1U)
32529 #define V_CREADPDU(x) ((x) << S_CREADPDU)
32530 #define F_CREADPDU    V_CREADPDU(1U)
32533 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
32534 #define F_EDATAOUT    V_EDATAOUT(1U)
32537 #define V_EREADPDU(x) ((x) << S_EREADPDU)
32538 #define F_EREADPDU    V_EREADPDU(1U)
32541 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
32542 #define F_ETCPOPSRDY    V_ETCPOPSRDY(1U)
32545 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
32546 #define F_CTCPOPSRDY    V_CTCPOPSRDY(1U)
32549 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
32550 #define F_CPKTOUT    V_CPKTOUT(1U)
32553 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
32554 #define F_CMDBRSPSRDY    V_CMDBRSPSRDY(1U)
32558 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
32559 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
32563 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
32564 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
32568 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
32569 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
32575 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
32576 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
32580 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
32581 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
32585 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
32586 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
32590 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
32591 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
32597 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
32598 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
32602 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
32603 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
32607 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
32608 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
32612 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
32613 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
32617 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
32618 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
32622 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
32623 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
32629 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
32630 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
32634 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
32635 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
32639 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
32640 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
32644 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
32645 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
32649 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
32650 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
32654 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
32655 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
32659 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
32660 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
32664 #define V_T5_RXFIFOCNG(x) ((x) << S_T5_RXFIFOCNG)
32665 #define G_T5_RXFIFOCNG(x) (((x) >> S_T5_RXFIFOCNG) & M_T5_RXFIFOCNG)
32669 #define V_T5_RXPCMDCNG(x) ((x) << S_T5_RXPCMDCNG)
32670 #define G_T5_RXPCMDCNG(x) (((x) >> S_T5_RXPCMDCNG) & M_T5_RXPCMDCNG)
32677 #define V_CPLCMDOUT3(x) ((x) << S_CPLCMDOUT3)
32678 #define G_CPLCMDOUT3(x) (((x) >> S_CPLCMDOUT3) & M_CPLCMDOUT3)
32682 #define V_CPLCMDOUT2(x) ((x) << S_CPLCMDOUT2)
32683 #define G_CPLCMDOUT2(x) (((x) >> S_CPLCMDOUT2) & M_CPLCMDOUT2)
32687 #define V_CPLCMDOUT1(x) ((x) << S_CPLCMDOUT1)
32688 #define G_CPLCMDOUT1(x) (((x) >> S_CPLCMDOUT1) & M_CPLCMDOUT1)
32692 #define V_CPLCMDOUT0(x) ((x) << S_CPLCMDOUT0)
32693 #define G_CPLCMDOUT0(x) (((x) >> S_CPLCMDOUT0) & M_CPLCMDOUT0)
32698 #define V_SRC3(x) ((x) << S_SRC3)
32699 #define F_SRC3    V_SRC3(1U)
32703 #define V_LINENUM3(x) ((x) << S_LINENUM3)
32704 #define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
32707 #define V_SRC2(x) ((x) << S_SRC2)
32708 #define F_SRC2    V_SRC2(1U)
32712 #define V_LINENUM2(x) ((x) << S_LINENUM2)
32713 #define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
32716 #define V_SRC1(x) ((x) << S_SRC1)
32717 #define F_SRC1    V_SRC1(1U)
32721 #define V_LINENUM1(x) ((x) << S_LINENUM1)
32722 #define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
32725 #define V_SRC0(x) ((x) << S_SRC0)
32726 #define F_SRC0    V_SRC0(1U)
32730 #define V_LINENUM0(x) ((x) << S_LINENUM0)
32731 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
32742 #define V_PFMAPALWAYS(x) ((x) << S_PFMAPALWAYS)
32743 #define F_PFMAPALWAYS    V_PFMAPALWAYS(1U)
32746 #define V_PFROUNDROBINEN(x) ((x) << S_PFROUNDROBINEN)
32747 #define F_PFROUNDROBINEN    V_PFROUNDROBINEN(1U)
32750 #define V_FOURCHNEN(x) ((x) << S_FOURCHNEN)
32751 #define F_FOURCHNEN    V_FOURCHNEN(1U)
32755 #define V_CH3DEFAULTQUEUE(x) ((x) << S_CH3DEFAULTQUEUE)
32756 #define G_CH3DEFAULTQUEUE(x) (((x) >> S_CH3DEFAULTQUEUE) & M_CH3DEFAULTQUEUE)
32760 #define V_CH2DEFAULTQUEUE(x) ((x) << S_CH2DEFAULTQUEUE)
32761 #define G_CH2DEFAULTQUEUE(x) (((x) >> S_CH2DEFAULTQUEUE) & M_CH2DEFAULTQUEUE)
32781 #define V_IGNAETHMSB(x) ((x) << S_IGNAETHMSB)
32782 #define F_IGNAETHMSB    V_IGNAETHMSB(1U)
32785 #define V_XDIDMMCTL(x) ((x) << S_XDIDMMCTL)
32786 #define F_XDIDMMCTL    V_XDIDMMCTL(1U)
32789 #define V_WRRETHDBGFWDEN(x) ((x) << S_WRRETHDBGFWDEN)
32790 #define F_WRRETHDBGFWDEN    V_WRRETHDBGFWDEN(1U)
32794 #define V_ACKINTGENCTRL(x) ((x) << S_ACKINTGENCTRL)
32795 #define G_ACKINTGENCTRL(x) (((x) >> S_ACKINTGENCTRL) & M_ACKINTGENCTRL)
32798 #define V_ATOMICALIGNCHKEN(x) ((x) << S_ATOMICALIGNCHKEN)
32799 #define F_ATOMICALIGNCHKEN    V_ATOMICALIGNCHKEN(1U)
32802 #define V_RDRETHLENCHKEN(x) ((x) << S_RDRETHLENCHKEN)
32803 #define F_RDRETHLENCHKEN    V_RDRETHLENCHKEN(1U)
32806 #define V_WRTOTALLENCHKEN(x) ((x) << S_WRTOTALLENCHKEN)
32807 #define F_WRTOTALLENCHKEN    V_WRTOTALLENCHKEN(1U)
32810 #define V_WRRETHLENCHKEN(x) ((x) << S_WRRETHLENCHKEN)
32811 #define F_WRRETHLENCHKEN    V_WRRETHLENCHKEN(1U)
32814 #define V_TNLERRORUDPLEN(x) ((x) << S_TNLERRORUDPLEN)
32815 #define F_TNLERRORUDPLEN    V_TNLERRORUDPLEN(1U)
32818 #define V_TNLERRORPKEY(x) ((x) << S_TNLERRORPKEY)
32819 #define F_TNLERRORPKEY    V_TNLERRORPKEY(1U)
32822 #define V_TNLERROROPCODE(x) ((x) << S_TNLERROROPCODE)
32823 #define F_TNLERROROPCODE    V_TNLERROROPCODE(1U)
32826 #define V_TNLERRORTVER(x) ((x) << S_TNLERRORTVER)
32827 #define F_TNLERRORTVER    V_TNLERRORTVER(1U)
32830 #define V_DROPERRORUDPLEN(x) ((x) << S_DROPERRORUDPLEN)
32831 #define F_DROPERRORUDPLEN    V_DROPERRORUDPLEN(1U)
32834 #define V_DROPERRORPKEY(x) ((x) << S_DROPERRORPKEY)
32835 #define F_DROPERRORPKEY    V_DROPERRORPKEY(1U)
32837 #define S_DROPERROROPCODE    1
32838 #define V_DROPERROROPCODE(x) ((x) << S_DROPERROROPCODE)
32839 #define F_DROPERROROPCODE    V_DROPERROROPCODE(1U)
32842 #define V_DROPERRORTVER(x) ((x) << S_DROPERRORTVER)
32843 #define F_DROPERRORTVER    V_DROPERRORTVER(1U)
32848 #define V_PDACHKEN(x) ((x) << S_PDACHKEN)
32849 #define F_PDACHKEN    V_PDACHKEN(1U)
32851 #define S_FORCERQNONDDP    1
32852 #define V_FORCERQNONDDP(x) ((x) << S_FORCERQNONDDP)
32853 #define F_FORCERQNONDDP    V_FORCERQNONDDP(1U)
32856 #define V_STRIPHCRC(x) ((x) << S_STRIPHCRC)
32857 #define F_STRIPHCRC    V_STRIPHCRC(1U)
32863 #define V_MAXHDR3(x) ((x) << S_MAXHDR3)
32864 #define G_MAXHDR3(x) (((x) >> S_MAXHDR3) & M_MAXHDR3)
32868 #define V_MAXHDR2(x) ((x) << S_MAXHDR2)
32869 #define G_MAXHDR2(x) (((x) >> S_MAXHDR2) & M_MAXHDR2)
32873 #define V_MAXHDR1(x) ((x) << S_MAXHDR1)
32874 #define G_MAXHDR1(x) (((x) >> S_MAXHDR1) & M_MAXHDR1)
32878 #define V_MAXHDR0(x) ((x) << S_MAXHDR0)
32879 #define G_MAXHDR0(x) (((x) >> S_MAXHDR0) & M_MAXHDR0)
32885 #define V_PDORSVD3(x) ((x) << S_PDORSVD3)
32886 #define G_PDORSVD3(x) (((x) >> S_PDORSVD3) & M_PDORSVD3)
32890 #define V_PDORSVD2(x) ((x) << S_PDORSVD2)
32891 #define G_PDORSVD2(x) (((x) >> S_PDORSVD2) & M_PDORSVD2)
32895 #define V_PDORSVD1(x) ((x) << S_PDORSVD1)
32896 #define G_PDORSVD1(x) (((x) >> S_PDORSVD1) & M_PDORSVD1)
32900 #define V_PDORSVD0(x) ((x) << S_PDORSVD0)
32901 #define G_PDORSVD0(x) (((x) >> S_PDORSVD0) & M_PDORSVD0)
32906 #define V_SRQLIMITEN(x) ((x) << S_SRQLIMITEN)
32907 #define F_SRQLIMITEN    V_SRQLIMITEN(1U)
32911 #define V_SNDIMMSEOP(x) ((x) << S_SNDIMMSEOP)
32912 #define G_SNDIMMSEOP(x) (((x) >> S_SNDIMMSEOP) & M_SNDIMMSEOP)
32916 #define V_SNDIMMOP(x) ((x) << S_SNDIMMOP)
32917 #define G_SNDIMMOP(x) (((x) >> S_SNDIMMOP) & M_SNDIMMOP)
32920 #define V_IWARPXRCIDCHKEN(x) ((x) << S_IWARPXRCIDCHKEN)
32921 #define F_IWARPXRCIDCHKEN    V_IWARPXRCIDCHKEN(1U)
32924 #define V_IWARPEXTOPEN(x) ((x) << S_IWARPEXTOPEN)
32925 #define F_IWARPEXTOPEN    V_IWARPEXTOPEN(1U)
32927 #define S_XRCIMPLTYPE    1
32928 #define V_XRCIMPLTYPE(x) ((x) << S_XRCIMPLTYPE)
32929 #define F_XRCIMPLTYPE    V_XRCIMPLTYPE(1U)
32932 #define V_XRCEN(x) ((x) << S_XRCEN)
32933 #define F_XRCEN    V_XRCEN(1U)
32939 #define V_GRP_CFG_RD(x) ((x) << S_GRP_CFG_RD)
32940 #define F_GRP_CFG_RD    V_GRP_CFG_RD(1U)
32943 #define V_GRP_CFG_INIT(x) ((x) << S_GRP_CFG_INIT)
32944 #define F_GRP_CFG_INIT    V_GRP_CFG_INIT(1U)
32947 #define V_GRP_CFG_RST(x) ((x) << S_GRP_CFG_RST)
32948 #define F_GRP_CFG_RST    V_GRP_CFG_RST(1U)
32952 #define V_GRP_CFG_SEL(x) ((x) << S_GRP_CFG_SEL)
32953 #define G_GRP_CFG_SEL(x) (((x) >> S_GRP_CFG_SEL) & M_GRP_CFG_SEL)
32957 #define V_US_TIMER_TICK(x) ((x) << S_US_TIMER_TICK)
32958 #define G_US_TIMER_TICK(x) (((x) >> S_US_TIMER_TICK) & M_US_TIMER_TICK)
32964 #define V_QUIESCETYPE1(x) ((x) << S_QUIESCETYPE1)
32965 #define G_QUIESCETYPE1(x) (((x) >> S_QUIESCETYPE1) & M_QUIESCETYPE1)
32969 #define V_QUIESCETYPE2(x) ((x) << S_QUIESCETYPE2)
32970 #define G_QUIESCETYPE2(x) (((x) >> S_QUIESCETYPE2) & M_QUIESCETYPE2)
32974 #define V_QUIESCETYPE3(x) ((x) << S_QUIESCETYPE3)
32975 #define G_QUIESCETYPE3(x) (((x) >> S_QUIESCETYPE3) & M_QUIESCETYPE3)
32984 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
32985 #define F_TIMERENABLED    V_TIMERENABLED(1U)
32988 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
32989 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
32993 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
32994 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
32998 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
32999 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
33006 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
33007 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
33011 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
33012 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
33018 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
33019 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
33023 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
33024 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
33029 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
33030 #define F_TXDROPMODECH3    V_TXDROPMODECH3(1U)
33033 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
33034 #define F_TXDROPMODECH2    V_TXDROPMODECH2(1U)
33036 #define S_TXDROPMODECH1    1
33037 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
33038 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
33041 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
33042 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
33048 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
33049 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
33053 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
33054 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
33058 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
33059 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
33063 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
33064 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
33068 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
33069 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
33073 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
33074 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
33078 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
33079 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
33083 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
33084 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
33092 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
33093 #define F_PLDRXCSUMVALID1    V_PLDRXCSUMVALID1(1U)
33096 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
33097 #define F_PLDRXZEROPSRDY1    V_PLDRXZEROPSRDY1(1U)
33100 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
33101 #define F_PLDRXVALID1    V_PLDRXVALID1(1U)
33104 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
33105 #define F_TCPRXVALID1    V_TCPRXVALID1(1U)
33108 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
33109 #define F_IPRXVALID1    V_IPRXVALID1(1U)
33112 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
33113 #define F_ETHRXVALID1    V_ETHRXVALID1(1U)
33116 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
33117 #define F_CPLRXVALID1    V_CPLRXVALID1(1U)
33120 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
33121 #define F_FSTATIC1    V_FSTATIC1(1U)
33124 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
33125 #define F_ERRORSRDY1    V_ERRORSRDY1(1U)
33128 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
33129 #define F_PLDTXSRDY1    V_PLDTXSRDY1(1U)
33132 #define V_DBVLD1(x) ((x) << S_DBVLD1)
33133 #define F_DBVLD1    V_DBVLD1(1U)
33136 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
33137 #define F_PLDTXVALID1    V_PLDTXVALID1(1U)
33140 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
33141 #define F_ETXVALID1    V_ETXVALID1(1U)
33144 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
33145 #define F_ETXFULL1    V_ETXFULL1(1U)
33148 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
33149 #define F_ERXVALID1    V_ERXVALID1(1U)
33152 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
33153 #define F_ERXFULL1    V_ERXFULL1(1U)
33156 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
33157 #define F_PLDRXCSUMVALID0    V_PLDRXCSUMVALID0(1U)
33160 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
33161 #define F_PLDRXZEROPSRDY0    V_PLDRXZEROPSRDY0(1U)
33164 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
33165 #define F_PLDRXVALID0    V_PLDRXVALID0(1U)
33168 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
33169 #define F_TCPRXVALID0    V_TCPRXVALID0(1U)
33172 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
33173 #define F_IPRXVALID0    V_IPRXVALID0(1U)
33176 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
33177 #define F_ETHRXVALID0    V_ETHRXVALID0(1U)
33180 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
33181 #define F_CPLRXVALID0    V_CPLRXVALID0(1U)
33184 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
33185 #define F_FSTATIC0    V_FSTATIC0(1U)
33188 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
33189 #define F_ERRORSRDY0    V_ERRORSRDY0(1U)
33192 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
33193 #define F_PLDTXSRDY0    V_PLDTXSRDY0(1U)
33196 #define V_DBVLD0(x) ((x) << S_DBVLD0)
33197 #define F_DBVLD0    V_DBVLD0(1U)
33200 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
33201 #define F_PLDTXVALID0    V_PLDTXVALID0(1U)
33204 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
33205 #define F_ETXVALID0    V_ETXVALID0(1U)
33208 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
33209 #define F_ETXFULL0    V_ETXFULL0(1U)
33211 #define S_ERXVALID0    1
33212 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
33213 #define F_ERXVALID0    V_ERXVALID0(1U)
33216 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
33217 #define F_ERXFULL0    V_ERXFULL0(1U)
33222 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
33223 #define F_PLDRXCSUMVALID3    V_PLDRXCSUMVALID3(1U)
33226 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
33227 #define F_PLDRXZEROPSRDY3    V_PLDRXZEROPSRDY3(1U)
33230 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
33231 #define F_PLDRXVALID3    V_PLDRXVALID3(1U)
33234 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
33235 #define F_TCPRXVALID3    V_TCPRXVALID3(1U)
33238 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
33239 #define F_IPRXVALID3    V_IPRXVALID3(1U)
33242 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
33243 #define F_ETHRXVALID3    V_ETHRXVALID3(1U)
33246 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
33247 #define F_CPLRXVALID3    V_CPLRXVALID3(1U)
33250 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
33251 #define F_FSTATIC3    V_FSTATIC3(1U)
33254 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
33255 #define F_ERRORSRDY3    V_ERRORSRDY3(1U)
33258 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
33259 #define F_PLDTXSRDY3    V_PLDTXSRDY3(1U)
33262 #define V_DBVLD3(x) ((x) << S_DBVLD3)
33263 #define F_DBVLD3    V_DBVLD3(1U)
33266 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
33267 #define F_PLDTXVALID3    V_PLDTXVALID3(1U)
33270 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
33271 #define F_ETXVALID3    V_ETXVALID3(1U)
33274 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
33275 #define F_ETXFULL3    V_ETXFULL3(1U)
33278 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
33279 #define F_ERXVALID3    V_ERXVALID3(1U)
33282 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
33283 #define F_ERXFULL3    V_ERXFULL3(1U)
33286 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
33287 #define F_PLDRXCSUMVALID2    V_PLDRXCSUMVALID2(1U)
33290 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
33291 #define F_PLDRXZEROPSRDY2    V_PLDRXZEROPSRDY2(1U)
33294 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
33295 #define F_PLDRXVALID2    V_PLDRXVALID2(1U)
33298 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
33299 #define F_TCPRXVALID2    V_TCPRXVALID2(1U)
33302 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
33303 #define F_IPRXVALID2    V_IPRXVALID2(1U)
33306 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
33307 #define F_ETHRXVALID2    V_ETHRXVALID2(1U)
33310 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
33311 #define F_CPLRXVALID2    V_CPLRXVALID2(1U)
33314 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
33315 #define F_FSTATIC2    V_FSTATIC2(1U)
33318 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
33319 #define F_ERRORSRDY2    V_ERRORSRDY2(1U)
33322 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
33323 #define F_PLDTXSRDY2    V_PLDTXSRDY2(1U)
33326 #define V_DBVLD2(x) ((x) << S_DBVLD2)
33327 #define F_DBVLD2    V_DBVLD2(1U)
33330 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
33331 #define F_PLDTXVALID2    V_PLDTXVALID2(1U)
33334 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
33335 #define F_ETXVALID2    V_ETXVALID2(1U)
33338 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
33339 #define F_ETXFULL2    V_ETXFULL2(1U)
33341 #define S_ERXVALID2    1
33342 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
33343 #define F_ERXVALID2    V_ERXVALID2(1U)
33346 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
33347 #define F_ERXFULL2    V_ERXFULL2(1U)
33352 #define V_RESRDY(x) ((x) << S_RESRDY)
33353 #define F_RESRDY    V_RESRDY(1U)
33357 #define V_STATE(x) ((x) << S_STATE)
33358 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
33361 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
33362 #define F_FIFOCPL5RXVALID    V_FIFOCPL5RXVALID(1U)
33365 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
33366 #define F_FIFOETHRXVALID    V_FIFOETHRXVALID(1U)
33369 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
33370 #define F_FIFOETHRXSOCP    V_FIFOETHRXSOCP(1U)
33373 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
33374 #define F_FIFOPLDRXZEROP    V_FIFOPLDRXZEROP(1U)
33377 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
33378 #define F_PLDRXVALID    V_PLDRXVALID(1U)
33381 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
33382 #define F_FIFOPLDRXZEROP_SRDY    V_FIFOPLDRXZEROP_SRDY(1U)
33385 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
33386 #define F_FIFOIPRXVALID    V_FIFOIPRXVALID(1U)
33389 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
33390 #define F_FIFOTCPRXVALID    V_FIFOTCPRXVALID(1U)
33393 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
33394 #define F_PLDRXCSUMVALID    V_PLDRXCSUMVALID(1U)
33397 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
33398 #define F_FIFOIPCSUMSRDY    V_FIFOIPCSUMSRDY(1U)
33401 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
33402 #define F_FIFOIPPSEUDOCSUMSRDY    V_FIFOIPPSEUDOCSUMSRDY(1U)
33405 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
33406 #define F_FIFOTCPCSUMSRDY    V_FIFOTCPCSUMSRDY(1U)
33410 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
33411 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
33415 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
33416 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
33420 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
33421 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
33425 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
33426 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
33430 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
33431 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
33435 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
33436 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
33438 #define S_ESTATIC6    1
33439 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
33440 #define F_ESTATIC6    V_ESTATIC6(1U)
33443 #define V_TXFULL(x) ((x) << S_TXFULL)
33444 #define F_TXFULL    V_TXFULL(1U)
33447 #define V_FIFOGRERXVALID(x) ((x) << S_FIFOGRERXVALID)
33448 #define F_FIFOGRERXVALID    V_FIFOGRERXVALID(1U)
33451 #define V_FIFOGRERXREADY(x) ((x) << S_FIFOGRERXREADY)
33452 #define F_FIFOGRERXREADY    V_FIFOGRERXREADY(1U)
33455 #define V_FIFOGRERXSOCP(x) ((x) << S_FIFOGRERXSOCP)
33456 #define F_FIFOGRERXSOCP    V_FIFOGRERXSOCP(1U)
33459 #define V_T6_ESTATIC4(x) ((x) << S_T6_ESTATIC4)
33460 #define F_T6_ESTATIC4    V_T6_ESTATIC4(1U)
33463 #define V_TXFULL_ESIDE0(x) ((x) << S_TXFULL_ESIDE0)
33464 #define F_TXFULL_ESIDE0    V_TXFULL_ESIDE0(1U)
33469 #define V_TXFULL_ESIDE1(x) ((x) << S_TXFULL_ESIDE1)
33470 #define F_TXFULL_ESIDE1    V_TXFULL_ESIDE1(1U)
33476 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
33477 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
33481 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
33482 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
33484 #define S_MAPREAD    1
33485 #define V_MAPREAD(x) ((x) << S_MAPREAD)
33486 #define F_MAPREAD    V_MAPREAD(1U)
33489 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
33490 #define F_MAPWRITE    V_MAPWRITE(1U)
33496 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
33497 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
33502 #define V_TXFULL_ESIDE2(x) ((x) << S_TXFULL_ESIDE2)
33503 #define F_TXFULL_ESIDE2    V_TXFULL_ESIDE2(1U)
33508 #define V_TXFULL_ESIDE3(x) ((x) << S_TXFULL_ESIDE3)
33509 #define F_TXFULL_ESIDE3    V_TXFULL_ESIDE3(1U)
33515 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
33516 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
33520 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
33521 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
33525 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
33526 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
33530 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
33531 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
33535 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
33536 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
33540 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
33541 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
33545 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
33546 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
33550 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
33551 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
33559 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
33560 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
33563 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
33564 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
33567 #define V_MACMATCH(x) ((x) << S_MACMATCH)
33568 #define F_MACMATCH    V_MACMATCH(1U)
33571 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
33572 #define F_ETHERTYPE    V_ETHERTYPE(1U)
33575 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
33576 #define F_PROTOCOL    V_PROTOCOL(1U)
33579 #define V_TOS(x) ((x) << S_TOS)
33580 #define F_TOS    V_TOS(1U)
33583 #define V_VLAN(x) ((x) << S_VLAN)
33584 #define F_VLAN    V_VLAN(1U)
33587 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
33588 #define F_VNIC_ID    V_VNIC_ID(1U)
33590 #define S_PORT    1
33591 #define V_PORT(x) ((x) << S_PORT)
33592 #define F_PORT    V_PORT(1U)
33595 #define V_FCOE(x) ((x) << S_FCOE)
33596 #define F_FCOE    V_FCOE(1U)
33599 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
33600 #define F_FILTERMODE    V_FILTERMODE(1U)
33603 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
33604 #define F_FCOEMASK    V_FCOEMASK(1U)
33607 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
33608 #define F_SRVRSRAM    V_SRVRSRAM(1U)
33611 #define V_T7_FILTERMODE(x) ((x) << S_T7_FILTERMODE)
33612 #define F_T7_FILTERMODE    V_T7_FILTERMODE(1U)
33615 #define V_T7_FCOEMASK(x) ((x) << S_T7_FCOEMASK)
33616 #define F_T7_FCOEMASK    V_T7_FCOEMASK(1U)
33619 #define V_T7_SRVRSRAM(x) ((x) << S_T7_SRVRSRAM)
33620 #define F_T7_SRVRSRAM    V_T7_SRVRSRAM(1U)
33623 #define V_ROCEUDFORCEIPV6(x) ((x) << S_ROCEUDFORCEIPV6)
33624 #define F_ROCEUDFORCEIPV6    V_ROCEUDFORCEIPV6(1U)
33627 #define V_TCPFLAGS8(x) ((x) << S_TCPFLAGS8)
33628 #define F_TCPFLAGS8    V_TCPFLAGS8(1U)
33631 #define V_MACMATCH11(x) ((x) << S_MACMATCH11)
33632 #define F_MACMATCH11    V_MACMATCH11(1U)
33635 #define V_SMACMATCH10(x) ((x) << S_SMACMATCH10)
33636 #define F_SMACMATCH10    V_SMACMATCH10(1U)
33639 #define V_SMACMATCH(x) ((x) << S_SMACMATCH)
33640 #define F_SMACMATCH    V_SMACMATCH(1U)
33643 #define V_TCPFLAGS(x) ((x) << S_TCPFLAGS)
33644 #define F_TCPFLAGS    V_TCPFLAGS(1U)
33647 #define V_SYNONLY(x) ((x) << S_SYNONLY)
33648 #define F_SYNONLY    V_SYNONLY(1U)
33651 #define V_ROCE(x) ((x) << S_ROCE)
33652 #define F_ROCE    V_ROCE(1U)
33655 #define V_T7_FRAGMENTATION(x) ((x) << S_T7_FRAGMENTATION)
33656 #define F_T7_FRAGMENTATION    V_T7_FRAGMENTATION(1U)
33659 #define V_T7_MPSHITTYPE(x) ((x) << S_T7_MPSHITTYPE)
33660 #define F_T7_MPSHITTYPE    V_T7_MPSHITTYPE(1U)
33663 #define V_T7_MACMATCH(x) ((x) << S_T7_MACMATCH)
33664 #define F_T7_MACMATCH    V_T7_MACMATCH(1U)
33667 #define V_T7_ETHERTYPE(x) ((x) << S_T7_ETHERTYPE)
33668 #define F_T7_ETHERTYPE    V_T7_ETHERTYPE(1U)
33671 #define V_T7_PROTOCOL(x) ((x) << S_T7_PROTOCOL)
33672 #define F_T7_PROTOCOL    V_T7_PROTOCOL(1U)
33675 #define V_T7_TOS(x) ((x) << S_T7_TOS)
33676 #define F_T7_TOS    V_T7_TOS(1U)
33679 #define V_T7_VLAN(x) ((x) << S_T7_VLAN)
33680 #define F_T7_VLAN    V_T7_VLAN(1U)
33683 #define V_T7_VNIC_ID(x) ((x) << S_T7_VNIC_ID)
33684 #define F_T7_VNIC_ID    V_T7_VNIC_ID(1U)
33687 #define V_T7_PORT(x) ((x) << S_T7_PORT)
33688 #define F_T7_PORT    V_T7_PORT(1U)
33690 #define S_T7_FCOE    1
33691 #define V_T7_FCOE(x) ((x) << S_T7_FCOE)
33692 #define F_T7_FCOE    V_T7_FCOE(1U)
33695 #define V_IPSECIDX(x) ((x) << S_IPSECIDX)
33696 #define F_IPSECIDX    V_IPSECIDX(1U)
33702 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
33703 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
33706 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
33707 #define F_OPAQUE_RM    V_OPAQUE_RM(1U)
33710 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
33711 #define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)
33714 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
33715 #define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)
33718 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
33719 #define F_FCOE_TARGET    V_FCOE_TARGET(1U)
33722 #define V_VNIC(x) ((x) << S_VNIC)
33723 #define F_VNIC    V_VNIC(1U)
33726 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
33727 #define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)
33730 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
33731 #define F_RM_OVLAN    V_RM_OVLAN(1U)
33734 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
33735 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
33739 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
33740 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
33743 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
33744 #define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
33747 #define V_USE_ENC_IDX(x) ((x) << S_USE_ENC_IDX)
33748 #define F_USE_ENC_IDX    V_USE_ENC_IDX(1U)
33751 #define V_USE_MPS_ECN(x) ((x) << S_USE_MPS_ECN)
33752 #define F_USE_MPS_ECN    V_USE_MPS_ECN(1U)
33755 #define V_USE_MPS_CONG(x) ((x) << S_USE_MPS_CONG)
33756 #define F_USE_MPS_CONG    V_USE_MPS_CONG(1U)
33763 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
33764 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
33769 #define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
33770 #define F_IPV6_UDP_CSUM_COMPAT    V_IPV6_UDP_CSUM_COMPAT(1U)
33773 #define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
33774 #define F_VNTAGPLDENABLE    V_VNTAGPLDENABLE(1U)
33778 #define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
33779 #define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
33783 #define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
33784 #define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
33788 #define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
33789 #define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
33795 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
33796 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
33800 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
33801 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
33805 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
33806 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
33810 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
33811 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
33818 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
33819 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
33823 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
33824 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
33828 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
33829 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
33833 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
33834 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
33838 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
33839 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
33843 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
33844 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
33847 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
33848 #define F_ERRORSRDY    V_ERRORSRDY(1U)
33851 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
33852 #define F_ERRORDRDY    V_ERRORDRDY(1U)
33855 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
33856 #define F_TCPOPSRDY    V_TCPOPSRDY(1U)
33859 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
33860 #define F_TCPOPDRDY    V_TCPOPDRDY(1U)
33863 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
33864 #define F_PLDTXSRDY    V_PLDTXSRDY(1U)
33867 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
33868 #define F_PLDTXDRDY    V_PLDTXDRDY(1U)
33870 #define S_TCPOPTTXVALID    1
33871 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
33872 #define F_TCPOPTTXVALID    V_TCPOPTTXVALID(1U)
33875 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
33876 #define F_TCPOPTTXFULL    V_TCPOPTTXFULL(1U)
33879 #define V_PKTATTRSRDY(x) ((x) << S_PKTATTRSRDY)
33880 #define F_PKTATTRSRDY    V_PKTATTRSRDY(1U)
33883 #define V_PKTATTRDRDY(x) ((x) << S_PKTATTRDRDY)
33884 #define F_PKTATTRDRDY    V_PKTATTRDRDY(1U)
33890 #define V_EALLDONE(x) ((x) << S_EALLDONE)
33891 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
33895 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
33896 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
33900 #define V_EDBDONE(x) ((x) << S_EDBDONE)
33901 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
33905 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
33906 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
33910 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
33911 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
33915 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
33916 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
33920 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
33921 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
33925 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
33926 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
33931 #define V_RXVALID(x) ((x) << S_RXVALID)
33932 #define F_RXVALID    V_RXVALID(1U)
33935 #define V_RXFULL(x) ((x) << S_RXFULL)
33936 #define F_RXFULL    V_RXFULL(1U)
33939 #define V_RXSOCP(x) ((x) << S_RXSOCP)
33940 #define F_RXSOCP    V_RXSOCP(1U)
33943 #define V_RXEOP(x) ((x) << S_RXEOP)
33944 #define F_RXEOP    V_RXEOP(1U)
33947 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
33948 #define F_RXVALID_I    V_RXVALID_I(1U)
33951 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
33952 #define F_RXFULL_I    V_RXFULL_I(1U)
33955 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
33956 #define F_RXSOCP_I    V_RXSOCP_I(1U)
33959 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
33960 #define F_RXEOP_I    V_RXEOP_I(1U)
33963 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
33964 #define F_RXVALID_I2    V_RXVALID_I2(1U)
33967 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
33968 #define F_RXFULL_I2    V_RXFULL_I2(1U)
33971 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
33972 #define F_RXSOCP_I2    V_RXSOCP_I2(1U)
33975 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
33976 #define F_RXEOP_I2    V_RXEOP_I2(1U)
33979 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
33980 #define F_CT_MPA_TXVALID_FIFO    V_CT_MPA_TXVALID_FIFO(1U)
33983 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
33984 #define F_CT_MPA_TXFULL_FIFO    V_CT_MPA_TXFULL_FIFO(1U)
33987 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
33988 #define F_CT_MPA_TXVALID    V_CT_MPA_TXVALID(1U)
33991 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
33992 #define F_CT_MPA_TXFULL    V_CT_MPA_TXFULL(1U)
33995 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
33996 #define F_RXVALID_BUF    V_RXVALID_BUF(1U)
33999 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
34000 #define F_RXFULL_BUF    V_RXFULL_BUF(1U)
34003 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
34004 #define F_PLD_TXVALID    V_PLD_TXVALID(1U)
34007 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
34008 #define F_PLD_TXFULL    V_PLD_TXFULL(1U)
34011 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
34012 #define F_ISS_FIFO_SRDY    V_ISS_FIFO_SRDY(1U)
34015 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
34016 #define F_ISS_FIFO_DRDY    V_ISS_FIFO_DRDY(1U)
34019 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
34020 #define F_CT_TCP_OP_ISS_SRDY    V_CT_TCP_OP_ISS_SRDY(1U)
34023 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
34024 #define F_CT_TCP_OP_ISS_DRDY    V_CT_TCP_OP_ISS_DRDY(1U)
34027 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
34028 #define F_P2CSUMERROR_SRDY    V_P2CSUMERROR_SRDY(1U)
34031 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
34032 #define F_P2CSUMERROR_DRDY    V_P2CSUMERROR_DRDY(1U)
34035 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
34036 #define F_FIFO_ERROR_SRDY    V_FIFO_ERROR_SRDY(1U)
34039 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
34040 #define F_FIFO_ERROR_DRDY    V_FIFO_ERROR_DRDY(1U)
34043 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
34044 #define F_PLD_SRDY    V_PLD_SRDY(1U)
34047 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
34048 #define F_PLD_DRDY    V_PLD_DRDY(1U)
34050 #define S_RX_PKT_ATTR_SRDY    1
34051 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
34052 #define F_RX_PKT_ATTR_SRDY    V_RX_PKT_ATTR_SRDY(1U)
34055 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
34056 #define F_RX_PKT_ATTR_DRDY    V_RX_PKT_ATTR_DRDY(1U)
34059 #define V_RXRUNT(x) ((x) << S_RXRUNT)
34060 #define F_RXRUNT    V_RXRUNT(1U)
34063 #define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
34064 #define F_RXRUNTPARSER    V_RXRUNTPARSER(1U)
34067 #define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
34068 #define F_ERROR_SRDY    V_ERROR_SRDY(1U)
34071 #define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
34072 #define F_ERROR_DRDY    V_ERROR_DRDY(1U)
34081 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
34082 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
34086 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
34087 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
34091 #define V_ETXERROR(x) ((x) << S_ETXERROR)
34092 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
34096 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
34097 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
34101 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
34102 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
34106 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
34107 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
34111 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
34112 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
34116 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
34117 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
34123 #define V_RXDROP3(x) ((x) << S_RXDROP3)
34124 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
34128 #define V_RXDROP2(x) ((x) << S_RXDROP2)
34129 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
34133 #define V_RXDROP1(x) ((x) << S_RXDROP1)
34134 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
34138 #define V_RXDROP0(x) ((x) << S_RXDROP0)
34139 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
34145 #define V_ETXVALID(x) ((x) << S_ETXVALID)
34146 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
34150 #define V_ETXFULL(x) ((x) << S_ETXFULL)
34151 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
34155 #define V_TXERRORCNT(x) ((x) << S_TXERRORCNT)
34156 #define G_TXERRORCNT(x) (((x) >> S_TXERRORCNT) & M_TXERRORCNT)
34163 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
34164 #define F_USE_LOOP_BIT    V_USE_LOOP_BIT(1U)
34168 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
34169 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
34173 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
34174 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
34178 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
34179 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
34184 #define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
34185 #define F_OPT_PARSER_FATAL_CHANNEL0    V_OPT_PARSER_FATAL_CHANNEL0(1U)
34188 #define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
34189 #define F_OPT_PARSER_BUSY_CHANNEL0    V_OPT_PARSER_BUSY_CHANNEL0(1U)
34193 #define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
34194 #define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
34198 #define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
34199 #define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
34202 #define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
34203 #define F_OPT_PARSER_FATAL_CHANNEL1    V_OPT_PARSER_FATAL_CHANNEL1(1U)
34206 #define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
34207 #define F_OPT_PARSER_BUSY_CHANNEL1    V_OPT_PARSER_BUSY_CHANNEL1(1U)
34211 #define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
34212 #define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
34216 #define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
34217 #define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
34220 #define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
34221 #define F_OPT_PARSER_FATAL_CHANNEL2    V_OPT_PARSER_FATAL_CHANNEL2(1U)
34224 #define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
34225 #define F_OPT_PARSER_BUSY_CHANNEL2    V_OPT_PARSER_BUSY_CHANNEL2(1U)
34229 #define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
34230 #define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
34234 #define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
34235 #define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
34238 #define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
34239 #define F_OPT_PARSER_FATAL_CHANNEL3    V_OPT_PARSER_FATAL_CHANNEL3(1U)
34242 #define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
34243 #define F_OPT_PARSER_BUSY_CHANNEL3    V_OPT_PARSER_BUSY_CHANNEL3(1U)
34247 #define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
34248 #define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
34252 #define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
34253 #define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
34258 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
34259 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0    V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
34263 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
34264 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
34267 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
34268 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1    V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
34272 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
34273 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
34276 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
34277 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2    V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
34281 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
34282 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
34285 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
34286 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3    V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
34290 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
34291 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
34297 #define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
34298 #define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
34302 #define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
34303 #define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
34307 #define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
34308 #define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
34312 #define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
34313 #define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
34319 #define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
34320 #define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
34324 #define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
34325 #define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
34329 #define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
34330 #define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
34334 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
34335 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
34344 #define V_VNI_EN(x) ((x) << S_VNI_EN)
34345 #define F_VNI_EN    V_VNI_EN(1U)
34348 #define V_ENC_RX_EN(x) ((x) << S_ENC_RX_EN)
34349 #define F_ENC_RX_EN    V_ENC_RX_EN(1U)
34352 #define V_TNL_LKP_INNER_SEL(x) ((x) << S_TNL_LKP_INNER_SEL)
34353 #define F_TNL_LKP_INNER_SEL    V_TNL_LKP_INNER_SEL(1U)
34357 #define V_ROCEV2UDPPORT(x) ((x) << S_ROCEV2UDPPORT)
34358 #define G_ROCEV2UDPPORT(x) (((x) >> S_ROCEV2UDPPORT) & M_ROCEV2UDPPORT)
34361 #define V_IPSECTUNETHTRANSEN(x) ((x) << S_IPSECTUNETHTRANSEN)
34362 #define F_IPSECTUNETHTRANSEN    V_IPSECTUNETHTRANSEN(1U)
34365 #define V_ROCEV2ZEROUDP6CSUM(x) ((x) << S_ROCEV2ZEROUDP6CSUM)
34366 #define F_ROCEV2ZEROUDP6CSUM    V_ROCEV2ZEROUDP6CSUM(1U)
34369 #define V_ROCEV2PROCEN(x) ((x) << S_ROCEV2PROCEN)
34370 #define F_ROCEV2PROCEN    V_ROCEV2PROCEN(1U)
34376 #define V_ROCEV2UDPPORT2(x) ((x) << S_ROCEV2UDPPORT2)
34377 #define G_ROCEV2UDPPORT2(x) (((x) >> S_ROCEV2UDPPORT2) & M_ROCEV2UDPPORT2)
34381 #define V_ROCEV2UDPPORT1(x) ((x) << S_ROCEV2UDPPORT1)
34382 #define G_ROCEV2UDPPORT1(x) (((x) >> S_ROCEV2UDPPORT1) & M_ROCEV2UDPPORT1)
34388 #define V_ROCEV2UDPPORT4(x) ((x) << S_ROCEV2UDPPORT4)
34389 #define G_ROCEV2UDPPORT4(x) (((x) >> S_ROCEV2UDPPORT4) & M_ROCEV2UDPPORT4)
34393 #define V_ROCEV2UDPPORT3(x) ((x) << S_ROCEV2UDPPORT3)
34394 #define G_ROCEV2UDPPORT3(x) (((x) >> S_ROCEV2UDPPORT3) & M_ROCEV2UDPPORT3)
34400 #define V_ROCEV2CRCIGN(x) ((x) << S_ROCEV2CRCIGN)
34401 #define G_ROCEV2CRCIGN(x) (((x) >> S_ROCEV2CRCIGN) & M_ROCEV2CRCIGN)
34409 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
34410 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
34414 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
34415 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
34419 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
34420 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
34424 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
34425 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
34429 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
34430 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
34434 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
34435 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
34439 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
34440 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
34444 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
34445 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
34454 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
34455 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
34459 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
34460 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
34464 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
34465 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
34469 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
34470 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
34474 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
34475 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
34479 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
34480 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
34484 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
34485 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
34489 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
34490 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
34498 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
34499 #define F_PLD_RXZEROP_SRDY1    V_PLD_RXZEROP_SRDY1(1U)
34502 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
34503 #define F_PLD_RXZEROP_DRDY1    V_PLD_RXZEROP_DRDY1(1U)
34506 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
34507 #define F_PLD_TXZEROP_SRDY1    V_PLD_TXZEROP_SRDY1(1U)
34510 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
34511 #define F_PLD_TXZEROP_DRDY1    V_PLD_TXZEROP_DRDY1(1U)
34514 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
34515 #define F_PLD_TX_SRDY1    V_PLD_TX_SRDY1(1U)
34518 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
34519 #define F_PLD_TX_DRDY1    V_PLD_TX_DRDY1(1U)
34522 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
34523 #define F_ERROR_SRDY1    V_ERROR_SRDY1(1U)
34526 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
34527 #define F_ERROR_DRDY1    V_ERROR_DRDY1(1U)
34530 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
34531 #define F_DB_VLD1    V_DB_VLD1(1U)
34534 #define V_DB_GT1(x) ((x) << S_DB_GT1)
34535 #define F_DB_GT1    V_DB_GT1(1U)
34538 #define V_TXVALID1(x) ((x) << S_TXVALID1)
34539 #define F_TXVALID1    V_TXVALID1(1U)
34542 #define V_TXFULL1(x) ((x) << S_TXFULL1)
34543 #define F_TXFULL1    V_TXFULL1(1U)
34546 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
34547 #define F_PLD_TXVALID1    V_PLD_TXVALID1(1U)
34550 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
34551 #define F_PLD_TXFULL1    V_PLD_TXFULL1(1U)
34554 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
34555 #define F_CPL5_TXVALID1    V_CPL5_TXVALID1(1U)
34558 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
34559 #define F_CPL5_TXFULL1    V_CPL5_TXFULL1(1U)
34562 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
34563 #define F_PLD_RXZEROP_SRDY0    V_PLD_RXZEROP_SRDY0(1U)
34566 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
34567 #define F_PLD_RXZEROP_DRDY0    V_PLD_RXZEROP_DRDY0(1U)
34570 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
34571 #define F_PLD_TXZEROP_SRDY0    V_PLD_TXZEROP_SRDY0(1U)
34574 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
34575 #define F_PLD_TXZEROP_DRDY0    V_PLD_TXZEROP_DRDY0(1U)
34578 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
34579 #define F_PLD_TX_SRDY0    V_PLD_TX_SRDY0(1U)
34582 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
34583 #define F_PLD_TX_DRDY0    V_PLD_TX_DRDY0(1U)
34586 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
34587 #define F_ERROR_SRDY0    V_ERROR_SRDY0(1U)
34590 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
34591 #define F_ERROR_DRDY0    V_ERROR_DRDY0(1U)
34594 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
34595 #define F_DB_VLD0    V_DB_VLD0(1U)
34598 #define V_DB_GT0(x) ((x) << S_DB_GT0)
34599 #define F_DB_GT0    V_DB_GT0(1U)
34602 #define V_TXVALID0(x) ((x) << S_TXVALID0)
34603 #define F_TXVALID0    V_TXVALID0(1U)
34606 #define V_TXFULL0(x) ((x) << S_TXFULL0)
34607 #define F_TXFULL0    V_TXFULL0(1U)
34610 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
34611 #define F_PLD_TXVALID0    V_PLD_TXVALID0(1U)
34614 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
34615 #define F_PLD_TXFULL0    V_PLD_TXFULL0(1U)
34617 #define S_CPL5_TXVALID0    1
34618 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
34619 #define F_CPL5_TXVALID0    V_CPL5_TXVALID0(1U)
34622 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
34623 #define F_CPL5_TXFULL0    V_CPL5_TXFULL0(1U)
34628 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
34629 #define F_PLD_RXZEROP_SRDY3    V_PLD_RXZEROP_SRDY3(1U)
34632 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
34633 #define F_PLD_RXZEROP_DRDY3    V_PLD_RXZEROP_DRDY3(1U)
34636 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
34637 #define F_PLD_TXZEROP_SRDY3    V_PLD_TXZEROP_SRDY3(1U)
34640 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
34641 #define F_PLD_TXZEROP_DRDY3    V_PLD_TXZEROP_DRDY3(1U)
34644 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
34645 #define F_PLD_TX_SRDY3    V_PLD_TX_SRDY3(1U)
34648 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
34649 #define F_PLD_TX_DRDY3    V_PLD_TX_DRDY3(1U)
34652 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
34653 #define F_ERROR_SRDY3    V_ERROR_SRDY3(1U)
34656 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
34657 #define F_ERROR_DRDY3    V_ERROR_DRDY3(1U)
34660 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
34661 #define F_DB_VLD3    V_DB_VLD3(1U)
34664 #define V_DB_GT3(x) ((x) << S_DB_GT3)
34665 #define F_DB_GT3    V_DB_GT3(1U)
34668 #define V_TXVALID3(x) ((x) << S_TXVALID3)
34669 #define F_TXVALID3    V_TXVALID3(1U)
34672 #define V_TXFULL3(x) ((x) << S_TXFULL3)
34673 #define F_TXFULL3    V_TXFULL3(1U)
34676 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
34677 #define F_PLD_TXVALID3    V_PLD_TXVALID3(1U)
34680 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
34681 #define F_PLD_TXFULL3    V_PLD_TXFULL3(1U)
34684 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
34685 #define F_CPL5_TXVALID3    V_CPL5_TXVALID3(1U)
34688 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
34689 #define F_CPL5_TXFULL3    V_CPL5_TXFULL3(1U)
34692 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
34693 #define F_PLD_RXZEROP_SRDY2    V_PLD_RXZEROP_SRDY2(1U)
34696 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
34697 #define F_PLD_RXZEROP_DRDY2    V_PLD_RXZEROP_DRDY2(1U)
34700 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
34701 #define F_PLD_TXZEROP_SRDY2    V_PLD_TXZEROP_SRDY2(1U)
34704 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
34705 #define F_PLD_TXZEROP_DRDY2    V_PLD_TXZEROP_DRDY2(1U)
34708 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
34709 #define F_PLD_TX_SRDY2    V_PLD_TX_SRDY2(1U)
34712 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
34713 #define F_PLD_TX_DRDY2    V_PLD_TX_DRDY2(1U)
34716 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
34717 #define F_ERROR_SRDY2    V_ERROR_SRDY2(1U)
34720 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
34721 #define F_ERROR_DRDY2    V_ERROR_DRDY2(1U)
34724 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
34725 #define F_DB_VLD2    V_DB_VLD2(1U)
34728 #define V_DB_GT2(x) ((x) << S_DB_GT2)
34729 #define F_DB_GT2    V_DB_GT2(1U)
34732 #define V_TXVALID2(x) ((x) << S_TXVALID2)
34733 #define F_TXVALID2    V_TXVALID2(1U)
34736 #define V_TXFULL2(x) ((x) << S_TXFULL2)
34737 #define F_TXFULL2    V_TXFULL2(1U)
34740 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
34741 #define F_PLD_TXVALID2    V_PLD_TXVALID2(1U)
34744 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
34745 #define F_PLD_TXFULL2    V_PLD_TXFULL2(1U)
34747 #define S_CPL5_TXVALID2    1
34748 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
34749 #define F_CPL5_TXVALID2    V_CPL5_TXVALID2(1U)
34752 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
34753 #define F_CPL5_TXFULL2    V_CPL5_TXFULL2(1U)
34758 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
34759 #define F_CPL5RXVALID    V_CPL5RXVALID(1U)
34762 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
34763 #define F_CSTATIC1    V_CSTATIC1(1U)
34766 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
34767 #define F_CSTATIC2    V_CSTATIC2(1U)
34770 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
34771 #define F_PLD_RXZEROP    V_PLD_RXZEROP(1U)
34774 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
34775 #define F_DDP_IN_PROGRESS    V_DDP_IN_PROGRESS(1U)
34778 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
34779 #define F_PLD_RXZEROP_SRDY    V_PLD_RXZEROP_SRDY(1U)
34782 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
34783 #define F_CSTATIC3    V_CSTATIC3(1U)
34786 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
34787 #define F_DDP_DRDY    V_DDP_DRDY(1U)
34791 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
34792 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
34795 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
34796 #define F_DDP_SRDY    V_DDP_SRDY(1U)
34800 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
34801 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
34805 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
34806 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
34810 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
34811 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
34813 #define S_CMD_SEL    1
34814 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
34815 #define F_CMD_SEL    V_CMD_SEL(1U)
34818 #define V_T5_TXFULL(x) ((x) << S_T5_TXFULL)
34819 #define F_T5_TXFULL    V_T5_TXFULL(1U)
34822 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
34823 #define F_CPL5RXFULL    V_CPL5RXFULL(1U)
34826 #define V_T5_PLD_RXZEROP_SRDY(x) ((x) << S_T5_PLD_RXZEROP_SRDY)
34827 #define F_T5_PLD_RXZEROP_SRDY    V_T5_PLD_RXZEROP_SRDY(1U)
34830 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
34831 #define F_PLD2XRXVALID    V_PLD2XRXVALID(1U)
34834 #define V_T5_DDP_SRDY(x) ((x) << S_T5_DDP_SRDY)
34835 #define F_T5_DDP_SRDY    V_T5_DDP_SRDY(1U)
34838 #define V_T5_DDP_DRDY(x) ((x) << S_T5_DDP_DRDY)
34839 #define F_T5_DDP_DRDY    V_T5_DDP_DRDY(1U)
34843 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
34844 #define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
34848 #define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
34849 #define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
34853 #define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
34854 #define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
34858 #define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
34859 #define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
34862 #define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
34863 #define F_TXFRMERR2    V_TXFRMERR2(1U)
34866 #define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
34867 #define F_TXFRMERR1    V_TXFRMERR1(1U)
34869 #define S_TXVALID2X    1
34870 #define V_TXVALID2X(x) ((x) << S_TXVALID2X)
34871 #define F_TXVALID2X    V_TXVALID2X(1U)
34874 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
34875 #define F_TXFULL2X    V_TXFULL2X(1U)
34882 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
34883 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
34887 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
34888 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
34892 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
34893 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
34897 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
34898 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
34902 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
34903 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
34907 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
34908 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
34912 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
34913 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
34917 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
34918 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
34925 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
34926 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
34930 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
34931 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
34935 #define V_CTXERROR(x) ((x) << S_CTXERROR)
34936 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
34940 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
34941 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
34945 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
34946 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
34950 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
34951 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
34955 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
34956 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
34962 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
34963 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
34967 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
34968 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
34972 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
34973 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
34977 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
34978 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
34982 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
34983 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
34987 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
34988 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
34992 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
34993 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
34997 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
34998 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
35001 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
35002 #define F_TRC_RXVALID    V_TRC_RXVALID(1U)
35005 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
35006 #define F_TRC_RXFULL    V_TRC_RXFULL(1U)
35009 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
35010 #define F_CPL5_TXVALID    V_CPL5_TXVALID(1U)
35013 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
35014 #define F_CPL5_TXFULL    V_CPL5_TXFULL(1U)
35018 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
35019 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
35023 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
35024 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
35030 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
35031 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
35035 #define V_CH1LOW(x) ((x) << S_CH1LOW)
35036 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
35040 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
35041 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
35045 #define V_CH0LOW(x) ((x) << S_CH0LOW)
35046 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
35052 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
35053 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
35057 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
35058 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
35062 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
35063 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
35068 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
35069 #define F_WRITEZEROEN    V_WRITEZEROEN(1U)
35073 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
35074 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
35077 #define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
35078 #define F_STARTSKIPPLD    V_STARTSKIPPLD(1U)
35081 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
35082 #define F_ATOMICCMDEN    V_ATOMICCMDEN(1U)
35085 #define V_ISCSICMDMODE(x) ((x) << S_ISCSICMDMODE)
35086 #define F_ISCSICMDMODE    V_ISCSICMDMODE(1U)
35089 #define V_NVMTOPUPDEN(x) ((x) << S_NVMTOPUPDEN)
35090 #define F_NVMTOPUPDEN    V_NVMTOPUPDEN(1U)
35093 #define V_NOPDIS(x) ((x) << S_NOPDIS)
35094 #define F_NOPDIS    V_NOPDIS(1U)
35097 #define V_IWARPINVREQEN(x) ((x) << S_IWARPINVREQEN)
35098 #define F_IWARPINVREQEN    V_IWARPINVREQEN(1U)
35101 #define V_ROCEINVREQEN(x) ((x) << S_ROCEINVREQEN)
35102 #define F_ROCEINVREQEN    V_ROCEINVREQEN(1U)
35105 #define V_ROCESRQFWEN(x) ((x) << S_ROCESRQFWEN)
35106 #define F_ROCESRQFWEN    V_ROCESRQFWEN(1U)
35110 #define V_T7_WRITEZEROOP(x) ((x) << S_T7_WRITEZEROOP)
35111 #define G_T7_WRITEZEROOP(x) (((x) >> S_T7_WRITEZEROOP) & M_T7_WRITEZEROOP)
35114 #define V_IWARPEXTMODE(x) ((x) << S_IWARPEXTMODE)
35115 #define F_IWARPEXTMODE    V_IWARPEXTMODE(1U)
35118 #define V_IWARPINVFWEN(x) ((x) << S_IWARPINVFWEN)
35119 #define F_IWARPINVFWEN    V_IWARPINVFWEN(1U)
35122 #define V_IWARPSRQFWEN(x) ((x) << S_IWARPSRQFWEN)
35123 #define F_IWARPSRQFWEN    V_IWARPSRQFWEN(1U)
35126 #define V_T7_STARTSKIPPLD(x) ((x) << S_T7_STARTSKIPPLD)
35127 #define F_T7_STARTSKIPPLD    V_T7_STARTSKIPPLD(1U)
35130 #define V_NVMTFLIMMEN(x) ((x) << S_NVMTFLIMMEN)
35131 #define F_NVMTFLIMMEN    V_NVMTFLIMMEN(1U)
35133 #define S_NVMTOPCTRLEN    1
35134 #define V_NVMTOPCTRLEN(x) ((x) << S_NVMTOPCTRLEN)
35135 #define F_NVMTOPCTRLEN    V_NVMTOPCTRLEN(1U)
35138 #define V_T7_WRITEZEROEN(x) ((x) << S_T7_WRITEZEROEN)
35139 #define F_T7_WRITEZEROEN    V_T7_WRITEZEROEN(1U)
35144 #define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
35145 #define F_GATECHNTX3    V_GATECHNTX3(1U)
35148 #define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
35149 #define F_GATECHNTX2    V_GATECHNTX2(1U)
35152 #define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
35153 #define F_GATECHNTX1    V_GATECHNTX1(1U)
35156 #define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
35157 #define F_GATECHNTX0    V_GATECHNTX0(1U)
35160 #define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
35161 #define F_GATECHNRX1    V_GATECHNRX1(1U)
35164 #define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
35165 #define F_GATECHNRX0    V_GATECHNRX0(1U)
35168 #define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
35169 #define F_SLEEPRDYUTRN    V_SLEEPRDYUTRN(1U)
35172 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
35173 #define F_SLEEPREQUTRN    V_SLEEPREQUTRN(1U)
35176 #define V_GATECHNRX3(x) ((x) << S_GATECHNRX3)
35177 #define F_GATECHNRX3    V_GATECHNRX3(1U)
35180 #define V_GATECHNRX2(x) ((x) << S_GATECHNRX2)
35181 #define F_GATECHNRX2    V_GATECHNRX2(1U)
35184 #define V_T7_GATECHNRX1(x) ((x) << S_T7_GATECHNRX1)
35185 #define F_T7_GATECHNRX1    V_T7_GATECHNRX1(1U)
35188 #define V_T7_GATECHNRX0(x) ((x) << S_T7_GATECHNRX0)
35189 #define F_T7_GATECHNRX0    V_T7_GATECHNRX0(1U)
35192 #define V_T7_SLEEPRDYUTRN(x) ((x) << S_T7_SLEEPRDYUTRN)
35193 #define F_T7_SLEEPRDYUTRN    V_T7_SLEEPRDYUTRN(1U)
35197 #define S_TRCRR    1
35198 #define V_TRCRR(x) ((x) << S_TRCRR)
35199 #define F_TRCRR    V_TRCRR(1U)
35202 #define V_TRCCH(x) ((x) << S_TRCCH)
35203 #define F_TRCCH    V_TRCCH(1U)
35206 #define V_DEBUGPG(x) ((x) << S_DEBUGPG)
35207 #define F_DEBUGPG    V_DEBUGPG(1U)
35210 #define V_T7_TRCRR(x) ((x) << S_T7_TRCRR)
35211 #define F_T7_TRCRR    V_T7_TRCRR(1U)
35215 #define V_T7_TRCCH(x) ((x) << S_T7_TRCCH)
35216 #define G_T7_TRCCH(x) (((x) >> S_T7_TRCCH) & M_T7_TRCCH)
35222 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
35223 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
35229 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
35230 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
35234 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
35235 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
35239 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
35240 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
35244 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
35245 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
35248 #define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
35249 #define F_C4TUPBUSY3    V_C4TUPBUSY3(1U)
35252 #define V_CDBVALID3(x) ((x) << S_CDBVALID3)
35253 #define F_CDBVALID3    V_CDBVALID3(1U)
35256 #define V_CRXVALID3(x) ((x) << S_CRXVALID3)
35257 #define F_CRXVALID3    V_CRXVALID3(1U)
35260 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
35261 #define F_CRXFULL3    V_CRXFULL3(1U)
35265 #define V_T5_CPRSSTATE3(x) ((x) << S_T5_CPRSSTATE3)
35266 #define G_T5_CPRSSTATE3(x) (((x) >> S_T5_CPRSSTATE3) & M_T5_CPRSSTATE3)
35269 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
35270 #define F_C4TUPBUSY2    V_C4TUPBUSY2(1U)
35273 #define V_CDBVALID2(x) ((x) << S_CDBVALID2)
35274 #define F_CDBVALID2    V_CDBVALID2(1U)
35277 #define V_CRXVALID2(x) ((x) << S_CRXVALID2)
35278 #define F_CRXVALID2    V_CRXVALID2(1U)
35281 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
35282 #define F_CRXFULL2    V_CRXFULL2(1U)
35286 #define V_T5_CPRSSTATE2(x) ((x) << S_T5_CPRSSTATE2)
35287 #define G_T5_CPRSSTATE2(x) (((x) >> S_T5_CPRSSTATE2) & M_T5_CPRSSTATE2)
35290 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
35291 #define F_C4TUPBUSY1    V_C4TUPBUSY1(1U)
35294 #define V_CDBVALID1(x) ((x) << S_CDBVALID1)
35295 #define F_CDBVALID1    V_CDBVALID1(1U)
35298 #define V_CRXVALID1(x) ((x) << S_CRXVALID1)
35299 #define F_CRXVALID1    V_CRXVALID1(1U)
35302 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
35303 #define F_CRXFULL1    V_CRXFULL1(1U)
35307 #define V_T5_CPRSSTATE1(x) ((x) << S_T5_CPRSSTATE1)
35308 #define G_T5_CPRSSTATE1(x) (((x) >> S_T5_CPRSSTATE1) & M_T5_CPRSSTATE1)
35311 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
35312 #define F_C4TUPBUSY0    V_C4TUPBUSY0(1U)
35315 #define V_CDBVALID0(x) ((x) << S_CDBVALID0)
35316 #define F_CDBVALID0    V_CDBVALID0(1U)
35319 #define V_CRXVALID0(x) ((x) << S_CRXVALID0)
35320 #define F_CRXVALID0    V_CRXVALID0(1U)
35323 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
35324 #define F_CRXFULL0    V_CRXFULL0(1U)
35328 #define V_T5_CPRSSTATE0(x) ((x) << S_T5_CPRSSTATE0)
35329 #define G_T5_CPRSSTATE0(x) (((x) >> S_T5_CPRSSTATE0) & M_T5_CPRSSTATE0)
35335 #define V_CALLDONE(x) ((x) << S_CALLDONE)
35336 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
35340 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
35341 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
35345 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
35346 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
35350 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
35351 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
35355 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
35356 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
35360 #define V_CDBDONE(x) ((x) << S_CDBDONE)
35361 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
35365 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
35366 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
35370 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
35371 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
35375 #define V_CARBVALID(x) ((x) << S_CARBVALID)
35376 #define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
35380 #define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
35381 #define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
35385 #define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
35386 #define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
35391 #define V_CPLVALID3(x) ((x) << S_CPLVALID3)
35392 #define F_CPLVALID3    V_CPLVALID3(1U)
35395 #define V_PLDVALID3(x) ((x) << S_PLDVALID3)
35396 #define F_PLDVALID3    V_PLDVALID3(1U)
35399 #define V_CRCVALID3(x) ((x) << S_CRCVALID3)
35400 #define F_CRCVALID3    V_CRCVALID3(1U)
35403 #define V_ISSVALID3(x) ((x) << S_ISSVALID3)
35404 #define F_ISSVALID3    V_ISSVALID3(1U)
35407 #define V_DBVALID3(x) ((x) << S_DBVALID3)
35408 #define F_DBVALID3    V_DBVALID3(1U)
35411 #define V_CHKVALID3(x) ((x) << S_CHKVALID3)
35412 #define F_CHKVALID3    V_CHKVALID3(1U)
35415 #define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
35416 #define F_ZRPVALID3    V_ZRPVALID3(1U)
35419 #define V_ERRVALID3(x) ((x) << S_ERRVALID3)
35420 #define F_ERRVALID3    V_ERRVALID3(1U)
35423 #define V_CPLVALID2(x) ((x) << S_CPLVALID2)
35424 #define F_CPLVALID2    V_CPLVALID2(1U)
35427 #define V_PLDVALID2(x) ((x) << S_PLDVALID2)
35428 #define F_PLDVALID2    V_PLDVALID2(1U)
35431 #define V_CRCVALID2(x) ((x) << S_CRCVALID2)
35432 #define F_CRCVALID2    V_CRCVALID2(1U)
35435 #define V_ISSVALID2(x) ((x) << S_ISSVALID2)
35436 #define F_ISSVALID2    V_ISSVALID2(1U)
35439 #define V_DBVALID2(x) ((x) << S_DBVALID2)
35440 #define F_DBVALID2    V_DBVALID2(1U)
35443 #define V_CHKVALID2(x) ((x) << S_CHKVALID2)
35444 #define F_CHKVALID2    V_CHKVALID2(1U)
35447 #define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
35448 #define F_ZRPVALID2    V_ZRPVALID2(1U)
35451 #define V_ERRVALID2(x) ((x) << S_ERRVALID2)
35452 #define F_ERRVALID2    V_ERRVALID2(1U)
35455 #define V_CPLVALID1(x) ((x) << S_CPLVALID1)
35456 #define F_CPLVALID1    V_CPLVALID1(1U)
35459 #define V_PLDVALID1(x) ((x) << S_PLDVALID1)
35460 #define F_PLDVALID1    V_PLDVALID1(1U)
35463 #define V_CRCVALID1(x) ((x) << S_CRCVALID1)
35464 #define F_CRCVALID1    V_CRCVALID1(1U)
35467 #define V_ISSVALID1(x) ((x) << S_ISSVALID1)
35468 #define F_ISSVALID1    V_ISSVALID1(1U)
35471 #define V_DBVALID1(x) ((x) << S_DBVALID1)
35472 #define F_DBVALID1    V_DBVALID1(1U)
35475 #define V_CHKVALID1(x) ((x) << S_CHKVALID1)
35476 #define F_CHKVALID1    V_CHKVALID1(1U)
35479 #define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
35480 #define F_ZRPVALID1    V_ZRPVALID1(1U)
35483 #define V_ERRVALID1(x) ((x) << S_ERRVALID1)
35484 #define F_ERRVALID1    V_ERRVALID1(1U)
35487 #define V_CPLVALID0(x) ((x) << S_CPLVALID0)
35488 #define F_CPLVALID0    V_CPLVALID0(1U)
35491 #define V_PLDVALID0(x) ((x) << S_PLDVALID0)
35492 #define F_PLDVALID0    V_PLDVALID0(1U)
35495 #define V_CRCVALID0(x) ((x) << S_CRCVALID0)
35496 #define F_CRCVALID0    V_CRCVALID0(1U)
35499 #define V_ISSVALID0(x) ((x) << S_ISSVALID0)
35500 #define F_ISSVALID0    V_ISSVALID0(1U)
35503 #define V_DBVALID0(x) ((x) << S_DBVALID0)
35504 #define F_DBVALID0    V_DBVALID0(1U)
35507 #define V_CHKVALID0(x) ((x) << S_CHKVALID0)
35508 #define F_CHKVALID0    V_CHKVALID0(1U)
35510 #define S_ZRPVALID0    1
35511 #define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
35512 #define F_ZRPVALID0    V_ZRPVALID0(1U)
35515 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
35516 #define F_ERRVALID0    V_ERRVALID0(1U)
35522 #define V_TRCSOPCNT(x) ((x) << S_TRCSOPCNT)
35523 #define G_TRCSOPCNT(x) (((x) >> S_TRCSOPCNT) & M_TRCSOPCNT)
35527 #define V_TRCEOPCNT(x) ((x) << S_TRCEOPCNT)
35528 #define G_TRCEOPCNT(x) (((x) >> S_TRCEOPCNT) & M_TRCEOPCNT)
35532 #define V_TRCFLTHIT(x) ((x) << S_TRCFLTHIT)
35533 #define G_TRCFLTHIT(x) (((x) >> S_TRCFLTHIT) & M_TRCFLTHIT)
35537 #define V_TRCRNTPKT(x) ((x) << S_TRCRNTPKT)
35538 #define G_TRCRNTPKT(x) (((x) >> S_TRCRNTPKT) & M_TRCRNTPKT)
35542 #define V_TRCPKTLEN(x) ((x) << S_TRCPKTLEN)
35543 #define G_TRCPKTLEN(x) (((x) >> S_TRCPKTLEN) & M_TRCPKTLEN)
35550 #define V_ETHTYPEQINQ(x) ((x) << S_ETHTYPEQINQ)
35551 #define G_ETHTYPEQINQ(x) (((x) >> S_ETHTYPEQINQ) & M_ETHTYPEQINQ)
35555 #define V_ETHTYPEVLAN(x) ((x) << S_ETHTYPEVLAN)
35556 #define G_ETHTYPEVLAN(x) (((x) >> S_ETHTYPEVLAN) & M_ETHTYPEVLAN)
35566 #define V_CH3HIGH(x) ((x) << S_CH3HIGH)
35567 #define G_CH3HIGH(x) (((x) >> S_CH3HIGH) & M_CH3HIGH)
35571 #define V_CH3LOW(x) ((x) << S_CH3LOW)
35572 #define G_CH3LOW(x) (((x) >> S_CH3LOW) & M_CH3LOW)
35576 #define V_CH2HIGH(x) ((x) << S_CH2HIGH)
35577 #define G_CH2HIGH(x) (((x) >> S_CH2HIGH) & M_CH2HIGH)
35581 #define V_CH2LOW(x) ((x) << S_CH2LOW)
35582 #define G_CH2LOW(x) (((x) >> S_CH2LOW) & M_CH2LOW)
35589 #define V_DEFOPCTRL(x) ((x) << S_DEFOPCTRL)
35590 #define G_DEFOPCTRL(x) (((x) >> S_DEFOPCTRL) & M_DEFOPCTRL)
35594 #define V_NVMTOPCTRL(x) ((x) << S_NVMTOPCTRL)
35595 #define G_NVMTOPCTRL(x) (((x) >> S_NVMTOPCTRL) & M_NVMTOPCTRL)
35600 #define V_T7_OR_EN(x) ((x) << S_T7_OR_EN)
35601 #define F_T7_OR_EN    V_T7_OR_EN(1U)
35604 #define V_T7_HI(x) ((x) << S_T7_HI)
35605 #define F_T7_HI    V_T7_HI(1U)
35609 #define V_T7_SELH(x) ((x) << S_T7_SELH)
35610 #define G_T7_SELH(x) (((x) >> S_T7_SELH) & M_T7_SELH)
35614 #define V_T7_SELL(x) ((x) << S_T7_SELL)
35615 #define G_T7_SELL(x) (((x) >> S_T7_SELL) & M_T7_SELL)
35622 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
35623 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
35627 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
35628 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
35631 #define V_STROBE1(x) ((x) << S_STROBE1)
35632 #define F_STROBE1    V_STROBE1(1U)
35636 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
35637 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
35641 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
35642 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
35644 #define S_CH3_INPUT    1
35646 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
35647 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
35650 #define V_STROBE0(x) ((x) << S_STROBE0)
35651 #define F_STROBE0    V_STROBE0(1U)
35934 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
35935 #define F_STAG_MIX_ENABLE    V_STAG_MIX_ENABLE(1U)
35937 #define S_STAGF_FIX_DISABLE    1
35938 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
35939 #define F_STAGF_FIX_DISABLE    V_STAGF_FIX_DISABLE(1U)
35942 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
35943 #define F_EXTRA_TAG_INSERTION_ENABLE    V_EXTRA_TAG_INSERTION_ENABLE(1U)
35946 #define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
35947 #define F_PHYS_ADDR_RESP_EN    V_PHYS_ADDR_RESP_EN(1U)
35950 #define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
35951 #define F_ENDIANESS_CHANGE    V_ENDIANESS_CHANGE(1U)
35954 #define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
35955 #define F_ERR_RTAG_EN    V_ERR_RTAG_EN(1U)
35958 #define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
35959 #define F_TSO_ETHLEN_EN    V_TSO_ETHLEN_EN(1U)
35962 #define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
35963 #define F_EMSG_MORE_INFO    V_EMSG_MORE_INFO(1U)
35965 #define S_LOSDR    1
35966 #define V_LOSDR(x) ((x) << S_LOSDR)
35967 #define F_LOSDR    V_LOSDR(1U)
35970 #define V_ULIMIT_EXCLUSIVE_FIX(x) ((x) << S_ULIMIT_EXCLUSIVE_FIX)
35971 #define F_ULIMIT_EXCLUSIVE_FIX    V_ULIMIT_EXCLUSIVE_FIX(1U)
35974 #define V_ISO_A_FLAG_EN(x) ((x) << S_ISO_A_FLAG_EN)
35975 #define F_ISO_A_FLAG_EN    V_ISO_A_FLAG_EN(1U)
35978 #define V_IWARP_SEQ_FLIT_DIS(x) ((x) << S_IWARP_SEQ_FLIT_DIS)
35979 #define F_IWARP_SEQ_FLIT_DIS    V_IWARP_SEQ_FLIT_DIS(1U)
35982 #define V_MR_SIZE_FIX_EN(x) ((x) << S_MR_SIZE_FIX_EN)
35983 #define F_MR_SIZE_FIX_EN    V_MR_SIZE_FIX_EN(1U)
35986 #define V_T10_ISO_FIX_EN(x) ((x) << S_T10_ISO_FIX_EN)
35987 #define F_T10_ISO_FIX_EN    V_T10_ISO_FIX_EN(1U)
35990 #define V_CPL_FLAGS_UPDATE_EN(x) ((x) << S_CPL_FLAGS_UPDATE_EN)
35991 #define F_CPL_FLAGS_UPDATE_EN    V_CPL_FLAGS_UPDATE_EN(1U)
35994 #define V_IWARP_SEQ_UPDATE_EN(x) ((x) << S_IWARP_SEQ_UPDATE_EN)
35995 #define F_IWARP_SEQ_UPDATE_EN    V_IWARP_SEQ_UPDATE_EN(1U)
35998 #define V_SEQ_UPDATE_EN(x) ((x) << S_SEQ_UPDATE_EN)
35999 #define F_SEQ_UPDATE_EN    V_SEQ_UPDATE_EN(1U)
36002 #define V_ERR_ITT_EN(x) ((x) << S_ERR_ITT_EN)
36003 #define F_ERR_ITT_EN    V_ERR_ITT_EN(1U)
36006 #define V_ATOMIC_FIX_DIS(x) ((x) << S_ATOMIC_FIX_DIS)
36007 #define F_ATOMIC_FIX_DIS    V_ATOMIC_FIX_DIS(1U)
36010 #define V_LB_LEN_SEL(x) ((x) << S_LB_LEN_SEL)
36011 #define F_LB_LEN_SEL    V_LB_LEN_SEL(1U)
36014 #define V_DISABLE_TPT_CREDIT_CHK(x) ((x) << S_DISABLE_TPT_CREDIT_CHK)
36015 #define F_DISABLE_TPT_CREDIT_CHK    V_DISABLE_TPT_CREDIT_CHK(1U)
36018 #define V_REQSRC(x) ((x) << S_REQSRC)
36019 #define F_REQSRC    V_REQSRC(1U)
36022 #define V_ERR2UP(x) ((x) << S_ERR2UP)
36023 #define F_ERR2UP    V_ERR2UP(1U)
36026 #define V_SGE_INVALIDATE_DIS(x) ((x) << S_SGE_INVALIDATE_DIS)
36027 #define F_SGE_INVALIDATE_DIS    V_SGE_INVALIDATE_DIS(1U)
36030 #define V_ROCE_ACKREQ_CTRL(x) ((x) << S_ROCE_ACKREQ_CTRL)
36031 #define F_ROCE_ACKREQ_CTRL    V_ROCE_ACKREQ_CTRL(1U)
36035 #define V_MEM_ADDR_CTRL(x) ((x) << S_MEM_ADDR_CTRL)
36036 #define G_MEM_ADDR_CTRL(x) (((x) >> S_MEM_ADDR_CTRL) & M_MEM_ADDR_CTRL)
36039 #define V_TPT_EXTENSION_MODE(x) ((x) << S_TPT_EXTENSION_MODE)
36040 #define F_TPT_EXTENSION_MODE    V_TPT_EXTENSION_MODE(1U)
36043 #define V_XRC_INDICATION(x) ((x) << S_XRC_INDICATION)
36044 #define F_XRC_INDICATION    V_XRC_INDICATION(1U)
36047 #define V_LSO_1SEG_LEN_UPD_EN(x) ((x) << S_LSO_1SEG_LEN_UPD_EN)
36048 #define F_LSO_1SEG_LEN_UPD_EN    V_LSO_1SEG_LEN_UPD_EN(1U)
36051 #define V_PKT_ISGL_ERR_ST_EN(x) ((x) << S_PKT_ISGL_ERR_ST_EN)
36052 #define F_PKT_ISGL_ERR_ST_EN    V_PKT_ISGL_ERR_ST_EN(1U)
36056 #define S_T7_1_MEMSEL    1
36058 #define V_T7_1_MEMSEL(x) ((x) << S_T7_1_MEMSEL)
36059 #define G_T7_1_MEMSEL(x) (((x) >> S_T7_1_MEMSEL) & M_T7_1_MEMSEL)
36064 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
36065 #define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)
36068 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
36069 #define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)
36072 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
36073 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
36076 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
36077 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
36080 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
36081 #define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)
36084 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
36085 #define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)
36088 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
36089 #define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)
36092 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
36093 #define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)
36096 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
36097 #define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)
36100 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
36101 #define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)
36104 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
36105 #define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)
36108 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
36109 #define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)
36112 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
36113 #define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)
36116 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
36117 #define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)
36120 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
36121 #define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)
36124 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
36125 #define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)
36128 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
36129 #define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)
36132 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
36133 #define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)
36136 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
36137 #define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)
36140 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
36141 #define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)
36144 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
36145 #define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)
36148 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
36149 #define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)
36152 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
36153 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
36156 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
36157 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
36160 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
36161 #define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)
36164 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
36165 #define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)
36168 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
36169 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
36172 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
36173 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
36176 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
36177 #define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)
36180 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
36181 #define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)
36183 #define S_IMM_DATA_PERR_SET_CH1    1
36184 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
36185 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
36188 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
36189 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
36194 #define V_TLS_DSGL_PARERR3(x) ((x) << S_TLS_DSGL_PARERR3)
36195 #define F_TLS_DSGL_PARERR3    V_TLS_DSGL_PARERR3(1U)
36198 #define V_TLS_DSGL_PARERR2(x) ((x) << S_TLS_DSGL_PARERR2)
36199 #define F_TLS_DSGL_PARERR2    V_TLS_DSGL_PARERR2(1U)
36201 #define S_TLS_DSGL_PARERR1    1
36202 #define V_TLS_DSGL_PARERR1(x) ((x) << S_TLS_DSGL_PARERR1)
36203 #define F_TLS_DSGL_PARERR1    V_TLS_DSGL_PARERR1(1U)
36206 #define V_TLS_DSGL_PARERR0(x) ((x) << S_TLS_DSGL_PARERR0)
36207 #define F_TLS_DSGL_PARERR0    V_TLS_DSGL_PARERR0(1U)
36221 #define V_TLSPERREN(x) ((x) << S_TLSPERREN)
36222 #define F_TLSPERREN    V_TLSPERREN(1U)
36225 #define V_TLSPATHCTL(x) ((x) << S_TLSPATHCTL)
36226 #define F_TLSPATHCTL    V_TLSPATHCTL(1U)
36229 #define V_TLSDISABLEIFUSE(x) ((x) << S_TLSDISABLEIFUSE)
36230 #define F_TLSDISABLEIFUSE    V_TLSDISABLEIFUSE(1U)
36232 #define S_TLSDISABLECFUSE    1
36233 #define V_TLSDISABLECFUSE(x) ((x) << S_TLSDISABLECFUSE)
36234 #define F_TLSDISABLECFUSE    V_TLSDISABLECFUSE(1U)
36237 #define V_TLSDISABLE(x) ((x) << S_TLSDISABLE)
36238 #define F_TLSDISABLE    V_TLSDISABLE(1U)
36245 #define V_FID_1(x) ((x) << S_FID_1)
36246 #define G_FID_1(x) (((x) >> S_FID_1) & M_FID_1)
36255 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
36256 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
36260 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
36261 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
36265 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
36266 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
36270 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
36271 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
36277 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
36278 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
36282 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
36283 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
36287 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
36288 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
36292 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
36293 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
36301 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
36302 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
36308 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
36309 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
36315 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
36316 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
36322 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
36323 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
36329 #define V_SOF_FS3(x) ((x) << S_SOF_FS3)
36330 #define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
36334 #define V_SOF_FS2(x) ((x) << S_SOF_FS2)
36335 #define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
36339 #define V_SOF_3(x) ((x) << S_SOF_3)
36340 #define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
36344 #define V_SOF_2(x) ((x) << S_SOF_2)
36345 #define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
36351 #define V_EOF_LS3(x) ((x) << S_EOF_LS3)
36352 #define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
36356 #define V_EOF_LS2(x) ((x) << S_EOF_LS2)
36357 #define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
36361 #define V_EOF_3(x) ((x) << S_EOF_3)
36362 #define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
36366 #define V_EOF_2(x) ((x) << S_EOF_2)
36367 #define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
36372 #define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
36373 #define F_ULP_TX_GLOBAL_CGEN    V_ULP_TX_GLOBAL_CGEN(1U)
36379 #define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
36380 #define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
36384 #define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
36385 #define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
36389 #define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
36390 #define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
36397 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
36398 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
36401 #define V_T7_GLOBALENABLE(x) ((x) << S_T7_GLOBALENABLE)
36402 #define F_T7_GLOBALENABLE    V_T7_GLOBALENABLE(1U)
36406 #define V_RDREQ_SZ(x) ((x) << S_RDREQ_SZ)
36407 #define G_RDREQ_SZ(x) (((x) >> S_RDREQ_SZ) & M_RDREQ_SZ)
36412 #define S_T5_MEMSEL    1
36414 #define V_T5_MEMSEL(x) ((x) << S_T5_MEMSEL)
36415 #define G_T5_MEMSEL(x) (((x) >> S_T5_MEMSEL) & M_T5_MEMSEL)
36417 #define S_MEMSEL_ULPTX    1
36419 #define V_MEMSEL_ULPTX(x) ((x) << S_MEMSEL_ULPTX)
36420 #define G_MEMSEL_ULPTX(x) (((x) >> S_MEMSEL_ULPTX) & M_MEMSEL_ULPTX)
36427 #define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
36428 #define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
36432 #define V_INTF_SEL(x) ((x) << S_INTF_SEL)
36433 #define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
36435 #define S_NUM_FLITS    1
36437 #define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
36438 #define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
36441 #define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
36442 #define F_CMD_GEN_EN    V_CMD_GEN_EN(1U)
36479 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
36480 #define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)
36483 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
36484 #define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)
36487 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
36488 #define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)
36491 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
36492 #define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)
36495 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
36496 #define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)
36499 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
36500 #define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)
36503 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
36504 #define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)
36507 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
36508 #define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)
36511 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
36512 #define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)
36515 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
36516 #define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)
36519 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
36520 #define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)
36522 #define S_T10_PI_SRAM_PERR_SET1    1
36523 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
36524 #define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)
36527 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
36528 #define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
36531 #define V_EDMA_IN_FIFO_PERR_SET3(x) ((x) << S_EDMA_IN_FIFO_PERR_SET3)
36532 #define F_EDMA_IN_FIFO_PERR_SET3    V_EDMA_IN_FIFO_PERR_SET3(1U)
36535 #define V_EDMA_IN_FIFO_PERR_SET2(x) ((x) << S_EDMA_IN_FIFO_PERR_SET2)
36536 #define F_EDMA_IN_FIFO_PERR_SET2    V_EDMA_IN_FIFO_PERR_SET2(1U)
36539 #define V_EDMA_IN_FIFO_PERR_SET1(x) ((x) << S_EDMA_IN_FIFO_PERR_SET1)
36540 #define F_EDMA_IN_FIFO_PERR_SET1    V_EDMA_IN_FIFO_PERR_SET1(1U)
36543 #define V_EDMA_IN_FIFO_PERR_SET0(x) ((x) << S_EDMA_IN_FIFO_PERR_SET0)
36544 #define F_EDMA_IN_FIFO_PERR_SET0    V_EDMA_IN_FIFO_PERR_SET0(1U)
36547 #define V_ALIGN_CTL_FIFO_PERR_SET3(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET3)
36548 #define F_ALIGN_CTL_FIFO_PERR_SET3    V_ALIGN_CTL_FIFO_PERR_SET3(1U)
36551 #define V_ALIGN_CTL_FIFO_PERR_SET2(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET2)
36552 #define F_ALIGN_CTL_FIFO_PERR_SET2    V_ALIGN_CTL_FIFO_PERR_SET2(1U)
36555 #define V_ALIGN_CTL_FIFO_PERR_SET1(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET1)
36556 #define F_ALIGN_CTL_FIFO_PERR_SET1    V_ALIGN_CTL_FIFO_PERR_SET1(1U)
36559 #define V_ALIGN_CTL_FIFO_PERR_SET0(x) ((x) << S_ALIGN_CTL_FIFO_PERR_SET0)
36560 #define F_ALIGN_CTL_FIFO_PERR_SET0    V_ALIGN_CTL_FIFO_PERR_SET0(1U)
36563 #define V_SGE_FIFO_PERR_SET3(x) ((x) << S_SGE_FIFO_PERR_SET3)
36564 #define F_SGE_FIFO_PERR_SET3    V_SGE_FIFO_PERR_SET3(1U)
36567 #define V_SGE_FIFO_PERR_SET2(x) ((x) << S_SGE_FIFO_PERR_SET2)
36568 #define F_SGE_FIFO_PERR_SET2    V_SGE_FIFO_PERR_SET2(1U)
36571 #define V_SGE_FIFO_PERR_SET1(x) ((x) << S_SGE_FIFO_PERR_SET1)
36572 #define F_SGE_FIFO_PERR_SET1    V_SGE_FIFO_PERR_SET1(1U)
36575 #define V_SGE_FIFO_PERR_SET0(x) ((x) << S_SGE_FIFO_PERR_SET0)
36576 #define F_SGE_FIFO_PERR_SET0    V_SGE_FIFO_PERR_SET0(1U)
36579 #define V_STAG_FIFO_PERR_SET3(x) ((x) << S_STAG_FIFO_PERR_SET3)
36580 #define F_STAG_FIFO_PERR_SET3    V_STAG_FIFO_PERR_SET3(1U)
36583 #define V_STAG_FIFO_PERR_SET2(x) ((x) << S_STAG_FIFO_PERR_SET2)
36584 #define F_STAG_FIFO_PERR_SET2    V_STAG_FIFO_PERR_SET2(1U)
36587 #define V_STAG_FIFO_PERR_SET1(x) ((x) << S_STAG_FIFO_PERR_SET1)
36588 #define F_STAG_FIFO_PERR_SET1    V_STAG_FIFO_PERR_SET1(1U)
36591 #define V_STAG_FIFO_PERR_SET0(x) ((x) << S_STAG_FIFO_PERR_SET0)
36592 #define F_STAG_FIFO_PERR_SET0    V_STAG_FIFO_PERR_SET0(1U)
36595 #define V_MAP_FIFO_PERR_SET3(x) ((x) << S_MAP_FIFO_PERR_SET3)
36596 #define F_MAP_FIFO_PERR_SET3    V_MAP_FIFO_PERR_SET3(1U)
36599 #define V_MAP_FIFO_PERR_SET2(x) ((x) << S_MAP_FIFO_PERR_SET2)
36600 #define F_MAP_FIFO_PERR_SET2    V_MAP_FIFO_PERR_SET2(1U)
36603 #define V_MAP_FIFO_PERR_SET1(x) ((x) << S_MAP_FIFO_PERR_SET1)
36604 #define F_MAP_FIFO_PERR_SET1    V_MAP_FIFO_PERR_SET1(1U)
36607 #define V_MAP_FIFO_PERR_SET0(x) ((x) << S_MAP_FIFO_PERR_SET0)
36608 #define F_MAP_FIFO_PERR_SET0    V_MAP_FIFO_PERR_SET0(1U)
36611 #define V_DMA_FIFO_PERR_SET3(x) ((x) << S_DMA_FIFO_PERR_SET3)
36612 #define F_DMA_FIFO_PERR_SET3    V_DMA_FIFO_PERR_SET3(1U)
36615 #define V_DMA_FIFO_PERR_SET2(x) ((x) << S_DMA_FIFO_PERR_SET2)
36616 #define F_DMA_FIFO_PERR_SET2    V_DMA_FIFO_PERR_SET2(1U)
36619 #define V_DMA_FIFO_PERR_SET1(x) ((x) << S_DMA_FIFO_PERR_SET1)
36620 #define F_DMA_FIFO_PERR_SET1    V_DMA_FIFO_PERR_SET1(1U)
36623 #define V_DMA_FIFO_PERR_SET0(x) ((x) << S_DMA_FIFO_PERR_SET0)
36624 #define F_DMA_FIFO_PERR_SET0    V_DMA_FIFO_PERR_SET0(1U)
36631 #define V_GF_SGE_FIFO_PARERR3(x) ((x) << S_GF_SGE_FIFO_PARERR3)
36632 #define F_GF_SGE_FIFO_PARERR3    V_GF_SGE_FIFO_PARERR3(1U)
36635 #define V_GF_SGE_FIFO_PARERR2(x) ((x) << S_GF_SGE_FIFO_PARERR2)
36636 #define F_GF_SGE_FIFO_PARERR2    V_GF_SGE_FIFO_PARERR2(1U)
36639 #define V_GF_SGE_FIFO_PARERR1(x) ((x) << S_GF_SGE_FIFO_PARERR1)
36640 #define F_GF_SGE_FIFO_PARERR1    V_GF_SGE_FIFO_PARERR1(1U)
36643 #define V_GF_SGE_FIFO_PARERR0(x) ((x) << S_GF_SGE_FIFO_PARERR0)
36644 #define F_GF_SGE_FIFO_PARERR0    V_GF_SGE_FIFO_PARERR0(1U)
36647 #define V_DEDUPE_SGE_FIFO_PARERR3(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR3)
36648 #define F_DEDUPE_SGE_FIFO_PARERR3    V_DEDUPE_SGE_FIFO_PARERR3(1U)
36651 #define V_DEDUPE_SGE_FIFO_PARERR2(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR2)
36652 #define F_DEDUPE_SGE_FIFO_PARERR2    V_DEDUPE_SGE_FIFO_PARERR2(1U)
36655 #define V_DEDUPE_SGE_FIFO_PARERR1(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR1)
36656 #define F_DEDUPE_SGE_FIFO_PARERR1    V_DEDUPE_SGE_FIFO_PARERR1(1U)
36659 #define V_DEDUPE_SGE_FIFO_PARERR0(x) ((x) << S_DEDUPE_SGE_FIFO_PARERR0)
36660 #define F_DEDUPE_SGE_FIFO_PARERR0    V_DEDUPE_SGE_FIFO_PARERR0(1U)
36663 #define V_GF3_DSGL_FIFO_PARERR(x) ((x) << S_GF3_DSGL_FIFO_PARERR)
36664 #define F_GF3_DSGL_FIFO_PARERR    V_GF3_DSGL_FIFO_PARERR(1U)
36667 #define V_GF2_DSGL_FIFO_PARERR(x) ((x) << S_GF2_DSGL_FIFO_PARERR)
36668 #define F_GF2_DSGL_FIFO_PARERR    V_GF2_DSGL_FIFO_PARERR(1U)
36671 #define V_GF1_DSGL_FIFO_PARERR(x) ((x) << S_GF1_DSGL_FIFO_PARERR)
36672 #define F_GF1_DSGL_FIFO_PARERR    V_GF1_DSGL_FIFO_PARERR(1U)
36675 #define V_GF0_DSGL_FIFO_PARERR(x) ((x) << S_GF0_DSGL_FIFO_PARERR)
36676 #define F_GF0_DSGL_FIFO_PARERR    V_GF0_DSGL_FIFO_PARERR(1U)
36679 #define V_DEDUPE3_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE3_DSGL_FIFO_PARERR)
36680 #define F_DEDUPE3_DSGL_FIFO_PARERR    V_DEDUPE3_DSGL_FIFO_PARERR(1U)
36683 #define V_DEDUPE2_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE2_DSGL_FIFO_PARERR)
36684 #define F_DEDUPE2_DSGL_FIFO_PARERR    V_DEDUPE2_DSGL_FIFO_PARERR(1U)
36687 #define V_DEDUPE1_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE1_DSGL_FIFO_PARERR)
36688 #define F_DEDUPE1_DSGL_FIFO_PARERR    V_DEDUPE1_DSGL_FIFO_PARERR(1U)
36691 #define V_DEDUPE0_DSGL_FIFO_PARERR(x) ((x) << S_DEDUPE0_DSGL_FIFO_PARERR)
36692 #define F_DEDUPE0_DSGL_FIFO_PARERR    V_DEDUPE0_DSGL_FIFO_PARERR(1U)
36695 #define V_XP10_SGE_FIFO_PARERR(x) ((x) << S_XP10_SGE_FIFO_PARERR)
36696 #define F_XP10_SGE_FIFO_PARERR    V_XP10_SGE_FIFO_PARERR(1U)
36699 #define V_DSGL_PAR_ERR(x) ((x) << S_DSGL_PAR_ERR)
36700 #define F_DSGL_PAR_ERR    V_DSGL_PAR_ERR(1U)
36703 #define V_CDDIP_INT(x) ((x) << S_CDDIP_INT)
36704 #define F_CDDIP_INT    V_CDDIP_INT(1U)
36707 #define V_CCEIP_INT(x) ((x) << S_CCEIP_INT)
36708 #define F_CCEIP_INT    V_CCEIP_INT(1U)
36711 #define V_TLS_SGE_FIFO_PARERR3(x) ((x) << S_TLS_SGE_FIFO_PARERR3)
36712 #define F_TLS_SGE_FIFO_PARERR3    V_TLS_SGE_FIFO_PARERR3(1U)
36715 #define V_TLS_SGE_FIFO_PARERR2(x) ((x) << S_TLS_SGE_FIFO_PARERR2)
36716 #define F_TLS_SGE_FIFO_PARERR2    V_TLS_SGE_FIFO_PARERR2(1U)
36719 #define V_TLS_SGE_FIFO_PARERR1(x) ((x) << S_TLS_SGE_FIFO_PARERR1)
36720 #define F_TLS_SGE_FIFO_PARERR1    V_TLS_SGE_FIFO_PARERR1(1U)
36723 #define V_TLS_SGE_FIFO_PARERR0(x) ((x) << S_TLS_SGE_FIFO_PARERR0)
36724 #define F_TLS_SGE_FIFO_PARERR0    V_TLS_SGE_FIFO_PARERR0(1U)
36727 #define V_ULP2SMARBT_RSP_PERR(x) ((x) << S_ULP2SMARBT_RSP_PERR)
36728 #define F_ULP2SMARBT_RSP_PERR    V_ULP2SMARBT_RSP_PERR(1U)
36731 #define V_ULPTX2MA_RSP_PERR(x) ((x) << S_ULPTX2MA_RSP_PERR)
36732 #define F_ULPTX2MA_RSP_PERR    V_ULPTX2MA_RSP_PERR(1U)
36735 #define V_PCIE2ULP_PERR3(x) ((x) << S_PCIE2ULP_PERR3)
36736 #define F_PCIE2ULP_PERR3    V_PCIE2ULP_PERR3(1U)
36739 #define V_PCIE2ULP_PERR2(x) ((x) << S_PCIE2ULP_PERR2)
36740 #define F_PCIE2ULP_PERR2    V_PCIE2ULP_PERR2(1U)
36743 #define V_PCIE2ULP_PERR1(x) ((x) << S_PCIE2ULP_PERR1)
36744 #define F_PCIE2ULP_PERR1    V_PCIE2ULP_PERR1(1U)
36746 #define S_PCIE2ULP_PERR0    1
36747 #define V_PCIE2ULP_PERR0(x) ((x) << S_PCIE2ULP_PERR0)
36748 #define F_PCIE2ULP_PERR0    V_PCIE2ULP_PERR0(1U)
36751 #define V_CIM2ULP_PERR(x) ((x) << S_CIM2ULP_PERR)
36752 #define F_CIM2ULP_PERR    V_CIM2ULP_PERR(1U)
36760 #define V_DMA_PAR_ERR3(x) ((x) << S_DMA_PAR_ERR3)
36761 #define G_DMA_PAR_ERR3(x) (((x) >> S_DMA_PAR_ERR3) & M_DMA_PAR_ERR3)
36765 #define V_DMA_PAR_ERR2(x) ((x) << S_DMA_PAR_ERR2)
36766 #define G_DMA_PAR_ERR2(x) (((x) >> S_DMA_PAR_ERR2) & M_DMA_PAR_ERR2)
36770 #define V_DMA_PAR_ERR1(x) ((x) << S_DMA_PAR_ERR1)
36771 #define G_DMA_PAR_ERR1(x) (((x) >> S_DMA_PAR_ERR1) & M_DMA_PAR_ERR1)
36775 #define V_DMA_PAR_ERR0(x) ((x) << S_DMA_PAR_ERR0)
36776 #define G_DMA_PAR_ERR0(x) (((x) >> S_DMA_PAR_ERR0) & M_DMA_PAR_ERR0)
36780 #define V_CORE_CMD_FIFO_LB1(x) ((x) << S_CORE_CMD_FIFO_LB1)
36781 #define G_CORE_CMD_FIFO_LB1(x) (((x) >> S_CORE_CMD_FIFO_LB1) & M_CORE_CMD_FIFO_LB1)
36785 #define V_CORE_CMD_FIFO_LB0(x) ((x) << S_CORE_CMD_FIFO_LB0)
36786 #define G_CORE_CMD_FIFO_LB0(x) (((x) >> S_CORE_CMD_FIFO_LB0) & M_CORE_CMD_FIFO_LB0)
36789 #define V_XP10_2_ULP_PERR(x) ((x) << S_XP10_2_ULP_PERR)
36790 #define F_XP10_2_ULP_PERR    V_XP10_2_ULP_PERR(1U)
36793 #define V_ULP_2_XP10_PERR(x) ((x) << S_ULP_2_XP10_PERR)
36794 #define F_ULP_2_XP10_PERR    V_ULP_2_XP10_PERR(1U)
36797 #define V_CMD_FIFO_LB1(x) ((x) << S_CMD_FIFO_LB1)
36798 #define F_CMD_FIFO_LB1    V_CMD_FIFO_LB1(1U)
36801 #define V_CMD_FIFO_LB0(x) ((x) << S_CMD_FIFO_LB0)
36802 #define F_CMD_FIFO_LB0    V_CMD_FIFO_LB0(1U)
36805 #define V_TF_TP_PERR(x) ((x) << S_TF_TP_PERR)
36806 #define F_TF_TP_PERR    V_TF_TP_PERR(1U)
36809 #define V_TF_SGE_PERR(x) ((x) << S_TF_SGE_PERR)
36810 #define F_TF_SGE_PERR    V_TF_SGE_PERR(1U)
36812 #define S_TF_MEM_PERR    1
36813 #define V_TF_MEM_PERR(x) ((x) << S_TF_MEM_PERR)
36814 #define F_TF_MEM_PERR    V_TF_MEM_PERR(1U)
36817 #define V_TF_MP_PERR(x) ((x) << S_TF_MP_PERR)
36818 #define F_TF_MP_PERR    V_TF_MP_PERR(1U)
36826 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
36827 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
36831 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
36832 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
36836 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
36837 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
36841 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
36842 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
36849 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
36850 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
36854 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
36855 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
36859 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
36860 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
36864 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
36865 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
36869 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
36870 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
36877 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
36878 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
36882 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
36883 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
36887 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
36888 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
36892 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
36893 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
36897 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
36898 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
36902 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
36903 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
36907 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
36908 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
36912 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
36913 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
36926 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
36927 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
36931 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
36932 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
36936 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
36937 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
36941 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
36942 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
36948 #define V_DROP_INVLD_MC_CH3(x) ((x) << S_DROP_INVLD_MC_CH3)
36949 #define G_DROP_INVLD_MC_CH3(x) (((x) >> S_DROP_INVLD_MC_CH3) & M_DROP_INVLD_MC_CH3)
36953 #define V_DROP_INVLD_MC_CH2(x) ((x) << S_DROP_INVLD_MC_CH2)
36954 #define G_DROP_INVLD_MC_CH2(x) (((x) >> S_DROP_INVLD_MC_CH2) & M_DROP_INVLD_MC_CH2)
36958 #define V_DROP_INVLD_MC_CH1(x) ((x) << S_DROP_INVLD_MC_CH1)
36959 #define G_DROP_INVLD_MC_CH1(x) (((x) >> S_DROP_INVLD_MC_CH1) & M_DROP_INVLD_MC_CH1)
36963 #define V_DROP_INVLD_MC_CH0(x) ((x) << S_DROP_INVLD_MC_CH0)
36964 #define G_DROP_INVLD_MC_CH0(x) (((x) >> S_DROP_INVLD_MC_CH0) & M_DROP_INVLD_MC_CH0)
36971 #define V_PL2APB_BRIDGE_HUNG(x) ((x) << S_PL2APB_BRIDGE_HUNG)
36972 #define F_PL2APB_BRIDGE_HUNG    V_PL2APB_BRIDGE_HUNG(1U)
36975 #define V_PL2APB_BRIDGE_STATE(x) ((x) << S_PL2APB_BRIDGE_STATE)
36976 #define F_PL2APB_BRIDGE_STATE    V_PL2APB_BRIDGE_STATE(1U)
36979 #define V_PL2APB_BRIDGE_HUNG_TYPE(x) ((x) << S_PL2APB_BRIDGE_HUNG_TYPE)
36980 #define F_PL2APB_BRIDGE_HUNG_TYPE    V_PL2APB_BRIDGE_HUNG_TYPE(1U)
36983 #define V_PL2APB_BRIDGE_HUNG_ID(x) ((x) << S_PL2APB_BRIDGE_HUNG_ID)
36984 #define F_PL2APB_BRIDGE_HUNG_ID    V_PL2APB_BRIDGE_HUNG_ID(1U)
36988 #define V_PL2APB_BRIDGE_HUNG_ADDR(x) ((x) << S_PL2APB_BRIDGE_HUNG_ADDR)
36989 #define G_PL2APB_BRIDGE_HUNG_ADDR(x) (((x) >> S_PL2APB_BRIDGE_HUNG_ADDR) & M_PL2APB_BRIDGE_HUNG_ADDR)
36995 #define V_DEDUPE_PERR3(x) ((x) << S_DEDUPE_PERR3)
36996 #define F_DEDUPE_PERR3    V_DEDUPE_PERR3(1U)
36999 #define V_DEDUPE_PERR2(x) ((x) << S_DEDUPE_PERR2)
37000 #define F_DEDUPE_PERR2    V_DEDUPE_PERR2(1U)
37003 #define V_DEDUPE_PERR1(x) ((x) << S_DEDUPE_PERR1)
37004 #define F_DEDUPE_PERR1    V_DEDUPE_PERR1(1U)
37007 #define V_DEDUPE_PERR0(x) ((x) << S_DEDUPE_PERR0)
37008 #define F_DEDUPE_PERR0    V_DEDUPE_PERR0(1U)
37011 #define V_GF_PERR3(x) ((x) << S_GF_PERR3)
37012 #define F_GF_PERR3    V_GF_PERR3(1U)
37015 #define V_GF_PERR2(x) ((x) << S_GF_PERR2)
37016 #define F_GF_PERR2    V_GF_PERR2(1U)
37019 #define V_GF_PERR1(x) ((x) << S_GF_PERR1)
37020 #define F_GF_PERR1    V_GF_PERR1(1U)
37023 #define V_GF_PERR0(x) ((x) << S_GF_PERR0)
37024 #define F_GF_PERR0    V_GF_PERR0(1U)
37027 #define V_SGE2ULP_INV_PERR(x) ((x) << S_SGE2ULP_INV_PERR)
37028 #define F_SGE2ULP_INV_PERR    V_SGE2ULP_INV_PERR(1U)
37031 #define V_T7_PL_BUSPERR(x) ((x) << S_T7_PL_BUSPERR)
37032 #define F_T7_PL_BUSPERR    V_T7_PL_BUSPERR(1U)
37035 #define V_TLSTX2ULPTX_PERR3(x) ((x) << S_TLSTX2ULPTX_PERR3)
37036 #define F_TLSTX2ULPTX_PERR3    V_TLSTX2ULPTX_PERR3(1U)
37039 #define V_TLSTX2ULPTX_PERR2(x) ((x) << S_TLSTX2ULPTX_PERR2)
37040 #define F_TLSTX2ULPTX_PERR2    V_TLSTX2ULPTX_PERR2(1U)
37043 #define V_TLSTX2ULPTX_PERR1(x) ((x) << S_TLSTX2ULPTX_PERR1)
37044 #define F_TLSTX2ULPTX_PERR1    V_TLSTX2ULPTX_PERR1(1U)
37047 #define V_TLSTX2ULPTX_PERR0(x) ((x) << S_TLSTX2ULPTX_PERR0)
37048 #define F_TLSTX2ULPTX_PERR0    V_TLSTX2ULPTX_PERR0(1U)
37050 #define S_XP10_2_ULP_PL_PERR    1
37051 #define V_XP10_2_ULP_PL_PERR(x) ((x) << S_XP10_2_ULP_PL_PERR)
37052 #define F_XP10_2_ULP_PL_PERR    V_XP10_2_ULP_PL_PERR(1U)
37055 #define V_ULP_2_XP10_PL_PERR(x) ((x) << S_ULP_2_XP10_PL_PERR)
37056 #define F_ULP_2_XP10_PL_PERR    V_ULP_2_XP10_PL_PERR(1U)
37066 #define V_DDR_HDR_FIFO_PERR_SET3(x) ((x) << S_DDR_HDR_FIFO_PERR_SET3)
37067 #define F_DDR_HDR_FIFO_PERR_SET3    V_DDR_HDR_FIFO_PERR_SET3(1U)
37070 #define V_DDR_HDR_FIFO_PERR_SET2(x) ((x) << S_DDR_HDR_FIFO_PERR_SET2)
37071 #define F_DDR_HDR_FIFO_PERR_SET2    V_DDR_HDR_FIFO_PERR_SET2(1U)
37074 #define V_DDR_HDR_FIFO_PERR_SET1(x) ((x) << S_DDR_HDR_FIFO_PERR_SET1)
37075 #define F_DDR_HDR_FIFO_PERR_SET1    V_DDR_HDR_FIFO_PERR_SET1(1U)
37078 #define V_DDR_HDR_FIFO_PERR_SET0(x) ((x) << S_DDR_HDR_FIFO_PERR_SET0)
37079 #define F_DDR_HDR_FIFO_PERR_SET0    V_DDR_HDR_FIFO_PERR_SET0(1U)
37082 #define V_PRE_MP_RSP_PERR_SET3(x) ((x) << S_PRE_MP_RSP_PERR_SET3)
37083 #define F_PRE_MP_RSP_PERR_SET3    V_PRE_MP_RSP_PERR_SET3(1U)
37086 #define V_PRE_MP_RSP_PERR_SET2(x) ((x) << S_PRE_MP_RSP_PERR_SET2)
37087 #define F_PRE_MP_RSP_PERR_SET2    V_PRE_MP_RSP_PERR_SET2(1U)
37090 #define V_PRE_MP_RSP_PERR_SET1(x) ((x) << S_PRE_MP_RSP_PERR_SET1)
37091 #define F_PRE_MP_RSP_PERR_SET1    V_PRE_MP_RSP_PERR_SET1(1U)
37094 #define V_PRE_MP_RSP_PERR_SET0(x) ((x) << S_PRE_MP_RSP_PERR_SET0)
37095 #define F_PRE_MP_RSP_PERR_SET0    V_PRE_MP_RSP_PERR_SET0(1U)
37098 #define V_PRE_CQE_FIFO_PERR_SET3(x) ((x) << S_PRE_CQE_FIFO_PERR_SET3)
37099 #define F_PRE_CQE_FIFO_PERR_SET3    V_PRE_CQE_FIFO_PERR_SET3(1U)
37102 #define V_PRE_CQE_FIFO_PERR_SET2(x) ((x) << S_PRE_CQE_FIFO_PERR_SET2)
37103 #define F_PRE_CQE_FIFO_PERR_SET2    V_PRE_CQE_FIFO_PERR_SET2(1U)
37106 #define V_PRE_CQE_FIFO_PERR_SET1(x) ((x) << S_PRE_CQE_FIFO_PERR_SET1)
37107 #define F_PRE_CQE_FIFO_PERR_SET1    V_PRE_CQE_FIFO_PERR_SET1(1U)
37109 #define S_PRE_CQE_FIFO_PERR_SET0    1
37110 #define V_PRE_CQE_FIFO_PERR_SET0(x) ((x) << S_PRE_CQE_FIFO_PERR_SET0)
37111 #define F_PRE_CQE_FIFO_PERR_SET0    V_PRE_CQE_FIFO_PERR_SET0(1U)
37114 #define V_RSP_FIFO_PERR_SET(x) ((x) << S_RSP_FIFO_PERR_SET)
37115 #define F_RSP_FIFO_PERR_SET    V_RSP_FIFO_PERR_SET(1U)
37125 #define V_TLS_SGE_FIFO_CORERR3(x) ((x) << S_TLS_SGE_FIFO_CORERR3)
37126 #define F_TLS_SGE_FIFO_CORERR3    V_TLS_SGE_FIFO_CORERR3(1U)
37129 #define V_TLS_SGE_FIFO_CORERR2(x) ((x) << S_TLS_SGE_FIFO_CORERR2)
37130 #define F_TLS_SGE_FIFO_CORERR2    V_TLS_SGE_FIFO_CORERR2(1U)
37133 #define V_TLS_SGE_FIFO_CORERR1(x) ((x) << S_TLS_SGE_FIFO_CORERR1)
37134 #define F_TLS_SGE_FIFO_CORERR1    V_TLS_SGE_FIFO_CORERR1(1U)
37137 #define V_TLS_SGE_FIFO_CORERR0(x) ((x) << S_TLS_SGE_FIFO_CORERR0)
37138 #define F_TLS_SGE_FIFO_CORERR0    V_TLS_SGE_FIFO_CORERR0(1U)
37141 #define V_LSO_HDR_SRAM_CERR_SET3(x) ((x) << S_LSO_HDR_SRAM_CERR_SET3)
37142 #define F_LSO_HDR_SRAM_CERR_SET3    V_LSO_HDR_SRAM_CERR_SET3(1U)
37145 #define V_LSO_HDR_SRAM_CERR_SET2(x) ((x) << S_LSO_HDR_SRAM_CERR_SET2)
37146 #define F_LSO_HDR_SRAM_CERR_SET2    V_LSO_HDR_SRAM_CERR_SET2(1U)
37149 #define V_LSO_HDR_SRAM_CERR_SET1(x) ((x) << S_LSO_HDR_SRAM_CERR_SET1)
37150 #define F_LSO_HDR_SRAM_CERR_SET1    V_LSO_HDR_SRAM_CERR_SET1(1U)
37153 #define V_LSO_HDR_SRAM_CERR_SET0(x) ((x) << S_LSO_HDR_SRAM_CERR_SET0)
37154 #define F_LSO_HDR_SRAM_CERR_SET0    V_LSO_HDR_SRAM_CERR_SET0(1U)
37157 #define V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB1)
37158 #define F_CORE_CMD_FIFO_CERR_SET_CH3_LB1    V_CORE_CMD_FIFO_CERR_SET_CH3_LB1(1U)
37161 #define V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB1)
37162 #define F_CORE_CMD_FIFO_CERR_SET_CH2_LB1    V_CORE_CMD_FIFO_CERR_SET_CH2_LB1(1U)
37165 #define V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB1)
37166 #define F_CORE_CMD_FIFO_CERR_SET_CH1_LB1    V_CORE_CMD_FIFO_CERR_SET_CH1_LB1(1U)
37169 #define V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB1)
37170 #define F_CORE_CMD_FIFO_CERR_SET_CH0_LB1    V_CORE_CMD_FIFO_CERR_SET_CH0_LB1(1U)
37173 #define V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH3_LB0)
37174 #define F_CORE_CMD_FIFO_CERR_SET_CH3_LB0    V_CORE_CMD_FIFO_CERR_SET_CH3_LB0(1U)
37177 #define V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH2_LB0)
37178 #define F_CORE_CMD_FIFO_CERR_SET_CH2_LB0    V_CORE_CMD_FIFO_CERR_SET_CH2_LB0(1U)
37181 #define V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH1_LB0)
37182 #define F_CORE_CMD_FIFO_CERR_SET_CH1_LB0    V_CORE_CMD_FIFO_CERR_SET_CH1_LB0(1U)
37185 #define V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(x) ((x) << S_CORE_CMD_FIFO_CERR_SET_CH0_LB0)
37186 #define F_CORE_CMD_FIFO_CERR_SET_CH0_LB0    V_CORE_CMD_FIFO_CERR_SET_CH0_LB0(1U)
37189 #define V_CQE_FIFO_CERR_SET3(x) ((x) << S_CQE_FIFO_CERR_SET3)
37190 #define F_CQE_FIFO_CERR_SET3    V_CQE_FIFO_CERR_SET3(1U)
37193 #define V_CQE_FIFO_CERR_SET2(x) ((x) << S_CQE_FIFO_CERR_SET2)
37194 #define F_CQE_FIFO_CERR_SET2    V_CQE_FIFO_CERR_SET2(1U)
37197 #define V_CQE_FIFO_CERR_SET1(x) ((x) << S_CQE_FIFO_CERR_SET1)
37198 #define F_CQE_FIFO_CERR_SET1    V_CQE_FIFO_CERR_SET1(1U)
37201 #define V_CQE_FIFO_CERR_SET0(x) ((x) << S_CQE_FIFO_CERR_SET0)
37202 #define F_CQE_FIFO_CERR_SET0    V_CQE_FIFO_CERR_SET0(1U)
37205 #define V_PRE_CQE_FIFO_CERR_SET3(x) ((x) << S_PRE_CQE_FIFO_CERR_SET3)
37206 #define F_PRE_CQE_FIFO_CERR_SET3    V_PRE_CQE_FIFO_CERR_SET3(1U)
37209 #define V_PRE_CQE_FIFO_CERR_SET2(x) ((x) << S_PRE_CQE_FIFO_CERR_SET2)
37210 #define F_PRE_CQE_FIFO_CERR_SET2    V_PRE_CQE_FIFO_CERR_SET2(1U)
37212 #define S_PRE_CQE_FIFO_CERR_SET1    1
37213 #define V_PRE_CQE_FIFO_CERR_SET1(x) ((x) << S_PRE_CQE_FIFO_CERR_SET1)
37214 #define F_PRE_CQE_FIFO_CERR_SET1    V_PRE_CQE_FIFO_CERR_SET1(1U)
37217 #define V_PRE_CQE_FIFO_CERR_SET0(x) ((x) << S_PRE_CQE_FIFO_CERR_SET0)
37218 #define F_PRE_CQE_FIFO_CERR_SET0    V_PRE_CQE_FIFO_CERR_SET0(1U)
37226 #define V_MEM_RSP_FIFO_CERR_SET3(x) ((x) << S_MEM_RSP_FIFO_CERR_SET3)
37227 #define F_MEM_RSP_FIFO_CERR_SET3    V_MEM_RSP_FIFO_CERR_SET3(1U)
37230 #define V_MEM_RSP_FIFO_CERR_SET2(x) ((x) << S_MEM_RSP_FIFO_CERR_SET2)
37231 #define F_MEM_RSP_FIFO_CERR_SET2    V_MEM_RSP_FIFO_CERR_SET2(1U)
37234 #define V_MEM_RSP_FIFO_CERR_SET1(x) ((x) << S_MEM_RSP_FIFO_CERR_SET1)
37235 #define F_MEM_RSP_FIFO_CERR_SET1    V_MEM_RSP_FIFO_CERR_SET1(1U)
37238 #define V_MEM_RSP_FIFO_CERR_SET0(x) ((x) << S_MEM_RSP_FIFO_CERR_SET0)
37239 #define F_MEM_RSP_FIFO_CERR_SET0    V_MEM_RSP_FIFO_CERR_SET0(1U)
37242 #define V_PI_SRAM_CERR_SET3(x) ((x) << S_PI_SRAM_CERR_SET3)
37243 #define F_PI_SRAM_CERR_SET3    V_PI_SRAM_CERR_SET3(1U)
37246 #define V_PI_SRAM_CERR_SET2(x) ((x) << S_PI_SRAM_CERR_SET2)
37247 #define F_PI_SRAM_CERR_SET2    V_PI_SRAM_CERR_SET2(1U)
37250 #define V_PI_SRAM_CERR_SET1(x) ((x) << S_PI_SRAM_CERR_SET1)
37251 #define F_PI_SRAM_CERR_SET1    V_PI_SRAM_CERR_SET1(1U)
37254 #define V_PI_SRAM_CERR_SET0(x) ((x) << S_PI_SRAM_CERR_SET0)
37255 #define F_PI_SRAM_CERR_SET0    V_PI_SRAM_CERR_SET0(1U)
37258 #define V_PRE_MP_RSP_CERR_SET3(x) ((x) << S_PRE_MP_RSP_CERR_SET3)
37259 #define F_PRE_MP_RSP_CERR_SET3    V_PRE_MP_RSP_CERR_SET3(1U)
37262 #define V_PRE_MP_RSP_CERR_SET2(x) ((x) << S_PRE_MP_RSP_CERR_SET2)
37263 #define F_PRE_MP_RSP_CERR_SET2    V_PRE_MP_RSP_CERR_SET2(1U)
37266 #define V_PRE_MP_RSP_CERR_SET1(x) ((x) << S_PRE_MP_RSP_CERR_SET1)
37267 #define F_PRE_MP_RSP_CERR_SET1    V_PRE_MP_RSP_CERR_SET1(1U)
37270 #define V_PRE_MP_RSP_CERR_SET0(x) ((x) << S_PRE_MP_RSP_CERR_SET0)
37271 #define F_PRE_MP_RSP_CERR_SET0    V_PRE_MP_RSP_CERR_SET0(1U)
37274 #define V_DDR_HDR_FIFO_CERR_SET3(x) ((x) << S_DDR_HDR_FIFO_CERR_SET3)
37275 #define F_DDR_HDR_FIFO_CERR_SET3    V_DDR_HDR_FIFO_CERR_SET3(1U)
37278 #define V_DDR_HDR_FIFO_CERR_SET2(x) ((x) << S_DDR_HDR_FIFO_CERR_SET2)
37279 #define F_DDR_HDR_FIFO_CERR_SET2    V_DDR_HDR_FIFO_CERR_SET2(1U)
37282 #define V_DDR_HDR_FIFO_CERR_SET1(x) ((x) << S_DDR_HDR_FIFO_CERR_SET1)
37283 #define F_DDR_HDR_FIFO_CERR_SET1    V_DDR_HDR_FIFO_CERR_SET1(1U)
37286 #define V_DDR_HDR_FIFO_CERR_SET0(x) ((x) << S_DDR_HDR_FIFO_CERR_SET0)
37287 #define F_DDR_HDR_FIFO_CERR_SET0    V_DDR_HDR_FIFO_CERR_SET0(1U)
37290 #define V_CMD_FIFO_CERR_SET3(x) ((x) << S_CMD_FIFO_CERR_SET3)
37291 #define F_CMD_FIFO_CERR_SET3    V_CMD_FIFO_CERR_SET3(1U)
37294 #define V_CMD_FIFO_CERR_SET2(x) ((x) << S_CMD_FIFO_CERR_SET2)
37295 #define F_CMD_FIFO_CERR_SET2    V_CMD_FIFO_CERR_SET2(1U)
37298 #define V_CMD_FIFO_CERR_SET1(x) ((x) << S_CMD_FIFO_CERR_SET1)
37299 #define F_CMD_FIFO_CERR_SET1    V_CMD_FIFO_CERR_SET1(1U)
37302 #define V_CMD_FIFO_CERR_SET0(x) ((x) << S_CMD_FIFO_CERR_SET0)
37303 #define F_CMD_FIFO_CERR_SET0    V_CMD_FIFO_CERR_SET0(1U)
37306 #define V_GF_SGE_FIFO_CORERR3(x) ((x) << S_GF_SGE_FIFO_CORERR3)
37307 #define F_GF_SGE_FIFO_CORERR3    V_GF_SGE_FIFO_CORERR3(1U)
37310 #define V_GF_SGE_FIFO_CORERR2(x) ((x) << S_GF_SGE_FIFO_CORERR2)
37311 #define F_GF_SGE_FIFO_CORERR2    V_GF_SGE_FIFO_CORERR2(1U)
37314 #define V_GF_SGE_FIFO_CORERR1(x) ((x) << S_GF_SGE_FIFO_CORERR1)
37315 #define F_GF_SGE_FIFO_CORERR1    V_GF_SGE_FIFO_CORERR1(1U)
37318 #define V_GF_SGE_FIFO_CORERR0(x) ((x) << S_GF_SGE_FIFO_CORERR0)
37319 #define F_GF_SGE_FIFO_CORERR0    V_GF_SGE_FIFO_CORERR0(1U)
37322 #define V_DEDUPE_SGE_FIFO_CORERR3(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR3)
37323 #define F_DEDUPE_SGE_FIFO_CORERR3    V_DEDUPE_SGE_FIFO_CORERR3(1U)
37326 #define V_DEDUPE_SGE_FIFO_CORERR2(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR2)
37327 #define F_DEDUPE_SGE_FIFO_CORERR2    V_DEDUPE_SGE_FIFO_CORERR2(1U)
37330 #define V_DEDUPE_SGE_FIFO_CORERR1(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR1)
37331 #define F_DEDUPE_SGE_FIFO_CORERR1    V_DEDUPE_SGE_FIFO_CORERR1(1U)
37333 #define S_DEDUPE_SGE_FIFO_CORERR0    1
37334 #define V_DEDUPE_SGE_FIFO_CORERR0(x) ((x) << S_DEDUPE_SGE_FIFO_CORERR0)
37335 #define F_DEDUPE_SGE_FIFO_CORERR0    V_DEDUPE_SGE_FIFO_CORERR0(1U)
37338 #define V_RSP_FIFO_CERR_SET(x) ((x) << S_RSP_FIFO_CERR_SET)
37339 #define F_RSP_FIFO_CERR_SET    V_RSP_FIFO_CERR_SET(1U)
37379 #define V_LA_WR0(x) ((x) << S_LA_WR0)
37380 #define F_LA_WR0    V_LA_WR0(1U)
37390 #define V_BYPASS_FIRST(x) ((x) << S_BYPASS_FIRST)
37391 #define F_BYPASS_FIRST    V_BYPASS_FIRST(1U)
37394 #define V_BYPASS_MIDDLE(x) ((x) << S_BYPASS_MIDDLE)
37395 #define F_BYPASS_MIDDLE    V_BYPASS_MIDDLE(1U)
37398 #define V_BYPASS_LAST(x) ((x) << S_BYPASS_LAST)
37399 #define F_BYPASS_LAST    V_BYPASS_LAST(1U)
37402 #define V_PUSH_FIRST(x) ((x) << S_PUSH_FIRST)
37403 #define F_PUSH_FIRST    V_PUSH_FIRST(1U)
37406 #define V_PUSH_MIDDLE(x) ((x) << S_PUSH_MIDDLE)
37407 #define F_PUSH_MIDDLE    V_PUSH_MIDDLE(1U)
37410 #define V_PUSH_LAST(x) ((x) << S_PUSH_LAST)
37411 #define F_PUSH_LAST    V_PUSH_LAST(1U)
37414 #define V_SAVE_FIRST(x) ((x) << S_SAVE_FIRST)
37415 #define F_SAVE_FIRST    V_SAVE_FIRST(1U)
37418 #define V_SAVE_MIDDLE(x) ((x) << S_SAVE_MIDDLE)
37419 #define F_SAVE_MIDDLE    V_SAVE_MIDDLE(1U)
37422 #define V_SAVE_LAST(x) ((x) << S_SAVE_LAST)
37423 #define F_SAVE_LAST    V_SAVE_LAST(1U)
37426 #define V_FLUSH_FIRST(x) ((x) << S_FLUSH_FIRST)
37427 #define F_FLUSH_FIRST    V_FLUSH_FIRST(1U)
37430 #define V_FLUSH_MIDDLE(x) ((x) << S_FLUSH_MIDDLE)
37431 #define F_FLUSH_MIDDLE    V_FLUSH_MIDDLE(1U)
37434 #define V_FLUSH_LAST(x) ((x) << S_FLUSH_LAST)
37435 #define F_FLUSH_LAST    V_FLUSH_LAST(1U)
37438 #define V_URGENT_FIRST(x) ((x) << S_URGENT_FIRST)
37439 #define F_URGENT_FIRST    V_URGENT_FIRST(1U)
37442 #define V_URGENT_MIDDLE(x) ((x) << S_URGENT_MIDDLE)
37443 #define F_URGENT_MIDDLE    V_URGENT_MIDDLE(1U)
37446 #define V_URGENT_LAST(x) ((x) << S_URGENT_LAST)
37447 #define F_URGENT_LAST    V_URGENT_LAST(1U)
37450 #define V_MORE_FIRST(x) ((x) << S_MORE_FIRST)
37451 #define F_MORE_FIRST    V_MORE_FIRST(1U)
37454 #define V_MORE_MIDDLE(x) ((x) << S_MORE_MIDDLE)
37455 #define F_MORE_MIDDLE    V_MORE_MIDDLE(1U)
37458 #define V_MORE_LAST(x) ((x) << S_MORE_LAST)
37459 #define F_MORE_LAST    V_MORE_LAST(1U)
37462 #define V_SHOVE_FIRST(x) ((x) << S_SHOVE_FIRST)
37463 #define F_SHOVE_FIRST    V_SHOVE_FIRST(1U)
37465 #define S_SHOVE_MIDDLE    1
37466 #define V_SHOVE_MIDDLE(x) ((x) << S_SHOVE_MIDDLE)
37467 #define F_SHOVE_MIDDLE    V_SHOVE_MIDDLE(1U)
37470 #define V_SHOVE_LAST(x) ((x) << S_SHOVE_LAST)
37471 #define F_SHOVE_LAST    V_SHOVE_LAST(1U)
37477 #define V_FIFO_THRESHOLD(x) ((x) << S_FIFO_THRESHOLD)
37478 #define G_FIFO_THRESHOLD(x) (((x) >> S_FIFO_THRESHOLD) & M_FIFO_THRESHOLD)
37481 #define V_COMPRESSION_XP10DISABLECFUSE(x) ((x) << S_COMPRESSION_XP10DISABLECFUSE)
37482 #define F_COMPRESSION_XP10DISABLECFUSE    V_COMPRESSION_XP10DISABLECFUSE(1U)
37485 #define V_COMPRESSION_XP10DISABLE(x) ((x) << S_COMPRESSION_XP10DISABLE)
37486 #define F_COMPRESSION_XP10DISABLE    V_COMPRESSION_XP10DISABLE(1U)
37489 #define V_DEDUPEDISABLECFUSE(x) ((x) << S_DEDUPEDISABLECFUSE)
37490 #define F_DEDUPEDISABLECFUSE    V_DEDUPEDISABLECFUSE(1U)
37493 #define V_DEDUPEDISABLE(x) ((x) << S_DEDUPEDISABLE)
37494 #define F_DEDUPEDISABLE    V_DEDUPEDISABLE(1U)
37496 #define S_GFDISABLECFUSE    1
37497 #define V_GFDISABLECFUSE(x) ((x) << S_GFDISABLECFUSE)
37498 #define F_GFDISABLECFUSE    V_GFDISABLECFUSE(1U)
37501 #define V_GFDISABLE(x) ((x) << S_GFDISABLE)
37502 #define F_GFDISABLE    V_GFDISABLE(1U)
37507 #define V_XP10_CONTROL(x) ((x) << S_XP10_CONTROL)
37508 #define F_XP10_CONTROL    V_XP10_CONTROL(1U)
37512 #define V_XP10_ADDR(x) ((x) << S_XP10_ADDR)
37513 #define G_XP10_ADDR(x) (((x) >> S_XP10_ADDR) & M_XP10_ADDR)
37520 #define V_RDMA_VERIFY_RESPONSE(x) ((x) << S_RDMA_VERIFY_RESPONSE)
37521 #define G_RDMA_VERIFY_RESPONSE(x) (((x) >> S_RDMA_VERIFY_RESPONSE) & M_RDMA_VERIFY_RESPONSE)
37525 #define V_RDMA_VERIFY_REQUEST(x) ((x) << S_RDMA_VERIFY_REQUEST)
37526 #define G_RDMA_VERIFY_REQUEST(x) (((x) >> S_RDMA_VERIFY_REQUEST) & M_RDMA_VERIFY_REQUEST)
37530 #define V_RDMA_FLUSH_RESPONSE(x) ((x) << S_RDMA_FLUSH_RESPONSE)
37531 #define G_RDMA_FLUSH_RESPONSE(x) (((x) >> S_RDMA_FLUSH_RESPONSE) & M_RDMA_FLUSH_RESPONSE)
37535 #define V_RDMA_FLUSH_REQUEST(x) ((x) << S_RDMA_FLUSH_REQUEST)
37536 #define G_RDMA_FLUSH_REQUEST(x) (((x) >> S_RDMA_FLUSH_REQUEST) & M_RDMA_FLUSH_REQUEST)
37542 #define V_RDMA_SEND_WITH_SE_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_SE_IMMEDIATE)
37543 #define G_RDMA_SEND_WITH_SE_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_SE_IMMEDIATE) & M_RDMA_SEND_WITH_SE_IMMEDIATE)
37547 #define V_RDMA_SEND_WITH_IMMEDIATE(x) ((x) << S_RDMA_SEND_WITH_IMMEDIATE)
37548 #define G_RDMA_SEND_WITH_IMMEDIATE(x) (((x) >> S_RDMA_SEND_WITH_IMMEDIATE) & M_RDMA_SEND_WITH_IMMEDIATE)
37552 #define V_RDMA_ATOMIC_WRITE_RESPONSE(x) ((x) << S_RDMA_ATOMIC_WRITE_RESPONSE)
37553 #define G_RDMA_ATOMIC_WRITE_RESPONSE(x) (((x) >> S_RDMA_ATOMIC_WRITE_RESPONSE) & M_RDMA_ATOMIC_WRITE_RESPONSE)
37557 #define V_RDMA_ATOMIC_WRITE_REQUEST(x) ((x) << S_RDMA_ATOMIC_WRITE_REQUEST)
37558 #define G_RDMA_ATOMIC_WRITE_REQUEST(x) (((x) >> S_RDMA_ATOMIC_WRITE_REQUEST) & M_RDMA_ATOMIC_WRITE_REQUEST)
37568 #define V_TLS_TX_REG_OFF_ADDR(x) ((x) << S_TLS_TX_REG_OFF_ADDR)
37569 #define G_TLS_TX_REG_OFF_ADDR(x) (((x) >> S_TLS_TX_REG_OFF_ADDR) & M_TLS_TX_REG_OFF_ADDR)
37577 #define V_GLUE_PERR(x) ((x) << S_GLUE_PERR)
37578 #define F_GLUE_PERR    V_GLUE_PERR(1U)
37581 #define V_DSGL_PERR(x) ((x) << S_DSGL_PERR)
37582 #define F_DSGL_PERR    V_DSGL_PERR(1U)
37584 #define S_SGE_PERR    1
37585 #define V_SGE_PERR(x) ((x) << S_SGE_PERR)
37586 #define F_SGE_PERR    V_SGE_PERR(1U)
37589 #define V_KEX_PERR(x) ((x) << S_KEX_PERR)
37590 #define F_KEX_PERR    V_KEX_PERR(1U)
37597 #define V_HMAC_CFG6(x) ((x) << S_HMAC_CFG6)
37598 #define G_HMAC_CFG6(x) (((x) >> S_HMAC_CFG6) & M_HMAC_CFG6)
37602 #define V_HMAC_CFG5(x) ((x) << S_HMAC_CFG5)
37603 #define G_HMAC_CFG5(x) (((x) >> S_HMAC_CFG5) & M_HMAC_CFG5)
37607 #define V_HMAC_CFG4(x) ((x) << S_HMAC_CFG4)
37608 #define G_HMAC_CFG4(x) (((x) >> S_HMAC_CFG4) & M_HMAC_CFG4)
37621 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
37622 #define F_RX_USE_BUNDLE_LEN    V_RX_USE_BUNDLE_LEN(1U)
37625 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
37626 #define F_STAT_TO_CH    V_STAT_TO_CH(1U)
37628 #define S_STAT_FROM_CH    1
37630 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
37631 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
37634 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
37635 #define F_PREFETCH_ENABLE    V_PREFETCH_ENABLE(1U)
37638 #define V_CACHE_HOLD(x) ((x) << S_CACHE_HOLD)
37639 #define F_CACHE_HOLD    V_CACHE_HOLD(1U)
37642 #define V_CACHE_INIT_DONE(x) ((x) << S_CACHE_INIT_DONE)
37643 #define F_CACHE_INIT_DONE    V_CACHE_INIT_DONE(1U)
37647 #define V_CACHE_DEPTH(x) ((x) << S_CACHE_DEPTH)
37648 #define G_CACHE_DEPTH(x) (((x) >> S_CACHE_DEPTH) & M_CACHE_DEPTH)
37651 #define V_CACHE_INIT(x) ((x) << S_CACHE_INIT)
37652 #define F_CACHE_INIT    V_CACHE_INIT(1U)
37655 #define V_CACHE_SLEEP(x) ((x) << S_CACHE_SLEEP)
37656 #define F_CACHE_SLEEP    V_CACHE_SLEEP(1U)
37659 #define V_CACHE_BYPASS(x) ((x) << S_CACHE_BYPASS)
37660 #define F_CACHE_BYPASS    V_CACHE_BYPASS(1U)
37669 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
37670 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
37674 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
37675 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
37679 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
37680 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
37684 #define V_T7_OSPIWRBUSY_T5(x) ((x) << S_T7_OSPIWRBUSY_T5)
37685 #define G_T7_OSPIWRBUSY_T5(x) (((x) >> S_T7_OSPIWRBUSY_T5) & M_T7_OSPIWRBUSY_T5)
37692 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
37693 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
37696 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
37697 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
37700 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
37701 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
37704 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
37705 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
37708 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
37709 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
37712 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
37713 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
37716 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
37717 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
37720 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
37721 #define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)
37724 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
37725 #define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)
37728 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
37729 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
37732 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
37733 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
37736 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
37737 #define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)
37740 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
37741 #define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)
37744 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
37745 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
37748 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
37749 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
37752 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
37753 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
37756 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
37757 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
37760 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
37761 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
37764 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
37765 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
37768 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
37769 #define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)
37772 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
37773 #define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)
37775 #define S_IESPI_PAR_ERROR    1
37776 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
37777 #define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)
37780 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
37781 #define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)
37784 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
37785 #define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)
37788 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
37789 #define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)
37792 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
37793 #define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)
37796 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
37797 #define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)
37800 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
37801 #define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)
37804 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
37805 #define F_SDC_ERR    V_SDC_ERR(1U)
37808 #define V_MASTER_PERR(x) ((x) << S_MASTER_PERR)
37809 #define F_MASTER_PERR    V_MASTER_PERR(1U)
37812 #define V_T7_OSPI_OVERFLOW3(x) ((x) << S_T7_OSPI_OVERFLOW3)
37813 #define F_T7_OSPI_OVERFLOW3    V_T7_OSPI_OVERFLOW3(1U)
37816 #define V_T7_OSPI_OVERFLOW2(x) ((x) << S_T7_OSPI_OVERFLOW2)
37817 #define F_T7_OSPI_OVERFLOW2    V_T7_OSPI_OVERFLOW2(1U)
37822 #define V_CACHE_SRAM_ERROR(x) ((x) << S_CACHE_SRAM_ERROR)
37823 #define F_CACHE_SRAM_ERROR    V_CACHE_SRAM_ERROR(1U)
37826 #define V_CACHE_LRU_ERROR(x) ((x) << S_CACHE_LRU_ERROR)
37827 #define F_CACHE_LRU_ERROR    V_CACHE_LRU_ERROR(1U)
37829 #define S_CACHE_ISLAND_ERROR    1
37830 #define V_CACHE_ISLAND_ERROR(x) ((x) << S_CACHE_ISLAND_ERROR)
37831 #define F_CACHE_ISLAND_ERROR    V_CACHE_ISLAND_ERROR(1U)
37834 #define V_CACHE_CTRL_ERROR(x) ((x) << S_CACHE_CTRL_ERROR)
37835 #define F_CACHE_CTRL_ERROR    V_CACHE_CTRL_ERROR(1U)
37862 #define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
37863 #define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
37867 #define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
37868 #define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
37872 #define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
37873 #define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
37877 #define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
37878 #define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
37883 #define V_SDC_EN(x) ((x) << S_SDC_EN)
37884 #define F_SDC_EN    V_SDC_EN(1U)
37889 #define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
37890 #define F_CHNL_3_SEL    V_CHNL_3_SEL(1U)
37893 #define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
37894 #define F_CHNL_2_SEL    V_CHNL_2_SEL(1U)
37896 #define S_CHNL_1_SEL    1
37897 #define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
37898 #define F_CHNL_1_SEL    V_CHNL_1_SEL(1U)
37901 #define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
37902 #define F_CHNL_0_SEL    V_CHNL_0_SEL(1U)
37907 #define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
37908 #define F_O_FIFO_WRITE    V_O_FIFO_WRITE(1U)
37911 #define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
37912 #define F_I_FIFO_WRITE    V_I_FIFO_WRITE(1U)
37914 #define S_O_FIFO_READ    1
37915 #define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
37916 #define F_O_FIFO_READ    V_O_FIFO_READ(1U)
37919 #define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
37920 #define F_I_FIFO_READ    V_I_FIFO_READ(1U)
37925 #define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
37926 #define F_ISPI_STR_FWD_EN    V_ISPI_STR_FWD_EN(1U)
37931 #define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
37932 #define F_PRFTCH_ACROSS_BNDLE_EN    V_PRFTCH_ACROSS_BNDLE_EN(1U)
37937 #define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
37938 #define F_PRFTCH_WRR_ENABLE    V_PRFTCH_WRR_ENABLE(1U)
37944 #define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
37945 #define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
37949 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
37950 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
37956 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
37957 #define F_PIO_CH_DEFICIT_CTL_EN_RX    V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
37963 #define V_CHNL3_MAX_DEFICIT_CNT(x) ((x) << S_CHNL3_MAX_DEFICIT_CNT)
37964 #define G_CHNL3_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL3_MAX_DEFICIT_CNT) & M_CHNL3_MAX_DEFICIT_CNT)
37968 #define V_CHNL2_MAX_DEFICIT_CNT(x) ((x) << S_CHNL2_MAX_DEFICIT_CNT)
37969 #define G_CHNL2_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL2_MAX_DEFICIT_CNT) & M_CHNL2_MAX_DEFICIT_CNT)
37975 #define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
37976 #define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
37982 #define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
37983 #define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
37989 #define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
37990 #define F_RX_RD_I_BUSY    V_RX_RD_I_BUSY(1U)
37993 #define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
37994 #define F_RX_WR_TO_O_BUSY    V_RX_WR_TO_O_BUSY(1U)
37997 #define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
37998 #define F_RX_M_TO_O_BUSY    V_RX_M_TO_O_BUSY(1U)
38001 #define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
38002 #define F_RX_I_TO_M_BUSY    V_RX_I_TO_M_BUSY(1U)
38005 #define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
38006 #define F_RX_PCMD_FB_ONLY    V_RX_PCMD_FB_ONLY(1U)
38009 #define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
38010 #define F_RX_PCMD_MEM    V_RX_PCMD_MEM(1U)
38013 #define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
38014 #define F_RX_PCMD_BYPASS    V_RX_PCMD_BYPASS(1U)
38017 #define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
38018 #define F_RX_PCMD_EOP    V_RX_PCMD_EOP(1U)
38021 #define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
38022 #define F_RX_DUMPLICATE_PCMD_EOP    V_RX_DUMPLICATE_PCMD_EOP(1U)
38025 #define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
38026 #define F_RX_PCMD_EOB    V_RX_PCMD_EOB(1U)
38030 #define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
38031 #define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
38035 #define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
38036 #define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
38041 #define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
38042 #define F_RX_PCMD0_MEM    V_RX_PCMD0_MEM(1U)
38046 #define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
38047 #define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
38051 #define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
38052 #define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
38056 #define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
38057 #define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
38059 #define S_RX_OFIFO_FULL0    1
38060 #define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
38061 #define F_RX_OFIFO_FULL0    V_RX_OFIFO_FULL0(1U)
38064 #define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
38065 #define F_RX_PCMD0_BYPASS    V_RX_PCMD0_BYPASS(1U)
38070 #define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
38071 #define F_RX_PCMD1_MEM    V_RX_PCMD1_MEM(1U)
38075 #define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
38076 #define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
38080 #define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
38081 #define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
38085 #define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
38086 #define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
38088 #define S_RX_OFIFO_FULL1    1
38089 #define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
38090 #define F_RX_OFIFO_FULL1    V_RX_OFIFO_FULL1(1U)
38093 #define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
38094 #define F_RX_PCMD1_BYPASS    V_RX_PCMD1_BYPASS(1U)
38100 #define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
38101 #define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
38105 #define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
38106 #define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
38110 #define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
38111 #define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
38115 #define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
38116 #define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
38119 #define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
38120 #define F_RX_DB_VLD    V_RX_DB_VLD(1U)
38122 #define S_RX_FIRST_BUNDLE    1
38124 #define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
38125 #define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
38128 #define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
38129 #define F_RX_SDC_DRDY    V_RX_SDC_DRDY(1U)
38134 #define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
38135 #define F_RX_PCMD_VLD    V_RX_PCMD_VLD(1U)
38138 #define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
38139 #define F_RX_PCMD_TO_CH    V_RX_PCMD_TO_CH(1U)
38143 #define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
38144 #define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
38148 #define V_RX_LINE(x) ((x) << S_RX_LINE)
38149 #define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
38153 #define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
38154 #define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
38158 #define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
38159 #define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
38163 #define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
38164 #define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
38168 #define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
38169 #define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
38173 #define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
38174 #define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
38178 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
38179 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
38183 #define V_RX_PCMD_SRDY_STAT4(x) ((x) << S_RX_PCMD_SRDY_STAT4)
38184 #define G_RX_PCMD_SRDY_STAT4(x) (((x) >> S_RX_PCMD_SRDY_STAT4) & M_RX_PCMD_SRDY_STAT4)
38188 #define V_RX_PCMD_DRDY_STAT4(x) ((x) << S_RX_PCMD_DRDY_STAT4)
38189 #define G_RX_PCMD_DRDY_STAT4(x) (((x) >> S_RX_PCMD_DRDY_STAT4) & M_RX_PCMD_DRDY_STAT4)
38194 #define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
38195 #define F_RX_ATLST_1_PCMD_CH1    V_RX_ATLST_1_PCMD_CH1(1U)
38198 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
38199 #define F_RX_ATLST_1_PCMD_CH0    V_RX_ATLST_1_PCMD_CH0(1U)
38203 #define V_T5_RX_PCMD_DRDY(x) ((x) << S_T5_RX_PCMD_DRDY)
38204 #define G_T5_RX_PCMD_DRDY(x) (((x) >> S_T5_RX_PCMD_DRDY) & M_T5_RX_PCMD_DRDY)
38208 #define V_T5_RX_PCMD_SRDY(x) ((x) << S_T5_RX_PCMD_SRDY)
38209 #define G_T5_RX_PCMD_SRDY(x) (((x) >> S_T5_RX_PCMD_SRDY) & M_T5_RX_PCMD_SRDY)
38213 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
38214 #define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
38218 #define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
38219 #define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
38223 #define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
38224 #define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
38228 #define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
38229 #define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
38233 #define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
38234 #define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
38238 #define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
38239 #define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
38243 #define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
38244 #define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
38248 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
38249 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
38255 #define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
38256 #define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
38259 #define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
38260 #define F_RX_M_REQADDRRDY    V_RX_M_REQADDRRDY(1U)
38263 #define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
38264 #define F_RX_M_REQWRITE    V_RX_M_REQWRITE(1U)
38266 #define S_RX_M_REQDATAVLD    1
38267 #define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
38268 #define F_RX_M_REQDATAVLD    V_RX_M_REQDATAVLD(1U)
38271 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
38272 #define F_RX_M_REQDATARDY    V_RX_M_REQDATARDY(1U)
38276 #define V_T6_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_T6_RX_M_INTRNL_FIFO_CNT)
38277 #define G_T6_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_T6_RX_M_INTRNL_FIFO_CNT) & M_T6_RX_M_INTRNL_FIFO_CNT)
38280 #define V_RX_M_RSPVLD(x) ((x) << S_RX_M_RSPVLD)
38281 #define F_RX_M_RSPVLD    V_RX_M_RSPVLD(1U)
38284 #define V_RX_M_RSPRDY(x) ((x) << S_RX_M_RSPRDY)
38285 #define F_RX_M_RSPRDY    V_RX_M_RSPRDY(1U)
38288 #define V_RX_M_REQADDRVLD(x) ((x) << S_RX_M_REQADDRVLD)
38289 #define F_RX_M_REQADDRVLD    V_RX_M_REQADDRVLD(1U)
38295 #define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
38296 #define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
38300 #define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
38301 #define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
38307 #define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
38308 #define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
38312 #define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
38313 #define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
38317 #define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
38318 #define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
38322 #define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
38323 #define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
38327 #define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
38328 #define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
38332 #define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
38333 #define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
38337 #define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
38338 #define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
38342 #define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
38343 #define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
38349 #define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
38350 #define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
38354 #define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
38355 #define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
38359 #define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
38360 #define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
38364 #define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
38365 #define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
38369 #define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
38370 #define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
38374 #define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
38375 #define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
38379 #define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
38380 #define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
38384 #define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
38385 #define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
38390 #define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
38391 #define F_RX_CH_DEFICIT_BLOWED    V_RX_CH_DEFICIT_BLOWED(1U)
38395 #define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
38396 #define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
38400 #define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
38401 #define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
38407 #define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
38408 #define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
38412 #define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
38413 #define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
38417 #define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
38418 #define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
38422 #define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
38423 #define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
38427 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
38428 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
38434 #define V_CACHE_SRAM_ODD_CERR(x) ((x) << S_CACHE_SRAM_ODD_CERR)
38435 #define F_CACHE_SRAM_ODD_CERR    V_CACHE_SRAM_ODD_CERR(1U)
38438 #define V_CACHE_SRAM_EVEN_CERR(x) ((x) << S_CACHE_SRAM_EVEN_CERR)
38439 #define F_CACHE_SRAM_EVEN_CERR    V_CACHE_SRAM_EVEN_CERR(1U)
38442 #define V_CACHE_LRU_LEFT_CERR(x) ((x) << S_CACHE_LRU_LEFT_CERR)
38443 #define F_CACHE_LRU_LEFT_CERR    V_CACHE_LRU_LEFT_CERR(1U)
38446 #define V_CACHE_LRU_RIGHT_CERR(x) ((x) << S_CACHE_LRU_RIGHT_CERR)
38447 #define F_CACHE_LRU_RIGHT_CERR    V_CACHE_LRU_RIGHT_CERR(1U)
38450 #define V_CACHE_ISLAND_CERR(x) ((x) << S_CACHE_ISLAND_CERR)
38451 #define F_CACHE_ISLAND_CERR    V_CACHE_ISLAND_CERR(1U)
38454 #define V_OCSPI_CERR(x) ((x) << S_OCSPI_CERR)
38455 #define F_OCSPI_CERR    V_OCSPI_CERR(1U)
38458 #define V_IESPI_CERR(x) ((x) << S_IESPI_CERR)
38459 #define F_IESPI_CERR    V_IESPI_CERR(1U)
38462 #define V_OCSPI2_RX_FRAMING_ERROR(x) ((x) << S_OCSPI2_RX_FRAMING_ERROR)
38463 #define F_OCSPI2_RX_FRAMING_ERROR    V_OCSPI2_RX_FRAMING_ERROR(1U)
38466 #define V_OCSPI3_RX_FRAMING_ERROR(x) ((x) << S_OCSPI3_RX_FRAMING_ERROR)
38467 #define F_OCSPI3_RX_FRAMING_ERROR    V_OCSPI3_RX_FRAMING_ERROR(1U)
38470 #define V_OCSPI2_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_TX_FRAMING_ERROR)
38471 #define F_OCSPI2_TX_FRAMING_ERROR    V_OCSPI2_TX_FRAMING_ERROR(1U)
38474 #define V_OCSPI3_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_TX_FRAMING_ERROR)
38475 #define F_OCSPI3_TX_FRAMING_ERROR    V_OCSPI3_TX_FRAMING_ERROR(1U)
38477 #define S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    1
38478 #define V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI2_OFIFO2X_TX_FRAMING_ERROR)
38479 #define F_OCSPI2_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38482 #define V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR)
38483 #define F_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38489 #define V_T7_SDC_ERR(x) ((x) << S_T7_SDC_ERR)
38490 #define F_T7_SDC_ERR    V_T7_SDC_ERR(1U)
38493 #define V_T7_MA_INTF_SDC_ERR(x) ((x) << S_T7_MA_INTF_SDC_ERR)
38494 #define F_T7_MA_INTF_SDC_ERR    V_T7_MA_INTF_SDC_ERR(1U)
38497 #define V_E_PCMD_PERR(x) ((x) << S_E_PCMD_PERR)
38498 #define F_E_PCMD_PERR    V_E_PCMD_PERR(1U)
38501 #define V_CACHE_RSP_DFIFO_PERR(x) ((x) << S_CACHE_RSP_DFIFO_PERR)
38502 #define F_CACHE_RSP_DFIFO_PERR    V_CACHE_RSP_DFIFO_PERR(1U)
38505 #define V_CACHE_SRAM_ODD_PERR(x) ((x) << S_CACHE_SRAM_ODD_PERR)
38506 #define F_CACHE_SRAM_ODD_PERR    V_CACHE_SRAM_ODD_PERR(1U)
38509 #define V_CACHE_SRAM_EVEN_PERR(x) ((x) << S_CACHE_SRAM_EVEN_PERR)
38510 #define F_CACHE_SRAM_EVEN_PERR    V_CACHE_SRAM_EVEN_PERR(1U)
38513 #define V_CACHE_RSVD_PERR(x) ((x) << S_CACHE_RSVD_PERR)
38514 #define F_CACHE_RSVD_PERR    V_CACHE_RSVD_PERR(1U)
38517 #define V_CACHE_LRU_LEFT_PERR(x) ((x) << S_CACHE_LRU_LEFT_PERR)
38518 #define F_CACHE_LRU_LEFT_PERR    V_CACHE_LRU_LEFT_PERR(1U)
38521 #define V_CACHE_LRU_RIGHT_PERR(x) ((x) << S_CACHE_LRU_RIGHT_PERR)
38522 #define F_CACHE_LRU_RIGHT_PERR    V_CACHE_LRU_RIGHT_PERR(1U)
38525 #define V_CACHE_RSP_CMD_PERR(x) ((x) << S_CACHE_RSP_CMD_PERR)
38526 #define F_CACHE_RSP_CMD_PERR    V_CACHE_RSP_CMD_PERR(1U)
38529 #define V_CACHE_SRAM_CMD_PERR(x) ((x) << S_CACHE_SRAM_CMD_PERR)
38530 #define F_CACHE_SRAM_CMD_PERR    V_CACHE_SRAM_CMD_PERR(1U)
38533 #define V_CACHE_MA_CMD_PERR(x) ((x) << S_CACHE_MA_CMD_PERR)
38534 #define F_CACHE_MA_CMD_PERR    V_CACHE_MA_CMD_PERR(1U)
38537 #define V_CACHE_TCAM_PERR(x) ((x) << S_CACHE_TCAM_PERR)
38538 #define F_CACHE_TCAM_PERR    V_CACHE_TCAM_PERR(1U)
38541 #define V_CACHE_ISLAND_PERR(x) ((x) << S_CACHE_ISLAND_PERR)
38542 #define F_CACHE_ISLAND_PERR    V_CACHE_ISLAND_PERR(1U)
38545 #define V_MC_WCNT_FIFO_PERR(x) ((x) << S_MC_WCNT_FIFO_PERR)
38546 #define F_MC_WCNT_FIFO_PERR    V_MC_WCNT_FIFO_PERR(1U)
38549 #define V_MC_WDATA_FIFO_PERR(x) ((x) << S_MC_WDATA_FIFO_PERR)
38550 #define F_MC_WDATA_FIFO_PERR    V_MC_WDATA_FIFO_PERR(1U)
38553 #define V_MC_RCNT_FIFO_PERR(x) ((x) << S_MC_RCNT_FIFO_PERR)
38554 #define F_MC_RCNT_FIFO_PERR    V_MC_RCNT_FIFO_PERR(1U)
38557 #define V_MC_RDATA_FIFO_PERR(x) ((x) << S_MC_RDATA_FIFO_PERR)
38558 #define F_MC_RDATA_FIFO_PERR    V_MC_RDATA_FIFO_PERR(1U)
38561 #define V_TOKEN_FIFO_PERR(x) ((x) << S_TOKEN_FIFO_PERR)
38562 #define F_TOKEN_FIFO_PERR    V_TOKEN_FIFO_PERR(1U)
38565 #define V_T7_BUNDLE_LEN_PARERR(x) ((x) << S_T7_BUNDLE_LEN_PARERR)
38566 #define F_T7_BUNDLE_LEN_PARERR    V_T7_BUNDLE_LEN_PARERR(1U)
38573 #define V_CH1_PTR_MAX(x) ((x) << S_CH1_PTR_MAX)
38574 #define G_CH1_PTR_MAX(x) (((x) >> S_CH1_PTR_MAX) & M_CH1_PTR_MAX)
38576 #define S_CH0_PTR_MAX    1
38578 #define V_CH0_PTR_MAX(x) ((x) << S_CH0_PTR_MAX)
38579 #define G_CH0_PTR_MAX(x) (((x) >> S_CH0_PTR_MAX) & M_CH0_PTR_MAX)
38582 #define V_STROBE(x) ((x) << S_STROBE)
38583 #define F_STROBE    V_STROBE(1U)
38587 #define S_CH2_PTR_MAX    1
38589 #define V_CH2_PTR_MAX(x) ((x) << S_CH2_PTR_MAX)
38590 #define G_CH2_PTR_MAX(x) (((x) >> S_CH2_PTR_MAX) & M_CH2_PTR_MAX)
38610 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
38611 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
38617 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
38618 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
38622 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
38623 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
38627 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
38628 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
38632 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
38633 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
38636 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
38637 #define F_TX_USE_BUNDLE_LEN    V_TX_USE_BUNDLE_LEN(1U)
38639 #define S_STAT_CHANNEL    1
38641 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
38642 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
38651 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
38652 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
38659 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
38660 #define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)
38663 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
38664 #define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)
38667 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
38668 #define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)
38671 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
38672 #define F_ZERO_C_CMD_ERRO    V_ZERO_C_CMD_ERRO(1U)
38675 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
38676 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
38679 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
38680 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
38683 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
38684 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
38687 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
38688 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
38691 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
38692 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
38695 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
38696 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
38699 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
38700 #define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)
38703 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
38704 #define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)
38707 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
38708 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
38711 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
38712 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
38715 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
38716 #define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)
38719 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
38720 #define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)
38723 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
38724 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
38727 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
38728 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
38731 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
38732 #define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)
38735 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
38736 #define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)
38739 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
38740 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
38743 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
38744 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
38747 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
38748 #define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)
38751 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
38752 #define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)
38755 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
38756 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
38759 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
38760 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
38763 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
38764 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38767 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
38768 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38771 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
38772 #define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)
38774 #define S_ICSPI_PAR_ERROR    1
38775 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
38776 #define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)
38779 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
38780 #define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
38783 #define V_T7_ZERO_C_CMD_ERROR(x) ((x) << S_T7_ZERO_C_CMD_ERROR)
38784 #define F_T7_ZERO_C_CMD_ERROR    V_T7_ZERO_C_CMD_ERROR(1U)
38787 #define V_OESPI_COR_ERR(x) ((x) << S_OESPI_COR_ERR)
38788 #define F_OESPI_COR_ERR    V_OESPI_COR_ERR(1U)
38791 #define V_ICSPI_COR_ERR(x) ((x) << S_ICSPI_COR_ERR)
38792 #define F_ICSPI_COR_ERR    V_ICSPI_COR_ERR(1U)
38795 #define V_ICSPI_OVFL(x) ((x) << S_ICSPI_OVFL)
38796 #define F_ICSPI_OVFL    V_ICSPI_OVFL(1U)
38799 #define V_PCMD_LEN_OVFL3(x) ((x) << S_PCMD_LEN_OVFL3)
38800 #define F_PCMD_LEN_OVFL3    V_PCMD_LEN_OVFL3(1U)
38803 #define V_T7_PCMD_LEN_OVFL2(x) ((x) << S_T7_PCMD_LEN_OVFL2)
38804 #define F_T7_PCMD_LEN_OVFL2    V_T7_PCMD_LEN_OVFL2(1U)
38807 #define V_T7_PCMD_LEN_OVFL1(x) ((x) << S_T7_PCMD_LEN_OVFL1)
38808 #define F_T7_PCMD_LEN_OVFL1    V_T7_PCMD_LEN_OVFL1(1U)
38811 #define V_T7_PCMD_LEN_OVFL0(x) ((x) << S_T7_PCMD_LEN_OVFL0)
38812 #define F_T7_PCMD_LEN_OVFL0    V_T7_PCMD_LEN_OVFL0(1U)
38815 #define V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
38816 #define F_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
38819 #define V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
38820 #define F_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
38823 #define V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
38824 #define F_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
38827 #define V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
38828 #define F_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_T7_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
38831 #define V_T7_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI0_TX_FRAMING_ERROR)
38832 #define F_T7_ICSPI0_TX_FRAMING_ERROR    V_T7_ICSPI0_TX_FRAMING_ERROR(1U)
38835 #define V_T7_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI1_TX_FRAMING_ERROR)
38836 #define F_T7_ICSPI1_TX_FRAMING_ERROR    V_T7_ICSPI1_TX_FRAMING_ERROR(1U)
38839 #define V_T7_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI2_TX_FRAMING_ERROR)
38840 #define F_T7_ICSPI2_TX_FRAMING_ERROR    V_T7_ICSPI2_TX_FRAMING_ERROR(1U)
38843 #define V_T7_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_ICSPI3_TX_FRAMING_ERROR)
38844 #define F_T7_ICSPI3_TX_FRAMING_ERROR    V_T7_ICSPI3_TX_FRAMING_ERROR(1U)
38847 #define V_T7_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_RX_FRAMING_ERROR)
38848 #define F_T7_OESPI0_RX_FRAMING_ERROR    V_T7_OESPI0_RX_FRAMING_ERROR(1U)
38851 #define V_T7_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_RX_FRAMING_ERROR)
38852 #define F_T7_OESPI1_RX_FRAMING_ERROR    V_T7_OESPI1_RX_FRAMING_ERROR(1U)
38855 #define V_T7_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_RX_FRAMING_ERROR)
38856 #define F_T7_OESPI2_RX_FRAMING_ERROR    V_T7_OESPI2_RX_FRAMING_ERROR(1U)
38859 #define V_T7_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_RX_FRAMING_ERROR)
38860 #define F_T7_OESPI3_RX_FRAMING_ERROR    V_T7_OESPI3_RX_FRAMING_ERROR(1U)
38863 #define V_T7_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_TX_FRAMING_ERROR)
38864 #define F_T7_OESPI0_TX_FRAMING_ERROR    V_T7_OESPI0_TX_FRAMING_ERROR(1U)
38867 #define V_T7_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_TX_FRAMING_ERROR)
38868 #define F_T7_OESPI1_TX_FRAMING_ERROR    V_T7_OESPI1_TX_FRAMING_ERROR(1U)
38871 #define V_T7_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_TX_FRAMING_ERROR)
38872 #define F_T7_OESPI2_TX_FRAMING_ERROR    V_T7_OESPI2_TX_FRAMING_ERROR(1U)
38875 #define V_T7_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_TX_FRAMING_ERROR)
38876 #define F_T7_OESPI3_TX_FRAMING_ERROR    V_T7_OESPI3_TX_FRAMING_ERROR(1U)
38879 #define V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
38880 #define F_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
38883 #define V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
38884 #define F_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
38886 #define S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    1
38887 #define V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
38888 #define F_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
38891 #define V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
38892 #define F_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
38897 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
38898 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
38901 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
38902 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
38923 #define V_IN_AFULL_TH(x) ((x) << S_IN_AFULL_TH)
38924 #define G_IN_AFULL_TH(x) (((x) >> S_IN_AFULL_TH) & M_IN_AFULL_TH)
38927 #define V_PIO_FROM_CH_EN(x) ((x) << S_PIO_FROM_CH_EN)
38928 #define F_PIO_FROM_CH_EN    V_PIO_FROM_CH_EN(1U)
38968 #define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
38969 #define F_PIO_CH_DEFICIT_CTL_EN    V_PIO_CH_DEFICIT_CTL_EN(1U)
38971 #define S_PIO_WRR_BASED_PRFTCH_EN    1
38972 #define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
38973 #define F_PIO_WRR_BASED_PRFTCH_EN    V_PIO_WRR_BASED_PRFTCH_EN(1U)
38978 #define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
38979 #define F_OSPI_OVERFLOW3    V_OSPI_OVERFLOW3(1U)
38982 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
38983 #define F_OSPI_OVERFLOW2    V_OSPI_OVERFLOW2(1U)
38986 #define V_T5_OSPI_OVERFLOW1(x) ((x) << S_T5_OSPI_OVERFLOW1)
38987 #define F_T5_OSPI_OVERFLOW1    V_T5_OSPI_OVERFLOW1(1U)
38990 #define V_T5_OSPI_OVERFLOW0(x) ((x) << S_T5_OSPI_OVERFLOW0)
38991 #define F_T5_OSPI_OVERFLOW0    V_T5_OSPI_OVERFLOW0(1U)
38994 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
38995 #define F_M_INTFPERREN    V_M_INTFPERREN(1U)
38998 #define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
38999 #define F_BUNDLE_LEN_PARERR_EN    V_BUNDLE_LEN_PARERR_EN(1U)
39001 #define S_BUNDLE_LEN_OVFL_EN    1
39002 #define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
39003 #define F_BUNDLE_LEN_OVFL_EN    V_BUNDLE_LEN_OVFL_EN(1U)
39006 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
39007 #define F_SDC_ERR_EN    V_SDC_ERR_EN(1U)
39010 #define V_OSPI_OVERFLOW3_T5(x) ((x) << S_OSPI_OVERFLOW3_T5)
39011 #define F_OSPI_OVERFLOW3_T5    V_OSPI_OVERFLOW3_T5(1U)
39014 #define V_OSPI_OVERFLOW2_T5(x) ((x) << S_OSPI_OVERFLOW2_T5)
39015 #define F_OSPI_OVERFLOW2_T5    V_OSPI_OVERFLOW2_T5(1U)
39018 #define V_OSPI_OVERFLOW1_T5(x) ((x) << S_OSPI_OVERFLOW1_T5)
39019 #define F_OSPI_OVERFLOW1_T5    V_OSPI_OVERFLOW1_T5(1U)
39022 #define V_OSPI_OVERFLOW0_T5(x) ((x) << S_OSPI_OVERFLOW0_T5)
39023 #define F_OSPI_OVERFLOW0_T5    V_OSPI_OVERFLOW0_T5(1U)
39034 #define V_T7_1_OSPI_OVERFLOW3(x) ((x) << S_T7_1_OSPI_OVERFLOW3)
39035 #define F_T7_1_OSPI_OVERFLOW3    V_T7_1_OSPI_OVERFLOW3(1U)
39038 #define V_T7_1_OSPI_OVERFLOW2(x) ((x) << S_T7_1_OSPI_OVERFLOW2)
39039 #define F_T7_1_OSPI_OVERFLOW2    V_T7_1_OSPI_OVERFLOW2(1U)
39042 #define V_T7_1_OSPI_OVERFLOW1(x) ((x) << S_T7_1_OSPI_OVERFLOW1)
39043 #define F_T7_1_OSPI_OVERFLOW1    V_T7_1_OSPI_OVERFLOW1(1U)
39046 #define V_T7_1_OSPI_OVERFLOW0(x) ((x) << S_T7_1_OSPI_OVERFLOW0)
39047 #define F_T7_1_OSPI_OVERFLOW0    V_T7_1_OSPI_OVERFLOW0(1U)
39050 #define V_T7_BUNDLE_LEN_OVFL_EN(x) ((x) << S_T7_BUNDLE_LEN_OVFL_EN)
39051 #define F_T7_BUNDLE_LEN_OVFL_EN    V_T7_BUNDLE_LEN_OVFL_EN(1U)
39054 #define V_T7_M_INTFPERREN(x) ((x) << S_T7_M_INTFPERREN)
39055 #define F_T7_M_INTFPERREN    V_T7_M_INTFPERREN(1U)
39058 #define V_T7_1_SDC_ERR(x) ((x) << S_T7_1_SDC_ERR)
39059 #define F_T7_1_SDC_ERR    V_T7_1_SDC_ERR(1U)
39062 #define V_TOKEN_PAR_ERROR(x) ((x) << S_TOKEN_PAR_ERROR)
39063 #define F_TOKEN_PAR_ERROR    V_TOKEN_PAR_ERROR(1U)
39066 #define V_BUNDLE_LEN_PAR_ERROR(x) ((x) << S_BUNDLE_LEN_PAR_ERROR)
39067 #define F_BUNDLE_LEN_PAR_ERROR    V_BUNDLE_LEN_PAR_ERROR(1U)
39070 #define V_C_PCMD_TOKEN_PAR_ERROR(x) ((x) << S_C_PCMD_TOKEN_PAR_ERROR)
39071 #define F_C_PCMD_TOKEN_PAR_ERROR    V_C_PCMD_TOKEN_PAR_ERROR(1U)
39077 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
39078 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
39085 #define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
39086 #define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
39092 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
39093 #define F_RD_I_BUSY    V_RD_I_BUSY(1U)
39096 #define V_WR_O_BUSY(x) ((x) << S_WR_O_BUSY)
39097 #define F_WR_O_BUSY    V_WR_O_BUSY(1U)
39100 #define V_M_TO_O_BUSY(x) ((x) << S_M_TO_O_BUSY)
39101 #define F_M_TO_O_BUSY    V_M_TO_O_BUSY(1U)
39104 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
39105 #define F_I_TO_M_BUSY    V_I_TO_M_BUSY(1U)
39108 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
39109 #define F_PCMD_FB_ONLY    V_PCMD_FB_ONLY(1U)
39112 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
39113 #define F_PCMD_MEM    V_PCMD_MEM(1U)
39116 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
39117 #define F_PCMD_BYPASS    V_PCMD_BYPASS(1U)
39120 #define V_PCMD_EOP2(x) ((x) << S_PCMD_EOP2)
39121 #define F_PCMD_EOP2    V_PCMD_EOP2(1U)
39124 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
39125 #define F_PCMD_EOP    V_PCMD_EOP(1U)
39128 #define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
39129 #define F_PCMD_END_BUNDLE    V_PCMD_END_BUNDLE(1U)
39133 #define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
39134 #define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
39138 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
39139 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
39142 #define V_T6_RD_I_BUSY(x) ((x) << S_T6_RD_I_BUSY)
39143 #define F_T6_RD_I_BUSY    V_T6_RD_I_BUSY(1U)
39146 #define V_T6_WR_O_BUSY(x) ((x) << S_T6_WR_O_BUSY)
39147 #define F_T6_WR_O_BUSY    V_T6_WR_O_BUSY(1U)
39150 #define V_T6_M_TO_O_BUSY(x) ((x) << S_T6_M_TO_O_BUSY)
39151 #define F_T6_M_TO_O_BUSY    V_T6_M_TO_O_BUSY(1U)
39154 #define V_T6_I_TO_M_BUSY(x) ((x) << S_T6_I_TO_M_BUSY)
39155 #define F_T6_I_TO_M_BUSY    V_T6_I_TO_M_BUSY(1U)
39158 #define V_T6_PCMD_FB_ONLY(x) ((x) << S_T6_PCMD_FB_ONLY)
39159 #define F_T6_PCMD_FB_ONLY    V_T6_PCMD_FB_ONLY(1U)
39162 #define V_T6_PCMD_MEM(x) ((x) << S_T6_PCMD_MEM)
39163 #define F_T6_PCMD_MEM    V_T6_PCMD_MEM(1U)
39166 #define V_T6_PCMD_BYPASS(x) ((x) << S_T6_PCMD_BYPASS)
39167 #define F_T6_PCMD_BYPASS    V_T6_PCMD_BYPASS(1U)
39172 #define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
39173 #define F_PCMD_MEM0    V_PCMD_MEM0(1U)
39177 #define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
39178 #define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
39182 #define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
39183 #define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
39187 #define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
39188 #define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
39191 #define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
39192 #define F_OFIFO_FULL0    V_OFIFO_FULL0(1U)
39194 #define S_GCSUM_DRDY0    1
39195 #define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
39196 #define F_GCSUM_DRDY0    V_GCSUM_DRDY0(1U)
39199 #define V_BYPASS0(x) ((x) << S_BYPASS0)
39200 #define F_BYPASS0    V_BYPASS0(1U)
39205 #define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
39206 #define F_PCMD_MEM1    V_PCMD_MEM1(1U)
39210 #define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
39211 #define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
39215 #define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
39216 #define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
39220 #define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
39221 #define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
39224 #define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
39225 #define F_OFIFO_FULL1    V_OFIFO_FULL1(1U)
39227 #define S_GCSUM_DRDY1    1
39228 #define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
39229 #define F_GCSUM_DRDY1    V_GCSUM_DRDY1(1U)
39232 #define V_BYPASS1(x) ((x) << S_BYPASS1)
39233 #define F_BYPASS1    V_BYPASS1(1U)
39238 #define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
39239 #define F_PCMD_MEM2    V_PCMD_MEM2(1U)
39243 #define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
39244 #define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
39248 #define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
39249 #define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
39253 #define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
39254 #define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
39257 #define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
39258 #define F_OFIFO_FULL2    V_OFIFO_FULL2(1U)
39260 #define S_GCSUM_DRDY2    1
39261 #define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
39262 #define F_GCSUM_DRDY2    V_GCSUM_DRDY2(1U)
39265 #define V_BYPASS2(x) ((x) << S_BYPASS2)
39266 #define F_BYPASS2    V_BYPASS2(1U)
39271 #define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
39272 #define F_PCMD_MEM3    V_PCMD_MEM3(1U)
39276 #define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
39277 #define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
39281 #define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
39282 #define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
39286 #define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
39287 #define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
39290 #define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
39291 #define F_OFIFO_FULL3    V_OFIFO_FULL3(1U)
39293 #define S_GCSUM_DRDY3    1
39294 #define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
39295 #define F_GCSUM_DRDY3    V_GCSUM_DRDY3(1U)
39298 #define V_BYPASS3(x) ((x) << S_BYPASS3)
39299 #define F_BYPASS3    V_BYPASS3(1U)
39305 #define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
39306 #define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
39310 #define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
39311 #define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
39315 #define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
39316 #define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
39320 #define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
39321 #define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
39324 #define V_DB_VLD(x) ((x) << S_DB_VLD)
39325 #define F_DB_VLD    V_DB_VLD(1U)
39328 #define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
39329 #define F_INJECT0_DRDY    V_INJECT0_DRDY(1U)
39332 #define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
39333 #define F_INJECT1_DRDY    V_INJECT1_DRDY(1U)
39337 #define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
39338 #define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
39340 #define S_GCSUM_MORE_THAN_2_LEFT    1
39342 #define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
39343 #define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
39346 #define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
39347 #define F_SDC_DRDY    V_SDC_DRDY(1U)
39352 #define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
39353 #define F_PCMD_VLD    V_PCMD_VLD(1U)
39357 #define V_PCMD_CH(x) ((x) << S_PCMD_CH)
39358 #define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
39362 #define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
39363 #define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
39367 #define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
39368 #define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
39372 #define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
39373 #define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
39377 #define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
39378 #define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
39382 #define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
39383 #define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
39387 #define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
39388 #define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
39391 #define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
39392 #define F_OEFIFO_FULL3    V_OEFIFO_FULL3(1U)
39395 #define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
39396 #define F_OEFIFO_FULL2    V_OEFIFO_FULL2(1U)
39398 #define S_OEFIFO_FULL1    1
39399 #define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
39400 #define F_OEFIFO_FULL1    V_OEFIFO_FULL1(1U)
39403 #define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
39404 #define F_OEFIFO_FULL0    V_OEFIFO_FULL0(1U)
39410 #define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
39411 #define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
39415 #define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
39416 #define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
39420 #define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
39421 #define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
39425 #define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
39426 #define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
39430 #define V_C_RXVALID(x) ((x) << S_C_RXVALID)
39431 #define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
39435 #define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
39436 #define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
39439 #define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
39440 #define F_E_TXVALID3    V_E_TXVALID3(1U)
39443 #define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
39444 #define F_E_TXVALID2    V_E_TXVALID2(1U)
39447 #define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
39448 #define F_E_TXVALID1    V_E_TXVALID1(1U)
39451 #define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
39452 #define F_E_TXVALID0    V_E_TXVALID0(1U)
39455 #define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
39456 #define F_E_TXFULL3    V_E_TXFULL3(1U)
39459 #define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
39460 #define F_E_TXFULL2    V_E_TXFULL2(1U)
39462 #define S_E_TXFULL1    1
39463 #define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
39464 #define F_E_TXFULL1    V_E_TXFULL1(1U)
39467 #define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
39468 #define F_E_TXFULL0    V_E_TXFULL0(1U)
39474 #define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
39475 #define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
39479 #define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
39480 #define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
39484 #define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
39485 #define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
39488 #define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
39489 #define F_M_REQADDRRDY    V_M_REQADDRRDY(1U)
39492 #define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
39493 #define F_M_REQWRITE    V_M_REQWRITE(1U)
39495 #define S_M_REQDATAVLD    1
39496 #define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
39497 #define F_M_REQDATAVLD    V_M_REQDATAVLD(1U)
39500 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
39501 #define F_M_REQDATARDY    V_M_REQDATARDY(1U)
39505 #define V_T6_MC_RSP_FIFO_CNT(x) ((x) << S_T6_MC_RSP_FIFO_CNT)
39506 #define G_T6_MC_RSP_FIFO_CNT(x) (((x) >> S_T6_MC_RSP_FIFO_CNT) & M_T6_MC_RSP_FIFO_CNT)
39510 #define V_T6_PCMD_FREE_CNT0(x) ((x) << S_T6_PCMD_FREE_CNT0)
39511 #define G_T6_PCMD_FREE_CNT0(x) (((x) >> S_T6_PCMD_FREE_CNT0) & M_T6_PCMD_FREE_CNT0)
39515 #define V_T6_PCMD_FREE_CNT1(x) ((x) << S_T6_PCMD_FREE_CNT1)
39516 #define G_T6_PCMD_FREE_CNT1(x) (((x) >> S_T6_PCMD_FREE_CNT1) & M_T6_PCMD_FREE_CNT1)
39519 #define V_M_RSPVLD(x) ((x) << S_M_RSPVLD)
39520 #define F_M_RSPVLD    V_M_RSPVLD(1U)
39523 #define V_M_RSPRDY(x) ((x) << S_M_RSPRDY)
39524 #define F_M_RSPRDY    V_M_RSPRDY(1U)
39527 #define V_M_REQADDRVLD(x) ((x) << S_M_REQADDRVLD)
39528 #define F_M_REQADDRVLD    V_M_REQADDRVLD(1U)
39534 #define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
39535 #define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
39539 #define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
39540 #define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
39546 #define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
39547 #define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
39551 #define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
39552 #define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
39556 #define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
39557 #define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
39561 #define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
39562 #define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
39566 #define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
39567 #define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
39571 #define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
39572 #define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
39576 #define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
39577 #define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
39581 #define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
39582 #define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
39588 #define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
39589 #define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
39593 #define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
39594 #define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
39598 #define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
39599 #define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
39603 #define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
39604 #define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
39608 #define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
39609 #define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
39613 #define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
39614 #define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
39618 #define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
39619 #define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
39623 #define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
39624 #define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
39630 #define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
39631 #define F_CH_DEFICIT_BLOWED    V_CH_DEFICIT_BLOWED(1U)
39635 #define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
39636 #define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
39640 #define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
39641 #define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
39647 #define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
39648 #define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
39652 #define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
39653 #define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
39659 #define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
39660 #define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
39664 #define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
39665 #define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
39669 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
39670 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
39674 #define V_T6_BUNDLE_LEN_SRDY(x) ((x) << S_T6_BUNDLE_LEN_SRDY)
39675 #define G_T6_BUNDLE_LEN_SRDY(x) (((x) >> S_T6_BUNDLE_LEN_SRDY) & M_T6_BUNDLE_LEN_SRDY)
39679 #define V_T6_BUNDLE_LEN1(x) ((x) << S_T6_BUNDLE_LEN1)
39680 #define G_T6_BUNDLE_LEN1(x) (((x) >> S_T6_BUNDLE_LEN1) & M_T6_BUNDLE_LEN1)
39686 #define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
39687 #define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
39691 #define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
39692 #define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
39700 #define V_LPBKEN(x) ((x) << S_LPBKEN)
39701 #define F_LPBKEN    V_LPBKEN(1U)
39704 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
39705 #define F_PORTTXEN    V_PORTTXEN(1U)
39708 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
39709 #define F_PORTRXEN    V_PORTRXEN(1U)
39712 #define V_PPPEN(x) ((x) << S_PPPEN)
39713 #define F_PPPEN    V_PPPEN(1U)
39716 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
39717 #define F_FCSSTRIPEN    V_FCSSTRIPEN(1U)
39720 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
39721 #define F_PPPANDPAUSE    V_PPPANDPAUSE(1U)
39725 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
39726 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
39733 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
39734 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
39740 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
39741 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
39745 #define V_REGSENDON(x) ((x) << S_REGSENDON)
39746 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
39750 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
39751 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
39755 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
39756 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
39761 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
39762 #define F_XOFFDISABLE    V_XOFFDISABLE(1U)
39768 #define V_REGHALTON(x) ((x) << S_REGHALTON)
39769 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
39773 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
39774 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
39780 #define V_REGSENDING(x) ((x) << S_REGSENDING)
39781 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
39785 #define V_SGESENDING(x) ((x) << S_SGESENDING)
39786 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
39790 #define V_RXSENDING(x) ((x) << S_RXSENDING)
39791 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
39797 #define V_REGHALTED(x) ((x) << S_REGHALTED)
39798 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
39802 #define V_RXHALTED(x) ((x) << S_RXHALTED)
39803 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
39810 #define V_ADDR(x) ((x) << S_ADDR)
39811 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
39820 #define V_PRTY7(x) ((x) << S_PRTY7)
39821 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
39825 #define V_PRTY6(x) ((x) << S_PRTY6)
39826 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
39830 #define V_PRTY5(x) ((x) << S_PRTY5)
39831 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
39835 #define V_PRTY4(x) ((x) << S_PRTY4)
39836 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
39840 #define V_PRTY3(x) ((x) << S_PRTY3)
39841 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
39845 #define V_PRTY2(x) ((x) << S_PRTY2)
39846 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
39850 #define V_PRTY1(x) ((x) << S_PRTY1)
39851 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
39855 #define V_PRTY0(x) ((x) << S_PRTY0)
39856 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
39862 #define V_TXPRTY7(x) ((x) << S_TXPRTY7)
39863 #define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
39867 #define V_TXPRTY6(x) ((x) << S_TXPRTY6)
39868 #define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
39872 #define V_TXPRTY5(x) ((x) << S_TXPRTY5)
39873 #define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
39877 #define V_TXPRTY4(x) ((x) << S_TXPRTY4)
39878 #define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
39882 #define V_TXPRTY3(x) ((x) << S_TXPRTY3)
39883 #define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
39887 #define V_TXPRTY2(x) ((x) << S_TXPRTY2)
39888 #define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
39892 #define V_TXPRTY1(x) ((x) << S_TXPRTY1)
39893 #define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
39897 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
39898 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
39905 #define V_TX2RX(x) ((x) << S_TX2RX)
39906 #define G_TX2RX(x) (((x) >> S_TX2RX) & M_TX2RX)
39910 #define V_MAC2MPS(x) ((x) << S_MAC2MPS)
39911 #define G_MAC2MPS(x) (((x) >> S_MAC2MPS) & M_MAC2MPS)
39915 #define V_MPS2MAC(x) ((x) << S_MPS2MAC)
39916 #define G_MPS2MAC(x) (((x) >> S_MPS2MAC) & M_MPS2MAC)
39955 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
39956 #define F_NO_RPLCT_M    V_NO_RPLCT_M(1U)
39960 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
39961 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
39964 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
39965 #define F_FLTR_VLAN_SEL    V_FLTR_VLAN_SEL(1U)
39968 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
39969 #define F_PRIO_VLAN_SEL    V_PRIO_VLAN_SEL(1U)
39972 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
39973 #define F_CHK_8023_LEN_M    V_CHK_8023_LEN_M(1U)
39976 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
39977 #define F_CHK_8023_LEN_L    V_CHK_8023_LEN_L(1U)
39980 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
39981 #define F_NIV_DROP    V_NIV_DROP(1U)
39984 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
39985 #define F_NOV_DROP    V_NOV_DROP(1U)
39988 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
39989 #define F_CLS_PRT    V_CLS_PRT(1U)
39992 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
39993 #define F_RX_QFC_EN    V_RX_QFC_EN(1U)
39996 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
39997 #define F_QFC_FWD_UP    V_QFC_FWD_UP(1U)
40000 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
40001 #define F_PPP_FWD_UP    V_PPP_FWD_UP(1U)
40004 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
40005 #define F_PAUSE_FWD_UP    V_PAUSE_FWD_UP(1U)
40008 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
40009 #define F_LPBK_BP    V_LPBK_BP(1U)
40012 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
40013 #define F_PASS_NO_MATCH    V_PASS_NO_MATCH(1U)
40016 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
40017 #define F_IVLAN_EN    V_IVLAN_EN(1U)
40020 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
40021 #define F_OVLAN_EN3    V_OVLAN_EN3(1U)
40024 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
40025 #define F_OVLAN_EN2    V_OVLAN_EN2(1U)
40027 #define S_OVLAN_EN1    1
40028 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
40029 #define F_OVLAN_EN1    V_OVLAN_EN1(1U)
40032 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
40033 #define F_OVLAN_EN0    V_OVLAN_EN0(1U)
40036 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
40037 #define F_PTP_FWD_UP    V_PTP_FWD_UP(1U)
40040 #define V_HASH_PRIO_SEL_LPBK(x) ((x) << S_HASH_PRIO_SEL_LPBK)
40041 #define F_HASH_PRIO_SEL_LPBK    V_HASH_PRIO_SEL_LPBK(1U)
40044 #define V_HASH_PRIO_SEL_MAC(x) ((x) << S_HASH_PRIO_SEL_MAC)
40045 #define F_HASH_PRIO_SEL_MAC    V_HASH_PRIO_SEL_MAC(1U)
40048 #define V_HASH_EN_LPBK(x) ((x) << S_HASH_EN_LPBK)
40049 #define F_HASH_EN_LPBK    V_HASH_EN_LPBK(1U)
40052 #define V_HASH_EN_MAC(x) ((x) << S_HASH_EN_MAC)
40053 #define F_HASH_EN_MAC    V_HASH_EN_MAC(1U)
40056 #define V_TRANS_ENCAP_EN(x) ((x) << S_TRANS_ENCAP_EN)
40057 #define F_TRANS_ENCAP_EN    V_TRANS_ENCAP_EN(1U)
40060 #define V_CRYPTO_DUMMY_PKT_CHK_EN(x) ((x) << S_CRYPTO_DUMMY_PKT_CHK_EN)
40061 #define F_CRYPTO_DUMMY_PKT_CHK_EN    V_CRYPTO_DUMMY_PKT_CHK_EN(1U)
40064 #define V_PASS_HPROM(x) ((x) << S_PASS_HPROM)
40065 #define F_PASS_HPROM    V_PASS_HPROM(1U)
40068 #define V_PASS_PROM(x) ((x) << S_PASS_PROM)
40069 #define F_PASS_PROM    V_PASS_PROM(1U)
40072 #define V_ENCAP_ONLY_IF_OUTER_HIT(x) ((x) << S_ENCAP_ONLY_IF_OUTER_HIT)
40073 #define F_ENCAP_ONLY_IF_OUTER_HIT    V_ENCAP_ONLY_IF_OUTER_HIT(1U)
40085 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
40086 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
40092 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
40093 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
40097 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
40098 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
40108 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
40109 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
40113 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
40114 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
40119 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
40120 #define F_FIXED_PFVF_MAC    V_FIXED_PFVF_MAC(1U)
40123 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
40124 #define F_FIXED_PFVF_LPBK    V_FIXED_PFVF_LPBK(1U)
40127 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
40128 #define F_FIXED_PFVF_LPBK_OV    V_FIXED_PFVF_LPBK_OV(1U)
40132 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
40133 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
40136 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
40137 #define F_FIXED_VF_VLD    V_FIXED_VF_VLD(1U)
40141 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
40142 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
40145 #define V_T6_FIXED_PFVF_MAC(x) ((x) << S_T6_FIXED_PFVF_MAC)
40146 #define F_T6_FIXED_PFVF_MAC    V_T6_FIXED_PFVF_MAC(1U)
40149 #define V_T6_FIXED_PFVF_LPBK(x) ((x) << S_T6_FIXED_PFVF_LPBK)
40150 #define F_T6_FIXED_PFVF_LPBK    V_T6_FIXED_PFVF_LPBK(1U)
40153 #define V_T6_FIXED_PFVF_LPBK_OV(x) ((x) << S_T6_FIXED_PFVF_LPBK_OV)
40154 #define F_T6_FIXED_PFVF_LPBK_OV    V_T6_FIXED_PFVF_LPBK_OV(1U)
40158 #define V_T6_FIXED_PF(x) ((x) << S_T6_FIXED_PF)
40159 #define G_T6_FIXED_PF(x) (((x) >> S_T6_FIXED_PF) & M_T6_FIXED_PF)
40162 #define V_T6_FIXED_VF_VLD(x) ((x) << S_T6_FIXED_VF_VLD)
40163 #define F_T6_FIXED_VF_VLD    V_T6_FIXED_VF_VLD(1U)
40167 #define V_T6_FIXED_VF(x) ((x) << S_T6_FIXED_VF)
40168 #define G_T6_FIXED_VF(x) (((x) >> S_T6_FIXED_VF) & M_T6_FIXED_VF)
40177 #define V_TS_VLD(x) ((x) << S_TS_VLD)
40178 #define G_TS_VLD(x) (((x) >> S_TS_VLD) & M_TS_VLD)
40183 #define V_LKP_SEL(x) ((x) << S_LKP_SEL)
40184 #define F_LKP_SEL    V_LKP_SEL(1U)
40193 #define V_OUTER_IPV4_N_INNER_IPV4(x) ((x) << S_OUTER_IPV4_N_INNER_IPV4)
40194 #define F_OUTER_IPV4_N_INNER_IPV4    V_OUTER_IPV4_N_INNER_IPV4(1U)
40197 #define V_OUTER_IPV4_N_INNER_IPV6(x) ((x) << S_OUTER_IPV4_N_INNER_IPV6)
40198 #define F_OUTER_IPV4_N_INNER_IPV6    V_OUTER_IPV4_N_INNER_IPV6(1U)
40201 #define V_OUTER_IPV6_N_INNER_IPV4(x) ((x) << S_OUTER_IPV6_N_INNER_IPV4)
40202 #define F_OUTER_IPV6_N_INNER_IPV4    V_OUTER_IPV6_N_INNER_IPV4(1U)
40205 #define V_OUTER_IPV6_N_INNER_IPV6(x) ((x) << S_OUTER_IPV6_N_INNER_IPV6)
40206 #define F_OUTER_IPV6_N_INNER_IPV6    V_OUTER_IPV6_N_INNER_IPV6(1U)
40209 #define V_OUTER_IPV4_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_VLAN_NVGRE)
40210 #define F_OUTER_IPV4_N_VLAN_NVGRE    V_OUTER_IPV4_N_VLAN_NVGRE(1U)
40213 #define V_OUTER_IPV6_N_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_VLAN_NVGRE)
40214 #define F_OUTER_IPV6_N_VLAN_NVGRE    V_OUTER_IPV6_N_VLAN_NVGRE(1U)
40217 #define V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE)
40218 #define F_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV4_N_DOUBLE_VLAN_NVGRE(1U)
40221 #define V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE)
40222 #define F_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE    V_OUTER_IPV6_N_DOUBLE_VLAN_NVGRE(1U)
40225 #define V_OUTER_IPV4_N_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_VLAN_GRE)
40226 #define F_OUTER_IPV4_N_VLAN_GRE    V_OUTER_IPV4_N_VLAN_GRE(1U)
40229 #define V_OUTER_IPV6_N_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_VLAN_GRE)
40230 #define F_OUTER_IPV6_N_VLAN_GRE    V_OUTER_IPV6_N_VLAN_GRE(1U)
40233 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GRE)
40234 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GRE    V_OUTER_IPV4_N_DOUBLE_VLAN_GRE(1U)
40237 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GRE)
40238 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GRE    V_OUTER_IPV6_N_DOUBLE_VLAN_GRE(1U)
40241 #define V_OUTER_IPV4_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_VLAN_VXLAN)
40242 #define F_OUTER_IPV4_N_VLAN_VXLAN    V_OUTER_IPV4_N_VLAN_VXLAN(1U)
40245 #define V_OUTER_IPV6_N_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_VLAN_VXLAN)
40246 #define F_OUTER_IPV6_N_VLAN_VXLAN    V_OUTER_IPV6_N_VLAN_VXLAN(1U)
40249 #define V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN)
40250 #define F_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV4_N_DOUBLE_VLAN_VXLAN(1U)
40253 #define V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN)
40254 #define F_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN    V_OUTER_IPV6_N_DOUBLE_VLAN_VXLAN(1U)
40257 #define V_OUTER_IPV4_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_VLAN_GENEVE)
40258 #define F_OUTER_IPV4_N_VLAN_GENEVE    V_OUTER_IPV4_N_VLAN_GENEVE(1U)
40261 #define V_OUTER_IPV6_N_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_VLAN_GENEVE)
40262 #define F_OUTER_IPV6_N_VLAN_GENEVE    V_OUTER_IPV6_N_VLAN_GENEVE(1U)
40265 #define V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE)
40266 #define F_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV4_N_DOUBLE_VLAN_GENEVE(1U)
40269 #define V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(x) ((x) << S_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE)
40270 #define F_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE    V_OUTER_IPV6_N_DOUBLE_VLAN_GENEVE(1U)
40273 #define V_ERR_TNL_HDR_LEN(x) ((x) << S_ERR_TNL_HDR_LEN)
40274 #define F_ERR_TNL_HDR_LEN    V_ERR_TNL_HDR_LEN(1U)
40277 #define V_NON_RUNT_FRAME(x) ((x) << S_NON_RUNT_FRAME)
40278 #define F_NON_RUNT_FRAME    V_NON_RUNT_FRAME(1U)
40281 #define V_INNER_VLAN_VLD(x) ((x) << S_INNER_VLAN_VLD)
40282 #define F_INNER_VLAN_VLD    V_INNER_VLAN_VLD(1U)
40285 #define V_ERR_IP_PAYLOAD_LEN(x) ((x) << S_ERR_IP_PAYLOAD_LEN)
40286 #define F_ERR_IP_PAYLOAD_LEN    V_ERR_IP_PAYLOAD_LEN(1U)
40289 #define V_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_ERR_UDP_PAYLOAD_LEN)
40290 #define F_ERR_UDP_PAYLOAD_LEN    V_ERR_UDP_PAYLOAD_LEN(1U)
40295 #define V_T6_INNER_VLAN_VLD(x) ((x) << S_T6_INNER_VLAN_VLD)
40296 #define F_T6_INNER_VLAN_VLD    V_T6_INNER_VLAN_VLD(1U)
40299 #define V_T6_ERR_IP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_IP_PAYLOAD_LEN)
40300 #define F_T6_ERR_IP_PAYLOAD_LEN    V_T6_ERR_IP_PAYLOAD_LEN(1U)
40303 #define V_T6_ERR_UDP_PAYLOAD_LEN(x) ((x) << S_T6_ERR_UDP_PAYLOAD_LEN)
40304 #define F_T6_ERR_UDP_PAYLOAD_LEN    V_T6_ERR_UDP_PAYLOAD_LEN(1U)
40309 #define V_DIS_REPL_VECT_SEL(x) ((x) << S_DIS_REPL_VECT_SEL)
40310 #define F_DIS_REPL_VECT_SEL    V_DIS_REPL_VECT_SEL(1U)
40314 #define V_REPL_VECT_SEL(x) ((x) << S_REPL_VECT_SEL)
40315 #define G_REPL_VECT_SEL(x) (((x) >> S_REPL_VECT_SEL) & M_REPL_VECT_SEL)
40321 #define V_PRIO(x) ((x) << S_PRIO)
40322 #define G_PRIO(x) (((x) >> S_PRIO) & M_PRIO)
40330 #define V_DBG_TYPE(x) ((x) << S_DBG_TYPE)
40331 #define G_DBG_TYPE(x) (((x) >> S_DBG_TYPE) & M_DBG_TYPE)
40338 #define V_CREDIT(x) ((x) << S_CREDIT)
40339 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
40354 #define V_FIFOTH(x) ((x) << S_FIFOTH)
40355 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
40358 #define V_FIFOEN(x) ((x) << S_FIFOEN)
40359 #define F_FIFOEN    V_FIFOEN(1U)
40363 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
40364 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
40368 #define V_OUT_TH(x) ((x) << S_OUT_TH)
40369 #define G_OUT_TH(x) (((x) >> S_OUT_TH) & M_OUT_TH)
40373 #define V_IN_TH(x) ((x) << S_IN_TH)
40374 #define G_IN_TH(x) (((x) >> S_IN_TH) & M_IN_TH)
40379 #define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
40380 #define F_FPGAPAUSEEN    V_FPGAPAUSEEN(1U)
40386 #define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
40387 #define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
40391 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
40392 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
40401 #define V_VALID(x) ((x) << S_VALID)
40402 #define F_VALID    V_VALID(1U)
40406 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
40407 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
40410 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
40411 #define F_MULTILISTEN    V_MULTILISTEN(1U)
40415 #define V_PRIORITY(x) ((x) << S_PRIORITY)
40416 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
40419 #define V_REPLICATE(x) ((x) << S_REPLICATE)
40420 #define F_REPLICATE    V_REPLICATE(1U)
40424 #define V_PF(x) ((x) << S_PF)
40425 #define G_PF(x) (((x) >> S_PF) & M_PF)
40428 #define V_VF_VALID(x) ((x) << S_VF_VALID)
40429 #define F_VF_VALID    V_VF_VALID(1U)
40433 #define V_VF(x) ((x) << S_VF)
40434 #define G_VF(x) (((x) >> S_VF) & M_VF)
40437 #define V_DISENCAPOUTERRPLCT(x) ((x) << S_DISENCAPOUTERRPLCT)
40438 #define F_DISENCAPOUTERRPLCT    V_DISENCAPOUTERRPLCT(1U)
40441 #define V_DISENCAP(x) ((x) << S_DISENCAP)
40442 #define F_DISENCAP    V_DISENCAP(1U)
40445 #define V_T6_VALID(x) ((x) << S_T6_VALID)
40446 #define F_T6_VALID    V_T6_VALID(1U)
40450 #define V_T6_HASHPORTMAP(x) ((x) << S_T6_HASHPORTMAP)
40451 #define G_T6_HASHPORTMAP(x) (((x) >> S_T6_HASHPORTMAP) & M_T6_HASHPORTMAP)
40454 #define V_T6_MULTILISTEN(x) ((x) << S_T6_MULTILISTEN)
40455 #define F_T6_MULTILISTEN    V_T6_MULTILISTEN(1U)
40459 #define V_T6_PRIORITY(x) ((x) << S_T6_PRIORITY)
40460 #define G_T6_PRIORITY(x) (((x) >> S_T6_PRIORITY) & M_T6_PRIORITY)
40463 #define V_T6_REPLICATE(x) ((x) << S_T6_REPLICATE)
40464 #define F_T6_REPLICATE    V_T6_REPLICATE(1U)
40468 #define V_T6_PF(x) ((x) << S_T6_PF)
40469 #define G_T6_PF(x) (((x) >> S_T6_PF) & M_T6_PF)
40472 #define V_T6_VF_VALID(x) ((x) << S_T6_VF_VALID)
40473 #define F_T6_VF_VALID    V_T6_VF_VALID(1U)
40477 #define V_T6_VF(x) ((x) << S_T6_VF)
40478 #define G_T6_VF(x) (((x) >> S_T6_VF) & M_T6_VF)
40482 #define S_TXEN    1
40483 #define V_TXEN(x) ((x) << S_TXEN)
40484 #define F_TXEN    V_TXEN(1U)
40487 #define V_RXEN(x) ((x) << S_RXEN)
40488 #define F_RXEN    V_RXEN(1U)
40494 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
40495 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
40499 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
40500 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
40503 #define V_CFI(x) ((x) << S_CFI)
40504 #define F_CFI    V_CFI(1U)
40508 #define V_TAG(x) ((x) << S_TAG)
40509 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
40515 #define V_T7_DROPEN(x) ((x) << S_T7_DROPEN)
40516 #define G_T7_DROPEN(x) (((x) >> S_T7_DROPEN) & M_T7_DROPEN)
40523 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
40524 #define F_UNICASTENABLE    V_UNICASTENABLE(1U)
40530 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
40531 #define F_PROMISCEN    V_PROMISCEN(1U)
40540 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
40541 #define F_MATCHBOTH    V_MATCHBOTH(1U)
40544 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
40545 #define F_BMC_VLD    V_BMC_VLD(1U)
40548 #define V_MATCHALL(x) ((x) << S_MATCHALL)
40549 #define F_MATCHALL    V_MATCHALL(1U)
40556 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
40557 #define F_BMC_VLAN_SEL    V_BMC_VLAN_SEL(1U)
40560 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
40561 #define F_VLAN_VLD    V_VLAN_VLD(1U)
40568 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
40569 #define F_PF_VLAN_SEL    V_PF_VLAN_SEL(1U)
40572 #define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
40573 #define F_LPBK_TCAM1_HIT_PRIORITY    V_LPBK_TCAM1_HIT_PRIORITY(1U)
40576 #define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
40577 #define F_LPBK_TCAM0_HIT_PRIORITY    V_LPBK_TCAM0_HIT_PRIORITY(1U)
40580 #define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
40581 #define F_LPBK_TCAM_PRIORITY    V_LPBK_TCAM_PRIORITY(1U)
40585 #define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
40586 #define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
40590 #define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
40591 #define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
40594 #define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
40595 #define F_TCAM1_HIT_PRIORITY    V_TCAM1_HIT_PRIORITY(1U)
40598 #define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
40599 #define F_TCAM0_HIT_PRIORITY    V_TCAM0_HIT_PRIORITY(1U)
40602 #define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
40603 #define F_TCAM_PRIORITY    V_TCAM_PRIORITY(1U)
40607 #define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
40608 #define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
40610 #define S_DMAC_TCAM_SEL    1
40612 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
40613 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
40616 #define V_SMAC_INDEX_EN(x) ((x) << S_SMAC_INDEX_EN)
40617 #define F_SMAC_INDEX_EN    V_SMAC_INDEX_EN(1U)
40620 #define V_LPBK_TCAM2_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM2_HIT_PRIORITY)
40621 #define F_LPBK_TCAM2_HIT_PRIORITY    V_LPBK_TCAM2_HIT_PRIORITY(1U)
40624 #define V_TCAM2_HIT_PRIORITY(x) ((x) << S_TCAM2_HIT_PRIORITY)
40625 #define F_TCAM2_HIT_PRIORITY    V_TCAM2_HIT_PRIORITY(1U)
40632 #define V_ETHTYPE2(x) ((x) << S_ETHTYPE2)
40633 #define G_ETHTYPE2(x) (((x) >> S_ETHTYPE2) & M_ETHTYPE2)
40638 #define S_EN1    1
40639 #define V_EN1(x) ((x) << S_EN1)
40640 #define F_EN1    V_EN1(1U)
40643 #define V_EN2(x) ((x) << S_EN2)
40644 #define F_EN2    V_EN2(1U)
40832 #define V_DETECT8023(x) ((x) << S_DETECT8023)
40833 #define F_DETECT8023    V_DETECT8023(1U)
40836 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
40837 #define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)
40841 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
40842 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
40845 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
40846 #define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
40849 #define V_TX_PORT_STATS_MODE(x) ((x) << S_TX_PORT_STATS_MODE)
40850 #define F_TX_PORT_STATS_MODE    V_TX_PORT_STATS_MODE(1U)
40853 #define V_T5MODE(x) ((x) << S_T5MODE)
40854 #define F_T5MODE    V_T5MODE(1U)
40858 #define V_SPEEDMODE(x) ((x) << S_SPEEDMODE)
40859 #define G_SPEEDMODE(x) (((x) >> S_SPEEDMODE) & M_SPEEDMODE)
40862 #define V_PT1_SEL_CFG(x) ((x) << S_PT1_SEL_CFG)
40863 #define F_PT1_SEL_CFG    V_PT1_SEL_CFG(1U)
40866 #define V_BUG_42938_EN(x) ((x) << S_BUG_42938_EN)
40867 #define F_BUG_42938_EN    V_BUG_42938_EN(1U)
40870 #define V_NO_BYPASS_PAUSE(x) ((x) << S_NO_BYPASS_PAUSE)
40871 #define F_NO_BYPASS_PAUSE    V_NO_BYPASS_PAUSE(1U)
40874 #define V_BYPASS_PAUSE(x) ((x) << S_BYPASS_PAUSE)
40875 #define F_BYPASS_PAUSE    V_BYPASS_PAUSE(1U)
40879 #define V_PBUS_EN(x) ((x) << S_PBUS_EN)
40880 #define G_PBUS_EN(x) (((x) >> S_PBUS_EN) & M_PBUS_EN)
40884 #define V_INIC_EN(x) ((x) << S_INIC_EN)
40885 #define G_INIC_EN(x) (((x) >> S_INIC_EN) & M_INIC_EN)
40889 #define V_SBA_EN(x) ((x) << S_SBA_EN)
40890 #define G_SBA_EN(x) (((x) >> S_SBA_EN) & M_SBA_EN)
40893 #define V_BG2TP_MAP_MODE(x) ((x) << S_BG2TP_MAP_MODE)
40894 #define F_BG2TP_MAP_MODE    V_BG2TP_MAP_MODE(1U)
40898 #define V_MPS_LB_MODE(x) ((x) << S_MPS_LB_MODE)
40899 #define G_MPS_LB_MODE(x) (((x) >> S_MPS_LB_MODE) & M_MPS_LB_MODE)
40904 #define V_STATINTENB(x) ((x) << S_STATINTENB)
40905 #define F_STATINTENB    V_STATINTENB(1U)
40908 #define V_TXINTENB(x) ((x) << S_TXINTENB)
40909 #define F_TXINTENB    V_TXINTENB(1U)
40912 #define V_RXINTENB(x) ((x) << S_RXINTENB)
40913 #define F_RXINTENB    V_RXINTENB(1U)
40916 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
40917 #define F_TRCINTENB    V_TRCINTENB(1U)
40919 #define S_CLSINTENB    1
40920 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
40921 #define F_CLSINTENB    V_CLSINTENB(1U)
40924 #define V_PLINTENB(x) ((x) << S_PLINTENB)
40925 #define F_PLINTENB    V_PLINTENB(1U)
40930 #define V_STATINT(x) ((x) << S_STATINT)
40931 #define F_STATINT    V_STATINT(1U)
40934 #define V_TXINT(x) ((x) << S_TXINT)
40935 #define F_TXINT    V_TXINT(1U)
40938 #define V_RXINT(x) ((x) << S_RXINT)
40939 #define F_RXINT    V_RXINT(1U)
40942 #define V_TRCINT(x) ((x) << S_TRCINT)
40943 #define F_TRCINT    V_TRCINT(1U)
40945 #define S_CLSINT    1
40946 #define V_CLSINT(x) ((x) << S_CLSINT)
40947 #define F_CLSINT    V_CLSINT(1U)
40950 #define V_PLINT(x) ((x) << S_PLINT)
40951 #define F_PLINT    V_PLINT(1U)
40956 #define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
40957 #define F_MPS_GLOBAL_CGEN    V_MPS_GLOBAL_CGEN(1U)
40971 #define V_VALUE(x) ((x) << S_VALUE)
40972 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
40985 #define V_WEIGHT(x) ((x) << S_WEIGHT)
40986 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
40992 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
40993 #define F_WOL_MODE    V_WOL_MODE(1U)
40998 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
40999 #define F_LPBK_EN    V_LPBK_EN(1U)
41003 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
41004 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
41008 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
41009 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
41013 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
41014 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
41018 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
41019 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
41023 #define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
41024 #define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
41029 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
41030 #define F_DBGMODECTL_H    V_DBGMODECTL_H(1U)
41034 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
41035 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
41038 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
41039 #define F_DBGMODECTL_L    V_DBGMODECTL_L(1U)
41043 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
41044 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
41052 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
41053 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
41056 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
41057 #define F_OVLANSELLPBK3    V_OVLANSELLPBK3(1U)
41060 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
41061 #define F_OVLANSELLPBK2    V_OVLANSELLPBK2(1U)
41064 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
41065 #define F_OVLANSELLPBK1    V_OVLANSELLPBK1(1U)
41068 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
41069 #define F_OVLANSELLPBK0    V_OVLANSELLPBK0(1U)
41072 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
41073 #define F_OVLANSELMAC3    V_OVLANSELMAC3(1U)
41076 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
41077 #define F_OVLANSELMAC2    V_OVLANSELMAC2(1U)
41079 #define S_OVLANSELMAC1    1
41080 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
41081 #define F_OVLANSELMAC1    V_OVLANSELMAC1(1U)
41084 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
41085 #define F_OVLANSELMAC0    V_OVLANSELMAC0(1U)
41089 #define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
41090 #define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
41097 #define V_VALUE_1(x) ((x) << S_VALUE_1)
41098 #define G_VALUE_1(x) (((x) >> S_VALUE_1) & M_VALUE_1)
41102 #define V_VALUE_0(x) ((x) << S_VALUE_0)
41103 #define G_VALUE_0(x) (((x) >> S_VALUE_0) & M_VALUE_0)
41149 #define V_ADDRMASK(x) ((x) << S_ADDRMASK)
41150 #define G_ADDRMASK(x) (((x) >> S_ADDRMASK) & M_ADDRMASK)
41154 #define V_T6_BASEADDR(x) ((x) << S_T6_BASEADDR)
41155 #define G_T6_BASEADDR(x) (((x) >> S_T6_BASEADDR) & M_T6_BASEADDR)
41163 #define V_T7_RD_WRN(x) ((x) << S_T7_RD_WRN)
41164 #define F_T7_RD_WRN    V_T7_RD_WRN(1U)
41173 #define V_LPBK_SHIFT_0(x) ((x) << S_LPBK_SHIFT_0)
41174 #define G_LPBK_SHIFT_0(x) (((x) >> S_LPBK_SHIFT_0) & M_LPBK_SHIFT_0)
41178 #define V_LPBK_SHIFT_1(x) ((x) << S_LPBK_SHIFT_1)
41179 #define G_LPBK_SHIFT_1(x) (((x) >> S_LPBK_SHIFT_1) & M_LPBK_SHIFT_1)
41183 #define V_LPBK_SHIFT_2(x) ((x) << S_LPBK_SHIFT_2)
41184 #define G_LPBK_SHIFT_2(x) (((x) >> S_LPBK_SHIFT_2) & M_LPBK_SHIFT_2)
41188 #define V_LPBK_SHIFT_3(x) ((x) << S_LPBK_SHIFT_3)
41189 #define G_LPBK_SHIFT_3(x) (((x) >> S_LPBK_SHIFT_3) & M_LPBK_SHIFT_3)
41193 #define V_MAC_SHIFT_0(x) ((x) << S_MAC_SHIFT_0)
41194 #define G_MAC_SHIFT_0(x) (((x) >> S_MAC_SHIFT_0) & M_MAC_SHIFT_0)
41198 #define V_MAC_SHIFT_1(x) ((x) << S_MAC_SHIFT_1)
41199 #define G_MAC_SHIFT_1(x) (((x) >> S_MAC_SHIFT_1) & M_MAC_SHIFT_1)
41203 #define V_MAC_SHIFT_2(x) ((x) << S_MAC_SHIFT_2)
41204 #define G_MAC_SHIFT_2(x) (((x) >> S_MAC_SHIFT_2) & M_MAC_SHIFT_2)
41208 #define V_MAC_SHIFT_3(x) ((x) << S_MAC_SHIFT_3)
41209 #define G_MAC_SHIFT_3(x) (((x) >> S_MAC_SHIFT_3) & M_MAC_SHIFT_3)
41214 #define V_LPBK_EN3(x) ((x) << S_LPBK_EN3)
41215 #define F_LPBK_EN3    V_LPBK_EN3(1U)
41218 #define V_LPBK_EN2(x) ((x) << S_LPBK_EN2)
41219 #define F_LPBK_EN2    V_LPBK_EN2(1U)
41222 #define V_LPBK_EN1(x) ((x) << S_LPBK_EN1)
41223 #define F_LPBK_EN1    V_LPBK_EN1(1U)
41226 #define V_LPBK_EN0(x) ((x) << S_LPBK_EN0)
41227 #define F_LPBK_EN0    V_LPBK_EN0(1U)
41230 #define V_MAC_EN3(x) ((x) << S_MAC_EN3)
41231 #define F_MAC_EN3    V_MAC_EN3(1U)
41234 #define V_MAC_EN2(x) ((x) << S_MAC_EN2)
41235 #define F_MAC_EN2    V_MAC_EN2(1U)
41237 #define S_MAC_EN1    1
41238 #define V_MAC_EN1(x) ((x) << S_MAC_EN1)
41239 #define F_MAC_EN1    V_MAC_EN1(1U)
41242 #define V_MAC_EN0(x) ((x) << S_MAC_EN0)
41243 #define F_MAC_EN0    V_MAC_EN0(1U)
41265 #define V_T7_MAC3(x) ((x) << S_T7_MAC3)
41266 #define G_T7_MAC3(x) (((x) >> S_T7_MAC3) & M_T7_MAC3)
41270 #define V_T7_MAC2(x) ((x) << S_T7_MAC2)
41271 #define G_T7_MAC2(x) (((x) >> S_T7_MAC2) & M_T7_MAC2)
41275 #define V_T7_MAC1(x) ((x) << S_T7_MAC1)
41276 #define G_T7_MAC1(x) (((x) >> S_T7_MAC1) & M_T7_MAC1)
41280 #define V_T7_MAC0(x) ((x) << S_T7_MAC0)
41281 #define G_T7_MAC0(x) (((x) >> S_T7_MAC0) & M_T7_MAC0)
41287 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
41288 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
41292 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
41293 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
41297 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
41298 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
41302 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
41303 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
41307 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
41308 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
41312 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
41313 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
41317 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
41318 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
41322 #define V_T7_CH4_PRTY(x) ((x) << S_T7_CH4_PRTY)
41323 #define G_T7_CH4_PRTY(x) (((x) >> S_T7_CH4_PRTY) & M_T7_CH4_PRTY)
41327 #define V_T7_CH3_PRTY(x) ((x) << S_T7_CH3_PRTY)
41328 #define G_T7_CH3_PRTY(x) (((x) >> S_T7_CH3_PRTY) & M_T7_CH3_PRTY)
41332 #define V_T7_CH2_PRTY(x) ((x) << S_T7_CH2_PRTY)
41333 #define G_T7_CH2_PRTY(x) (((x) >> S_T7_CH2_PRTY) & M_T7_CH2_PRTY)
41337 #define V_T7_CH1_PRTY(x) ((x) << S_T7_CH1_PRTY)
41338 #define G_T7_CH1_PRTY(x) (((x) >> S_T7_CH1_PRTY) & M_T7_CH1_PRTY)
41343 #define V_PORTERR(x) ((x) << S_PORTERR)
41344 #define F_PORTERR    V_PORTERR(1U)
41347 #define V_FRMERR(x) ((x) << S_FRMERR)
41348 #define F_FRMERR    V_FRMERR(1U)
41351 #define V_SECNTERR(x) ((x) << S_SECNTERR)
41352 #define F_SECNTERR    V_SECNTERR(1U)
41355 #define V_BUBBLE(x) ((x) << S_BUBBLE)
41356 #define F_BUBBLE    V_BUBBLE(1U)
41360 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
41361 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
41365 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
41366 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
41369 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
41370 #define F_NCSIFIFO    V_NCSIFIFO(1U)
41374 #define V_TPFIFO(x) ((x) << S_TPFIFO)
41375 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
41378 #define V_T7_PORTERR(x) ((x) << S_T7_PORTERR)
41379 #define F_T7_PORTERR    V_T7_PORTERR(1U)
41382 #define V_T7_FRMERR(x) ((x) << S_T7_FRMERR)
41383 #define F_T7_FRMERR    V_T7_FRMERR(1U)
41386 #define V_T7_SECNTERR(x) ((x) << S_T7_SECNTERR)
41387 #define F_T7_SECNTERR    V_T7_SECNTERR(1U)
41390 #define V_T7_BUBBLE(x) ((x) << S_T7_BUBBLE)
41391 #define F_T7_BUBBLE    V_T7_BUBBLE(1U)
41395 #define V_TXTOKENFIFO(x) ((x) << S_TXTOKENFIFO)
41396 #define G_TXTOKENFIFO(x) (((x) >> S_TXTOKENFIFO) & M_TXTOKENFIFO)
41400 #define V_PERR_TP2MPS_TFIFO(x) ((x) << S_PERR_TP2MPS_TFIFO)
41401 #define G_PERR_TP2MPS_TFIFO(x) (((x) >> S_PERR_TP2MPS_TFIFO) & M_PERR_TP2MPS_TFIFO)
41408 #define V_PORTERRINT(x) ((x) << S_PORTERRINT)
41409 #define F_PORTERRINT    V_PORTERRINT(1U)
41412 #define V_FRAMINGERRINT(x) ((x) << S_FRAMINGERRINT)
41413 #define F_FRAMINGERRINT    V_FRAMINGERRINT(1U)
41416 #define V_SECNTERRINT(x) ((x) << S_SECNTERRINT)
41417 #define F_SECNTERRINT    V_SECNTERRINT(1U)
41420 #define V_BUBBLEERRINT(x) ((x) << S_BUBBLEERRINT)
41421 #define F_BUBBLEERRINT    V_BUBBLEERRINT(1U)
41425 #define S_MPSTXMEMSEL    1
41427 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
41428 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
41438 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
41439 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
41443 #define V_SPI(x) ((x) << S_SPI)
41444 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
41448 #define V_SECNT(x) ((x) << S_SECNT)
41449 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
41455 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
41456 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
41459 #define V_NCSISECNT(x) ((x) << S_NCSISECNT)
41460 #define F_NCSISECNT    V_NCSISECNT(1U)
41464 #define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
41465 #define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
41470 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
41471 #define F_LPBKPT3    V_LPBKPT3(1U)
41474 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
41475 #define F_LPBKPT2    V_LPBKPT2(1U)
41478 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
41479 #define F_LPBKPT1    V_LPBKPT1(1U)
41482 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
41483 #define F_LPBKPT0    V_LPBKPT0(1U)
41486 #define V_PT3(x) ((x) << S_PT3)
41487 #define F_PT3    V_PT3(1U)
41490 #define V_PT2(x) ((x) << S_PT2)
41491 #define F_PT2    V_PT2(1U)
41493 #define S_PT1    1
41494 #define V_PT1(x) ((x) << S_PT1)
41495 #define F_PT1    V_PT1(1U)
41498 #define V_PT0(x) ((x) << S_PT0)
41499 #define F_PT0    V_PT0(1U)
41503 #define S_BPEN    1
41504 #define V_BPEN(x) ((x) << S_BPEN)
41505 #define F_BPEN    V_BPEN(1U)
41508 #define V_DROPEN(x) ((x) << S_DROPEN)
41509 #define F_DROPEN    V_DROPEN(1U)
41517 #define V_SOPCH1(x) ((x) << S_SOPCH1)
41518 #define F_SOPCH1    V_SOPCH1(1U)
41521 #define V_EOPCH1(x) ((x) << S_EOPCH1)
41522 #define F_EOPCH1    V_EOPCH1(1U)
41526 #define V_SIZECH1(x) ((x) << S_SIZECH1)
41527 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
41530 #define V_ERRCH1(x) ((x) << S_ERRCH1)
41531 #define F_ERRCH1    V_ERRCH1(1U)
41534 #define V_FULLCH1(x) ((x) << S_FULLCH1)
41535 #define F_FULLCH1    V_FULLCH1(1U)
41538 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
41539 #define F_VALIDCH1    V_VALIDCH1(1U)
41543 #define V_DATACH1(x) ((x) << S_DATACH1)
41544 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
41547 #define V_SOPCH0(x) ((x) << S_SOPCH0)
41548 #define F_SOPCH0    V_SOPCH0(1U)
41551 #define V_EOPCH0(x) ((x) << S_EOPCH0)
41552 #define F_EOPCH0    V_EOPCH0(1U)
41556 #define V_SIZECH0(x) ((x) << S_SIZECH0)
41557 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
41560 #define V_ERRCH0(x) ((x) << S_ERRCH0)
41561 #define F_ERRCH0    V_ERRCH0(1U)
41564 #define V_FULLCH0(x) ((x) << S_FULLCH0)
41565 #define F_FULLCH0    V_FULLCH0(1U)
41568 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
41569 #define F_VALIDCH0    V_VALIDCH0(1U)
41573 #define V_DATACH0(x) ((x) << S_DATACH0)
41574 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
41578 #define V_T5_SIZECH1(x) ((x) << S_T5_SIZECH1)
41579 #define G_T5_SIZECH1(x) (((x) >> S_T5_SIZECH1) & M_T5_SIZECH1)
41582 #define V_T5_ERRCH1(x) ((x) << S_T5_ERRCH1)
41583 #define F_T5_ERRCH1    V_T5_ERRCH1(1U)
41586 #define V_T5_FULLCH1(x) ((x) << S_T5_FULLCH1)
41587 #define F_T5_FULLCH1    V_T5_FULLCH1(1U)
41590 #define V_T5_VALIDCH1(x) ((x) << S_T5_VALIDCH1)
41591 #define F_T5_VALIDCH1    V_T5_VALIDCH1(1U)
41595 #define V_T5_DATACH1(x) ((x) << S_T5_DATACH1)
41596 #define G_T5_DATACH1(x) (((x) >> S_T5_DATACH1) & M_T5_DATACH1)
41600 #define V_T5_SIZECH0(x) ((x) << S_T5_SIZECH0)
41601 #define G_T5_SIZECH0(x) (((x) >> S_T5_SIZECH0) & M_T5_SIZECH0)
41604 #define V_T5_ERRCH0(x) ((x) << S_T5_ERRCH0)
41605 #define F_T5_ERRCH0    V_T5_ERRCH0(1U)
41608 #define V_T5_FULLCH0(x) ((x) << S_T5_FULLCH0)
41609 #define F_T5_FULLCH0    V_T5_FULLCH0(1U)
41612 #define V_T5_VALIDCH0(x) ((x) << S_T5_VALIDCH0)
41613 #define F_T5_VALIDCH0    V_T5_VALIDCH0(1U)
41617 #define V_T5_DATACH0(x) ((x) << S_T5_DATACH0)
41618 #define G_T5_DATACH0(x) (((x) >> S_T5_DATACH0) & M_T5_DATACH0)
41623 #define V_SOPCH3(x) ((x) << S_SOPCH3)
41624 #define F_SOPCH3    V_SOPCH3(1U)
41627 #define V_EOPCH3(x) ((x) << S_EOPCH3)
41628 #define F_EOPCH3    V_EOPCH3(1U)
41632 #define V_SIZECH3(x) ((x) << S_SIZECH3)
41633 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
41636 #define V_ERRCH3(x) ((x) << S_ERRCH3)
41637 #define F_ERRCH3    V_ERRCH3(1U)
41640 #define V_FULLCH3(x) ((x) << S_FULLCH3)
41641 #define F_FULLCH3    V_FULLCH3(1U)
41644 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
41645 #define F_VALIDCH3    V_VALIDCH3(1U)
41649 #define V_DATACH3(x) ((x) << S_DATACH3)
41650 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
41653 #define V_SOPCH2(x) ((x) << S_SOPCH2)
41654 #define F_SOPCH2    V_SOPCH2(1U)
41657 #define V_EOPCH2(x) ((x) << S_EOPCH2)
41658 #define F_EOPCH2    V_EOPCH2(1U)
41662 #define V_SIZECH2(x) ((x) << S_SIZECH2)
41663 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
41666 #define V_ERRCH2(x) ((x) << S_ERRCH2)
41667 #define F_ERRCH2    V_ERRCH2(1U)
41670 #define V_FULLCH2(x) ((x) << S_FULLCH2)
41671 #define F_FULLCH2    V_FULLCH2(1U)
41674 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
41675 #define F_VALIDCH2    V_VALIDCH2(1U)
41679 #define V_DATACH2(x) ((x) << S_DATACH2)
41680 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
41684 #define V_T5_SIZECH3(x) ((x) << S_T5_SIZECH3)
41685 #define G_T5_SIZECH3(x) (((x) >> S_T5_SIZECH3) & M_T5_SIZECH3)
41688 #define V_T5_ERRCH3(x) ((x) << S_T5_ERRCH3)
41689 #define F_T5_ERRCH3    V_T5_ERRCH3(1U)
41692 #define V_T5_FULLCH3(x) ((x) << S_T5_FULLCH3)
41693 #define F_T5_FULLCH3    V_T5_FULLCH3(1U)
41696 #define V_T5_VALIDCH3(x) ((x) << S_T5_VALIDCH3)
41697 #define F_T5_VALIDCH3    V_T5_VALIDCH3(1U)
41701 #define V_T5_DATACH3(x) ((x) << S_T5_DATACH3)
41702 #define G_T5_DATACH3(x) (((x) >> S_T5_DATACH3) & M_T5_DATACH3)
41706 #define V_T5_SIZECH2(x) ((x) << S_T5_SIZECH2)
41707 #define G_T5_SIZECH2(x) (((x) >> S_T5_SIZECH2) & M_T5_SIZECH2)
41710 #define V_T5_ERRCH2(x) ((x) << S_T5_ERRCH2)
41711 #define F_T5_ERRCH2    V_T5_ERRCH2(1U)
41714 #define V_T5_FULLCH2(x) ((x) << S_T5_FULLCH2)
41715 #define F_T5_FULLCH2    V_T5_FULLCH2(1U)
41718 #define V_T5_VALIDCH2(x) ((x) << S_T5_VALIDCH2)
41719 #define F_T5_VALIDCH2    V_T5_VALIDCH2(1U)
41723 #define V_T5_DATACH2(x) ((x) << S_T5_DATACH2)
41724 #define G_T5_DATACH2(x) (((x) >> S_T5_DATACH2) & M_T5_DATACH2)
41729 #define V_SOPPT1(x) ((x) << S_SOPPT1)
41730 #define F_SOPPT1    V_SOPPT1(1U)
41733 #define V_EOPPT1(x) ((x) << S_EOPPT1)
41734 #define F_EOPPT1    V_EOPPT1(1U)
41738 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
41739 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
41742 #define V_ERRPT1(x) ((x) << S_ERRPT1)
41743 #define F_ERRPT1    V_ERRPT1(1U)
41746 #define V_FULLPT1(x) ((x) << S_FULLPT1)
41747 #define F_FULLPT1    V_FULLPT1(1U)
41750 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
41751 #define F_VALIDPT1    V_VALIDPT1(1U)
41755 #define V_DATAPT1(x) ((x) << S_DATAPT1)
41756 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
41759 #define V_SOPPT0(x) ((x) << S_SOPPT0)
41760 #define F_SOPPT0    V_SOPPT0(1U)
41763 #define V_EOPPT0(x) ((x) << S_EOPPT0)
41764 #define F_EOPPT0    V_EOPPT0(1U)
41768 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
41769 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
41772 #define V_ERRPT0(x) ((x) << S_ERRPT0)
41773 #define F_ERRPT0    V_ERRPT0(1U)
41776 #define V_FULLPT0(x) ((x) << S_FULLPT0)
41777 #define F_FULLPT0    V_FULLPT0(1U)
41780 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
41781 #define F_VALIDPT0    V_VALIDPT0(1U)
41785 #define V_DATAPT0(x) ((x) << S_DATAPT0)
41786 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
41790 #define V_T5_SIZEPT1(x) ((x) << S_T5_SIZEPT1)
41791 #define G_T5_SIZEPT1(x) (((x) >> S_T5_SIZEPT1) & M_T5_SIZEPT1)
41794 #define V_T5_ERRPT1(x) ((x) << S_T5_ERRPT1)
41795 #define F_T5_ERRPT1    V_T5_ERRPT1(1U)
41798 #define V_T5_FULLPT1(x) ((x) << S_T5_FULLPT1)
41799 #define F_T5_FULLPT1    V_T5_FULLPT1(1U)
41802 #define V_T5_VALIDPT1(x) ((x) << S_T5_VALIDPT1)
41803 #define F_T5_VALIDPT1    V_T5_VALIDPT1(1U)
41807 #define V_T5_DATAPT1(x) ((x) << S_T5_DATAPT1)
41808 #define G_T5_DATAPT1(x) (((x) >> S_T5_DATAPT1) & M_T5_DATAPT1)
41812 #define V_T5_SIZEPT0(x) ((x) << S_T5_SIZEPT0)
41813 #define G_T5_SIZEPT0(x) (((x) >> S_T5_SIZEPT0) & M_T5_SIZEPT0)
41816 #define V_T5_ERRPT0(x) ((x) << S_T5_ERRPT0)
41817 #define F_T5_ERRPT0    V_T5_ERRPT0(1U)
41820 #define V_T5_FULLPT0(x) ((x) << S_T5_FULLPT0)
41821 #define F_T5_FULLPT0    V_T5_FULLPT0(1U)
41824 #define V_T5_VALIDPT0(x) ((x) << S_T5_VALIDPT0)
41825 #define F_T5_VALIDPT0    V_T5_VALIDPT0(1U)
41829 #define V_T5_DATAPT0(x) ((x) << S_T5_DATAPT0)
41830 #define G_T5_DATAPT0(x) (((x) >> S_T5_DATAPT0) & M_T5_DATAPT0)
41835 #define V_SOPPT3(x) ((x) << S_SOPPT3)
41836 #define F_SOPPT3    V_SOPPT3(1U)
41839 #define V_EOPPT3(x) ((x) << S_EOPPT3)
41840 #define F_EOPPT3    V_EOPPT3(1U)
41844 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
41845 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
41848 #define V_ERRPT3(x) ((x) << S_ERRPT3)
41849 #define F_ERRPT3    V_ERRPT3(1U)
41852 #define V_FULLPT3(x) ((x) << S_FULLPT3)
41853 #define F_FULLPT3    V_FULLPT3(1U)
41856 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
41857 #define F_VALIDPT3    V_VALIDPT3(1U)
41861 #define V_DATAPT3(x) ((x) << S_DATAPT3)
41862 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
41865 #define V_SOPPT2(x) ((x) << S_SOPPT2)
41866 #define F_SOPPT2    V_SOPPT2(1U)
41869 #define V_EOPPT2(x) ((x) << S_EOPPT2)
41870 #define F_EOPPT2    V_EOPPT2(1U)
41874 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
41875 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
41878 #define V_ERRPT2(x) ((x) << S_ERRPT2)
41879 #define F_ERRPT2    V_ERRPT2(1U)
41882 #define V_FULLPT2(x) ((x) << S_FULLPT2)
41883 #define F_FULLPT2    V_FULLPT2(1U)
41886 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
41887 #define F_VALIDPT2    V_VALIDPT2(1U)
41891 #define V_DATAPT2(x) ((x) << S_DATAPT2)
41892 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
41896 #define V_T5_SIZEPT3(x) ((x) << S_T5_SIZEPT3)
41897 #define G_T5_SIZEPT3(x) (((x) >> S_T5_SIZEPT3) & M_T5_SIZEPT3)
41900 #define V_T5_ERRPT3(x) ((x) << S_T5_ERRPT3)
41901 #define F_T5_ERRPT3    V_T5_ERRPT3(1U)
41904 #define V_T5_FULLPT3(x) ((x) << S_T5_FULLPT3)
41905 #define F_T5_FULLPT3    V_T5_FULLPT3(1U)
41908 #define V_T5_VALIDPT3(x) ((x) << S_T5_VALIDPT3)
41909 #define F_T5_VALIDPT3    V_T5_VALIDPT3(1U)
41913 #define V_T5_DATAPT3(x) ((x) << S_T5_DATAPT3)
41914 #define G_T5_DATAPT3(x) (((x) >> S_T5_DATAPT3) & M_T5_DATAPT3)
41918 #define V_T5_SIZEPT2(x) ((x) << S_T5_SIZEPT2)
41919 #define G_T5_SIZEPT2(x) (((x) >> S_T5_SIZEPT2) & M_T5_SIZEPT2)
41922 #define V_T5_ERRPT2(x) ((x) << S_T5_ERRPT2)
41923 #define F_T5_ERRPT2    V_T5_ERRPT2(1U)
41926 #define V_T5_FULLPT2(x) ((x) << S_T5_FULLPT2)
41927 #define F_T5_FULLPT2    V_T5_FULLPT2(1U)
41930 #define V_T5_VALIDPT2(x) ((x) << S_T5_VALIDPT2)
41931 #define F_T5_VALIDPT2    V_T5_VALIDPT2(1U)
41935 #define V_T5_DATAPT2(x) ((x) << S_T5_DATAPT2)
41936 #define G_T5_DATAPT2(x) (((x) >> S_T5_DATAPT2) & M_T5_DATAPT2)
41942 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
41943 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
41949 #define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
41950 #define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
41956 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
41957 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
41961 #define V_PORTH(x) ((x) << S_PORTH)
41962 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
41966 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
41967 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
41971 #define V_PORTL(x) ((x) << S_PORTL)
41972 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
41977 #define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
41978 #define F_LPBKPADENPT3    V_LPBKPADENPT3(1U)
41981 #define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
41982 #define F_LPBKPADENPT2    V_LPBKPADENPT2(1U)
41985 #define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
41986 #define F_LPBKPADENPT1    V_LPBKPADENPT1(1U)
41989 #define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
41990 #define F_LPBKPADENPT0    V_LPBKPADENPT0(1U)
41993 #define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
41994 #define F_MACPADENPT3    V_MACPADENPT3(1U)
41997 #define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
41998 #define F_MACPADENPT2    V_MACPADENPT2(1U)
42000 #define S_MACPADENPT1    1
42001 #define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
42002 #define F_MACPADENPT1    V_MACPADENPT1(1U)
42005 #define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
42006 #define F_MACPADENPT0    V_MACPADENPT0(1U)
42012 #define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
42013 #define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
42017 #define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
42018 #define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
42022 #define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
42023 #define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
42027 #define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
42028 #define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
42034 #define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
42035 #define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
42040 #define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
42041 #define F_PFNOVFDROP    V_PFNOVFDROP(1U)
42044 #define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
42045 #define F_NCSI_CH4_CLR    V_NCSI_CH4_CLR(1U)
42048 #define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
42049 #define F_TP2MPS_CH3_CLR    V_TP2MPS_CH3_CLR(1U)
42052 #define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
42053 #define F_TP2MPS_CH2_CLR    V_TP2MPS_CH2_CLR(1U)
42055 #define S_TP2MPS_CH1_CLR    1
42056 #define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
42057 #define F_TP2MPS_CH1_CLR    V_TP2MPS_CH1_CLR(1U)
42060 #define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
42061 #define F_TP2MPS_CH0_CLR    V_TP2MPS_CH0_CLR(1U)
42066 #define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
42067 #define F_TXOUTLPBK3_CGEN    V_TXOUTLPBK3_CGEN(1U)
42070 #define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
42071 #define F_TXOUTLPBK2_CGEN    V_TXOUTLPBK2_CGEN(1U)
42074 #define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
42075 #define F_TXOUTLPBK1_CGEN    V_TXOUTLPBK1_CGEN(1U)
42078 #define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
42079 #define F_TXOUTLPBK0_CGEN    V_TXOUTLPBK0_CGEN(1U)
42082 #define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
42083 #define F_TXOUTMAC3_CGEN    V_TXOUTMAC3_CGEN(1U)
42086 #define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
42087 #define F_TXOUTMAC2_CGEN    V_TXOUTMAC2_CGEN(1U)
42090 #define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
42091 #define F_TXOUTMAC1_CGEN    V_TXOUTMAC1_CGEN(1U)
42094 #define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
42095 #define F_TXOUTMAC0_CGEN    V_TXOUTMAC0_CGEN(1U)
42098 #define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
42099 #define F_TXSCHLPBK3_CGEN    V_TXSCHLPBK3_CGEN(1U)
42102 #define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
42103 #define F_TXSCHLPBK2_CGEN    V_TXSCHLPBK2_CGEN(1U)
42106 #define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
42107 #define F_TXSCHLPBK1_CGEN    V_TXSCHLPBK1_CGEN(1U)
42110 #define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
42111 #define F_TXSCHLPBK0_CGEN    V_TXSCHLPBK0_CGEN(1U)
42114 #define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
42115 #define F_TXSCHMAC3_CGEN    V_TXSCHMAC3_CGEN(1U)
42118 #define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
42119 #define F_TXSCHMAC2_CGEN    V_TXSCHMAC2_CGEN(1U)
42122 #define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
42123 #define F_TXSCHMAC1_CGEN    V_TXSCHMAC1_CGEN(1U)
42126 #define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
42127 #define F_TXSCHMAC0_CGEN    V_TXSCHMAC0_CGEN(1U)
42130 #define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
42131 #define F_TXINCH4_CGEN    V_TXINCH4_CGEN(1U)
42134 #define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
42135 #define F_TXINCH3_CGEN    V_TXINCH3_CGEN(1U)
42138 #define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
42139 #define F_TXINCH2_CGEN    V_TXINCH2_CGEN(1U)
42142 #define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
42143 #define F_TXINCH1_CGEN    V_TXINCH1_CGEN(1U)
42146 #define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
42147 #define F_TXINCH0_CGEN    V_TXINCH0_CGEN(1U)
42153 #define V_ENABLELBK_CH3(x) ((x) << S_ENABLELBK_CH3)
42154 #define F_ENABLELBK_CH3    V_ENABLELBK_CH3(1U)
42157 #define V_ENABLELBK_CH2(x) ((x) << S_ENABLELBK_CH2)
42158 #define F_ENABLELBK_CH2    V_ENABLELBK_CH2(1U)
42160 #define S_ENABLELBK_CH1    1
42161 #define V_ENABLELBK_CH1(x) ((x) << S_ENABLELBK_CH1)
42162 #define F_ENABLELBK_CH1    V_ENABLELBK_CH1(1U)
42165 #define V_ENABLELBK_CH0(x) ((x) << S_ENABLELBK_CH0)
42166 #define F_ENABLELBK_CH0    V_ENABLELBK_CH0(1U)
42172 #define V_DBG_CNT_CTL(x) ((x) << S_DBG_CNT_CTL)
42173 #define G_DBG_CNT_CTL(x) (((x) >> S_DBG_CNT_CTL) & M_DBG_CNT_CTL)
42187 #define S_COUNTVFINPF    1
42188 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
42189 #define F_COUNTVFINPF    V_COUNTVFINPF(1U)
42192 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
42193 #define F_LPBKERRSTAT    V_LPBKERRSTAT(1U)
42196 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
42197 #define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)
42200 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
42201 #define F_STOPSTAT    V_STOPSTAT(1U)
42204 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
42205 #define F_STATWRITECTRL    V_STATWRITECTRL(1U)
42208 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
42209 #define F_COUNTLBPF    V_COUNTLBPF(1U)
42212 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
42213 #define F_COUNTLBVF    V_COUNTLBVF(1U)
42216 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
42217 #define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
42220 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
42221 #define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
42224 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
42225 #define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
42228 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
42229 #define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
42234 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
42235 #define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)
42241 #define V_RXBG(x) ((x) << S_RXBG)
42242 #define F_RXBG    V_RXBG(1U)
42246 #define V_RXVF(x) ((x) << S_RXVF)
42247 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
42251 #define V_TXVF(x) ((x) << S_TXVF)
42252 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
42256 #define V_RXPF(x) ((x) << S_RXPF)
42257 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
42261 #define V_TXPF(x) ((x) << S_TXPF)
42262 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
42266 #define V_RXPORT(x) ((x) << S_RXPORT)
42267 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
42271 #define V_LBPORT(x) ((x) << S_LBPORT)
42272 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
42276 #define V_TXPORT(x) ((x) << S_TXPORT)
42277 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
42281 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
42282 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
42286 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
42287 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
42291 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
42292 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
42296 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
42297 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
42301 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
42302 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
42306 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
42307 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
42315 #define V_TX(x) ((x) << S_TX)
42316 #define G_TX(x) (((x) >> S_TX) & M_TX)
42320 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
42321 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
42325 #define V_DROP(x) ((x) << S_DROP)
42326 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
42330 #define V_TXCH(x) ((x) << S_TXCH)
42331 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
42339 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
42340 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
42344 #define V_LPBK(x) ((x) << S_LPBK)
42345 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
42349 #define V_NQ(x) ((x) << S_NQ)
42350 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
42354 #define V_PV(x) ((x) << S_PV)
42355 #define G_PV(x) (((x) >> S_PV) & M_PV)
42359 #define V_MAC(x) ((x) << S_MAC)
42360 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
42366 #define S_STATMEMSEL    1
42368 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
42369 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
42375 #define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
42376 #define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
42380 #define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
42381 #define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
42385 #define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
42386 #define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
42424 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
42425 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
42429 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
42430 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
42438 #define V_BGRX(x) ((x) << S_BGRX)
42439 #define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
42445 #define V_PTLPBK(x) ((x) << S_PTLPBK)
42446 #define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
42450 #define V_PTTX(x) ((x) << S_PTTX)
42451 #define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
42455 #define V_PTRX(x) ((x) << S_PTRX)
42456 #define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
42462 #define V_PFTX(x) ((x) << S_PFTX)
42463 #define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
42467 #define V_PFRX(x) ((x) << S_PFRX)
42468 #define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
42489 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
42490 #define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)
42493 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
42494 #define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)
42497 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
42498 #define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)
42500 #define S_TRCEN    1
42501 #define V_TRCEN(x) ((x) << S_TRCEN)
42502 #define F_TRCEN    V_TRCEN(1U)
42505 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
42506 #define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)
42509 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
42510 #define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)
42519 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
42520 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
42524 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
42525 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
42531 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
42532 #define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)
42535 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
42536 #define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)
42539 #define V_TFEN(x) ((x) << S_TFEN)
42540 #define F_TFEN    V_TFEN(1U)
42544 #define V_TFPORT(x) ((x) << S_TFPORT)
42545 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
42548 #define V_TFDROP(x) ((x) << S_TFDROP)
42549 #define F_TFDROP    V_TFDROP(1U)
42552 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
42553 #define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)
42557 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
42558 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
42562 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
42563 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
42566 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
42567 #define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)
42570 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
42571 #define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)
42574 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
42575 #define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)
42578 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
42579 #define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)
42582 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
42583 #define F_T5_TFEN    V_T5_TFEN(1U)
42587 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
42588 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
42594 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
42595 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
42599 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
42600 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
42606 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
42607 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
42613 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
42614 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
42618 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
42619 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
42623 #define S_TRCMEMSEL    1
42625 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
42626 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
42631 #define V_MISCPERR(x) ((x) << S_MISCPERR)
42632 #define F_MISCPERR    V_MISCPERR(1U)
42636 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
42637 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
42641 #define V_FILTMEM(x) ((x) << S_FILTMEM)
42642 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
42645 #define V_T7_MISCPERR(x) ((x) << S_T7_MISCPERR)
42646 #define F_T7_MISCPERR    V_T7_MISCPERR(1U)
42650 #define V_T7_PKTFIFO(x) ((x) << S_T7_PKTFIFO)
42651 #define G_T7_PKTFIFO(x) (((x) >> S_T7_PKTFIFO) & M_T7_PKTFIFO)
42655 #define V_T7_FILTMEM(x) ((x) << S_T7_FILTMEM)
42656 #define G_T7_FILTMEM(x) (((x) >> S_T7_FILTMEM) & M_T7_FILTMEM)
42661 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
42662 #define F_TRCPLERRENB    V_TRCPLERRENB(1U)
42687 #define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
42688 #define F_TRCMPS2TP_MACONLY    V_TRCMPS2TP_MACONLY(1U)
42691 #define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
42692 #define F_TRCALLMPS2TP    V_TRCALLMPS2TP(1U)
42695 #define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
42696 #define F_TRCALLTP2MPS    V_TRCALLTP2MPS(1U)
42699 #define V_TRCALLVF(x) ((x) << S_TRCALLVF)
42700 #define F_TRCALLVF    V_TRCALLVF(1U)
42703 #define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
42704 #define F_TRC_OFLD_EN    V_TRC_OFLD_EN(1U)
42707 #define V_VFFILTEN(x) ((x) << S_VFFILTEN)
42708 #define F_VFFILTEN    V_VFFILTEN(1U)
42712 #define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
42713 #define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
42716 #define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
42717 #define F_VFFILTVALID    V_VFFILTVALID(1U)
42721 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
42722 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
42725 #define V_T6_TRCMPS2TP_MACONLY(x) ((x) << S_T6_TRCMPS2TP_MACONLY)
42726 #define F_T6_TRCMPS2TP_MACONLY    V_T6_TRCMPS2TP_MACONLY(1U)
42729 #define V_T6_TRCALLMPS2TP(x) ((x) << S_T6_TRCALLMPS2TP)
42730 #define F_T6_TRCALLMPS2TP    V_T6_TRCALLMPS2TP(1U)
42733 #define V_T6_TRCALLTP2MPS(x) ((x) << S_T6_TRCALLTP2MPS)
42734 #define F_T6_TRCALLTP2MPS    V_T6_TRCALLTP2MPS(1U)
42737 #define V_T6_TRCALLVF(x) ((x) << S_T6_TRCALLVF)
42738 #define F_T6_TRCALLVF    V_T6_TRCALLVF(1U)
42741 #define V_T6_TRC_OFLD_EN(x) ((x) << S_T6_TRC_OFLD_EN)
42742 #define F_T6_TRC_OFLD_EN    V_T6_TRC_OFLD_EN(1U)
42745 #define V_T6_VFFILTEN(x) ((x) << S_T6_VFFILTEN)
42746 #define F_T6_VFFILTEN    V_T6_VFFILTEN(1U)
42750 #define V_T6_VFFILTMASK(x) ((x) << S_T6_VFFILTMASK)
42751 #define G_T6_VFFILTMASK(x) (((x) >> S_T6_VFFILTMASK) & M_T6_VFFILTMASK)
42754 #define V_T6_VFFILTVALID(x) ((x) << S_T6_VFFILTVALID)
42755 #define F_T6_VFFILTVALID    V_T6_VFFILTVALID(1U)
42759 #define V_T6_VFFILTDATA(x) ((x) << S_T6_VFFILTDATA)
42760 #define G_T6_VFFILTDATA(x) (((x) >> S_T6_VFFILTDATA) & M_T6_VFFILTDATA)
42769 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
42770 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
42809 #define V_T7_MPSTRCCGEN(x) ((x) << S_T7_MPSTRCCGEN)
42810 #define G_T7_MPSTRCCGEN(x) (((x) >> S_T7_MPSTRCCGEN) & M_T7_MPSTRCCGEN)
42819 #define V_T7_TRCPLERRENB(x) ((x) << S_T7_TRCPLERRENB)
42820 #define F_T7_TRCPLERRENB    V_T7_TRCPLERRENB(1U)
42829 #define V_TRC_TF_ECC(x) ((x) << S_TRC_TF_ECC)
42830 #define G_TRC_TF_ECC(x) (((x) >> S_TRC_TF_ECC) & M_TRC_TF_ECC)
42834 #define V_MPS2MAC_CONV_TRC_CERR(x) ((x) << S_MPS2MAC_CONV_TRC_CERR)
42835 #define G_MPS2MAC_CONV_TRC_CERR(x) (((x) >> S_MPS2MAC_CONV_TRC_CERR) & M_MPS2MAC_CONV_TRC_CERR)
42839 #define V_MPS2MAC_CONV_TRC(x) ((x) << S_MPS2MAC_CONV_TRC)
42840 #define G_MPS2MAC_CONV_TRC(x) (((x) >> S_MPS2MAC_CONV_TRC) & M_MPS2MAC_CONV_TRC)
42843 #define V_TF0_PERR_1(x) ((x) << S_TF0_PERR_1)
42844 #define F_TF0_PERR_1    V_TF0_PERR_1(1U)
42847 #define V_TF1_PERR_1(x) ((x) << S_TF1_PERR_1)
42848 #define F_TF1_PERR_1    V_TF1_PERR_1(1U)
42851 #define V_TF2_PERR_1(x) ((x) << S_TF2_PERR_1)
42852 #define F_TF2_PERR_1    V_TF2_PERR_1(1U)
42855 #define V_TF3_PERR_1(x) ((x) << S_TF3_PERR_1)
42856 #define F_TF3_PERR_1    V_TF3_PERR_1(1U)
42859 #define V_TF4_PERR_1(x) ((x) << S_TF4_PERR_1)
42860 #define F_TF4_PERR_1    V_TF4_PERR_1(1U)
42863 #define V_TF0_PERR_0(x) ((x) << S_TF0_PERR_0)
42864 #define F_TF0_PERR_0    V_TF0_PERR_0(1U)
42867 #define V_TF1_PERR_0(x) ((x) << S_TF1_PERR_0)
42868 #define F_TF1_PERR_0    V_TF1_PERR_0(1U)
42871 #define V_TF2_PERR_0(x) ((x) << S_TF2_PERR_0)
42872 #define F_TF2_PERR_0    V_TF2_PERR_0(1U)
42875 #define V_TF3_PERR_0(x) ((x) << S_TF3_PERR_0)
42876 #define F_TF3_PERR_0    V_TF3_PERR_0(1U)
42879 #define V_TF4_PERR_0(x) ((x) << S_TF4_PERR_0)
42880 #define F_TF4_PERR_0    V_TF4_PERR_0(1U)
42884 #define V_PERR_TF_IN_CTL(x) ((x) << S_PERR_TF_IN_CTL)
42885 #define G_PERR_TF_IN_CTL(x) (((x) >> S_PERR_TF_IN_CTL) & M_PERR_TF_IN_CTL)
42892 #define V_T7_TRC_TF_ECC(x) ((x) << S_T7_TRC_TF_ECC)
42893 #define G_T7_TRC_TF_ECC(x) (((x) >> S_T7_TRC_TF_ECC) & M_T7_TRC_TF_ECC)
42898 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
42899 #define F_MEMWRITEFAULT    V_MEMWRITEFAULT(1U)
42902 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
42903 #define F_MEMWRITEWAITING    V_MEMWRITEWAITING(1U)
42906 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
42907 #define F_CIMNOPROMISCUOUS    V_CIMNOPROMISCUOUS(1U)
42909 #define S_HYPERVISORONLY    1
42910 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
42911 #define F_HYPERVISORONLY    V_HYPERVISORONLY(1U)
42914 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
42915 #define F_VLANCLSEN    V_VLANCLSEN(1U)
42918 #define V_VLANCLSEN_IN(x) ((x) << S_VLANCLSEN_IN)
42919 #define F_VLANCLSEN_IN    V_VLANCLSEN_IN(1U)
42922 #define V_DISTCAMPARCHK(x) ((x) << S_DISTCAMPARCHK)
42923 #define F_DISTCAMPARCHK    V_DISTCAMPARCHK(1U)
42926 #define V_VLANLKPEN(x) ((x) << S_VLANLKPEN)
42927 #define F_VLANLKPEN    V_VLANLKPEN(1U)
42933 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
42934 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
42938 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
42939 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
42943 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
42944 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
42953 #define S_CLS_MEMSEL    1
42955 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
42956 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
42961 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
42962 #define F_HASHSRAM    V_HASHSRAM(1U)
42964 #define S_MATCHTCAM    1
42965 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
42966 #define F_MATCHTCAM    V_MATCHTCAM(1U)
42969 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
42970 #define F_MATCHSRAM    V_MATCHSRAM(1U)
42973 #define V_CIM2MPS_INTF_PAR(x) ((x) << S_CIM2MPS_INTF_PAR)
42974 #define F_CIM2MPS_INTF_PAR    V_CIM2MPS_INTF_PAR(1U)
42977 #define V_TCAM_CRC_SRAM(x) ((x) << S_TCAM_CRC_SRAM)
42978 #define F_TCAM_CRC_SRAM    V_TCAM_CRC_SRAM(1U)
42983 #define V_PLERRENB(x) ((x) << S_PLERRENB)
42984 #define F_PLERRENB    V_PLERRENB(1U)
42987 #define V_T7_PLERRENB(x) ((x) << S_T7_PLERRENB)
42988 #define F_T7_PLERRENB    V_T7_PLERRENB(1U)
42997 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
42998 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
43001 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
43002 #define F_CLS_REPLICATE    V_CLS_REPLICATE(1U)
43006 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
43007 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
43011 #define V_CLS_VF(x) ((x) << S_CLS_VF)
43012 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
43015 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
43016 #define F_CLS_VF_VLD    V_CLS_VF_VLD(1U)
43020 #define V_CLS_PF(x) ((x) << S_CLS_PF)
43021 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
43025 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
43026 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
43030 #define V_CLS_SPARE(x) ((x) << S_CLS_SPARE)
43031 #define G_CLS_SPARE(x) (((x) >> S_CLS_SPARE) & M_CLS_SPARE)
43035 #define V_T6_CLS_PRIORITY(x) ((x) << S_T6_CLS_PRIORITY)
43036 #define G_T6_CLS_PRIORITY(x) (((x) >> S_T6_CLS_PRIORITY) & M_T6_CLS_PRIORITY)
43039 #define V_T6_CLS_REPLICATE(x) ((x) << S_T6_CLS_REPLICATE)
43040 #define F_T6_CLS_REPLICATE    V_T6_CLS_REPLICATE(1U)
43044 #define V_T6_CLS_INDEX(x) ((x) << S_T6_CLS_INDEX)
43045 #define G_T6_CLS_INDEX(x) (((x) >> S_T6_CLS_INDEX) & M_T6_CLS_INDEX)
43049 #define V_T6_CLS_VF(x) ((x) << S_T6_CLS_VF)
43050 #define G_T6_CLS_VF(x) (((x) >> S_T6_CLS_VF) & M_T6_CLS_VF)
43054 #define V_T7_CLS_SPARE(x) ((x) << S_T7_CLS_SPARE)
43055 #define G_T7_CLS_SPARE(x) (((x) >> S_T7_CLS_SPARE) & M_T7_CLS_SPARE)
43059 #define V_T7_1_CLS_PRIORITY(x) ((x) << S_T7_1_CLS_PRIORITY)
43060 #define G_T7_1_CLS_PRIORITY(x) (((x) >> S_T7_1_CLS_PRIORITY) & M_T7_1_CLS_PRIORITY)
43063 #define V_T7_1_CLS_REPLICATE(x) ((x) << S_T7_1_CLS_REPLICATE)
43064 #define F_T7_1_CLS_REPLICATE    V_T7_1_CLS_REPLICATE(1U)
43068 #define V_T7_1_CLS_INDEX(x) ((x) << S_T7_1_CLS_INDEX)
43069 #define G_T7_1_CLS_INDEX(x) (((x) >> S_T7_1_CLS_INDEX) & M_T7_1_CLS_INDEX)
43074 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
43075 #define F_PLTESTCTL    V_PLTESTCTL(1U)
43080 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
43081 #define F_PRTBMCCTL    V_PRTBMCCTL(1U)
43109 #define V_CLSTRCMACDAHI(x) ((x) << S_CLSTRCMACDAHI)
43110 #define G_CLSTRCMACDAHI(x) (((x) >> S_CLSTRCMACDAHI) & M_CLSTRCMACDAHI)
43117 #define V_CLSTRCMACSAHI(x) ((x) << S_CLSTRCMACSAHI)
43118 #define G_CLSTRCMACSAHI(x) (((x) >> S_CLSTRCMACSAHI) & M_CLSTRCMACSAHI)
43123 #define V_CLSTRCVLANVLD(x) ((x) << S_CLSTRCVLANVLD)
43124 #define F_CLSTRCVLANVLD    V_CLSTRCVLANVLD(1U)
43128 #define V_CLSTRCVLANID(x) ((x) << S_CLSTRCVLANID)
43129 #define G_CLSTRCVLANID(x) (((x) >> S_CLSTRCVLANID) & M_CLSTRCVLANID)
43133 #define V_CLSTRCREQPORT(x) ((x) << S_CLSTRCREQPORT)
43134 #define G_CLSTRCREQPORT(x) (((x) >> S_CLSTRCREQPORT) & M_CLSTRCREQPORT)
43139 #define V_CLSTRCLKPTYPE(x) ((x) << S_CLSTRCLKPTYPE)
43140 #define F_CLSTRCLKPTYPE    V_CLSTRCLKPTYPE(1U)
43143 #define V_CLSTRCDIPHIT(x) ((x) << S_CLSTRCDIPHIT)
43144 #define F_CLSTRCDIPHIT    V_CLSTRCDIPHIT(1U)
43148 #define V_CLSTRCVNI(x) ((x) << S_CLSTRCVNI)
43149 #define G_CLSTRCVNI(x) (((x) >> S_CLSTRCVNI) & M_CLSTRCVNI)
43154 #define V_CLSTRCPORTNUM(x) ((x) << S_CLSTRCPORTNUM)
43155 #define F_CLSTRCPORTNUM    V_CLSTRCPORTNUM(1U)
43159 #define V_CLSTRCPRIORITY(x) ((x) << S_CLSTRCPRIORITY)
43160 #define G_CLSTRCPRIORITY(x) (((x) >> S_CLSTRCPRIORITY) & M_CLSTRCPRIORITY)
43163 #define V_CLSTRCMULTILISTEN(x) ((x) << S_CLSTRCMULTILISTEN)
43164 #define F_CLSTRCMULTILISTEN    V_CLSTRCMULTILISTEN(1U)
43167 #define V_CLSTRCREPLICATE(x) ((x) << S_CLSTRCREPLICATE)
43168 #define F_CLSTRCREPLICATE    V_CLSTRCREPLICATE(1U)
43172 #define V_CLSTRCPORTMAP(x) ((x) << S_CLSTRCPORTMAP)
43173 #define G_CLSTRCPORTMAP(x) (((x) >> S_CLSTRCPORTMAP) & M_CLSTRCPORTMAP)
43177 #define V_CLSTRCMATCH(x) ((x) << S_CLSTRCMATCH)
43178 #define G_CLSTRCMATCH(x) (((x) >> S_CLSTRCMATCH) & M_CLSTRCMATCH)
43182 #define V_CLSTRCINDEX(x) ((x) << S_CLSTRCINDEX)
43183 #define G_CLSTRCINDEX(x) (((x) >> S_CLSTRCINDEX) & M_CLSTRCINDEX)
43186 #define V_CLSTRCVF_VLD(x) ((x) << S_CLSTRCVF_VLD)
43187 #define F_CLSTRCVF_VLD    V_CLSTRCVF_VLD(1U)
43191 #define V_CLSTRCPF(x) ((x) << S_CLSTRCPF)
43192 #define G_CLSTRCPF(x) (((x) >> S_CLSTRCPF) & M_CLSTRCPF)
43196 #define V_CLSTRCVF(x) ((x) << S_CLSTRCVF)
43197 #define G_CLSTRCVF(x) (((x) >> S_CLSTRCVF) & M_CLSTRCVF)
43200 #define V_T7_CLSTRCMATCH(x) ((x) << S_T7_CLSTRCMATCH)
43201 #define F_T7_CLSTRCMATCH    V_T7_CLSTRCMATCH(1U)
43205 #define V_T7_CLSTRCINDEX(x) ((x) << S_T7_CLSTRCINDEX)
43206 #define G_T7_CLSTRCINDEX(x) (((x) >> S_T7_CLSTRCINDEX) & M_T7_CLSTRCINDEX)
43212 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
43213 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
43217 #define V_VLANPF(x) ((x) << S_VLANPF)
43218 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
43221 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
43222 #define F_VLAN_VALID    V_VLAN_VALID(1U)
43227 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
43228 #define F_MULTILISTEN3    V_MULTILISTEN3(1U)
43231 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
43232 #define F_MULTILISTEN2    V_MULTILISTEN2(1U)
43235 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
43236 #define F_MULTILISTEN1    V_MULTILISTEN1(1U)
43239 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
43240 #define F_MULTILISTEN0    V_MULTILISTEN0(1U)
43244 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
43245 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
43249 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
43250 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
43254 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
43255 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
43259 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
43260 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
43263 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
43264 #define F_SRAM_VLD    V_SRAM_VLD(1U)
43269 #define V_T6_DISENCAPOUTERRPLCT(x) ((x) << S_T6_DISENCAPOUTERRPLCT)
43270 #define F_T6_DISENCAPOUTERRPLCT    V_T6_DISENCAPOUTERRPLCT(1U)
43273 #define V_T6_DISENCAP(x) ((x) << S_T6_DISENCAP)
43274 #define F_T6_DISENCAP    V_T6_DISENCAP(1U)
43277 #define V_T6_MULTILISTEN3(x) ((x) << S_T6_MULTILISTEN3)
43278 #define F_T6_MULTILISTEN3    V_T6_MULTILISTEN3(1U)
43281 #define V_T6_MULTILISTEN2(x) ((x) << S_T6_MULTILISTEN2)
43282 #define F_T6_MULTILISTEN2    V_T6_MULTILISTEN2(1U)
43285 #define V_T6_MULTILISTEN1(x) ((x) << S_T6_MULTILISTEN1)
43286 #define F_T6_MULTILISTEN1    V_T6_MULTILISTEN1(1U)
43289 #define V_T6_MULTILISTEN0(x) ((x) << S_T6_MULTILISTEN0)
43290 #define F_T6_MULTILISTEN0    V_T6_MULTILISTEN0(1U)
43294 #define V_T6_SRAM_PRIO3(x) ((x) << S_T6_SRAM_PRIO3)
43295 #define G_T6_SRAM_PRIO3(x) (((x) >> S_T6_SRAM_PRIO3) & M_T6_SRAM_PRIO3)
43299 #define V_T6_SRAM_PRIO2(x) ((x) << S_T6_SRAM_PRIO2)
43300 #define G_T6_SRAM_PRIO2(x) (((x) >> S_T6_SRAM_PRIO2) & M_T6_SRAM_PRIO2)
43304 #define V_T6_SRAM_PRIO1(x) ((x) << S_T6_SRAM_PRIO1)
43305 #define G_T6_SRAM_PRIO1(x) (((x) >> S_T6_SRAM_PRIO1) & M_T6_SRAM_PRIO1)
43309 #define V_T6_SRAM_PRIO0(x) ((x) << S_T6_SRAM_PRIO0)
43310 #define G_T6_SRAM_PRIO0(x) (((x) >> S_T6_SRAM_PRIO0) & M_T6_SRAM_PRIO0)
43313 #define V_T6_SRAM_VLD(x) ((x) << S_T6_SRAM_VLD)
43314 #define F_T6_SRAM_VLD    V_T6_SRAM_VLD(1U)
43319 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
43320 #define F_MACPARITY1    V_MACPARITY1(1U)
43323 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
43324 #define F_MACPARITY0    V_MACPARITY0(1U)
43328 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
43329 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
43333 #define V_PORTMAP(x) ((x) << S_PORTMAP)
43334 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
43339 #define V_MACPARITY2(x) ((x) << S_MACPARITY2)
43340 #define F_MACPARITY2    V_MACPARITY2(1U)
43343 #define V_SRAMWRN(x) ((x) << S_SRAMWRN)
43344 #define F_SRAMWRN    V_SRAMWRN(1U)
43348 #define V_SRAMSPARE(x) ((x) << S_SRAMSPARE)
43349 #define G_SRAMSPARE(x) (((x) >> S_SRAMSPARE) & M_SRAMSPARE)
43353 #define V_SRAMINDEX(x) ((x) << S_SRAMINDEX)
43354 #define G_SRAMINDEX(x) (((x) >> S_SRAMINDEX) & M_SRAMINDEX)
43359 #define V_T7_CTLCMDTYPE(x) ((x) << S_T7_CTLCMDTYPE)
43360 #define F_T7_CTLCMDTYPE    V_T7_CTLCMDTYPE(1U)
43363 #define V_T7_CTLXYBITSEL(x) ((x) << S_T7_CTLXYBITSEL)
43364 #define F_T7_CTLXYBITSEL    V_T7_CTLXYBITSEL(1U)
43368 #define V_T7_CTLTCAMINDEX(x) ((x) << S_T7_CTLTCAMINDEX)
43369 #define G_T7_CTLTCAMINDEX(x) (((x) >> S_T7_CTLTCAMINDEX) & M_T7_CTLTCAMINDEX)
43374 #define V_LKPTYPE(x) ((x) << S_LKPTYPE)
43375 #define F_LKPTYPE    V_LKPTYPE(1U)
43383 #define V_TCAMYH(x) ((x) << S_TCAMYH)
43384 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
43390 #define V_VIDL(x) ((x) << S_VIDL)
43391 #define G_VIDL(x) (((x) >> S_VIDL) & M_VIDL)
43395 #define V_DMACH(x) ((x) << S_DMACH)
43396 #define G_DMACH(x) (((x) >> S_DMACH) & M_DMACH)
43402 #define V_CTLCMDTYPE(x) ((x) << S_CTLCMDTYPE)
43403 #define F_CTLCMDTYPE    V_CTLCMDTYPE(1U)
43406 #define V_CTLREQID(x) ((x) << S_CTLREQID)
43407 #define F_CTLREQID    V_CTLREQID(1U)
43410 #define V_CTLTCAMSEL(x) ((x) << S_CTLTCAMSEL)
43411 #define F_CTLTCAMSEL    V_CTLTCAMSEL(1U)
43415 #define V_CTLTCAMINDEX(x) ((x) << S_CTLTCAMINDEX)
43416 #define G_CTLTCAMINDEX(x) (((x) >> S_CTLTCAMINDEX) & M_CTLTCAMINDEX)
43419 #define V_CTLXYBITSEL(x) ((x) << S_CTLXYBITSEL)
43420 #define F_CTLXYBITSEL    V_CTLXYBITSEL(1U)
43424 #define V_DATAPORTNUM(x) ((x) << S_DATAPORTNUM)
43425 #define G_DATAPORTNUM(x) (((x) >> S_DATAPORTNUM) & M_DATAPORTNUM)
43429 #define V_DATALKPTYPE(x) ((x) << S_DATALKPTYPE)
43430 #define G_DATALKPTYPE(x) (((x) >> S_DATALKPTYPE) & M_DATALKPTYPE)
43433 #define V_DATADIPHIT(x) ((x) << S_DATADIPHIT)
43434 #define F_DATADIPHIT    V_DATADIPHIT(1U)
43437 #define V_DATAVIDH2(x) ((x) << S_DATAVIDH2)
43438 #define F_DATAVIDH2    V_DATAVIDH2(1U)
43442 #define V_DATAVIDH1(x) ((x) << S_DATAVIDH1)
43443 #define G_DATAVIDH1(x) (((x) >> S_DATAVIDH1) & M_DATAVIDH1)
43447 #define V_T7_CTLTCAMSEL(x) ((x) << S_T7_CTLTCAMSEL)
43448 #define G_T7_CTLTCAMSEL(x) (((x) >> S_T7_CTLTCAMSEL) & M_T7_CTLTCAMSEL)
43452 #define V_T7_1_CTLTCAMINDEX(x) ((x) << S_T7_1_CTLTCAMINDEX)
43453 #define G_T7_1_CTLTCAMINDEX(x) (((x) >> S_T7_1_CTLTCAMINDEX) & M_T7_1_CTLTCAMINDEX)
43459 #define V_TCAMXH(x) ((x) << S_TCAMXH)
43460 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
43486 #define V_MASK_0_2(x) ((x) << S_MASK_0_2)
43487 #define G_MASK_0_2(x) (((x) >> S_MASK_0_2) & M_MASK_0_2)
43495 #define V_MASK_1_2(x) ((x) << S_MASK_1_2)
43496 #define G_MASK_1_2(x) (((x) >> S_MASK_1_2) & M_MASK_1_2)
43507 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
43508 #define F_FILT_VLAN_SEL    V_FILT_VLAN_SEL(1U)
43511 #define V_CBA_EN(x) ((x) << S_CBA_EN)
43512 #define F_CBA_EN    V_CBA_EN(1U)
43516 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
43517 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
43521 #define V_CMPRS(x) ((x) << S_CMPRS)
43522 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
43526 #define V_SNF(x) ((x) << S_SNF)
43527 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
43530 #define V_HASH_TCAM_EN(x) ((x) << S_HASH_TCAM_EN)
43531 #define F_HASH_TCAM_EN    V_HASH_TCAM_EN(1U)
43534 #define V_SND_ORG_PFVF(x) ((x) << S_SND_ORG_PFVF)
43535 #define F_SND_ORG_PFVF    V_SND_ORG_PFVF(1U)
43541 #define V_CTL_P3(x) ((x) << S_CTL_P3)
43542 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
43546 #define V_CTL_P2(x) ((x) << S_CTL_P2)
43547 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
43551 #define V_CTL_P1(x) ((x) << S_CTL_P1)
43552 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
43556 #define V_CTL_P0(x) ((x) << S_CTL_P0)
43557 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
43562 #define V_RST(x) ((x) << S_RST)
43563 #define F_RST    V_RST(1U)
43567 #define V_CNT(x) ((x) << S_CNT)
43568 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
43574 #define V_DEST_SELECT(x) ((x) << S_DEST_SELECT)
43575 #define G_DEST_SELECT(x) (((x) >> S_DEST_SELECT) & M_DEST_SELECT)
43582 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
43583 #define F_CLR_INTR    V_CLR_INTR(1U)
43586 #define V_SET_INTR(x) ((x) << S_SET_INTR)
43587 #define F_SET_INTR    V_SET_INTR(1U)
43591 #define V_USED(x) ((x) << S_USED)
43592 #define G_USED(x) (((x) >> S_USED) & M_USED)
43596 #define V_ALLOC(x) ((x) << S_ALLOC)
43597 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
43601 #define V_T5_USED(x) ((x) << S_T5_USED)
43602 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
43606 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
43607 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
43621 #define V_EN(x) ((x) << S_EN)
43622 #define F_EN    V_EN(1U)
43625 #define V_SEL(x) ((x) << S_SEL)
43626 #define F_SEL    V_SEL(1U)
43630 #define V_MAX(x) ((x) << S_MAX)
43631 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
43635 #define V_BORW(x) ((x) << S_BORW)
43636 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
43640 #define V_T5_MAX(x) ((x) << S_T5_MAX)
43641 #define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
43645 #define V_T5_BORW(x) ((x) << S_T5_BORW)
43646 #define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
43655 #define V_QUOTA(x) ((x) << S_QUOTA)
43656 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
43660 #define V_SHR_USED(x) ((x) << S_SHR_USED)
43661 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
43665 #define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
43666 #define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
43670 #define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
43671 #define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
43678 #define V_TH(x) ((x) << S_TH)
43679 #define G_TH(x) (((x) >> S_TH) & M_TH)
43683 #define V_T5_TH(x) ((x) << S_T5_TH)
43684 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
43688 #define V_T6_TH(x) ((x) << S_T6_TH)
43689 #define G_T6_TH(x) (((x) >> S_T6_TH) & M_T6_TH)
43698 #define V_DROP_WT(x) ((x) << S_DROP_WT)
43699 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
43703 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
43704 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
43708 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
43709 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
43713 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
43714 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
43718 #define V_STOP(x) ((x) << S_STOP)
43719 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
43725 #define V_THRESH(x) ((x) << S_THRESH)
43726 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
43730 #define V_T7_THRESH(x) ((x) << S_T7_THRESH)
43731 #define G_T7_THRESH(x) (((x) >> S_T7_THRESH) & M_T7_THRESH)
43740 #define V_GAP(x) ((x) << S_GAP)
43741 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
43747 #define V_T7_CTL(x) ((x) << S_T7_CTL)
43748 #define F_T7_CTL    V_T7_CTL(1U)
43753 #define V_FF(x) ((x) << S_FF)
43754 #define F_FF    V_FF(1U)
43757 #define V_PGMO(x) ((x) << S_PGMO)
43758 #define F_PGMO    V_PGMO(1U)
43761 #define V_PGME(x) ((x) << S_PGME)
43762 #define F_PGME    V_PGME(1U)
43765 #define V_CHMN(x) ((x) << S_CHMN)
43766 #define F_CHMN    V_CHMN(1U)
43769 #define V_RPLC(x) ((x) << S_RPLC)
43770 #define F_RPLC    V_RPLC(1U)
43773 #define V_ATRB(x) ((x) << S_ATRB)
43774 #define F_ATRB    V_ATRB(1U)
43777 #define V_PSMX(x) ((x) << S_PSMX)
43778 #define F_PSMX    V_PSMX(1U)
43781 #define V_PGLL(x) ((x) << S_PGLL)
43782 #define F_PGLL    V_PGLL(1U)
43785 #define V_PGFL(x) ((x) << S_PGFL)
43786 #define F_PGFL    V_PGFL(1U)
43789 #define V_PKTQ(x) ((x) << S_PKTQ)
43790 #define F_PKTQ    V_PKTQ(1U)
43793 #define V_PKFL(x) ((x) << S_PKFL)
43794 #define F_PKFL    V_PKFL(1U)
43797 #define V_PPM3(x) ((x) << S_PPM3)
43798 #define F_PPM3    V_PPM3(1U)
43801 #define V_PPM2(x) ((x) << S_PPM2)
43802 #define F_PPM2    V_PPM2(1U)
43805 #define V_PPM1(x) ((x) << S_PPM1)
43806 #define F_PPM1    V_PPM1(1U)
43809 #define V_PPM0(x) ((x) << S_PPM0)
43810 #define F_PPM0    V_PPM0(1U)
43813 #define V_SPMX(x) ((x) << S_SPMX)
43814 #define F_SPMX    V_SPMX(1U)
43817 #define V_CDL3(x) ((x) << S_CDL3)
43818 #define F_CDL3    V_CDL3(1U)
43821 #define V_CDL2(x) ((x) << S_CDL2)
43822 #define F_CDL2    V_CDL2(1U)
43825 #define V_CDL1(x) ((x) << S_CDL1)
43826 #define F_CDL1    V_CDL1(1U)
43829 #define V_CDL0(x) ((x) << S_CDL0)
43830 #define F_CDL0    V_CDL0(1U)
43833 #define V_CDM3(x) ((x) << S_CDM3)
43834 #define F_CDM3    V_CDM3(1U)
43837 #define V_CDM2(x) ((x) << S_CDM2)
43838 #define F_CDM2    V_CDM2(1U)
43840 #define S_CDM1    1
43841 #define V_CDM1(x) ((x) << S_CDM1)
43842 #define F_CDM1    V_CDM1(1U)
43845 #define V_CDM0(x) ((x) << S_CDM0)
43846 #define F_CDM0    V_CDM0(1U)
43849 #define V_T6_INT_ERR_INT(x) ((x) << S_T6_INT_ERR_INT)
43850 #define F_T6_INT_ERR_INT    V_T6_INT_ERR_INT(1U)
43853 #define V_MAC_IN_FIFO_768B(x) ((x) << S_MAC_IN_FIFO_768B)
43854 #define F_MAC_IN_FIFO_768B    V_MAC_IN_FIFO_768B(1U)
43857 #define V_T7_1_INT_ERR_INT(x) ((x) << S_T7_1_INT_ERR_INT)
43858 #define F_T7_1_INT_ERR_INT    V_T7_1_INT_ERR_INT(1U)
43861 #define V_FLOP_PERR(x) ((x) << S_FLOP_PERR)
43862 #define F_FLOP_PERR    V_FLOP_PERR(1U)
43866 #define V_RPLC_MAP(x) ((x) << S_RPLC_MAP)
43867 #define G_RPLC_MAP(x) (((x) >> S_RPLC_MAP) & M_RPLC_MAP)
43870 #define V_TKN_RUNT_DROP_FIFO(x) ((x) << S_TKN_RUNT_DROP_FIFO)
43871 #define F_TKN_RUNT_DROP_FIFO    V_TKN_RUNT_DROP_FIFO(1U)
43875 #define V_T7_PPM3(x) ((x) << S_T7_PPM3)
43876 #define G_T7_PPM3(x) (((x) >> S_T7_PPM3) & M_T7_PPM3)
43880 #define V_T7_PPM2(x) ((x) << S_T7_PPM2)
43881 #define G_T7_PPM2(x) (((x) >> S_T7_PPM2) & M_T7_PPM2)
43885 #define V_T7_PPM1(x) ((x) << S_T7_PPM1)
43886 #define G_T7_PPM1(x) (((x) >> S_T7_PPM1) & M_T7_PPM1)
43890 #define V_T7_PPM0(x) ((x) << S_T7_PPM0)
43891 #define G_T7_PPM0(x) (((x) >> S_T7_PPM0) & M_T7_PPM0)
43896 #define V_T7_2_INT_ERR_INT(x) ((x) << S_T7_2_INT_ERR_INT)
43897 #define F_T7_2_INT_ERR_INT    V_T7_2_INT_ERR_INT(1U)
43905 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
43906 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
43909 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
43910 #define F_PG_TH_INT7    V_PG_TH_INT7(1U)
43913 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
43914 #define F_PG_TH_INT6    V_PG_TH_INT6(1U)
43917 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
43918 #define F_PG_TH_INT5    V_PG_TH_INT5(1U)
43921 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
43922 #define F_PG_TH_INT4    V_PG_TH_INT4(1U)
43925 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
43926 #define F_PG_TH_INT3    V_PG_TH_INT3(1U)
43929 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
43930 #define F_PG_TH_INT2    V_PG_TH_INT2(1U)
43932 #define S_PG_TH_INT1    1
43933 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
43934 #define F_PG_TH_INT1    V_PG_TH_INT1(1U)
43937 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
43938 #define F_PG_TH_INT0    V_PG_TH_INT0(1U)
43941 #define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
43942 #define F_MTU_ERR_INT3    V_MTU_ERR_INT3(1U)
43945 #define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
43946 #define F_MTU_ERR_INT2    V_MTU_ERR_INT2(1U)
43949 #define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
43950 #define F_MTU_ERR_INT1    V_MTU_ERR_INT1(1U)
43953 #define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
43954 #define F_MTU_ERR_INT0    V_MTU_ERR_INT0(1U)
43957 #define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
43958 #define F_SE_CNT_ERR_INT    V_SE_CNT_ERR_INT(1U)
43961 #define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
43962 #define F_FRM_ERR_INT    V_FRM_ERR_INT(1U)
43965 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
43966 #define F_LEN_ERR_INT    V_LEN_ERR_INT(1U)
43973 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
43974 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
43978 #define V_TH_LOW(x) ((x) << S_TH_LOW)
43979 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
43985 #define V_CRYPT2MPS_RX_INTF_FIFO(x) ((x) << S_CRYPT2MPS_RX_INTF_FIFO)
43986 #define G_CRYPT2MPS_RX_INTF_FIFO(x) (((x) >> S_CRYPT2MPS_RX_INTF_FIFO) & M_CRYPT2MPS_RX_INTF_FIFO)
43989 #define V_INIC2MPS_TX0_PERR(x) ((x) << S_INIC2MPS_TX0_PERR)
43990 #define F_INIC2MPS_TX0_PERR    V_INIC2MPS_TX0_PERR(1U)
43993 #define V_INIC2MPS_TX1_PERR(x) ((x) << S_INIC2MPS_TX1_PERR)
43994 #define F_INIC2MPS_TX1_PERR    V_INIC2MPS_TX1_PERR(1U)
43997 #define V_XGMAC2MPS_RX0_PERR(x) ((x) << S_XGMAC2MPS_RX0_PERR)
43998 #define F_XGMAC2MPS_RX0_PERR    V_XGMAC2MPS_RX0_PERR(1U)
44001 #define V_XGMAC2MPS_RX1_PERR(x) ((x) << S_XGMAC2MPS_RX1_PERR)
44002 #define F_XGMAC2MPS_RX1_PERR    V_XGMAC2MPS_RX1_PERR(1U)
44006 #define V_MPS2CRYPTO_RX_INTF_FIFO(x) ((x) << S_MPS2CRYPTO_RX_INTF_FIFO)
44007 #define G_MPS2CRYPTO_RX_INTF_FIFO(x) (((x) >> S_MPS2CRYPTO_RX_INTF_FIFO) & M_MPS2CRYPTO_RX_INTF_FIFO)
44011 #define V_RX_PRE_PROC_PERR(x) ((x) << S_RX_PRE_PROC_PERR)
44012 #define G_RX_PRE_PROC_PERR(x) (((x) >> S_RX_PRE_PROC_PERR) & M_RX_PRE_PROC_PERR)
44022 #define V_INDEX_SEL(x) ((x) << S_INDEX_SEL)
44023 #define F_INDEX_SEL    V_INDEX_SEL(1U)
44029 #define V_ETYPE(x) ((x) << S_ETYPE)
44030 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
44034 #define V_OPCODE(x) ((x) << S_OPCODE)
44035 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
44041 #define V_DA(x) ((x) << S_DA)
44042 #define G_DA(x) (((x) >> S_DA) & M_DA)
44049 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
44050 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
44054 #define V_MAC_WT(x) ((x) << S_MAC_WT)
44055 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
44070 #define V_OUTEN(x) ((x) << S_OUTEN)
44071 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
44079 #define V_MTU(x) ((x) << S_MTU)
44080 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
44089 #define V_T6_PFVF(x) ((x) << S_T6_PFVF)
44090 #define G_T6_PFVF(x) (((x) >> S_T6_PFVF) & M_T6_PFVF)
44097 #define V_FULL_FRAME_MODE(x) ((x) << S_FULL_FRAME_MODE)
44098 #define F_FULL_FRAME_MODE    V_FULL_FRAME_MODE(1U)
44103 #define V_EXTRACT_DEL_VLAN(x) ((x) << S_EXTRACT_DEL_VLAN)
44104 #define F_EXTRACT_DEL_VLAN    V_EXTRACT_DEL_VLAN(1U)
44109 #define V_RD_WRN(x) ((x) << S_RD_WRN)
44110 #define F_RD_WRN    V_RD_WRN(1U)
44114 #define V_PFVF(x) ((x) << S_PFVF)
44115 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
44123 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
44124 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
44127 #define V_OFF(x) ((x) << S_OFF)
44128 #define F_OFF    V_OFF(1U)
44131 #define V_NV_DROP(x) ((x) << S_NV_DROP)
44132 #define F_NV_DROP    V_NV_DROP(1U)
44135 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
44136 #define F_ATTR_MODE    V_ATTR_MODE(1U)
44143 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
44144 #define F_VLAN_EN    V_VLAN_EN(1U)
44148 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
44149 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
44198 #define V_T7_RPLC_MAP_ADDR(x) ((x) << S_T7_RPLC_MAP_ADDR)
44199 #define G_T7_RPLC_MAP_ADDR(x) (((x) >> S_T7_RPLC_MAP_ADDR) & M_T7_RPLC_MAP_ADDR)
44208 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
44209 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
44217 #define V_PF_EN(x) ((x) << S_PF_EN)
44218 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
44233 #define V_PKD(x) ((x) << S_PKD)
44234 #define F_PKD    V_PKD(1U)
44237 #define V_PGD(x) ((x) << S_PGD)
44238 #define F_PGD    V_PGD(1U)
44248 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
44249 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
44256 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
44257 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
44261 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
44262 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
44266 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
44267 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
44271 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
44272 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
44285 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
44286 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
44290 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
44291 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
44295 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
44296 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
44300 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
44301 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
44307 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
44308 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
44312 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
44313 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
44317 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
44318 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
44322 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
44323 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
44329 #define V_LENERR(x) ((x) << S_LENERR)
44330 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
44334 #define V_SPIERR(x) ((x) << S_SPIERR)
44335 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
44341 #define V_ST3(x) ((x) << S_ST3)
44342 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
44346 #define V_ST2(x) ((x) << S_ST2)
44347 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
44351 #define V_ST1(x) ((x) << S_ST1)
44352 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
44356 #define V_ST0(x) ((x) << S_ST0)
44357 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
44363 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
44364 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
44368 #define V_ST_TP(x) ((x) << S_ST_TP)
44369 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
44375 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
44376 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
44379 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
44380 #define F_DBG_PKD_QSEL    V_DBG_PKD_QSEL(1U)
44383 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
44384 #define F_DBG_CDS_INV    V_DBG_CDS_INV(1U)
44388 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
44389 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
44393 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
44394 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
44400 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
44401 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
44405 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
44406 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
44412 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
44413 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
44417 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
44418 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
44424 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
44425 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
44429 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
44430 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
44436 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
44437 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
44441 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
44442 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
44449 #define V_PETYPE2(x) ((x) << S_PETYPE2)
44450 #define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
44454 #define V_PETYPE1(x) ((x) << S_PETYPE1)
44455 #define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
44461 #define V_PTCPORT2(x) ((x) << S_PTCPORT2)
44462 #define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
44466 #define V_PTCPORT1(x) ((x) << S_PTCPORT1)
44467 #define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
44473 #define V_PUDPORT2(x) ((x) << S_PUDPORT2)
44474 #define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
44478 #define V_PUDPORT1(x) ((x) << S_PUDPORT1)
44479 #define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
44485 #define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
44486 #define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
44490 #define V_PUDP2EN(x) ((x) << S_PUDP2EN)
44491 #define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
44495 #define V_PUDP1EN(x) ((x) << S_PUDP1EN)
44496 #define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
44500 #define V_PTCP2EN(x) ((x) << S_PTCP2EN)
44501 #define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
44505 #define V_PTCP1EN(x) ((x) << S_PTCP1EN)
44506 #define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
44510 #define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
44511 #define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
44515 #define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
44516 #define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
44545 #define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
44546 #define F_MPS_RX_CGEN_NCSI    V_MPS_RX_CGEN_NCSI(1U)
44550 #define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
44551 #define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
44555 #define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
44556 #define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
44560 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
44561 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
44567 #define V_MAC_USED(x) ((x) << S_MAC_USED)
44568 #define G_MAC_USED(x) (((x) >> S_MAC_USED) & M_MAC_USED)
44572 #define V_MAC_ALLOC(x) ((x) << S_MAC_ALLOC)
44573 #define G_MAC_ALLOC(x) (((x) >> S_MAC_ALLOC) & M_MAC_ALLOC)
44582 #define V_LPBK_USED(x) ((x) << S_LPBK_USED)
44583 #define G_LPBK_USED(x) (((x) >> S_LPBK_USED) & M_LPBK_USED)
44587 #define V_LPBK_ALLOC(x) ((x) << S_LPBK_ALLOC)
44588 #define G_LPBK_ALLOC(x) (((x) >> S_LPBK_ALLOC) & M_LPBK_ALLOC)
44594 #define V_CONG_EN(x) ((x) << S_CONG_EN)
44595 #define F_CONG_EN    V_CONG_EN(1U)
44599 #define V_CONG_TH(x) ((x) << S_CONG_TH)
44600 #define G_CONG_TH(x) (((x) >> S_CONG_TH) & M_CONG_TH)
44612 #define V_NVGRE_EN(x) ((x) << S_NVGRE_EN)
44613 #define F_NVGRE_EN    V_NVGRE_EN(1U)
44616 #define V_GRE_EN(x) ((x) << S_GRE_EN)
44617 #define F_GRE_EN    V_GRE_EN(1U)
44621 #define V_GRE(x) ((x) << S_GRE)
44622 #define G_GRE(x) (((x) >> S_GRE) & M_GRE)
44628 #define V_VXLAN_EN(x) ((x) << S_VXLAN_EN)
44629 #define F_VXLAN_EN    V_VXLAN_EN(1U)
44633 #define V_VXLAN(x) ((x) << S_VXLAN)
44634 #define G_VXLAN(x) (((x) >> S_VXLAN) & M_VXLAN)
44640 #define V_GENEVE_EN(x) ((x) << S_GENEVE_EN)
44641 #define F_GENEVE_EN    V_GENEVE_EN(1U)
44645 #define V_GENEVE(x) ((x) << S_GENEVE)
44646 #define G_GENEVE(x) (((x) >> S_GENEVE) & M_GENEVE)
44652 #define V_T6_IVLAN_EN(x) ((x) << S_T6_IVLAN_EN)
44653 #define F_T6_IVLAN_EN    V_T6_IVLAN_EN(1U)
44659 #define V_ETYPE_EN(x) ((x) << S_ETYPE_EN)
44660 #define F_ETYPE_EN    V_ETYPE_EN(1U)
44664 #define V_T6_ETYPE(x) ((x) << S_T6_ETYPE)
44665 #define G_T6_ETYPE(x) (((x) >> S_T6_ETYPE) & M_T6_ETYPE)
44673 #define V_PROT_TYPE_EN(x) ((x) << S_PROT_TYPE_EN)
44674 #define F_PROT_TYPE_EN    V_PROT_TYPE_EN(1U)
44678 #define V_PROT_TYPE(x) ((x) << S_PROT_TYPE)
44679 #define G_PROT_TYPE(x) (((x) >> S_PROT_TYPE) & M_PROT_TYPE)
44690 #define V_SAP_VALUE(x) ((x) << S_SAP_VALUE)
44691 #define G_SAP_VALUE(x) (((x) >> S_SAP_VALUE) & M_SAP_VALUE)
44695 #define V_LENGTH_ETYPE(x) ((x) << S_LENGTH_ETYPE)
44696 #define G_LENGTH_ETYPE(x) (((x) >> S_LENGTH_ETYPE) & M_LENGTH_ETYPE)
44703 #define V_CTL_VALUE(x) ((x) << S_CTL_VALUE)
44704 #define G_CTL_VALUE(x) (((x) >> S_CTL_VALUE) & M_CTL_VALUE)
44708 #define V_ORG_VALUE(x) ((x) << S_ORG_VALUE)
44709 #define G_ORG_VALUE(x) (((x) >> S_ORG_VALUE) & M_ORG_VALUE)
44716 #define V_ETYPE_IPV4(x) ((x) << S_ETYPE_IPV4)
44717 #define G_ETYPE_IPV4(x) (((x) >> S_ETYPE_IPV4) & M_ETYPE_IPV4)
44724 #define V_ETYPE_IPV6(x) ((x) << S_ETYPE_IPV6)
44725 #define G_ETYPE_IPV6(x) (((x) >> S_ETYPE_IPV6) & M_ETYPE_IPV6)
44732 #define V_TTL_IPV4(x) ((x) << S_TTL_IPV4)
44733 #define G_TTL_IPV4(x) (((x) >> S_TTL_IPV4) & M_TTL_IPV4)
44737 #define V_TTL_IPV6(x) ((x) << S_TTL_IPV6)
44738 #define G_TTL_IPV6(x) (((x) >> S_TTL_IPV6) & M_TTL_IPV6)
44740 #define S_TTL_CHK_EN_IPV4    1
44741 #define V_TTL_CHK_EN_IPV4(x) ((x) << S_TTL_CHK_EN_IPV4)
44742 #define F_TTL_CHK_EN_IPV4    V_TTL_CHK_EN_IPV4(1U)
44745 #define V_TTL_CHK_EN_IPV6(x) ((x) << S_TTL_CHK_EN_IPV6)
44746 #define F_TTL_CHK_EN_IPV6    V_TTL_CHK_EN_IPV6(1U)
44753 #define V_VNI(x) ((x) << S_VNI)
44754 #define G_VNI(x) (((x) >> S_VNI) & M_VNI)
44760 #define V_CTL_CHK_EN(x) ((x) << S_CTL_CHK_EN)
44761 #define F_CTL_CHK_EN    V_CTL_CHK_EN(1U)
44764 #define V_ORG_CHK_EN(x) ((x) << S_ORG_CHK_EN)
44765 #define F_ORG_CHK_EN    V_ORG_CHK_EN(1U)
44768 #define V_SAP_CHK_EN(x) ((x) << S_SAP_CHK_EN)
44769 #define F_SAP_CHK_EN    V_SAP_CHK_EN(1U)
44772 #define V_VXLAN_FLAG_CHK_EN(x) ((x) << S_VXLAN_FLAG_CHK_EN)
44773 #define F_VXLAN_FLAG_CHK_EN    V_VXLAN_FLAG_CHK_EN(1U)
44777 #define V_VXLAN_FLAG_MASK(x) ((x) << S_VXLAN_FLAG_MASK)
44778 #define G_VXLAN_FLAG_MASK(x) (((x) >> S_VXLAN_FLAG_MASK) & M_VXLAN_FLAG_MASK)
44782 #define V_VXLAN_FLAG(x) ((x) << S_VXLAN_FLAG)
44783 #define G_VXLAN_FLAG(x) (((x) >> S_VXLAN_FLAG) & M_VXLAN_FLAG)
44786 #define V_GRE_VER_CHK_EN(x) ((x) << S_GRE_VER_CHK_EN)
44787 #define F_GRE_VER_CHK_EN    V_GRE_VER_CHK_EN(1U)
44791 #define V_GRE_VER(x) ((x) << S_GRE_VER)
44792 #define G_GRE_VER(x) (((x) >> S_GRE_VER) & M_GRE_VER)
44795 #define V_GENEVE_VER_CHK_EN(x) ((x) << S_GENEVE_VER_CHK_EN)
44796 #define F_GENEVE_VER_CHK_EN    V_GENEVE_VER_CHK_EN(1U)
44800 #define V_GENEVE_VER(x) ((x) << S_GENEVE_VER)
44801 #define G_GENEVE_VER(x) (((x) >> S_GENEVE_VER) & M_GENEVE_VER)
44803 #define S_DIP_EN    1
44804 #define V_DIP_EN(x) ((x) << S_DIP_EN)
44805 #define F_DIP_EN    V_DIP_EN(1U)
44811 #define V_EN_UDP_CSUM_CHK(x) ((x) << S_EN_UDP_CSUM_CHK)
44812 #define F_EN_UDP_CSUM_CHK    V_EN_UDP_CSUM_CHK(1U)
44815 #define V_EN_UDP_LEN_CHK(x) ((x) << S_EN_UDP_LEN_CHK)
44816 #define F_EN_UDP_LEN_CHK    V_EN_UDP_LEN_CHK(1U)
44819 #define V_EN_IP_CSUM_CHK(x) ((x) << S_EN_IP_CSUM_CHK)
44820 #define F_EN_IP_CSUM_CHK    V_EN_IP_CSUM_CHK(1U)
44822 #define S_EN_IP_PAYLOAD_LEN_CHK    1
44823 #define V_EN_IP_PAYLOAD_LEN_CHK(x) ((x) << S_EN_IP_PAYLOAD_LEN_CHK)
44824 #define F_EN_IP_PAYLOAD_LEN_CHK    V_EN_IP_PAYLOAD_LEN_CHK(1U)
44827 #define V_T6_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_T6_IPV6_UDP_CSUM_COMPAT)
44828 #define F_T6_IPV6_UDP_CSUM_COMPAT    V_T6_IPV6_UDP_CSUM_COMPAT(1U)
44837 #define V_T6_LEN(x) ((x) << S_T6_LEN)
44838 #define G_T6_LEN(x) (((x) >> S_T6_LEN) & M_T6_LEN)
44843 #define V_IP_EXT_HDR_EN(x) ((x) << S_IP_EXT_HDR_EN)
44844 #define F_IP_EXT_HDR_EN    V_IP_EXT_HDR_EN(1U)
44852 #define V_MPS_TNL_HDR_LEN_MODE(x) ((x) << S_MPS_TNL_HDR_LEN_MODE)
44853 #define F_MPS_TNL_HDR_LEN_MODE    V_MPS_TNL_HDR_LEN_MODE(1U)
44857 #define V_MPS_MAX_TNL_HDR_LEN(x) ((x) << S_MPS_MAX_TNL_HDR_LEN)
44858 #define G_MPS_MAX_TNL_HDR_LEN(x) (((x) >> S_MPS_MAX_TNL_HDR_LEN) & M_MPS_MAX_TNL_HDR_LEN)
44914 #define V_EN_CH3(x) ((x) << S_EN_CH3)
44915 #define F_EN_CH3    V_EN_CH3(1U)
44918 #define V_EN_CH2(x) ((x) << S_EN_CH2)
44919 #define F_EN_CH2    V_EN_CH2(1U)
44921 #define S_EN_CH1    1
44922 #define V_EN_CH1(x) ((x) << S_EN_CH1)
44923 #define F_EN_CH1    V_EN_CH1(1U)
44926 #define V_EN_CH0(x) ((x) << S_EN_CH0)
44927 #define F_EN_CH0    V_EN_CH0(1U)
44940 #define V_CLS(x) ((x) << S_CLS)
44941 #define G_CLS(x) (((x) >> S_CLS) & M_CLS)
44945 #define V_RX_PRE_PROC(x) ((x) << S_RX_PRE_PROC)
44946 #define G_RX_PRE_PROC(x) (((x) >> S_RX_PRE_PROC) & M_RX_PRE_PROC)
44950 #define V_PPROC3(x) ((x) << S_PPROC3)
44951 #define G_PPROC3(x) (((x) >> S_PPROC3) & M_PPROC3)
44955 #define V_PPROC2(x) ((x) << S_PPROC2)
44956 #define G_PPROC2(x) (((x) >> S_PPROC2) & M_PPROC2)
44960 #define V_PPROC1(x) ((x) << S_PPROC1)
44961 #define G_PPROC1(x) (((x) >> S_PPROC1) & M_PPROC1)
44965 #define V_PPROC0(x) ((x) << S_PPROC0)
44966 #define G_PPROC0(x) (((x) >> S_PPROC0) & M_PPROC0)
44974 #define V_MPS2CRYP_RX_FIFO(x) ((x) << S_MPS2CRYP_RX_FIFO)
44975 #define G_MPS2CRYP_RX_FIFO(x) (((x) >> S_MPS2CRYP_RX_FIFO) & M_MPS2CRYP_RX_FIFO)
44979 #define V_RX_OUT(x) ((x) << S_RX_OUT)
44980 #define G_RX_OUT(x) (((x) >> S_RX_OUT) & M_RX_OUT)
44984 #define V_MEM_WRAP(x) ((x) << S_MEM_WRAP)
44985 #define G_MEM_WRAP(x) (((x) >> S_MEM_WRAP) & M_MEM_WRAP)
44993 #define V_MPS_RX_MEM_WRAP(x) ((x) << S_MPS_RX_MEM_WRAP)
44994 #define G_MPS_RX_MEM_WRAP(x) (((x) >> S_MPS_RX_MEM_WRAP) & M_MPS_RX_MEM_WRAP)
45028 #define V_DIP_VLD(x) ((x) << S_DIP_VLD)
45029 #define F_DIP_VLD    V_DIP_VLD(1U)
45032 #define V_DIP_TYPE(x) ((x) << S_DIP_TYPE)
45033 #define F_DIP_TYPE    V_DIP_TYPE(1U)
45036 #define V_DIP_WRN(x) ((x) << S_DIP_WRN)
45037 #define F_DIP_WRN    V_DIP_WRN(1U)
45041 #define V_DIP_SEG(x) ((x) << S_DIP_SEG)
45042 #define G_DIP_SEG(x) (((x) >> S_DIP_SEG) & M_DIP_SEG)
45046 #define V_DIP_TBL_RSVD1(x) ((x) << S_DIP_TBL_RSVD1)
45047 #define G_DIP_TBL_RSVD1(x) (((x) >> S_DIP_TBL_RSVD1) & M_DIP_TBL_RSVD1)
45051 #define V_DIP_TBL_ADDR(x) ((x) << S_DIP_TBL_ADDR)
45052 #define G_DIP_TBL_ADDR(x) (((x) >> S_DIP_TBL_ADDR) & M_DIP_TBL_ADDR)
45070 #define V_DMAC(x) ((x) << S_DMAC)
45071 #define G_DMAC(x) (((x) >> S_DMAC) & M_DMAC)
45107 #define V_INT_TYPE_EN(x) ((x) << S_INT_TYPE_EN)
45108 #define F_INT_TYPE_EN    V_INT_TYPE_EN(1U)
45112 #define V_INT_TYPE(x) ((x) << S_INT_TYPE)
45113 #define G_INT_TYPE(x) (((x) >> S_INT_TYPE) & M_INT_TYPE)
45119 #define V_EXTRACT_DEL_ENCAP(x) ((x) << S_EXTRACT_DEL_ENCAP)
45120 #define F_EXTRACT_DEL_ENCAP    V_EXTRACT_DEL_ENCAP(1U)
45125 #define V_TIMEOUT_FLT_CLR_EN(x) ((x) << S_TIMEOUT_FLT_CLR_EN)
45126 #define F_TIMEOUT_FLT_CLR_EN    V_TIMEOUT_FLT_CLR_EN(1U)
45130 #define V_FLTR_TIMOUT_VAL(x) ((x) << S_FLTR_TIMOUT_VAL)
45131 #define G_FLTR_TIMOUT_VAL(x) (((x) >> S_FLTR_TIMOUT_VAL) & M_FLTR_TIMOUT_VAL)
45169 #define V_DROP_TH(x) ((x) << S_DROP_TH)
45170 #define G_DROP_TH(x) (((x) >> S_DROP_TH) & M_DROP_TH)
45247 #define V_FIFO_CONFIG2(x) ((x) << S_FIFO_CONFIG2)
45248 #define G_FIFO_CONFIG2(x) (((x) >> S_FIFO_CONFIG2) & M_FIFO_CONFIG2)
45252 #define V_FIFO_CONFIG1(x) ((x) << S_FIFO_CONFIG1)
45253 #define G_FIFO_CONFIG1(x) (((x) >> S_FIFO_CONFIG1) & M_FIFO_CONFIG1)
45259 #define V_FIFO_CONFIG3(x) ((x) << S_FIFO_CONFIG3)
45260 #define G_FIFO_CONFIG3(x) (((x) >> S_FIFO_CONFIG3) & M_FIFO_CONFIG3)
45271 #define V_BG0_PAUSE_EN(x) ((x) << S_BG0_PAUSE_EN)
45272 #define F_BG0_PAUSE_EN    V_BG0_PAUSE_EN(1U)
45275 #define V_BG1_PAUSE_EN(x) ((x) << S_BG1_PAUSE_EN)
45276 #define F_BG1_PAUSE_EN    V_BG1_PAUSE_EN(1U)
45278 #define S_BG2_PAUSE_EN    1
45279 #define V_BG2_PAUSE_EN(x) ((x) << S_BG2_PAUSE_EN)
45280 #define F_BG2_PAUSE_EN    V_BG2_PAUSE_EN(1U)
45283 #define V_BG3_PAUSE_EN(x) ((x) << S_BG3_PAUSE_EN)
45284 #define F_BG3_PAUSE_EN    V_BG3_PAUSE_EN(1U)
45293 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
45294 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
45297 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
45298 #define F_CIM_TRUNCATE_ENABLE    V_CIM_TRUNCATE_ENABLE(1U)
45301 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
45302 #define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
45305 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
45306 #define F_CPU_NO_ENABLE    V_CPU_NO_ENABLE(1U)
45309 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
45310 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
45312 #define S_SGE_ENABLE    1
45313 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
45314 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
45317 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
45318 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
45321 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
45322 #define F_CIM_SPLIT_ENABLE    V_CIM_SPLIT_ENABLE(1U)
45329 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
45330 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
45339 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
45340 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
45344 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
45345 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
45351 #define V_ZERO_CMD_CH3(x) ((x) << S_ZERO_CMD_CH3)
45352 #define G_ZERO_CMD_CH3(x) (((x) >> S_ZERO_CMD_CH3) & M_ZERO_CMD_CH3)
45356 #define V_ZERO_CMD_CH2(x) ((x) << S_ZERO_CMD_CH2)
45357 #define G_ZERO_CMD_CH2(x) (((x) >> S_ZERO_CMD_CH2) & M_ZERO_CMD_CH2)
45362 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
45363 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
45366 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
45367 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
45370 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
45371 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
45374 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
45375 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
45377 #define S_CIM_FRAMING_ERROR    1
45378 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
45379 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
45382 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
45383 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
45386 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
45387 #define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)
45390 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
45391 #define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
45396 #define V_PERR_CPL_128TO128_3(x) ((x) << S_PERR_CPL_128TO128_3)
45397 #define F_PERR_CPL_128TO128_3    V_PERR_CPL_128TO128_3(1U)
45400 #define V_PERR_CPL_128TO128_2(x) ((x) << S_PERR_CPL_128TO128_2)
45401 #define F_PERR_CPL_128TO128_2    V_PERR_CPL_128TO128_2(1U)
45409 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
45410 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
45413 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
45414 #define F_CIM_SPLIT_OPCODE_PROGRAM    V_CIM_SPLIT_OPCODE_PROGRAM(1U)
45420 #define V_CPL_MAP_TBL_SEL(x) ((x) << S_CPL_MAP_TBL_SEL)
45421 #define G_CPL_MAP_TBL_SEL(x) (((x) >> S_CPL_MAP_TBL_SEL) & M_CPL_MAP_TBL_SEL)
45427 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
45428 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
45439 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
45440 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
45444 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
45445 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
45449 #define V_T7_MACROCNTCFG(x) ((x) << S_T7_MACROCNTCFG)
45450 #define G_T7_MACROCNTCFG(x) (((x) >> S_T7_MACROCNTCFG) & M_T7_MACROCNTCFG)
45454 #define V_T7_MICROCNTCFG(x) ((x) << S_T7_MICROCNTCFG)
45455 #define G_T7_MICROCNTCFG(x) (((x) >> S_T7_MICROCNTCFG) & M_T7_MICROCNTCFG)
45461 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
45462 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
45467 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
45468 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
45471 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
45472 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
45476 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
45477 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
45481 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
45482 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
45484 #define S_MSTRESET    1
45485 #define V_MSTRESET(x) ((x) << S_MSTRESET)
45486 #define F_MSTRESET    V_MSTRESET(1U)
45489 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
45490 #define F_MSTCTLEN    V_MSTCTLEN(1U)
45496 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
45497 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
45501 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
45502 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
45505 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
45506 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
45514 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
45515 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
45520 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
45521 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
45524 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
45525 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
45528 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
45529 #define F_SLVCRCOUTBITINV    V_SLVCRCOUTBITINV(1U)
45532 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
45533 #define F_SLVCRCOUTBITREV    V_SLVCRCOUTBITREV(1U)
45536 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
45537 #define F_SLVCRCINBITREV    V_SLVCRCINBITREV(1U)
45541 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
45542 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
45546 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
45547 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
45550 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
45551 #define F_SLVALRTSET    V_SLVALRTSET(1U)
45553 #define S_SLVRESET    1
45554 #define V_SLVRESET(x) ((x) << S_SLVRESET)
45555 #define F_SLVRESET    V_SLVRESET(1U)
45558 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
45559 #define F_SLVCTLEN    V_SLVCTLEN(1U)
45565 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
45566 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
45570 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
45571 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
45574 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
45575 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
45578 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
45579 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
45585 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
45586 #define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)
45589 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
45590 #define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)
45593 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
45594 #define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)
45597 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
45598 #define F_SLVUNEXPBUSSTOPEN    V_SLVUNEXPBUSSTOPEN(1U)
45601 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
45602 #define F_SLVUNEXPBUSSTARTEN    V_SLVUNEXPBUSSTARTEN(1U)
45605 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
45606 #define F_SLVCOMMANDCODEINVEN    V_SLVCOMMANDCODEINVEN(1U)
45609 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
45610 #define F_SLVBYTECNTERREN    V_SLVBYTECNTERREN(1U)
45613 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
45614 #define F_SLVUNEXPACKMSTEN    V_SLVUNEXPACKMSTEN(1U)
45617 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
45618 #define F_SLVUNEXPNACKMSTEN    V_SLVUNEXPNACKMSTEN(1U)
45621 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
45622 #define F_SLVNOBUSSTOPEN    V_SLVNOBUSSTOPEN(1U)
45625 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
45626 #define F_SLVNOREPSTARTEN    V_SLVNOREPSTARTEN(1U)
45629 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
45630 #define F_SLVRXADDRINTEN    V_SLVRXADDRINTEN(1U)
45633 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
45634 #define F_SLVRXPECERRINTEN    V_SLVRXPECERRINTEN(1U)
45637 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
45638 #define F_SLVPREPTOARPINTEN    V_SLVPREPTOARPINTEN(1U)
45641 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
45642 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
45645 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
45646 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
45649 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
45650 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
45653 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
45654 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
45657 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
45658 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
45661 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
45662 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
45664 #define S_MSTLOSTARBINTEN    1
45665 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
45666 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
45669 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
45670 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
45675 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
45676 #define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)
45679 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
45680 #define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)
45683 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
45684 #define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)
45687 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
45688 #define F_SLVUNEXPBUSSTOPINT    V_SLVUNEXPBUSSTOPINT(1U)
45691 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
45692 #define F_SLVUNEXPBUSSTARTINT    V_SLVUNEXPBUSSTARTINT(1U)
45695 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
45696 #define F_SLVCOMMANDCODEINVINT    V_SLVCOMMANDCODEINVINT(1U)
45699 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
45700 #define F_SLVBYTECNTERRINT    V_SLVBYTECNTERRINT(1U)
45703 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
45704 #define F_SLVUNEXPACKMSTINT    V_SLVUNEXPACKMSTINT(1U)
45707 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
45708 #define F_SLVUNEXPNACKMSTINT    V_SLVUNEXPNACKMSTINT(1U)
45711 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
45712 #define F_SLVNOBUSSTOPINT    V_SLVNOBUSSTOPINT(1U)
45715 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
45716 #define F_SLVNOREPSTARTINT    V_SLVNOREPSTARTINT(1U)
45719 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
45720 #define F_SLVRXADDRINT    V_SLVRXADDRINT(1U)
45723 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
45724 #define F_SLVRXPECERRINT    V_SLVRXPECERRINT(1U)
45727 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
45728 #define F_SLVPREPTOARPINT    V_SLVPREPTOARPINT(1U)
45731 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
45732 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
45735 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
45736 #define F_SLVERRINT    V_SLVERRINT(1U)
45739 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
45740 #define F_SLVDONEINT    V_SLVDONEINT(1U)
45743 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
45744 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
45747 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
45748 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
45751 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
45752 #define F_MSTNACKINT    V_MSTNACKINT(1U)
45754 #define S_MSTLOSTARBINT    1
45755 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
45756 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
45759 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
45760 #define F_MSTDONEINT    V_MSTDONEINT(1U)
45766 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
45767 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
45771 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
45772 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
45777 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
45778 #define F_MSTTXFIFOPERREN    V_MSTTXFIFOPERREN(1U)
45780 #define S_MSTRXFIFOPERREN    1
45781 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
45782 #define F_MSTRXFIFOPERREN    V_MSTRXFIFOPERREN(1U)
45785 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
45786 #define F_SLVFIFOPERREN    V_SLVFIFOPERREN(1U)
45789 #define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
45790 #define F_MSTTXFIFO    V_MSTTXFIFO(1U)
45793 #define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
45794 #define F_MSTRXFIFO    V_MSTRXFIFO(1U)
45797 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
45798 #define F_SLVFIFO    V_SLVFIFO(1U)
45803 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
45804 #define F_MSTTXINJDATAERR    V_MSTTXINJDATAERR(1U)
45807 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
45808 #define F_MSTRXINJDATAERR    V_MSTRXINJDATAERR(1U)
45810 #define S_SLVINJDATAERR    1
45811 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
45812 #define F_SLVINJDATAERR    V_SLVINJDATAERR(1U)
45815 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
45816 #define F_FIFOINJDATAERREN    V_FIFOINJDATAERREN(1U)
45822 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
45823 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
45825 #define S_ARPADDRRES    1
45826 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
45827 #define F_ARPADDRRES    V_ARPADDRRES(1U)
45830 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
45831 #define F_ARPADDRVAL    V_ARPADDRVAL(1U)
45838 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
45839 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
45843 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
45844 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
45850 #define V_DEVICEID(x) ((x) << S_DEVICEID)
45851 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
45855 #define V_INTERFACE(x) ((x) << S_INTERFACE)
45856 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
45862 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
45863 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
45867 #define V_VERSIONID(x) ((x) << S_VERSIONID)
45868 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
45872 #define V_VENDORID(x) ((x) << S_VENDORID)
45873 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
45878 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
45879 #define F_AUXADDR0VAL    V_AUXADDR0VAL(1U)
45883 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
45884 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
45889 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
45890 #define F_AUXADDR1VAL    V_AUXADDR1VAL(1U)
45894 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
45895 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
45900 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
45901 #define F_AUXADDR2VAL    V_AUXADDR2VAL(1U)
45905 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
45906 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
45911 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
45912 #define F_AUXADDR3VAL    V_AUXADDR3VAL(1U)
45916 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
45917 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
45923 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
45924 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
45930 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
45931 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
45937 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
45938 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
45944 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
45945 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
45951 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
45952 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
45958 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
45959 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
45965 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
45966 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
45972 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
45973 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
45979 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
45980 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
45984 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
45985 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
45990 #define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
45991 #define F_MSTBUSBUSY    V_MSTBUSBUSY(1U)
45993 #define S_SLVBUSBUSY    1
45994 #define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
45995 #define F_SLVBUSBUSY    V_SLVBUSBUSY(1U)
45998 #define V_BUSBUSY(x) ((x) << S_BUSBUSY)
45999 #define F_BUSBUSY    V_BUSBUSY(1U)
46008 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
46009 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
46013 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
46014 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
46020 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
46021 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
46026 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
46027 #define F_I2C_ACK    V_I2C_ACK(1U)
46029 #define S_I2C_CONT    1
46030 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
46031 #define F_I2C_CONT    V_I2C_CONT(1U)
46034 #define V_OP(x) ((x) << S_OP)
46035 #define F_OP    V_OP(1U)
46043 #define V_T4_ST(x) ((x) << S_T4_ST)
46044 #define F_T4_ST    V_T4_ST(1U)
46048 #define V_CLKDIV(x) ((x) << S_CLKDIV)
46049 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
46053 #define V_ST(x) ((x) << S_ST)
46054 #define G_ST(x) (((x) >> S_ST) & M_ST)
46057 #define V_PREEN(x) ((x) << S_PREEN)
46058 #define F_PREEN    V_PREEN(1U)
46060 #define S_MDIINV    1
46061 #define V_MDIINV(x) ((x) << S_MDIINV)
46062 #define F_MDIINV    V_MDIINV(1U)
46065 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
46066 #define F_MDIO_1P2V_SEL    V_MDIO_1P2V_SEL(1U)
46072 #define V_PHYADDR(x) ((x) << S_PHYADDR)
46073 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
46077 #define V_REGADDR(x) ((x) << S_REGADDR)
46078 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
46084 #define V_MDIDATA(x) ((x) << S_MDIDATA)
46085 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
46090 #define V_INC(x) ((x) << S_INC)
46091 #define F_INC    V_INC(1U)
46095 #define V_MDIOP(x) ((x) << S_MDIOP)
46096 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
46105 #define V_STOPBITS(x) ((x) << S_STOPBITS)
46106 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
46110 #define V_PARITY(x) ((x) << S_PARITY)
46111 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
46115 #define V_DATABITS(x) ((x) << S_DATABITS)
46116 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
46120 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
46121 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
46125 #define V_T7_STOPBITS(x) ((x) << S_T7_STOPBITS)
46126 #define G_T7_STOPBITS(x) (((x) >> S_T7_STOPBITS) & M_T7_STOPBITS)
46130 #define V_T7_PARITY(x) ((x) << S_T7_PARITY)
46131 #define G_T7_PARITY(x) (((x) >> S_T7_PARITY) & M_T7_PARITY)
46135 #define V_T7_DATABITS(x) ((x) << S_T7_DATABITS)
46136 #define G_T7_DATABITS(x) (((x) >> S_T7_DATABITS) & M_T7_DATABITS)
46140 #define V_T7_UART_CLKDIV(x) ((x) << S_T7_UART_CLKDIV)
46141 #define G_T7_UART_CLKDIV(x) (((x) >> S_T7_UART_CLKDIV) & M_T7_UART_CLKDIV)
46149 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
46150 #define F_TPPARTCGEN    V_TPPARTCGEN(1U)
46153 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
46154 #define F_PDPPARTCGEN    V_PDPPARTCGEN(1U)
46157 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
46158 #define F_PCIEPARTCGEN    V_PCIEPARTCGEN(1U)
46161 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
46162 #define F_EDC1PARTCGEN    V_EDC1PARTCGEN(1U)
46165 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
46166 #define F_MCPARTCGEN    V_MCPARTCGEN(1U)
46169 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
46170 #define F_EDC0PARTCGEN    V_EDC0PARTCGEN(1U)
46173 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
46174 #define F_LEPARTCGEN    V_LEPARTCGEN(1U)
46178 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
46179 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
46182 #define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
46183 #define F_SGE_PART_CGEN    V_SGE_PART_CGEN(1U)
46186 #define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
46187 #define F_PDP_PART_CGEN    V_PDP_PART_CGEN(1U)
46190 #define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
46191 #define F_TP_PART_CGEN    V_TP_PART_CGEN(1U)
46194 #define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
46195 #define F_EDC0_PART_CGEN    V_EDC0_PART_CGEN(1U)
46198 #define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
46199 #define F_EDC1_PART_CGEN    V_EDC1_PART_CGEN(1U)
46202 #define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
46203 #define F_LE_PART_CGEN    V_LE_PART_CGEN(1U)
46206 #define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
46207 #define F_MA_PART_CGEN    V_MA_PART_CGEN(1U)
46210 #define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
46211 #define F_MC0_PART_CGEN    V_MC0_PART_CGEN(1U)
46214 #define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
46215 #define F_MC1_PART_CGEN    V_MC1_PART_CGEN(1U)
46218 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
46219 #define F_PCIE_PART_CGEN    V_PCIE_PART_CGEN(1U)
46222 #define V_PL_DIS_PRTY_CHK(x) ((x) << S_PL_DIS_PRTY_CHK)
46223 #define F_PL_DIS_PRTY_CHK    V_PL_DIS_PRTY_CHK(1U)
46226 #define V_ARM_PART_CGEN(x) ((x) << S_ARM_PART_CGEN)
46227 #define F_ARM_PART_CGEN    V_ARM_PART_CGEN(1U)
46230 #define V_CRYPTO_PART_CGEN(x) ((x) << S_CRYPTO_PART_CGEN)
46231 #define F_CRYPTO_PART_CGEN    V_CRYPTO_PART_CGEN(1U)
46234 #define V_NVME_PART_CGEN(x) ((x) << S_NVME_PART_CGEN)
46235 #define F_NVME_PART_CGEN    V_NVME_PART_CGEN(1U)
46238 #define V_XP10_PART_CGEN(x) ((x) << S_XP10_PART_CGEN)
46239 #define F_XP10_PART_CGEN    V_XP10_PART_CGEN(1U)
46242 #define V_GPEX_PART_CGEN(x) ((x) << S_GPEX_PART_CGEN)
46243 #define F_GPEX_PART_CGEN    V_GPEX_PART_CGEN(1U)
46248 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
46249 #define F_HWWAKEUPEN    V_HWWAKEUPEN(1U)
46252 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
46253 #define F_PORT3SLEEPMODE    V_PORT3SLEEPMODE(1U)
46256 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
46257 #define F_PORT2SLEEPMODE    V_PORT2SLEEPMODE(1U)
46260 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
46261 #define F_PORT1SLEEPMODE    V_PORT1SLEEPMODE(1U)
46263 #define S_PORT0SLEEPMODE    1
46264 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
46265 #define F_PORT0SLEEPMODE    V_PORT0SLEEPMODE(1U)
46268 #define V_WAKEUP(x) ((x) << S_WAKEUP)
46269 #define F_WAKEUP    V_WAKEUP(1U)
46272 #define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
46273 #define F_GLOBALDEEPSLEEPEN    V_GLOBALDEEPSLEEPEN(1U)
46282 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
46283 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
46287 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
46288 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
46291 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
46292 #define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)
46296 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
46297 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
46300 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
46301 #define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)
46304 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
46305 #define F_STAG_RQE    V_STAG_RQE(1U)
46308 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
46309 #define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)
46312 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
46313 #define F_CRC1_EN    V_CRC1_EN(1U)
46316 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
46317 #define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)
46320 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
46321 #define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)
46324 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
46325 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
46328 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
46329 #define F_PAGEPODME    V_PAGEPODME(1U)
46331 #define S_ISCSITAGTCB    1
46332 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
46333 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
46336 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
46337 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
46340 #define V_ISCSI_PAGE_SIZE_CHK_ENB(x) ((x) << S_ISCSI_PAGE_SIZE_CHK_ENB)
46341 #define F_ISCSI_PAGE_SIZE_CHK_ENB    V_ISCSI_PAGE_SIZE_CHK_ENB(1U)
46344 #define V_RDMA_0B_WR_OPCODE_HI(x) ((x) << S_RDMA_0B_WR_OPCODE_HI)
46345 #define F_RDMA_0B_WR_OPCODE_HI    V_RDMA_0B_WR_OPCODE_HI(1U)
46348 #define V_RDMA_IMMEDIATE_CQE(x) ((x) << S_RDMA_IMMEDIATE_CQE)
46349 #define F_RDMA_IMMEDIATE_CQE    V_RDMA_IMMEDIATE_CQE(1U)
46352 #define V_RDMA_ATOMIC_WR_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_WR_RSP_CQE)
46353 #define F_RDMA_ATOMIC_WR_RSP_CQE    V_RDMA_ATOMIC_WR_RSP_CQE(1U)
46356 #define V_RDMA_VERIFY_RSP_FLUSH(x) ((x) << S_RDMA_VERIFY_RSP_FLUSH)
46357 #define F_RDMA_VERIFY_RSP_FLUSH    V_RDMA_VERIFY_RSP_FLUSH(1U)
46360 #define V_RDMA_VERIFY_RSP_CQE(x) ((x) << S_RDMA_VERIFY_RSP_CQE)
46361 #define F_RDMA_VERIFY_RSP_CQE    V_RDMA_VERIFY_RSP_CQE(1U)
46364 #define V_RDMA_FLUSH_RSP_CQE(x) ((x) << S_RDMA_FLUSH_RSP_CQE)
46365 #define F_RDMA_FLUSH_RSP_CQE    V_RDMA_FLUSH_RSP_CQE(1U)
46368 #define V_RDMA_ATOMIC_RSP_CQE(x) ((x) << S_RDMA_ATOMIC_RSP_CQE)
46369 #define F_RDMA_ATOMIC_RSP_CQE    V_RDMA_ATOMIC_RSP_CQE(1U)
46372 #define V_T7_TPT_EXTENSION_MODE(x) ((x) << S_T7_TPT_EXTENSION_MODE)
46373 #define F_T7_TPT_EXTENSION_MODE    V_T7_TPT_EXTENSION_MODE(1U)
46376 #define V_NVME_TCP_DDP_VAL_EN(x) ((x) << S_NVME_TCP_DDP_VAL_EN)
46377 #define F_NVME_TCP_DDP_VAL_EN    V_NVME_TCP_DDP_VAL_EN(1U)
46380 #define V_NVME_TCP_REMOVE_HDR_CRC(x) ((x) << S_NVME_TCP_REMOVE_HDR_CRC)
46381 #define F_NVME_TCP_REMOVE_HDR_CRC    V_NVME_TCP_REMOVE_HDR_CRC(1U)
46384 #define V_NVME_TCP_LAST_PDU_CHECK_ENB(x) ((x) << S_NVME_TCP_LAST_PDU_CHECK_ENB)
46385 #define F_NVME_TCP_LAST_PDU_CHECK_ENB    V_NVME_TCP_LAST_PDU_CHECK_ENB(1U)
46389 #define V_NVME_TCP_OFFSET_SUBMODE(x) ((x) << S_NVME_TCP_OFFSET_SUBMODE)
46390 #define G_NVME_TCP_OFFSET_SUBMODE(x) (((x) >> S_NVME_TCP_OFFSET_SUBMODE) & M_NVME_TCP_OFFSET_SUBMODE)
46393 #define V_NVME_TCP_OFFSET_MODE(x) ((x) << S_NVME_TCP_OFFSET_MODE)
46394 #define F_NVME_TCP_OFFSET_MODE    V_NVME_TCP_OFFSET_MODE(1U)
46397 #define V_QPID_CHECK_DISABLE_FOR_SEND(x) ((x) << S_QPID_CHECK_DISABLE_FOR_SEND)
46398 #define F_QPID_CHECK_DISABLE_FOR_SEND    V_QPID_CHECK_DISABLE_FOR_SEND(1U)
46402 #define V_RDMA_0B_WR_OPCODE_LO(x) ((x) << S_RDMA_0B_WR_OPCODE_LO)
46403 #define G_RDMA_0B_WR_OPCODE_LO(x) (((x) >> S_RDMA_0B_WR_OPCODE_LO) & M_RDMA_0B_WR_OPCODE_LO)
46408 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
46409 #define F_ENABLE_CTX_1    V_ENABLE_CTX_1(1U)
46412 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
46413 #define F_ENABLE_CTX_0    V_ENABLE_CTX_0(1U)
46416 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
46417 #define F_ENABLE_FF    V_ENABLE_FF(1U)
46420 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
46421 #define F_ENABLE_APF_1    V_ENABLE_APF_1(1U)
46424 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
46425 #define F_ENABLE_APF_0    V_ENABLE_APF_0(1U)
46428 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
46429 #define F_ENABLE_AF_1    V_ENABLE_AF_1(1U)
46432 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
46433 #define F_ENABLE_AF_0    V_ENABLE_AF_0(1U)
46436 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
46437 #define F_ENABLE_DDPDF_1    V_ENABLE_DDPDF_1(1U)
46440 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
46441 #define F_ENABLE_DDPMF_1    V_ENABLE_DDPMF_1(1U)
46444 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
46445 #define F_ENABLE_MEMRF_1    V_ENABLE_MEMRF_1(1U)
46448 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
46449 #define F_ENABLE_PRSDF_1    V_ENABLE_PRSDF_1(1U)
46452 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
46453 #define F_ENABLE_DDPDF_0    V_ENABLE_DDPDF_0(1U)
46456 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
46457 #define F_ENABLE_DDPMF_0    V_ENABLE_DDPMF_0(1U)
46460 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
46461 #define F_ENABLE_MEMRF_0    V_ENABLE_MEMRF_0(1U)
46464 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
46465 #define F_ENABLE_PRSDF_0    V_ENABLE_PRSDF_0(1U)
46468 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
46469 #define F_ENABLE_PCMDF_1    V_ENABLE_PCMDF_1(1U)
46472 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
46473 #define F_ENABLE_TPTCF_1    V_ENABLE_TPTCF_1(1U)
46476 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
46477 #define F_ENABLE_DDPCF_1    V_ENABLE_DDPCF_1(1U)
46480 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
46481 #define F_ENABLE_MPARF_1    V_ENABLE_MPARF_1(1U)
46484 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
46485 #define F_ENABLE_MPARC_1    V_ENABLE_MPARC_1(1U)
46488 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
46489 #define F_ENABLE_PCMDF_0    V_ENABLE_PCMDF_0(1U)
46492 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
46493 #define F_ENABLE_TPTCF_0    V_ENABLE_TPTCF_0(1U)
46496 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
46497 #define F_ENABLE_DDPCF_0    V_ENABLE_DDPCF_0(1U)
46499 #define S_ENABLE_MPARF_0    1
46500 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
46501 #define F_ENABLE_MPARF_0    V_ENABLE_MPARF_0(1U)
46504 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
46505 #define F_ENABLE_MPARC_0    V_ENABLE_MPARC_0(1U)
46508 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
46509 #define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)
46512 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
46513 #define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
46516 #define V_CERR_PCMD_FIFO_3(x) ((x) << S_CERR_PCMD_FIFO_3)
46517 #define F_CERR_PCMD_FIFO_3    V_CERR_PCMD_FIFO_3(1U)
46520 #define V_CERR_PCMD_FIFO_2(x) ((x) << S_CERR_PCMD_FIFO_2)
46521 #define F_CERR_PCMD_FIFO_2    V_CERR_PCMD_FIFO_2(1U)
46524 #define V_CERR_PCMD_FIFO_1(x) ((x) << S_CERR_PCMD_FIFO_1)
46525 #define F_CERR_PCMD_FIFO_1    V_CERR_PCMD_FIFO_1(1U)
46528 #define V_CERR_PCMD_FIFO_0(x) ((x) << S_CERR_PCMD_FIFO_0)
46529 #define F_CERR_PCMD_FIFO_0    V_CERR_PCMD_FIFO_0(1U)
46532 #define V_CERR_DATA_FIFO_3(x) ((x) << S_CERR_DATA_FIFO_3)
46533 #define F_CERR_DATA_FIFO_3    V_CERR_DATA_FIFO_3(1U)
46536 #define V_CERR_DATA_FIFO_2(x) ((x) << S_CERR_DATA_FIFO_2)
46537 #define F_CERR_DATA_FIFO_2    V_CERR_DATA_FIFO_2(1U)
46540 #define V_CERR_DATA_FIFO_1(x) ((x) << S_CERR_DATA_FIFO_1)
46541 #define F_CERR_DATA_FIFO_1    V_CERR_DATA_FIFO_1(1U)
46544 #define V_CERR_DATA_FIFO_0(x) ((x) << S_CERR_DATA_FIFO_0)
46545 #define F_CERR_DATA_FIFO_0    V_CERR_DATA_FIFO_0(1U)
46548 #define V_SE_CNT_MISMATCH_3(x) ((x) << S_SE_CNT_MISMATCH_3)
46549 #define F_SE_CNT_MISMATCH_3    V_SE_CNT_MISMATCH_3(1U)
46552 #define V_SE_CNT_MISMATCH_2(x) ((x) << S_SE_CNT_MISMATCH_2)
46553 #define F_SE_CNT_MISMATCH_2    V_SE_CNT_MISMATCH_2(1U)
46556 #define V_T7_SE_CNT_MISMATCH_1(x) ((x) << S_T7_SE_CNT_MISMATCH_1)
46557 #define F_T7_SE_CNT_MISMATCH_1    V_T7_SE_CNT_MISMATCH_1(1U)
46560 #define V_T7_SE_CNT_MISMATCH_0(x) ((x) << S_T7_SE_CNT_MISMATCH_0)
46561 #define F_T7_SE_CNT_MISMATCH_0    V_T7_SE_CNT_MISMATCH_0(1U)
46564 #define V_ENABLE_CTX_3(x) ((x) << S_ENABLE_CTX_3)
46565 #define F_ENABLE_CTX_3    V_ENABLE_CTX_3(1U)
46568 #define V_ENABLE_CTX_2(x) ((x) << S_ENABLE_CTX_2)
46569 #define F_ENABLE_CTX_2    V_ENABLE_CTX_2(1U)
46572 #define V_T7_ENABLE_CTX_1(x) ((x) << S_T7_ENABLE_CTX_1)
46573 #define F_T7_ENABLE_CTX_1    V_T7_ENABLE_CTX_1(1U)
46576 #define V_T7_ENABLE_CTX_0(x) ((x) << S_T7_ENABLE_CTX_0)
46577 #define F_T7_ENABLE_CTX_0    V_T7_ENABLE_CTX_0(1U)
46580 #define V_ENABLE_ALN_SDC_ERR_3(x) ((x) << S_ENABLE_ALN_SDC_ERR_3)
46581 #define F_ENABLE_ALN_SDC_ERR_3    V_ENABLE_ALN_SDC_ERR_3(1U)
46584 #define V_ENABLE_ALN_SDC_ERR_2(x) ((x) << S_ENABLE_ALN_SDC_ERR_2)
46585 #define F_ENABLE_ALN_SDC_ERR_2    V_ENABLE_ALN_SDC_ERR_2(1U)
46587 #define S_T7_ENABLE_ALN_SDC_ERR_1    1
46588 #define V_T7_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_1)
46589 #define F_T7_ENABLE_ALN_SDC_ERR_1    V_T7_ENABLE_ALN_SDC_ERR_1(1U)
46592 #define V_T7_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_T7_ENABLE_ALN_SDC_ERR_0)
46593 #define F_T7_ENABLE_ALN_SDC_ERR_0    V_T7_ENABLE_ALN_SDC_ERR_0(1U)
46598 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
46599 #define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)
46602 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
46603 #define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)
46606 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
46607 #define F_CAUSE_FF    V_CAUSE_FF(1U)
46610 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
46611 #define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)
46614 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
46615 #define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)
46618 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
46619 #define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)
46622 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
46623 #define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)
46626 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
46627 #define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)
46630 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
46631 #define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)
46634 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
46635 #define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)
46638 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
46639 #define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)
46642 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
46643 #define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)
46646 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
46647 #define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)
46650 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
46651 #define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)
46654 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
46655 #define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)
46658 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
46659 #define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)
46662 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
46663 #define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)
46666 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
46667 #define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)
46670 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
46671 #define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)
46674 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
46675 #define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)
46678 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
46679 #define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)
46682 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
46683 #define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)
46686 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
46687 #define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)
46689 #define S_CAUSE_MPARF_0    1
46690 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
46691 #define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)
46694 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
46695 #define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)
46701 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
46702 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
46708 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
46709 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
46715 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
46716 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
46722 #define V_HPZ3(x) ((x) << S_HPZ3)
46723 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
46727 #define V_HPZ2(x) ((x) << S_HPZ2)
46728 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
46732 #define V_HPZ1(x) ((x) << S_HPZ1)
46733 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
46737 #define V_HPZ0(x) ((x) << S_HPZ0)
46738 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
46744 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
46745 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
46751 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
46752 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
46758 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
46759 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
46772 #define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
46773 #define F_PERR_ENABLE_FF    V_PERR_ENABLE_FF(1U)
46776 #define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
46777 #define F_PERR_ENABLE_APF_1    V_PERR_ENABLE_APF_1(1U)
46780 #define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
46781 #define F_PERR_ENABLE_APF_0    V_PERR_ENABLE_APF_0(1U)
46784 #define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
46785 #define F_PERR_ENABLE_AF_1    V_PERR_ENABLE_AF_1(1U)
46788 #define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
46789 #define F_PERR_ENABLE_AF_0    V_PERR_ENABLE_AF_0(1U)
46792 #define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
46793 #define F_PERR_ENABLE_DDPDF_1    V_PERR_ENABLE_DDPDF_1(1U)
46796 #define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
46797 #define F_PERR_ENABLE_DDPMF_1    V_PERR_ENABLE_DDPMF_1(1U)
46800 #define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
46801 #define F_PERR_ENABLE_MEMRF_1    V_PERR_ENABLE_MEMRF_1(1U)
46804 #define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
46805 #define F_PERR_ENABLE_PRSDF_1    V_PERR_ENABLE_PRSDF_1(1U)
46808 #define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
46809 #define F_PERR_ENABLE_DDPDF_0    V_PERR_ENABLE_DDPDF_0(1U)
46812 #define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
46813 #define F_PERR_ENABLE_DDPMF_0    V_PERR_ENABLE_DDPMF_0(1U)
46816 #define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
46817 #define F_PERR_ENABLE_MEMRF_0    V_PERR_ENABLE_MEMRF_0(1U)
46820 #define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
46821 #define F_PERR_ENABLE_PRSDF_0    V_PERR_ENABLE_PRSDF_0(1U)
46824 #define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
46825 #define F_PERR_ENABLE_PCMDF_1    V_PERR_ENABLE_PCMDF_1(1U)
46828 #define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
46829 #define F_PERR_ENABLE_TPTCF_1    V_PERR_ENABLE_TPTCF_1(1U)
46832 #define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
46833 #define F_PERR_ENABLE_DDPCF_1    V_PERR_ENABLE_DDPCF_1(1U)
46836 #define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
46837 #define F_PERR_ENABLE_MPARF_1    V_PERR_ENABLE_MPARF_1(1U)
46840 #define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
46841 #define F_PERR_ENABLE_MPARC_1    V_PERR_ENABLE_MPARC_1(1U)
46844 #define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
46845 #define F_PERR_ENABLE_PCMDF_0    V_PERR_ENABLE_PCMDF_0(1U)
46848 #define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
46849 #define F_PERR_ENABLE_TPTCF_0    V_PERR_ENABLE_TPTCF_0(1U)
46852 #define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
46853 #define F_PERR_ENABLE_DDPCF_0    V_PERR_ENABLE_DDPCF_0(1U)
46855 #define S_PERR_ENABLE_MPARF_0    1
46856 #define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
46857 #define F_PERR_ENABLE_MPARF_0    V_PERR_ENABLE_MPARF_0(1U)
46860 #define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
46861 #define F_PERR_ENABLE_MPARC_0    V_PERR_ENABLE_MPARC_0(1U)
46864 #define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
46865 #define F_PERR_SE_CNT_MISMATCH_1    V_PERR_SE_CNT_MISMATCH_1(1U)
46868 #define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
46869 #define F_PERR_SE_CNT_MISMATCH_0    V_PERR_SE_CNT_MISMATCH_0(1U)
46872 #define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
46873 #define F_PERR_RSVD0    V_PERR_RSVD0(1U)
46876 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
46877 #define F_PERR_RSVD1    V_PERR_RSVD1(1U)
46880 #define V_PERR_ENABLE_CTX_1(x) ((x) << S_PERR_ENABLE_CTX_1)
46881 #define F_PERR_ENABLE_CTX_1    V_PERR_ENABLE_CTX_1(1U)
46884 #define V_PERR_ENABLE_CTX_0(x) ((x) << S_PERR_ENABLE_CTX_0)
46885 #define F_PERR_ENABLE_CTX_0    V_PERR_ENABLE_CTX_0(1U)
46893 #define V_REQ(x) ((x) << S_REQ)
46894 #define F_REQ    V_REQ(1U)
46897 #define V_WB(x) ((x) << S_WB)
46898 #define F_WB    V_WB(1U)
46902 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
46903 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
46912 #define V_PCMD3THRESHOLD(x) ((x) << S_PCMD3THRESHOLD)
46913 #define G_PCMD3THRESHOLD(x) (((x) >> S_PCMD3THRESHOLD) & M_PCMD3THRESHOLD)
46917 #define V_PCMD2THRESHOLD(x) ((x) << S_PCMD2THRESHOLD)
46918 #define G_PCMD2THRESHOLD(x) (((x) >> S_PCMD2THRESHOLD) & M_PCMD2THRESHOLD)
46922 #define V_T7_PCMD1THRESHOLD(x) ((x) << S_T7_PCMD1THRESHOLD)
46923 #define G_T7_PCMD1THRESHOLD(x) (((x) >> S_T7_PCMD1THRESHOLD) & M_T7_PCMD1THRESHOLD)
46927 #define V_T7_PCMD0THRESHOLD(x) ((x) << S_T7_PCMD0THRESHOLD)
46928 #define G_T7_PCMD0THRESHOLD(x) (((x) >> S_T7_PCMD0THRESHOLD) & M_T7_PCMD0THRESHOLD)
46933 #define V_ENABLE_ULPRX2SBT_RSPPERR(x) ((x) << S_ENABLE_ULPRX2SBT_RSPPERR)
46934 #define F_ENABLE_ULPRX2SBT_RSPPERR    V_ENABLE_ULPRX2SBT_RSPPERR(1U)
46937 #define V_ENABLE_ULPRX2MA_RSPPERR(x) ((x) << S_ENABLE_ULPRX2MA_RSPPERR)
46938 #define F_ENABLE_ULPRX2MA_RSPPERR    V_ENABLE_ULPRX2MA_RSPPERR(1U)
46941 #define V_ENABME_PIO_BUS_PERR(x) ((x) << S_ENABME_PIO_BUS_PERR)
46942 #define F_ENABME_PIO_BUS_PERR    V_ENABME_PIO_BUS_PERR(1U)
46945 #define V_ENABLE_PM2ULP_SNOOPDATA_3(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_3)
46946 #define F_ENABLE_PM2ULP_SNOOPDATA_3    V_ENABLE_PM2ULP_SNOOPDATA_3(1U)
46949 #define V_ENABLE_PM2ULP_SNOOPDATA_2(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_2)
46950 #define F_ENABLE_PM2ULP_SNOOPDATA_2    V_ENABLE_PM2ULP_SNOOPDATA_2(1U)
46953 #define V_ENABLE_PM2ULP_SNOOPDATA_1(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_1)
46954 #define F_ENABLE_PM2ULP_SNOOPDATA_1    V_ENABLE_PM2ULP_SNOOPDATA_1(1U)
46957 #define V_ENABLE_PM2ULP_SNOOPDATA_0(x) ((x) << S_ENABLE_PM2ULP_SNOOPDATA_0)
46958 #define F_ENABLE_PM2ULP_SNOOPDATA_0    V_ENABLE_PM2ULP_SNOOPDATA_0(1U)
46961 #define V_ENABLE_TLS2ULP_DATA_3(x) ((x) << S_ENABLE_TLS2ULP_DATA_3)
46962 #define F_ENABLE_TLS2ULP_DATA_3    V_ENABLE_TLS2ULP_DATA_3(1U)
46965 #define V_ENABLE_TLS2ULP_DATA_2(x) ((x) << S_ENABLE_TLS2ULP_DATA_2)
46966 #define F_ENABLE_TLS2ULP_DATA_2    V_ENABLE_TLS2ULP_DATA_2(1U)
46969 #define V_ENABLE_TLS2ULP_DATA_1(x) ((x) << S_ENABLE_TLS2ULP_DATA_1)
46970 #define F_ENABLE_TLS2ULP_DATA_1    V_ENABLE_TLS2ULP_DATA_1(1U)
46973 #define V_ENABLE_TLS2ULP_DATA_0(x) ((x) << S_ENABLE_TLS2ULP_DATA_0)
46974 #define F_ENABLE_TLS2ULP_DATA_0    V_ENABLE_TLS2ULP_DATA_0(1U)
46977 #define V_ENABLE_TLS2ULP_PLENDATA_3(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_3)
46978 #define F_ENABLE_TLS2ULP_PLENDATA_3    V_ENABLE_TLS2ULP_PLENDATA_3(1U)
46981 #define V_ENABLE_TLS2ULP_PLENDATA_2(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_2)
46982 #define F_ENABLE_TLS2ULP_PLENDATA_2    V_ENABLE_TLS2ULP_PLENDATA_2(1U)
46985 #define V_ENABLE_TLS2ULP_PLENDATA_1(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_1)
46986 #define F_ENABLE_TLS2ULP_PLENDATA_1    V_ENABLE_TLS2ULP_PLENDATA_1(1U)
46989 #define V_ENABLE_TLS2ULP_PLENDATA_0(x) ((x) << S_ENABLE_TLS2ULP_PLENDATA_0)
46990 #define F_ENABLE_TLS2ULP_PLENDATA_0    V_ENABLE_TLS2ULP_PLENDATA_0(1U)
46993 #define V_ENABLE_PM2ULP_DATA_3(x) ((x) << S_ENABLE_PM2ULP_DATA_3)
46994 #define F_ENABLE_PM2ULP_DATA_3    V_ENABLE_PM2ULP_DATA_3(1U)
46997 #define V_ENABLE_PM2ULP_DATA_2(x) ((x) << S_ENABLE_PM2ULP_DATA_2)
46998 #define F_ENABLE_PM2ULP_DATA_2    V_ENABLE_PM2ULP_DATA_2(1U)
47001 #define V_ENABLE_PM2ULP_DATA_1(x) ((x) << S_ENABLE_PM2ULP_DATA_1)
47002 #define F_ENABLE_PM2ULP_DATA_1    V_ENABLE_PM2ULP_DATA_1(1U)
47005 #define V_ENABLE_PM2ULP_DATA_0(x) ((x) << S_ENABLE_PM2ULP_DATA_0)
47006 #define F_ENABLE_PM2ULP_DATA_0    V_ENABLE_PM2ULP_DATA_0(1U)
47009 #define V_ENABLE_TP2ULP_PCMD_3(x) ((x) << S_ENABLE_TP2ULP_PCMD_3)
47010 #define F_ENABLE_TP2ULP_PCMD_3    V_ENABLE_TP2ULP_PCMD_3(1U)
47013 #define V_ENABLE_TP2ULP_PCMD_2(x) ((x) << S_ENABLE_TP2ULP_PCMD_2)
47014 #define F_ENABLE_TP2ULP_PCMD_2    V_ENABLE_TP2ULP_PCMD_2(1U)
47016 #define S_ENABLE_TP2ULP_PCMD_1    1
47017 #define V_ENABLE_TP2ULP_PCMD_1(x) ((x) << S_ENABLE_TP2ULP_PCMD_1)
47018 #define F_ENABLE_TP2ULP_PCMD_1    V_ENABLE_TP2ULP_PCMD_1(1U)
47021 #define V_ENABLE_TP2ULP_PCMD_0(x) ((x) << S_ENABLE_TP2ULP_PCMD_0)
47022 #define F_ENABLE_TP2ULP_PCMD_0    V_ENABLE_TP2ULP_PCMD_0(1U)
47027 #define V_CAUSE_ULPRX2SBT_RSPPERR(x) ((x) << S_CAUSE_ULPRX2SBT_RSPPERR)
47028 #define F_CAUSE_ULPRX2SBT_RSPPERR    V_CAUSE_ULPRX2SBT_RSPPERR(1U)
47031 #define V_CAUSE_ULPRX2MA_RSPPERR(x) ((x) << S_CAUSE_ULPRX2MA_RSPPERR)
47032 #define F_CAUSE_ULPRX2MA_RSPPERR    V_CAUSE_ULPRX2MA_RSPPERR(1U)
47035 #define V_CAUSE_PIO_BUS_PERR(x) ((x) << S_CAUSE_PIO_BUS_PERR)
47036 #define F_CAUSE_PIO_BUS_PERR    V_CAUSE_PIO_BUS_PERR(1U)
47039 #define V_CAUSE_PM2ULP_SNOOPDATA_3(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_3)
47040 #define F_CAUSE_PM2ULP_SNOOPDATA_3    V_CAUSE_PM2ULP_SNOOPDATA_3(1U)
47043 #define V_CAUSE_PM2ULP_SNOOPDATA_2(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_2)
47044 #define F_CAUSE_PM2ULP_SNOOPDATA_2    V_CAUSE_PM2ULP_SNOOPDATA_2(1U)
47047 #define V_CAUSE_PM2ULP_SNOOPDATA_1(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_1)
47048 #define F_CAUSE_PM2ULP_SNOOPDATA_1    V_CAUSE_PM2ULP_SNOOPDATA_1(1U)
47051 #define V_CAUSE_PM2ULP_SNOOPDATA_0(x) ((x) << S_CAUSE_PM2ULP_SNOOPDATA_0)
47052 #define F_CAUSE_PM2ULP_SNOOPDATA_0    V_CAUSE_PM2ULP_SNOOPDATA_0(1U)
47055 #define V_CAUSE_TLS2ULP_DATA_3(x) ((x) << S_CAUSE_TLS2ULP_DATA_3)
47056 #define F_CAUSE_TLS2ULP_DATA_3    V_CAUSE_TLS2ULP_DATA_3(1U)
47059 #define V_CAUSE_TLS2ULP_DATA_2(x) ((x) << S_CAUSE_TLS2ULP_DATA_2)
47060 #define F_CAUSE_TLS2ULP_DATA_2    V_CAUSE_TLS2ULP_DATA_2(1U)
47063 #define V_CAUSE_TLS2ULP_DATA_1(x) ((x) << S_CAUSE_TLS2ULP_DATA_1)
47064 #define F_CAUSE_TLS2ULP_DATA_1    V_CAUSE_TLS2ULP_DATA_1(1U)
47067 #define V_CAUSE_TLS2ULP_DATA_0(x) ((x) << S_CAUSE_TLS2ULP_DATA_0)
47068 #define F_CAUSE_TLS2ULP_DATA_0    V_CAUSE_TLS2ULP_DATA_0(1U)
47071 #define V_CAUSE_TLS2ULP_PLENDATA_3(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_3)
47072 #define F_CAUSE_TLS2ULP_PLENDATA_3    V_CAUSE_TLS2ULP_PLENDATA_3(1U)
47075 #define V_CAUSE_TLS2ULP_PLENDATA_2(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_2)
47076 #define F_CAUSE_TLS2ULP_PLENDATA_2    V_CAUSE_TLS2ULP_PLENDATA_2(1U)
47079 #define V_CAUSE_TLS2ULP_PLENDATA_1(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_1)
47080 #define F_CAUSE_TLS2ULP_PLENDATA_1    V_CAUSE_TLS2ULP_PLENDATA_1(1U)
47083 #define V_CAUSE_TLS2ULP_PLENDATA_0(x) ((x) << S_CAUSE_TLS2ULP_PLENDATA_0)
47084 #define F_CAUSE_TLS2ULP_PLENDATA_0    V_CAUSE_TLS2ULP_PLENDATA_0(1U)
47087 #define V_CAUSE_PM2ULP_DATA_3(x) ((x) << S_CAUSE_PM2ULP_DATA_3)
47088 #define F_CAUSE_PM2ULP_DATA_3    V_CAUSE_PM2ULP_DATA_3(1U)
47091 #define V_CAUSE_PM2ULP_DATA_2(x) ((x) << S_CAUSE_PM2ULP_DATA_2)
47092 #define F_CAUSE_PM2ULP_DATA_2    V_CAUSE_PM2ULP_DATA_2(1U)
47095 #define V_CAUSE_PM2ULP_DATA_1(x) ((x) << S_CAUSE_PM2ULP_DATA_1)
47096 #define F_CAUSE_PM2ULP_DATA_1    V_CAUSE_PM2ULP_DATA_1(1U)
47099 #define V_CAUSE_PM2ULP_DATA_0(x) ((x) << S_CAUSE_PM2ULP_DATA_0)
47100 #define F_CAUSE_PM2ULP_DATA_0    V_CAUSE_PM2ULP_DATA_0(1U)
47103 #define V_CAUSE_TP2ULP_PCMD_3(x) ((x) << S_CAUSE_TP2ULP_PCMD_3)
47104 #define F_CAUSE_TP2ULP_PCMD_3    V_CAUSE_TP2ULP_PCMD_3(1U)
47107 #define V_CAUSE_TP2ULP_PCMD_2(x) ((x) << S_CAUSE_TP2ULP_PCMD_2)
47108 #define F_CAUSE_TP2ULP_PCMD_2    V_CAUSE_TP2ULP_PCMD_2(1U)
47110 #define S_CAUSE_TP2ULP_PCMD_1    1
47111 #define V_CAUSE_TP2ULP_PCMD_1(x) ((x) << S_CAUSE_TP2ULP_PCMD_1)
47112 #define F_CAUSE_TP2ULP_PCMD_1    V_CAUSE_TP2ULP_PCMD_1(1U)
47115 #define V_CAUSE_TP2ULP_PCMD_0(x) ((x) << S_CAUSE_TP2ULP_PCMD_0)
47116 #define F_CAUSE_TP2ULP_PCMD_0    V_CAUSE_TP2ULP_PCMD_0(1U)
47121 #define V_PERR_ULPRX2SBT_RSPPERR(x) ((x) << S_PERR_ULPRX2SBT_RSPPERR)
47122 #define F_PERR_ULPRX2SBT_RSPPERR    V_PERR_ULPRX2SBT_RSPPERR(1U)
47125 #define V_PERR_ULPRX2MA_RSPPERR(x) ((x) << S_PERR_ULPRX2MA_RSPPERR)
47126 #define F_PERR_ULPRX2MA_RSPPERR    V_PERR_ULPRX2MA_RSPPERR(1U)
47129 #define V_PERR_PIO_BUS_PERR(x) ((x) << S_PERR_PIO_BUS_PERR)
47130 #define F_PERR_PIO_BUS_PERR    V_PERR_PIO_BUS_PERR(1U)
47133 #define V_PERR_PM2ULP_SNOOPDATA_3(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_3)
47134 #define F_PERR_PM2ULP_SNOOPDATA_3    V_PERR_PM2ULP_SNOOPDATA_3(1U)
47137 #define V_PERR_PM2ULP_SNOOPDATA_2(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_2)
47138 #define F_PERR_PM2ULP_SNOOPDATA_2    V_PERR_PM2ULP_SNOOPDATA_2(1U)
47141 #define V_PERR_PM2ULP_SNOOPDATA_1(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_1)
47142 #define F_PERR_PM2ULP_SNOOPDATA_1    V_PERR_PM2ULP_SNOOPDATA_1(1U)
47145 #define V_PERR_PM2ULP_SNOOPDATA_0(x) ((x) << S_PERR_PM2ULP_SNOOPDATA_0)
47146 #define F_PERR_PM2ULP_SNOOPDATA_0    V_PERR_PM2ULP_SNOOPDATA_0(1U)
47149 #define V_PERR_TLS2ULP_DATA_3(x) ((x) << S_PERR_TLS2ULP_DATA_3)
47150 #define F_PERR_TLS2ULP_DATA_3    V_PERR_TLS2ULP_DATA_3(1U)
47153 #define V_PERR_TLS2ULP_DATA_2(x) ((x) << S_PERR_TLS2ULP_DATA_2)
47154 #define F_PERR_TLS2ULP_DATA_2    V_PERR_TLS2ULP_DATA_2(1U)
47157 #define V_PERR_TLS2ULP_DATA_1(x) ((x) << S_PERR_TLS2ULP_DATA_1)
47158 #define F_PERR_TLS2ULP_DATA_1    V_PERR_TLS2ULP_DATA_1(1U)
47161 #define V_PERR_TLS2ULP_DATA_0(x) ((x) << S_PERR_TLS2ULP_DATA_0)
47162 #define F_PERR_TLS2ULP_DATA_0    V_PERR_TLS2ULP_DATA_0(1U)
47165 #define V_PERR_TLS2ULP_PLENDATA_3(x) ((x) << S_PERR_TLS2ULP_PLENDATA_3)
47166 #define F_PERR_TLS2ULP_PLENDATA_3    V_PERR_TLS2ULP_PLENDATA_3(1U)
47169 #define V_PERR_TLS2ULP_PLENDATA_2(x) ((x) << S_PERR_TLS2ULP_PLENDATA_2)
47170 #define F_PERR_TLS2ULP_PLENDATA_2    V_PERR_TLS2ULP_PLENDATA_2(1U)
47173 #define V_PERR_TLS2ULP_PLENDATA_1(x) ((x) << S_PERR_TLS2ULP_PLENDATA_1)
47174 #define F_PERR_TLS2ULP_PLENDATA_1    V_PERR_TLS2ULP_PLENDATA_1(1U)
47177 #define V_PERR_TLS2ULP_PLENDATA_0(x) ((x) << S_PERR_TLS2ULP_PLENDATA_0)
47178 #define F_PERR_TLS2ULP_PLENDATA_0    V_PERR_TLS2ULP_PLENDATA_0(1U)
47181 #define V_PERR_PM2ULP_DATA_3(x) ((x) << S_PERR_PM2ULP_DATA_3)
47182 #define F_PERR_PM2ULP_DATA_3    V_PERR_PM2ULP_DATA_3(1U)
47185 #define V_PERR_PM2ULP_DATA_2(x) ((x) << S_PERR_PM2ULP_DATA_2)
47186 #define F_PERR_PM2ULP_DATA_2    V_PERR_PM2ULP_DATA_2(1U)
47189 #define V_PERR_PM2ULP_DATA_1(x) ((x) << S_PERR_PM2ULP_DATA_1)
47190 #define F_PERR_PM2ULP_DATA_1    V_PERR_PM2ULP_DATA_1(1U)
47193 #define V_PERR_PM2ULP_DATA_0(x) ((x) << S_PERR_PM2ULP_DATA_0)
47194 #define F_PERR_PM2ULP_DATA_0    V_PERR_PM2ULP_DATA_0(1U)
47197 #define V_PERR_TP2ULP_PCMD_3(x) ((x) << S_PERR_TP2ULP_PCMD_3)
47198 #define F_PERR_TP2ULP_PCMD_3    V_PERR_TP2ULP_PCMD_3(1U)
47201 #define V_PERR_TP2ULP_PCMD_2(x) ((x) << S_PERR_TP2ULP_PCMD_2)
47202 #define F_PERR_TP2ULP_PCMD_2    V_PERR_TP2ULP_PCMD_2(1U)
47204 #define S_PERR_TP2ULP_PCMD_1    1
47205 #define V_PERR_TP2ULP_PCMD_1(x) ((x) << S_PERR_TP2ULP_PCMD_1)
47206 #define F_PERR_TP2ULP_PCMD_1    V_PERR_TP2ULP_PCMD_1(1U)
47209 #define V_PERR_TP2ULP_PCMD_0(x) ((x) << S_PERR_TP2ULP_PCMD_0)
47210 #define F_PERR_TP2ULP_PCMD_0    V_PERR_TP2ULP_PCMD_0(1U)
47217 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
47218 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
47222 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
47223 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
47227 #define V_CLRCHAN3(x) ((x) << S_CLRCHAN3)
47228 #define G_CLRCHAN3(x) (((x) >> S_CLRCHAN3) & M_CLRCHAN3)
47232 #define V_CLRCHAN2(x) ((x) << S_CLRCHAN2)
47233 #define G_CLRCHAN2(x) (((x) >> S_CLRCHAN2) & M_CLRCHAN2)
47237 #define V_T7_CLRCHAN1(x) ((x) << S_T7_CLRCHAN1)
47238 #define G_T7_CLRCHAN1(x) (((x) >> S_T7_CLRCHAN1) & M_T7_CLRCHAN1)
47242 #define V_T7_CLRCHAN0(x) ((x) << S_T7_CLRCHAN0)
47243 #define G_T7_CLRCHAN0(x) (((x) >> S_T7_CLRCHAN0) & M_T7_CLRCHAN0)
47249 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
47250 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
47254 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
47255 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
47259 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
47260 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
47264 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
47265 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
47269 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
47270 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
47274 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
47275 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
47279 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
47280 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
47284 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
47285 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
47291 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
47292 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
47296 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
47297 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
47301 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
47302 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
47306 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
47307 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
47311 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
47312 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
47316 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
47317 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
47321 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
47322 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
47326 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
47327 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
47332 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
47333 #define F_EN_DBG_H    V_EN_DBG_H(1U)
47336 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
47337 #define F_EN_DBG_L    V_EN_DBG_L(1U)
47341 #define V_SEL_H(x) ((x) << S_SEL_H)
47342 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
47346 #define V_SEL_L(x) ((x) << S_SEL_L)
47347 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
47355 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
47356 #define F_CHNL_SEL    V_CHNL_SEL(1U)
47361 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
47362 #define F_TRC_SEL    V_TRC_SEL(1U)
47368 #define V_RD_PTR(x) ((x) << S_RD_PTR)
47369 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
47376 #define V_WR_PTR(x) ((x) << S_WR_PTR)
47377 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
47382 #define S_TERMIMATE_MSG    1
47383 #define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
47384 #define F_TERMIMATE_MSG    V_TERMIMATE_MSG(1U)
47387 #define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
47388 #define F_TERMINATE_WITH_ERR    V_TERMINATE_WITH_ERR(1U)
47394 #define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
47395 #define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
47399 #define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
47400 #define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
47404 #define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
47405 #define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
47409 #define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
47410 #define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
47414 #define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
47415 #define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
47419 #define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
47420 #define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
47424 #define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
47425 #define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
47429 #define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
47430 #define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
47435 #define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
47436 #define F_EN_ORIG_DATA    V_EN_ORIG_DATA(1U)
47441 #define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
47442 #define F_TERMINATE_STATUS_EN    V_TERMINATE_STATUS_EN(1U)
47445 #define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
47446 #define F_MULTIPLE_PREF_ENABLE    V_MULTIPLE_PREF_ENABLE(1U)
47449 #define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
47450 #define F_UMUDP_PBL_PREF_ENABLE    V_UMUDP_PBL_PREF_ENABLE(1U)
47452 #define S_RDMA_PBL_PREF_EN    1
47453 #define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
47454 #define F_RDMA_PBL_PREF_EN    V_RDMA_PBL_PREF_EN(1U)
47457 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
47458 #define F_SDC_CRC_PROT_EN    V_SDC_CRC_PROT_EN(1U)
47461 #define V_ISCSI_DCRC_ERROR_CMP_EN(x) ((x) << S_ISCSI_DCRC_ERROR_CMP_EN)
47462 #define F_ISCSI_DCRC_ERROR_CMP_EN    V_ISCSI_DCRC_ERROR_CMP_EN(1U)
47465 #define V_ISCSITAGPI(x) ((x) << S_ISCSITAGPI)
47466 #define F_ISCSITAGPI    V_ISCSITAGPI(1U)
47470 #define V_DDP_VERSION_1(x) ((x) << S_DDP_VERSION_1)
47471 #define G_DDP_VERSION_1(x) (((x) >> S_DDP_VERSION_1) & M_DDP_VERSION_1)
47475 #define V_DDP_VERSION_0(x) ((x) << S_DDP_VERSION_0)
47476 #define G_DDP_VERSION_0(x) (((x) >> S_DDP_VERSION_0) & M_DDP_VERSION_0)
47480 #define V_RDMA_VERSION_1(x) ((x) << S_RDMA_VERSION_1)
47481 #define G_RDMA_VERSION_1(x) (((x) >> S_RDMA_VERSION_1) & M_RDMA_VERSION_1)
47485 #define V_RDMA_VERSION_0(x) ((x) << S_RDMA_VERSION_0)
47486 #define G_RDMA_VERSION_0(x) (((x) >> S_RDMA_VERSION_0) & M_RDMA_VERSION_0)
47489 #define V_PBL_BOUND_CHECK_W_PGLEN(x) ((x) << S_PBL_BOUND_CHECK_W_PGLEN)
47490 #define F_PBL_BOUND_CHECK_W_PGLEN    V_PBL_BOUND_CHECK_W_PGLEN(1U)
47493 #define V_ZBYTE_FIX_DISABLE(x) ((x) << S_ZBYTE_FIX_DISABLE)
47494 #define F_ZBYTE_FIX_DISABLE    V_ZBYTE_FIX_DISABLE(1U)
47497 #define V_T10_OFFSET_UPDATE_EN(x) ((x) << S_T10_OFFSET_UPDATE_EN)
47498 #define F_T10_OFFSET_UPDATE_EN    V_T10_OFFSET_UPDATE_EN(1U)
47501 #define V_ULP_INSERT_PI(x) ((x) << S_ULP_INSERT_PI)
47502 #define F_ULP_INSERT_PI    V_ULP_INSERT_PI(1U)
47505 #define V_PDU_DPI(x) ((x) << S_PDU_DPI)
47506 #define F_PDU_DPI    V_PDU_DPI(1U)
47509 #define V_ISCSI_EFF_OFFSET_EN(x) ((x) << S_ISCSI_EFF_OFFSET_EN)
47510 #define F_ISCSI_EFF_OFFSET_EN    V_ISCSI_EFF_OFFSET_EN(1U)
47513 #define V_ISCSI_ALL_CMP_MODE(x) ((x) << S_ISCSI_ALL_CMP_MODE)
47514 #define F_ISCSI_ALL_CMP_MODE    V_ISCSI_ALL_CMP_MODE(1U)
47517 #define V_ISCSI_ENABLE_HDR_CMD(x) ((x) << S_ISCSI_ENABLE_HDR_CMD)
47518 #define F_ISCSI_ENABLE_HDR_CMD    V_ISCSI_ENABLE_HDR_CMD(1U)
47521 #define V_ISCSI_FORCE_CMP_MODE(x) ((x) << S_ISCSI_FORCE_CMP_MODE)
47522 #define F_ISCSI_FORCE_CMP_MODE    V_ISCSI_FORCE_CMP_MODE(1U)
47525 #define V_ISCSI_ENABLE_CMP_MODE(x) ((x) << S_ISCSI_ENABLE_CMP_MODE)
47526 #define F_ISCSI_ENABLE_CMP_MODE    V_ISCSI_ENABLE_CMP_MODE(1U)
47529 #define V_PIO_RDMA_SEND_RQE(x) ((x) << S_PIO_RDMA_SEND_RQE)
47530 #define F_PIO_RDMA_SEND_RQE    V_PIO_RDMA_SEND_RQE(1U)
47534 #define V_TLS_KEYSIZECONF(x) ((x) << S_TLS_KEYSIZECONF)
47535 #define G_TLS_KEYSIZECONF(x) (((x) >> S_TLS_KEYSIZECONF) & M_TLS_KEYSIZECONF)
47540 #define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
47541 #define F_BYPASS_CGEN    V_BYPASS_CGEN(1U)
47544 #define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
47545 #define F_TDDP_CGEN    V_TDDP_CGEN(1U)
47548 #define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
47549 #define F_ISCSI_CGEN    V_ISCSI_CGEN(1U)
47552 #define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
47553 #define F_RDMA_CGEN    V_RDMA_CGEN(1U)
47556 #define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
47557 #define F_CHANNEL_CGEN    V_CHANNEL_CGEN(1U)
47560 #define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
47561 #define F_ALL_DATAPATH_CGEN    V_ALL_DATAPATH_CGEN(1U)
47563 #define S_T10DIFF_DATAPATH_CGEN    1
47564 #define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
47565 #define F_T10DIFF_DATAPATH_CGEN    V_T10DIFF_DATAPATH_CGEN(1U)
47568 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
47569 #define F_RDMA_DATAPATH_CGEN    V_RDMA_DATAPATH_CGEN(1U)
47575 #define V_T7_BYPASS_CGEN(x) ((x) << S_T7_BYPASS_CGEN)
47576 #define G_T7_BYPASS_CGEN(x) (((x) >> S_T7_BYPASS_CGEN) & M_T7_BYPASS_CGEN)
47580 #define V_T7_TDDP_CGEN(x) ((x) << S_T7_TDDP_CGEN)
47581 #define G_T7_TDDP_CGEN(x) (((x) >> S_T7_TDDP_CGEN) & M_T7_TDDP_CGEN)
47585 #define V_T7_ISCSI_CGEN(x) ((x) << S_T7_ISCSI_CGEN)
47586 #define G_T7_ISCSI_CGEN(x) (((x) >> S_T7_ISCSI_CGEN) & M_T7_ISCSI_CGEN)
47590 #define V_T7_RDMA_CGEN(x) ((x) << S_T7_RDMA_CGEN)
47591 #define G_T7_RDMA_CGEN(x) (((x) >> S_T7_RDMA_CGEN) & M_T7_RDMA_CGEN)
47595 #define V_T7_CHANNEL_CGEN(x) ((x) << S_T7_CHANNEL_CGEN)
47596 #define G_T7_CHANNEL_CGEN(x) (((x) >> S_T7_CHANNEL_CGEN) & M_T7_CHANNEL_CGEN)
47600 #define V_T7_ALL_DATAPATH_CGEN(x) ((x) << S_T7_ALL_DATAPATH_CGEN)
47601 #define G_T7_ALL_DATAPATH_CGEN(x) (((x) >> S_T7_ALL_DATAPATH_CGEN) & M_T7_ALL_DATAPATH_CGEN)
47605 #define V_T7_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T7_T10DIFF_DATAPATH_CGEN)
47606 #define G_T7_T10DIFF_DATAPATH_CGEN(x) (((x) >> S_T7_T10DIFF_DATAPATH_CGEN) & M_T7_T10DIFF_DATAPATH_CGEN)
47610 #define V_T7_RDMA_DATAPATH_CGEN(x) ((x) << S_T7_RDMA_DATAPATH_CGEN)
47611 #define G_T7_RDMA_DATAPATH_CGEN(x) (((x) >> S_T7_RDMA_DATAPATH_CGEN) & M_T7_RDMA_DATAPATH_CGEN)
47618 #define V_NVME_TCP_CGEN(x) ((x) << S_NVME_TCP_CGEN)
47619 #define G_NVME_TCP_CGEN(x) (((x) >> S_NVME_TCP_CGEN) & M_NVME_TCP_CGEN)
47623 #define V_ROCE_CGEN(x) ((x) << S_ROCE_CGEN)
47624 #define G_ROCE_CGEN(x) (((x) >> S_ROCE_CGEN) & M_ROCE_CGEN)
47629 #define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
47630 #define F_RQE_LIM_CHECK_RFE_DISABLE    V_RQE_LIM_CHECK_RFE_DISABLE(1U)
47635 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
47636 #define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)
47639 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
47640 #define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)
47643 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
47644 #define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)
47647 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
47648 #define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)
47651 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
47652 #define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)
47655 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
47656 #define F_PF_PBL_1    V_PF_PBL_1(1U)
47659 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
47660 #define F_PF_PBL_0    V_PF_PBL_0(1U)
47662 #define S_DDP_HINT_1    1
47663 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
47664 #define F_DDP_HINT_1    V_DDP_HINT_1(1U)
47667 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
47668 #define F_DDP_HINT_0    V_DDP_HINT_0(1U)
47674 #define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
47675 #define F_ENABLE_ULPRX2MA_INTFPERR    V_ENABLE_ULPRX2MA_INTFPERR(1U)
47678 #define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
47679 #define F_ENABLE_ALN_SDC_ERR_1    V_ENABLE_ALN_SDC_ERR_1(1U)
47682 #define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
47683 #define F_ENABLE_ALN_SDC_ERR_0    V_ENABLE_ALN_SDC_ERR_0(1U)
47686 #define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
47687 #define F_ENABLE_PF_UNTAGGED_TPT_1    V_ENABLE_PF_UNTAGGED_TPT_1(1U)
47690 #define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
47691 #define F_ENABLE_PF_UNTAGGED_TPT_0    V_ENABLE_PF_UNTAGGED_TPT_0(1U)
47694 #define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
47695 #define F_ENABLE_PF_PBL_1    V_ENABLE_PF_PBL_1(1U)
47698 #define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
47699 #define F_ENABLE_PF_PBL_0    V_ENABLE_PF_PBL_0(1U)
47701 #define S_ENABLE_DDP_HINT_1    1
47702 #define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
47703 #define F_ENABLE_DDP_HINT_1    V_ENABLE_DDP_HINT_1(1U)
47706 #define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
47707 #define F_ENABLE_DDP_HINT_0    V_ENABLE_DDP_HINT_0(1U)
47713 #define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
47714 #define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
47720 #define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
47721 #define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
47725 #define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
47726 #define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
47730 #define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
47731 #define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
47737 #define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
47738 #define F_CLEAR_CTX_ERR_CNT1    V_CLEAR_CTX_ERR_CNT1(1U)
47741 #define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
47742 #define F_CLEAR_CTX_ERR_CNT0    V_CLEAR_CTX_ERR_CNT0(1U)
47744 #define S_SKIP_MA_REQ_EN1    1
47745 #define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
47746 #define F_SKIP_MA_REQ_EN1    V_SKIP_MA_REQ_EN1(1U)
47749 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
47750 #define F_SKIP_MA_REQ_EN0    V_SKIP_MA_REQ_EN0(1U)
47753 #define V_CLEAR_CTX_ERR_CNT3(x) ((x) << S_CLEAR_CTX_ERR_CNT3)
47754 #define F_CLEAR_CTX_ERR_CNT3    V_CLEAR_CTX_ERR_CNT3(1U)
47757 #define V_CLEAR_CTX_ERR_CNT2(x) ((x) << S_CLEAR_CTX_ERR_CNT2)
47758 #define F_CLEAR_CTX_ERR_CNT2    V_CLEAR_CTX_ERR_CNT2(1U)
47761 #define V_T7_CLEAR_CTX_ERR_CNT1(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT1)
47762 #define F_T7_CLEAR_CTX_ERR_CNT1    V_T7_CLEAR_CTX_ERR_CNT1(1U)
47765 #define V_T7_CLEAR_CTX_ERR_CNT0(x) ((x) << S_T7_CLEAR_CTX_ERR_CNT0)
47766 #define F_T7_CLEAR_CTX_ERR_CNT0    V_T7_CLEAR_CTX_ERR_CNT0(1U)
47769 #define V_SKIP_MA_REQ_EN3(x) ((x) << S_SKIP_MA_REQ_EN3)
47770 #define F_SKIP_MA_REQ_EN3    V_SKIP_MA_REQ_EN3(1U)
47773 #define V_SKIP_MA_REQ_EN2(x) ((x) << S_SKIP_MA_REQ_EN2)
47774 #define F_SKIP_MA_REQ_EN2    V_SKIP_MA_REQ_EN2(1U)
47781 #define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
47782 #define F_RD_OR_TERM_MSN_CHECK_ENABLE    V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
47784 #define S_ATOMIC_OP_MSN_CHECK_ENABLE    1
47785 #define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
47786 #define F_ATOMIC_OP_MSN_CHECK_ENABLE    V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
47789 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
47790 #define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
47796 #define V_SOP_CNT_OUT2(x) ((x) << S_SOP_CNT_OUT2)
47797 #define G_SOP_CNT_OUT2(x) (((x) >> S_SOP_CNT_OUT2) & M_SOP_CNT_OUT2)
47801 #define V_EOP_CNT_OUT2(x) ((x) << S_EOP_CNT_OUT2)
47802 #define G_EOP_CNT_OUT2(x) (((x) >> S_EOP_CNT_OUT2) & M_EOP_CNT_OUT2)
47806 #define V_SOP_CNT_AL2(x) ((x) << S_SOP_CNT_AL2)
47807 #define G_SOP_CNT_AL2(x) (((x) >> S_SOP_CNT_AL2) & M_SOP_CNT_AL2)
47811 #define V_EOP_CNT_AL2(x) ((x) << S_EOP_CNT_AL2)
47812 #define G_EOP_CNT_AL2(x) (((x) >> S_EOP_CNT_AL2) & M_EOP_CNT_AL2)
47816 #define V_SOP_CNT_MR2(x) ((x) << S_SOP_CNT_MR2)
47817 #define G_SOP_CNT_MR2(x) (((x) >> S_SOP_CNT_MR2) & M_SOP_CNT_MR2)
47821 #define V_EOP_CNT_MR2(x) ((x) << S_EOP_CNT_MR2)
47822 #define G_EOP_CNT_MR2(x) (((x) >> S_EOP_CNT_MR2) & M_EOP_CNT_MR2)
47826 #define V_SOP_CNT_IN2(x) ((x) << S_SOP_CNT_IN2)
47827 #define G_SOP_CNT_IN2(x) (((x) >> S_SOP_CNT_IN2) & M_SOP_CNT_IN2)
47831 #define V_EOP_CNT_IN2(x) ((x) << S_EOP_CNT_IN2)
47832 #define G_EOP_CNT_IN2(x) (((x) >> S_EOP_CNT_IN2) & M_EOP_CNT_IN2)
47838 #define V_SOP_CNT_OUT3(x) ((x) << S_SOP_CNT_OUT3)
47839 #define G_SOP_CNT_OUT3(x) (((x) >> S_SOP_CNT_OUT3) & M_SOP_CNT_OUT3)
47843 #define V_EOP_CNT_OUT3(x) ((x) << S_EOP_CNT_OUT3)
47844 #define G_EOP_CNT_OUT3(x) (((x) >> S_EOP_CNT_OUT3) & M_EOP_CNT_OUT3)
47848 #define V_SOP_CNT_AL3(x) ((x) << S_SOP_CNT_AL3)
47849 #define G_SOP_CNT_AL3(x) (((x) >> S_SOP_CNT_AL3) & M_SOP_CNT_AL3)
47853 #define V_EOP_CNT_AL3(x) ((x) << S_EOP_CNT_AL3)
47854 #define G_EOP_CNT_AL3(x) (((x) >> S_EOP_CNT_AL3) & M_EOP_CNT_AL3)
47858 #define V_SOP_CNT_MR3(x) ((x) << S_SOP_CNT_MR3)
47859 #define G_SOP_CNT_MR3(x) (((x) >> S_SOP_CNT_MR3) & M_SOP_CNT_MR3)
47863 #define V_EOP_CNT_MR3(x) ((x) << S_EOP_CNT_MR3)
47864 #define G_EOP_CNT_MR3(x) (((x) >> S_EOP_CNT_MR3) & M_EOP_CNT_MR3)
47868 #define V_SOP_CNT_IN3(x) ((x) << S_SOP_CNT_IN3)
47869 #define G_SOP_CNT_IN3(x) (((x) >> S_SOP_CNT_IN3) & M_SOP_CNT_IN3)
47873 #define V_EOP_CNT_IN3(x) ((x) << S_EOP_CNT_IN3)
47874 #define G_EOP_CNT_IN3(x) (((x) >> S_EOP_CNT_IN3) & M_EOP_CNT_IN3)
47882 #define V_TLSPPLLIMIT(x) ((x) << S_TLSPPLLIMIT)
47883 #define G_TLSPPLLIMIT(x) (((x) >> S_TLSPPLLIMIT) & M_TLSPPLLIMIT)
47889 #define V_TLSPPULIMIT(x) ((x) << S_TLSPPULIMIT)
47890 #define G_TLSPPULIMIT(x) (((x) >> S_TLSPPULIMIT) & M_TLSPPULIMIT)
47896 #define V_TLSKEYLLIMIT(x) ((x) << S_TLSKEYLLIMIT)
47897 #define G_TLSKEYLLIMIT(x) (((x) >> S_TLSKEYLLIMIT) & M_TLSKEYLLIMIT)
47903 #define V_TLSKEYULIMIT(x) ((x) << S_TLSKEYULIMIT)
47904 #define G_TLSKEYULIMIT(x) (((x) >> S_TLSKEYULIMIT) & M_TLSKEYULIMIT)
47919 #define V_NVME_TCP_MAX_PLEN01(x) ((x) << S_NVME_TCP_MAX_PLEN01)
47920 #define G_NVME_TCP_MAX_PLEN01(x) (((x) >> S_NVME_TCP_MAX_PLEN01) & M_NVME_TCP_MAX_PLEN01)
47924 #define V_NVME_TCP_MAX_PLEN23(x) ((x) << S_NVME_TCP_MAX_PLEN23)
47925 #define G_NVME_TCP_MAX_PLEN23(x) (((x) >> S_NVME_TCP_MAX_PLEN23) & M_NVME_TCP_MAX_PLEN23)
47929 #define V_NVME_TCP_MAX_CMD_PDU_LENGTH(x) ((x) << S_NVME_TCP_MAX_CMD_PDU_LENGTH)
47930 #define G_NVME_TCP_MAX_CMD_PDU_LENGTH(x) (((x) >> S_NVME_TCP_MAX_CMD_PDU_LENGTH) & M_NVME_TCP_MAX_CMD_PDU_LENGTH)
47939 #define V_ENABLE_PCMD_SFIFO_3(x) ((x) << S_ENABLE_PCMD_SFIFO_3)
47940 #define F_ENABLE_PCMD_SFIFO_3    V_ENABLE_PCMD_SFIFO_3(1U)
47943 #define V_ENABLE_PCMD_FIFO_3(x) ((x) << S_ENABLE_PCMD_FIFO_3)
47944 #define F_ENABLE_PCMD_FIFO_3    V_ENABLE_PCMD_FIFO_3(1U)
47947 #define V_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_ENABLE_PCMD_DDP_HINT_3)
47948 #define F_ENABLE_PCMD_DDP_HINT_3    V_ENABLE_PCMD_DDP_HINT_3(1U)
47951 #define V_ENABLE_PCMD_TPT_3(x) ((x) << S_ENABLE_PCMD_TPT_3)
47952 #define F_ENABLE_PCMD_TPT_3    V_ENABLE_PCMD_TPT_3(1U)
47955 #define V_ENABLE_PCMD_DDP_3(x) ((x) << S_ENABLE_PCMD_DDP_3)
47956 #define F_ENABLE_PCMD_DDP_3    V_ENABLE_PCMD_DDP_3(1U)
47959 #define V_ENABLE_PCMD_MPAR_3(x) ((x) << S_ENABLE_PCMD_MPAR_3)
47960 #define F_ENABLE_PCMD_MPAR_3    V_ENABLE_PCMD_MPAR_3(1U)
47963 #define V_ENABLE_PCMD_MPAC_3(x) ((x) << S_ENABLE_PCMD_MPAC_3)
47964 #define F_ENABLE_PCMD_MPAC_3    V_ENABLE_PCMD_MPAC_3(1U)
47967 #define V_ENABLE_PCMD_SFIFO_2(x) ((x) << S_ENABLE_PCMD_SFIFO_2)
47968 #define F_ENABLE_PCMD_SFIFO_2    V_ENABLE_PCMD_SFIFO_2(1U)
47971 #define V_ENABLE_PCMD_FIFO_2(x) ((x) << S_ENABLE_PCMD_FIFO_2)
47972 #define F_ENABLE_PCMD_FIFO_2    V_ENABLE_PCMD_FIFO_2(1U)
47975 #define V_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_ENABLE_PCMD_DDP_HINT_2)
47976 #define F_ENABLE_PCMD_DDP_HINT_2    V_ENABLE_PCMD_DDP_HINT_2(1U)
47979 #define V_ENABLE_PCMD_TPT_2(x) ((x) << S_ENABLE_PCMD_TPT_2)
47980 #define F_ENABLE_PCMD_TPT_2    V_ENABLE_PCMD_TPT_2(1U)
47983 #define V_ENABLE_PCMD_DDP_2(x) ((x) << S_ENABLE_PCMD_DDP_2)
47984 #define F_ENABLE_PCMD_DDP_2    V_ENABLE_PCMD_DDP_2(1U)
47987 #define V_ENABLE_PCMD_MPAR_2(x) ((x) << S_ENABLE_PCMD_MPAR_2)
47988 #define F_ENABLE_PCMD_MPAR_2    V_ENABLE_PCMD_MPAR_2(1U)
47991 #define V_ENABLE_PCMD_MPAC_2(x) ((x) << S_ENABLE_PCMD_MPAC_2)
47992 #define F_ENABLE_PCMD_MPAC_2    V_ENABLE_PCMD_MPAC_2(1U)
47995 #define V_ENABLE_PCMD_SFIFO_1(x) ((x) << S_ENABLE_PCMD_SFIFO_1)
47996 #define F_ENABLE_PCMD_SFIFO_1    V_ENABLE_PCMD_SFIFO_1(1U)
47999 #define V_ENABLE_PCMD_FIFO_1(x) ((x) << S_ENABLE_PCMD_FIFO_1)
48000 #define F_ENABLE_PCMD_FIFO_1    V_ENABLE_PCMD_FIFO_1(1U)
48003 #define V_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_ENABLE_PCMD_DDP_HINT_1)
48004 #define F_ENABLE_PCMD_DDP_HINT_1    V_ENABLE_PCMD_DDP_HINT_1(1U)
48007 #define V_ENABLE_PCMD_TPT_1(x) ((x) << S_ENABLE_PCMD_TPT_1)
48008 #define F_ENABLE_PCMD_TPT_1    V_ENABLE_PCMD_TPT_1(1U)
48011 #define V_ENABLE_PCMD_DDP_1(x) ((x) << S_ENABLE_PCMD_DDP_1)
48012 #define F_ENABLE_PCMD_DDP_1    V_ENABLE_PCMD_DDP_1(1U)
48015 #define V_ENABLE_PCMD_MPAR_1(x) ((x) << S_ENABLE_PCMD_MPAR_1)
48016 #define F_ENABLE_PCMD_MPAR_1    V_ENABLE_PCMD_MPAR_1(1U)
48019 #define V_ENABLE_PCMD_MPAC_1(x) ((x) << S_ENABLE_PCMD_MPAC_1)
48020 #define F_ENABLE_PCMD_MPAC_1    V_ENABLE_PCMD_MPAC_1(1U)
48023 #define V_ENABLE_PCMD_SFIFO_0(x) ((x) << S_ENABLE_PCMD_SFIFO_0)
48024 #define F_ENABLE_PCMD_SFIFO_0    V_ENABLE_PCMD_SFIFO_0(1U)
48027 #define V_ENABLE_PCMD_FIFO_0(x) ((x) << S_ENABLE_PCMD_FIFO_0)
48028 #define F_ENABLE_PCMD_FIFO_0    V_ENABLE_PCMD_FIFO_0(1U)
48031 #define V_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_ENABLE_PCMD_DDP_HINT_0)
48032 #define F_ENABLE_PCMD_DDP_HINT_0    V_ENABLE_PCMD_DDP_HINT_0(1U)
48035 #define V_ENABLE_PCMD_TPT_0(x) ((x) << S_ENABLE_PCMD_TPT_0)
48036 #define F_ENABLE_PCMD_TPT_0    V_ENABLE_PCMD_TPT_0(1U)
48039 #define V_ENABLE_PCMD_DDP_0(x) ((x) << S_ENABLE_PCMD_DDP_0)
48040 #define F_ENABLE_PCMD_DDP_0    V_ENABLE_PCMD_DDP_0(1U)
48042 #define S_ENABLE_PCMD_MPAR_0    1
48043 #define V_ENABLE_PCMD_MPAR_0(x) ((x) << S_ENABLE_PCMD_MPAR_0)
48044 #define F_ENABLE_PCMD_MPAR_0    V_ENABLE_PCMD_MPAR_0(1U)
48047 #define V_ENABLE_PCMD_MPAC_0(x) ((x) << S_ENABLE_PCMD_MPAC_0)
48048 #define F_ENABLE_PCMD_MPAC_0    V_ENABLE_PCMD_MPAC_0(1U)
48053 #define V_CAUSE_PCMD_SFIFO_3(x) ((x) << S_CAUSE_PCMD_SFIFO_3)
48054 #define F_CAUSE_PCMD_SFIFO_3    V_CAUSE_PCMD_SFIFO_3(1U)
48057 #define V_CAUSE_PCMD_FIFO_3(x) ((x) << S_CAUSE_PCMD_FIFO_3)
48058 #define F_CAUSE_PCMD_FIFO_3    V_CAUSE_PCMD_FIFO_3(1U)
48061 #define V_CAUSE_PCMD_DDP_HINT_3(x) ((x) << S_CAUSE_PCMD_DDP_HINT_3)
48062 #define F_CAUSE_PCMD_DDP_HINT_3    V_CAUSE_PCMD_DDP_HINT_3(1U)
48065 #define V_CAUSE_PCMD_TPT_3(x) ((x) << S_CAUSE_PCMD_TPT_3)
48066 #define F_CAUSE_PCMD_TPT_3    V_CAUSE_PCMD_TPT_3(1U)
48069 #define V_CAUSE_PCMD_DDP_3(x) ((x) << S_CAUSE_PCMD_DDP_3)
48070 #define F_CAUSE_PCMD_DDP_3    V_CAUSE_PCMD_DDP_3(1U)
48073 #define V_CAUSE_PCMD_MPAR_3(x) ((x) << S_CAUSE_PCMD_MPAR_3)
48074 #define F_CAUSE_PCMD_MPAR_3    V_CAUSE_PCMD_MPAR_3(1U)
48077 #define V_CAUSE_PCMD_MPAC_3(x) ((x) << S_CAUSE_PCMD_MPAC_3)
48078 #define F_CAUSE_PCMD_MPAC_3    V_CAUSE_PCMD_MPAC_3(1U)
48081 #define V_CAUSE_PCMD_SFIFO_2(x) ((x) << S_CAUSE_PCMD_SFIFO_2)
48082 #define F_CAUSE_PCMD_SFIFO_2    V_CAUSE_PCMD_SFIFO_2(1U)
48085 #define V_CAUSE_PCMD_FIFO_2(x) ((x) << S_CAUSE_PCMD_FIFO_2)
48086 #define F_CAUSE_PCMD_FIFO_2    V_CAUSE_PCMD_FIFO_2(1U)
48089 #define V_CAUSE_PCMD_DDP_HINT_2(x) ((x) << S_CAUSE_PCMD_DDP_HINT_2)
48090 #define F_CAUSE_PCMD_DDP_HINT_2    V_CAUSE_PCMD_DDP_HINT_2(1U)
48093 #define V_CAUSE_PCMD_TPT_2(x) ((x) << S_CAUSE_PCMD_TPT_2)
48094 #define F_CAUSE_PCMD_TPT_2    V_CAUSE_PCMD_TPT_2(1U)
48097 #define V_CAUSE_PCMD_DDP_2(x) ((x) << S_CAUSE_PCMD_DDP_2)
48098 #define F_CAUSE_PCMD_DDP_2    V_CAUSE_PCMD_DDP_2(1U)
48101 #define V_CAUSE_PCMD_MPAR_2(x) ((x) << S_CAUSE_PCMD_MPAR_2)
48102 #define F_CAUSE_PCMD_MPAR_2    V_CAUSE_PCMD_MPAR_2(1U)
48105 #define V_CAUSE_PCMD_MPAC_2(x) ((x) << S_CAUSE_PCMD_MPAC_2)
48106 #define F_CAUSE_PCMD_MPAC_2    V_CAUSE_PCMD_MPAC_2(1U)
48109 #define V_CAUSE_PCMD_SFIFO_1(x) ((x) << S_CAUSE_PCMD_SFIFO_1)
48110 #define F_CAUSE_PCMD_SFIFO_1    V_CAUSE_PCMD_SFIFO_1(1U)
48113 #define V_CAUSE_PCMD_FIFO_1(x) ((x) << S_CAUSE_PCMD_FIFO_1)
48114 #define F_CAUSE_PCMD_FIFO_1    V_CAUSE_PCMD_FIFO_1(1U)
48117 #define V_CAUSE_PCMD_DDP_HINT_1(x) ((x) << S_CAUSE_PCMD_DDP_HINT_1)
48118 #define F_CAUSE_PCMD_DDP_HINT_1    V_CAUSE_PCMD_DDP_HINT_1(1U)
48121 #define V_CAUSE_PCMD_TPT_1(x) ((x) << S_CAUSE_PCMD_TPT_1)
48122 #define F_CAUSE_PCMD_TPT_1    V_CAUSE_PCMD_TPT_1(1U)
48125 #define V_CAUSE_PCMD_DDP_1(x) ((x) << S_CAUSE_PCMD_DDP_1)
48126 #define F_CAUSE_PCMD_DDP_1    V_CAUSE_PCMD_DDP_1(1U)
48129 #define V_CAUSE_PCMD_MPAR_1(x) ((x) << S_CAUSE_PCMD_MPAR_1)
48130 #define F_CAUSE_PCMD_MPAR_1    V_CAUSE_PCMD_MPAR_1(1U)
48133 #define V_CAUSE_PCMD_MPAC_1(x) ((x) << S_CAUSE_PCMD_MPAC_1)
48134 #define F_CAUSE_PCMD_MPAC_1    V_CAUSE_PCMD_MPAC_1(1U)
48137 #define V_CAUSE_PCMD_SFIFO_0(x) ((x) << S_CAUSE_PCMD_SFIFO_0)
48138 #define F_CAUSE_PCMD_SFIFO_0    V_CAUSE_PCMD_SFIFO_0(1U)
48141 #define V_CAUSE_PCMD_FIFO_0(x) ((x) << S_CAUSE_PCMD_FIFO_0)
48142 #define F_CAUSE_PCMD_FIFO_0    V_CAUSE_PCMD_FIFO_0(1U)
48145 #define V_CAUSE_PCMD_DDP_HINT_0(x) ((x) << S_CAUSE_PCMD_DDP_HINT_0)
48146 #define F_CAUSE_PCMD_DDP_HINT_0    V_CAUSE_PCMD_DDP_HINT_0(1U)
48149 #define V_CAUSE_PCMD_TPT_0(x) ((x) << S_CAUSE_PCMD_TPT_0)
48150 #define F_CAUSE_PCMD_TPT_0    V_CAUSE_PCMD_TPT_0(1U)
48153 #define V_CAUSE_PCMD_DDP_0(x) ((x) << S_CAUSE_PCMD_DDP_0)
48154 #define F_CAUSE_PCMD_DDP_0    V_CAUSE_PCMD_DDP_0(1U)
48156 #define S_CAUSE_PCMD_MPAR_0    1
48157 #define V_CAUSE_PCMD_MPAR_0(x) ((x) << S_CAUSE_PCMD_MPAR_0)
48158 #define F_CAUSE_PCMD_MPAR_0    V_CAUSE_PCMD_MPAR_0(1U)
48161 #define V_CAUSE_PCMD_MPAC_0(x) ((x) << S_CAUSE_PCMD_MPAC_0)
48162 #define F_CAUSE_PCMD_MPAC_0    V_CAUSE_PCMD_MPAC_0(1U)
48167 #define V_PERR_ENABLE_PCMD_SFIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_3)
48168 #define F_PERR_ENABLE_PCMD_SFIFO_3    V_PERR_ENABLE_PCMD_SFIFO_3(1U)
48171 #define V_PERR_ENABLE_PCMD_FIFO_3(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_3)
48172 #define F_PERR_ENABLE_PCMD_FIFO_3    V_PERR_ENABLE_PCMD_FIFO_3(1U)
48175 #define V_PERR_ENABLE_PCMD_DDP_HINT_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_3)
48176 #define F_PERR_ENABLE_PCMD_DDP_HINT_3    V_PERR_ENABLE_PCMD_DDP_HINT_3(1U)
48179 #define V_PERR_ENABLE_PCMD_TPT_3(x) ((x) << S_PERR_ENABLE_PCMD_TPT_3)
48180 #define F_PERR_ENABLE_PCMD_TPT_3    V_PERR_ENABLE_PCMD_TPT_3(1U)
48183 #define V_PERR_ENABLE_PCMD_DDP_3(x) ((x) << S_PERR_ENABLE_PCMD_DDP_3)
48184 #define F_PERR_ENABLE_PCMD_DDP_3    V_PERR_ENABLE_PCMD_DDP_3(1U)
48187 #define V_PERR_ENABLE_PCMD_MPAR_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_3)
48188 #define F_PERR_ENABLE_PCMD_MPAR_3    V_PERR_ENABLE_PCMD_MPAR_3(1U)
48191 #define V_PERR_ENABLE_PCMD_MPAC_3(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_3)
48192 #define F_PERR_ENABLE_PCMD_MPAC_3    V_PERR_ENABLE_PCMD_MPAC_3(1U)
48195 #define V_PERR_ENABLE_PCMD_SFIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_2)
48196 #define F_PERR_ENABLE_PCMD_SFIFO_2    V_PERR_ENABLE_PCMD_SFIFO_2(1U)
48199 #define V_PERR_ENABLE_PCMD_FIFO_2(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_2)
48200 #define F_PERR_ENABLE_PCMD_FIFO_2    V_PERR_ENABLE_PCMD_FIFO_2(1U)
48203 #define V_PERR_ENABLE_PCMD_DDP_HINT_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_2)
48204 #define F_PERR_ENABLE_PCMD_DDP_HINT_2    V_PERR_ENABLE_PCMD_DDP_HINT_2(1U)
48207 #define V_PERR_ENABLE_PCMD_TPT_2(x) ((x) << S_PERR_ENABLE_PCMD_TPT_2)
48208 #define F_PERR_ENABLE_PCMD_TPT_2    V_PERR_ENABLE_PCMD_TPT_2(1U)
48211 #define V_PERR_ENABLE_PCMD_DDP_2(x) ((x) << S_PERR_ENABLE_PCMD_DDP_2)
48212 #define F_PERR_ENABLE_PCMD_DDP_2    V_PERR_ENABLE_PCMD_DDP_2(1U)
48215 #define V_PERR_ENABLE_PCMD_MPAR_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_2)
48216 #define F_PERR_ENABLE_PCMD_MPAR_2    V_PERR_ENABLE_PCMD_MPAR_2(1U)
48219 #define V_PERR_ENABLE_PCMD_MPAC_2(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_2)
48220 #define F_PERR_ENABLE_PCMD_MPAC_2    V_PERR_ENABLE_PCMD_MPAC_2(1U)
48223 #define V_PERR_ENABLE_PCMD_SFIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_1)
48224 #define F_PERR_ENABLE_PCMD_SFIFO_1    V_PERR_ENABLE_PCMD_SFIFO_1(1U)
48227 #define V_PERR_ENABLE_PCMD_FIFO_1(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_1)
48228 #define F_PERR_ENABLE_PCMD_FIFO_1    V_PERR_ENABLE_PCMD_FIFO_1(1U)
48231 #define V_PERR_ENABLE_PCMD_DDP_HINT_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_1)
48232 #define F_PERR_ENABLE_PCMD_DDP_HINT_1    V_PERR_ENABLE_PCMD_DDP_HINT_1(1U)
48235 #define V_PERR_ENABLE_PCMD_TPT_1(x) ((x) << S_PERR_ENABLE_PCMD_TPT_1)
48236 #define F_PERR_ENABLE_PCMD_TPT_1    V_PERR_ENABLE_PCMD_TPT_1(1U)
48239 #define V_PERR_ENABLE_PCMD_DDP_1(x) ((x) << S_PERR_ENABLE_PCMD_DDP_1)
48240 #define F_PERR_ENABLE_PCMD_DDP_1    V_PERR_ENABLE_PCMD_DDP_1(1U)
48243 #define V_PERR_ENABLE_PCMD_MPAR_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_1)
48244 #define F_PERR_ENABLE_PCMD_MPAR_1    V_PERR_ENABLE_PCMD_MPAR_1(1U)
48247 #define V_PERR_ENABLE_PCMD_MPAC_1(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_1)
48248 #define F_PERR_ENABLE_PCMD_MPAC_1    V_PERR_ENABLE_PCMD_MPAC_1(1U)
48251 #define V_PERR_ENABLE_PCMD_SFIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_SFIFO_0)
48252 #define F_PERR_ENABLE_PCMD_SFIFO_0    V_PERR_ENABLE_PCMD_SFIFO_0(1U)
48255 #define V_PERR_ENABLE_PCMD_FIFO_0(x) ((x) << S_PERR_ENABLE_PCMD_FIFO_0)
48256 #define F_PERR_ENABLE_PCMD_FIFO_0    V_PERR_ENABLE_PCMD_FIFO_0(1U)
48259 #define V_PERR_ENABLE_PCMD_DDP_HINT_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_HINT_0)
48260 #define F_PERR_ENABLE_PCMD_DDP_HINT_0    V_PERR_ENABLE_PCMD_DDP_HINT_0(1U)
48263 #define V_PERR_ENABLE_PCMD_TPT_0(x) ((x) << S_PERR_ENABLE_PCMD_TPT_0)
48264 #define F_PERR_ENABLE_PCMD_TPT_0    V_PERR_ENABLE_PCMD_TPT_0(1U)
48267 #define V_PERR_ENABLE_PCMD_DDP_0(x) ((x) << S_PERR_ENABLE_PCMD_DDP_0)
48268 #define F_PERR_ENABLE_PCMD_DDP_0    V_PERR_ENABLE_PCMD_DDP_0(1U)
48270 #define S_PERR_ENABLE_PCMD_MPAR_0    1
48271 #define V_PERR_ENABLE_PCMD_MPAR_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAR_0)
48272 #define F_PERR_ENABLE_PCMD_MPAR_0    V_PERR_ENABLE_PCMD_MPAR_0(1U)
48275 #define V_PERR_ENABLE_PCMD_MPAC_0(x) ((x) << S_PERR_ENABLE_PCMD_MPAC_0)
48276 #define F_PERR_ENABLE_PCMD_MPAC_0    V_PERR_ENABLE_PCMD_MPAC_0(1U)
48281 #define V_ENABLE_DATA_SNOOP_3(x) ((x) << S_ENABLE_DATA_SNOOP_3)
48282 #define F_ENABLE_DATA_SNOOP_3    V_ENABLE_DATA_SNOOP_3(1U)
48285 #define V_ENABLE_DATA_SFIFO_3(x) ((x) << S_ENABLE_DATA_SFIFO_3)
48286 #define F_ENABLE_DATA_SFIFO_3    V_ENABLE_DATA_SFIFO_3(1U)
48289 #define V_ENABLE_DATA_FIFO_3(x) ((x) << S_ENABLE_DATA_FIFO_3)
48290 #define F_ENABLE_DATA_FIFO_3    V_ENABLE_DATA_FIFO_3(1U)
48293 #define V_ENABLE_DATA_DDP_3(x) ((x) << S_ENABLE_DATA_DDP_3)
48294 #define F_ENABLE_DATA_DDP_3    V_ENABLE_DATA_DDP_3(1U)
48297 #define V_ENABLE_DATA_CTX_3(x) ((x) << S_ENABLE_DATA_CTX_3)
48298 #define F_ENABLE_DATA_CTX_3    V_ENABLE_DATA_CTX_3(1U)
48301 #define V_ENABLE_DATA_PARSER_3(x) ((x) << S_ENABLE_DATA_PARSER_3)
48302 #define F_ENABLE_DATA_PARSER_3    V_ENABLE_DATA_PARSER_3(1U)
48305 #define V_ENABLE_DATA_SNOOP_2(x) ((x) << S_ENABLE_DATA_SNOOP_2)
48306 #define F_ENABLE_DATA_SNOOP_2    V_ENABLE_DATA_SNOOP_2(1U)
48309 #define V_ENABLE_DATA_SFIFO_2(x) ((x) << S_ENABLE_DATA_SFIFO_2)
48310 #define F_ENABLE_DATA_SFIFO_2    V_ENABLE_DATA_SFIFO_2(1U)
48313 #define V_ENABLE_DATA_FIFO_2(x) ((x) << S_ENABLE_DATA_FIFO_2)
48314 #define F_ENABLE_DATA_FIFO_2    V_ENABLE_DATA_FIFO_2(1U)
48317 #define V_ENABLE_DATA_DDP_2(x) ((x) << S_ENABLE_DATA_DDP_2)
48318 #define F_ENABLE_DATA_DDP_2    V_ENABLE_DATA_DDP_2(1U)
48321 #define V_ENABLE_DATA_CTX_2(x) ((x) << S_ENABLE_DATA_CTX_2)
48322 #define F_ENABLE_DATA_CTX_2    V_ENABLE_DATA_CTX_2(1U)
48325 #define V_ENABLE_DATA_PARSER_2(x) ((x) << S_ENABLE_DATA_PARSER_2)
48326 #define F_ENABLE_DATA_PARSER_2    V_ENABLE_DATA_PARSER_2(1U)
48329 #define V_ENABLE_DATA_SNOOP_1(x) ((x) << S_ENABLE_DATA_SNOOP_1)
48330 #define F_ENABLE_DATA_SNOOP_1    V_ENABLE_DATA_SNOOP_1(1U)
48333 #define V_ENABLE_DATA_SFIFO_1(x) ((x) << S_ENABLE_DATA_SFIFO_1)
48334 #define F_ENABLE_DATA_SFIFO_1    V_ENABLE_DATA_SFIFO_1(1U)
48337 #define V_ENABLE_DATA_FIFO_1(x) ((x) << S_ENABLE_DATA_FIFO_1)
48338 #define F_ENABLE_DATA_FIFO_1    V_ENABLE_DATA_FIFO_1(1U)
48341 #define V_ENABLE_DATA_DDP_1(x) ((x) << S_ENABLE_DATA_DDP_1)
48342 #define F_ENABLE_DATA_DDP_1    V_ENABLE_DATA_DDP_1(1U)
48345 #define V_ENABLE_DATA_CTX_1(x) ((x) << S_ENABLE_DATA_CTX_1)
48346 #define F_ENABLE_DATA_CTX_1    V_ENABLE_DATA_CTX_1(1U)
48349 #define V_ENABLE_DATA_PARSER_1(x) ((x) << S_ENABLE_DATA_PARSER_1)
48350 #define F_ENABLE_DATA_PARSER_1    V_ENABLE_DATA_PARSER_1(1U)
48353 #define V_ENABLE_DATA_SNOOP_0(x) ((x) << S_ENABLE_DATA_SNOOP_0)
48354 #define F_ENABLE_DATA_SNOOP_0    V_ENABLE_DATA_SNOOP_0(1U)
48357 #define V_ENABLE_DATA_SFIFO_0(x) ((x) << S_ENABLE_DATA_SFIFO_0)
48358 #define F_ENABLE_DATA_SFIFO_0    V_ENABLE_DATA_SFIFO_0(1U)
48361 #define V_ENABLE_DATA_FIFO_0(x) ((x) << S_ENABLE_DATA_FIFO_0)
48362 #define F_ENABLE_DATA_FIFO_0    V_ENABLE_DATA_FIFO_0(1U)
48365 #define V_ENABLE_DATA_DDP_0(x) ((x) << S_ENABLE_DATA_DDP_0)
48366 #define F_ENABLE_DATA_DDP_0    V_ENABLE_DATA_DDP_0(1U)
48368 #define S_ENABLE_DATA_CTX_0    1
48369 #define V_ENABLE_DATA_CTX_0(x) ((x) << S_ENABLE_DATA_CTX_0)
48370 #define F_ENABLE_DATA_CTX_0    V_ENABLE_DATA_CTX_0(1U)
48373 #define V_ENABLE_DATA_PARSER_0(x) ((x) << S_ENABLE_DATA_PARSER_0)
48374 #define F_ENABLE_DATA_PARSER_0    V_ENABLE_DATA_PARSER_0(1U)
48379 #define V_CAUSE_DATA_SNOOP_3(x) ((x) << S_CAUSE_DATA_SNOOP_3)
48380 #define F_CAUSE_DATA_SNOOP_3    V_CAUSE_DATA_SNOOP_3(1U)
48383 #define V_CAUSE_DATA_SFIFO_3(x) ((x) << S_CAUSE_DATA_SFIFO_3)
48384 #define F_CAUSE_DATA_SFIFO_3    V_CAUSE_DATA_SFIFO_3(1U)
48387 #define V_CAUSE_DATA_FIFO_3(x) ((x) << S_CAUSE_DATA_FIFO_3)
48388 #define F_CAUSE_DATA_FIFO_3    V_CAUSE_DATA_FIFO_3(1U)
48391 #define V_CAUSE_DATA_DDP_3(x) ((x) << S_CAUSE_DATA_DDP_3)
48392 #define F_CAUSE_DATA_DDP_3    V_CAUSE_DATA_DDP_3(1U)
48395 #define V_CAUSE_DATA_CTX_3(x) ((x) << S_CAUSE_DATA_CTX_3)
48396 #define F_CAUSE_DATA_CTX_3    V_CAUSE_DATA_CTX_3(1U)
48399 #define V_CAUSE_DATA_PARSER_3(x) ((x) << S_CAUSE_DATA_PARSER_3)
48400 #define F_CAUSE_DATA_PARSER_3    V_CAUSE_DATA_PARSER_3(1U)
48403 #define V_CAUSE_DATA_SNOOP_2(x) ((x) << S_CAUSE_DATA_SNOOP_2)
48404 #define F_CAUSE_DATA_SNOOP_2    V_CAUSE_DATA_SNOOP_2(1U)
48407 #define V_CAUSE_DATA_SFIFO_2(x) ((x) << S_CAUSE_DATA_SFIFO_2)
48408 #define F_CAUSE_DATA_SFIFO_2    V_CAUSE_DATA_SFIFO_2(1U)
48411 #define V_CAUSE_DATA_FIFO_2(x) ((x) << S_CAUSE_DATA_FIFO_2)
48412 #define F_CAUSE_DATA_FIFO_2    V_CAUSE_DATA_FIFO_2(1U)
48415 #define V_CAUSE_DATA_DDP_2(x) ((x) << S_CAUSE_DATA_DDP_2)
48416 #define F_CAUSE_DATA_DDP_2    V_CAUSE_DATA_DDP_2(1U)
48419 #define V_CAUSE_DATA_CTX_2(x) ((x) << S_CAUSE_DATA_CTX_2)
48420 #define F_CAUSE_DATA_CTX_2    V_CAUSE_DATA_CTX_2(1U)
48423 #define V_CAUSE_DATA_PARSER_2(x) ((x) << S_CAUSE_DATA_PARSER_2)
48424 #define F_CAUSE_DATA_PARSER_2    V_CAUSE_DATA_PARSER_2(1U)
48427 #define V_CAUSE_DATA_SNOOP_1(x) ((x) << S_CAUSE_DATA_SNOOP_1)
48428 #define F_CAUSE_DATA_SNOOP_1    V_CAUSE_DATA_SNOOP_1(1U)
48431 #define V_CAUSE_DATA_SFIFO_1(x) ((x) << S_CAUSE_DATA_SFIFO_1)
48432 #define F_CAUSE_DATA_SFIFO_1    V_CAUSE_DATA_SFIFO_1(1U)
48435 #define V_CAUSE_DATA_FIFO_1(x) ((x) << S_CAUSE_DATA_FIFO_1)
48436 #define F_CAUSE_DATA_FIFO_1    V_CAUSE_DATA_FIFO_1(1U)
48439 #define V_CAUSE_DATA_DDP_1(x) ((x) << S_CAUSE_DATA_DDP_1)
48440 #define F_CAUSE_DATA_DDP_1    V_CAUSE_DATA_DDP_1(1U)
48443 #define V_CAUSE_DATA_CTX_1(x) ((x) << S_CAUSE_DATA_CTX_1)
48444 #define F_CAUSE_DATA_CTX_1    V_CAUSE_DATA_CTX_1(1U)
48447 #define V_CAUSE_DATA_PARSER_1(x) ((x) << S_CAUSE_DATA_PARSER_1)
48448 #define F_CAUSE_DATA_PARSER_1    V_CAUSE_DATA_PARSER_1(1U)
48451 #define V_CAUSE_DATA_SNOOP_0(x) ((x) << S_CAUSE_DATA_SNOOP_0)
48452 #define F_CAUSE_DATA_SNOOP_0    V_CAUSE_DATA_SNOOP_0(1U)
48455 #define V_CAUSE_DATA_SFIFO_0(x) ((x) << S_CAUSE_DATA_SFIFO_0)
48456 #define F_CAUSE_DATA_SFIFO_0    V_CAUSE_DATA_SFIFO_0(1U)
48459 #define V_CAUSE_DATA_FIFO_0(x) ((x) << S_CAUSE_DATA_FIFO_0)
48460 #define F_CAUSE_DATA_FIFO_0    V_CAUSE_DATA_FIFO_0(1U)
48463 #define V_CAUSE_DATA_DDP_0(x) ((x) << S_CAUSE_DATA_DDP_0)
48464 #define F_CAUSE_DATA_DDP_0    V_CAUSE_DATA_DDP_0(1U)
48466 #define S_CAUSE_DATA_CTX_0    1
48467 #define V_CAUSE_DATA_CTX_0(x) ((x) << S_CAUSE_DATA_CTX_0)
48468 #define F_CAUSE_DATA_CTX_0    V_CAUSE_DATA_CTX_0(1U)
48471 #define V_CAUSE_DATA_PARSER_0(x) ((x) << S_CAUSE_DATA_PARSER_0)
48472 #define F_CAUSE_DATA_PARSER_0    V_CAUSE_DATA_PARSER_0(1U)
48477 #define V_PERR_ENABLE_DATA_SNOOP_3(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_3)
48478 #define F_PERR_ENABLE_DATA_SNOOP_3    V_PERR_ENABLE_DATA_SNOOP_3(1U)
48481 #define V_PERR_ENABLE_DATA_SFIFO_3(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_3)
48482 #define F_PERR_ENABLE_DATA_SFIFO_3    V_PERR_ENABLE_DATA_SFIFO_3(1U)
48485 #define V_PERR_ENABLE_DATA_FIFO_3(x) ((x) << S_PERR_ENABLE_DATA_FIFO_3)
48486 #define F_PERR_ENABLE_DATA_FIFO_3    V_PERR_ENABLE_DATA_FIFO_3(1U)
48489 #define V_PERR_ENABLE_DATA_DDP_3(x) ((x) << S_PERR_ENABLE_DATA_DDP_3)
48490 #define F_PERR_ENABLE_DATA_DDP_3    V_PERR_ENABLE_DATA_DDP_3(1U)
48493 #define V_PERR_ENABLE_DATA_CTX_3(x) ((x) << S_PERR_ENABLE_DATA_CTX_3)
48494 #define F_PERR_ENABLE_DATA_CTX_3    V_PERR_ENABLE_DATA_CTX_3(1U)
48497 #define V_PERR_ENABLE_DATA_PARSER_3(x) ((x) << S_PERR_ENABLE_DATA_PARSER_3)
48498 #define F_PERR_ENABLE_DATA_PARSER_3    V_PERR_ENABLE_DATA_PARSER_3(1U)
48501 #define V_PERR_ENABLE_DATA_SNOOP_2(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_2)
48502 #define F_PERR_ENABLE_DATA_SNOOP_2    V_PERR_ENABLE_DATA_SNOOP_2(1U)
48505 #define V_PERR_ENABLE_DATA_SFIFO_2(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_2)
48506 #define F_PERR_ENABLE_DATA_SFIFO_2    V_PERR_ENABLE_DATA_SFIFO_2(1U)
48509 #define V_PERR_ENABLE_DATA_FIFO_2(x) ((x) << S_PERR_ENABLE_DATA_FIFO_2)
48510 #define F_PERR_ENABLE_DATA_FIFO_2    V_PERR_ENABLE_DATA_FIFO_2(1U)
48513 #define V_PERR_ENABLE_DATA_DDP_2(x) ((x) << S_PERR_ENABLE_DATA_DDP_2)
48514 #define F_PERR_ENABLE_DATA_DDP_2    V_PERR_ENABLE_DATA_DDP_2(1U)
48517 #define V_PERR_ENABLE_DATA_CTX_2(x) ((x) << S_PERR_ENABLE_DATA_CTX_2)
48518 #define F_PERR_ENABLE_DATA_CTX_2    V_PERR_ENABLE_DATA_CTX_2(1U)
48521 #define V_PERR_ENABLE_DATA_PARSER_2(x) ((x) << S_PERR_ENABLE_DATA_PARSER_2)
48522 #define F_PERR_ENABLE_DATA_PARSER_2    V_PERR_ENABLE_DATA_PARSER_2(1U)
48525 #define V_PERR_ENABLE_DATA_SNOOP_1(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_1)
48526 #define F_PERR_ENABLE_DATA_SNOOP_1    V_PERR_ENABLE_DATA_SNOOP_1(1U)
48529 #define V_PERR_ENABLE_DATA_SFIFO_1(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_1)
48530 #define F_PERR_ENABLE_DATA_SFIFO_1    V_PERR_ENABLE_DATA_SFIFO_1(1U)
48533 #define V_PERR_ENABLE_DATA_FIFO_1(x) ((x) << S_PERR_ENABLE_DATA_FIFO_1)
48534 #define F_PERR_ENABLE_DATA_FIFO_1    V_PERR_ENABLE_DATA_FIFO_1(1U)
48537 #define V_PERR_ENABLE_DATA_DDP_1(x) ((x) << S_PERR_ENABLE_DATA_DDP_1)
48538 #define F_PERR_ENABLE_DATA_DDP_1    V_PERR_ENABLE_DATA_DDP_1(1U)
48541 #define V_PERR_ENABLE_DATA_CTX_1(x) ((x) << S_PERR_ENABLE_DATA_CTX_1)
48542 #define F_PERR_ENABLE_DATA_CTX_1    V_PERR_ENABLE_DATA_CTX_1(1U)
48545 #define V_PERR_ENABLE_DATA_PARSER_1(x) ((x) << S_PERR_ENABLE_DATA_PARSER_1)
48546 #define F_PERR_ENABLE_DATA_PARSER_1    V_PERR_ENABLE_DATA_PARSER_1(1U)
48549 #define V_PERR_ENABLE_DATA_SNOOP_0(x) ((x) << S_PERR_ENABLE_DATA_SNOOP_0)
48550 #define F_PERR_ENABLE_DATA_SNOOP_0    V_PERR_ENABLE_DATA_SNOOP_0(1U)
48553 #define V_PERR_ENABLE_DATA_SFIFO_0(x) ((x) << S_PERR_ENABLE_DATA_SFIFO_0)
48554 #define F_PERR_ENABLE_DATA_SFIFO_0    V_PERR_ENABLE_DATA_SFIFO_0(1U)
48557 #define V_PERR_ENABLE_DATA_FIFO_0(x) ((x) << S_PERR_ENABLE_DATA_FIFO_0)
48558 #define F_PERR_ENABLE_DATA_FIFO_0    V_PERR_ENABLE_DATA_FIFO_0(1U)
48561 #define V_PERR_ENABLE_DATA_DDP_0(x) ((x) << S_PERR_ENABLE_DATA_DDP_0)
48562 #define F_PERR_ENABLE_DATA_DDP_0    V_PERR_ENABLE_DATA_DDP_0(1U)
48564 #define S_PERR_ENABLE_DATA_CTX_0    1
48565 #define V_PERR_ENABLE_DATA_CTX_0(x) ((x) << S_PERR_ENABLE_DATA_CTX_0)
48566 #define F_PERR_ENABLE_DATA_CTX_0    V_PERR_ENABLE_DATA_CTX_0(1U)
48569 #define V_PERR_ENABLE_DATA_PARSER_0(x) ((x) << S_PERR_ENABLE_DATA_PARSER_0)
48570 #define F_PERR_ENABLE_DATA_PARSER_0    V_PERR_ENABLE_DATA_PARSER_0(1U)
48575 #define V_ENABLE_ARB_PBL_PF_3(x) ((x) << S_ENABLE_ARB_PBL_PF_3)
48576 #define F_ENABLE_ARB_PBL_PF_3    V_ENABLE_ARB_PBL_PF_3(1U)
48579 #define V_ENABLE_ARB_PF_3(x) ((x) << S_ENABLE_ARB_PF_3)
48580 #define F_ENABLE_ARB_PF_3    V_ENABLE_ARB_PF_3(1U)
48583 #define V_ENABLE_ARB_TPT_PF_3(x) ((x) << S_ENABLE_ARB_TPT_PF_3)
48584 #define F_ENABLE_ARB_TPT_PF_3    V_ENABLE_ARB_TPT_PF_3(1U)
48587 #define V_ENABLE_ARB_F_3(x) ((x) << S_ENABLE_ARB_F_3)
48588 #define F_ENABLE_ARB_F_3    V_ENABLE_ARB_F_3(1U)
48591 #define V_ENABLE_ARB_PBL_PF_2(x) ((x) << S_ENABLE_ARB_PBL_PF_2)
48592 #define F_ENABLE_ARB_PBL_PF_2    V_ENABLE_ARB_PBL_PF_2(1U)
48595 #define V_ENABLE_ARB_PF_2(x) ((x) << S_ENABLE_ARB_PF_2)
48596 #define F_ENABLE_ARB_PF_2    V_ENABLE_ARB_PF_2(1U)
48599 #define V_ENABLE_ARB_TPT_PF_2(x) ((x) << S_ENABLE_ARB_TPT_PF_2)
48600 #define F_ENABLE_ARB_TPT_PF_2    V_ENABLE_ARB_TPT_PF_2(1U)
48603 #define V_ENABLE_ARB_F_2(x) ((x) << S_ENABLE_ARB_F_2)
48604 #define F_ENABLE_ARB_F_2    V_ENABLE_ARB_F_2(1U)
48607 #define V_ENABLE_ARB_PBL_PF_1(x) ((x) << S_ENABLE_ARB_PBL_PF_1)
48608 #define F_ENABLE_ARB_PBL_PF_1    V_ENABLE_ARB_PBL_PF_1(1U)
48611 #define V_ENABLE_ARB_PF_1(x) ((x) << S_ENABLE_ARB_PF_1)
48612 #define F_ENABLE_ARB_PF_1    V_ENABLE_ARB_PF_1(1U)
48615 #define V_ENABLE_ARB_TPT_PF_1(x) ((x) << S_ENABLE_ARB_TPT_PF_1)
48616 #define F_ENABLE_ARB_TPT_PF_1    V_ENABLE_ARB_TPT_PF_1(1U)
48619 #define V_ENABLE_ARB_F_1(x) ((x) << S_ENABLE_ARB_F_1)
48620 #define F_ENABLE_ARB_F_1    V_ENABLE_ARB_F_1(1U)
48623 #define V_ENABLE_ARB_PBL_PF_0(x) ((x) << S_ENABLE_ARB_PBL_PF_0)
48624 #define F_ENABLE_ARB_PBL_PF_0    V_ENABLE_ARB_PBL_PF_0(1U)
48627 #define V_ENABLE_ARB_PF_0(x) ((x) << S_ENABLE_ARB_PF_0)
48628 #define F_ENABLE_ARB_PF_0    V_ENABLE_ARB_PF_0(1U)
48630 #define S_ENABLE_ARB_TPT_PF_0    1
48631 #define V_ENABLE_ARB_TPT_PF_0(x) ((x) << S_ENABLE_ARB_TPT_PF_0)
48632 #define F_ENABLE_ARB_TPT_PF_0    V_ENABLE_ARB_TPT_PF_0(1U)
48635 #define V_ENABLE_ARB_F_0(x) ((x) << S_ENABLE_ARB_F_0)
48636 #define F_ENABLE_ARB_F_0    V_ENABLE_ARB_F_0(1U)
48641 #define V_CAUSE_ARB_PBL_PF_3(x) ((x) << S_CAUSE_ARB_PBL_PF_3)
48642 #define F_CAUSE_ARB_PBL_PF_3    V_CAUSE_ARB_PBL_PF_3(1U)
48645 #define V_CAUSE_ARB_PF_3(x) ((x) << S_CAUSE_ARB_PF_3)
48646 #define F_CAUSE_ARB_PF_3    V_CAUSE_ARB_PF_3(1U)
48649 #define V_CAUSE_ARB_TPT_PF_3(x) ((x) << S_CAUSE_ARB_TPT_PF_3)
48650 #define F_CAUSE_ARB_TPT_PF_3    V_CAUSE_ARB_TPT_PF_3(1U)
48653 #define V_CAUSE_ARB_F_3(x) ((x) << S_CAUSE_ARB_F_3)
48654 #define F_CAUSE_ARB_F_3    V_CAUSE_ARB_F_3(1U)
48657 #define V_CAUSE_ARB_PBL_PF_2(x) ((x) << S_CAUSE_ARB_PBL_PF_2)
48658 #define F_CAUSE_ARB_PBL_PF_2    V_CAUSE_ARB_PBL_PF_2(1U)
48661 #define V_CAUSE_ARB_PF_2(x) ((x) << S_CAUSE_ARB_PF_2)
48662 #define F_CAUSE_ARB_PF_2    V_CAUSE_ARB_PF_2(1U)
48665 #define V_CAUSE_ARB_TPT_PF_2(x) ((x) << S_CAUSE_ARB_TPT_PF_2)
48666 #define F_CAUSE_ARB_TPT_PF_2    V_CAUSE_ARB_TPT_PF_2(1U)
48669 #define V_CAUSE_ARB_F_2(x) ((x) << S_CAUSE_ARB_F_2)
48670 #define F_CAUSE_ARB_F_2    V_CAUSE_ARB_F_2(1U)
48673 #define V_CAUSE_ARB_PBL_PF_1(x) ((x) << S_CAUSE_ARB_PBL_PF_1)
48674 #define F_CAUSE_ARB_PBL_PF_1    V_CAUSE_ARB_PBL_PF_1(1U)
48677 #define V_CAUSE_ARB_PF_1(x) ((x) << S_CAUSE_ARB_PF_1)
48678 #define F_CAUSE_ARB_PF_1    V_CAUSE_ARB_PF_1(1U)
48681 #define V_CAUSE_ARB_TPT_PF_1(x) ((x) << S_CAUSE_ARB_TPT_PF_1)
48682 #define F_CAUSE_ARB_TPT_PF_1    V_CAUSE_ARB_TPT_PF_1(1U)
48685 #define V_CAUSE_ARB_F_1(x) ((x) << S_CAUSE_ARB_F_1)
48686 #define F_CAUSE_ARB_F_1    V_CAUSE_ARB_F_1(1U)
48689 #define V_CAUSE_ARB_PBL_PF_0(x) ((x) << S_CAUSE_ARB_PBL_PF_0)
48690 #define F_CAUSE_ARB_PBL_PF_0    V_CAUSE_ARB_PBL_PF_0(1U)
48693 #define V_CAUSE_ARB_PF_0(x) ((x) << S_CAUSE_ARB_PF_0)
48694 #define F_CAUSE_ARB_PF_0    V_CAUSE_ARB_PF_0(1U)
48696 #define S_CAUSE_ARB_TPT_PF_0    1
48697 #define V_CAUSE_ARB_TPT_PF_0(x) ((x) << S_CAUSE_ARB_TPT_PF_0)
48698 #define F_CAUSE_ARB_TPT_PF_0    V_CAUSE_ARB_TPT_PF_0(1U)
48701 #define V_CAUSE_ARB_F_0(x) ((x) << S_CAUSE_ARB_F_0)
48702 #define F_CAUSE_ARB_F_0    V_CAUSE_ARB_F_0(1U)
48707 #define V_PERR_ENABLE_ARB_PBL_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_3)
48708 #define F_PERR_ENABLE_ARB_PBL_PF_3    V_PERR_ENABLE_ARB_PBL_PF_3(1U)
48711 #define V_PERR_ENABLE_ARB_PF_3(x) ((x) << S_PERR_ENABLE_ARB_PF_3)
48712 #define F_PERR_ENABLE_ARB_PF_3    V_PERR_ENABLE_ARB_PF_3(1U)
48715 #define V_PERR_ENABLE_ARB_TPT_PF_3(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_3)
48716 #define F_PERR_ENABLE_ARB_TPT_PF_3    V_PERR_ENABLE_ARB_TPT_PF_3(1U)
48719 #define V_PERR_ENABLE_ARB_F_3(x) ((x) << S_PERR_ENABLE_ARB_F_3)
48720 #define F_PERR_ENABLE_ARB_F_3    V_PERR_ENABLE_ARB_F_3(1U)
48723 #define V_PERR_ENABLE_ARB_PBL_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_2)
48724 #define F_PERR_ENABLE_ARB_PBL_PF_2    V_PERR_ENABLE_ARB_PBL_PF_2(1U)
48727 #define V_PERR_ENABLE_ARB_PF_2(x) ((x) << S_PERR_ENABLE_ARB_PF_2)
48728 #define F_PERR_ENABLE_ARB_PF_2    V_PERR_ENABLE_ARB_PF_2(1U)
48731 #define V_PERR_ENABLE_ARB_TPT_PF_2(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_2)
48732 #define F_PERR_ENABLE_ARB_TPT_PF_2    V_PERR_ENABLE_ARB_TPT_PF_2(1U)
48735 #define V_PERR_ENABLE_ARB_F_2(x) ((x) << S_PERR_ENABLE_ARB_F_2)
48736 #define F_PERR_ENABLE_ARB_F_2    V_PERR_ENABLE_ARB_F_2(1U)
48739 #define V_PERR_ENABLE_ARB_PBL_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_1)
48740 #define F_PERR_ENABLE_ARB_PBL_PF_1    V_PERR_ENABLE_ARB_PBL_PF_1(1U)
48743 #define V_PERR_ENABLE_ARB_PF_1(x) ((x) << S_PERR_ENABLE_ARB_PF_1)
48744 #define F_PERR_ENABLE_ARB_PF_1    V_PERR_ENABLE_ARB_PF_1(1U)
48747 #define V_PERR_ENABLE_ARB_TPT_PF_1(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_1)
48748 #define F_PERR_ENABLE_ARB_TPT_PF_1    V_PERR_ENABLE_ARB_TPT_PF_1(1U)
48751 #define V_PERR_ENABLE_ARB_F_1(x) ((x) << S_PERR_ENABLE_ARB_F_1)
48752 #define F_PERR_ENABLE_ARB_F_1    V_PERR_ENABLE_ARB_F_1(1U)
48755 #define V_PERR_ENABLE_ARB_PBL_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PBL_PF_0)
48756 #define F_PERR_ENABLE_ARB_PBL_PF_0    V_PERR_ENABLE_ARB_PBL_PF_0(1U)
48759 #define V_PERR_ENABLE_ARB_PF_0(x) ((x) << S_PERR_ENABLE_ARB_PF_0)
48760 #define F_PERR_ENABLE_ARB_PF_0    V_PERR_ENABLE_ARB_PF_0(1U)
48762 #define S_PERR_ENABLE_ARB_TPT_PF_0    1
48763 #define V_PERR_ENABLE_ARB_TPT_PF_0(x) ((x) << S_PERR_ENABLE_ARB_TPT_PF_0)
48764 #define F_PERR_ENABLE_ARB_TPT_PF_0    V_PERR_ENABLE_ARB_TPT_PF_0(1U)
48767 #define V_PERR_ENABLE_ARB_F_0(x) ((x) << S_PERR_ENABLE_ARB_F_0)
48768 #define F_PERR_ENABLE_ARB_F_0    V_PERR_ENABLE_ARB_F_0(1U)
48773 #define V_ISCSI_CTL2(x) ((x) << S_ISCSI_CTL2)
48774 #define F_ISCSI_CTL2    V_ISCSI_CTL2(1U)
48777 #define V_ISCSI_CTL1(x) ((x) << S_ISCSI_CTL1)
48778 #define F_ISCSI_CTL1    V_ISCSI_CTL1(1U)
48781 #define V_ISCSI_CTL0(x) ((x) << S_ISCSI_CTL0)
48782 #define F_ISCSI_CTL0    V_ISCSI_CTL0(1U)
48786 #define V_NVME_TCP_DATA_ALIGNMENT(x) ((x) << S_NVME_TCP_DATA_ALIGNMENT)
48787 #define G_NVME_TCP_DATA_ALIGNMENT(x) (((x) >> S_NVME_TCP_DATA_ALIGNMENT) & M_NVME_TCP_DATA_ALIGNMENT)
48791 #define V_NVME_TCP_INVLD_MSG_DIS(x) ((x) << S_NVME_TCP_INVLD_MSG_DIS)
48792 #define G_NVME_TCP_INVLD_MSG_DIS(x) (((x) >> S_NVME_TCP_INVLD_MSG_DIS) & M_NVME_TCP_INVLD_MSG_DIS)
48795 #define V_NVME_TCP_DDP_PDU_CHK_TYPE(x) ((x) << S_NVME_TCP_DDP_PDU_CHK_TYPE)
48796 #define F_NVME_TCP_DDP_PDU_CHK_TYPE    V_NVME_TCP_DDP_PDU_CHK_TYPE(1U)
48799 #define V_T10_CONFIG_ENB(x) ((x) << S_T10_CONFIG_ENB)
48800 #define F_T10_CONFIG_ENB    V_T10_CONFIG_ENB(1U)
48804 #define V_NVME_TCP_COLOUR_ENB(x) ((x) << S_NVME_TCP_COLOUR_ENB)
48805 #define G_NVME_TCP_COLOUR_ENB(x) (((x) >> S_NVME_TCP_COLOUR_ENB) & M_NVME_TCP_COLOUR_ENB)
48808 #define V_ROCE_SEND_RQE(x) ((x) << S_ROCE_SEND_RQE)
48809 #define F_ROCE_SEND_RQE    V_ROCE_SEND_RQE(1U)
48813 #define V_RDMA_INVLD_MSG_DIS(x) ((x) << S_RDMA_INVLD_MSG_DIS)
48814 #define G_RDMA_INVLD_MSG_DIS(x) (((x) >> S_RDMA_INVLD_MSG_DIS) & M_RDMA_INVLD_MSG_DIS)
48818 #define V_ROCE_INVLD_MSG_DIS(x) ((x) << S_ROCE_INVLD_MSG_DIS)
48819 #define G_ROCE_INVLD_MSG_DIS(x) (((x) >> S_ROCE_INVLD_MSG_DIS) & M_ROCE_INVLD_MSG_DIS)
48823 #define V_T7_MEM_ADDR_CTRL(x) ((x) << S_T7_MEM_ADDR_CTRL)
48824 #define G_T7_MEM_ADDR_CTRL(x) (((x) >> S_T7_MEM_ADDR_CTRL) & M_T7_MEM_ADDR_CTRL)
48826 #define S_ENB_32K_PDU    1
48827 #define V_ENB_32K_PDU(x) ((x) << S_ENB_32K_PDU)
48828 #define F_ENB_32K_PDU    V_ENB_32K_PDU(1U)
48831 #define V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(x) ((x) << S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS)
48832 #define F_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    V_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS(1U)
48838 #define V_TLS_RX_REG_OFF_ADDR(x) ((x) << S_TLS_RX_REG_OFF_ADDR)
48839 #define G_TLS_RX_REG_OFF_ADDR(x) (((x) >> S_TLS_RX_REG_OFF_ADDR) & M_TLS_RX_REG_OFF_ADDR)
48852 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
48853 #define F_SF_LOCK    V_SF_LOCK(1U)
48856 #define V_CONT(x) ((x) << S_CONT)
48857 #define F_CONT    V_CONT(1U)
48859 #define S_BYTECNT    1
48861 #define V_BYTECNT(x) ((x) << S_BYTECNT)
48862 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
48865 #define V_EN32BADDR(x) ((x) << S_EN32BADDR)
48866 #define F_EN32BADDR    V_EN32BADDR(1U)
48868 #define S_NUM_OF_BYTES    1
48870 #define V_NUM_OF_BYTES(x) ((x) << S_NUM_OF_BYTES)
48871 #define G_NUM_OF_BYTES(x) (((x) >> S_NUM_OF_BYTES) & M_NUM_OF_BYTES)
48874 #define V_QUADREADDISABLE(x) ((x) << S_QUADREADDISABLE)
48875 #define F_QUADREADDISABLE    V_QUADREADDISABLE(1U)
48878 #define V_EXIT4B(x) ((x) << S_EXIT4B)
48879 #define F_EXIT4B    V_EXIT4B(1U)
48882 #define V_ENTER4B(x) ((x) << S_ENTER4B)
48883 #define F_ENTER4B    V_ENTER4B(1U)
48886 #define V_QUADWRENABLE(x) ((x) << S_QUADWRENABLE)
48887 #define F_QUADWRENABLE    V_QUADWRENABLE(1U)
48890 #define V_REGDBG_SEL(x) ((x) << S_REGDBG_SEL)
48891 #define F_REGDBG_SEL    V_REGDBG_SEL(1U)
48894 #define V_REGDBG_MODE(x) ((x) << S_REGDBG_MODE)
48895 #define F_REGDBG_MODE    V_REGDBG_MODE(1U)
48904 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
48905 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
48909 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
48910 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
48914 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
48915 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
48918 #define V_ISVF(x) ((x) << S_ISVF)
48919 #define F_ISVF    V_ISVF(1U)
48923 #define V_VFID(x) ((x) << S_VFID)
48924 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
48928 #define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
48929 #define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
48932 #define V_T6_ISVF(x) ((x) << S_T6_ISVF)
48933 #define F_T6_ISVF    V_T6_ISVF(1U)
48937 #define V_T6_VFID(x) ((x) << S_T6_VFID)
48938 #define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
48944 #define V_CHIPID(x) ((x) << S_CHIPID)
48945 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
48951 #define V_PFSW(x) ((x) << S_PFSW)
48952 #define F_PFSW    V_PFSW(1U)
48955 #define V_PFSGE(x) ((x) << S_PFSGE)
48956 #define F_PFSGE    V_PFSGE(1U)
48958 #define S_PFCIM    1
48959 #define V_PFCIM(x) ((x) << S_PFCIM)
48960 #define F_PFCIM    V_PFCIM(1U)
48963 #define V_PFMPS(x) ((x) << S_PFMPS)
48964 #define F_PFMPS    V_PFMPS(1U)
48970 #define V_SWINT(x) ((x) << S_SWINT)
48971 #define F_SWINT    V_SWINT(1U)
48977 #define V_UART(x) ((x) << S_UART)
48978 #define F_UART    V_UART(1U)
48981 #define V_ULP_TX(x) ((x) << S_ULP_TX)
48982 #define F_ULP_TX    V_ULP_TX(1U)
48985 #define V_SGE(x) ((x) << S_SGE)
48986 #define F_SGE    V_SGE(1U)
48989 #define V_HMA(x) ((x) << S_HMA)
48990 #define F_HMA    V_HMA(1U)
48993 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
48994 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
48997 #define V_ULP_RX(x) ((x) << S_ULP_RX)
48998 #define F_ULP_RX    V_ULP_RX(1U)
49001 #define V_PM_RX(x) ((x) << S_PM_RX)
49002 #define F_PM_RX    V_PM_RX(1U)
49005 #define V_PM_TX(x) ((x) << S_PM_TX)
49006 #define F_PM_TX    V_PM_TX(1U)
49009 #define V_MA(x) ((x) << S_MA)
49010 #define F_MA    V_MA(1U)
49013 #define V_TP(x) ((x) << S_TP)
49014 #define F_TP    V_TP(1U)
49017 #define V_LE(x) ((x) << S_LE)
49018 #define F_LE    V_LE(1U)
49021 #define V_EDC1(x) ((x) << S_EDC1)
49022 #define F_EDC1    V_EDC1(1U)
49025 #define V_EDC0(x) ((x) << S_EDC0)
49026 #define F_EDC0    V_EDC0(1U)
49029 #define V_MC(x) ((x) << S_MC)
49030 #define F_MC    V_MC(1U)
49033 #define V_PCIE(x) ((x) << S_PCIE)
49034 #define F_PCIE    V_PCIE(1U)
49037 #define V_PMU(x) ((x) << S_PMU)
49038 #define F_PMU    V_PMU(1U)
49041 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
49042 #define F_XGMAC_KR1    V_XGMAC_KR1(1U)
49045 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
49046 #define F_XGMAC_KR0    V_XGMAC_KR0(1U)
49049 #define V_XGMAC1(x) ((x) << S_XGMAC1)
49050 #define F_XGMAC1    V_XGMAC1(1U)
49053 #define V_XGMAC0(x) ((x) << S_XGMAC0)
49054 #define F_XGMAC0    V_XGMAC0(1U)
49057 #define V_SMB(x) ((x) << S_SMB)
49058 #define F_SMB    V_SMB(1U)
49061 #define V_SF(x) ((x) << S_SF)
49062 #define F_SF    V_SF(1U)
49065 #define V_PL(x) ((x) << S_PL)
49066 #define F_PL    V_PL(1U)
49069 #define V_NCSI(x) ((x) << S_NCSI)
49070 #define F_NCSI    V_NCSI(1U)
49073 #define V_MPS(x) ((x) << S_MPS)
49074 #define F_MPS    V_MPS(1U)
49077 #define V_MI(x) ((x) << S_MI)
49078 #define F_MI    V_MI(1U)
49081 #define V_DBG(x) ((x) << S_DBG)
49082 #define F_DBG    V_DBG(1U)
49084 #define S_I2CM    1
49085 #define V_I2CM(x) ((x) << S_I2CM)
49086 #define F_I2CM    V_I2CM(1U)
49089 #define V_CIM(x) ((x) << S_CIM)
49090 #define F_CIM    V_CIM(1U)
49093 #define V_MC1(x) ((x) << S_MC1)
49094 #define F_MC1    V_MC1(1U)
49097 #define V_MC0(x) ((x) << S_MC0)
49098 #define F_MC0    V_MC0(1U)
49101 #define V_ANYMAC(x) ((x) << S_ANYMAC)
49102 #define F_ANYMAC    V_ANYMAC(1U)
49105 #define V_T7_PL_PERR_CRYPTO_KEY(x) ((x) << S_T7_PL_PERR_CRYPTO_KEY)
49106 #define F_T7_PL_PERR_CRYPTO_KEY    V_T7_PL_PERR_CRYPTO_KEY(1U)
49109 #define V_T7_PL_PERR_CRYPTO1(x) ((x) << S_T7_PL_PERR_CRYPTO1)
49110 #define F_T7_PL_PERR_CRYPTO1    V_T7_PL_PERR_CRYPTO1(1U)
49113 #define V_T7_PL_PERR_CRYPTO0(x) ((x) << S_T7_PL_PERR_CRYPTO0)
49114 #define F_T7_PL_PERR_CRYPTO0    V_T7_PL_PERR_CRYPTO0(1U)
49117 #define V_T7_PL_PERR_GCACHE(x) ((x) << S_T7_PL_PERR_GCACHE)
49118 #define F_T7_PL_PERR_GCACHE    V_T7_PL_PERR_GCACHE(1U)
49121 #define V_T7_PL_PERR_ARM(x) ((x) << S_T7_PL_PERR_ARM)
49122 #define F_T7_PL_PERR_ARM    V_T7_PL_PERR_ARM(1U)
49125 #define V_T7_PL_PERR_ULP_TX(x) ((x) << S_T7_PL_PERR_ULP_TX)
49126 #define F_T7_PL_PERR_ULP_TX    V_T7_PL_PERR_ULP_TX(1U)
49129 #define V_T7_PL_PERR_SGE(x) ((x) << S_T7_PL_PERR_SGE)
49130 #define F_T7_PL_PERR_SGE    V_T7_PL_PERR_SGE(1U)
49133 #define V_T7_PL_PERR_HMA(x) ((x) << S_T7_PL_PERR_HMA)
49134 #define F_T7_PL_PERR_HMA    V_T7_PL_PERR_HMA(1U)
49137 #define V_T7_PL_PERR_CPL_SWITCH(x) ((x) << S_T7_PL_PERR_CPL_SWITCH)
49138 #define F_T7_PL_PERR_CPL_SWITCH    V_T7_PL_PERR_CPL_SWITCH(1U)
49141 #define V_T7_PL_PERR_ULP_RX(x) ((x) << S_T7_PL_PERR_ULP_RX)
49142 #define F_T7_PL_PERR_ULP_RX    V_T7_PL_PERR_ULP_RX(1U)
49145 #define V_T7_PL_PERR_PM_RX(x) ((x) << S_T7_PL_PERR_PM_RX)
49146 #define F_T7_PL_PERR_PM_RX    V_T7_PL_PERR_PM_RX(1U)
49149 #define V_T7_PL_PERR_PM_TX(x) ((x) << S_T7_PL_PERR_PM_TX)
49150 #define F_T7_PL_PERR_PM_TX    V_T7_PL_PERR_PM_TX(1U)
49153 #define V_T7_PL_PERR_MA(x) ((x) << S_T7_PL_PERR_MA)
49154 #define F_T7_PL_PERR_MA    V_T7_PL_PERR_MA(1U)
49157 #define V_T7_PL_PERR_TP(x) ((x) << S_T7_PL_PERR_TP)
49158 #define F_T7_PL_PERR_TP    V_T7_PL_PERR_TP(1U)
49161 #define V_T7_PL_PERR_LE(x) ((x) << S_T7_PL_PERR_LE)
49162 #define F_T7_PL_PERR_LE    V_T7_PL_PERR_LE(1U)
49165 #define V_T7_PL_PERR_EDC1(x) ((x) << S_T7_PL_PERR_EDC1)
49166 #define F_T7_PL_PERR_EDC1    V_T7_PL_PERR_EDC1(1U)
49169 #define V_T7_PL_PERR_EDC0(x) ((x) << S_T7_PL_PERR_EDC0)
49170 #define F_T7_PL_PERR_EDC0    V_T7_PL_PERR_EDC0(1U)
49173 #define V_T7_PL_PERR_MC1(x) ((x) << S_T7_PL_PERR_MC1)
49174 #define F_T7_PL_PERR_MC1    V_T7_PL_PERR_MC1(1U)
49177 #define V_T7_PL_PERR_MC0(x) ((x) << S_T7_PL_PERR_MC0)
49178 #define F_T7_PL_PERR_MC0    V_T7_PL_PERR_MC0(1U)
49181 #define V_T7_PL_PERR_PCIE(x) ((x) << S_T7_PL_PERR_PCIE)
49182 #define F_T7_PL_PERR_PCIE    V_T7_PL_PERR_PCIE(1U)
49185 #define V_T7_PL_PERR_UART(x) ((x) << S_T7_PL_PERR_UART)
49186 #define F_T7_PL_PERR_UART    V_T7_PL_PERR_UART(1U)
49189 #define V_T7_PL_PERR_PMU(x) ((x) << S_T7_PL_PERR_PMU)
49190 #define F_T7_PL_PERR_PMU    V_T7_PL_PERR_PMU(1U)
49193 #define V_T7_PL_PERR_MAC(x) ((x) << S_T7_PL_PERR_MAC)
49194 #define F_T7_PL_PERR_MAC    V_T7_PL_PERR_MAC(1U)
49197 #define V_T7_PL_PERR_SMB(x) ((x) << S_T7_PL_PERR_SMB)
49198 #define F_T7_PL_PERR_SMB    V_T7_PL_PERR_SMB(1U)
49201 #define V_T7_PL_PERR_SF(x) ((x) << S_T7_PL_PERR_SF)
49202 #define F_T7_PL_PERR_SF    V_T7_PL_PERR_SF(1U)
49205 #define V_T7_PL_PERR_PL(x) ((x) << S_T7_PL_PERR_PL)
49206 #define F_T7_PL_PERR_PL    V_T7_PL_PERR_PL(1U)
49209 #define V_T7_PL_PERR_NCSI(x) ((x) << S_T7_PL_PERR_NCSI)
49210 #define F_T7_PL_PERR_NCSI    V_T7_PL_PERR_NCSI(1U)
49213 #define V_T7_PL_PERR_MPS(x) ((x) << S_T7_PL_PERR_MPS)
49214 #define F_T7_PL_PERR_MPS    V_T7_PL_PERR_MPS(1U)
49217 #define V_T7_PL_PERR_MI(x) ((x) << S_T7_PL_PERR_MI)
49218 #define F_T7_PL_PERR_MI    V_T7_PL_PERR_MI(1U)
49221 #define V_T7_PL_PERR_DBG(x) ((x) << S_T7_PL_PERR_DBG)
49222 #define F_T7_PL_PERR_DBG    V_T7_PL_PERR_DBG(1U)
49224 #define S_T7_PL_PERR_I2CM    1
49225 #define V_T7_PL_PERR_I2CM(x) ((x) << S_T7_PL_PERR_I2CM)
49226 #define F_T7_PL_PERR_I2CM    V_T7_PL_PERR_I2CM(1U)
49229 #define V_T7_PL_PERR_CIM(x) ((x) << S_T7_PL_PERR_CIM)
49230 #define F_T7_PL_PERR_CIM    V_T7_PL_PERR_CIM(1U)
49236 #define V_FLR(x) ((x) << S_FLR)
49237 #define F_FLR    V_FLR(1U)
49240 #define V_SW_CIM(x) ((x) << S_SW_CIM)
49241 #define F_SW_CIM    V_SW_CIM(1U)
49244 #define V_MAC3(x) ((x) << S_MAC3)
49245 #define F_MAC3    V_MAC3(1U)
49248 #define V_MAC2(x) ((x) << S_MAC2)
49249 #define F_MAC2    V_MAC2(1U)
49252 #define V_MAC1(x) ((x) << S_MAC1)
49253 #define F_MAC1    V_MAC1(1U)
49256 #define V_MAC0(x) ((x) << S_MAC0)
49257 #define F_MAC0    V_MAC0(1U)
49260 #define V_T7_FLR(x) ((x) << S_T7_FLR)
49261 #define F_T7_FLR    V_T7_FLR(1U)
49264 #define V_T7_SW_CIM(x) ((x) << S_T7_SW_CIM)
49265 #define F_T7_SW_CIM    V_T7_SW_CIM(1U)
49268 #define V_T7_ULP_TX(x) ((x) << S_T7_ULP_TX)
49269 #define F_T7_ULP_TX    V_T7_ULP_TX(1U)
49272 #define V_T7_SGE(x) ((x) << S_T7_SGE)
49273 #define F_T7_SGE    V_T7_SGE(1U)
49276 #define V_T7_HMA(x) ((x) << S_T7_HMA)
49277 #define F_T7_HMA    V_T7_HMA(1U)
49280 #define V_T7_CPL_SWITCH(x) ((x) << S_T7_CPL_SWITCH)
49281 #define F_T7_CPL_SWITCH    V_T7_CPL_SWITCH(1U)
49284 #define V_T7_ULP_RX(x) ((x) << S_T7_ULP_RX)
49285 #define F_T7_ULP_RX    V_T7_ULP_RX(1U)
49288 #define V_T7_PM_RX(x) ((x) << S_T7_PM_RX)
49289 #define F_T7_PM_RX    V_T7_PM_RX(1U)
49292 #define V_T7_PM_TX(x) ((x) << S_T7_PM_TX)
49293 #define F_T7_PM_TX    V_T7_PM_TX(1U)
49296 #define V_T7_MA(x) ((x) << S_T7_MA)
49297 #define F_T7_MA    V_T7_MA(1U)
49300 #define V_T7_TP(x) ((x) << S_T7_TP)
49301 #define F_T7_TP    V_T7_TP(1U)
49304 #define V_T7_LE(x) ((x) << S_T7_LE)
49305 #define F_T7_LE    V_T7_LE(1U)
49308 #define V_T7_EDC1(x) ((x) << S_T7_EDC1)
49309 #define F_T7_EDC1    V_T7_EDC1(1U)
49312 #define V_T7_EDC0(x) ((x) << S_T7_EDC0)
49313 #define F_T7_EDC0    V_T7_EDC0(1U)
49316 #define V_T7_MC1(x) ((x) << S_T7_MC1)
49317 #define F_T7_MC1    V_T7_MC1(1U)
49320 #define V_T7_MC0(x) ((x) << S_T7_MC0)
49321 #define F_T7_MC0    V_T7_MC0(1U)
49324 #define V_T7_PCIE(x) ((x) << S_T7_PCIE)
49325 #define F_T7_PCIE    V_T7_PCIE(1U)
49328 #define V_T7_UART(x) ((x) << S_T7_UART)
49329 #define F_T7_UART    V_T7_UART(1U)
49336 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
49337 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
49341 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
49342 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
49348 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
49349 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
49353 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
49354 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
49358 #define V_MAPMAC1(x) ((x) << S_MAPMAC1)
49359 #define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
49363 #define V_MAPMAC0(x) ((x) << S_MAPMAC0)
49364 #define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
49370 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
49371 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
49375 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
49376 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
49380 #define V_MAPMAC3(x) ((x) << S_MAPMAC3)
49381 #define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
49385 #define V_MAPMAC2(x) ((x) << S_MAPMAC2)
49386 #define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
49392 #define V_MAPMI(x) ((x) << S_MAPMI)
49393 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
49397 #define V_MAPSMB(x) ((x) << S_MAPSMB)
49398 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
49404 #define V_MAPDBG(x) ((x) << S_MAPDBG)
49405 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
49409 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
49410 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
49415 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
49416 #define F_FATALPERREN    V_FATALPERREN(1U)
49419 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
49420 #define F_SWINTCIM    V_SWINTCIM(1U)
49422 #define S_PIORST    1
49423 #define V_PIORST(x) ((x) << S_PIORST)
49424 #define F_PIORST    V_PIORST(1U)
49427 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
49428 #define F_PIORSTMODE    V_PIORSTMODE(1U)
49431 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
49432 #define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)
49436 #define S_PL_MEMSEL    1
49437 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
49438 #define F_PL_MEMSEL    V_PL_MEMSEL(1U)
49443 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
49444 #define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)
49447 #define V_FATALPERR(x) ((x) << S_FATALPERR)
49448 #define F_FATALPERR    V_FATALPERR(1U)
49451 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
49452 #define F_INVALIDACCESS    V_INVALIDACCESS(1U)
49455 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
49456 #define F_TIMEOUT    V_TIMEOUT(1U)
49458 #define S_PLERR    1
49459 #define V_PLERR(x) ((x) << S_PLERR)
49460 #define F_PLERR    V_PLERR(1U)
49463 #define V_PERRVFID(x) ((x) << S_PERRVFID)
49464 #define F_PERRVFID    V_PERRVFID(1U)
49467 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
49468 #define F_PL_BUSPERR    V_PL_BUSPERR(1U)
49476 #define V_REV(x) ((x) << S_REV)
49477 #define G_REV(x) (((x) >> S_REV) & M_REV)
49483 #define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
49484 #define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
49488 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
49489 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
49493 #define V_T5_STATECFGINITF(x) ((x) << S_T5_STATECFGINITF)
49494 #define G_T5_STATECFGINITF(x) (((x) >> S_T5_STATECFGINITF) & M_T5_STATECFGINITF)
49498 #define V_T5_STATECFGINIT(x) ((x) << S_T5_STATECFGINIT)
49499 #define G_T5_STATECFGINIT(x) (((x) >> S_T5_STATECFGINIT) & M_T5_STATECFGINIT)
49503 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
49504 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
49507 #define V_T5_PERSTTIMEOUT(x) ((x) << S_T5_PERSTTIMEOUT)
49508 #define F_T5_PERSTTIMEOUT    V_T5_PERSTTIMEOUT(1U)
49511 #define V_T5_LTSSMENABLE(x) ((x) << S_T5_LTSSMENABLE)
49512 #define F_T5_LTSSMENABLE    V_T5_LTSSMENABLE(1U)
49516 #define V_LTSSM(x) ((x) << S_LTSSM)
49517 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
49521 #define V_T6_LN0_AESTAT(x) ((x) << S_T6_LN0_AESTAT)
49522 #define G_T6_LN0_AESTAT(x) (((x) >> S_T6_LN0_AESTAT) & M_T6_LN0_AESTAT)
49526 #define V_T6_LN0_AECMD(x) ((x) << S_T6_LN0_AECMD)
49527 #define G_T6_LN0_AECMD(x) (((x) >> S_T6_LN0_AECMD) & M_T6_LN0_AECMD)
49531 #define V_T6_1_STATECFGINITF(x) ((x) << S_T6_1_STATECFGINITF)
49532 #define G_T6_1_STATECFGINITF(x) (((x) >> S_T6_1_STATECFGINITF) & M_T6_1_STATECFGINITF)
49535 #define V_PHY_STATUS(x) ((x) << S_PHY_STATUS)
49536 #define F_PHY_STATUS    V_PHY_STATUS(1U)
49540 #define V_SPEED_PL(x) ((x) << S_SPEED_PL)
49541 #define G_SPEED_PL(x) (((x) >> S_SPEED_PL) & M_SPEED_PL)
49544 #define V_PERSTTIMEOUT_PL(x) ((x) << S_PERSTTIMEOUT_PL)
49545 #define F_PERSTTIMEOUT_PL    V_PERSTTIMEOUT_PL(1U)
49548 #define V_SPEEDMS(x) ((x) << S_SPEEDMS)
49549 #define F_SPEEDMS    V_SPEEDMS(1U)
49555 #define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
49556 #define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
49560 #define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
49561 #define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
49567 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
49568 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
49571 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
49572 #define F_OWNEROVERRIDE    V_OWNEROVERRIDE(1U)
49576 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
49577 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
49582 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
49583 #define F_SEMLOCK    V_SEMLOCK(1U)
49587 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
49588 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
49592 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
49593 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
49599 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
49600 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
49606 #define V_MAP7(x) ((x) << S_MAP7)
49607 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
49611 #define V_MAP6(x) ((x) << S_MAP6)
49612 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
49616 #define V_MAP5(x) ((x) << S_MAP5)
49617 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
49621 #define V_MAP4(x) ((x) << S_MAP4)
49622 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
49626 #define V_MAP3(x) ((x) << S_MAP3)
49627 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
49631 #define V_MAP2(x) ((x) << S_MAP2)
49632 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
49636 #define V_MAP1(x) ((x) << S_MAP1)
49637 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
49641 #define V_MAP0(x) ((x) << S_MAP0)
49642 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
49647 #define V_CRYPTO_KEY(x) ((x) << S_CRYPTO_KEY)
49648 #define F_CRYPTO_KEY    V_CRYPTO_KEY(1U)
49651 #define V_CRYPTO1(x) ((x) << S_CRYPTO1)
49652 #define F_CRYPTO1    V_CRYPTO1(1U)
49655 #define V_CRYPTO0(x) ((x) << S_CRYPTO0)
49656 #define F_CRYPTO0    V_CRYPTO0(1U)
49658 #define S_GCACHE    1
49659 #define V_GCACHE(x) ((x) << S_GCACHE)
49660 #define F_GCACHE    V_GCACHE(1U)
49663 #define V_ARM(x) ((x) << S_ARM)
49664 #define F_ARM    V_ARM(1U)
49671 #define V_ER_ADDR(x) ((x) << S_ER_ADDR)
49672 #define G_ER_ADDR(x) (((x) >> S_ER_ADDR) & M_ER_ADDR)
49679 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
49680 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
49684 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
49685 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
49691 #define V_MODINDX(x) ((x) << S_MODINDX)
49692 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
49696 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
49697 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
49704 #define V_FLR_PF(x) ((x) << S_FLR_PF)
49705 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
49711 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
49712 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
49715 #define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
49716 #define F_PERRCAPTURE    V_PERRCAPTURE(1U)
49722 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
49723 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
49728 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
49729 #define F_PL_TOVALID    V_PL_TOVALID(1U)
49732 #define V_WRITE(x) ((x) << S_WRITE)
49733 #define F_WRITE    V_WRITE(1U)
49737 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
49738 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
49741 #define V_RGN(x) ((x) << S_RGN)
49742 #define F_RGN    V_RGN(1U)
49746 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
49747 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
49751 #define V_PL_TORID(x) ((x) << S_PL_TORID)
49752 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
49755 #define V_VALIDPERR(x) ((x) << S_VALIDPERR)
49756 #define F_VALIDPERR    V_VALIDPERR(1U)
49760 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
49761 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
49765 #define V_T6_PL_TOVFID(x) ((x) << S_T6_PL_TOVFID)
49766 #define G_T6_PL_TOVFID(x) (((x) >> S_T6_PL_TOVFID) & M_T6_PL_TOVFID)
49771 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
49772 #define F_VFID_VLD    V_VFID_VLD(1U)
49782 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
49783 #define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)
49786 #define V_HASHEN(x) ((x) << S_HASHEN)
49787 #define F_HASHEN    V_HASHEN(1U)
49790 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
49791 #define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)
49794 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
49795 #define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)
49798 #define V_BUILD(x) ((x) << S_BUILD)
49799 #define F_BUILD    V_BUILD(1U)
49802 #define V_FILTEREN(x) ((x) << S_FILTEREN)
49803 #define F_FILTEREN    V_FILTEREN(1U)
49807 #define V_SYNMODE(x) ((x) << S_SYNMODE)
49808 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
49811 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
49812 #define F_LEBUSEN    V_LEBUSEN(1U)
49815 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
49816 #define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)
49819 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
49820 #define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)
49823 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
49824 #define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)
49826 #define S_DELACTSYNOEN    1
49827 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
49828 #define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)
49831 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
49832 #define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)
49835 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
49836 #define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)
49839 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
49840 #define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)
49843 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
49844 #define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)
49847 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
49848 #define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)
49851 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
49852 #define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)
49855 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
49856 #define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)
49859 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
49860 #define F_POCLIPTID0    V_POCLIPTID0(1U)
49863 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
49864 #define F_TCAMARBOFF    V_TCAMARBOFF(1U)
49867 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
49868 #define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)
49871 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
49872 #define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)
49875 #define V_CRCHASH(x) ((x) << S_CRCHASH)
49876 #define F_CRCHASH    V_CRCHASH(1U)
49879 #define V_COMPTID(x) ((x) << S_COMPTID)
49880 #define F_COMPTID    V_COMPTID(1U)
49883 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
49884 #define F_SINGLETHREAD    V_SINGLETHREAD(1U)
49887 #define V_CHK_FUL_TUP_ZERO(x) ((x) << S_CHK_FUL_TUP_ZERO)
49888 #define F_CHK_FUL_TUP_ZERO    V_CHK_FUL_TUP_ZERO(1U)
49891 #define V_PRI_HASH(x) ((x) << S_PRI_HASH)
49892 #define F_PRI_HASH    V_PRI_HASH(1U)
49895 #define V_EXTN_HASH_IPV4(x) ((x) << S_EXTN_HASH_IPV4)
49896 #define F_EXTN_HASH_IPV4    V_EXTN_HASH_IPV4(1U)
49899 #define V_ASLIPCOMPEN_IPV4(x) ((x) << S_ASLIPCOMPEN_IPV4)
49900 #define F_ASLIPCOMPEN_IPV4    V_ASLIPCOMPEN_IPV4(1U)
49903 #define V_IGNR_TUP_ZERO(x) ((x) << S_IGNR_TUP_ZERO)
49904 #define F_IGNR_TUP_ZERO    V_IGNR_TUP_ZERO(1U)
49907 #define V_IGNR_LIP_ZERO(x) ((x) << S_IGNR_LIP_ZERO)
49908 #define F_IGNR_LIP_ZERO    V_IGNR_LIP_ZERO(1U)
49911 #define V_CLCAM_INIT_BUSY(x) ((x) << S_CLCAM_INIT_BUSY)
49912 #define F_CLCAM_INIT_BUSY    V_CLCAM_INIT_BUSY(1U)
49915 #define V_CLCAM_INIT(x) ((x) << S_CLCAM_INIT)
49916 #define F_CLCAM_INIT    V_CLCAM_INIT(1U)
49919 #define V_MTCAM_INIT_BUSY(x) ((x) << S_MTCAM_INIT_BUSY)
49920 #define F_MTCAM_INIT_BUSY    V_MTCAM_INIT_BUSY(1U)
49923 #define V_MTCAM_INIT(x) ((x) << S_MTCAM_INIT)
49924 #define F_MTCAM_INIT    V_MTCAM_INIT(1U)
49928 #define V_REGION_EN(x) ((x) << S_REGION_EN)
49929 #define G_REGION_EN(x) (((x) >> S_REGION_EN) & M_REGION_EN)
49932 #define V_CACHEBYPASS(x) ((x) << S_CACHEBYPASS)
49933 #define F_CACHEBYPASS    V_CACHEBYPASS(1U)
49939 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
49940 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
49943 #define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
49944 #define F_SRAMDEEPSLEEP_STAT    V_SRAMDEEPSLEEP_STAT(1U)
49947 #define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
49948 #define F_TCAMDEEPSLEEP1_STAT    V_TCAMDEEPSLEEP1_STAT(1U)
49951 #define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
49952 #define F_TCAMDEEPSLEEP0_STAT    V_TCAMDEEPSLEEP0_STAT(1U)
49955 #define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
49956 #define F_SRAMDEEPSLEEP    V_SRAMDEEPSLEEP(1U)
49959 #define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
49960 #define F_TCAMDEEPSLEEP1    V_TCAMDEEPSLEEP1(1U)
49963 #define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
49964 #define F_TCAMDEEPSLEEP0    V_TCAMDEEPSLEEP0(1U)
49967 #define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
49968 #define F_SRVRAMCLKOFF    V_SRVRAMCLKOFF(1U)
49971 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
49972 #define F_HASHCLKOFF    V_HASHCLKOFF(1U)
49977 #define V_TPDB_IF_PAUSE_ACK(x) ((x) << S_TPDB_IF_PAUSE_ACK)
49978 #define F_TPDB_IF_PAUSE_ACK    V_TPDB_IF_PAUSE_ACK(1U)
49981 #define V_TPDB_IF_PAUSE_REQ(x) ((x) << S_TPDB_IF_PAUSE_REQ)
49982 #define F_TPDB_IF_PAUSE_REQ    V_TPDB_IF_PAUSE_REQ(1U)
49985 #define V_ERRSTOP_EN(x) ((x) << S_ERRSTOP_EN)
49986 #define F_ERRSTOP_EN    V_ERRSTOP_EN(1U)
49990 #define V_CMDLIMIT(x) ((x) << S_CMDLIMIT)
49991 #define G_CMDLIMIT(x) (((x) >> S_CMDLIMIT) & M_CMDLIMIT)
49996 #define V_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_CLTCAMDEEPSLEEP_STAT)
49997 #define F_CLTCAMDEEPSLEEP_STAT    V_CLTCAMDEEPSLEEP_STAT(1U)
50000 #define V_TCAMDEEPSLEEP_STAT(x) ((x) << S_TCAMDEEPSLEEP_STAT)
50001 #define F_TCAMDEEPSLEEP_STAT    V_TCAMDEEPSLEEP_STAT(1U)
50004 #define V_CLTCAMDEEPSLEEP(x) ((x) << S_CLTCAMDEEPSLEEP)
50005 #define F_CLTCAMDEEPSLEEP    V_CLTCAMDEEPSLEEP(1U)
50008 #define V_TCAMDEEPSLEEP(x) ((x) << S_TCAMDEEPSLEEP)
50009 #define F_TCAMDEEPSLEEP    V_TCAMDEEPSLEEP(1U)
50015 #define V_RTINDX(x) ((x) << S_RTINDX)
50016 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
50022 #define V_ATINDX(x) ((x) << S_ATINDX)
50023 #define G_ATINDX(x) (((x) >> S_ATINDX) & M_ATINDX)
50029 #define V_FTINDX(x) ((x) << S_FTINDX)
50030 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
50036 #define V_NFTINDX(x) ((x) << S_NFTINDX)
50037 #define G_NFTINDX(x) (((x) >> S_NFTINDX) & M_NFTINDX)
50043 #define V_SRINDX(x) ((x) << S_SRINDX)
50044 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
50050 #define V_T6_SRINDX(x) ((x) << S_T6_SRINDX)
50051 #define G_T6_SRINDX(x) (((x) >> S_T6_SRINDX) & M_T6_SRINDX)
50057 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
50058 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
50064 #define V_HFTINDX(x) ((x) << S_HFTINDX)
50065 #define G_HFTINDX(x) (((x) >> S_HFTINDX) & M_HFTINDX)
50071 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
50072 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
50078 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
50079 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
50085 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
50086 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
50090 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
50091 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
50095 #define V_NUMHASHBKT(x) ((x) << S_NUMHASHBKT)
50096 #define G_NUMHASHBKT(x) (((x) >> S_NUMHASHBKT) & M_NUMHASHBKT)
50100 #define V_HASHTBLSIZE(x) ((x) << S_HASHTBLSIZE)
50101 #define G_HASHTBLSIZE(x) (((x) >> S_HASHTBLSIZE) & M_HASHTBLSIZE)
50108 #define V_MIN_ATCAM_ENTS(x) ((x) << S_MIN_ATCAM_ENTS)
50109 #define G_MIN_ATCAM_ENTS(x) (((x) >> S_MIN_ATCAM_ENTS) & M_MIN_ATCAM_ENTS)
50116 #define V_HASHTBLADDR(x) ((x) << S_HASHTBLADDR)
50117 #define G_HASHTBLADDR(x) (((x) >> S_HASHTBLADDR) & M_HASHTBLADDR)
50124 #define V_TCAM_SIZE(x) ((x) << S_TCAM_SIZE)
50125 #define G_TCAM_SIZE(x) (((x) >> S_TCAM_SIZE) & M_TCAM_SIZE)
50128 #define V_MLL_MASK(x) ((x) << S_MLL_MASK)
50129 #define F_MLL_MASK    V_MLL_MASK(1U)
50135 #define V_MSGSEL(x) ((x) << S_MSGSEL)
50136 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
50139 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
50140 #define F_REQQPARERR    V_REQQPARERR(1U)
50143 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
50144 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
50147 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
50148 #define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)
50151 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
50152 #define F_FILTERHIT    V_FILTERHIT(1U)
50155 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
50156 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
50159 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
50160 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
50163 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
50164 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
50167 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
50168 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
50171 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
50172 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
50175 #define V_PARITYERR(x) ((x) << S_PARITYERR)
50176 #define F_PARITYERR    V_PARITYERR(1U)
50179 #define V_LIPMISS(x) ((x) << S_LIPMISS)
50180 #define F_LIPMISS    V_LIPMISS(1U)
50183 #define V_LIP0(x) ((x) << S_LIP0)
50184 #define F_LIP0    V_LIP0(1U)
50187 #define V_MISS(x) ((x) << S_MISS)
50188 #define F_MISS    V_MISS(1U)
50191 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
50192 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
50194 #define S_ACTIVEHIT    1
50195 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
50196 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
50199 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
50200 #define F_SERVERHIT    V_SERVERHIT(1U)
50203 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
50204 #define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)
50207 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
50208 #define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)
50211 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
50212 #define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)
50215 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
50216 #define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)
50219 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
50220 #define F_MARSPPARERR    V_MARSPPARERR(1U)
50223 #define V_VFPARERR(x) ((x) << S_VFPARERR)
50224 #define F_VFPARERR    V_VFPARERR(1U)
50227 #define V_CLIPSUBERR(x) ((x) << S_CLIPSUBERR)
50228 #define F_CLIPSUBERR    V_CLIPSUBERR(1U)
50231 #define V_CLCAMFIFOERR(x) ((x) << S_CLCAMFIFOERR)
50232 #define F_CLCAMFIFOERR    V_CLCAMFIFOERR(1U)
50235 #define V_HASHTBLMEMCRCERR(x) ((x) << S_HASHTBLMEMCRCERR)
50236 #define F_HASHTBLMEMCRCERR    V_HASHTBLMEMCRCERR(1U)
50239 #define V_CTCAMINVLDENT(x) ((x) << S_CTCAMINVLDENT)
50240 #define F_CTCAMINVLDENT    V_CTCAMINVLDENT(1U)
50243 #define V_TCAMINVLDENT(x) ((x) << S_TCAMINVLDENT)
50244 #define F_TCAMINVLDENT    V_TCAMINVLDENT(1U)
50247 #define V_TOTCNTERR(x) ((x) << S_TOTCNTERR)
50248 #define F_TOTCNTERR    V_TOTCNTERR(1U)
50251 #define V_CMDPRSRINTERR(x) ((x) << S_CMDPRSRINTERR)
50252 #define F_CMDPRSRINTERR    V_CMDPRSRINTERR(1U)
50255 #define V_CMDTIDERR(x) ((x) << S_CMDTIDERR)
50256 #define F_CMDTIDERR    V_CMDTIDERR(1U)
50259 #define V_T6_ACTRGNFULL(x) ((x) << S_T6_ACTRGNFULL)
50260 #define F_T6_ACTRGNFULL    V_T6_ACTRGNFULL(1U)
50263 #define V_T6_ACTCNTIPV6TZERO(x) ((x) << S_T6_ACTCNTIPV6TZERO)
50264 #define F_T6_ACTCNTIPV6TZERO    V_T6_ACTCNTIPV6TZERO(1U)
50267 #define V_T6_ACTCNTIPV4TZERO(x) ((x) << S_T6_ACTCNTIPV4TZERO)
50268 #define F_T6_ACTCNTIPV4TZERO    V_T6_ACTCNTIPV4TZERO(1U)
50271 #define V_T6_ACTCNTIPV6ZERO(x) ((x) << S_T6_ACTCNTIPV6ZERO)
50272 #define F_T6_ACTCNTIPV6ZERO    V_T6_ACTCNTIPV6ZERO(1U)
50275 #define V_T6_ACTCNTIPV4ZERO(x) ((x) << S_T6_ACTCNTIPV4ZERO)
50276 #define F_T6_ACTCNTIPV4ZERO    V_T6_ACTCNTIPV4ZERO(1U)
50279 #define V_MAIFWRINTPERR(x) ((x) << S_MAIFWRINTPERR)
50280 #define F_MAIFWRINTPERR    V_MAIFWRINTPERR(1U)
50283 #define V_HASHTBLMEMACCERR(x) ((x) << S_HASHTBLMEMACCERR)
50284 #define F_HASHTBLMEMACCERR    V_HASHTBLMEMACCERR(1U)
50287 #define V_TCAMCRCERR(x) ((x) << S_TCAMCRCERR)
50288 #define F_TCAMCRCERR    V_TCAMCRCERR(1U)
50291 #define V_TCAMINTPERR(x) ((x) << S_TCAMINTPERR)
50292 #define F_TCAMINTPERR    V_TCAMINTPERR(1U)
50295 #define V_VFSRAMPERR(x) ((x) << S_VFSRAMPERR)
50296 #define F_VFSRAMPERR    V_VFSRAMPERR(1U)
50299 #define V_SRVSRAMPERR(x) ((x) << S_SRVSRAMPERR)
50300 #define F_SRVSRAMPERR    V_SRVSRAMPERR(1U)
50303 #define V_SSRAMINTPERR(x) ((x) << S_SSRAMINTPERR)
50304 #define F_SSRAMINTPERR    V_SSRAMINTPERR(1U)
50307 #define V_CLCAMINTPERR(x) ((x) << S_CLCAMINTPERR)
50308 #define F_CLCAMINTPERR    V_CLCAMINTPERR(1U)
50311 #define V_CLCAMCRCPARERR(x) ((x) << S_CLCAMCRCPARERR)
50312 #define F_CLCAMCRCPARERR    V_CLCAMCRCPARERR(1U)
50315 #define V_HASHTBLACCFAIL(x) ((x) << S_HASHTBLACCFAIL)
50316 #define F_HASHTBLACCFAIL    V_HASHTBLACCFAIL(1U)
50319 #define V_TCAMACCFAIL(x) ((x) << S_TCAMACCFAIL)
50320 #define F_TCAMACCFAIL    V_TCAMACCFAIL(1U)
50323 #define V_SRVSRAMACCFAIL(x) ((x) << S_SRVSRAMACCFAIL)
50324 #define F_SRVSRAMACCFAIL    V_SRVSRAMACCFAIL(1U)
50327 #define V_CLIPTCAMACCFAIL(x) ((x) << S_CLIPTCAMACCFAIL)
50328 #define F_CLIPTCAMACCFAIL    V_CLIPTCAMACCFAIL(1U)
50331 #define V_T6_UNKNOWNCMD(x) ((x) << S_T6_UNKNOWNCMD)
50332 #define F_T6_UNKNOWNCMD    V_T6_UNKNOWNCMD(1U)
50335 #define V_T6_LIP0(x) ((x) << S_T6_LIP0)
50336 #define F_T6_LIP0    V_T6_LIP0(1U)
50338 #define S_T6_LIPMISS    1
50339 #define V_T6_LIPMISS(x) ((x) << S_T6_LIPMISS)
50340 #define F_T6_LIPMISS    V_T6_LIPMISS(1U)
50343 #define V_PIPELINEERR(x) ((x) << S_PIPELINEERR)
50344 #define F_PIPELINEERR    V_PIPELINEERR(1U)
50347 #define V_CACHEINTPERR(x) ((x) << S_CACHEINTPERR)
50348 #define F_CACHEINTPERR    V_CACHEINTPERR(1U)
50351 #define V_CACHESRAMPERR(x) ((x) << S_CACHESRAMPERR)
50352 #define F_CACHESRAMPERR    V_CACHESRAMPERR(1U)
50359 #define V_INTTID(x) ((x) << S_INTTID)
50360 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
50366 #define V_CMD_CMP_MASK(x) ((x) << S_CMD_CMP_MASK)
50367 #define G_CMD_CMP_MASK(x) (((x) >> S_CMD_CMP_MASK) & M_CMD_CMP_MASK)
50371 #define V_TID_CMP_MASK(x) ((x) << S_TID_CMP_MASK)
50372 #define G_TID_CMP_MASK(x) (((x) >> S_TID_CMP_MASK) & M_TID_CMP_MASK)
50378 #define V_INTPTID(x) ((x) << S_INTPTID)
50379 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
50385 #define V_CMD_CMP(x) ((x) << S_CMD_CMP)
50386 #define G_CMD_CMP(x) (((x) >> S_CMD_CMP) & M_CMD_CMP)
50390 #define V_TID_CMP(x) ((x) << S_TID_CMP)
50391 #define G_TID_CMP(x) (((x) >> S_TID_CMP) & M_TID_CMP)
50397 #define V_INTINDEX(x) ((x) << S_INTINDEX)
50398 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
50404 #define V_ERR_CID(x) ((x) << S_ERR_CID)
50405 #define G_ERR_CID(x) (((x) >> S_ERR_CID) & M_ERR_CID)
50409 #define V_ERR_PROT(x) ((x) << S_ERR_PROT)
50410 #define G_ERR_PROT(x) (((x) >> S_ERR_PROT) & M_ERR_PROT)
50414 #define V_ERR_TID(x) ((x) << S_ERR_TID)
50415 #define G_ERR_TID(x) (((x) >> S_ERR_TID) & M_ERR_TID)
50421 #define V_INTCMD(x) ((x) << S_INTCMD)
50422 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
50431 #define V_MAX_HASH_ENTS(x) ((x) << S_MAX_HASH_ENTS)
50432 #define G_MAX_HASH_ENTS(x) (((x) >> S_MAX_HASH_ENTS) & M_MAX_HASH_ENTS)
50438 #define V_SUCCESS(x) ((x) << S_SUCCESS)
50439 #define G_SUCCESS(x) (((x) >> S_SUCCESS) & M_SUCCESS)
50443 #define V_TCAM_ACTV_SUCC(x) ((x) << S_TCAM_ACTV_SUCC)
50444 #define G_TCAM_ACTV_SUCC(x) (((x) >> S_TCAM_ACTV_SUCC) & M_TCAM_ACTV_SUCC)
50448 #define V_HASH_ACTV_SUCC(x) ((x) << S_HASH_ACTV_SUCC)
50449 #define G_HASH_ACTV_SUCC(x) (((x) >> S_HASH_ACTV_SUCC) & M_HASH_ACTV_SUCC)
50453 #define V_TCAM_SRVR_HIT(x) ((x) << S_TCAM_SRVR_HIT)
50454 #define G_TCAM_SRVR_HIT(x) (((x) >> S_TCAM_SRVR_HIT) & M_TCAM_SRVR_HIT)
50458 #define V_SRAM_SRVR_HIT(x) ((x) << S_SRAM_SRVR_HIT)
50459 #define G_SRAM_SRVR_HIT(x) (((x) >> S_SRAM_SRVR_HIT) & M_SRAM_SRVR_HIT)
50463 #define V_TCAM_ACTV_HIT(x) ((x) << S_TCAM_ACTV_HIT)
50464 #define G_TCAM_ACTV_HIT(x) (((x) >> S_TCAM_ACTV_HIT) & M_TCAM_ACTV_HIT)
50470 #define V_HASH_ACTV_HIT(x) ((x) << S_HASH_ACTV_HIT)
50471 #define G_HASH_ACTV_HIT(x) (((x) >> S_HASH_ACTV_HIT) & M_HASH_ACTV_HIT)
50475 #define V_T6_MISS(x) ((x) << S_T6_MISS)
50476 #define G_T6_MISS(x) (((x) >> S_T6_MISS) & M_T6_MISS)
50480 #define V_NORM_FILT_HIT(x) ((x) << S_NORM_FILT_HIT)
50481 #define G_NORM_FILT_HIT(x) (((x) >> S_NORM_FILT_HIT) & M_NORM_FILT_HIT)
50485 #define V_HPRI_FILT_HIT(x) ((x) << S_HPRI_FILT_HIT)
50486 #define G_HPRI_FILT_HIT(x) (((x) >> S_HPRI_FILT_HIT) & M_HPRI_FILT_HIT)
50490 #define V_ACTV_OPEN_ERR(x) ((x) << S_ACTV_OPEN_ERR)
50491 #define G_ACTV_OPEN_ERR(x) (((x) >> S_ACTV_OPEN_ERR) & M_ACTV_OPEN_ERR)
50495 #define V_ACTV_FULL_ERR(x) ((x) << S_ACTV_FULL_ERR)
50496 #define G_ACTV_FULL_ERR(x) (((x) >> S_ACTV_FULL_ERR) & M_ACTV_FULL_ERR)
50502 #define V_SRCH_RGN_HIT(x) ((x) << S_SRCH_RGN_HIT)
50503 #define G_SRCH_RGN_HIT(x) (((x) >> S_SRCH_RGN_HIT) & M_SRCH_RGN_HIT)
50507 #define V_CLIP_FAIL(x) ((x) << S_CLIP_FAIL)
50508 #define G_CLIP_FAIL(x) (((x) >> S_CLIP_FAIL) & M_CLIP_FAIL)
50512 #define V_LIP_ZERO_ERR(x) ((x) << S_LIP_ZERO_ERR)
50513 #define G_LIP_ZERO_ERR(x) (((x) >> S_LIP_ZERO_ERR) & M_LIP_ZERO_ERR)
50517 #define V_UNKNOWN_CMD(x) ((x) << S_UNKNOWN_CMD)
50518 #define G_UNKNOWN_CMD(x) (((x) >> S_UNKNOWN_CMD) & M_UNKNOWN_CMD)
50522 #define V_CMD_TID_ERR(x) ((x) << S_CMD_TID_ERR)
50523 #define G_CMD_TID_ERR(x) (((x) >> S_CMD_TID_ERR) & M_CMD_TID_ERR)
50527 #define V_INTERNAL_ERR(x) ((x) << S_INTERNAL_ERR)
50528 #define G_INTERNAL_ERR(x) (((x) >> S_INTERNAL_ERR) & M_INTERNAL_ERR)
50534 #define V_SRAM_SRVR_HIT_ACTF(x) ((x) << S_SRAM_SRVR_HIT_ACTF)
50535 #define G_SRAM_SRVR_HIT_ACTF(x) (((x) >> S_SRAM_SRVR_HIT_ACTF) & M_SRAM_SRVR_HIT_ACTF)
50539 #define V_TCAM_SRVR_HIT_ACTF(x) ((x) << S_TCAM_SRVR_HIT_ACTF)
50540 #define G_TCAM_SRVR_HIT_ACTF(x) (((x) >> S_TCAM_SRVR_HIT_ACTF) & M_TCAM_SRVR_HIT_ACTF)
50544 #define V_INVLDRD(x) ((x) << S_INVLDRD)
50545 #define G_INVLDRD(x) (((x) >> S_INVLDRD) & M_INVLDRD)
50549 #define V_TUPLZERO(x) ((x) << S_TUPLZERO)
50550 #define G_TUPLZERO(x) (((x) >> S_TUPLZERO) & M_TUPLZERO)
50558 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
50559 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
50575 #define V_T4_RSPCNT(x) ((x) << S_T4_RSPCNT)
50576 #define G_T4_RSPCNT(x) (((x) >> S_T4_RSPCNT) & M_T4_RSPCNT)
50580 #define V_T4_REQCNT(x) ((x) << S_T4_REQCNT)
50581 #define G_T4_REQCNT(x) (((x) >> S_T4_REQCNT) & M_T4_REQCNT)
50585 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
50586 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
50590 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
50591 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
50597 #define V_T7_1_ADDR(x) ((x) << S_T7_1_ADDR)
50598 #define G_T7_1_ADDR(x) (((x) >> S_T7_1_ADDR) & M_T7_1_ADDR)
50604 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
50605 #define F_DBGICMDPERR    V_DBGICMDPERR(1U)
50609 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
50610 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
50613 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
50614 #define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)
50617 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
50618 #define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)
50621 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
50622 #define F_DBGICMDREAD    V_DBGICMDREAD(1U)
50625 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
50626 #define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)
50629 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
50630 #define F_DBGICMDERASE    V_DBGICMDERASE(1U)
50633 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
50634 #define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)
50638 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
50639 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
50642 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
50643 #define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)
50646 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
50647 #define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)
50650 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
50651 #define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)
50655 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
50656 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
50659 #define V_DBGICMDMSKREAD(x) ((x) << S_DBGICMDMSKREAD)
50660 #define F_DBGICMDMSKREAD    V_DBGICMDMSKREAD(1U)
50663 #define V_DBGICMDWRITE(x) ((x) << S_DBGICMDWRITE)
50664 #define F_DBGICMDWRITE    V_DBGICMDWRITE(1U)
50670 #define V_DBGICMD(x) ((x) << S_DBGICMD)
50671 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
50675 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
50676 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
50682 #define V_DBGITID(x) ((x) << S_DBGITID)
50683 #define G_DBGITID(x) (((x) >> S_DBGITID) & M_DBGITID)
50687 #define S_REQQUEUE    1
50688 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
50689 #define F_REQQUEUE    V_REQQUEUE(1U)
50692 #define V_TCAM(x) ((x) << S_TCAM)
50693 #define F_TCAM    V_TCAM(1U)
50696 #define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
50697 #define F_MARSPPARERRLE    V_MARSPPARERRLE(1U)
50700 #define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
50701 #define F_REQQUEUELE    V_REQQUEUELE(1U)
50704 #define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
50705 #define F_VFPARERRLE    V_VFPARERRLE(1U)
50708 #define V_TCAMLE(x) ((x) << S_TCAMLE)
50709 #define F_TCAMLE    V_TCAMLE(1U)
50713 #define V_BKCHKPERIOD(x) ((x) << S_BKCHKPERIOD)
50714 #define G_BKCHKPERIOD(x) (((x) >> S_BKCHKPERIOD) & M_BKCHKPERIOD)
50717 #define V_TCAMBKCHKEN(x) ((x) << S_TCAMBKCHKEN)
50718 #define F_TCAMBKCHKEN    V_TCAMBKCHKEN(1U)
50721 #define V_T6_CLCAMFIFOERR(x) ((x) << S_T6_CLCAMFIFOERR)
50722 #define F_T6_CLCAMFIFOERR    V_T6_CLCAMFIFOERR(1U)
50724 #define S_T6_HASHTBLMEMCRCERR    1
50725 #define V_T6_HASHTBLMEMCRCERR(x) ((x) << S_T6_HASHTBLMEMCRCERR)
50726 #define F_T6_HASHTBLMEMCRCERR    V_T6_HASHTBLMEMCRCERR(1U)
50730 #define V_T7_BKCHKPERIOD(x) ((x) << S_T7_BKCHKPERIOD)
50731 #define G_T7_BKCHKPERIOD(x) (((x) >> S_T7_BKCHKPERIOD) & M_T7_BKCHKPERIOD)
50740 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
50741 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
50745 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
50746 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
50749 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
50750 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
50753 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
50754 #define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)
50756 #define S_DBGIRSPHIT    1
50757 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
50758 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
50761 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
50762 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
50766 #define V_DBGIRSPTID(x) ((x) << S_DBGIRSPTID)
50767 #define G_DBGIRSPTID(x) (((x) >> S_DBGIRSPTID) & M_DBGIRSPTID)
50770 #define V_DBGIRSPLEARN(x) ((x) << S_DBGIRSPLEARN)
50771 #define F_DBGIRSPLEARN    V_DBGIRSPLEARN(1U)
50779 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
50780 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
50784 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
50785 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
50790 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
50791 #define F_DROPFILTEREN    V_DROPFILTEREN(1U)
50794 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
50795 #define F_DROPFILTERCLEAR    V_DROPFILTERCLEAR(1U)
50798 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
50799 #define F_DROPFILTERSET    V_DROPFILTERSET(1U)
50803 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
50804 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
50810 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
50811 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
50817 #define V_TCAM_TID_BASE(x) ((x) << S_TCAM_TID_BASE)
50818 #define G_TCAM_TID_BASE(x) (((x) >> S_TCAM_TID_BASE) & M_TCAM_TID_BASE)
50824 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
50825 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
50831 #define V_CLCAM_TID_BASE(x) ((x) << S_CLCAM_TID_BASE)
50832 #define G_CLCAM_TID_BASE(x) (((x) >> S_CLCAM_TID_BASE) & M_CLCAM_TID_BASE)
50838 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
50839 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
50845 #define V_HASH_TID_BASE(x) ((x) << S_HASH_TID_BASE)
50846 #define G_HASH_TID_BASE(x) (((x) >> S_HASH_TID_BASE) & M_HASH_TID_BASE)
50851 #define S_LEMEMSEL    1
50853 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
50854 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
50860 #define V_SSRAM_TID_BASE(x) ((x) << S_SSRAM_TID_BASE)
50861 #define G_SSRAM_TID_BASE(x) (((x) >> S_SSRAM_TID_BASE) & M_SSRAM_TID_BASE)
50890 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
50891 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
50893 #define S_SRVRINITBUSY    1
50894 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
50895 #define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)
50898 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
50899 #define F_SRVRINIT    V_SRVRINIT(1U)
50904 #define V_PRI_HFILT(x) ((x) << S_PRI_HFILT)
50905 #define F_PRI_HFILT    V_PRI_HFILT(1U)
50908 #define V_PRI_SRVR(x) ((x) << S_PRI_SRVR)
50909 #define F_PRI_SRVR    V_PRI_SRVR(1U)
50912 #define V_PRI_FILT(x) ((x) << S_PRI_FILT)
50913 #define F_PRI_FILT    V_PRI_FILT(1U)
50919 #define V_RDWR(x) ((x) << S_RDWR)
50920 #define F_RDWR    V_RDWR(1U)
50924 #define V_VFINDEX(x) ((x) << S_VFINDEX)
50925 #define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
50929 #define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
50930 #define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
50934 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
50935 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
50940 #define V_VFLUTBUSY(x) ((x) << S_VFLUTBUSY)
50941 #define F_VFLUTBUSY    V_VFLUTBUSY(1U)
50944 #define V_VFLUTSTART(x) ((x) << S_VFLUTSTART)
50945 #define F_VFLUTSTART    V_VFLUTSTART(1U)
50948 #define V_T6_RDWR(x) ((x) << S_T6_RDWR)
50949 #define F_T6_RDWR    V_T6_RDWR(1U)
50953 #define V_T6_VFINDEX(x) ((x) << S_T6_VFINDEX)
50954 #define G_T6_VFINDEX(x) (((x) >> S_T6_VFINDEX) & M_T6_VFINDEX)
50961 #define V_T6_SRCHHADDR(x) ((x) << S_T6_SRCHHADDR)
50962 #define G_T6_SRCHHADDR(x) (((x) >> S_T6_SRCHHADDR) & M_T6_SRCHHADDR)
50966 #define V_T6_SRCHLADDR(x) ((x) << S_T6_SRCHLADDR)
50967 #define G_T6_SRCHLADDR(x) (((x) >> S_T6_SRCHLADDR) & M_T6_SRCHLADDR)
51028 #define V_WIREEN(x) ((x) << S_WIREEN)
51029 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
51033 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
51034 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
51037 #define V_RX_HALT(x) ((x) << S_RX_HALT)
51038 #define F_RX_HALT    V_RX_HALT(1U)
51041 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
51042 #define F_FLUSH_RX_FIFO    V_FLUSH_RX_FIFO(1U)
51045 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
51046 #define F_HW_ARB_EN    V_HW_ARB_EN(1U)
51049 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
51050 #define F_SOFT_PKG_SEL    V_SOFT_PKG_SEL(1U)
51053 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
51054 #define F_ERR_DISCARD_EN    V_ERR_DISCARD_EN(1U)
51058 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
51059 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
51062 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
51063 #define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)
51066 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
51067 #define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
51070 #define V_XGMAC0_EN(x) ((x) << S_XGMAC0_EN)
51071 #define F_XGMAC0_EN    V_XGMAC0_EN(1U)
51076 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
51077 #define F_MAC_REF_RST    V_MAC_REF_RST(1U)
51079 #define S_MAC_RX_RST    1
51080 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
51081 #define F_MAC_RX_RST    V_MAC_RX_RST(1U)
51084 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
51085 #define F_MAC_TX_RST    V_MAC_TX_RST(1U)
51091 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
51092 #define F_CHO_SADDR_EN    V_CHO_SADDR_EN(1U)
51096 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
51097 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
51103 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
51104 #define F_CH1_SADDR_EN    V_CH1_SADDR_EN(1U)
51108 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
51109 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
51115 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
51116 #define F_CH2_SADDR_EN    V_CH2_SADDR_EN(1U)
51120 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
51121 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
51127 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
51128 #define F_CH3_SADDR_EN    V_CH3_SADDR_EN(1U)
51132 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
51133 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
51144 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
51145 #define F_STRIP_OVLAN    V_STRIP_OVLAN(1U)
51148 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
51149 #define F_BMC_DROP_NON_BC    V_BMC_DROP_NON_BC(1U)
51151 #define S_BMC_RX_FWD_ALL    1
51152 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
51153 #define F_BMC_RX_FWD_ALL    V_BMC_RX_FWD_ALL(1U)
51156 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
51157 #define F_FWD_BMC    V_FWD_BMC(1U)
51163 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
51164 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
51170 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
51171 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
51181 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
51182 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
51186 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
51187 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
51193 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
51194 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
51198 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
51199 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
51205 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
51206 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
51212 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
51213 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
51219 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
51220 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
51224 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
51225 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
51229 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
51230 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
51234 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
51235 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
51241 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
51242 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
51246 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
51247 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
51251 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
51252 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
51256 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
51257 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
51263 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
51264 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
51268 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
51269 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
51273 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
51274 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
51278 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
51279 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
51283 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
51284 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
51294 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
51295 #define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)
51298 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
51299 #define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)
51302 #define V_TOKEN(x) ((x) << S_TOKEN)
51303 #define F_TOKEN    V_TOKEN(1U)
51306 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
51307 #define F_ARB_DONE    V_ARB_DONE(1U)
51310 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
51311 #define F_ARB_STARTED    V_ARB_STARTED(1U)
51314 #define V_WOL(x) ((x) << S_WOL)
51315 #define F_WOL    V_WOL(1U)
51318 #define V_MACINT(x) ((x) << S_MACINT)
51319 #define F_MACINT    V_MACINT(1U)
51321 #define S_TXFIFO_PRTY_ERR    1
51322 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
51323 #define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)
51326 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
51327 #define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
51330 #define V_CIM2NC_PERR(x) ((x) << S_CIM2NC_PERR)
51331 #define F_CIM2NC_PERR    V_CIM2NC_PERR(1U)
51336 #define S_MASTER    1
51337 #define V_MASTER(x) ((x) << S_MASTER)
51338 #define F_MASTER    V_MASTER(1U)
51341 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
51342 #define F_ARB_STATUS    V_ARB_STATUS(1U)
51347 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
51348 #define F_FORCEPAUSE    V_FORCEPAUSE(1U)
51355 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
51356 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
51360 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
51361 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
51367 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
51368 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
51371 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
51372 #define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
51375 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
51376 #define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
51380 #define V_PKG_ID(x) ((x) << S_PKG_ID)
51381 #define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
51385 #define S_MCSIMELSEL    1
51386 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
51387 #define F_MCSIMELSEL    V_MCSIMELSEL(1U)
51393 #define V_XGMAC_MODE(x) ((x) << S_XGMAC_MODE)
51394 #define F_XGMAC_MODE    V_XGMAC_MODE(1U)
51399 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
51400 #define F_TXSNDZEROPAUSE    V_TXSNDZEROPAUSE(1U)
51403 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
51404 #define F_TXSNDPAUSE    V_TXSNDPAUSE(1U)
51407 #define V_TXSTOP(x) ((x) << S_TXSTOP)
51408 #define F_TXSTOP    V_TXSTOP(1U)
51411 #define V_TXSTART(x) ((x) << S_TXSTART)
51412 #define F_TXSTART    V_TXSTART(1U)
51415 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
51416 #define F_BACKPRESS    V_BACKPRESS(1U)
51419 #define V_STATWREN(x) ((x) << S_STATWREN)
51420 #define F_STATWREN    V_STATWREN(1U)
51423 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
51424 #define F_INCRSTAT    V_INCRSTAT(1U)
51427 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
51428 #define F_CLEARSTAT    V_CLEARSTAT(1U)
51431 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
51432 #define F_ENMGMTPORT    V_ENMGMTPORT(1U)
51435 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
51436 #define F_NCSITXEN    V_NCSITXEN(1U)
51439 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
51440 #define F_NCSIRXEN    V_NCSIRXEN(1U)
51442 #define S_LOOPLOCAL    1
51443 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
51444 #define F_LOOPLOCAL    V_LOOPLOCAL(1U)
51447 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
51448 #define F_LOOPPHY    V_LOOPPHY(1U)
51453 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
51454 #define F_PCLKDIV128    V_PCLKDIV128(1U)
51457 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
51458 #define F_COPYPAUSE    V_COPYPAUSE(1U)
51461 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
51462 #define F_NONSTDPREOK    V_NONSTDPREOK(1U)
51465 #define V_NOFCS(x) ((x) << S_NOFCS)
51466 #define F_NOFCS    V_NOFCS(1U)
51469 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
51470 #define F_RXENHALFDUP    V_RXENHALFDUP(1U)
51473 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
51474 #define F_NOCOPYFCS    V_NOCOPYFCS(1U)
51477 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
51478 #define F_LENCHKEN    V_LENCHKEN(1U)
51482 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
51483 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
51486 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
51487 #define F_PAUSEEN    V_PAUSEEN(1U)
51490 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
51491 #define F_RETRYTEST    V_RETRYTEST(1U)
51495 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
51496 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
51499 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
51500 #define F_EXTCLASS    V_EXTCLASS(1U)
51503 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
51504 #define F_EN1536FRAME    V_EN1536FRAME(1U)
51507 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
51508 #define F_UCASTHASHEN    V_UCASTHASHEN(1U)
51511 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
51512 #define F_MCASTHASHEN    V_MCASTHASHEN(1U)
51515 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
51516 #define F_RXBCASTDIS    V_RXBCASTDIS(1U)
51519 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
51520 #define F_NCSICOPYALLFRAMES    V_NCSICOPYALLFRAMES(1U)
51523 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
51524 #define F_JUMBOEN    V_JUMBOEN(1U)
51527 #define V_SEREN(x) ((x) << S_SEREN)
51528 #define F_SEREN    V_SEREN(1U)
51530 #define S_FULLDUPLEX    1
51531 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
51532 #define F_FULLDUPLEX    V_FULLDUPLEX(1U)
51535 #define V_SPEED(x) ((x) << S_SPEED)
51536 #define F_SPEED    V_SPEED(1U)
51541 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
51542 #define F_PHYMGMTSTATUS    V_PHYMGMTSTATUS(1U)
51544 #define S_MDISTATUS    1
51545 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
51546 #define F_MDISTATUS    V_MDISTATUS(1U)
51549 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
51550 #define F_LINKSTATUS    V_LINKSTATUS(1U)
51555 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
51556 #define F_UNDERRUNERR    V_UNDERRUNERR(1U)
51559 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
51560 #define F_TXCOMPLETE    V_TXCOMPLETE(1U)
51563 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
51564 #define F_BUFFEREXHAUSTED    V_BUFFEREXHAUSTED(1U)
51567 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
51568 #define F_TXPROGRESS    V_TXPROGRESS(1U)
51571 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
51572 #define F_RETRYLIMIT    V_RETRYLIMIT(1U)
51574 #define S_COLEVENT    1
51575 #define V_COLEVENT(x) ((x) << S_COLEVENT)
51576 #define F_COLEVENT    V_COLEVENT(1U)
51579 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
51580 #define F_USEDBITREAD    V_USEDBITREAD(1U)
51586 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
51587 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
51593 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
51594 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
51599 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
51600 #define F_RXOVERRUNERR    V_RXOVERRUNERR(1U)
51602 #define S_MACB_FRAMERCVD    1
51603 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
51604 #define F_MACB_FRAMERCVD    V_MACB_FRAMERCVD(1U)
51607 #define V_NORXBUF(x) ((x) << S_NORXBUF)
51608 #define F_NORXBUF    V_NORXBUF(1U)
51613 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
51614 #define F_PAUSETIMEZERO    V_PAUSETIMEZERO(1U)
51617 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
51618 #define F_PAUSERCVD    V_PAUSERCVD(1U)
51621 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
51622 #define F_HRESPNOTOK    V_HRESPNOTOK(1U)
51625 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
51626 #define F_RXOVERRUN    V_RXOVERRUN(1U)
51629 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
51630 #define F_LINKCHANGE    V_LINKCHANGE(1U)
51633 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
51634 #define F_INT_TXCOMPLETE    V_INT_TXCOMPLETE(1U)
51637 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
51638 #define F_TXBUFERR    V_TXBUFERR(1U)
51641 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
51642 #define F_RETRYLIMITERR    V_RETRYLIMITERR(1U)
51645 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
51646 #define F_TXBUFUNDERRUN    V_TXBUFUNDERRUN(1U)
51649 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
51650 #define F_TXUSEDBITREAD    V_TXUSEDBITREAD(1U)
51653 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
51654 #define F_RXUSEDBITREAD    V_RXUSEDBITREAD(1U)
51656 #define S_RXCOMPLETE    1
51657 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
51658 #define F_RXCOMPLETE    V_RXCOMPLETE(1U)
51661 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
51662 #define F_MGMTFRAMESENT    V_MGMTFRAMESENT(1U)
51671 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
51672 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
51678 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
51679 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
51685 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
51686 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
51692 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
51693 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
51699 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
51700 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
51706 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
51707 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
51713 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
51714 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
51720 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
51721 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
51727 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
51728 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
51734 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
51735 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
51741 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
51742 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
51748 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
51749 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
51755 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
51756 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
51762 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
51763 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
51769 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
51770 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
51776 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
51777 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
51783 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
51784 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
51790 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
51791 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
51797 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
51798 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
51804 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
51805 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
51811 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
51812 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
51818 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
51819 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
51828 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
51829 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
51841 #define V_TYPEID(x) ((x) << S_TYPEID)
51842 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
51848 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
51849 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
51855 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
51856 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
51860 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
51861 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
51866 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
51867 #define F_MCHASHEN    V_MCHASHEN(1U)
51870 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
51871 #define F_SPECIFIC1EN    V_SPECIFIC1EN(1U)
51874 #define V_ARPEN(x) ((x) << S_ARPEN)
51875 #define F_ARPEN    V_ARPEN(1U)
51878 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
51879 #define F_MAGICPKTEN    V_MAGICPKTEN(1U)
51883 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
51884 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
51890 #define V_PARTREF(x) ((x) << S_PARTREF)
51891 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
51895 #define V_DESREV(x) ((x) << S_DESREV)
51896 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
51901 #define V_T7_TXEN(x) ((x) << S_T7_TXEN)
51902 #define F_T7_TXEN    V_T7_TXEN(1U)
51939 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
51940 #define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
51943 #define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
51944 #define F_RXFIFO_FULL    V_RXFIFO_FULL(1U)
51948 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
51949 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
51953 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
51954 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
51957 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
51958 #define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
51961 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
51962 #define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
51965 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
51966 #define F_RXBYTESWAP    V_RXBYTESWAP(1U)
51968 #define S_RXSTRFRWRD    1
51969 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
51970 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
51973 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
51974 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
51979 #define V_T7_TXFIFO_EMPTY(x) ((x) << S_T7_TXFIFO_EMPTY)
51980 #define F_T7_TXFIFO_EMPTY    V_T7_TXFIFO_EMPTY(1U)
51983 #define V_T7_TXFIFO_FULL(x) ((x) << S_T7_TXFIFO_FULL)
51984 #define F_T7_TXFIFO_FULL    V_T7_TXFIFO_FULL(1U)
51987 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
51988 #define F_UNDERUNFIX    V_UNDERUNFIX(1U)
51991 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
51992 #define F_ENDROPPKT    V_ENDROPPKT(1U)
51996 #define V_TXIPG(x) ((x) << S_TXIPG)
51997 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
52001 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
52002 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
52005 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
52006 #define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
52009 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
52010 #define F_TXBYTESWAP    V_TXBYTESWAP(1U)
52012 #define S_DISCRC    1
52013 #define V_DISCRC(x) ((x) << S_DISCRC)
52014 #define F_DISCRC    V_DISCRC(1U)
52017 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
52018 #define F_DISPREAMBLE    V_DISPREAMBLE(1U)
52023 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
52024 #define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
52028 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
52029 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
52035 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
52036 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
52040 #define S_TESTPATTERN    1
52042 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
52043 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
52046 #define V_ENTEST(x) ((x) << S_ENTEST)
52047 #define F_ENTEST    V_ENTEST(1U)
52051 #define S_PHALIGNFIFOTHRESH    1
52053 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
52054 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
52057 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
52058 #define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
52063 #define V_CALRESET(x) ((x) << S_CALRESET)
52064 #define F_CALRESET    V_CALRESET(1U)
52067 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
52068 #define F_CALUPDATE    V_CALUPDATE(1U)
52071 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
52072 #define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
52076 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
52077 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
52081 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
52082 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
52088 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
52089 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
52092 #define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
52093 #define F_RXENERRORGATHER    V_RXENERRORGATHER(1U)
52096 #define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
52097 #define F_RXENSINGLEFLIT    V_RXENSINGLEFLIT(1U)
52100 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
52101 #define F_RXENFRAMER    V_RXENFRAMER(1U)
52105 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
52106 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
52111 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
52112 #define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
52115 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
52116 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
52119 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
52120 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
52122 #define S_PCS_RESET_    1
52123 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
52124 #define F_PCS_RESET_    V_PCS_RESET_(1U)
52127 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
52128 #define F_MAC_RESET_    V_MAC_RESET_(1U)
52134 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
52135 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
52140 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
52141 #define F_LANEREVERSAL    V_LANEREVERSAL(1U)
52145 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
52146 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
52150 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
52151 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
52156 #define V_NCSI_SAFESPEEDCHANGE(x) ((x) << S_NCSI_SAFESPEEDCHANGE)
52157 #define F_NCSI_SAFESPEEDCHANGE    V_NCSI_SAFESPEEDCHANGE(1U)
52160 #define V_NCSI_CLKDIVRESET_(x) ((x) << S_NCSI_CLKDIVRESET_)
52161 #define F_NCSI_CLKDIVRESET_    V_NCSI_CLKDIVRESET_(1U)
52163 #define S_NCSI_PORTSPEED    1
52165 #define V_NCSI_PORTSPEED(x) ((x) << S_NCSI_PORTSPEED)
52166 #define G_NCSI_PORTSPEED(x) (((x) >> S_NCSI_PORTSPEED) & M_NCSI_PORTSPEED)
52169 #define V_NCSI_ENRGMII(x) ((x) << S_NCSI_ENRGMII)
52170 #define F_NCSI_ENRGMII    V_NCSI_ENRGMII(1U)
52179 #define V_PIO_READY(x) ((x) << S_PIO_READY)
52180 #define F_PIO_READY    V_PIO_READY(1U)
52183 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
52184 #define F_PIO_WRRD    V_PIO_WRRD(1U)
52188 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
52189 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
52194 #define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
52195 #define F_XAUIPCSDECERR    V_XAUIPCSDECERR(1U)
52198 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
52199 #define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
52202 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
52203 #define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
52206 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
52207 #define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
52210 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
52211 #define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
52215 #define V_T7_TXFIFO_PRTY_ERR(x) ((x) << S_T7_TXFIFO_PRTY_ERR)
52216 #define G_T7_TXFIFO_PRTY_ERR(x) (((x) >> S_T7_TXFIFO_PRTY_ERR) & M_T7_TXFIFO_PRTY_ERR)
52220 #define V_T7_RXFIFO_PRTY_ERR(x) ((x) << S_T7_RXFIFO_PRTY_ERR)
52221 #define G_T7_RXFIFO_PRTY_ERR(x) (((x) >> S_T7_RXFIFO_PRTY_ERR) & M_T7_RXFIFO_PRTY_ERR)
52224 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
52225 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
52228 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
52229 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
52233 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
52234 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
52238 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
52239 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
52242 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
52243 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
52246 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
52247 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
52249 #define S_RGMIILINKSTSCHANGE    1
52250 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
52251 #define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
52254 #define V_T7_XGM_INT(x) ((x) << S_T7_XGM_INT)
52255 #define F_T7_XGM_INT    V_T7_XGM_INT(1U)
52262 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
52263 #define F_INTSERLPBK3    V_INTSERLPBK3(1U)
52266 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
52267 #define F_INTSERLPBK2    V_INTSERLPBK2(1U)
52270 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
52271 #define F_INTSERLPBK1    V_INTSERLPBK1(1U)
52274 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
52275 #define F_INTSERLPBK0    V_INTSERLPBK0(1U)
52278 #define V_RESET3(x) ((x) << S_RESET3)
52279 #define F_RESET3    V_RESET3(1U)
52282 #define V_RESET2(x) ((x) << S_RESET2)
52283 #define F_RESET2    V_RESET2(1U)
52286 #define V_RESET1(x) ((x) << S_RESET1)
52287 #define F_RESET1    V_RESET1(1U)
52290 #define V_RESET0(x) ((x) << S_RESET0)
52291 #define F_RESET0    V_RESET0(1U)
52294 #define V_PWRDN3(x) ((x) << S_PWRDN3)
52295 #define F_PWRDN3    V_PWRDN3(1U)
52298 #define V_PWRDN2(x) ((x) << S_PWRDN2)
52299 #define F_PWRDN2    V_PWRDN2(1U)
52302 #define V_PWRDN1(x) ((x) << S_PWRDN1)
52303 #define F_PWRDN1    V_PWRDN1(1U)
52306 #define V_PWRDN0(x) ((x) << S_PWRDN0)
52307 #define F_PWRDN0    V_PWRDN0(1U)
52310 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
52311 #define F_RESETPLL23    V_RESETPLL23(1U)
52314 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
52315 #define F_RESETPLL01    V_RESETPLL01(1U)
52319 #define V_PW23(x) ((x) << S_PW23)
52320 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
52324 #define V_PW01(x) ((x) << S_PW01)
52325 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
52329 #define V_DEQ(x) ((x) << S_DEQ)
52330 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
52334 #define V_DTX(x) ((x) << S_DTX)
52335 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
52337 #define S_LODRV    1
52338 #define V_LODRV(x) ((x) << S_LODRV)
52339 #define F_LODRV    V_LODRV(1U)
52342 #define V_HIDRV(x) ((x) << S_HIDRV)
52343 #define F_HIDRV    V_HIDRV(1U)
52349 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
52350 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
52353 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
52354 #define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
52358 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
52359 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
52362 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
52363 #define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
52367 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
52368 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
52371 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
52372 #define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
52374 #define S_FMOFFSET0    1
52376 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
52377 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
52380 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
52381 #define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
52386 #define V_DNIN3(x) ((x) << S_DNIN3)
52387 #define F_DNIN3    V_DNIN3(1U)
52390 #define V_UPIN3(x) ((x) << S_UPIN3)
52391 #define F_UPIN3    V_UPIN3(1U)
52394 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
52395 #define F_RXSLAVE3    V_RXSLAVE3(1U)
52398 #define V_DNIN2(x) ((x) << S_DNIN2)
52399 #define F_DNIN2    V_DNIN2(1U)
52402 #define V_UPIN2(x) ((x) << S_UPIN2)
52403 #define F_UPIN2    V_UPIN2(1U)
52406 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
52407 #define F_RXSLAVE2    V_RXSLAVE2(1U)
52410 #define V_DNIN1(x) ((x) << S_DNIN1)
52411 #define F_DNIN1    V_DNIN1(1U)
52414 #define V_UPIN1(x) ((x) << S_UPIN1)
52415 #define F_UPIN1    V_UPIN1(1U)
52418 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
52419 #define F_RXSLAVE1    V_RXSLAVE1(1U)
52422 #define V_DNIN0(x) ((x) << S_DNIN0)
52423 #define F_DNIN0    V_DNIN0(1U)
52425 #define S_UPIN0    1
52426 #define V_UPIN0(x) ((x) << S_UPIN0)
52427 #define F_UPIN0    V_UPIN0(1U)
52430 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
52431 #define F_RXSLAVE0    V_RXSLAVE0(1U)
52436 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
52437 #define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
52440 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
52441 #define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
52444 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
52445 #define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
52449 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
52450 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
52453 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
52454 #define F_EXTPARRESET3    V_EXTPARRESET3(1U)
52457 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
52458 #define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
52461 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
52462 #define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
52465 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
52466 #define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
52469 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
52470 #define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
52474 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
52475 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
52478 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
52479 #define F_EXTPARRESET2    V_EXTPARRESET2(1U)
52482 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
52483 #define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
52486 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
52487 #define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
52490 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
52491 #define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
52494 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
52495 #define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
52499 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
52500 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
52503 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
52504 #define F_EXTPARRESET1    V_EXTPARRESET1(1U)
52507 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
52508 #define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
52511 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
52512 #define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
52515 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
52516 #define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
52519 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
52520 #define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
52524 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
52525 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
52527 #define S_EXTPARRESET0    1
52528 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
52529 #define F_EXTPARRESET0    V_EXTPARRESET0(1U)
52532 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
52533 #define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
52539 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
52540 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
52543 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
52544 #define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
52547 #define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
52548 #define F_LOWSIGFORCEEN0    V_LOWSIGFORCEEN0(1U)
52550 #define S_LOWSIGFORCEVALUE0    1
52551 #define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
52552 #define F_LOWSIGFORCEVALUE0    V_LOWSIGFORCEVALUE0(1U)
52555 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
52556 #define F_LOWSIG0    V_LOWSIG0(1U)
52562 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
52563 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
52566 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
52567 #define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
52570 #define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
52571 #define F_LOWSIGFORCEEN1    V_LOWSIGFORCEEN1(1U)
52573 #define S_LOWSIGFORCEVALUE1    1
52574 #define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
52575 #define F_LOWSIGFORCEVALUE1    V_LOWSIGFORCEVALUE1(1U)
52578 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
52579 #define F_LOWSIG1    V_LOWSIG1(1U)
52585 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
52586 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
52589 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
52590 #define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
52593 #define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
52594 #define F_LOWSIGFORCEEN2    V_LOWSIGFORCEEN2(1U)
52596 #define S_LOWSIGFORCEVALUE2    1
52597 #define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
52598 #define F_LOWSIGFORCEVALUE2    V_LOWSIGFORCEVALUE2(1U)
52601 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
52602 #define F_LOWSIG2    V_LOWSIG2(1U)
52608 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
52609 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
52612 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
52613 #define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
52616 #define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
52617 #define F_LOWSIGFORCEEN3    V_LOWSIGFORCEEN3(1U)
52619 #define S_LOWSIGFORCEVALUE3    1
52620 #define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
52621 #define F_LOWSIGFORCEVALUE3    V_LOWSIGFORCEVALUE3(1U)
52624 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
52625 #define F_LOWSIG3    V_LOWSIG3(1U)
52666 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
52667 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
52669 #define S_PCS_CTCFIFOERR    1
52671 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
52672 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
52675 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
52676 #define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
52681 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
52682 #define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
52684 #define S_GMIISPEED    1
52686 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
52687 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
52690 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
52691 #define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
52696 #define V_T7_PATDETECTED(x) ((x) << S_T7_PATDETECTED)
52697 #define F_T7_PATDETECTED    V_T7_PATDETECTED(1U)
52704 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
52705 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
52709 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
52710 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
52716 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
52717 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
52721 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
52722 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
52731 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
52732 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
52735 #define V_SINKTX(x) ((x) << S_SINKTX)
52736 #define F_SINKTX    V_SINKTX(1U)
52739 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
52740 #define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)
52743 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
52744 #define F_XG2G_SPEED_MODE    V_XG2G_SPEED_MODE(1U)
52747 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
52748 #define F_LOOPNOFWD    V_LOOPNOFWD(1U)
52751 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
52752 #define F_XGM_TX_PAUSE_SIZE    V_XGM_TX_PAUSE_SIZE(1U)
52755 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
52756 #define F_XGM_TX_PAUSE_FRAME    V_XGM_TX_PAUSE_FRAME(1U)
52759 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
52760 #define F_XGM_TX_DISABLE_PRE    V_XGM_TX_DISABLE_PRE(1U)
52763 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
52764 #define F_XGM_TX_DISABLE_CRC    V_XGM_TX_DISABLE_CRC(1U)
52767 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
52768 #define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)
52771 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
52772 #define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)
52775 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
52776 #define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)
52779 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
52780 #define F_SIGNAL_DET    V_SIGNAL_DET(1U)
52783 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
52784 #define F_PMUX_RX_LOOP    V_PMUX_RX_LOOP(1U)
52787 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
52788 #define F_PMUX_TX_LOOP    V_PMUX_TX_LOOP(1U)
52792 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
52793 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
52797 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
52798 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
52801 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
52802 #define F_XAUI20_REM_PRE    V_XAUI20_REM_PRE(1U)
52805 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
52806 #define F_XAUI20_XGMII_SEL    V_XAUI20_XGMII_SEL(1U)
52809 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
52810 #define F_PORT_SEL    V_PORT_SEL(1U)
52815 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
52816 #define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)
52819 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
52820 #define F_TXFIFO_RESET    V_TXFIFO_RESET(1U)
52823 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
52824 #define F_RXFIFO_RESET    V_RXFIFO_RESET(1U)
52827 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
52828 #define F_BEAN_RESET    V_BEAN_RESET(1U)
52831 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
52832 #define F_XAUI_RESET    V_XAUI_RESET(1U)
52835 #define V_AE_RESET(x) ((x) << S_AE_RESET)
52836 #define F_AE_RESET    V_AE_RESET(1U)
52839 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
52840 #define F_XGM_RESET    V_XGM_RESET(1U)
52843 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
52844 #define F_XG2G_RESET    V_XG2G_RESET(1U)
52847 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
52848 #define F_WOL_RESET    V_WOL_RESET(1U)
52850 #define S_XFI_PCS_RESET    1
52851 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
52852 #define F_XFI_PCS_RESET    V_XFI_PCS_RESET(1U)
52855 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
52856 #define F_HSS_RESET    V_HSS_RESET(1U)
52862 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
52863 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
52866 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
52867 #define F_LED1_POLARITY_INV    V_LED1_POLARITY_INV(1U)
52869 #define S_LED0_CFG    1
52871 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
52872 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
52875 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
52876 #define F_LED0_POLARITY_INV    V_LED0_POLARITY_INV(1U)
52882 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
52883 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
52889 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
52890 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
52896 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
52897 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
52903 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
52904 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
52908 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
52909 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
52913 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
52914 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
52917 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
52918 #define F_STOPONPERR    V_STOPONPERR(1U)
52921 #define V_MACTXEN(x) ((x) << S_MACTXEN)
52922 #define F_MACTXEN    V_MACTXEN(1U)
52925 #define V_MACRXEN(x) ((x) << S_MACRXEN)
52926 #define F_MACRXEN    V_MACRXEN(1U)
52929 #define V_PATEN(x) ((x) << S_PATEN)
52930 #define F_PATEN    V_PATEN(1U)
52933 #define V_MAGICEN(x) ((x) << S_MAGICEN)
52934 #define F_MAGICEN    V_MAGICEN(1U)
52938 #define V_TX_IPG(x) ((x) << S_TX_IPG)
52939 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
52941 #define S_AEC_PMA_TX_READY    1
52942 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
52943 #define F_AEC_PMA_TX_READY    V_AEC_PMA_TX_READY(1U)
52946 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
52947 #define F_AEC_PMA_RX_READY    V_AEC_PMA_RX_READY(1U)
52953 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
52954 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
52958 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
52959 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
52963 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
52964 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
52968 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
52969 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
52973 #define S_XGMMEMSEL    1
52974 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
52975 #define F_XGMMEMSEL    V_XGMMEMSEL(1U)
52982 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
52983 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
52990 #define V_TXSOP(x) ((x) << S_TXSOP)
52991 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
52995 #define V_TXEOP(x) ((x) << S_TXEOP)
52996 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
53000 #define V_RXSOP(x) ((x) << S_RXSOP)
53001 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
53005 #define V_T4_RXEOP(x) ((x) << S_T4_RXEOP)
53006 #define G_T4_RXEOP(x) (((x) >> S_T4_RXEOP) & M_T4_RXEOP)
53011 #define V_REMFLT(x) ((x) << S_REMFLT)
53012 #define F_REMFLT    V_REMFLT(1U)
53015 #define V_LOCFLT(x) ((x) << S_LOCFLT)
53016 #define F_LOCFLT    V_LOCFLT(1U)
53018 #define S_LINKUP    1
53019 #define V_LINKUP(x) ((x) << S_LINKUP)
53020 #define F_LINKUP    V_LINKUP(1U)
53023 #define V_LINKDN(x) ((x) << S_LINKDN)
53024 #define F_LINKDN    V_LINKDN(1U)
53028 #define S_PREAMBLE    1
53029 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
53030 #define F_PREAMBLE    V_PREAMBLE(1U)
53033 #define V_CHECKIN(x) ((x) << S_CHECKIN)
53034 #define F_CHECKIN    V_CHECKIN(1U)
53038 #define S_FLTTYPE    1
53039 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
53040 #define F_FLTTYPE    V_FLTTYPE(1U)
53043 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
53044 #define F_FLTCTRL    V_FLTCTRL(1U)
53051 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
53052 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
53059 #define V_CTRL(x) ((x) << S_CTRL)
53060 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
53065 #define V_CTL(x) ((x) << S_CTL)
53066 #define F_CTL    V_CTL(1U)
53070 #define V_HWM(x) ((x) << S_HWM)
53071 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
53075 #define V_LWM(x) ((x) << S_LWM)
53076 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
53084 #define V_RXRST(x) ((x) << S_RXRST)
53085 #define F_RXRST    V_RXRST(1U)
53088 #define V_TXRST(x) ((x) << S_TXRST)
53089 #define F_TXRST    V_TXRST(1U)
53092 #define V_XGMII(x) ((x) << S_XGMII)
53093 #define F_XGMII    V_XGMII(1U)
53096 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
53097 #define F_LAPAUSE    V_LAPAUSE(1U)
53099 #define S_STOPERR    1
53100 #define V_STOPERR(x) ((x) << S_STOPERR)
53101 #define F_STOPERR    V_STOPERR(1U)
53104 #define V_LASTOP(x) ((x) << S_LASTOP)
53105 #define F_LASTOP    V_LASTOP(1U)
53114 #define V_EPIOWR(x) ((x) << S_EPIOWR)
53115 #define F_EPIOWR    V_EPIOWR(1U)
53119 #define V_ADDRESS(x) ((x) << S_ADDRESS)
53120 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
53125 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
53126 #define F_MAGICDETECTED    V_MAGICDETECTED(1U)
53129 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
53130 #define F_PATDETECTED    V_PATDETECTED(1U)
53133 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
53134 #define F_CLEARMAGIC    V_CLEARMAGIC(1U)
53137 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
53138 #define F_CLEARMATCH    V_CLEARMATCH(1U)
53142 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
53143 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
53148 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
53149 #define F_EXT_LOS    V_EXT_LOS(1U)
53152 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
53153 #define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)
53156 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
53157 #define F_PATDETWAKE    V_PATDETWAKE(1U)
53160 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
53161 #define F_MAGICWAKE    V_MAGICWAKE(1U)
53164 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
53165 #define F_SIGDETCHG    V_SIGDETCHG(1U)
53168 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
53169 #define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)
53172 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
53173 #define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)
53176 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
53177 #define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)
53180 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
53181 #define F_HSSPRT_READY    V_HSSPRT_READY(1U)
53184 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
53185 #define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)
53188 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
53189 #define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)
53192 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
53193 #define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)
53196 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
53197 #define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)
53200 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
53201 #define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)
53204 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
53205 #define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)
53208 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
53209 #define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)
53212 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
53213 #define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)
53216 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
53217 #define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)
53220 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
53221 #define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)
53224 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
53225 #define F_HSSPRBSERR    V_HSSPRBSERR(1U)
53228 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
53229 #define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)
53232 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
53233 #define F_REMOTEFAULT    V_REMOTEFAULT(1U)
53236 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
53237 #define F_LOCALFAULT    V_LOCALFAULT(1U)
53240 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
53241 #define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)
53244 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
53245 #define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)
53248 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
53249 #define F_BEAN_INT    V_BEAN_INT(1U)
53252 #define V_XGM_INT(x) ((x) << S_XGM_INT)
53253 #define F_XGM_INT    V_XGM_INT(1U)
53259 #define V_TXDTS(x) ((x) << S_TXDTS)
53260 #define F_TXDTS    V_TXDTS(1U)
53263 #define V_TXCTS(x) ((x) << S_TXCTS)
53264 #define F_TXCTS    V_TXCTS(1U)
53267 #define V_TXBTS(x) ((x) << S_TXBTS)
53268 #define F_TXBTS    V_TXBTS(1U)
53271 #define V_TXATS(x) ((x) << S_TXATS)
53272 #define F_TXATS    V_TXATS(1U)
53275 #define V_TXDOBS(x) ((x) << S_TXDOBS)
53276 #define F_TXDOBS    V_TXDOBS(1U)
53279 #define V_TXCOBS(x) ((x) << S_TXCOBS)
53280 #define F_TXCOBS    V_TXCOBS(1U)
53283 #define V_TXBOBS(x) ((x) << S_TXBOBS)
53284 #define F_TXBOBS    V_TXBOBS(1U)
53287 #define V_TXAOBS(x) ((x) << S_TXAOBS)
53288 #define F_TXAOBS    V_TXAOBS(1U)
53291 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
53292 #define F_HSSREFCLKSEL    V_HSSREFCLKSEL(1U)
53295 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
53296 #define F_HSSAVDHI    V_HSSAVDHI(1U)
53299 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
53300 #define F_HSSRXTS    V_HSSRXTS(1U)
53303 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
53304 #define F_HSSTXACMODE    V_HSSTXACMODE(1U)
53307 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
53308 #define F_HSSRXACMODE    V_HSSRXACMODE(1U)
53311 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
53312 #define F_HSSRESYNC    V_HSSRESYNC(1U)
53315 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
53316 #define F_HSSRECCAL    V_HSSRECCAL(1U)
53319 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
53320 #define F_HSSPDWNPLL    V_HSSPDWNPLL(1U)
53324 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
53325 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
53328 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
53329 #define F_HSSREFDIV    V_HSSREFDIV(1U)
53332 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
53333 #define F_HSSPLLBYP    V_HSSPLLBYP(1U)
53336 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
53337 #define F_HSSLOFREQPLL    V_HSSLOFREQPLL(1U)
53340 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
53341 #define F_HSSLOFREQ2PLL    V_HSSLOFREQ2PLL(1U)
53344 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
53345 #define F_HSSEXTC16SEL    V_HSSEXTC16SEL(1U)
53347 #define S_HSSRSTCONFIG    1
53349 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
53350 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
53353 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
53354 #define F_HSSPRBSEN    V_HSSPRBSEN(1U)
53359 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
53360 #define F_RXDPRBSRST    V_RXDPRBSRST(1U)
53363 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
53364 #define F_RXDPRBSEN    V_RXDPRBSEN(1U)
53367 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
53368 #define F_RXDPRBSFRCERR    V_RXDPRBSFRCERR(1U)
53371 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
53372 #define F_TXDPRBSRST    V_TXDPRBSRST(1U)
53375 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
53376 #define F_TXDPRBSEN    V_TXDPRBSEN(1U)
53379 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
53380 #define F_RXCPRBSRST    V_RXCPRBSRST(1U)
53383 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
53384 #define F_RXCPRBSEN    V_RXCPRBSEN(1U)
53387 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
53388 #define F_RXCPRBSFRCERR    V_RXCPRBSFRCERR(1U)
53391 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
53392 #define F_TXCPRBSRST    V_TXCPRBSRST(1U)
53395 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
53396 #define F_TXCPRBSEN    V_TXCPRBSEN(1U)
53399 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
53400 #define F_RXBPRBSRST    V_RXBPRBSRST(1U)
53403 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
53404 #define F_RXBPRBSEN    V_RXBPRBSEN(1U)
53407 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
53408 #define F_RXBPRBSFRCERR    V_RXBPRBSFRCERR(1U)
53411 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
53412 #define F_TXBPRBSRST    V_TXBPRBSRST(1U)
53415 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
53416 #define F_TXBPRBSEN    V_TXBPRBSEN(1U)
53419 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
53420 #define F_RXAPRBSRST    V_RXAPRBSRST(1U)
53423 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
53424 #define F_RXAPRBSEN    V_RXAPRBSEN(1U)
53427 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
53428 #define F_RXAPRBSFRCERR    V_RXAPRBSFRCERR(1U)
53430 #define S_TXAPRBSRST    1
53431 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
53432 #define F_TXAPRBSRST    V_TXAPRBSRST(1U)
53435 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
53436 #define F_TXAPRBSEN    V_TXAPRBSEN(1U)
53441 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
53442 #define F_RXDDATASYNC    V_RXDDATASYNC(1U)
53445 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
53446 #define F_RXCDATASYNC    V_RXCDATASYNC(1U)
53449 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
53450 #define F_RXBDATASYNC    V_RXBDATASYNC(1U)
53453 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
53454 #define F_RXADATASYNC    V_RXADATASYNC(1U)
53457 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
53458 #define F_RXDEARLYIN    V_RXDEARLYIN(1U)
53461 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
53462 #define F_RXDLATEIN    V_RXDLATEIN(1U)
53465 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
53466 #define F_RXDPHSLOCK    V_RXDPHSLOCK(1U)
53469 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
53470 #define F_RXDPHSDNIN    V_RXDPHSDNIN(1U)
53473 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
53474 #define F_RXDPHSUPIN    V_RXDPHSUPIN(1U)
53477 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
53478 #define F_RXCEARLYIN    V_RXCEARLYIN(1U)
53481 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
53482 #define F_RXCLATEIN    V_RXCLATEIN(1U)
53485 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
53486 #define F_RXCPHSLOCK    V_RXCPHSLOCK(1U)
53489 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
53490 #define F_RXCPHSDNIN    V_RXCPHSDNIN(1U)
53493 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
53494 #define F_RXCPHSUPIN    V_RXCPHSUPIN(1U)
53497 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
53498 #define F_RXBEARLYIN    V_RXBEARLYIN(1U)
53501 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
53502 #define F_RXBLATEIN    V_RXBLATEIN(1U)
53505 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
53506 #define F_RXBPHSLOCK    V_RXBPHSLOCK(1U)
53509 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
53510 #define F_RXBPHSDNIN    V_RXBPHSDNIN(1U)
53513 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
53514 #define F_RXBPHSUPIN    V_RXBPHSUPIN(1U)
53517 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
53518 #define F_RXAEARLYIN    V_RXAEARLYIN(1U)
53521 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
53522 #define F_RXALATEIN    V_RXALATEIN(1U)
53525 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
53526 #define F_RXAPHSLOCK    V_RXAPHSLOCK(1U)
53528 #define S_RXAPHSDNIN    1
53529 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
53530 #define F_RXAPHSDNIN    V_RXAPHSDNIN(1U)
53533 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
53534 #define F_RXAPHSUPIN    V_RXAPHSUPIN(1U)
53539 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
53540 #define F_RXDPRBSSYNC    V_RXDPRBSSYNC(1U)
53543 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
53544 #define F_RXCPRBSSYNC    V_RXCPRBSSYNC(1U)
53547 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
53548 #define F_RXBPRBSSYNC    V_RXBPRBSSYNC(1U)
53551 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
53552 #define F_RXAPRBSSYNC    V_RXAPRBSSYNC(1U)
53555 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
53556 #define F_RXDPRBSERR    V_RXDPRBSERR(1U)
53559 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
53560 #define F_RXCPRBSERR    V_RXCPRBSERR(1U)
53563 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
53564 #define F_RXBPRBSERR    V_RXBPRBSERR(1U)
53567 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
53568 #define F_RXAPRBSERR    V_RXAPRBSERR(1U)
53571 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
53572 #define F_RXDSIGDET    V_RXDSIGDET(1U)
53575 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
53576 #define F_RXCSIGDET    V_RXCSIGDET(1U)
53579 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
53580 #define F_RXBSIGDET    V_RXBSIGDET(1U)
53583 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
53584 #define F_RXASIGDET    V_RXASIGDET(1U)
53586 #define S_HSSPLLLOCK    1
53587 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
53588 #define F_HSSPLLLOCK    V_HSSPLLLOCK(1U)
53591 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
53592 #define F_HSSPRTREADY    V_HSSPRTREADY(1U)
53597 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
53598 #define F_SENDPAUSE    V_SENDPAUSE(1U)
53600 #define S_SENDZEROPAUSE    1
53601 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
53602 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
53605 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
53606 #define F_XGM_TXEN    V_XGM_TXEN(1U)
53612 #define V_CRCCAL(x) ((x) << S_CRCCAL)
53613 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
53616 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
53617 #define F_DISDEFIDLECNT    V_DISDEFIDLECNT(1U)
53620 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
53621 #define F_DECAVGTXIPG    V_DECAVGTXIPG(1U)
53624 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
53625 #define F_UNIDIRTXEN    V_UNIDIRTXEN(1U)
53629 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
53630 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
53632 #define S_STRETCHMODE    1
53633 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
53634 #define F_STRETCHMODE    V_STRETCHMODE(1U)
53637 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
53638 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
53644 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
53645 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
53652 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
53653 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
53656 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
53657 #define F_STATLOCALFAULT    V_STATLOCALFAULT(1U)
53660 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
53661 #define F_STATREMOTEFAULT    V_STATREMOTEFAULT(1U)
53664 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
53665 #define F_LENERRFRAMEDIS    V_LENERRFRAMEDIS(1U)
53668 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
53669 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
53672 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
53673 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
53676 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
53677 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
53680 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
53681 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
53684 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
53685 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
53688 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
53689 #define F_ENJUMBO    V_ENJUMBO(1U)
53692 #define V_RMFCS(x) ((x) << S_RMFCS)
53693 #define F_RMFCS    V_RMFCS(1U)
53696 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
53697 #define F_DISNONVLAN    V_DISNONVLAN(1U)
53700 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
53701 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
53704 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
53705 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
53708 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
53709 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
53711 #define S_DISBCAST    1
53712 #define V_DISBCAST(x) ((x) << S_DISBCAST)
53713 #define F_DISBCAST    V_DISBCAST(1U)
53716 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
53717 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
53726 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
53727 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
53746 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
53747 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
53751 #define V_TYPE(x) ((x) << S_TYPE)
53752 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
53760 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
53761 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
53764 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
53765 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
53768 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
53769 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
53772 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
53773 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
53776 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
53777 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
53780 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
53781 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
53784 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
53785 #define F_STATOFLOW    V_STATOFLOW(1U)
53788 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
53789 #define F_TXERRFIFO    V_TXERRFIFO(1U)
53792 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
53793 #define F_TXUFLOW    V_TXUFLOW(1U)
53795 #define S_FRAMETXMT    1
53796 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
53797 #define F_FRAMETXMT    V_FRAMETXMT(1U)
53800 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
53801 #define F_FRAMERCVD    V_FRAMERCVD(1U)
53810 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
53811 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
53816 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
53817 #define F_READSNPSHOT    V_READSNPSHOT(1U)
53820 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
53821 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
53824 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
53825 #define F_CLRSTATS    V_CLRSTATS(1U)
53827 #define S_INCRSTATS    1
53828 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
53829 #define F_INCRSTATS    V_INCRSTATS(1U)
53832 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
53833 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
53839 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
53840 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
53844 #define V_OPERATION(x) ((x) << S_OPERATION)
53845 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
53849 #define V_PORTADDR(x) ((x) << S_PORTADDR)
53850 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
53854 #define V_DEVADDR(x) ((x) << S_DEVADDR)
53855 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
53859 #define V_RESRV(x) ((x) << S_RESRV)
53860 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
53864 #define V_DATA(x) ((x) << S_DATA)
53865 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
53871 #define V_MODULEID(x) ((x) << S_MODULEID)
53872 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
53876 #define V_MODULEREV(x) ((x) << S_MODULEREV)
53877 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
53884 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
53885 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
53892 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
53893 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
53911 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
53912 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
53919 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
53920 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
53928 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
53929 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
53942 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
53943 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
53949 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
53950 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
53956 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
53957 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
53963 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
53964 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
53970 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
53971 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
53977 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
53978 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
53984 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
53985 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
53989 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
53990 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
53994 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
53995 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
53998 #define V_TEST_EN(x) ((x) << S_TEST_EN)
53999 #define F_TEST_EN    V_TEST_EN(1U)
54005 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
54006 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
54009 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
54010 #define F_LANE3_CTC_STATUS    V_LANE3_CTC_STATUS(1U)
54013 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
54014 #define F_LANE2_CTC_STATUS    V_LANE2_CTC_STATUS(1U)
54017 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
54018 #define F_LANE1_CTC_STATUS    V_LANE1_CTC_STATUS(1U)
54021 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
54022 #define F_LANE0_CTC_STATUS    V_LANE0_CTC_STATUS(1U)
54025 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
54026 #define F_ALIGN_STATUS    V_ALIGN_STATUS(1U)
54029 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
54030 #define F_LANE3_SYNC_STATUS    V_LANE3_SYNC_STATUS(1U)
54033 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
54034 #define F_LANE2_SYNC_STATUS    V_LANE2_SYNC_STATUS(1U)
54036 #define S_LANE1_SYNC_STATUS    1
54037 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
54038 #define F_LANE1_SYNC_STATUS    V_LANE1_SYNC_STATUS(1U)
54041 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
54042 #define F_LANE0_SYNC_STATUS    V_LANE0_SYNC_STATUS(1U)
54047 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
54048 #define F_RX_CLK_SPEED    V_RX_CLK_SPEED(1U)
54051 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
54052 #define F_SCRBYPASS    V_SCRBYPASS(1U)
54055 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
54056 #define F_FECERRINDEN    V_FECERRINDEN(1U)
54059 #define V_FECEN(x) ((x) << S_FECEN)
54060 #define F_FECEN    V_FECEN(1U)
54064 #define V_TESTSEL(x) ((x) << S_TESTSEL)
54065 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
54067 #define S_SCRLOOPEN    1
54068 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
54069 #define F_SCRLOOPEN    V_SCRLOOPEN(1U)
54072 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
54073 #define F_XGMIILOOPEN    V_XGMIILOOPEN(1U)
54078 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
54079 #define F_TX_PRBS9_EN    V_TX_PRBS9_EN(1U)
54082 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
54083 #define F_TX_PRBS31_EN    V_TX_PRBS31_EN(1U)
54086 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
54087 #define F_TX_TST_DAT_SEL    V_TX_TST_DAT_SEL(1U)
54089 #define S_TX_TST_SEL    1
54090 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
54091 #define F_TX_TST_SEL    V_TX_TST_SEL(1U)
54094 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
54095 #define F_TX_TST_EN    V_TX_TST_EN(1U)
54102 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
54103 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
54110 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
54111 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
54116 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
54117 #define F_TPTER_CNT_RST    V_TPTER_CNT_RST(1U)
54120 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
54121 #define F_TEST_CNT_125US    V_TEST_CNT_125US(1U)
54124 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
54125 #define F_TEST_CNT_PRE    V_TEST_CNT_PRE(1U)
54128 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
54129 #define F_BER_CNT_RST    V_BER_CNT_RST(1U)
54132 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
54133 #define F_ERR_BLK_CNT_RST    V_ERR_BLK_CNT_RST(1U)
54136 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
54137 #define F_RX_PRBS31_EN    V_RX_PRBS31_EN(1U)
54139 #define S_RX_TST_DAT_SEL    1
54140 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
54141 #define F_RX_TST_DAT_SEL    V_RX_TST_DAT_SEL(1U)
54144 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
54145 #define F_RX_TST_EN    V_RX_TST_EN(1U)
54151 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
54152 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
54156 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
54157 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
54160 #define V_HI_BER(x) ((x) << S_HI_BER)
54161 #define F_HI_BER    V_HI_BER(1U)
54163 #define S_RX_FAULT    1
54164 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
54165 #define F_RX_FAULT    V_RX_FAULT(1U)
54168 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
54169 #define F_TX_FAULT    V_TX_FAULT(1U)
54175 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
54176 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
54181 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
54182 #define F_SOFT_RESET    V_SOFT_RESET(1U)
54185 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
54186 #define F_AN_ENABLE    V_AN_ENABLE(1U)
54189 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
54190 #define F_RESTART_AN    V_RESTART_AN(1U)
54195 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
54196 #define F_NONCER_MATCH    V_NONCER_MATCH(1U)
54199 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
54200 #define F_PARALLEL_DET_FAULT    V_PARALLEL_DET_FAULT(1U)
54203 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
54204 #define F_PAGE_RECEIVED    V_PAGE_RECEIVED(1U)
54207 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
54208 #define F_AN_COMPLETE    V_AN_COMPLETE(1U)
54211 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
54212 #define F_STAT_REMFAULT    V_STAT_REMFAULT(1U)
54215 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
54216 #define F_AN_ABILITY    V_AN_ABILITY(1U)
54219 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
54220 #define F_LINK_STATUS    V_LINK_STATUS(1U)
54223 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
54224 #define F_PARTNER_AN_ABILITY    V_PARTNER_AN_ABILITY(1U)
54229 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
54230 #define F_FEC_ENABLE    V_FEC_ENABLE(1U)
54233 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
54234 #define F_FEC_ABILITY    V_FEC_ABILITY(1U)
54237 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
54238 #define F_10GBASE_KR_CAPABLE    V_10GBASE_KR_CAPABLE(1U)
54241 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
54242 #define F_10GBASE_KX4_CAPABLE    V_10GBASE_KX4_CAPABLE(1U)
54245 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
54246 #define F_1000BASE_KX_CAPABLE    V_1000BASE_KX_CAPABLE(1U)
54250 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
54251 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
54254 #define V_NP(x) ((x) << S_NP)
54255 #define F_NP    V_NP(1U)
54258 #define V_ACK(x) ((x) << S_ACK)
54259 #define F_ACK    V_ACK(1U)
54262 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
54263 #define F_REMOTE_FAULT    V_REMOTE_FAULT(1U)
54266 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
54267 #define F_ASM_DIR    V_ASM_DIR(1U)
54270 #define V_PAUSE(x) ((x) << S_PAUSE)
54271 #define F_PAUSE    V_PAUSE(1U)
54275 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
54276 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
54282 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
54283 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
54289 #define V_NP_INFO(x) ((x) << S_NP_INFO)
54290 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
54293 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
54294 #define F_NP_INDICATION    V_NP_INDICATION(1U)
54297 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
54298 #define F_MESSAGE_PAGE    V_MESSAGE_PAGE(1U)
54301 #define V_ACK_2(x) ((x) << S_ACK_2)
54302 #define F_ACK_2    V_ACK_2(1U)
54305 #define V_TOGGLE(x) ((x) << S_TOGGLE)
54306 #define F_TOGGLE    V_TOGGLE(1U)
54312 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
54313 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
54320 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
54321 #define F_TX_PAUSE_OKAY    V_TX_PAUSE_OKAY(1U)
54324 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
54325 #define F_RX_PAUSE_OKAY    V_RX_PAUSE_OKAY(1U)
54328 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
54329 #define F_10GBASE_KR_FEC_NEG    V_10GBASE_KR_FEC_NEG(1U)
54332 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
54333 #define F_10GBASE_KR_NEG    V_10GBASE_KR_NEG(1U)
54336 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
54337 #define F_10GBASE_KX4_NEG    V_10GBASE_KX4_NEG(1U)
54339 #define S_1000BASE_KX_NEG    1
54340 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
54341 #define F_1000BASE_KX_NEG    V_1000BASE_KX_NEG(1U)
54344 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
54345 #define F_BP_AN_ABILITY    V_BP_AN_ABILITY(1U)
54350 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
54351 #define F_BYPASS_LFSR    V_BYPASS_LFSR(1U)
54355 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
54356 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
54361 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
54362 #define F_NP_FROM_LP    V_NP_FROM_LP(1U)
54365 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
54366 #define F_PARALLELDETFAULTINT    V_PARALLELDETFAULTINT(1U)
54368 #define S_BP_FROM_LP    1
54369 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
54370 #define F_BP_FROM_LP    V_BP_FROM_LP(1U)
54373 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
54374 #define F_PCS_AN_COMPLETE    V_PCS_AN_COMPLETE(1U)
54380 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
54381 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
54387 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
54388 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
54394 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
54395 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
54399 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
54400 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
54405 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
54406 #define F_RXREQ_CPRE    V_RXREQ_CPRE(1U)
54409 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
54410 #define F_RXREQ_CINIT    V_RXREQ_CINIT(1U)
54414 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
54415 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
54419 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
54420 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
54424 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
54425 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
54430 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
54431 #define F_RXSTAT_RDY    V_RXSTAT_RDY(1U)
54435 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
54436 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
54440 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
54441 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
54445 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
54446 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
54451 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
54452 #define F_TXREQ_CPRE    V_TXREQ_CPRE(1U)
54455 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
54456 #define F_TXREQ_CINIT    V_TXREQ_CINIT(1U)
54460 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
54461 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
54465 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
54466 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
54470 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
54471 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
54476 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
54477 #define F_TXSTAT_RDY    V_TXSTAT_RDY(1U)
54481 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
54482 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
54486 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
54487 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
54491 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
54492 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
54498 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
54499 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
54502 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
54503 #define F_MANUAL_RDY    V_MANUAL_RDY(1U)
54506 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
54507 #define F_MWT_DISABLE    V_MWT_DISABLE(1U)
54509 #define S_MDIO_OVR    1
54510 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
54511 #define F_MDIO_OVR    V_MDIO_OVR(1U)
54514 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
54515 #define F_STICKY_MODE    V_STICKY_MODE(1U)
54521 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
54522 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
54526 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
54527 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
54530 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
54531 #define F_PRBS_CHK_SYNC    V_PRBS_CHK_SYNC(1U)
54534 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
54535 #define F_PRBS_CHK_RST    V_PRBS_CHK_RST(1U)
54538 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
54539 #define F_PRBS_CHK_OFF    V_PRBS_CHK_OFF(1U)
54541 #define S_PRBS_GEN_FRCERR    1
54542 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
54543 #define F_PRBS_GEN_FRCERR    V_PRBS_GEN_FRCERR(1U)
54546 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
54547 #define F_PRBS_GEN_OFF    V_PRBS_GEN_OFF(1U)
54552 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
54553 #define F_FSM_TR_LCL    V_FSM_TR_LCL(1U)
54557 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
54558 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
54562 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
54563 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
54566 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
54567 #define F_FSM_TR_FAIL    V_FSM_TR_FAIL(1U)
54570 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
54571 #define F_FSM_TR_ACT    V_FSM_TR_ACT(1U)
54574 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
54575 #define F_FSM_FRM_LCK    V_FSM_FRM_LCK(1U)
54578 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
54579 #define F_FSM_TR_COMP    V_FSM_TR_COMP(1U)
54582 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
54583 #define F_MC_RX_RDY    V_MC_RX_RDY(1U)
54586 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
54587 #define F_FSM_CU_DIS    V_FSM_CU_DIS(1U)
54589 #define S_FSM_TR_RST    1
54590 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
54591 #define F_FSM_TR_RST    V_FSM_TR_RST(1U)
54594 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
54595 #define F_FSM_TR_EN    V_FSM_TR_EN(1U)
54601 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
54602 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
54606 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
54607 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
54611 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
54612 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
54616 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
54617 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
54621 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
54622 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
54627 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
54628 #define F_PMD_TX_DIS    V_PMD_TX_DIS(1U)
54632 #define S_TRAINING_ENABLE    1
54633 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
54634 #define F_TRAINING_ENABLE    V_TRAINING_ENABLE(1U)
54637 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
54638 #define F_RESTART_TRAINING    V_RESTART_TRAINING(1U)
54643 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
54644 #define F_PMD_SIGDET    V_PMD_SIGDET(1U)
54649 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
54650 #define F_TRAINING_FAILURE    V_TRAINING_FAILURE(1U)
54653 #define V_TRAINING(x) ((x) << S_TRAINING)
54654 #define F_TRAINING    V_TRAINING(1U)
54656 #define S_FRAME_LOCK    1
54657 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
54658 #define F_FRAME_LOCK    V_FRAME_LOCK(1U)
54661 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
54662 #define F_RX_TRAINED    V_RX_TRAINED(1U)
54668 #define V_BWSEL(x) ((x) << S_BWSEL)
54669 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
54673 #define V_RTSEL(x) ((x) << S_RTSEL)
54674 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
54679 #define V_TWDP(x) ((x) << S_TWDP)
54680 #define F_TWDP    V_TWDP(1U)
54683 #define V_TPGRST(x) ((x) << S_TPGRST)
54684 #define F_TPGRST    V_TPGRST(1U)
54687 #define V_TPGEN(x) ((x) << S_TPGEN)
54688 #define F_TPGEN    V_TPGEN(1U)
54692 #define V_TPSEL(x) ((x) << S_TPSEL)
54693 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
54698 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
54699 #define F_AEINVPOL    V_AEINVPOL(1U)
54702 #define V_AESOURCE(x) ((x) << S_AESOURCE)
54703 #define F_AESOURCE    V_AESOURCE(1U)
54706 #define V_EQMODE(x) ((x) << S_EQMODE)
54707 #define F_EQMODE    V_EQMODE(1U)
54710 #define V_OCOEF(x) ((x) << S_OCOEF)
54711 #define F_OCOEF    V_OCOEF(1U)
54714 #define V_COEFRST(x) ((x) << S_COEFRST)
54715 #define F_COEFRST    V_COEFRST(1U)
54717 #define S_SPEN    1
54718 #define V_SPEN(x) ((x) << S_SPEN)
54719 #define F_SPEN    V_SPEN(1U)
54722 #define V_ALOAD(x) ((x) << S_ALOAD)
54723 #define F_ALOAD    V_ALOAD(1U)
54728 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
54729 #define F_DRVOFFT    V_DRVOFFT(1U)
54733 #define V_SLEW(x) ((x) << S_SLEW)
54734 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
54738 #define V_FFE(x) ((x) << S_FFE)
54739 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
54744 #define V_VLINC(x) ((x) << S_VLINC)
54745 #define F_VLINC    V_VLINC(1U)
54748 #define V_VLDEC(x) ((x) << S_VLDEC)
54749 #define F_VLDEC    V_VLDEC(1U)
54752 #define V_LOPWR(x) ((x) << S_LOPWR)
54753 #define F_LOPWR    V_LOPWR(1U)
54756 #define V_TDMEN(x) ((x) << S_TDMEN)
54757 #define F_TDMEN    V_TDMEN(1U)
54760 #define V_DCCEN(x) ((x) << S_DCCEN)
54761 #define F_DCCEN    V_DCCEN(1U)
54764 #define V_VHSEL(x) ((x) << S_VHSEL)
54765 #define F_VHSEL    V_VHSEL(1U)
54769 #define V_IDAC(x) ((x) << S_IDAC)
54770 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
54776 #define V_STBY(x) ((x) << S_STBY)
54777 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
54783 #define V_PON(x) ((x) << S_PON)
54784 #define G_PON(x) (((x) >> S_PON) & M_PON)
54790 #define V_NXTT0(x) ((x) << S_NXTT0)
54791 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
54797 #define V_NXTT1(x) ((x) << S_NXTT1)
54798 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
54804 #define V_NXTT2(x) ((x) << S_NXTT2)
54805 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
54811 #define V_TXPWR(x) ((x) << S_TXPWR)
54812 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
54818 #define V_TXPOL(x) ((x) << S_TXPOL)
54819 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
54823 #define V_NTXPOL(x) ((x) << S_NTXPOL)
54824 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
54829 #define V_CXPRESET(x) ((x) << S_CXPRESET)
54830 #define F_CXPRESET    V_CXPRESET(1U)
54833 #define V_CXINIT(x) ((x) << S_CXINIT)
54834 #define F_CXINIT    V_CXINIT(1U)
54838 #define V_C2UPDT(x) ((x) << S_C2UPDT)
54839 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
54843 #define V_C1UPDT(x) ((x) << S_C1UPDT)
54844 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
54848 #define V_C0UPDT(x) ((x) << S_C0UPDT)
54849 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
54855 #define V_C2STAT(x) ((x) << S_C2STAT)
54856 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
54860 #define V_C1STAT(x) ((x) << S_C1STAT)
54861 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
54865 #define V_C0STAT(x) ((x) << S_C0STAT)
54866 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
54872 #define V_NIDAC0(x) ((x) << S_NIDAC0)
54873 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
54879 #define V_NIDAC1(x) ((x) << S_NIDAC1)
54880 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
54886 #define V_NIDAC2(x) ((x) << S_NIDAC2)
54887 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
54892 #define V_OPEN(x) ((x) << S_OPEN)
54893 #define F_OPEN    V_OPEN(1U)
54897 #define V_OPVAL(x) ((x) << S_OPVAL)
54898 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
54904 #define V_PDAC(x) ((x) << S_PDAC)
54905 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
54911 #define V_AIDAC0(x) ((x) << S_AIDAC0)
54912 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
54918 #define V_AIDAC1(x) ((x) << S_AIDAC1)
54919 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
54925 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
54926 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
54932 #define V_CURSD(x) ((x) << S_CURSD)
54933 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
54939 #define V_XDATA(x) ((x) << S_XDATA)
54940 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
54944 #define S_EXTADDR    1
54946 #define V_EXTADDR(x) ((x) << S_EXTADDR)
54947 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
54950 #define V_XWR(x) ((x) << S_XWR)
54951 #define F_XWR    V_XWR(1U)
54978 #define V_AIDAC2(x) ((x) << S_AIDAC2)
54979 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
54987 #define V_XADDR(x) ((x) << S_XADDR)
54988 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
54993 #define V_BW810(x) ((x) << S_BW810)
54994 #define F_BW810    V_BW810(1U)
54997 #define V_AUXCLK(x) ((x) << S_AUXCLK)
54998 #define F_AUXCLK    V_AUXCLK(1U)
55002 #define V_DMSEL(x) ((x) << S_DMSEL)
55003 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
55008 #define V_RCLKEN(x) ((x) << S_RCLKEN)
55009 #define F_RCLKEN    V_RCLKEN(1U)
55013 #define V_RRATE(x) ((x) << S_RRATE)
55014 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
55017 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
55018 #define F_LBFRCERROR    V_LBFRCERROR(1U)
55021 #define V_LBERROR(x) ((x) << S_LBERROR)
55022 #define F_LBERROR    V_LBERROR(1U)
55025 #define V_LBSYNC(x) ((x) << S_LBSYNC)
55026 #define F_LBSYNC    V_LBSYNC(1U)
55029 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
55030 #define F_FDWRAPCLK    V_FDWRAPCLK(1U)
55033 #define V_FDWRAP(x) ((x) << S_FDWRAP)
55034 #define F_FDWRAP    V_FDWRAP(1U)
55037 #define V_PRST(x) ((x) << S_PRST)
55038 #define F_PRST    V_PRST(1U)
55041 #define V_PCHKEN(x) ((x) << S_PCHKEN)
55042 #define F_PCHKEN    V_PCHKEN(1U)
55046 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
55047 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
55053 #define V_FTHROT(x) ((x) << S_FTHROT)
55054 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
55057 #define V_RTHROT(x) ((x) << S_RTHROT)
55058 #define F_RTHROT    V_RTHROT(1U)
55062 #define V_FILTCTL(x) ((x) << S_FILTCTL)
55063 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
55067 #define V_RSRVO(x) ((x) << S_RSRVO)
55068 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
55071 #define V_EXTEL(x) ((x) << S_EXTEL)
55072 #define F_EXTEL    V_EXTEL(1U)
55075 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
55076 #define F_RSTONSTUCK    V_RSTONSTUCK(1U)
55079 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
55080 #define F_FREEZEFW    V_FREEZEFW(1U)
55082 #define S_RESETFW    1
55083 #define V_RESETFW(x) ((x) << S_RESETFW)
55084 #define F_RESETFW    V_RESETFW(1U)
55087 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
55088 #define F_SSCENABLE    V_SSCENABLE(1U)
55093 #define V_RSNP(x) ((x) << S_RSNP)
55094 #define F_RSNP    V_RSNP(1U)
55097 #define V_TSOEN(x) ((x) << S_TSOEN)
55098 #define F_TSOEN    V_TSOEN(1U)
55101 #define V_OFFEN(x) ((x) << S_OFFEN)
55102 #define F_OFFEN    V_OFFEN(1U)
55106 #define V_TMSCAL(x) ((x) << S_TMSCAL)
55107 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
55110 #define V_APADJ(x) ((x) << S_APADJ)
55111 #define F_APADJ    V_APADJ(1U)
55114 #define V_RSEL(x) ((x) << S_RSEL)
55115 #define F_RSEL    V_RSEL(1U)
55119 #define V_PHOFFS(x) ((x) << S_PHOFFS)
55120 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
55126 #define V_ROT0A(x) ((x) << S_ROT0A)
55127 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
55131 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
55132 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
55138 #define V_ROT90(x) ((x) << S_ROT90)
55139 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
55144 #define V_RCALER(x) ((x) << S_RCALER)
55145 #define F_RCALER    V_RCALER(1U)
55149 #define V_RAOOFF(x) ((x) << S_RAOOFF)
55150 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
55154 #define V_RAEOFF(x) ((x) << S_RAEOFF)
55155 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
55159 #define V_RDOFF(x) ((x) << S_RDOFF)
55160 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
55166 #define V_SIGNSD(x) ((x) << S_SIGNSD)
55167 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
55171 #define V_DACSD(x) ((x) << S_DACSD)
55172 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
55175 #define V_SDPDN(x) ((x) << S_SDPDN)
55176 #define F_SDPDN    V_SDPDN(1U)
55179 #define V_SIGDET(x) ((x) << S_SIGDET)
55180 #define F_SIGDET    V_SIGDET(1U)
55184 #define V_SDLVL(x) ((x) << S_SDLVL)
55185 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
55190 #define V_REQCMP(x) ((x) << S_REQCMP)
55191 #define F_REQCMP    V_REQCMP(1U)
55194 #define V_DFEREQ(x) ((x) << S_DFEREQ)
55195 #define F_DFEREQ    V_DFEREQ(1U)
55198 #define V_SPCEN(x) ((x) << S_SPCEN)
55199 #define F_SPCEN    V_SPCEN(1U)
55202 #define V_GATEEN(x) ((x) << S_GATEEN)
55203 #define F_GATEEN    V_GATEEN(1U)
55207 #define V_SPIFMT(x) ((x) << S_SPIFMT)
55208 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
55212 #define V_DFEPWR(x) ((x) << S_DFEPWR)
55213 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
55216 #define V_STNDBY(x) ((x) << S_STNDBY)
55217 #define F_STNDBY    V_STNDBY(1U)
55220 #define V_FRCH(x) ((x) << S_FRCH)
55221 #define F_FRCH    V_FRCH(1U)
55224 #define V_NONRND(x) ((x) << S_NONRND)
55225 #define F_NONRND    V_NONRND(1U)
55228 #define V_NONRNF(x) ((x) << S_NONRNF)
55229 #define F_NONRNF    V_NONRNF(1U)
55231 #define S_FSTLCK    1
55232 #define V_FSTLCK(x) ((x) << S_FSTLCK)
55233 #define F_FSTLCK    V_FSTLCK(1U)
55236 #define V_DFERST(x) ((x) << S_DFERST)
55237 #define F_DFERST    V_DFERST(1U)
55243 #define V_ESAMP(x) ((x) << S_ESAMP)
55244 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
55248 #define V_DSAMP(x) ((x) << S_DSAMP)
55249 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
55255 #define V_SMODE(x) ((x) << S_SMODE)
55256 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
55259 #define V_ADCORR(x) ((x) << S_ADCORR)
55260 #define F_ADCORR    V_ADCORR(1U)
55263 #define V_TRAINEN(x) ((x) << S_TRAINEN)
55264 #define F_TRAINEN    V_TRAINEN(1U)
55268 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
55269 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
55273 #define V_ASAMP(x) ((x) << S_ASAMP)
55274 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
55280 #define V_POLE(x) ((x) << S_POLE)
55281 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
55285 #define V_PEAK(x) ((x) << S_PEAK)
55286 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
55290 #define V_VOFFSN(x) ((x) << S_VOFFSN)
55291 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
55295 #define V_VOFFA(x) ((x) << S_VOFFA)
55296 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
55301 #define V_SHORTV(x) ((x) << S_SHORTV)
55302 #define F_SHORTV    V_SHORTV(1U)
55306 #define V_VGAIN(x) ((x) << S_VGAIN)
55307 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
55312 #define V_HBND1(x) ((x) << S_HBND1)
55313 #define F_HBND1    V_HBND1(1U)
55316 #define V_HBND0(x) ((x) << S_HBND0)
55317 #define F_HBND0    V_HBND0(1U)
55320 #define V_VLCKD(x) ((x) << S_VLCKD)
55321 #define F_VLCKD    V_VLCKD(1U)
55324 #define V_VLCKDF(x) ((x) << S_VLCKDF)
55325 #define F_VLCKDF    V_VLCKDF(1U)
55329 #define V_AMAXT(x) ((x) << S_AMAXT)
55330 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
55336 #define V_D01SN(x) ((x) << S_D01SN)
55337 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
55341 #define V_D01AMP(x) ((x) << S_D01AMP)
55342 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
55346 #define V_D00SN(x) ((x) << S_D00SN)
55347 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
55351 #define V_D00AMP(x) ((x) << S_D00AMP)
55352 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
55358 #define V_D11SN(x) ((x) << S_D11SN)
55359 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
55363 #define V_D11AMP(x) ((x) << S_D11AMP)
55364 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
55368 #define V_D10SN(x) ((x) << S_D10SN)
55369 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
55373 #define V_D10AMP(x) ((x) << S_D10AMP)
55374 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
55380 #define V_E1SN(x) ((x) << S_E1SN)
55381 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
55385 #define V_E1AMP(x) ((x) << S_E1AMP)
55386 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
55390 #define V_E0SN(x) ((x) << S_E0SN)
55391 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
55395 #define V_E0AMP(x) ((x) << S_E0AMP)
55396 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
55402 #define V_AOFFO(x) ((x) << S_AOFFO)
55403 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
55407 #define V_AOFFE(x) ((x) << S_AOFFE)
55408 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
55414 #define V_DACAN(x) ((x) << S_DACAN)
55415 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
55419 #define V_DACAP(x) ((x) << S_DACAP)
55420 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
55426 #define V_DACAZ(x) ((x) << S_DACAZ)
55427 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
55431 #define V_DACAM(x) ((x) << S_DACAM)
55432 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
55438 #define V_ADSN(x) ((x) << S_ADSN)
55439 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
55443 #define V_ADMAG(x) ((x) << S_ADMAG)
55444 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
55449 #define V_BLKAZ(x) ((x) << S_BLKAZ)
55450 #define F_BLKAZ    V_BLKAZ(1U)
55454 #define V_WIDTH(x) ((x) << S_WIDTH)
55455 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
55459 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
55460 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
55464 #define V_MINAMP(x) ((x) << S_MINAMP)
55465 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
55470 #define V_EMBRDY(x) ((x) << S_EMBRDY)
55471 #define F_EMBRDY    V_EMBRDY(1U)
55474 #define V_EMBUMP(x) ((x) << S_EMBUMP)
55475 #define F_EMBUMP    V_EMBUMP(1U)
55479 #define V_EMMD(x) ((x) << S_EMMD)
55480 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
55482 #define S_EMPAT    1
55483 #define V_EMPAT(x) ((x) << S_EMPAT)
55484 #define F_EMPAT    V_EMPAT(1U)
55487 #define V_EMEN(x) ((x) << S_EMEN)
55488 #define F_EMEN    V_EMEN(1U)
55494 #define V_H1OSN(x) ((x) << S_H1OSN)
55495 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
55499 #define V_H1OMAG(x) ((x) << S_H1OMAG)
55500 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
55504 #define V_H1ESN(x) ((x) << S_H1ESN)
55505 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
55509 #define V_H1EMAG(x) ((x) << S_H1EMAG)
55510 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
55516 #define V_H2OSN(x) ((x) << S_H2OSN)
55517 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
55521 #define V_H2OMAG(x) ((x) << S_H2OMAG)
55522 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
55526 #define V_H2ESN(x) ((x) << S_H2ESN)
55527 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
55531 #define V_H2EMAG(x) ((x) << S_H2EMAG)
55532 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
55538 #define V_H3OSN(x) ((x) << S_H3OSN)
55539 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
55543 #define V_H3OMAG(x) ((x) << S_H3OMAG)
55544 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
55548 #define V_H3ESN(x) ((x) << S_H3ESN)
55549 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
55553 #define V_H3EMAG(x) ((x) << S_H3EMAG)
55554 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
55560 #define V_H4OSN(x) ((x) << S_H4OSN)
55561 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
55565 #define V_H4OMAG(x) ((x) << S_H4OMAG)
55566 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
55570 #define V_H4ESN(x) ((x) << S_H4ESN)
55571 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
55575 #define V_H4EMAG(x) ((x) << S_H4EMAG)
55576 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
55582 #define V_H5OSN(x) ((x) << S_H5OSN)
55583 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
55587 #define V_H5OMAG(x) ((x) << S_H5OMAG)
55588 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
55592 #define V_H5ESN(x) ((x) << S_H5ESN)
55593 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
55597 #define V_H5EMAG(x) ((x) << S_H5EMAG)
55598 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
55603 #define V_DPCCVG(x) ((x) << S_DPCCVG)
55604 #define F_DPCCVG    V_DPCCVG(1U)
55607 #define V_DACCVG(x) ((x) << S_DACCVG)
55608 #define F_DACCVG    V_DACCVG(1U)
55612 #define V_DPCTGT(x) ((x) << S_DPCTGT)
55613 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
55616 #define V_BLKH1T(x) ((x) << S_BLKH1T)
55617 #define F_BLKH1T    V_BLKH1T(1U)
55620 #define V_BLKOAE(x) ((x) << S_BLKOAE)
55621 #define F_BLKOAE    V_BLKOAE(1U)
55625 #define V_H1TGT(x) ((x) << S_H1TGT)
55626 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
55630 #define V_OAE(x) ((x) << S_OAE)
55631 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
55637 #define V_OLS(x) ((x) << S_OLS)
55638 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
55642 #define V_OES(x) ((x) << S_OES)
55643 #define G_OES(x) (((x) >> S_OES) & M_OES)
55646 #define V_BLKODEC(x) ((x) << S_BLKODEC)
55647 #define F_BLKODEC    V_BLKODEC(1U)
55651 #define V_ODEC(x) ((x) << S_ODEC)
55652 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
55657 #define V_BER6(x) ((x) << S_BER6)
55658 #define F_BER6    V_BER6(1U)
55661 #define V_BER6VAL(x) ((x) << S_BER6VAL)
55662 #define F_BER6VAL    V_BER6VAL(1U)
55665 #define V_BER3VAL(x) ((x) << S_BER3VAL)
55666 #define F_BER3VAL    V_BER3VAL(1U)
55669 #define V_DPCCMP(x) ((x) << S_DPCCMP)
55670 #define F_DPCCMP    V_DPCCMP(1U)
55673 #define V_DACCMP(x) ((x) << S_DACCMP)
55674 #define F_DACCMP    V_DACCMP(1U)
55677 #define V_DDCCMP(x) ((x) << S_DDCCMP)
55678 #define F_DDCCMP    V_DDCCMP(1U)
55681 #define V_AERRFLG(x) ((x) << S_AERRFLG)
55682 #define F_AERRFLG    V_AERRFLG(1U)
55685 #define V_WERRFLG(x) ((x) << S_WERRFLG)
55686 #define F_WERRFLG    V_WERRFLG(1U)
55689 #define V_TRCMP(x) ((x) << S_TRCMP)
55690 #define F_TRCMP    V_TRCMP(1U)
55693 #define V_VLCKF(x) ((x) << S_VLCKF)
55694 #define F_VLCKF    V_VLCKF(1U)
55697 #define V_ROCADJ(x) ((x) << S_ROCADJ)
55698 #define F_ROCADJ    V_ROCADJ(1U)
55700 #define S_ROCCMP    1
55701 #define V_ROCCMP(x) ((x) << S_ROCCMP)
55702 #define F_ROCCMP    V_ROCCMP(1U)
55705 #define V_OCCMP(x) ((x) << S_OCCMP)
55706 #define F_OCCMP    V_OCCMP(1U)
55711 #define V_FDPC(x) ((x) << S_FDPC)
55712 #define F_FDPC    V_FDPC(1U)
55715 #define V_FDAC(x) ((x) << S_FDAC)
55716 #define F_FDAC    V_FDAC(1U)
55719 #define V_FDDC(x) ((x) << S_FDDC)
55720 #define F_FDDC    V_FDDC(1U)
55723 #define V_FNRND(x) ((x) << S_FNRND)
55724 #define F_FNRND    V_FNRND(1U)
55727 #define V_FVGAIN(x) ((x) << S_FVGAIN)
55728 #define F_FVGAIN    V_FVGAIN(1U)
55731 #define V_FVOFF(x) ((x) << S_FVOFF)
55732 #define F_FVOFF    V_FVOFF(1U)
55735 #define V_FSDET(x) ((x) << S_FSDET)
55736 #define F_FSDET    V_FSDET(1U)
55739 #define V_FBER6(x) ((x) << S_FBER6)
55740 #define F_FBER6    V_FBER6(1U)
55743 #define V_FROTO(x) ((x) << S_FROTO)
55744 #define F_FROTO    V_FROTO(1U)
55747 #define V_FH4H5(x) ((x) << S_FH4H5)
55748 #define F_FH4H5    V_FH4H5(1U)
55751 #define V_FH2H3(x) ((x) << S_FH2H3)
55752 #define F_FH2H3    V_FH2H3(1U)
55755 #define V_FH1(x) ((x) << S_FH1)
55756 #define F_FH1    V_FH1(1U)
55759 #define V_FH1SN(x) ((x) << S_FH1SN)
55760 #define F_FH1SN    V_FH1SN(1U)
55763 #define V_FNRDF(x) ((x) << S_FNRDF)
55764 #define F_FNRDF    V_FNRDF(1U)
55767 #define V_FADAC(x) ((x) << S_FADAC)
55768 #define F_FADAC    V_FADAC(1U)
55920 #define V_BSELO(x) ((x) << S_BSELO)
55921 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
55926 #define V_LDET(x) ((x) << S_LDET)
55927 #define F_LDET    V_LDET(1U)
55930 #define V_CCERR(x) ((x) << S_CCERR)
55931 #define F_CCERR    V_CCERR(1U)
55934 #define V_CCCMP(x) ((x) << S_CCCMP)
55935 #define F_CCCMP    V_CCCMP(1U)
55941 #define V_BSELI(x) ((x) << S_BSELI)
55942 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
55947 #define V_VISEL(x) ((x) << S_VISEL)
55948 #define F_VISEL    V_VISEL(1U)
55951 #define V_FMIN(x) ((x) << S_FMIN)
55952 #define F_FMIN    V_FMIN(1U)
55955 #define V_FMAX(x) ((x) << S_FMAX)
55956 #define F_FMAX    V_FMAX(1U)
55958 #define S_CVHOLD    1
55959 #define V_CVHOLD(x) ((x) << S_CVHOLD)
55960 #define F_CVHOLD    V_CVHOLD(1U)
55963 #define V_TCDIS(x) ((x) << S_TCDIS)
55964 #define F_TCDIS    V_TCDIS(1U)
55969 #define V_CMETH(x) ((x) << S_CMETH)
55970 #define F_CMETH    V_CMETH(1U)
55972 #define S_RECAL    1
55973 #define V_RECAL(x) ((x) << S_RECAL)
55974 #define F_RECAL    V_RECAL(1U)
55977 #define V_CCLD(x) ((x) << S_CCLD)
55978 #define F_CCLD    V_CCLD(1U)
55984 #define V_ATST(x) ((x) << S_ATST)
55985 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
55990 #define V_RXDEN(x) ((x) << S_RXDEN)
55991 #define F_RXDEN    V_RXDEN(1U)
55994 #define V_RXCEN(x) ((x) << S_RXCEN)
55995 #define F_RXCEN    V_RXCEN(1U)
55998 #define V_TXDEN(x) ((x) << S_TXDEN)
55999 #define F_TXDEN    V_TXDEN(1U)
56002 #define V_TXCEN(x) ((x) << S_TXCEN)
56003 #define F_TXCEN    V_TXCEN(1U)
56006 #define V_RXBEN(x) ((x) << S_RXBEN)
56007 #define F_RXBEN    V_RXBEN(1U)
56010 #define V_RXAEN(x) ((x) << S_RXAEN)
56011 #define F_RXAEN    V_RXAEN(1U)
56013 #define S_TXBEN    1
56014 #define V_TXBEN(x) ((x) << S_TXBEN)
56015 #define F_TXBEN    V_TXBEN(1U)
56018 #define V_TXAEN(x) ((x) << S_TXAEN)
56019 #define F_TXAEN    V_TXAEN(1U)
56024 #define V_RXDRST(x) ((x) << S_RXDRST)
56025 #define F_RXDRST    V_RXDRST(1U)
56028 #define V_RXCRST(x) ((x) << S_RXCRST)
56029 #define F_RXCRST    V_RXCRST(1U)
56032 #define V_TXDRST(x) ((x) << S_TXDRST)
56033 #define F_TXDRST    V_TXDRST(1U)
56036 #define V_TXCRST(x) ((x) << S_TXCRST)
56037 #define F_TXCRST    V_TXCRST(1U)
56040 #define V_RXBRST(x) ((x) << S_RXBRST)
56041 #define F_RXBRST    V_RXBRST(1U)
56044 #define V_RXARST(x) ((x) << S_RXARST)
56045 #define F_RXARST    V_RXARST(1U)
56047 #define S_TXBRST    1
56048 #define V_TXBRST(x) ((x) << S_TXBRST)
56049 #define F_TXBRST    V_TXBRST(1U)
56052 #define V_TXARST(x) ((x) << S_TXARST)
56053 #define F_TXARST    V_TXARST(1U)
56058 #define V_ENCPIS(x) ((x) << S_ENCPIS)
56059 #define F_ENCPIS    V_ENCPIS(1U)
56063 #define V_CPISEL(x) ((x) << S_CPISEL)
56064 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
56070 #define V_BGCTL(x) ((x) << S_BGCTL)
56071 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
56076 #define V_LFREQ2(x) ((x) << S_LFREQ2)
56077 #define F_LFREQ2    V_LFREQ2(1U)
56080 #define V_LFREQ1(x) ((x) << S_LFREQ1)
56081 #define F_LFREQ1    V_LFREQ1(1U)
56083 #define S_LFREQO    1
56084 #define V_LFREQO(x) ((x) << S_LFREQO)
56085 #define F_LFREQO    V_LFREQO(1U)
56088 #define V_LFSEL(x) ((x) << S_LFSEL)
56089 #define F_LFSEL    V_LFSEL(1U)
56094 #define V_PFVAL(x) ((x) << S_PFVAL)
56095 #define F_PFVAL    V_PFVAL(1U)
56097 #define S_PFEN    1
56098 #define V_PFEN(x) ((x) << S_PFEN)
56099 #define F_PFEN    V_PFEN(1U)
56102 #define V_VBADJ(x) ((x) << S_VBADJ)
56103 #define F_VBADJ    V_VBADJ(1U)
56172 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
56173 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
56175 #define S_IBQBUSY    1
56176 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
56177 #define F_IBQBUSY    V_IBQBUSY(1U)
56180 #define V_IBQEN(x) ((x) << S_IBQEN)
56181 #define F_IBQEN    V_IBQEN(1U)
56187 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
56188 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
56190 #define S_OBQBUSY    1
56191 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
56192 #define F_OBQBUSY    V_OBQBUSY(1U)
56195 #define V_OBQEN(x) ((x) << S_OBQEN)
56196 #define F_OBQEN    V_OBQEN(1U)
56202 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
56203 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
56207 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
56208 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
56211 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
56212 #define F_IBQMBVFSTATUS    V_IBQMBVFSTATUS(1U)
56215 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
56216 #define F_IBQMBSTATUS    V_IBQMBSTATUS(1U)
56220 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
56221 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
56225 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
56226 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
56230 #define V_T7_IBQGEN1(x) ((x) << S_T7_IBQGEN1)
56231 #define G_T7_IBQGEN1(x) (((x) >> S_T7_IBQGEN1) & M_T7_IBQGEN1)
56235 #define V_T7_IBQEMPTY(x) ((x) << S_T7_IBQEMPTY)
56236 #define G_T7_IBQEMPTY(x) (((x) >> S_T7_IBQEMPTY) & M_T7_IBQEMPTY)
56242 #define V_OBQGEN(x) ((x) << S_OBQGEN)
56243 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
56247 #define V_OBQFULL(x) ((x) << S_OBQFULL)
56248 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
56252 #define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
56253 #define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
56257 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
56258 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
56262 #define V_T7_T5_OBQGEN(x) ((x) << S_T7_T5_OBQGEN)
56263 #define G_T7_T5_OBQGEN(x) (((x) >> S_T7_T5_OBQGEN) & M_T7_T5_OBQGEN)
56267 #define V_T7_T5_OBQFULL(x) ((x) << S_T7_T5_OBQFULL)
56268 #define G_T7_T5_OBQFULL(x) (((x) >> S_T7_T5_OBQFULL) & M_T7_T5_OBQFULL)
56274 #define V_QUEID(x) ((x) << S_QUEID)
56275 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
56279 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
56280 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
56286 #define V_IPCEMPTY(x) ((x) << S_IPCEMPTY)
56287 #define G_IPCEMPTY(x) (((x) >> S_IPCEMPTY) & M_IPCEMPTY)
56293 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
56294 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
56299 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
56300 #define F_QUEERRFRAME    V_QUEERRFRAME(1U)
56304 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
56305 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
56311 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
56312 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
56316 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
56317 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
56343 #define V_OBQID(x) ((x) << S_OBQID)
56344 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
56348 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
56349 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
56355 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
56356 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
56392 #define V_FIFO_SIZE(x) ((x) << S_FIFO_SIZE)
56393 #define G_FIFO_SIZE(x) (((x) >> S_FIFO_SIZE) & M_FIFO_SIZE)
56396 #define V_ROCE_MODE(x) ((x) << S_ROCE_MODE)
56397 #define F_ROCE_MODE    V_ROCE_MODE(1U)
56401 #define V_SEQ_WR_PTR(x) ((x) << S_SEQ_WR_PTR)
56402 #define G_SEQ_WR_PTR(x) (((x) >> S_SEQ_WR_PTR) & M_SEQ_WR_PTR)
56406 #define V_SEQ_RD_PTR(x) ((x) << S_SEQ_RD_PTR)
56407 #define G_SEQ_RD_PTR(x) (((x) >> S_SEQ_RD_PTR) & M_SEQ_RD_PTR)
56413 #define V_QUESIZE(x) ((x) << S_QUESIZE)
56414 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
56418 #define V_QUEBASE(x) ((x) << S_QUEBASE)
56419 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
56422 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
56423 #define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)
56426 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
56427 #define F_QUEBAREADDR    V_QUEBAREADDR(1U)
56430 #define V_QUE1KEN(x) ((x) << S_QUE1KEN)
56431 #define F_QUE1KEN    V_QUE1KEN(1U)
56436 #define V_INV_SEQ(x) ((x) << S_INV_SEQ)
56437 #define F_INV_SEQ    V_INV_SEQ(1U)
56440 #define V_DUP_SEQ(x) ((x) << S_DUP_SEQ)
56441 #define F_DUP_SEQ    V_DUP_SEQ(1U)
56444 #define V_MATCH_VLD(x) ((x) << S_MATCH_VLD)
56445 #define F_MATCH_VLD    V_MATCH_VLD(1U)
56449 #define V_MATCH_INDEX(x) ((x) << S_MATCH_INDEX)
56450 #define G_MATCH_INDEX(x) (((x) >> S_MATCH_INDEX) & M_MATCH_INDEX)
56455 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
56456 #define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)
56459 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
56460 #define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)
56464 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
56465 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
56481 #define S_HALTINFO    1
56483 #define V_HALTINFO(x) ((x) << S_HALTINFO)
56484 #define G_HALTINFO(x) (((x) >> S_HALTINFO) & M_HALTINFO)
56504 #define V_HALTREQ(x) ((x) << S_HALTREQ)
56505 #define F_HALTREQ    V_HALTREQ(1U)
56514 #define V_MBGEN0(x) ((x) << S_MBGEN0)
56515 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
56519 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
56520 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
56524 #define V_MBGEN1(x) ((x) << S_MBGEN1)
56525 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
56529 #define V_MBPFINT(x) ((x) << S_MBPFINT)
56530 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
56535 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
56536 #define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)
56539 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
56540 #define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)
56543 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
56544 #define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)
56547 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
56548 #define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)
56552 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
56553 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
56557 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
56558 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
56560 #define S_UPDBGLARDEN    1
56561 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
56562 #define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)
56565 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
56566 #define F_UPDBGLAEN    V_UPDBGLAEN(1U)
56569 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
56570 #define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)
56577 #define V_FLSRC(x) ((x) << S_FLSRC)
56578 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
56581 #define V_SEPROT(x) ((x) << S_SEPROT)
56582 #define F_SEPROT    V_SEPROT(1U)
56586 #define V_SESRC(x) ((x) << S_SESRC)
56587 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
56590 #define V_UPRGN(x) ((x) << S_UPRGN)
56591 #define F_UPRGN    V_UPRGN(1U)
56595 #define V_UPPF(x) ((x) << S_UPPF)
56596 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
56600 #define V_UPRID(x) ((x) << S_UPRID)
56601 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
56604 #define V_REQVFVLD(x) ((x) << S_REQVFVLD)
56605 #define F_REQVFVLD    V_REQVFVLD(1U)
56609 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
56610 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
56614 #define V_T6_UPRID(x) ((x) << S_T6_UPRID)
56615 #define G_T6_UPRID(x) (((x) >> S_T6_UPRID) & M_T6_UPRID)
56620 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
56621 #define F_UPSELFRESET    V_UPSELFRESET(1U)
56634 #define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
56635 #define F_ECO_15444_SGE_DB_BUSY    V_ECO_15444_SGE_DB_BUSY(1U)
56638 #define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
56639 #define F_ECO_15444_PL_INTF_BUSY    V_ECO_15444_PL_INTF_BUSY(1U)
56643 #define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
56644 #define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
56650 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
56651 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
56655 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
56656 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
56662 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
56663 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
56667 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
56668 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
56674 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
56675 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
56679 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
56680 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
56683 #define V_TSCHCHNLCHDIS(x) ((x) << S_TSCHCHNLCHDIS)
56684 #define F_TSCHCHNLCHDIS    V_TSCHCHNLCHDIS(1U)
56687 #define V_TSCHCHNLWDIS(x) ((x) << S_TSCHCHNLWDIS)
56688 #define F_TSCHCHNLWDIS    V_TSCHCHNLWDIS(1U)
56691 #define V_TSCHCHNLCLDIS(x) ((x) << S_TSCHCHNLCLDIS)
56692 #define F_TSCHCHNLCLDIS    V_TSCHCHNLCLDIS(1U)
56792 #define V_T7_QUEREMFLITS(x) ((x) << S_T7_QUEREMFLITS)
56793 #define G_T7_QUEREMFLITS(x) (((x) >> S_T7_QUEREMFLITS) & M_T7_QUEREMFLITS)
56992 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
56993 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
56996 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
56997 #define F_AUTOPREFEN    V_AUTOPREFEN(1U)
57000 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
57001 #define F_DISMATIMEOUT    V_DISMATIMEOUT(1U)
57004 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
57005 #define F_PIFMULTICMD    V_PIFMULTICMD(1U)
57008 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
57009 #define F_UPSELFRESETTOUT    V_UPSELFRESETTOUT(1U)
57012 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
57013 #define F_PLSWAPDISWR    V_PLSWAPDISWR(1U)
57016 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
57017 #define F_PLSWAPDISRD    V_PLSWAPDISRD(1U)
57020 #define V_PREFEN(x) ((x) << S_PREFEN)
57021 #define F_PREFEN    V_PREFEN(1U)
57024 #define V_DISSLOWTIMEOUT(x) ((x) << S_DISSLOWTIMEOUT)
57025 #define F_DISSLOWTIMEOUT    V_DISSLOWTIMEOUT(1U)
57028 #define V_INTLRSPEN(x) ((x) << S_INTLRSPEN)
57029 #define F_INTLRSPEN    V_INTLRSPEN(1U)
57050 #define V_SEMINIT(x) ((x) << S_SEMINIT)
57051 #define F_SEMINIT    V_SEMINIT(1U)
57055 #define V_NUMSEM(x) ((x) << S_NUMSEM)
57056 #define G_NUMSEM(x) (((x) >> S_NUMSEM) & M_NUMSEM)
57063 #define V_SEMMABASE(x) ((x) << S_SEMMABASE)
57064 #define G_SEMMABASE(x) (((x) >> S_SEMMABASE) & M_SEMMABASE)
57068 #define V_SEMMATHREADID(x) ((x) << S_SEMMATHREADID)
57069 #define G_SEMMATHREADID(x) (((x) >> S_SEMMATHREADID) & M_SEMMATHREADID)
57078 #define V_NUMLOCK(x) ((x) << S_NUMLOCK)
57079 #define G_NUMLOCK(x) (((x) >> S_NUMLOCK) & M_NUMLOCK)
57086 #define V_LOCKMABASE(x) ((x) << S_LOCKMABASE)
57087 #define G_LOCKMABASE(x) (((x) >> S_LOCKMABASE) & M_LOCKMABASE)
57091 #define V_LOCKMATHREADID(x) ((x) << S_LOCKMATHREADID)
57092 #define G_LOCKMATHREADID(x) (((x) >> S_LOCKMATHREADID) & M_LOCKMATHREADID)
57116 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
57117 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
57130 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
57131 #define F_GENTIMERRUN    V_GENTIMERRUN(1U)
57134 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
57135 #define F_GENTIMERTRIG    V_GENTIMERTRIG(1U)
57139 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
57140 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
57144 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
57145 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
57147 #define S_GENTIMERSTOP    1
57148 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
57149 #define F_GENTIMERSTOP    V_GENTIMERSTOP(1U)
57152 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
57153 #define F_GENTIMERSTRT    V_GENTIMERSTRT(1U)
57170 #define V_TIDDEFCORE(x) ((x) << S_TIDDEFCORE)
57171 #define G_TIDDEFCORE(x) (((x) >> S_TIDDEFCORE) & M_TIDDEFCORE)
57175 #define V_TIDVECBASE(x) ((x) << S_TIDVECBASE)
57176 #define G_TIDVECBASE(x) (((x) >> S_TIDVECBASE) & M_TIDVECBASE)
57184 #define V_CRYPTOKEYDATAREGNUM(x) ((x) << S_CRYPTOKEYDATAREGNUM)
57185 #define G_CRYPTOKEYDATAREGNUM(x) (((x) >> S_CRYPTOKEYDATAREGNUM) & M_CRYPTOKEYDATAREGNUM)
57188 #define V_CRYPTOKEYSTARTBUSY(x) ((x) << S_CRYPTOKEYSTARTBUSY)
57189 #define F_CRYPTOKEYSTARTBUSY    V_CRYPTOKEYSTARTBUSY(1U)
57196 #define V_FLOWBASEADDR(x) ((x) << S_FLOWBASEADDR)
57197 #define G_FLOWBASEADDR(x) (((x) >> S_FLOWBASEADDR) & M_FLOWBASEADDR)
57201 #define V_SEQSRCHALIGNCFG(x) ((x) << S_SEQSRCHALIGNCFG)
57202 #define G_SEQSRCHALIGNCFG(x) (((x) >> S_SEQSRCHALIGNCFG) & M_SEQSRCHALIGNCFG)
57204 #define S_FLOWADDRSIZE    1
57206 #define V_FLOWADDRSIZE(x) ((x) << S_FLOWADDRSIZE)
57207 #define G_FLOWADDRSIZE(x) (((x) >> S_FLOWADDRSIZE) & M_FLOWADDRSIZE)
57210 #define V_FLOWIDEN(x) ((x) << S_FLOWIDEN)
57211 #define F_FLOWIDEN    V_FLOWIDEN(1U)
57217 #define V_MAXFLOWID(x) ((x) << S_MAXFLOWID)
57218 #define G_MAXFLOWID(x) (((x) >> S_MAXFLOWID) & M_MAXFLOWID)
57227 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
57228 #define F_TSCHNLEN    V_TSCHNLEN(1U)
57231 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
57232 #define F_TSCHNRESET    V_TSCHNRESET(1U)
57235 #define V_T6_MIN_MAX_EN(x) ((x) << S_T6_MIN_MAX_EN)
57236 #define F_T6_MIN_MAX_EN    V_T6_MIN_MAX_EN(1U)
57242 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
57243 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
57248 #define V_TSC15RATECTL(x) ((x) << S_TSC15RATECTL)
57249 #define F_TSC15RATECTL    V_TSC15RATECTL(1U)
57252 #define V_TSC14RATECTL(x) ((x) << S_TSC14RATECTL)
57253 #define F_TSC14RATECTL    V_TSC14RATECTL(1U)
57256 #define V_TSC13RATECTL(x) ((x) << S_TSC13RATECTL)
57257 #define F_TSC13RATECTL    V_TSC13RATECTL(1U)
57260 #define V_TSC12RATECTL(x) ((x) << S_TSC12RATECTL)
57261 #define F_TSC12RATECTL    V_TSC12RATECTL(1U)
57264 #define V_TSC11RATECTL(x) ((x) << S_TSC11RATECTL)
57265 #define F_TSC11RATECTL    V_TSC11RATECTL(1U)
57268 #define V_TSC10RATECTL(x) ((x) << S_TSC10RATECTL)
57269 #define F_TSC10RATECTL    V_TSC10RATECTL(1U)
57272 #define V_TSC9RATECTL(x) ((x) << S_TSC9RATECTL)
57273 #define F_TSC9RATECTL    V_TSC9RATECTL(1U)
57276 #define V_TSC8RATECTL(x) ((x) << S_TSC8RATECTL)
57277 #define F_TSC8RATECTL    V_TSC8RATECTL(1U)
57280 #define V_TSC7RATECTL(x) ((x) << S_TSC7RATECTL)
57281 #define F_TSC7RATECTL    V_TSC7RATECTL(1U)
57284 #define V_TSC6RATECTL(x) ((x) << S_TSC6RATECTL)
57285 #define F_TSC6RATECTL    V_TSC6RATECTL(1U)
57288 #define V_TSC5RATECTL(x) ((x) << S_TSC5RATECTL)
57289 #define F_TSC5RATECTL    V_TSC5RATECTL(1U)
57292 #define V_TSC4RATECTL(x) ((x) << S_TSC4RATECTL)
57293 #define F_TSC4RATECTL    V_TSC4RATECTL(1U)
57296 #define V_TSC3RATECTL(x) ((x) << S_TSC3RATECTL)
57297 #define F_TSC3RATECTL    V_TSC3RATECTL(1U)
57300 #define V_TSC2RATECTL(x) ((x) << S_TSC2RATECTL)
57301 #define F_TSC2RATECTL    V_TSC2RATECTL(1U)
57303 #define S_TSC1RATECTL    1
57304 #define V_TSC1RATECTL(x) ((x) << S_TSC1RATECTL)
57305 #define F_TSC1RATECTL    V_TSC1RATECTL(1U)
57308 #define V_TSC0RATECTL(x) ((x) << S_TSC0RATECTL)
57309 #define F_TSC0RATECTL    V_TSC0RATECTL(1U)
57314 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
57315 #define F_TSC15WRREN    V_TSC15WRREN(1U)
57318 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
57319 #define F_TSC15RATEEN    V_TSC15RATEEN(1U)
57322 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
57323 #define F_TSC14WRREN    V_TSC14WRREN(1U)
57326 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
57327 #define F_TSC14RATEEN    V_TSC14RATEEN(1U)
57330 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
57331 #define F_TSC13WRREN    V_TSC13WRREN(1U)
57334 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
57335 #define F_TSC13RATEEN    V_TSC13RATEEN(1U)
57338 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
57339 #define F_TSC12WRREN    V_TSC12WRREN(1U)
57342 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
57343 #define F_TSC12RATEEN    V_TSC12RATEEN(1U)
57346 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
57347 #define F_TSC11WRREN    V_TSC11WRREN(1U)
57350 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
57351 #define F_TSC11RATEEN    V_TSC11RATEEN(1U)
57354 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
57355 #define F_TSC10WRREN    V_TSC10WRREN(1U)
57358 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
57359 #define F_TSC10RATEEN    V_TSC10RATEEN(1U)
57362 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
57363 #define F_TSC9WRREN    V_TSC9WRREN(1U)
57366 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
57367 #define F_TSC9RATEEN    V_TSC9RATEEN(1U)
57370 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
57371 #define F_TSC8WRREN    V_TSC8WRREN(1U)
57374 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
57375 #define F_TSC8RATEEN    V_TSC8RATEEN(1U)
57378 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
57379 #define F_TSC7WRREN    V_TSC7WRREN(1U)
57382 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
57383 #define F_TSC7RATEEN    V_TSC7RATEEN(1U)
57386 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
57387 #define F_TSC6WRREN    V_TSC6WRREN(1U)
57390 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
57391 #define F_TSC6RATEEN    V_TSC6RATEEN(1U)
57394 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
57395 #define F_TSC5WRREN    V_TSC5WRREN(1U)
57398 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
57399 #define F_TSC5RATEEN    V_TSC5RATEEN(1U)
57402 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
57403 #define F_TSC4WRREN    V_TSC4WRREN(1U)
57406 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
57407 #define F_TSC4RATEEN    V_TSC4RATEEN(1U)
57410 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
57411 #define F_TSC3WRREN    V_TSC3WRREN(1U)
57414 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
57415 #define F_TSC3RATEEN    V_TSC3RATEEN(1U)
57418 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
57419 #define F_TSC2WRREN    V_TSC2WRREN(1U)
57422 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
57423 #define F_TSC2RATEEN    V_TSC2RATEEN(1U)
57426 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
57427 #define F_TSC1WRREN    V_TSC1WRREN(1U)
57430 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
57431 #define F_TSC1RATEEN    V_TSC1RATEEN(1U)
57433 #define S_TSC0WRREN    1
57434 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
57435 #define F_TSC0WRREN    V_TSC0WRREN(1U)
57438 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
57439 #define F_TSC0RATEEN    V_TSC0RATEEN(1U)
57444 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
57445 #define F_MIN_MAX_EN    V_MIN_MAX_EN(1U)
57450 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
57451 #define F_TSCHNLRATENEG    V_TSCHNLRATENEG(1U)
57455 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
57456 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
57459 #define V_TSCHNLRATEPROT(x) ((x) << S_TSCHNLRATEPROT)
57460 #define F_TSCHNLRATEPROT    V_TSCHNLRATEPROT(1U)
57464 #define V_T6_TSCHNLRATEL(x) ((x) << S_T6_TSCHNLRATEL)
57465 #define G_T6_TSCHNLRATEL(x) (((x) >> S_T6_TSCHNLRATEL) & M_T6_TSCHNLRATEL)
57471 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
57472 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
57476 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
57477 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
57481 #define V_TSCHNLRTSEL(x) ((x) << S_TSCHNLRTSEL)
57482 #define G_TSCHNLRTSEL(x) (((x) >> S_TSCHNLRTSEL) & M_TSCHNLRTSEL)
57486 #define V_T6_TSCHNLRINCR(x) ((x) << S_T6_TSCHNLRINCR)
57487 #define G_T6_TSCHNLRINCR(x) (((x) >> S_T6_TSCHNLRINCR) & M_T6_TSCHNLRINCR)
57494 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
57495 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
57500 #define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
57501 #define F_TSCCLRATENEG    V_TSCCLRATENEG(1U)
57505 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
57506 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
57509 #define V_TSCCLRATEPROT(x) ((x) << S_TSCCLRATEPROT)
57510 #define F_TSCCLRATEPROT    V_TSCCLRATEPROT(1U)
57516 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
57517 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
57521 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
57522 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
57526 #define V_TSCCLRTSEL(x) ((x) << S_TSCCLRTSEL)
57527 #define G_TSCCLRTSEL(x) (((x) >> S_TSCCLRTSEL) & M_TSCCLRTSEL)
57531 #define V_T6_TSCCLRINCR(x) ((x) << S_T6_TSCCLRINCR)
57532 #define G_T6_TSCCLRINCR(x) (((x) >> S_T6_TSCCLRINCR) & M_T6_TSCCLRINCR)
57537 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
57538 #define F_TSCCLWRRNEG    V_TSCCLWRRNEG(1U)
57542 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
57543 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
57546 #define V_TSCCLWRRPROT(x) ((x) << S_TSCCLWRRPROT)
57547 #define F_TSCCLWRRPROT    V_TSCCLWRRPROT(1U)
57553 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
57554 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
57558 #define V_PAUSEVECSEL(x) ((x) << S_PAUSEVECSEL)
57559 #define G_PAUSEVECSEL(x) (((x) >> S_PAUSEVECSEL) & M_PAUSEVECSEL)
57563 #define V_MPSPAUSEMASK(x) ((x) << S_MPSPAUSEMASK)
57564 #define G_MPSPAUSEMASK(x) (((x) >> S_MPSPAUSEMASK) & M_MPSPAUSEMASK)
57591 #define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
57592 #define F_PF7_OWNER_PL    V_PF7_OWNER_PL(1U)
57595 #define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
57596 #define F_PF6_OWNER_PL    V_PF6_OWNER_PL(1U)
57599 #define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
57600 #define F_PF5_OWNER_PL    V_PF5_OWNER_PL(1U)
57603 #define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
57604 #define F_PF4_OWNER_PL    V_PF4_OWNER_PL(1U)
57607 #define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
57608 #define F_PF3_OWNER_PL    V_PF3_OWNER_PL(1U)
57611 #define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
57612 #define F_PF2_OWNER_PL    V_PF2_OWNER_PL(1U)
57615 #define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
57616 #define F_PF1_OWNER_PL    V_PF1_OWNER_PL(1U)
57619 #define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
57620 #define F_PF0_OWNER_PL    V_PF0_OWNER_PL(1U)
57623 #define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
57624 #define F_PF7_OWNER_UP    V_PF7_OWNER_UP(1U)
57627 #define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
57628 #define F_PF6_OWNER_UP    V_PF6_OWNER_UP(1U)
57631 #define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
57632 #define F_PF5_OWNER_UP    V_PF5_OWNER_UP(1U)
57635 #define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
57636 #define F_PF4_OWNER_UP    V_PF4_OWNER_UP(1U)
57639 #define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
57640 #define F_PF3_OWNER_UP    V_PF3_OWNER_UP(1U)
57643 #define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
57644 #define F_PF2_OWNER_UP    V_PF2_OWNER_UP(1U)
57646 #define S_PF1_OWNER_UP    1
57647 #define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
57648 #define F_PF1_OWNER_UP    V_PF1_OWNER_UP(1U)
57651 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
57652 #define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
57660 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
57661 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
57677 #define S_CH1_PRIO_EN    1
57678 #define V_CH1_PRIO_EN(x) ((x) << S_CH1_PRIO_EN)
57679 #define F_CH1_PRIO_EN    V_CH1_PRIO_EN(1U)
57682 #define V_CH0_PRIO_EN(x) ((x) << S_CH0_PRIO_EN)
57683 #define F_CH0_PRIO_EN    V_CH0_PRIO_EN(1U)
57689 #define V_SLOW_TIMEOUT(x) ((x) << S_SLOW_TIMEOUT)
57690 #define G_SLOW_TIMEOUT(x) (((x) >> S_SLOW_TIMEOUT) & M_SLOW_TIMEOUT)
57694 #define V_MA_TIMEOUT(x) ((x) << S_MA_TIMEOUT)
57695 #define G_MA_TIMEOUT(x) (((x) >> S_MA_TIMEOUT) & M_MA_TIMEOUT)
57701 #define V_XOCDMODE(x) ((x) << S_XOCDMODE)
57702 #define G_XOCDMODE(x) (((x) >> S_XOCDMODE) & M_XOCDMODE)
57706 #define V_BREAKIN_CONTROL(x) ((x) << S_BREAKIN_CONTROL)
57707 #define G_BREAKIN_CONTROL(x) (((x) >> S_BREAKIN_CONTROL) & M_BREAKIN_CONTROL)
57713 #define V_T7_UPGEN(x) ((x) << S_T7_UPGEN)
57714 #define G_T7_UPGEN(x) (((x) >> S_T7_UPGEN) & M_T7_UPGEN)
57717 #define V_UPCLKEN(x) ((x) << S_UPCLKEN)
57718 #define F_UPCLKEN    V_UPCLKEN(1U)
57762 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
57763 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
57766 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
57767 #define F_SMUXTXSEL    V_SMUXTXSEL(1U)
57770 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
57771 #define F_SMUXRXSEL    V_SMUXRXSEL(1U)
57775 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
57776 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
57779 #define V_ENA_ERR_RSP(x) ((x) << S_ENA_ERR_RSP)
57780 #define F_ENA_ERR_RSP    V_ENA_ERR_RSP(1U)
57783 #define V_DEBUG_CLR(x) ((x) << S_DEBUG_CLR)
57784 #define F_DEBUG_CLR    V_DEBUG_CLR(1U)
57787 #define V_PLL_SEL(x) ((x) << S_PLL_SEL)
57788 #define F_PLL_SEL    V_PLL_SEL(1U)
57792 #define V_PORT_MAP(x) ((x) << S_PORT_MAP)
57793 #define G_PORT_MAP(x) (((x) >> S_PORT_MAP) & M_PORT_MAP)
57796 #define V_AEC_PAT_DATA(x) ((x) << S_AEC_PAT_DATA)
57797 #define F_AEC_PAT_DATA    V_AEC_PAT_DATA(1U)
57800 #define V_MACCLK_SEL(x) ((x) << S_MACCLK_SEL)
57801 #define F_MACCLK_SEL    V_MACCLK_SEL(1U)
57804 #define V_XGMII_SEL(x) ((x) << S_XGMII_SEL)
57805 #define F_XGMII_SEL    V_XGMII_SEL(1U)
57809 #define V_DEBUG_PORT_SEL(x) ((x) << S_DEBUG_PORT_SEL)
57810 #define G_DEBUG_PORT_SEL(x) (((x) >> S_DEBUG_PORT_SEL) & M_DEBUG_PORT_SEL)
57813 #define V_ENABLE_25G(x) ((x) << S_ENABLE_25G)
57814 #define F_ENABLE_25G    V_ENABLE_25G(1U)
57817 #define V_ENABLE_50G(x) ((x) << S_ENABLE_50G)
57818 #define F_ENABLE_50G    V_ENABLE_50G(1U)
57820 #define S_DEBUG_TX_RX_SEL    1
57821 #define V_DEBUG_TX_RX_SEL(x) ((x) << S_DEBUG_TX_RX_SEL)
57822 #define F_DEBUG_TX_RX_SEL    V_DEBUG_TX_RX_SEL(1U)
57827 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
57828 #define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)
57831 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
57832 #define F_EEE_RESET    V_EEE_RESET(1U)
57835 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
57836 #define F_PTP_TIMER    V_PTP_TIMER(1U)
57839 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
57840 #define F_MTIPREFRESET    V_MTIPREFRESET(1U)
57843 #define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
57844 #define F_MTIPTXFFRESET    V_MTIPTXFFRESET(1U)
57847 #define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
57848 #define F_MTIPRXFFRESET    V_MTIPRXFFRESET(1U)
57851 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
57852 #define F_MTIPREGRESET    V_MTIPREGRESET(1U)
57855 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
57856 #define F_AEC3RESET    V_AEC3RESET(1U)
57859 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
57860 #define F_AEC2RESET    V_AEC2RESET(1U)
57863 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
57864 #define F_AEC1RESET    V_AEC1RESET(1U)
57867 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
57868 #define F_AEC0RESET    V_AEC0RESET(1U)
57871 #define V_AET3RESET(x) ((x) << S_AET3RESET)
57872 #define F_AET3RESET    V_AET3RESET(1U)
57875 #define V_AET2RESET(x) ((x) << S_AET2RESET)
57876 #define F_AET2RESET    V_AET2RESET(1U)
57879 #define V_AET1RESET(x) ((x) << S_AET1RESET)
57880 #define F_AET1RESET    V_AET1RESET(1U)
57883 #define V_AET0RESET(x) ((x) << S_AET0RESET)
57884 #define F_AET0RESET    V_AET0RESET(1U)
57887 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
57888 #define F_TXIF_RESET    V_TXIF_RESET(1U)
57891 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
57892 #define F_RXIF_RESET    V_RXIF_RESET(1U)
57895 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
57896 #define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)
57899 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
57900 #define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)
57903 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
57904 #define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)
57907 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
57908 #define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)
57911 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
57912 #define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)
57915 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
57916 #define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)
57919 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
57920 #define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)
57922 #define S_MTIPSD0RXRST    1
57923 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
57924 #define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
57927 #define V_MAC100G40G_RESET(x) ((x) << S_MAC100G40G_RESET)
57928 #define F_MAC100G40G_RESET    V_MAC100G40G_RESET(1U)
57931 #define V_MAC10G1G_RESET(x) ((x) << S_MAC10G1G_RESET)
57932 #define F_MAC10G1G_RESET    V_MAC10G1G_RESET(1U)
57935 #define V_PCS1G_RESET(x) ((x) << S_PCS1G_RESET)
57936 #define F_PCS1G_RESET    V_PCS1G_RESET(1U)
57939 #define V_PCS10G_RESET(x) ((x) << S_PCS10G_RESET)
57940 #define F_PCS10G_RESET    V_PCS10G_RESET(1U)
57943 #define V_PCS40G_RESET(x) ((x) << S_PCS40G_RESET)
57944 #define F_PCS40G_RESET    V_PCS40G_RESET(1U)
57947 #define V_PCS100G_RESET(x) ((x) << S_PCS100G_RESET)
57948 #define F_PCS100G_RESET    V_PCS100G_RESET(1U)
57954 #define V_LED1_CFG1(x) ((x) << S_LED1_CFG1)
57955 #define G_LED1_CFG1(x) (((x) >> S_LED1_CFG1) & M_LED1_CFG1)
57959 #define V_LED0_CFG1(x) ((x) << S_LED0_CFG1)
57960 #define G_LED0_CFG1(x) (((x) >> S_LED0_CFG1) & M_LED0_CFG1)
57963 #define V_LED1_TLO(x) ((x) << S_LED1_TLO)
57964 #define F_LED1_TLO    V_LED1_TLO(1U)
57967 #define V_LED1_THI(x) ((x) << S_LED1_THI)
57968 #define F_LED1_THI    V_LED1_THI(1U)
57971 #define V_LED0_TLO(x) ((x) << S_LED0_TLO)
57972 #define F_LED0_TLO    V_LED0_TLO(1U)
57975 #define V_LED0_THI(x) ((x) << S_LED0_THI)
57976 #define F_LED0_THI    V_LED0_THI(1U)
57984 #define V_T5_FPGA_PTP_PORT(x) ((x) << S_T5_FPGA_PTP_PORT)
57985 #define G_T5_FPGA_PTP_PORT(x) (((x) >> S_T5_FPGA_PTP_PORT) & M_T5_FPGA_PTP_PORT)
57988 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
57989 #define F_FCSDISCTRL    V_FCSDISCTRL(1U)
57992 #define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
57993 #define F_SIGDETCTRL    V_SIGDETCTRL(1U)
57996 #define V_TX_LANE(x) ((x) << S_TX_LANE)
57997 #define F_TX_LANE    V_TX_LANE(1U)
58000 #define V_RX_LANE(x) ((x) << S_RX_LANE)
58001 #define F_RX_LANE    V_RX_LANE(1U)
58004 #define V_SE_CLR(x) ((x) << S_SE_CLR)
58005 #define F_SE_CLR    V_SE_CLR(1U)
58009 #define V_AN_ENA(x) ((x) << S_AN_ENA)
58010 #define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
58014 #define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
58015 #define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
58019 #define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
58020 #define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
58023 #define V_SGMIISEL(x) ((x) << S_SGMIISEL)
58024 #define F_SGMIISEL    V_SGMIISEL(1U)
58028 #define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
58029 #define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
58033 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
58034 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
58038 #define V_REF_CLK_SEL(x) ((x) << S_REF_CLK_SEL)
58039 #define G_REF_CLK_SEL(x) (((x) >> S_REF_CLK_SEL) & M_REF_CLK_SEL)
58042 #define V_SGMII_SD_SIG_DET(x) ((x) << S_SGMII_SD_SIG_DET)
58043 #define F_SGMII_SD_SIG_DET    V_SGMII_SD_SIG_DET(1U)
58046 #define V_SGMII_SGPCS_ENA(x) ((x) << S_SGMII_SGPCS_ENA)
58047 #define F_SGMII_SGPCS_ENA    V_SGMII_SGPCS_ENA(1U)
58051 #define V_MAC_FPGA_PTP_PORT(x) ((x) << S_MAC_FPGA_PTP_PORT)
58052 #define G_MAC_FPGA_PTP_PORT(x) (((x) >> S_MAC_FPGA_PTP_PORT) & M_MAC_FPGA_PTP_PORT)
58058 #define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
58059 #define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
58063 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
58064 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
58067 #define V_AN_DATA_CTL(x) ((x) << S_AN_DATA_CTL)
58068 #define F_AN_DATA_CTL    V_AN_DATA_CTL(1U)
58075 #define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
58076 #define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
58080 #define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
58081 #define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
58085 #define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
58086 #define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
58090 #define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
58091 #define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
58095 #define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
58096 #define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
58100 #define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
58101 #define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
58105 #define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
58106 #define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
58110 #define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
58111 #define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
58118 #define V_AN_RESET_SD_TX_CLK(x) ((x) << S_AN_RESET_SD_TX_CLK)
58119 #define F_AN_RESET_SD_TX_CLK    V_AN_RESET_SD_TX_CLK(1U)
58122 #define V_AN_RESET_SD_RX_CLK(x) ((x) << S_AN_RESET_SD_RX_CLK)
58123 #define F_AN_RESET_SD_RX_CLK    V_AN_RESET_SD_RX_CLK(1U)
58126 #define V_SGMII_RESET_TX_CLK(x) ((x) << S_SGMII_RESET_TX_CLK)
58127 #define F_SGMII_RESET_TX_CLK    V_SGMII_RESET_TX_CLK(1U)
58130 #define V_SGMII_RESET_RX_CLK(x) ((x) << S_SGMII_RESET_RX_CLK)
58131 #define F_SGMII_RESET_RX_CLK    V_SGMII_RESET_RX_CLK(1U)
58134 #define V_SGMII_RESET_REF_CLK(x) ((x) << S_SGMII_RESET_REF_CLK)
58135 #define F_SGMII_RESET_REF_CLK    V_SGMII_RESET_REF_CLK(1U)
58138 #define V_PCS10G_RESET_XFI_RXCLK(x) ((x) << S_PCS10G_RESET_XFI_RXCLK)
58139 #define F_PCS10G_RESET_XFI_RXCLK    V_PCS10G_RESET_XFI_RXCLK(1U)
58142 #define V_PCS10G_RESET_XFI_TXCLK(x) ((x) << S_PCS10G_RESET_XFI_TXCLK)
58143 #define F_PCS10G_RESET_XFI_TXCLK    V_PCS10G_RESET_XFI_TXCLK(1U)
58146 #define V_PCS10G_RESET_SD_TX_CLK(x) ((x) << S_PCS10G_RESET_SD_TX_CLK)
58147 #define F_PCS10G_RESET_SD_TX_CLK    V_PCS10G_RESET_SD_TX_CLK(1U)
58150 #define V_PCS10G_RESET_SD_RX_CLK(x) ((x) << S_PCS10G_RESET_SD_RX_CLK)
58151 #define F_PCS10G_RESET_SD_RX_CLK    V_PCS10G_RESET_SD_RX_CLK(1U)
58154 #define V_PCS40G_RESET_RXCLK(x) ((x) << S_PCS40G_RESET_RXCLK)
58155 #define F_PCS40G_RESET_RXCLK    V_PCS40G_RESET_RXCLK(1U)
58158 #define V_PCS40G_RESET_SD_TX_CLK(x) ((x) << S_PCS40G_RESET_SD_TX_CLK)
58159 #define F_PCS40G_RESET_SD_TX_CLK    V_PCS40G_RESET_SD_TX_CLK(1U)
58162 #define V_PCS40G_RESET_SD0_RX_CLK(x) ((x) << S_PCS40G_RESET_SD0_RX_CLK)
58163 #define F_PCS40G_RESET_SD0_RX_CLK    V_PCS40G_RESET_SD0_RX_CLK(1U)
58166 #define V_PCS40G_RESET_SD1_RX_CLK(x) ((x) << S_PCS40G_RESET_SD1_RX_CLK)
58167 #define F_PCS40G_RESET_SD1_RX_CLK    V_PCS40G_RESET_SD1_RX_CLK(1U)
58170 #define V_PCS40G_RESET_SD2_RX_CLK(x) ((x) << S_PCS40G_RESET_SD2_RX_CLK)
58171 #define F_PCS40G_RESET_SD2_RX_CLK    V_PCS40G_RESET_SD2_RX_CLK(1U)
58174 #define V_PCS40G_RESET_SD3_RX_CLK(x) ((x) << S_PCS40G_RESET_SD3_RX_CLK)
58175 #define F_PCS40G_RESET_SD3_RX_CLK    V_PCS40G_RESET_SD3_RX_CLK(1U)
58178 #define V_PCS100G_RESET_CGMII_RXCLK(x) ((x) << S_PCS100G_RESET_CGMII_RXCLK)
58179 #define F_PCS100G_RESET_CGMII_RXCLK    V_PCS100G_RESET_CGMII_RXCLK(1U)
58182 #define V_PCS100G_RESET_CGMII_TXCLK(x) ((x) << S_PCS100G_RESET_CGMII_TXCLK)
58183 #define F_PCS100G_RESET_CGMII_TXCLK    V_PCS100G_RESET_CGMII_TXCLK(1U)
58186 #define V_PCS100G_RESET_TX_CLK(x) ((x) << S_PCS100G_RESET_TX_CLK)
58187 #define F_PCS100G_RESET_TX_CLK    V_PCS100G_RESET_TX_CLK(1U)
58190 #define V_PCS100G_RESET_SD0_RX_CLK(x) ((x) << S_PCS100G_RESET_SD0_RX_CLK)
58191 #define F_PCS100G_RESET_SD0_RX_CLK    V_PCS100G_RESET_SD0_RX_CLK(1U)
58194 #define V_PCS100G_RESET_SD1_RX_CLK(x) ((x) << S_PCS100G_RESET_SD1_RX_CLK)
58195 #define F_PCS100G_RESET_SD1_RX_CLK    V_PCS100G_RESET_SD1_RX_CLK(1U)
58198 #define V_PCS100G_RESET_SD2_RX_CLK(x) ((x) << S_PCS100G_RESET_SD2_RX_CLK)
58199 #define F_PCS100G_RESET_SD2_RX_CLK    V_PCS100G_RESET_SD2_RX_CLK(1U)
58202 #define V_PCS100G_RESET_SD3_RX_CLK(x) ((x) << S_PCS100G_RESET_SD3_RX_CLK)
58203 #define F_PCS100G_RESET_SD3_RX_CLK    V_PCS100G_RESET_SD3_RX_CLK(1U)
58206 #define V_MAC40G100G_RESET_TXCLK(x) ((x) << S_MAC40G100G_RESET_TXCLK)
58207 #define F_MAC40G100G_RESET_TXCLK    V_MAC40G100G_RESET_TXCLK(1U)
58210 #define V_MAC40G100G_RESET_RXCLK(x) ((x) << S_MAC40G100G_RESET_RXCLK)
58211 #define F_MAC40G100G_RESET_RXCLK    V_MAC40G100G_RESET_RXCLK(1U)
58214 #define V_MAC40G100G_RESET_FF_TX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_TX_CLK)
58215 #define F_MAC40G100G_RESET_FF_TX_CLK    V_MAC40G100G_RESET_FF_TX_CLK(1U)
58218 #define V_MAC40G100G_RESET_FF_RX_CLK(x) ((x) << S_MAC40G100G_RESET_FF_RX_CLK)
58219 #define F_MAC40G100G_RESET_FF_RX_CLK    V_MAC40G100G_RESET_FF_RX_CLK(1U)
58222 #define V_MAC40G100G_RESET_TS_CLK(x) ((x) << S_MAC40G100G_RESET_TS_CLK)
58223 #define F_MAC40G100G_RESET_TS_CLK    V_MAC40G100G_RESET_TS_CLK(1U)
58226 #define V_MAC1G10G_RESET_RXCLK(x) ((x) << S_MAC1G10G_RESET_RXCLK)
58227 #define F_MAC1G10G_RESET_RXCLK    V_MAC1G10G_RESET_RXCLK(1U)
58230 #define V_MAC1G10G_RESET_TXCLK(x) ((x) << S_MAC1G10G_RESET_TXCLK)
58231 #define F_MAC1G10G_RESET_TXCLK    V_MAC1G10G_RESET_TXCLK(1U)
58234 #define V_MAC1G10G_RESET_FF_RX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_RX_CLK)
58235 #define F_MAC1G10G_RESET_FF_RX_CLK    V_MAC1G10G_RESET_FF_RX_CLK(1U)
58237 #define S_MAC1G10G_RESET_FF_TX_CLK    1
58238 #define V_MAC1G10G_RESET_FF_TX_CLK(x) ((x) << S_MAC1G10G_RESET_FF_TX_CLK)
58239 #define F_MAC1G10G_RESET_FF_TX_CLK    V_MAC1G10G_RESET_FF_TX_CLK(1U)
58242 #define V_XGMII_CLK_RESET(x) ((x) << S_XGMII_CLK_RESET)
58243 #define F_XGMII_CLK_RESET    V_XGMII_CLK_RESET(1U)
58248 #define V_AN_GATE_SD_TX_CLK(x) ((x) << S_AN_GATE_SD_TX_CLK)
58249 #define F_AN_GATE_SD_TX_CLK    V_AN_GATE_SD_TX_CLK(1U)
58252 #define V_AN_GATE_SD_RX_CLK(x) ((x) << S_AN_GATE_SD_RX_CLK)
58253 #define F_AN_GATE_SD_RX_CLK    V_AN_GATE_SD_RX_CLK(1U)
58256 #define V_SGMII_GATE_TX_CLK(x) ((x) << S_SGMII_GATE_TX_CLK)
58257 #define F_SGMII_GATE_TX_CLK    V_SGMII_GATE_TX_CLK(1U)
58260 #define V_SGMII_GATE_RX_CLK(x) ((x) << S_SGMII_GATE_RX_CLK)
58261 #define F_SGMII_GATE_RX_CLK    V_SGMII_GATE_RX_CLK(1U)
58264 #define V_SGMII_GATE_REF_CLK(x) ((x) << S_SGMII_GATE_REF_CLK)
58265 #define F_SGMII_GATE_REF_CLK    V_SGMII_GATE_REF_CLK(1U)
58268 #define V_PCS10G_GATE_XFI_RXCLK(x) ((x) << S_PCS10G_GATE_XFI_RXCLK)
58269 #define F_PCS10G_GATE_XFI_RXCLK    V_PCS10G_GATE_XFI_RXCLK(1U)
58272 #define V_PCS10G_GATE_XFI_TXCLK(x) ((x) << S_PCS10G_GATE_XFI_TXCLK)
58273 #define F_PCS10G_GATE_XFI_TXCLK    V_PCS10G_GATE_XFI_TXCLK(1U)
58276 #define V_PCS10G_GATE_SD_TX_CLK(x) ((x) << S_PCS10G_GATE_SD_TX_CLK)
58277 #define F_PCS10G_GATE_SD_TX_CLK    V_PCS10G_GATE_SD_TX_CLK(1U)
58280 #define V_PCS10G_GATE_SD_RX_CLK(x) ((x) << S_PCS10G_GATE_SD_RX_CLK)
58281 #define F_PCS10G_GATE_SD_RX_CLK    V_PCS10G_GATE_SD_RX_CLK(1U)
58284 #define V_PCS40G_GATE_RXCLK(x) ((x) << S_PCS40G_GATE_RXCLK)
58285 #define F_PCS40G_GATE_RXCLK    V_PCS40G_GATE_RXCLK(1U)
58288 #define V_PCS40G_GATE_SD_TX_CLK(x) ((x) << S_PCS40G_GATE_SD_TX_CLK)
58289 #define F_PCS40G_GATE_SD_TX_CLK    V_PCS40G_GATE_SD_TX_CLK(1U)
58292 #define V_PCS40G_GATE_SD_RX_CLK(x) ((x) << S_PCS40G_GATE_SD_RX_CLK)
58293 #define F_PCS40G_GATE_SD_RX_CLK    V_PCS40G_GATE_SD_RX_CLK(1U)
58296 #define V_PCS100G_GATE_CGMII_RXCLK(x) ((x) << S_PCS100G_GATE_CGMII_RXCLK)
58297 #define F_PCS100G_GATE_CGMII_RXCLK    V_PCS100G_GATE_CGMII_RXCLK(1U)
58300 #define V_PCS100G_GATE_CGMII_TXCLK(x) ((x) << S_PCS100G_GATE_CGMII_TXCLK)
58301 #define F_PCS100G_GATE_CGMII_TXCLK    V_PCS100G_GATE_CGMII_TXCLK(1U)
58304 #define V_PCS100G_GATE_TX_CLK(x) ((x) << S_PCS100G_GATE_TX_CLK)
58305 #define F_PCS100G_GATE_TX_CLK    V_PCS100G_GATE_TX_CLK(1U)
58308 #define V_PCS100G_GATE_SD_RX_CLK(x) ((x) << S_PCS100G_GATE_SD_RX_CLK)
58309 #define F_PCS100G_GATE_SD_RX_CLK    V_PCS100G_GATE_SD_RX_CLK(1U)
58312 #define V_MAC40G100G_GATE_TXCLK(x) ((x) << S_MAC40G100G_GATE_TXCLK)
58313 #define F_MAC40G100G_GATE_TXCLK    V_MAC40G100G_GATE_TXCLK(1U)
58316 #define V_MAC40G100G_GATE_RXCLK(x) ((x) << S_MAC40G100G_GATE_RXCLK)
58317 #define F_MAC40G100G_GATE_RXCLK    V_MAC40G100G_GATE_RXCLK(1U)
58320 #define V_MAC40G100G_GATE_FF_TX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_TX_CLK)
58321 #define F_MAC40G100G_GATE_FF_TX_CLK    V_MAC40G100G_GATE_FF_TX_CLK(1U)
58324 #define V_MAC40G100G_GATE_FF_RX_CLK(x) ((x) << S_MAC40G100G_GATE_FF_RX_CLK)
58325 #define F_MAC40G100G_GATE_FF_RX_CLK    V_MAC40G100G_GATE_FF_RX_CLK(1U)
58328 #define V_MAC40G100G_TS_CLK(x) ((x) << S_MAC40G100G_TS_CLK)
58329 #define F_MAC40G100G_TS_CLK    V_MAC40G100G_TS_CLK(1U)
58332 #define V_MAC1G10G_GATE_RXCLK(x) ((x) << S_MAC1G10G_GATE_RXCLK)
58333 #define F_MAC1G10G_GATE_RXCLK    V_MAC1G10G_GATE_RXCLK(1U)
58336 #define V_MAC1G10G_GATE_TXCLK(x) ((x) << S_MAC1G10G_GATE_TXCLK)
58337 #define F_MAC1G10G_GATE_TXCLK    V_MAC1G10G_GATE_TXCLK(1U)
58340 #define V_MAC1G10G_GATE_FF_RX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_RX_CLK)
58341 #define F_MAC1G10G_GATE_FF_RX_CLK    V_MAC1G10G_GATE_FF_RX_CLK(1U)
58344 #define V_MAC1G10G_GATE_FF_TX_CLK(x) ((x) << S_MAC1G10G_GATE_FF_TX_CLK)
58345 #define F_MAC1G10G_GATE_FF_TX_CLK    V_MAC1G10G_GATE_FF_TX_CLK(1U)
58348 #define V_AEC_RX(x) ((x) << S_AEC_RX)
58349 #define F_AEC_RX    V_AEC_RX(1U)
58352 #define V_AEC_TX(x) ((x) << S_AEC_TX)
58353 #define F_AEC_TX    V_AEC_TX(1U)
58356 #define V_PCS100G_CLK_ENABLE(x) ((x) << S_PCS100G_CLK_ENABLE)
58357 #define F_PCS100G_CLK_ENABLE    V_PCS100G_CLK_ENABLE(1U)
58360 #define V_PCS40G_CLK_ENABLE(x) ((x) << S_PCS40G_CLK_ENABLE)
58361 #define F_PCS40G_CLK_ENABLE    V_PCS40G_CLK_ENABLE(1U)
58364 #define V_PCS10G_CLK_ENABLE(x) ((x) << S_PCS10G_CLK_ENABLE)
58365 #define F_PCS10G_CLK_ENABLE    V_PCS10G_CLK_ENABLE(1U)
58367 #define S_PCS1G_CLK_ENABLE    1
58368 #define V_PCS1G_CLK_ENABLE(x) ((x) << S_PCS1G_CLK_ENABLE)
58369 #define F_PCS1G_CLK_ENABLE    V_PCS1G_CLK_ENABLE(1U)
58372 #define V_AN_CLK_ENABLE(x) ((x) << S_AN_CLK_ENABLE)
58373 #define F_AN_CLK_ENABLE    V_AN_CLK_ENABLE(1U)
58378 #define V_AN_DONE(x) ((x) << S_AN_DONE)
58379 #define F_AN_DONE    V_AN_DONE(1U)
58382 #define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
58383 #define F_ALIGN_DONE    V_ALIGN_DONE(1U)
58386 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
58387 #define F_BLOCK_LOCK    V_BLOCK_LOCK(1U)
58390 #define V_HI_BER_ST(x) ((x) << S_HI_BER_ST)
58391 #define F_HI_BER_ST    V_HI_BER_ST(1U)
58394 #define V_AN_DONE_ST(x) ((x) << S_AN_DONE_ST)
58395 #define F_AN_DONE_ST    V_AN_DONE_ST(1U)
58400 #define V_AEC_SYS_LANE_TYPE_3(x) ((x) << S_AEC_SYS_LANE_TYPE_3)
58401 #define F_AEC_SYS_LANE_TYPE_3    V_AEC_SYS_LANE_TYPE_3(1U)
58404 #define V_AEC_SYS_LANE_TYPE_2(x) ((x) << S_AEC_SYS_LANE_TYPE_2)
58405 #define F_AEC_SYS_LANE_TYPE_2    V_AEC_SYS_LANE_TYPE_2(1U)
58408 #define V_AEC_SYS_LANE_TYPE_1(x) ((x) << S_AEC_SYS_LANE_TYPE_1)
58409 #define F_AEC_SYS_LANE_TYPE_1    V_AEC_SYS_LANE_TYPE_1(1U)
58412 #define V_AEC_SYS_LANE_TYPE_0(x) ((x) << S_AEC_SYS_LANE_TYPE_0)
58413 #define F_AEC_SYS_LANE_TYPE_0    V_AEC_SYS_LANE_TYPE_0(1U)
58417 #define V_AEC_SYS_LANE_SELECT_3(x) ((x) << S_AEC_SYS_LANE_SELECT_3)
58418 #define G_AEC_SYS_LANE_SELECT_3(x) (((x) >> S_AEC_SYS_LANE_SELECT_3) & M_AEC_SYS_LANE_SELECT_3)
58422 #define V_AEC_SYS_LANE_SELECT_2(x) ((x) << S_AEC_SYS_LANE_SELECT_2)
58423 #define G_AEC_SYS_LANE_SELECT_2(x) (((x) >> S_AEC_SYS_LANE_SELECT_2) & M_AEC_SYS_LANE_SELECT_2)
58427 #define V_AEC_SYS_LANE_SELECT_1(x) ((x) << S_AEC_SYS_LANE_SELECT_1)
58428 #define G_AEC_SYS_LANE_SELECT_1(x) (((x) >> S_AEC_SYS_LANE_SELECT_1) & M_AEC_SYS_LANE_SELECT_1)
58432 #define V_AEC_SYS_LANE_SELECT_O(x) ((x) << S_AEC_SYS_LANE_SELECT_O)
58433 #define G_AEC_SYS_LANE_SELECT_O(x) (((x) >> S_AEC_SYS_LANE_SELECT_O) & M_AEC_SYS_LANE_SELECT_O)
58438 #define V_AEC_RX_UNKNOWN_LANE_3(x) ((x) << S_AEC_RX_UNKNOWN_LANE_3)
58439 #define F_AEC_RX_UNKNOWN_LANE_3    V_AEC_RX_UNKNOWN_LANE_3(1U)
58442 #define V_AEC_RX_UNKNOWN_LANE_2(x) ((x) << S_AEC_RX_UNKNOWN_LANE_2)
58443 #define F_AEC_RX_UNKNOWN_LANE_2    V_AEC_RX_UNKNOWN_LANE_2(1U)
58446 #define V_AEC_RX_UNKNOWN_LANE_1(x) ((x) << S_AEC_RX_UNKNOWN_LANE_1)
58447 #define F_AEC_RX_UNKNOWN_LANE_1    V_AEC_RX_UNKNOWN_LANE_1(1U)
58450 #define V_AEC_RX_UNKNOWN_LANE_0(x) ((x) << S_AEC_RX_UNKNOWN_LANE_0)
58451 #define F_AEC_RX_UNKNOWN_LANE_0    V_AEC_RX_UNKNOWN_LANE_0(1U)
58455 #define V_AEC_RX_LANE_ID_3(x) ((x) << S_AEC_RX_LANE_ID_3)
58456 #define G_AEC_RX_LANE_ID_3(x) (((x) >> S_AEC_RX_LANE_ID_3) & M_AEC_RX_LANE_ID_3)
58460 #define V_AEC_RX_LANE_ID_2(x) ((x) << S_AEC_RX_LANE_ID_2)
58461 #define G_AEC_RX_LANE_ID_2(x) (((x) >> S_AEC_RX_LANE_ID_2) & M_AEC_RX_LANE_ID_2)
58465 #define V_AEC_RX_LANE_ID_1(x) ((x) << S_AEC_RX_LANE_ID_1)
58466 #define G_AEC_RX_LANE_ID_1(x) (((x) >> S_AEC_RX_LANE_ID_1) & M_AEC_RX_LANE_ID_1)
58470 #define V_AEC_RX_LANE_ID_O(x) ((x) << S_AEC_RX_LANE_ID_O)
58471 #define G_AEC_RX_LANE_ID_O(x) (((x) >> S_AEC_RX_LANE_ID_O) & M_AEC_RX_LANE_ID_O)
58477 #define V_XGMII_CLK_IN_1MS_LO_40G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_40G)
58478 #define G_XGMII_CLK_IN_1MS_LO_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_40G) & M_XGMII_CLK_IN_1MS_LO_40G)
58484 #define V_XGMII_CLK_IN_1MS_HI_40G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_40G)
58485 #define G_XGMII_CLK_IN_1MS_HI_40G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_40G) & M_XGMII_CLK_IN_1MS_HI_40G)
58491 #define V_XGMII_CLK_IN_1MS_LO_100G(x) ((x) << S_XGMII_CLK_IN_1MS_LO_100G)
58492 #define G_XGMII_CLK_IN_1MS_LO_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_LO_100G) & M_XGMII_CLK_IN_1MS_LO_100G)
58498 #define V_XGMII_CLK_IN_1MS_HI_100G(x) ((x) << S_XGMII_CLK_IN_1MS_HI_100G)
58499 #define G_XGMII_CLK_IN_1MS_HI_100G(x) (((x) >> S_XGMII_CLK_IN_1MS_HI_100G) & M_XGMII_CLK_IN_1MS_HI_100G)
58505 #define V_CTL_FSM_CUR_STATE(x) ((x) << S_CTL_FSM_CUR_STATE)
58506 #define G_CTL_FSM_CUR_STATE(x) (((x) >> S_CTL_FSM_CUR_STATE) & M_CTL_FSM_CUR_STATE)
58510 #define V_CIN_FSM_CUR_STATE(x) ((x) << S_CIN_FSM_CUR_STATE)
58511 #define G_CIN_FSM_CUR_STATE(x) (((x) >> S_CIN_FSM_CUR_STATE) & M_CIN_FSM_CUR_STATE)
58515 #define V_CRI_FSM_CUR_STATE(x) ((x) << S_CRI_FSM_CUR_STATE)
58516 #define G_CRI_FSM_CUR_STATE(x) (((x) >> S_CRI_FSM_CUR_STATE) & M_CRI_FSM_CUR_STATE)
58520 #define V_CU_C3_ACK_VALUE(x) ((x) << S_CU_C3_ACK_VALUE)
58521 #define G_CU_C3_ACK_VALUE(x) (((x) >> S_CU_C3_ACK_VALUE) & M_CU_C3_ACK_VALUE)
58525 #define V_CU_C2_ACK_VALUE(x) ((x) << S_CU_C2_ACK_VALUE)
58526 #define G_CU_C2_ACK_VALUE(x) (((x) >> S_CU_C2_ACK_VALUE) & M_CU_C2_ACK_VALUE)
58530 #define V_CU_C1_ACK_VALUE(x) ((x) << S_CU_C1_ACK_VALUE)
58531 #define G_CU_C1_ACK_VALUE(x) (((x) >> S_CU_C1_ACK_VALUE) & M_CU_C1_ACK_VALUE)
58535 #define V_CU_C0_ACK_VALUE(x) ((x) << S_CU_C0_ACK_VALUE)
58536 #define G_CU_C0_ACK_VALUE(x) (((x) >> S_CU_C0_ACK_VALUE) & M_CU_C0_ACK_VALUE)
58539 #define V_CX_INIT(x) ((x) << S_CX_INIT)
58540 #define F_CX_INIT    V_CX_INIT(1U)
58543 #define V_CX_PRESET(x) ((x) << S_CX_PRESET)
58544 #define F_CX_PRESET    V_CX_PRESET(1U)
58548 #define V_CUF_C3_UPDATE(x) ((x) << S_CUF_C3_UPDATE)
58549 #define G_CUF_C3_UPDATE(x) (((x) >> S_CUF_C3_UPDATE) & M_CUF_C3_UPDATE)
58553 #define V_CUF_C2_UPDATE(x) ((x) << S_CUF_C2_UPDATE)
58554 #define G_CUF_C2_UPDATE(x) (((x) >> S_CUF_C2_UPDATE) & M_CUF_C2_UPDATE)
58558 #define V_CUF_C1_UPDATE(x) ((x) << S_CUF_C1_UPDATE)
58559 #define G_CUF_C1_UPDATE(x) (((x) >> S_CUF_C1_UPDATE) & M_CUF_C1_UPDATE)
58563 #define V_CUF_C0_UPDATE(x) ((x) << S_CUF_C0_UPDATE)
58564 #define G_CUF_C0_UPDATE(x) (((x) >> S_CUF_C0_UPDATE) & M_CUF_C0_UPDATE)
58567 #define V_REG_FPH_ATTR_TXUPDAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXUPDAT_VALID)
58568 #define F_REG_FPH_ATTR_TXUPDAT_VALID    V_REG_FPH_ATTR_TXUPDAT_VALID(1U)
58570 #define S_REG_FPH_ATTR_TXSTAT_VALID    1
58571 #define V_REG_FPH_ATTR_TXSTAT_VALID(x) ((x) << S_REG_FPH_ATTR_TXSTAT_VALID)
58572 #define F_REG_FPH_ATTR_TXSTAT_VALID    V_REG_FPH_ATTR_TXSTAT_VALID(1U)
58575 #define V_REG_MAN_DEC_REQ(x) ((x) << S_REG_MAN_DEC_REQ)
58576 #define F_REG_MAN_DEC_REQ    V_REG_MAN_DEC_REQ(1U)
58581 #define V_FC_LSNA_(x) ((x) << S_FC_LSNA_)
58582 #define F_FC_LSNA_    V_FC_LSNA_(1U)
58586 #define V_CUF_C0_FSM_DEBUG(x) ((x) << S_CUF_C0_FSM_DEBUG)
58587 #define G_CUF_C0_FSM_DEBUG(x) (((x) >> S_CUF_C0_FSM_DEBUG) & M_CUF_C0_FSM_DEBUG)
58591 #define V_CUF_C1_FSM_DEBUG(x) ((x) << S_CUF_C1_FSM_DEBUG)
58592 #define G_CUF_C1_FSM_DEBUG(x) (((x) >> S_CUF_C1_FSM_DEBUG) & M_CUF_C1_FSM_DEBUG)
58596 #define V_CUF_C2_FSM_DEBUG(x) ((x) << S_CUF_C2_FSM_DEBUG)
58597 #define G_CUF_C2_FSM_DEBUG(x) (((x) >> S_CUF_C2_FSM_DEBUG) & M_CUF_C2_FSM_DEBUG)
58601 #define V_LCK_FSM_CUR_STATE(x) ((x) << S_LCK_FSM_CUR_STATE)
58602 #define G_LCK_FSM_CUR_STATE(x) (((x) >> S_LCK_FSM_CUR_STATE) & M_LCK_FSM_CUR_STATE)
58613 #define V_MAC40G100G_TX_UNDERFLOW(x) ((x) << S_MAC40G100G_TX_UNDERFLOW)
58614 #define F_MAC40G100G_TX_UNDERFLOW    V_MAC40G100G_TX_UNDERFLOW(1U)
58617 #define V_MAC1G10G_MAGIC_IND(x) ((x) << S_MAC1G10G_MAGIC_IND)
58618 #define F_MAC1G10G_MAGIC_IND    V_MAC1G10G_MAGIC_IND(1U)
58621 #define V_MAC1G10G_FF_RX_EMPTY(x) ((x) << S_MAC1G10G_FF_RX_EMPTY)
58622 #define F_MAC1G10G_FF_RX_EMPTY    V_MAC1G10G_FF_RX_EMPTY(1U)
58625 #define V_MAC1G10G_FF_TX_OVR_ERR(x) ((x) << S_MAC1G10G_FF_TX_OVR_ERR)
58626 #define F_MAC1G10G_FF_TX_OVR_ERR    V_MAC1G10G_FF_TX_OVR_ERR(1U)
58630 #define V_MAC1G10G_IF_MODE_ENA(x) ((x) << S_MAC1G10G_IF_MODE_ENA)
58631 #define G_MAC1G10G_IF_MODE_ENA(x) (((x) >> S_MAC1G10G_IF_MODE_ENA) & M_MAC1G10G_IF_MODE_ENA)
58634 #define V_MAC1G10G_MII_ENA_10(x) ((x) << S_MAC1G10G_MII_ENA_10)
58635 #define F_MAC1G10G_MII_ENA_10    V_MAC1G10G_MII_ENA_10(1U)
58638 #define V_MAC1G10G_PAUSE_ON(x) ((x) << S_MAC1G10G_PAUSE_ON)
58639 #define F_MAC1G10G_PAUSE_ON    V_MAC1G10G_PAUSE_ON(1U)
58642 #define V_MAC1G10G_PFC_MODE(x) ((x) << S_MAC1G10G_PFC_MODE)
58643 #define F_MAC1G10G_PFC_MODE    V_MAC1G10G_PFC_MODE(1U)
58646 #define V_MAC1G10G_RX_SFD_O(x) ((x) << S_MAC1G10G_RX_SFD_O)
58647 #define F_MAC1G10G_RX_SFD_O    V_MAC1G10G_RX_SFD_O(1U)
58650 #define V_MAC1G10G_TX_EMPTY(x) ((x) << S_MAC1G10G_TX_EMPTY)
58651 #define F_MAC1G10G_TX_EMPTY    V_MAC1G10G_TX_EMPTY(1U)
58654 #define V_MAC1G10G_TX_SFD_O(x) ((x) << S_MAC1G10G_TX_SFD_O)
58655 #define F_MAC1G10G_TX_SFD_O    V_MAC1G10G_TX_SFD_O(1U)
58657 #define S_MAC1G10G_TX_TS_FRM_OUT    1
58658 #define V_MAC1G10G_TX_TS_FRM_OUT(x) ((x) << S_MAC1G10G_TX_TS_FRM_OUT)
58659 #define F_MAC1G10G_TX_TS_FRM_OUT    V_MAC1G10G_TX_TS_FRM_OUT(1U)
58662 #define V_MAC1G10G_TX_UNDERFLOW(x) ((x) << S_MAC1G10G_TX_UNDERFLOW)
58663 #define F_MAC1G10G_TX_UNDERFLOW    V_MAC1G10G_TX_UNDERFLOW(1U)
58669 #define V_MAC40G100G_FF_TX_PFC_XOFF(x) ((x) << S_MAC40G100G_FF_TX_PFC_XOFF)
58670 #define G_MAC40G100G_FF_TX_PFC_XOFF(x) (((x) >> S_MAC40G100G_FF_TX_PFC_XOFF) & M_MAC40G100G_FF_TX_PFC_XOFF)
58673 #define V_MAC40G100G_TX_LOC_FAULT(x) ((x) << S_MAC40G100G_TX_LOC_FAULT)
58674 #define F_MAC40G100G_TX_LOC_FAULT    V_MAC40G100G_TX_LOC_FAULT(1U)
58677 #define V_MAC40G100G_TX_REM_FAULT(x) ((x) << S_MAC40G100G_TX_REM_FAULT)
58678 #define F_MAC40G100G_TX_REM_FAULT    V_MAC40G100G_TX_REM_FAULT(1U)
58681 #define V_MAC40G_LOOP_BCK(x) ((x) << S_MAC40G_LOOP_BCK)
58682 #define F_MAC40G_LOOP_BCK    V_MAC40G_LOOP_BCK(1U)
58685 #define V_MAC1G10G_MAGIC_ENA(x) ((x) << S_MAC1G10G_MAGIC_ENA)
58686 #define F_MAC1G10G_MAGIC_ENA    V_MAC1G10G_MAGIC_ENA(1U)
58690 #define V_MAC1G10G_IF_MODE_SET(x) ((x) << S_MAC1G10G_IF_MODE_SET)
58691 #define G_MAC1G10G_IF_MODE_SET(x) (((x) >> S_MAC1G10G_IF_MODE_SET) & M_MAC1G10G_IF_MODE_SET)
58694 #define V_MAC1G10G_TX_LOC_FAULT(x) ((x) << S_MAC1G10G_TX_LOC_FAULT)
58695 #define F_MAC1G10G_TX_LOC_FAULT    V_MAC1G10G_TX_LOC_FAULT(1U)
58698 #define V_MAC1G10G_TX_REM_FAULT(x) ((x) << S_MAC1G10G_TX_REM_FAULT)
58699 #define F_MAC1G10G_TX_REM_FAULT    V_MAC1G10G_TX_REM_FAULT(1U)
58701 #define S_MAC1G10G_XOFF_GEN    1
58703 #define V_MAC1G10G_XOFF_GEN(x) ((x) << S_MAC1G10G_XOFF_GEN)
58704 #define G_MAC1G10G_XOFF_GEN(x) (((x) >> S_MAC1G10G_XOFF_GEN) & M_MAC1G10G_XOFF_GEN)
58707 #define V_MAC1G_LOOP_BCK(x) ((x) << S_MAC1G_LOOP_BCK)
58708 #define F_MAC1G_LOOP_BCK    V_MAC1G_LOOP_BCK(1U)
58714 #define V_FPGA_LOCK(x) ((x) << S_FPGA_LOCK)
58715 #define G_FPGA_LOCK(x) (((x) >> S_FPGA_LOCK) & M_FPGA_LOCK)
58718 #define V_T6_AN_DONE(x) ((x) << S_T6_AN_DONE)
58719 #define F_T6_AN_DONE    V_T6_AN_DONE(1U)
58722 #define V_AN_INT(x) ((x) << S_AN_INT)
58723 #define F_AN_INT    V_AN_INT(1U)
58726 #define V_AN_PCS_RX_CLK_ENA(x) ((x) << S_AN_PCS_RX_CLK_ENA)
58727 #define F_AN_PCS_RX_CLK_ENA    V_AN_PCS_RX_CLK_ENA(1U)
58730 #define V_AN_PCS_TX_CLK_ENA(x) ((x) << S_AN_PCS_TX_CLK_ENA)
58731 #define F_AN_PCS_TX_CLK_ENA    V_AN_PCS_TX_CLK_ENA(1U)
58735 #define V_AN_SELECT(x) ((x) << S_AN_SELECT)
58736 #define G_AN_SELECT(x) (((x) >> S_AN_SELECT) & M_AN_SELECT)
58739 #define V_AN_PROG(x) ((x) << S_AN_PROG)
58740 #define F_AN_PROG    V_AN_PROG(1U)
58744 #define V_PCS40G_BLOCK_LOCK(x) ((x) << S_PCS40G_BLOCK_LOCK)
58745 #define G_PCS40G_BLOCK_LOCK(x) (((x) >> S_PCS40G_BLOCK_LOCK) & M_PCS40G_BLOCK_LOCK)
58748 #define V_PCS40G_BER_TIMER_DONE(x) ((x) << S_PCS40G_BER_TIMER_DONE)
58749 #define F_PCS40G_BER_TIMER_DONE    V_PCS40G_BER_TIMER_DONE(1U)
58752 #define V_PCS10G_FEC_LOCKED(x) ((x) << S_PCS10G_FEC_LOCKED)
58753 #define F_PCS10G_FEC_LOCKED    V_PCS10G_FEC_LOCKED(1U)
58756 #define V_PCS10G_BLOCK_LOCK(x) ((x) << S_PCS10G_BLOCK_LOCK)
58757 #define F_PCS10G_BLOCK_LOCK    V_PCS10G_BLOCK_LOCK(1U)
58760 #define V_SGMII_GMII_COL(x) ((x) << S_SGMII_GMII_COL)
58761 #define F_SGMII_GMII_COL    V_SGMII_GMII_COL(1U)
58764 #define V_SGMII_GMII_CRS(x) ((x) << S_SGMII_GMII_CRS)
58765 #define F_SGMII_GMII_CRS    V_SGMII_GMII_CRS(1U)
58768 #define V_SGMII_SD_LOOPBACK(x) ((x) << S_SGMII_SD_LOOPBACK)
58769 #define F_SGMII_SD_LOOPBACK    V_SGMII_SD_LOOPBACK(1U)
58772 #define V_SGMII_SG_AN_DONE(x) ((x) << S_SGMII_SG_AN_DONE)
58773 #define F_SGMII_SG_AN_DONE    V_SGMII_SG_AN_DONE(1U)
58776 #define V_SGMII_SG_HD(x) ((x) << S_SGMII_SG_HD)
58777 #define F_SGMII_SG_HD    V_SGMII_SG_HD(1U)
58780 #define V_SGMII_SG_PAGE_RX(x) ((x) << S_SGMII_SG_PAGE_RX)
58781 #define F_SGMII_SG_PAGE_RX    V_SGMII_SG_PAGE_RX(1U)
58784 #define V_SGMII_SG_RX_SYNC(x) ((x) << S_SGMII_SG_RX_SYNC)
58785 #define F_SGMII_SG_RX_SYNC    V_SGMII_SG_RX_SYNC(1U)
58789 #define V_SGMII_SG_SPEED(x) ((x) << S_SGMII_SG_SPEED)
58790 #define G_SGMII_SG_SPEED(x) (((x) >> S_SGMII_SG_SPEED) & M_SGMII_SG_SPEED)
58795 #define V_TX_LI_FAULT(x) ((x) << S_TX_LI_FAULT)
58796 #define F_TX_LI_FAULT    V_TX_LI_FAULT(1U)
58799 #define V_T6_PAD(x) ((x) << S_T6_PAD)
58800 #define F_T6_PAD    V_T6_PAD(1U)
58804 #define V_BLK_STB_VAL(x) ((x) << S_BLK_STB_VAL)
58805 #define G_BLK_STB_VAL(x) (((x) >> S_BLK_STB_VAL) & M_BLK_STB_VAL)
58809 #define V_DEBUG_SEL(x) ((x) << S_DEBUG_SEL)
58810 #define G_DEBUG_SEL(x) (((x) >> S_DEBUG_SEL) & M_DEBUG_SEL)
58814 #define V_SGMII_LOOP(x) ((x) << S_SGMII_LOOP)
58815 #define G_SGMII_LOOP(x) (((x) >> S_SGMII_LOOP) & M_SGMII_LOOP)
58818 #define V_AN_DIS_TIMER(x) ((x) << S_AN_DIS_TIMER)
58819 #define F_AN_DIS_TIMER    V_AN_DIS_TIMER(1U)
58822 #define V_PCS100G_BER_TIMER_SHORT(x) ((x) << S_PCS100G_BER_TIMER_SHORT)
58823 #define F_PCS100G_BER_TIMER_SHORT    V_PCS100G_BER_TIMER_SHORT(1U)
58827 #define V_PCS100G_TX_LANE_THRESH(x) ((x) << S_PCS100G_TX_LANE_THRESH)
58828 #define G_PCS100G_TX_LANE_THRESH(x) (((x) >> S_PCS100G_TX_LANE_THRESH) & M_PCS100G_TX_LANE_THRESH)
58831 #define V_PCS100G_VL_INTVL(x) ((x) << S_PCS100G_VL_INTVL)
58832 #define F_PCS100G_VL_INTVL    V_PCS100G_VL_INTVL(1U)
58836 #define V_SGMII_TX_LANE_CKMULT(x) ((x) << S_SGMII_TX_LANE_CKMULT)
58837 #define G_SGMII_TX_LANE_CKMULT(x) (((x) >> S_SGMII_TX_LANE_CKMULT) & M_SGMII_TX_LANE_CKMULT)
58841 #define V_SGMII_TX_LANE_THRESH(x) ((x) << S_SGMII_TX_LANE_THRESH)
58842 #define G_SGMII_TX_LANE_THRESH(x) (((x) >> S_SGMII_TX_LANE_THRESH) & M_SGMII_TX_LANE_THRESH)
58847 #define V_PCS100G_ALIGN_LOCK(x) ((x) << S_PCS100G_ALIGN_LOCK)
58848 #define F_PCS100G_ALIGN_LOCK    V_PCS100G_ALIGN_LOCK(1U)
58851 #define V_PCS100G_BER_TIMER_DONE(x) ((x) << S_PCS100G_BER_TIMER_DONE)
58852 #define F_PCS100G_BER_TIMER_DONE    V_PCS100G_BER_TIMER_DONE(1U)
58856 #define V_PCS100G_BLOCK_LOCK(x) ((x) << S_PCS100G_BLOCK_LOCK)
58857 #define G_PCS100G_BLOCK_LOCK(x) (((x) >> S_PCS100G_BLOCK_LOCK) & M_PCS100G_BLOCK_LOCK)
58862 #define V_PERR_RX_FEC100G_DLY(x) ((x) << S_PERR_RX_FEC100G_DLY)
58863 #define F_PERR_RX_FEC100G_DLY    V_PERR_RX_FEC100G_DLY(1U)
58866 #define V_PERR_RX_FEC100G(x) ((x) << S_PERR_RX_FEC100G)
58867 #define F_PERR_RX_FEC100G    V_PERR_RX_FEC100G(1U)
58870 #define V_PERR_RX3_FEC100G_DK(x) ((x) << S_PERR_RX3_FEC100G_DK)
58871 #define F_PERR_RX3_FEC100G_DK    V_PERR_RX3_FEC100G_DK(1U)
58874 #define V_PERR_RX2_FEC100G_DK(x) ((x) << S_PERR_RX2_FEC100G_DK)
58875 #define F_PERR_RX2_FEC100G_DK    V_PERR_RX2_FEC100G_DK(1U)
58878 #define V_PERR_RX1_FEC100G_DK(x) ((x) << S_PERR_RX1_FEC100G_DK)
58879 #define F_PERR_RX1_FEC100G_DK    V_PERR_RX1_FEC100G_DK(1U)
58882 #define V_PERR_RX0_FEC100G_DK(x) ((x) << S_PERR_RX0_FEC100G_DK)
58883 #define F_PERR_RX0_FEC100G_DK    V_PERR_RX0_FEC100G_DK(1U)
58886 #define V_PERR_TX3_PCS100G(x) ((x) << S_PERR_TX3_PCS100G)
58887 #define F_PERR_TX3_PCS100G    V_PERR_TX3_PCS100G(1U)
58890 #define V_PERR_TX2_PCS100G(x) ((x) << S_PERR_TX2_PCS100G)
58891 #define F_PERR_TX2_PCS100G    V_PERR_TX2_PCS100G(1U)
58894 #define V_PERR_TX1_PCS100G(x) ((x) << S_PERR_TX1_PCS100G)
58895 #define F_PERR_TX1_PCS100G    V_PERR_TX1_PCS100G(1U)
58898 #define V_PERR_TX0_PCS100G(x) ((x) << S_PERR_TX0_PCS100G)
58899 #define F_PERR_TX0_PCS100G    V_PERR_TX0_PCS100G(1U)
58902 #define V_PERR_RX19_PCS100G(x) ((x) << S_PERR_RX19_PCS100G)
58903 #define F_PERR_RX19_PCS100G    V_PERR_RX19_PCS100G(1U)
58906 #define V_PERR_RX18_PCS100G(x) ((x) << S_PERR_RX18_PCS100G)
58907 #define F_PERR_RX18_PCS100G    V_PERR_RX18_PCS100G(1U)
58910 #define V_PERR_RX17_PCS100G(x) ((x) << S_PERR_RX17_PCS100G)
58911 #define F_PERR_RX17_PCS100G    V_PERR_RX17_PCS100G(1U)
58914 #define V_PERR_RX16_PCS100G(x) ((x) << S_PERR_RX16_PCS100G)
58915 #define F_PERR_RX16_PCS100G    V_PERR_RX16_PCS100G(1U)
58918 #define V_PERR_RX15_PCS100G(x) ((x) << S_PERR_RX15_PCS100G)
58919 #define F_PERR_RX15_PCS100G    V_PERR_RX15_PCS100G(1U)
58922 #define V_PERR_RX14_PCS100G(x) ((x) << S_PERR_RX14_PCS100G)
58923 #define F_PERR_RX14_PCS100G    V_PERR_RX14_PCS100G(1U)
58926 #define V_PERR_RX13_PCS100G(x) ((x) << S_PERR_RX13_PCS100G)
58927 #define F_PERR_RX13_PCS100G    V_PERR_RX13_PCS100G(1U)
58930 #define V_PERR_RX12_PCS100G(x) ((x) << S_PERR_RX12_PCS100G)
58931 #define F_PERR_RX12_PCS100G    V_PERR_RX12_PCS100G(1U)
58934 #define V_PERR_RX11_PCS100G(x) ((x) << S_PERR_RX11_PCS100G)
58935 #define F_PERR_RX11_PCS100G    V_PERR_RX11_PCS100G(1U)
58938 #define V_PERR_RX10_PCS100G(x) ((x) << S_PERR_RX10_PCS100G)
58939 #define F_PERR_RX10_PCS100G    V_PERR_RX10_PCS100G(1U)
58942 #define V_PERR_RX9_PCS100G(x) ((x) << S_PERR_RX9_PCS100G)
58943 #define F_PERR_RX9_PCS100G    V_PERR_RX9_PCS100G(1U)
58946 #define V_PERR_RX8_PCS100G(x) ((x) << S_PERR_RX8_PCS100G)
58947 #define F_PERR_RX8_PCS100G    V_PERR_RX8_PCS100G(1U)
58950 #define V_PERR_RX7_PCS100G(x) ((x) << S_PERR_RX7_PCS100G)
58951 #define F_PERR_RX7_PCS100G    V_PERR_RX7_PCS100G(1U)
58954 #define V_PERR_RX6_PCS100G(x) ((x) << S_PERR_RX6_PCS100G)
58955 #define F_PERR_RX6_PCS100G    V_PERR_RX6_PCS100G(1U)
58958 #define V_PERR_RX5_PCS100G(x) ((x) << S_PERR_RX5_PCS100G)
58959 #define F_PERR_RX5_PCS100G    V_PERR_RX5_PCS100G(1U)
58962 #define V_PERR_RX4_PCS100G(x) ((x) << S_PERR_RX4_PCS100G)
58963 #define F_PERR_RX4_PCS100G    V_PERR_RX4_PCS100G(1U)
58966 #define V_PERR_RX3_PCS100G(x) ((x) << S_PERR_RX3_PCS100G)
58967 #define F_PERR_RX3_PCS100G    V_PERR_RX3_PCS100G(1U)
58970 #define V_PERR_RX2_PCS100G(x) ((x) << S_PERR_RX2_PCS100G)
58971 #define F_PERR_RX2_PCS100G    V_PERR_RX2_PCS100G(1U)
58973 #define S_PERR_RX1_PCS100G    1
58974 #define V_PERR_RX1_PCS100G(x) ((x) << S_PERR_RX1_PCS100G)
58975 #define F_PERR_RX1_PCS100G    V_PERR_RX1_PCS100G(1U)
58978 #define V_PERR_RX0_PCS100G(x) ((x) << S_PERR_RX0_PCS100G)
58979 #define F_PERR_RX0_PCS100G    V_PERR_RX0_PCS100G(1U)
58998 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
58999 #define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)
59002 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
59003 #define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
59006 #define V_PPS(x) ((x) << S_PPS)
59007 #define F_PPS    V_PPS(1U)
59010 #define V_SINGLE_ALARM(x) ((x) << S_SINGLE_ALARM)
59011 #define F_SINGLE_ALARM    V_SINGLE_ALARM(1U)
59014 #define V_PERIODIC_ALARM(x) ((x) << S_PERIODIC_ALARM)
59015 #define F_PERIODIC_ALARM    V_PERIODIC_ALARM(1U)
59021 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
59022 #define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)
59025 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
59026 #define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)
59029 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
59030 #define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)
59033 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
59034 #define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)
59037 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
59038 #define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)
59041 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
59042 #define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)
59045 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
59046 #define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)
59049 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
59050 #define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)
59053 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
59054 #define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)
59057 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
59058 #define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)
59061 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
59062 #define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)
59065 #define V_RX_STATS(x) ((x) << S_RX_STATS)
59066 #define F_RX_STATS    V_RX_STATS(1U)
59069 #define V_TX_STATS(x) ((x) << S_TX_STATS)
59070 #define F_TX_STATS    V_TX_STATS(1U)
59073 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
59074 #define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)
59077 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
59078 #define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)
59081 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
59082 #define F_PERR3_TX    V_PERR3_TX(1U)
59085 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
59086 #define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)
59089 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
59090 #define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)
59093 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
59094 #define F_PERR2_TX    V_PERR2_TX(1U)
59097 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
59098 #define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)
59101 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
59102 #define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)
59105 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
59106 #define F_PERR1_TX    V_PERR1_TX(1U)
59109 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
59110 #define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)
59112 #define S_PERR0_RX_SD    1
59113 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
59114 #define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)
59117 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
59118 #define F_PERR0_TX    V_PERR0_TX(1U)
59121 #define V_T6_PERR_PKT_RAM(x) ((x) << S_T6_PERR_PKT_RAM)
59122 #define F_T6_PERR_PKT_RAM    V_T6_PERR_PKT_RAM(1U)
59125 #define V_T6_PERR_MASK_RAM(x) ((x) << S_T6_PERR_MASK_RAM)
59126 #define F_T6_PERR_MASK_RAM    V_T6_PERR_MASK_RAM(1U)
59129 #define V_T6_PERR_CRC_RAM(x) ((x) << S_T6_PERR_CRC_RAM)
59130 #define F_T6_PERR_CRC_RAM    V_T6_PERR_CRC_RAM(1U)
59133 #define V_RX_MAC40G(x) ((x) << S_RX_MAC40G)
59134 #define F_RX_MAC40G    V_RX_MAC40G(1U)
59137 #define V_TX_MAC40G(x) ((x) << S_TX_MAC40G)
59138 #define F_TX_MAC40G    V_TX_MAC40G(1U)
59141 #define V_RX_ST_MAC40G(x) ((x) << S_RX_ST_MAC40G)
59142 #define F_RX_ST_MAC40G    V_RX_ST_MAC40G(1U)
59145 #define V_TX_ST_MAC40G(x) ((x) << S_TX_ST_MAC40G)
59146 #define F_TX_ST_MAC40G    V_TX_ST_MAC40G(1U)
59149 #define V_TX_MAC1G10G(x) ((x) << S_TX_MAC1G10G)
59150 #define F_TX_MAC1G10G    V_TX_MAC1G10G(1U)
59153 #define V_RX_MAC1G10G(x) ((x) << S_RX_MAC1G10G)
59154 #define F_RX_MAC1G10G    V_RX_MAC1G10G(1U)
59157 #define V_RX_STATUS_MAC1G10G(x) ((x) << S_RX_STATUS_MAC1G10G)
59158 #define F_RX_STATUS_MAC1G10G    V_RX_STATUS_MAC1G10G(1U)
59161 #define V_RX_ST_MAC1G10G(x) ((x) << S_RX_ST_MAC1G10G)
59162 #define F_RX_ST_MAC1G10G    V_RX_ST_MAC1G10G(1U)
59165 #define V_TX_ST_MAC1G10G(x) ((x) << S_TX_ST_MAC1G10G)
59166 #define F_TX_ST_MAC1G10G    V_TX_ST_MAC1G10G(1U)
59169 #define V_PERR_TX0_PCS40G(x) ((x) << S_PERR_TX0_PCS40G)
59170 #define F_PERR_TX0_PCS40G    V_PERR_TX0_PCS40G(1U)
59173 #define V_PERR_TX1_PCS40G(x) ((x) << S_PERR_TX1_PCS40G)
59174 #define F_PERR_TX1_PCS40G    V_PERR_TX1_PCS40G(1U)
59177 #define V_PERR_TX2_PCS40G(x) ((x) << S_PERR_TX2_PCS40G)
59178 #define F_PERR_TX2_PCS40G    V_PERR_TX2_PCS40G(1U)
59181 #define V_PERR_TX3_PCS40G(x) ((x) << S_PERR_TX3_PCS40G)
59182 #define F_PERR_TX3_PCS40G    V_PERR_TX3_PCS40G(1U)
59185 #define V_PERR_TX0_FEC40G(x) ((x) << S_PERR_TX0_FEC40G)
59186 #define F_PERR_TX0_FEC40G    V_PERR_TX0_FEC40G(1U)
59189 #define V_PERR_TX1_FEC40G(x) ((x) << S_PERR_TX1_FEC40G)
59190 #define F_PERR_TX1_FEC40G    V_PERR_TX1_FEC40G(1U)
59193 #define V_PERR_TX2_FEC40G(x) ((x) << S_PERR_TX2_FEC40G)
59194 #define F_PERR_TX2_FEC40G    V_PERR_TX2_FEC40G(1U)
59197 #define V_PERR_TX3_FEC40G(x) ((x) << S_PERR_TX3_FEC40G)
59198 #define F_PERR_TX3_FEC40G    V_PERR_TX3_FEC40G(1U)
59201 #define V_PERR_RX0_PCS40G(x) ((x) << S_PERR_RX0_PCS40G)
59202 #define F_PERR_RX0_PCS40G    V_PERR_RX0_PCS40G(1U)
59205 #define V_PERR_RX1_PCS40G(x) ((x) << S_PERR_RX1_PCS40G)
59206 #define F_PERR_RX1_PCS40G    V_PERR_RX1_PCS40G(1U)
59209 #define V_PERR_RX2_PCS40G(x) ((x) << S_PERR_RX2_PCS40G)
59210 #define F_PERR_RX2_PCS40G    V_PERR_RX2_PCS40G(1U)
59213 #define V_PERR_RX3_PCS40G(x) ((x) << S_PERR_RX3_PCS40G)
59214 #define F_PERR_RX3_PCS40G    V_PERR_RX3_PCS40G(1U)
59217 #define V_PERR_RX0_FEC40G(x) ((x) << S_PERR_RX0_FEC40G)
59218 #define F_PERR_RX0_FEC40G    V_PERR_RX0_FEC40G(1U)
59221 #define V_PERR_RX1_FEC40G(x) ((x) << S_PERR_RX1_FEC40G)
59222 #define F_PERR_RX1_FEC40G    V_PERR_RX1_FEC40G(1U)
59225 #define V_PERR_RX2_FEC40G(x) ((x) << S_PERR_RX2_FEC40G)
59226 #define F_PERR_RX2_FEC40G    V_PERR_RX2_FEC40G(1U)
59229 #define V_PERR_RX3_FEC40G(x) ((x) << S_PERR_RX3_FEC40G)
59230 #define F_PERR_RX3_FEC40G    V_PERR_RX3_FEC40G(1U)
59233 #define V_PERR_RX_PCS10G_LPBK(x) ((x) << S_PERR_RX_PCS10G_LPBK)
59234 #define F_PERR_RX_PCS10G_LPBK    V_PERR_RX_PCS10G_LPBK(1U)
59237 #define V_PERR_RX_PCS10G(x) ((x) << S_PERR_RX_PCS10G)
59238 #define F_PERR_RX_PCS10G    V_PERR_RX_PCS10G(1U)
59240 #define S_PERR_RX_PCS1G    1
59241 #define V_PERR_RX_PCS1G(x) ((x) << S_PERR_RX_PCS1G)
59242 #define F_PERR_RX_PCS1G    V_PERR_RX_PCS1G(1U)
59245 #define V_PERR_TX_PCS1G(x) ((x) << S_PERR_TX_PCS1G)
59246 #define F_PERR_TX_PCS1G    V_PERR_TX_PCS1G(1U)
59252 #define S_MEMSEL_PERR    1
59254 #define V_MEMSEL_PERR(x) ((x) << S_MEMSEL_PERR)
59255 #define G_MEMSEL_PERR(x) (((x) >> S_MEMSEL_PERR) & M_MEMSEL_PERR)
59260 #define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
59261 #define F_HSSREFCLKVALIDA    V_HSSREFCLKVALIDA(1U)
59264 #define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
59265 #define F_HSSREFCLKVALIDB    V_HSSREFCLKVALIDB(1U)
59268 #define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
59269 #define F_HSSRESYNCA    V_HSSRESYNCA(1U)
59272 #define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
59273 #define F_HSSRESYNCB    V_HSSRESYNCB(1U)
59276 #define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
59277 #define F_HSSRECCALA    V_HSSRECCALA(1U)
59280 #define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
59281 #define F_HSSRECCALB    V_HSSRECCALB(1U)
59284 #define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
59285 #define F_HSSPLLBYPA    V_HSSPLLBYPA(1U)
59288 #define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
59289 #define F_HSSPLLBYPB    V_HSSPLLBYPB(1U)
59292 #define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
59293 #define F_HSSPDWNPLLA    V_HSSPDWNPLLA(1U)
59296 #define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
59297 #define F_HSSPDWNPLLB    V_HSSPDWNPLLB(1U)
59300 #define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
59301 #define F_HSSVCOSELA    V_HSSVCOSELA(1U)
59304 #define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
59305 #define F_HSSVCOSELB    V_HSSVCOSELB(1U)
59308 #define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
59309 #define F_HSSCALCOMP    V_HSSCALCOMP(1U)
59312 #define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
59313 #define F_HSSCALENAB    V_HSSCALENAB(1U)
59319 #define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
59320 #define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
59323 #define V_RXAQUIET(x) ((x) << S_RXAQUIET)
59324 #define F_RXAQUIET    V_RXAQUIET(1U)
59327 #define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
59328 #define F_RXAREFRESH    V_RXAREFRESH(1U)
59332 #define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
59333 #define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
59336 #define V_RXBQUIET(x) ((x) << S_RXBQUIET)
59337 #define F_RXBQUIET    V_RXBQUIET(1U)
59340 #define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
59341 #define F_RXBREFRESH    V_RXBREFRESH(1U)
59345 #define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
59346 #define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
59349 #define V_RXCQUIET(x) ((x) << S_RXCQUIET)
59350 #define F_RXCQUIET    V_RXCQUIET(1U)
59353 #define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
59354 #define F_RXCREFRESH    V_RXCREFRESH(1U)
59358 #define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
59359 #define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
59362 #define V_RXDQUIET(x) ((x) << S_RXDQUIET)
59363 #define F_RXDQUIET    V_RXDQUIET(1U)
59366 #define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
59367 #define F_RXDREFRESH    V_RXDREFRESH(1U)
59371 #define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
59372 #define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
59375 #define V_TXAQUIET(x) ((x) << S_TXAQUIET)
59376 #define F_TXAQUIET    V_TXAQUIET(1U)
59379 #define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
59380 #define F_TXAREFRESH    V_TXAREFRESH(1U)
59384 #define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
59385 #define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
59388 #define V_TXBQUIET(x) ((x) << S_TXBQUIET)
59389 #define F_TXBQUIET    V_TXBQUIET(1U)
59392 #define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
59393 #define F_TXBREFRESH    V_TXBREFRESH(1U)
59397 #define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
59398 #define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
59401 #define V_TXCQUIET(x) ((x) << S_TXCQUIET)
59402 #define F_TXCQUIET    V_TXCQUIET(1U)
59405 #define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
59406 #define F_TXCREFRESH    V_TXCREFRESH(1U)
59410 #define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
59411 #define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
59413 #define S_TXDQUIET    1
59414 #define V_TXDQUIET(x) ((x) << S_TXDQUIET)
59415 #define F_TXDQUIET    V_TXDQUIET(1U)
59418 #define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
59419 #define F_TXDREFRESH    V_TXDREFRESH(1U)
59424 #define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
59425 #define F_RXAASSTCLK    V_RXAASSTCLK(1U)
59428 #define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
59429 #define F_T5RXAPRBSRST    V_T5RXAPRBSRST(1U)
59432 #define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
59433 #define F_RXBASSTCLK    V_RXBASSTCLK(1U)
59436 #define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
59437 #define F_T5RXBPRBSRST    V_T5RXBPRBSRST(1U)
59440 #define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
59441 #define F_RXCASSTCLK    V_RXCASSTCLK(1U)
59444 #define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
59445 #define F_T5RXCPRBSRST    V_T5RXCPRBSRST(1U)
59448 #define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
59449 #define F_RXDASSTCLK    V_RXDASSTCLK(1U)
59452 #define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
59453 #define F_T5RXDPRBSRST    V_T5RXDPRBSRST(1U)
59459 #define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
59460 #define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
59464 #define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
59465 #define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
59469 #define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
59470 #define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
59474 #define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
59475 #define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
59479 #define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
59480 #define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
59484 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
59485 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
59489 #define V_T6_HSSCALSSTN(x) ((x) << S_T6_HSSCALSSTN)
59490 #define G_T6_HSSCALSSTN(x) (((x) >> S_T6_HSSCALSSTN) & M_T6_HSSCALSSTN)
59494 #define V_T6_HSSCALSSTP(x) ((x) << S_T6_HSSCALSSTP)
59495 #define G_T6_HSSCALSSTP(x) (((x) >> S_T6_HSSCALSSTP) & M_T6_HSSCALSSTP)
59501 #define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
59502 #define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
59506 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
59507 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
59511 #define V_HSSREFDIVA(x) ((x) << S_HSSREFDIVA)
59512 #define G_HSSREFDIVA(x) (((x) >> S_HSSREFDIVA) & M_HSSREFDIVA)
59516 #define V_HSSREFDIVB(x) ((x) << S_HSSREFDIVB)
59517 #define G_HSSREFDIVB(x) (((x) >> S_HSSREFDIVB) & M_HSSREFDIVB)
59520 #define V_HSSPLLDIV2B(x) ((x) << S_HSSPLLDIV2B)
59521 #define F_HSSPLLDIV2B    V_HSSPLLDIV2B(1U)
59524 #define V_HSSPLLDIV2A(x) ((x) << S_HSSPLLDIV2A)
59525 #define F_HSSPLLDIV2A    V_HSSPLLDIV2A(1U)
59530 #define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
59531 #define F_HSSPLLLOCKB    V_HSSPLLLOCKB(1U)
59534 #define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
59535 #define F_HSSPLLLOCKA    V_HSSPLLLOCKA(1U)
59537 #define S_HSSPRTREADYB    1
59538 #define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
59539 #define F_HSSPRTREADYB    V_HSSPRTREADYB(1U)
59542 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
59543 #define F_HSSPRTREADYA    V_HSSPRTREADYA(1U)
59546 #define V_RXDERROFLOW(x) ((x) << S_RXDERROFLOW)
59547 #define F_RXDERROFLOW    V_RXDERROFLOW(1U)
59550 #define V_RXCERROFLOW(x) ((x) << S_RXCERROFLOW)
59551 #define F_RXCERROFLOW    V_RXCERROFLOW(1U)
59554 #define V_RXBERROFLOW(x) ((x) << S_RXBERROFLOW)
59555 #define F_RXBERROFLOW    V_RXBERROFLOW(1U)
59558 #define V_RXAERROFLOW(x) ((x) << S_RXAERROFLOW)
59559 #define F_RXAERROFLOW    V_RXAERROFLOW(1U)
59564 #define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
59565 #define F_RXAQUIET_STATUS    V_RXAQUIET_STATUS(1U)
59568 #define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
59569 #define F_RXAREFRESH_STATUS    V_RXAREFRESH_STATUS(1U)
59572 #define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
59573 #define F_RXBQUIET_STATUS    V_RXBQUIET_STATUS(1U)
59576 #define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
59577 #define F_RXBREFRESH_STATUS    V_RXBREFRESH_STATUS(1U)
59580 #define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
59581 #define F_RXCQUIET_STATUS    V_RXCQUIET_STATUS(1U)
59584 #define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
59585 #define F_RXCREFRESH_STATUS    V_RXCREFRESH_STATUS(1U)
59588 #define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
59589 #define F_RXDQUIET_STATUS    V_RXDQUIET_STATUS(1U)
59592 #define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
59593 #define F_RXDREFRESH_STATUS    V_RXDREFRESH_STATUS(1U)
59596 #define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
59597 #define F_TXAQUIET_STATUS    V_TXAQUIET_STATUS(1U)
59600 #define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
59601 #define F_TXAREFRESH_STATUS    V_TXAREFRESH_STATUS(1U)
59604 #define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
59605 #define F_TXBQUIET_STATUS    V_TXBQUIET_STATUS(1U)
59608 #define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
59609 #define F_TXBREFRESH_STATUS    V_TXBREFRESH_STATUS(1U)
59612 #define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
59613 #define F_TXCQUIET_STATUS    V_TXCQUIET_STATUS(1U)
59616 #define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
59617 #define F_TXCREFRESH_STATUS    V_TXCREFRESH_STATUS(1U)
59619 #define S_TXDQUIET_STATUS    1
59620 #define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
59621 #define F_TXDQUIET_STATUS    V_TXDQUIET_STATUS(1U)
59624 #define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
59625 #define F_TXDREFRESH_STATUS    V_TXDREFRESH_STATUS(1U)
59632 #define V_TOV(x) ((x) << S_TOV)
59633 #define G_TOV(x) (((x) >> S_TOV) & M_TOV)
59637 #define V_TSU(x) ((x) << S_TSU)
59638 #define G_TSU(x) (((x) >> S_TSU) & M_TSU)
59642 #define V_IPW(x) ((x) << S_IPW)
59643 #define G_IPW(x) (((x) >> S_IPW) & M_IPW)
59648 #define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
59649 #define F_RUNTCLEAR    V_RUNTCLEAR(1U)
59653 #define V_RUNT(x) ((x) << S_RUNT)
59654 #define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
59660 #define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
59661 #define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
59665 #define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
59666 #define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
59670 #define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
59671 #define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
59675 #define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
59676 #define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
59679 #define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
59680 #define F_PMA_RX_REFRESH    V_PMA_RX_REFRESH(1U)
59683 #define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
59684 #define F_PMA_RX_QUIET    V_PMA_RX_QUIET(1U)
59686 #define S_PMA_TX_REFRESH    1
59687 #define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
59688 #define F_PMA_TX_REFRESH    V_PMA_TX_REFRESH(1U)
59691 #define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
59692 #define F_PMA_TX_QUIET    V_PMA_TX_QUIET(1U)
59697 #define V_CGEN(x) ((x) << S_CGEN)
59698 #define F_CGEN    V_CGEN(1U)
59701 #define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
59702 #define F_SD7_CGEN    V_SD7_CGEN(1U)
59705 #define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
59706 #define F_SD6_CGEN    V_SD6_CGEN(1U)
59709 #define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
59710 #define F_SD5_CGEN    V_SD5_CGEN(1U)
59713 #define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
59714 #define F_SD4_CGEN    V_SD4_CGEN(1U)
59717 #define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
59718 #define F_SD3_CGEN    V_SD3_CGEN(1U)
59721 #define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
59722 #define F_SD2_CGEN    V_SD2_CGEN(1U)
59724 #define S_SD1_CGEN    1
59725 #define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
59726 #define F_SD1_CGEN    V_SD1_CGEN(1U)
59729 #define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
59730 #define F_SD0_CGEN    V_SD0_CGEN(1U)
59735 #define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
59736 #define F_MACSEG5_CGEN    V_MACSEG5_CGEN(1U)
59739 #define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
59740 #define F_PCSSEG5_CGEN    V_PCSSEG5_CGEN(1U)
59743 #define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
59744 #define F_MACSEG4_CGEN    V_MACSEG4_CGEN(1U)
59747 #define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
59748 #define F_PCSSEG4_CGEN    V_PCSSEG4_CGEN(1U)
59751 #define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
59752 #define F_MACSEG3_CGEN    V_MACSEG3_CGEN(1U)
59755 #define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
59756 #define F_PCSSEG3_CGEN    V_PCSSEG3_CGEN(1U)
59759 #define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
59760 #define F_MACSEG2_CGEN    V_MACSEG2_CGEN(1U)
59763 #define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
59764 #define F_PCSSEG2_CGEN    V_PCSSEG2_CGEN(1U)
59767 #define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
59768 #define F_MACSEG1_CGEN    V_MACSEG1_CGEN(1U)
59771 #define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
59772 #define F_PCSSEG1_CGEN    V_PCSSEG1_CGEN(1U)
59774 #define S_MACSEG0_CGEN    1
59775 #define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
59776 #define F_MACSEG0_CGEN    V_MACSEG0_CGEN(1U)
59779 #define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
59780 #define F_PCSSEG0_CGEN    V_PCSSEG0_CGEN(1U)
59786 #define V_TS_ID(x) ((x) << S_TS_ID)
59787 #define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
59795 #define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
59796 #define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
59798 #define S_TICK_START    1
59799 #define V_TICK_START(x) ((x) << S_TICK_START)
59800 #define F_TICK_START    V_TICK_START(1U)
59803 #define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
59804 #define F_EEE_ENABLE    V_EEE_ENABLE(1U)
59810 #define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
59811 #define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
59815 #define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
59816 #define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
59819 #define V_HSS_CTL(x) ((x) << S_HSS_CTL)
59820 #define F_HSS_CTL    V_HSS_CTL(1U)
59823 #define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
59824 #define F_LPI_ACTIVE    V_LPI_ACTIVE(1U)
59827 #define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
59828 #define F_LPI_TXHOLD    V_LPI_TXHOLD(1U)
59830 #define S_LPI_REQ    1
59831 #define V_LPI_REQ(x) ((x) << S_LPI_REQ)
59832 #define F_LPI_REQ    V_LPI_REQ(1U)
59835 #define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
59836 #define F_EEE_TX_RESET    V_EEE_TX_RESET(1U)
59840 #define S_LPI_IND    1
59841 #define V_LPI_IND(x) ((x) << S_LPI_IND)
59842 #define F_LPI_IND    V_LPI_IND(1U)
59845 #define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
59846 #define F_EEE_RX_RESET    V_EEE_RX_RESET(1U)
59862 #define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
59863 #define F_WAKE_CNT_CLR    V_WAKE_CNT_CLR(1U)
59867 #define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
59868 #define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
59882 #define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
59883 #define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
59891 #define V_Y(x) ((x) << S_Y)
59892 #define G_Y(x) (((x) >> S_Y) & M_Y)
59896 #define V_X(x) ((x) << S_X)
59897 #define G_X(x) (((x) >> S_X) & M_X)
59903 #define V_Y_TICK(x) ((x) << S_Y_TICK)
59904 #define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
59908 #define V_X_TICK(x) ((x) << S_X_TICK)
59909 #define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
59917 #define V_B(x) ((x) << S_B)
59918 #define G_B(x) (((x) >> S_B) & M_B)
59923 #define V_A(x) ((x) << S_A)
59924 #define G_A(x) (((x) >> S_A) & M_A)
59930 #define V_FRZ(x) ((x) << S_FRZ)
59931 #define F_FRZ    V_FRZ(1U)
59934 #define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
59935 #define F_OFFSER_ADJUST_SIGN    V_OFFSER_ADJUST_SIGN(1U)
59938 #define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
59939 #define F_ADD_OFFSET    V_ADD_OFFSET(1U)
59943 #define V_CYCLE1(x) ((x) << S_CYCLE1)
59944 #define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
59948 #define V_Q(x) ((x) << S_Q)
59949 #define G_Q(x) (((x) >> S_Q) & M_Q)
59952 #define V_ALARM_EN(x) ((x) << S_ALARM_EN)
59953 #define F_ALARM_EN    V_ALARM_EN(1U)
59956 #define V_ALARM_START(x) ((x) << S_ALARM_START)
59957 #define F_ALARM_START    V_ALARM_START(1U)
59960 #define V_PPS_EN(x) ((x) << S_PPS_EN)
59961 #define F_PPS_EN    V_PPS_EN(1U)
59969 #define V_ALARM_DONE(x) ((x) << S_ALARM_DONE)
59970 #define F_ALARM_DONE    V_ALARM_DONE(1U)
59976 #define V_CUSTREV(x) ((x) << S_CUSTREV)
59977 #define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
59981 #define V_VER(x) ((x) << S_VER)
59982 #define G_VER(x) (((x) >> S_VER) & M_VER)
59986 #define V_MTIP_REV(x) ((x) << S_MTIP_REV)
59987 #define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
59993 #define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
59994 #define F_TX_FLUSH_ENABLE    V_TX_FLUSH_ENABLE(1U)
59997 #define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
59998 #define F_RX_SFD_ANY    V_RX_SFD_ANY(1U)
60001 #define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
60002 #define F_PAUSE_PFC_COMP    V_PAUSE_PFC_COMP(1U)
60005 #define V_PFC_MODE(x) ((x) << S_PFC_MODE)
60006 #define F_PFC_MODE    V_PFC_MODE(1U)
60009 #define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
60010 #define F_RS_COL_CNT_EXT    V_RS_COL_CNT_EXT(1U)
60013 #define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
60014 #define F_NO_LGTH_CHECK    V_NO_LGTH_CHECK(1U)
60017 #define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
60018 #define F_SEND_IDLE    V_SEND_IDLE(1U)
60021 #define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
60022 #define F_PHY_TXENA    V_PHY_TXENA(1U)
60025 #define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
60026 #define F_RX_ERR_DISC    V_RX_ERR_DISC(1U)
60029 #define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
60030 #define F_CMD_FRAME_ENA    V_CMD_FRAME_ENA(1U)
60033 #define V_SW_RESET(x) ((x) << S_SW_RESET)
60034 #define F_SW_RESET    V_SW_RESET(1U)
60037 #define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
60038 #define F_TX_PAD_EN    V_TX_PAD_EN(1U)
60041 #define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
60042 #define F_PHY_LOOPBACK_EN    V_PHY_LOOPBACK_EN(1U)
60045 #define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
60046 #define F_TX_ADDR_INS    V_TX_ADDR_INS(1U)
60049 #define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
60050 #define F_PAUSE_IGNORE    V_PAUSE_IGNORE(1U)
60053 #define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
60054 #define F_PAUSE_FWD    V_PAUSE_FWD(1U)
60057 #define V_CRC_FWD(x) ((x) << S_CRC_FWD)
60058 #define F_CRC_FWD    V_CRC_FWD(1U)
60061 #define V_PAD_EN(x) ((x) << S_PAD_EN)
60062 #define F_PAD_EN    V_PAD_EN(1U)
60065 #define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
60066 #define F_PROMIS_EN    V_PROMIS_EN(1U)
60069 #define V_WAN_MODE(x) ((x) << S_WAN_MODE)
60070 #define F_WAN_MODE    V_WAN_MODE(1U)
60072 #define S_RX_ENA    1
60073 #define V_RX_ENA(x) ((x) << S_RX_ENA)
60074 #define F_RX_ENA    V_RX_ENA(1U)
60077 #define V_TX_ENA(x) ((x) << S_TX_ENA)
60078 #define F_TX_ENA    V_TX_ENA(1U)
60085 #define V_MACADDRHI(x) ((x) << S_MACADDRHI)
60086 #define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
60092 #define V_LEN(x) ((x) << S_LEN)
60093 #define G_LEN(x) (((x) >> S_LEN) & M_LEN)
60099 #define V_AVAIL(x) ((x) << S_AVAIL)
60100 #define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
60104 #define V_EMPTY(x) ((x) << S_EMPTY)
60105 #define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
60112 #define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
60113 #define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
60117 #define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
60118 #define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
60124 #define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
60125 #define F_ENABLE_MCAST_RX    V_ENABLE_MCAST_RX(1U)
60129 #define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
60130 #define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
60135 #define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
60136 #define F_TS_AVAIL    V_TS_AVAIL(1U)
60139 #define V_PHY_LOS(x) ((x) << S_PHY_LOS)
60140 #define F_PHY_LOS    V_PHY_LOS(1U)
60142 #define S_RX_REM_FAULT    1
60143 #define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
60144 #define F_RX_REM_FAULT    V_RX_REM_FAULT(1U)
60147 #define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
60148 #define F_RX_LOC_FAULT    V_RX_LOC_FAULT(1U)
60154 #define V_IPG(x) ((x) << S_IPG)
60155 #define G_IPG(x) (((x) >> S_IPG) & M_IPG)
60160 #define V_RXFIFORST(x) ((x) << S_RXFIFORST)
60161 #define F_RXFIFORST    V_RXFIFORST(1U)
60167 #define V_MACCRDRST(x) ((x) << S_MACCRDRST)
60168 #define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
60174 #define V_INITCREDIT(x) ((x) << S_INITCREDIT)
60175 #define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
60181 #define V_STATUS(x) ((x) << S_STATUS)
60182 #define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
60292 #define V_RESET(x) ((x) << S_RESET)
60293 #define F_RESET    V_RESET(1U)
60296 #define V_LOOPBACK(x) ((x) << S_LOOPBACK)
60297 #define F_LOOPBACK    V_LOOPBACK(1U)
60300 #define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
60301 #define F_SPPEDSEL1    V_SPPEDSEL1(1U)
60304 #define V_AN_EN(x) ((x) << S_AN_EN)
60305 #define F_AN_EN    V_AN_EN(1U)
60308 #define V_PWRDWN(x) ((x) << S_PWRDWN)
60309 #define F_PWRDWN    V_PWRDWN(1U)
60312 #define V_ISOLATE(x) ((x) << S_ISOLATE)
60313 #define F_ISOLATE    V_ISOLATE(1U)
60316 #define V_AN_RESTART(x) ((x) << S_AN_RESTART)
60317 #define F_AN_RESTART    V_AN_RESTART(1U)
60320 #define V_DPLX(x) ((x) << S_DPLX)
60321 #define F_DPLX    V_DPLX(1U)
60324 #define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
60325 #define F_COLLISIONTEST    V_COLLISIONTEST(1U)
60328 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
60329 #define F_SPEEDSEL0    V_SPEEDSEL0(1U)
60335 #define V_VER_1G10G(x) ((x) << S_VER_1G10G)
60336 #define G_VER_1G10G(x) (((x) >> S_VER_1G10G) & M_VER_1G10G)
60340 #define V_REV_1G10G(x) ((x) << S_REV_1G10G)
60341 #define G_REV_1G10G(x) (((x) >> S_REV_1G10G) & M_REV_1G10G)
60346 #define V_100BASET4(x) ((x) << S_100BASET4)
60347 #define F_100BASET4    V_100BASET4(1U)
60350 #define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
60351 #define F_100BASEXFULLDPLX    V_100BASEXFULLDPLX(1U)
60354 #define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
60355 #define F_100BASEXHALFDPLX    V_100BASEXHALFDPLX(1U)
60358 #define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
60359 #define F_10MBPSFULLDPLX    V_10MBPSFULLDPLX(1U)
60362 #define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
60363 #define F_10MBPSHALFDPLX    V_10MBPSHALFDPLX(1U)
60366 #define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
60367 #define F_100BASET2FULLDPLX    V_100BASET2FULLDPLX(1U)
60370 #define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
60371 #define F_100BASET2HALFDPLX    V_100BASET2HALFDPLX(1U)
60374 #define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
60375 #define F_EXTDSTATUS    V_EXTDSTATUS(1U)
60378 #define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
60379 #define F_SGMII_REM_FAULT    V_SGMII_REM_FAULT(1U)
60381 #define S_JABBERDETECT    1
60382 #define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
60383 #define F_JABBERDETECT    V_JABBERDETECT(1U)
60386 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
60387 #define F_EXTDCAPABILITY    V_EXTDCAPABILITY(1U)
60394 #define V_SHORT_DISCARD(x) ((x) << S_SHORT_DISCARD)
60395 #define F_SHORT_DISCARD    V_SHORT_DISCARD(1U)
60398 #define V_REG_LOWP_RXEMPTY(x) ((x) << S_REG_LOWP_RXEMPTY)
60399 #define F_REG_LOWP_RXEMPTY    V_REG_LOWP_RXEMPTY(1U)
60402 #define V_TX_LOWP_ENA(x) ((x) << S_TX_LOWP_ENA)
60403 #define F_TX_LOWP_ENA    V_TX_LOWP_ENA(1U)
60406 #define V_TX_FLUSH_EN(x) ((x) << S_TX_FLUSH_EN)
60407 #define F_TX_FLUSH_EN    V_TX_FLUSH_EN(1U)
60410 #define V_SFD_ANY(x) ((x) << S_SFD_ANY)
60411 #define F_SFD_ANY    V_SFD_ANY(1U)
60414 #define V_COL_CNT_EXT(x) ((x) << S_COL_CNT_EXT)
60415 #define F_COL_CNT_EXT    V_COL_CNT_EXT(1U)
60418 #define V_FORCE_SEND_IDLE(x) ((x) << S_FORCE_SEND_IDLE)
60419 #define F_FORCE_SEND_IDLE    V_FORCE_SEND_IDLE(1U)
60422 #define V_CNTL_FRM_ENA(x) ((x) << S_CNTL_FRM_ENA)
60423 #define F_CNTL_FRM_ENA    V_CNTL_FRM_ENA(1U)
60425 #define S_RX_ENAMAC    1
60426 #define V_RX_ENAMAC(x) ((x) << S_RX_ENAMAC)
60427 #define F_RX_ENAMAC    V_RX_ENAMAC(1U)
60430 #define V_TX_ENAMAC(x) ((x) << S_TX_ENAMAC)
60431 #define F_TX_ENAMAC    V_TX_ENAMAC(1U)
60438 #define V_RF2(x) ((x) << S_RF2)
60439 #define F_RF2    V_RF2(1U)
60442 #define V_RF1(x) ((x) << S_RF1)
60443 #define F_RF1    V_RF1(1U)
60446 #define V_PS2(x) ((x) << S_PS2)
60447 #define F_PS2    V_PS2(1U)
60450 #define V_PS1(x) ((x) << S_PS1)
60451 #define F_PS1    V_PS1(1U)
60454 #define V_HD(x) ((x) << S_HD)
60455 #define F_HD    V_HD(1U)
60458 #define V_FD(x) ((x) << S_FD)
60459 #define F_FD    V_FD(1U)
60465 #define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
60466 #define F_CULINKSTATUS    V_CULINKSTATUS(1U)
60469 #define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
60470 #define F_CUDPLXSTATUS    V_CUDPLXSTATUS(1U)
60474 #define V_CUSPEED(x) ((x) << S_CUSPEED)
60475 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
60481 #define V_SET_LEN(x) ((x) << S_SET_LEN)
60482 #define G_SET_LEN(x) (((x) >> S_SET_LEN) & M_SET_LEN)
60486 #define V_FRM_LEN_SET(x) ((x) << S_FRM_LEN_SET)
60487 #define G_FRM_LEN_SET(x) (((x) >> S_FRM_LEN_SET) & M_FRM_LEN_SET)
60491 #define S_PGRCVD    1
60492 #define V_PGRCVD(x) ((x) << S_PGRCVD)
60493 #define F_PGRCVD    V_PGRCVD(1U)
60496 #define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
60497 #define F_REALTIMEPGRCVD    V_REALTIMEPGRCVD(1U)
60504 #define V_RX1G10G_EMPTY(x) ((x) << S_RX1G10G_EMPTY)
60505 #define G_RX1G10G_EMPTY(x) (((x) >> S_RX1G10G_EMPTY) & M_RX1G10G_EMPTY)
60509 #define V_RX1G10G_AVAIL(x) ((x) << S_RX1G10G_AVAIL)
60510 #define G_RX1G10G_AVAIL(x) (((x) >> S_RX1G10G_AVAIL) & M_RX1G10G_AVAIL)
60517 #define V_TX1G10G_EMPTY(x) ((x) << S_TX1G10G_EMPTY)
60518 #define G_TX1G10G_EMPTY(x) (((x) >> S_TX1G10G_EMPTY) & M_TX1G10G_EMPTY)
60522 #define V_TX1G10G_AVAIL(x) ((x) << S_TX1G10G_AVAIL)
60523 #define G_TX1G10G_AVAIL(x) (((x) >> S_TX1G10G_AVAIL) & M_TX1G10G_AVAIL)
60529 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
60530 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
60534 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
60535 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
60543 #define V_CLK_DIVISOR(x) ((x) << S_CLK_DIVISOR)
60544 #define G_CLK_DIVISOR(x) (((x) >> S_CLK_DIVISOR) & M_CLK_DIVISOR)
60547 #define V_ENA_CLAUSE(x) ((x) << S_ENA_CLAUSE)
60548 #define F_ENA_CLAUSE    V_ENA_CLAUSE(1U)
60551 #define V_PREAMBLE_DISABLE(x) ((x) << S_PREAMBLE_DISABLE)
60552 #define F_PREAMBLE_DISABLE    V_PREAMBLE_DISABLE(1U)
60556 #define V_HOLD_TIME_SETTING(x) ((x) << S_HOLD_TIME_SETTING)
60557 #define G_HOLD_TIME_SETTING(x) (((x) >> S_HOLD_TIME_SETTING) & M_HOLD_TIME_SETTING)
60559 #define S_MDIO_READ_ERROR    1
60560 #define V_MDIO_READ_ERROR(x) ((x) << S_MDIO_READ_ERROR)
60561 #define F_MDIO_READ_ERROR    V_MDIO_READ_ERROR(1U)
60566 #define V_READ_MODE(x) ((x) << S_READ_MODE)
60567 #define F_READ_MODE    V_READ_MODE(1U)
60570 #define V_POST_INCR_READ(x) ((x) << S_POST_INCR_READ)
60571 #define F_POST_INCR_READ    V_POST_INCR_READ(1U)
60575 #define V_PORT_PHY_ADDR(x) ((x) << S_PORT_PHY_ADDR)
60576 #define G_PORT_PHY_ADDR(x) (((x) >> S_PORT_PHY_ADDR) & M_PORT_PHY_ADDR)
60580 #define V_DEVICE_REG_ADDR(x) ((x) << S_DEVICE_REG_ADDR)
60581 #define G_DEVICE_REG_ADDR(x) (((x) >> S_DEVICE_REG_ADDR) & M_DEVICE_REG_ADDR)
60587 #define V_MDIO_DATA(x) ((x) << S_MDIO_DATA)
60588 #define G_MDIO_DATA(x) (((x) >> S_MDIO_DATA) & M_MDIO_DATA)
60595 #define V_RX_LINT_FAULT(x) ((x) << S_RX_LINT_FAULT)
60596 #define F_RX_LINT_FAULT    V_RX_LINT_FAULT(1U)
60599 #define V_RX_EMPTY(x) ((x) << S_RX_EMPTY)
60600 #define F_RX_EMPTY    V_RX_EMPTY(1U)
60603 #define V_TX_EMPTY(x) ((x) << S_TX_EMPTY)
60604 #define F_TX_EMPTY    V_TX_EMPTY(1U)
60607 #define V_RX_LOWP(x) ((x) << S_RX_LOWP)
60608 #define F_RX_LOWP    V_RX_LOWP(1U)
60615 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
60616 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
60623 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
60624 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
60630 #define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
60631 #define F_SGMII_PCS_ENABLE    V_SGMII_PCS_ENABLE(1U)
60634 #define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
60635 #define F_SGMII_HDUPLEX    V_SGMII_HDUPLEX(1U)
60639 #define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
60640 #define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
60642 #define S_USE_SGMII_AN    1
60643 #define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
60644 #define F_USE_SGMII_AN    V_USE_SGMII_AN(1U)
60647 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
60648 #define F_SGMII_ENA    V_SGMII_ENA(1U)
60654 #define V_CL1_PAUSE_QUANTA(x) ((x) << S_CL1_PAUSE_QUANTA)
60655 #define G_CL1_PAUSE_QUANTA(x) (((x) >> S_CL1_PAUSE_QUANTA) & M_CL1_PAUSE_QUANTA)
60659 #define V_CL0_PAUSE_QUANTA(x) ((x) << S_CL0_PAUSE_QUANTA)
60660 #define G_CL0_PAUSE_QUANTA(x) (((x) >> S_CL0_PAUSE_QUANTA) & M_CL0_PAUSE_QUANTA)
60666 #define V_CL3_PAUSE_QUANTA(x) ((x) << S_CL3_PAUSE_QUANTA)
60667 #define G_CL3_PAUSE_QUANTA(x) (((x) >> S_CL3_PAUSE_QUANTA) & M_CL3_PAUSE_QUANTA)
60671 #define V_CL2_PAUSE_QUANTA(x) ((x) << S_CL2_PAUSE_QUANTA)
60672 #define G_CL2_PAUSE_QUANTA(x) (((x) >> S_CL2_PAUSE_QUANTA) & M_CL2_PAUSE_QUANTA)
60678 #define V_CL5_PAUSE_QUANTA(x) ((x) << S_CL5_PAUSE_QUANTA)
60679 #define G_CL5_PAUSE_QUANTA(x) (((x) >> S_CL5_PAUSE_QUANTA) & M_CL5_PAUSE_QUANTA)
60683 #define V_CL4_PAUSE_QUANTA(x) ((x) << S_CL4_PAUSE_QUANTA)
60684 #define G_CL4_PAUSE_QUANTA(x) (((x) >> S_CL4_PAUSE_QUANTA) & M_CL4_PAUSE_QUANTA)
60690 #define V_CL7_PAUSE_QUANTA(x) ((x) << S_CL7_PAUSE_QUANTA)
60691 #define G_CL7_PAUSE_QUANTA(x) (((x) >> S_CL7_PAUSE_QUANTA) & M_CL7_PAUSE_QUANTA)
60695 #define V_CL6_PAUSE_QUANTA(x) ((x) << S_CL6_PAUSE_QUANTA)
60696 #define G_CL6_PAUSE_QUANTA(x) (((x) >> S_CL6_PAUSE_QUANTA) & M_CL6_PAUSE_QUANTA)
60702 #define V_CL1_QUANTA_THRESH(x) ((x) << S_CL1_QUANTA_THRESH)
60703 #define G_CL1_QUANTA_THRESH(x) (((x) >> S_CL1_QUANTA_THRESH) & M_CL1_QUANTA_THRESH)
60707 #define V_CL0_QUANTA_THRESH(x) ((x) << S_CL0_QUANTA_THRESH)
60708 #define G_CL0_QUANTA_THRESH(x) (((x) >> S_CL0_QUANTA_THRESH) & M_CL0_QUANTA_THRESH)
60714 #define V_CL3_QUANTA_THRESH(x) ((x) << S_CL3_QUANTA_THRESH)
60715 #define G_CL3_QUANTA_THRESH(x) (((x) >> S_CL3_QUANTA_THRESH) & M_CL3_QUANTA_THRESH)
60719 #define V_CL2_QUANTA_THRESH(x) ((x) << S_CL2_QUANTA_THRESH)
60720 #define G_CL2_QUANTA_THRESH(x) (((x) >> S_CL2_QUANTA_THRESH) & M_CL2_QUANTA_THRESH)
60726 #define V_CL5_QUANTA_THRESH(x) ((x) << S_CL5_QUANTA_THRESH)
60727 #define G_CL5_QUANTA_THRESH(x) (((x) >> S_CL5_QUANTA_THRESH) & M_CL5_QUANTA_THRESH)
60731 #define V_CL4_QUANTA_THRESH(x) ((x) << S_CL4_QUANTA_THRESH)
60732 #define G_CL4_QUANTA_THRESH(x) (((x) >> S_CL4_QUANTA_THRESH) & M_CL4_QUANTA_THRESH)
60738 #define V_CL7_QUANTA_THRESH(x) ((x) << S_CL7_QUANTA_THRESH)
60739 #define G_CL7_QUANTA_THRESH(x) (((x) >> S_CL7_QUANTA_THRESH) & M_CL7_QUANTA_THRESH)
60743 #define V_CL6_QUANTA_THRESH(x) ((x) << S_CL6_QUANTA_THRESH)
60744 #define G_CL6_QUANTA_THRESH(x) (((x) >> S_CL6_QUANTA_THRESH) & M_CL6_QUANTA_THRESH)
60750 #define V_STATUS_BIT(x) ((x) << S_STATUS_BIT)
60751 #define G_STATUS_BIT(x) (((x) >> S_STATUS_BIT) & M_STATUS_BIT)
60757 #define V_CLEAR(x) ((x) << S_CLEAR)
60758 #define F_CLEAR    V_CLEAR(1U)
60760 #define S_CLEAR_ON_READ    1
60761 #define V_CLEAR_ON_READ(x) ((x) << S_CLEAR_ON_READ)
60762 #define F_CLEAR_ON_READ    V_CLEAR_ON_READ(1U)
60765 #define V_SATURATE(x) ((x) << S_SATURATE)
60766 #define F_SATURATE    V_SATURATE(1U)
60869 #define V_MII_ENA_10(x) ((x) << S_MII_ENA_10)
60870 #define F_MII_ENA_10    V_MII_ENA_10(1U)
60874 #define V_IF_MODE(x) ((x) << S_IF_MODE)
60875 #define G_IF_MODE(x) (((x) >> S_IF_MODE) & M_IF_MODE)
60881 #define V_IF_STATUS_MODE(x) ((x) << S_IF_STATUS_MODE)
60882 #define G_IF_STATUS_MODE(x) (((x) >> S_IF_STATUS_MODE) & M_IF_STATUS_MODE)
60920 #define V_ACTIVE(x) ((x) << S_ACTIVE)
60921 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
60926 #define V_SPEED_SEL(x) ((x) << S_SPEED_SEL)
60927 #define F_SPEED_SEL    V_SPEED_SEL(1U)
60930 #define V_PWR_DWN(x) ((x) << S_PWR_DWN)
60931 #define F_PWR_DWN    V_PWR_DWN(1U)
60934 #define V_DUPLEX_MODE(x) ((x) << S_DUPLEX_MODE)
60935 #define F_DUPLEX_MODE    V_DUPLEX_MODE(1U)
60938 #define V_COLLISION_TEST(x) ((x) << S_COLLISION_TEST)
60939 #define F_COLLISION_TEST    V_COLLISION_TEST(1U)
60942 #define V_T6_SPEED_SEL1(x) ((x) << S_T6_SPEED_SEL1)
60943 #define F_T6_SPEED_SEL1    V_T6_SPEED_SEL1(1U)
60949 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
60950 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
60955 #define V_T6_REM_FAULT(x) ((x) << S_T6_REM_FAULT)
60956 #define F_T6_REM_FAULT    V_T6_REM_FAULT(1U)
60962 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
60963 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
60973 #define V_NEXT_PAGE_ABLE(x) ((x) << S_NEXT_PAGE_ABLE)
60974 #define F_NEXT_PAGE_ABLE    V_NEXT_PAGE_ABLE(1U)
60976 #define S_PAGE_RECEIVE    1
60977 #define V_PAGE_RECEIVE(x) ((x) << S_PAGE_RECEIVE)
60978 #define F_PAGE_RECEIVE    V_PAGE_RECEIVE(1U)
60984 #define V_NP_TX(x) ((x) << S_NP_TX)
60985 #define G_NP_TX(x) (((x) >> S_NP_TX) & M_NP_TX)
60991 #define V_COL_CNT(x) ((x) << S_COL_CNT)
60992 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
60998 #define V_LP_NP_RX(x) ((x) << S_LP_NP_RX)
60999 #define G_LP_NP_RX(x) (((x) >> S_LP_NP_RX) & M_LP_NP_RX)
61005 #define V_EXTENDED_STATUS(x) ((x) << S_EXTENDED_STATUS)
61006 #define G_EXTENDED_STATUS(x) (((x) >> S_EXTENDED_STATUS) & M_EXTENDED_STATUS)
61010 #define S_VL_INTVL    1
61011 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
61012 #define F_VL_INTVL    V_VL_INTVL(1U)
61018 #define V_SCRATCH(x) ((x) << S_SCRATCH)
61019 #define G_SCRATCH(x) (((x) >> S_SCRATCH) & M_SCRATCH)
61025 #define V_SGMII_VER(x) ((x) << S_SGMII_VER)
61026 #define G_SGMII_VER(x) (((x) >> S_SGMII_VER) & M_SGMII_VER)
61030 #define V_SGMII_REV(x) ((x) << S_SGMII_REV)
61031 #define G_SGMII_REV(x) (((x) >> S_SGMII_REV) & M_SGMII_REV)
61037 #define V_LINK_TIMER_LO(x) ((x) << S_LINK_TIMER_LO)
61038 #define G_LINK_TIMER_LO(x) (((x) >> S_LINK_TIMER_LO) & M_LINK_TIMER_LO)
61044 #define V_LINK_TIMER_HI(x) ((x) << S_LINK_TIMER_HI)
61045 #define G_LINK_TIMER_HI(x) (((x) >> S_LINK_TIMER_HI) & M_LINK_TIMER_HI)
61050 #define V_SGMII_DUPLEX(x) ((x) << S_SGMII_DUPLEX)
61051 #define F_SGMII_DUPLEX    V_SGMII_DUPLEX(1U)
61057 #define V_T6_DECODE_ERROR(x) ((x) << S_T6_DECODE_ERROR)
61058 #define G_T6_DECODE_ERROR(x) (((x) >> S_T6_DECODE_ERROR) & M_T6_DECODE_ERROR)
61063 #define V_LOW_POWER(x) ((x) << S_LOW_POWER)
61064 #define F_LOW_POWER    V_LOW_POWER(1U)
61068 #define V_SPEED_SEL2(x) ((x) << S_SPEED_SEL2)
61069 #define G_SPEED_SEL2(x) (((x) >> S_SPEED_SEL2) & M_SPEED_SEL2)
61074 #define V_TX_LPI(x) ((x) << S_TX_LPI)
61075 #define F_TX_LPI    V_TX_LPI(1U)
61078 #define V_RX_LPI(x) ((x) << S_RX_LPI)
61079 #define F_RX_LPI    V_RX_LPI(1U)
61082 #define V_TX_LPI_ACTIVE(x) ((x) << S_TX_LPI_ACTIVE)
61083 #define F_TX_LPI_ACTIVE    V_TX_LPI_ACTIVE(1U)
61086 #define V_RX_LPI_ACTIVE(x) ((x) << S_RX_LPI_ACTIVE)
61087 #define F_RX_LPI_ACTIVE    V_RX_LPI_ACTIVE(1U)
61090 #define V_FAULT(x) ((x) << S_FAULT)
61091 #define F_FAULT    V_FAULT(1U)
61094 #define V_PCS_RX_LINK_STAT(x) ((x) << S_PCS_RX_LINK_STAT)
61095 #define F_PCS_RX_LINK_STAT    V_PCS_RX_LINK_STAT(1U)
61097 #define S_LOW_POWER_ABILITY    1
61098 #define V_LOW_POWER_ABILITY(x) ((x) << S_LOW_POWER_ABILITY)
61099 #define F_LOW_POWER_ABILITY    V_LOW_POWER_ABILITY(1U)
61106 #define V_10G_CAPABLE(x) ((x) << S_10G_CAPABLE)
61107 #define F_10G_CAPABLE    V_10G_CAPABLE(1U)
61112 #define V_AUTO_NEGOTIATION_PRESENT(x) ((x) << S_AUTO_NEGOTIATION_PRESENT)
61113 #define F_AUTO_NEGOTIATION_PRESENT    V_AUTO_NEGOTIATION_PRESENT(1U)
61116 #define V_DTE_XS_PRESENT(x) ((x) << S_DTE_XS_PRESENT)
61117 #define F_DTE_XS_PRESENT    V_DTE_XS_PRESENT(1U)
61120 #define V_PHY_XS_PRESENT(x) ((x) << S_PHY_XS_PRESENT)
61121 #define F_PHY_XS_PRESENT    V_PHY_XS_PRESENT(1U)
61124 #define V_PCS_PRESENT(x) ((x) << S_PCS_PRESENT)
61125 #define F_PCS_PRESENT    V_PCS_PRESENT(1U)
61128 #define V_WIS_PRESENT(x) ((x) << S_WIS_PRESENT)
61129 #define F_WIS_PRESENT    V_WIS_PRESENT(1U)
61131 #define S_PMD_PMA_PRESENT    1
61132 #define V_PMD_PMA_PRESENT(x) ((x) << S_PMD_PMA_PRESENT)
61133 #define F_PMD_PMA_PRESENT    V_PMD_PMA_PRESENT(1U)
61136 #define V_CLAUSE_22_REG_PRESENT(x) ((x) << S_CLAUSE_22_REG_PRESENT)
61137 #define F_CLAUSE_22_REG_PRESENT    V_CLAUSE_22_REG_PRESENT(1U)
61144 #define V_PCS_TYPE_SELECTION(x) ((x) << S_PCS_TYPE_SELECTION)
61145 #define G_PCS_TYPE_SELECTION(x) (((x) >> S_PCS_TYPE_SELECTION) & M_PCS_TYPE_SELECTION)
61151 #define V_DEVICE_PRESENT(x) ((x) << S_DEVICE_PRESENT)
61152 #define G_DEVICE_PRESENT(x) (((x) >> S_DEVICE_PRESENT) & M_DEVICE_PRESENT)
61155 #define V_TRANSMIT_FAULT(x) ((x) << S_TRANSMIT_FAULT)
61156 #define F_TRANSMIT_FAULT    V_TRANSMIT_FAULT(1U)
61159 #define V_RECEIVE_FAULT(x) ((x) << S_RECEIVE_FAULT)
61160 #define F_RECEIVE_FAULT    V_RECEIVE_FAULT(1U)
61163 #define V_10GBASE_W_CAPABLE(x) ((x) << S_10GBASE_W_CAPABLE)
61164 #define F_10GBASE_W_CAPABLE    V_10GBASE_W_CAPABLE(1U)
61166 #define S_10GBASE_X_CAPABLE    1
61167 #define V_10GBASE_X_CAPABLE(x) ((x) << S_10GBASE_X_CAPABLE)
61168 #define F_10GBASE_X_CAPABLE    V_10GBASE_X_CAPABLE(1U)
61171 #define V_10GBASE_R_CAPABLE(x) ((x) << S_10GBASE_R_CAPABLE)
61172 #define F_10GBASE_R_CAPABLE    V_10GBASE_R_CAPABLE(1U)
61178 #define V_PCS_PACKAGE_IDENTIFIER_LO(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_LO)
61179 #define G_PCS_PACKAGE_IDENTIFIER_LO(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_LO) & M_PCS_PACKAGE_IDENTIFIER_LO)
61185 #define V_PCS_PACKAGE_IDENTIFIER_HI(x) ((x) << S_PCS_PACKAGE_IDENTIFIER_HI)
61186 #define G_PCS_PACKAGE_IDENTIFIER_HI(x) (((x) >> S_PCS_PACKAGE_IDENTIFIER_HI) & M_PCS_PACKAGE_IDENTIFIER_HI)
61191 #define V_10GBASE_R_RX_LINK_STATUS(x) ((x) << S_10GBASE_R_RX_LINK_STATUS)
61192 #define F_10GBASE_R_RX_LINK_STATUS    V_10GBASE_R_RX_LINK_STATUS(1U)
61195 #define V_PRBS9_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS9_PTTRN_TSTNG_ABILITY)
61196 #define F_PRBS9_PTTRN_TSTNG_ABILITY    V_PRBS9_PTTRN_TSTNG_ABILITY(1U)
61199 #define V_PRBS31_PTTRN_TSTNG_ABILITY(x) ((x) << S_PRBS31_PTTRN_TSTNG_ABILITY)
61200 #define F_PRBS31_PTTRN_TSTNG_ABILITY    V_PRBS31_PTTRN_TSTNG_ABILITY(1U)
61202 #define S_10GBASE_R_PCS_HIGH_BER    1
61203 #define V_10GBASE_R_PCS_HIGH_BER(x) ((x) << S_10GBASE_R_PCS_HIGH_BER)
61204 #define F_10GBASE_R_PCS_HIGH_BER    V_10GBASE_R_PCS_HIGH_BER(1U)
61207 #define V_10GBASE_R_PCS_BLOCK_LOCK(x) ((x) << S_10GBASE_R_PCS_BLOCK_LOCK)
61208 #define F_10GBASE_R_PCS_BLOCK_LOCK    V_10GBASE_R_PCS_BLOCK_LOCK(1U)
61213 #define V_LATCHED_BLOCK_LOCK(x) ((x) << S_LATCHED_BLOCK_LOCK)
61214 #define F_LATCHED_BLOCK_LOCK    V_LATCHED_BLOCK_LOCK(1U)
61217 #define V_LATCHED_HIGH_BER(x) ((x) << S_LATCHED_HIGH_BER)
61218 #define F_LATCHED_HIGH_BER    V_LATCHED_HIGH_BER(1U)
61222 #define V_BERBER_COUNTER(x) ((x) << S_BERBER_COUNTER)
61223 #define G_BERBER_COUNTER(x) (((x) >> S_BERBER_COUNTER) & M_BERBER_COUNTER)
61229 #define V_TEST_PATTERN_SEED_A0(x) ((x) << S_TEST_PATTERN_SEED_A0)
61230 #define G_TEST_PATTERN_SEED_A0(x) (((x) >> S_TEST_PATTERN_SEED_A0) & M_TEST_PATTERN_SEED_A0)
61236 #define V_TEST_PATTERN_SEED_A1(x) ((x) << S_TEST_PATTERN_SEED_A1)
61237 #define G_TEST_PATTERN_SEED_A1(x) (((x) >> S_TEST_PATTERN_SEED_A1) & M_TEST_PATTERN_SEED_A1)
61243 #define V_TEST_PATTERN_SEED_A2(x) ((x) << S_TEST_PATTERN_SEED_A2)
61244 #define G_TEST_PATTERN_SEED_A2(x) (((x) >> S_TEST_PATTERN_SEED_A2) & M_TEST_PATTERN_SEED_A2)
61250 #define V_TEST_PATTERN_SEED_A3(x) ((x) << S_TEST_PATTERN_SEED_A3)
61251 #define G_TEST_PATTERN_SEED_A3(x) (((x) >> S_TEST_PATTERN_SEED_A3) & M_TEST_PATTERN_SEED_A3)
61257 #define V_TEST_PATTERN_SEED_B0(x) ((x) << S_TEST_PATTERN_SEED_B0)
61258 #define G_TEST_PATTERN_SEED_B0(x) (((x) >> S_TEST_PATTERN_SEED_B0) & M_TEST_PATTERN_SEED_B0)
61264 #define V_TEST_PATTERN_SEED_B1(x) ((x) << S_TEST_PATTERN_SEED_B1)
61265 #define G_TEST_PATTERN_SEED_B1(x) (((x) >> S_TEST_PATTERN_SEED_B1) & M_TEST_PATTERN_SEED_B1)
61271 #define V_TEST_PATTERN_SEED_B2(x) ((x) << S_TEST_PATTERN_SEED_B2)
61272 #define G_TEST_PATTERN_SEED_B2(x) (((x) >> S_TEST_PATTERN_SEED_B2) & M_TEST_PATTERN_SEED_B2)
61278 #define V_TEST_PATTERN_SEED_B3(x) ((x) << S_TEST_PATTERN_SEED_B3)
61279 #define G_TEST_PATTERN_SEED_B3(x) (((x) >> S_TEST_PATTERN_SEED_B3) & M_TEST_PATTERN_SEED_B3)
61284 #define V_PRBS9_TX_TST_PTTRN_EN(x) ((x) << S_PRBS9_TX_TST_PTTRN_EN)
61285 #define F_PRBS9_TX_TST_PTTRN_EN    V_PRBS9_TX_TST_PTTRN_EN(1U)
61288 #define V_PRBS31_RX_TST_PTTRN_EN(x) ((x) << S_PRBS31_RX_TST_PTTRN_EN)
61289 #define F_PRBS31_RX_TST_PTTRN_EN    V_PRBS31_RX_TST_PTTRN_EN(1U)
61292 #define V_PRBS31_TX_TST_PTTRN_EN(x) ((x) << S_PRBS31_TX_TST_PTTRN_EN)
61293 #define F_PRBS31_TX_TST_PTTRN_EN    V_PRBS31_TX_TST_PTTRN_EN(1U)
61296 #define V_TX_TEST_PATTERN_EN(x) ((x) << S_TX_TEST_PATTERN_EN)
61297 #define F_TX_TEST_PATTERN_EN    V_TX_TEST_PATTERN_EN(1U)
61300 #define V_RX_TEST_PATTERN_EN(x) ((x) << S_RX_TEST_PATTERN_EN)
61301 #define F_RX_TEST_PATTERN_EN    V_RX_TEST_PATTERN_EN(1U)
61303 #define S_TEST_PATTERN_SELECT    1
61304 #define V_TEST_PATTERN_SELECT(x) ((x) << S_TEST_PATTERN_SELECT)
61305 #define F_TEST_PATTERN_SELECT    V_TEST_PATTERN_SELECT(1U)
61308 #define V_DATA_PATTERN_SELECT(x) ((x) << S_DATA_PATTERN_SELECT)
61309 #define F_DATA_PATTERN_SELECT    V_DATA_PATTERN_SELECT(1U)
61315 #define V_TEST_PATTERN_ERR_CNTR(x) ((x) << S_TEST_PATTERN_ERR_CNTR)
61316 #define G_TEST_PATTERN_ERR_CNTR(x) (((x) >> S_TEST_PATTERN_ERR_CNTR) & M_TEST_PATTERN_ERR_CNTR)
61320 #define S_TRANSMIT_FIFO_FAULT    1
61321 #define V_TRANSMIT_FIFO_FAULT(x) ((x) << S_TRANSMIT_FIFO_FAULT)
61322 #define F_TRANSMIT_FIFO_FAULT    V_TRANSMIT_FIFO_FAULT(1U)
61325 #define V_RECEIVE_FIFO_FAULT(x) ((x) << S_RECEIVE_FIFO_FAULT)
61326 #define F_RECEIVE_FIFO_FAULT    V_RECEIVE_FIFO_FAULT(1U)
61331 #define V_SPEED_SELECTION(x) ((x) << S_SPEED_SELECTION)
61332 #define F_SPEED_SELECTION    V_SPEED_SELECTION(1U)
61335 #define V_SPEED_SELECTION1(x) ((x) << S_SPEED_SELECTION1)
61336 #define F_SPEED_SELECTION1    V_SPEED_SELECTION1(1U)
61340 #define V_SPEED_SELECTION2(x) ((x) << S_SPEED_SELECTION2)
61341 #define G_SPEED_SELECTION2(x) (((x) >> S_SPEED_SELECTION2) & M_SPEED_SELECTION2)
61346 #define V_RECEIVE_LINK_STAT(x) ((x) << S_RECEIVE_LINK_STAT)
61347 #define F_RECEIVE_LINK_STAT    V_RECEIVE_LINK_STAT(1U)
61354 #define V_T6_DEVICE_ID1(x) ((x) << S_T6_DEVICE_ID1)
61355 #define G_T6_DEVICE_ID1(x) (((x) >> S_T6_DEVICE_ID1) & M_T6_DEVICE_ID1)
61360 #define V_100G_CAPABLE(x) ((x) << S_100G_CAPABLE)
61361 #define F_100G_CAPABLE    V_100G_CAPABLE(1U)
61364 #define V_40G_CAPABLE(x) ((x) << S_40G_CAPABLE)
61365 #define F_40G_CAPABLE    V_40G_CAPABLE(1U)
61367 #define S_10PASS_TS_2BASE_TL_CAPABLE    1
61368 #define V_10PASS_TS_2BASE_TL_CAPABLE(x) ((x) << S_10PASS_TS_2BASE_TL_CAPABLE)
61369 #define F_10PASS_TS_2BASE_TL_CAPABLE    V_10PASS_TS_2BASE_TL_CAPABLE(1U)
61374 #define V_CLAUSE_22_REG(x) ((x) << S_CLAUSE_22_REG)
61375 #define F_CLAUSE_22_REG    V_CLAUSE_22_REG(1U)
61380 #define V_VENDOR_SPECIFIC_DEVICE(x) ((x) << S_VENDOR_SPECIFIC_DEVICE)
61381 #define F_VENDOR_SPECIFIC_DEVICE    V_VENDOR_SPECIFIC_DEVICE(1U)
61384 #define V_VENDOR_SPECIFIC_DEVICE1(x) ((x) << S_VENDOR_SPECIFIC_DEVICE1)
61385 #define F_VENDOR_SPECIFIC_DEVICE1    V_VENDOR_SPECIFIC_DEVICE1(1U)
61388 #define V_CLAUSE_22_EXT(x) ((x) << S_CLAUSE_22_EXT)
61389 #define F_CLAUSE_22_EXT    V_CLAUSE_22_EXT(1U)
61395 #define V_PCS_TYPE_SEL(x) ((x) << S_PCS_TYPE_SEL)
61396 #define G_PCS_TYPE_SEL(x) (((x) >> S_PCS_TYPE_SEL) & M_PCS_TYPE_SEL)
61401 #define V_100GBASE_R_CAPABLE(x) ((x) << S_100GBASE_R_CAPABLE)
61402 #define F_100GBASE_R_CAPABLE    V_100GBASE_R_CAPABLE(1U)
61405 #define V_40GBASE_R_CAPABLE(x) ((x) << S_40GBASE_R_CAPABLE)
61406 #define F_40GBASE_R_CAPABLE    V_40GBASE_R_CAPABLE(1U)
61409 #define V_10GBASE_T_CAPABLE(x) ((x) << S_10GBASE_T_CAPABLE)
61410 #define F_10GBASE_T_CAPABLE    V_10GBASE_T_CAPABLE(1U)
61417 #define V_T6_RX_LINK_STATUS(x) ((x) << S_T6_RX_LINK_STATUS)
61418 #define F_T6_RX_LINK_STATUS    V_T6_RX_LINK_STATUS(1U)
61420 #define S_HIGH_BER    1
61421 #define V_HIGH_BER(x) ((x) << S_HIGH_BER)
61422 #define F_HIGH_BER    V_HIGH_BER(1U)
61425 #define V_KR4_BLOCK_LOCK(x) ((x) << S_KR4_BLOCK_LOCK)
61426 #define F_KR4_BLOCK_LOCK    V_KR4_BLOCK_LOCK(1U)
61431 #define V_LATCHED_BL_LK(x) ((x) << S_LATCHED_BL_LK)
61432 #define F_LATCHED_BL_LK    V_LATCHED_BL_LK(1U)
61435 #define V_LATCHED_HG_BR(x) ((x) << S_LATCHED_HG_BR)
61436 #define F_LATCHED_HG_BR    V_LATCHED_HG_BR(1U)
61440 #define V_BER_CNT(x) ((x) << S_BER_CNT)
61441 #define G_BER_CNT(x) (((x) >> S_BER_CNT) & M_BER_CNT)
61445 #define V_ERR_BL_CNT(x) ((x) << S_ERR_BL_CNT)
61446 #define G_ERR_BL_CNT(x) (((x) >> S_ERR_BL_CNT) & M_ERR_BL_CNT)
61451 #define V_TX_TP_EN(x) ((x) << S_TX_TP_EN)
61452 #define F_TX_TP_EN    V_TX_TP_EN(1U)
61455 #define V_RX_TP_EN(x) ((x) << S_RX_TP_EN)
61456 #define F_RX_TP_EN    V_RX_TP_EN(1U)
61462 #define V_TP_ERR_CNTR(x) ((x) << S_TP_ERR_CNTR)
61463 #define G_TP_ERR_CNTR(x) (((x) >> S_TP_ERR_CNTR) & M_TP_ERR_CNTR)
61469 #define V_BER_HI_ORDER_CNT(x) ((x) << S_BER_HI_ORDER_CNT)
61470 #define G_BER_HI_ORDER_CNT(x) (((x) >> S_BER_HI_ORDER_CNT) & M_BER_HI_ORDER_CNT)
61475 #define V_HI_ORDER_CNT_EN(x) ((x) << S_HI_ORDER_CNT_EN)
61476 #define F_HI_ORDER_CNT_EN    V_HI_ORDER_CNT_EN(1U)
61480 #define V_ERR_BLK_CNTR(x) ((x) << S_ERR_BLK_CNTR)
61481 #define G_ERR_BLK_CNTR(x) (((x) >> S_ERR_BLK_CNTR) & M_ERR_BLK_CNTR)
61486 #define V_LANE_ALIGN_STATUS(x) ((x) << S_LANE_ALIGN_STATUS)
61487 #define F_LANE_ALIGN_STATUS    V_LANE_ALIGN_STATUS(1U)
61490 #define V_LANE_3_BLK_LCK(x) ((x) << S_LANE_3_BLK_LCK)
61491 #define F_LANE_3_BLK_LCK    V_LANE_3_BLK_LCK(1U)
61494 #define V_LANE_2_BLK_LC32_6431K(x) ((x) << S_LANE_2_BLK_LC32_6431K)
61495 #define F_LANE_2_BLK_LC32_6431K    V_LANE_2_BLK_LC32_6431K(1U)
61497 #define S_LANE_1_BLK_LCK    1
61498 #define V_LANE_1_BLK_LCK(x) ((x) << S_LANE_1_BLK_LCK)
61499 #define F_LANE_1_BLK_LCK    V_LANE_1_BLK_LCK(1U)
61502 #define V_LANE_0_BLK_LCK(x) ((x) << S_LANE_0_BLK_LCK)
61503 #define F_LANE_0_BLK_LCK    V_LANE_0_BLK_LCK(1U)
61509 #define V_LANE_3_ALIGN_MRKR_LCK(x) ((x) << S_LANE_3_ALIGN_MRKR_LCK)
61510 #define F_LANE_3_ALIGN_MRKR_LCK    V_LANE_3_ALIGN_MRKR_LCK(1U)
61513 #define V_LANE_2_ALIGN_MRKR_LCK(x) ((x) << S_LANE_2_ALIGN_MRKR_LCK)
61514 #define F_LANE_2_ALIGN_MRKR_LCK    V_LANE_2_ALIGN_MRKR_LCK(1U)
61516 #define S_LANE_1_ALIGN_MRKR_LCK    1
61517 #define V_LANE_1_ALIGN_MRKR_LCK(x) ((x) << S_LANE_1_ALIGN_MRKR_LCK)
61518 #define F_LANE_1_ALIGN_MRKR_LCK    V_LANE_1_ALIGN_MRKR_LCK(1U)
61521 #define V_LANE_0_ALIGN_MRKR_LCK(x) ((x) << S_LANE_0_ALIGN_MRKR_LCK)
61522 #define F_LANE_0_ALIGN_MRKR_LCK    V_LANE_0_ALIGN_MRKR_LCK(1U)
61529 #define V_CLK_DIV(x) ((x) << S_CLK_DIV)
61530 #define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
61533 #define V_CL45_EN(x) ((x) << S_CL45_EN)
61534 #define F_CL45_EN    V_CL45_EN(1U)
61537 #define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
61538 #define F_DISABLE_PREAMBLE    V_DISABLE_PREAMBLE(1U)
61542 #define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
61543 #define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
61545 #define S_MDIO_READ_ERR    1
61546 #define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
61547 #define F_MDIO_READ_ERR    V_MDIO_READ_ERR(1U)
61550 #define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
61551 #define F_MDIO_BUSY    V_MDIO_BUSY(1U)
61556 #define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
61557 #define F_MDIO_CMD_READ    V_MDIO_CMD_READ(1U)
61560 #define V_READ_INCR(x) ((x) << S_READ_INCR)
61561 #define F_READ_INCR    V_READ_INCR(1U)
61565 #define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
61566 #define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
61570 #define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
61571 #define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
61576 #define V_READBUSY(x) ((x) << S_READBUSY)
61577 #define F_READBUSY    V_READBUSY(1U)
61581 #define V_DATA_WORD(x) ((x) << S_DATA_WORD)
61582 #define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
61588 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
61589 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
61595 #define V_BIP_ERR_CNT_LANE_0(x) ((x) << S_BIP_ERR_CNT_LANE_0)
61596 #define G_BIP_ERR_CNT_LANE_0(x) (((x) >> S_BIP_ERR_CNT_LANE_0) & M_BIP_ERR_CNT_LANE_0)
61602 #define V_BIP_ERR_CNT_LANE_1(x) ((x) << S_BIP_ERR_CNT_LANE_1)
61603 #define G_BIP_ERR_CNT_LANE_1(x) (((x) >> S_BIP_ERR_CNT_LANE_1) & M_BIP_ERR_CNT_LANE_1)
61609 #define V_BIP_ERR_CNT_LANE_2(x) ((x) << S_BIP_ERR_CNT_LANE_2)
61610 #define G_BIP_ERR_CNT_LANE_2(x) (((x) >> S_BIP_ERR_CNT_LANE_2) & M_BIP_ERR_CNT_LANE_2)
61616 #define V_BIP_ERR_CNT_LANE_3(x) ((x) << S_BIP_ERR_CNT_LANE_3)
61617 #define G_BIP_ERR_CNT_LANE_3(x) (((x) >> S_BIP_ERR_CNT_LANE_3) & M_BIP_ERR_CNT_LANE_3)
61623 #define V_VLANTAG(x) ((x) << S_VLANTAG)
61624 #define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
61637 #define V_KR4_LANE_0_MAPPING(x) ((x) << S_KR4_LANE_0_MAPPING)
61638 #define G_KR4_LANE_0_MAPPING(x) (((x) >> S_KR4_LANE_0_MAPPING) & M_KR4_LANE_0_MAPPING)
61644 #define V_KR4_LANE_1_MAPPING(x) ((x) << S_KR4_LANE_1_MAPPING)
61645 #define G_KR4_LANE_1_MAPPING(x) (((x) >> S_KR4_LANE_1_MAPPING) & M_KR4_LANE_1_MAPPING)
61651 #define V_KR4_LANE_2_MAPPING(x) ((x) << S_KR4_LANE_2_MAPPING)
61652 #define G_KR4_LANE_2_MAPPING(x) (((x) >> S_KR4_LANE_2_MAPPING) & M_KR4_LANE_2_MAPPING)
61658 #define V_KR4_LANE_3_MAPPING(x) ((x) << S_KR4_LANE_3_MAPPING)
61659 #define G_KR4_LANE_3_MAPPING(x) (((x) >> S_KR4_LANE_3_MAPPING) & M_KR4_LANE_3_MAPPING)
61666 #define V_SHRT_MRKR_CNFG(x) ((x) << S_SHRT_MRKR_CNFG)
61667 #define F_SHRT_MRKR_CNFG    V_SHRT_MRKR_CNFG(1U)
61674 #define V_CR4_RX_LINK_STATUS(x) ((x) << S_CR4_RX_LINK_STATUS)
61675 #define F_CR4_RX_LINK_STATUS    V_CR4_RX_LINK_STATUS(1U)
61681 #define V_CR4_DEVICE_ID0(x) ((x) << S_CR4_DEVICE_ID0)
61682 #define G_CR4_DEVICE_ID0(x) (((x) >> S_CR4_DEVICE_ID0) & M_CR4_DEVICE_ID0)
61688 #define V_CR4_DEVICE_ID1(x) ((x) << S_CR4_DEVICE_ID1)
61689 #define G_CR4_DEVICE_ID1(x) (((x) >> S_CR4_DEVICE_ID1) & M_CR4_DEVICE_ID1)
61694 #define V_CR4_100G_CAPABLE(x) ((x) << S_CR4_100G_CAPABLE)
61695 #define F_CR4_100G_CAPABLE    V_CR4_100G_CAPABLE(1U)
61698 #define V_CR4_40G_CAPABLE(x) ((x) << S_CR4_40G_CAPABLE)
61699 #define F_CR4_40G_CAPABLE    V_CR4_40G_CAPABLE(1U)
61704 #define V_CLAUSE22REG_PRESENT(x) ((x) << S_CLAUSE22REG_PRESENT)
61705 #define F_CLAUSE22REG_PRESENT    V_CLAUSE22REG_PRESENT(1U)
61710 #define V_VSD_2_PRESENT(x) ((x) << S_VSD_2_PRESENT)
61711 #define F_VSD_2_PRESENT    V_VSD_2_PRESENT(1U)
61714 #define V_VSD_1_PRESENT(x) ((x) << S_VSD_1_PRESENT)
61715 #define F_VSD_1_PRESENT    V_VSD_1_PRESENT(1U)
61718 #define V_CLAUSE22_EXT_PRESENT(x) ((x) << S_CLAUSE22_EXT_PRESENT)
61719 #define F_CLAUSE22_EXT_PRESENT    V_CLAUSE22_EXT_PRESENT(1U)
61725 #define V_CR4_PCS_TYPE_SELECTION(x) ((x) << S_CR4_PCS_TYPE_SELECTION)
61726 #define G_CR4_PCS_TYPE_SELECTION(x) (((x) >> S_CR4_PCS_TYPE_SELECTION) & M_CR4_PCS_TYPE_SELECTION)
61734 #define V_RX_LINK_STAT(x) ((x) << S_RX_LINK_STAT)
61735 #define F_RX_LINK_STAT    V_RX_LINK_STAT(1U)
61738 #define V_BR_BLOCK_LOCK(x) ((x) << S_BR_BLOCK_LOCK)
61739 #define F_BR_BLOCK_LOCK    V_BR_BLOCK_LOCK(1U)
61745 #define V_BER_COUNTER(x) ((x) << S_BER_COUNTER)
61746 #define G_BER_COUNTER(x) (((x) >> S_BER_COUNTER) & M_BER_COUNTER)
61750 #define V_ERRORED_BLOCKS_CNTR(x) ((x) << S_ERRORED_BLOCKS_CNTR)
61751 #define G_ERRORED_BLOCKS_CNTR(x) (((x) >> S_ERRORED_BLOCKS_CNTR) & M_ERRORED_BLOCKS_CNTR)
61756 #define V_SCRAMBLED_ID_TP_EN(x) ((x) << S_SCRAMBLED_ID_TP_EN)
61757 #define F_SCRAMBLED_ID_TP_EN    V_SCRAMBLED_ID_TP_EN(1U)
61763 #define V_BASE_R_TEST_ERR_CNT(x) ((x) << S_BASE_R_TEST_ERR_CNT)
61764 #define G_BASE_R_TEST_ERR_CNT(x) (((x) >> S_BASE_R_TEST_ERR_CNT) & M_BASE_R_TEST_ERR_CNT)
61770 #define V_BER_HIGH_ORDER_CNT(x) ((x) << S_BER_HIGH_ORDER_CNT)
61771 #define G_BER_HIGH_ORDER_CNT(x) (((x) >> S_BER_HIGH_ORDER_CNT) & M_BER_HIGH_ORDER_CNT)
61776 #define V_HI_ORDER_CNT_PRESENT(x) ((x) << S_HI_ORDER_CNT_PRESENT)
61777 #define F_HI_ORDER_CNT_PRESENT    V_HI_ORDER_CNT_PRESENT(1U)
61781 #define V_ERR_BLKS_CNTR(x) ((x) << S_ERR_BLKS_CNTR)
61782 #define G_ERR_BLKS_CNTR(x) (((x) >> S_ERR_BLKS_CNTR) & M_ERR_BLKS_CNTR)
61787 #define V_LANE_ALIGN_STAT(x) ((x) << S_LANE_ALIGN_STAT)
61788 #define F_LANE_ALIGN_STAT    V_LANE_ALIGN_STAT(1U)
61791 #define V_LANE_7_BLCK_LCK(x) ((x) << S_LANE_7_BLCK_LCK)
61792 #define F_LANE_7_BLCK_LCK    V_LANE_7_BLCK_LCK(1U)
61795 #define V_LANE_6_BLCK_LCK(x) ((x) << S_LANE_6_BLCK_LCK)
61796 #define F_LANE_6_BLCK_LCK    V_LANE_6_BLCK_LCK(1U)
61799 #define V_LANE_5_BLCK_LCK(x) ((x) << S_LANE_5_BLCK_LCK)
61800 #define F_LANE_5_BLCK_LCK    V_LANE_5_BLCK_LCK(1U)
61803 #define V_LANE_4_BLCK_LCK(x) ((x) << S_LANE_4_BLCK_LCK)
61804 #define F_LANE_4_BLCK_LCK    V_LANE_4_BLCK_LCK(1U)
61807 #define V_LANE_3_BLCK_LCK(x) ((x) << S_LANE_3_BLCK_LCK)
61808 #define F_LANE_3_BLCK_LCK    V_LANE_3_BLCK_LCK(1U)
61811 #define V_LANE_2_BLCK_LCK(x) ((x) << S_LANE_2_BLCK_LCK)
61812 #define F_LANE_2_BLCK_LCK    V_LANE_2_BLCK_LCK(1U)
61814 #define S_LANE_1_BLCK_LCK    1
61815 #define V_LANE_1_BLCK_LCK(x) ((x) << S_LANE_1_BLCK_LCK)
61816 #define F_LANE_1_BLCK_LCK    V_LANE_1_BLCK_LCK(1U)
61819 #define V_LANE_0_BLCK_LCK(x) ((x) << S_LANE_0_BLCK_LCK)
61820 #define F_LANE_0_BLCK_LCK    V_LANE_0_BLCK_LCK(1U)
61825 #define V_LANE_19_BLCK_LCK(x) ((x) << S_LANE_19_BLCK_LCK)
61826 #define F_LANE_19_BLCK_LCK    V_LANE_19_BLCK_LCK(1U)
61829 #define V_LANE_18_BLCK_LCK(x) ((x) << S_LANE_18_BLCK_LCK)
61830 #define F_LANE_18_BLCK_LCK    V_LANE_18_BLCK_LCK(1U)
61833 #define V_LANE_17_BLCK_LCK(x) ((x) << S_LANE_17_BLCK_LCK)
61834 #define F_LANE_17_BLCK_LCK    V_LANE_17_BLCK_LCK(1U)
61837 #define V_LANE_16_BLCK_LCK(x) ((x) << S_LANE_16_BLCK_LCK)
61838 #define F_LANE_16_BLCK_LCK    V_LANE_16_BLCK_LCK(1U)
61841 #define V_LANE_15_BLCK_LCK(x) ((x) << S_LANE_15_BLCK_LCK)
61842 #define F_LANE_15_BLCK_LCK    V_LANE_15_BLCK_LCK(1U)
61845 #define V_LANE_14_BLCK_LCK(x) ((x) << S_LANE_14_BLCK_LCK)
61846 #define F_LANE_14_BLCK_LCK    V_LANE_14_BLCK_LCK(1U)
61849 #define V_LANE_13_BLCK_LCK(x) ((x) << S_LANE_13_BLCK_LCK)
61850 #define F_LANE_13_BLCK_LCK    V_LANE_13_BLCK_LCK(1U)
61853 #define V_LANE_12_BLCK_LCK(x) ((x) << S_LANE_12_BLCK_LCK)
61854 #define F_LANE_12_BLCK_LCK    V_LANE_12_BLCK_LCK(1U)
61857 #define V_LANE_11_BLCK_LCK(x) ((x) << S_LANE_11_BLCK_LCK)
61858 #define F_LANE_11_BLCK_LCK    V_LANE_11_BLCK_LCK(1U)
61861 #define V_LANE_10_BLCK_LCK(x) ((x) << S_LANE_10_BLCK_LCK)
61862 #define F_LANE_10_BLCK_LCK    V_LANE_10_BLCK_LCK(1U)
61864 #define S_LANE_9_BLCK_LCK    1
61865 #define V_LANE_9_BLCK_LCK(x) ((x) << S_LANE_9_BLCK_LCK)
61866 #define F_LANE_9_BLCK_LCK    V_LANE_9_BLCK_LCK(1U)
61869 #define V_LANE_8_BLCK_LCK(x) ((x) << S_LANE_8_BLCK_LCK)
61870 #define F_LANE_8_BLCK_LCK    V_LANE_8_BLCK_LCK(1U)
61875 #define V_LANE7_ALGN_MRKR_LCK(x) ((x) << S_LANE7_ALGN_MRKR_LCK)
61876 #define F_LANE7_ALGN_MRKR_LCK    V_LANE7_ALGN_MRKR_LCK(1U)
61879 #define V_LANE6_ALGN_MRKR_LCK(x) ((x) << S_LANE6_ALGN_MRKR_LCK)
61880 #define F_LANE6_ALGN_MRKR_LCK    V_LANE6_ALGN_MRKR_LCK(1U)
61883 #define V_LANE5_ALGN_MRKR_LCK(x) ((x) << S_LANE5_ALGN_MRKR_LCK)
61884 #define F_LANE5_ALGN_MRKR_LCK    V_LANE5_ALGN_MRKR_LCK(1U)
61887 #define V_LANE4_ALGN_MRKR_LCK(x) ((x) << S_LANE4_ALGN_MRKR_LCK)
61888 #define F_LANE4_ALGN_MRKR_LCK    V_LANE4_ALGN_MRKR_LCK(1U)
61891 #define V_LANE3_ALGN_MRKR_LCK(x) ((x) << S_LANE3_ALGN_MRKR_LCK)
61892 #define F_LANE3_ALGN_MRKR_LCK    V_LANE3_ALGN_MRKR_LCK(1U)
61895 #define V_LANE2_ALGN_MRKR_LCK(x) ((x) << S_LANE2_ALGN_MRKR_LCK)
61896 #define F_LANE2_ALGN_MRKR_LCK    V_LANE2_ALGN_MRKR_LCK(1U)
61898 #define S_LANE1_ALGN_MRKR_LCK    1
61899 #define V_LANE1_ALGN_MRKR_LCK(x) ((x) << S_LANE1_ALGN_MRKR_LCK)
61900 #define F_LANE1_ALGN_MRKR_LCK    V_LANE1_ALGN_MRKR_LCK(1U)
61903 #define V_LANE0_ALGN_MRKR_LCK(x) ((x) << S_LANE0_ALGN_MRKR_LCK)
61904 #define F_LANE0_ALGN_MRKR_LCK    V_LANE0_ALGN_MRKR_LCK(1U)
61909 #define V_LANE19_ALGN_MRKR_LCK(x) ((x) << S_LANE19_ALGN_MRKR_LCK)
61910 #define F_LANE19_ALGN_MRKR_LCK    V_LANE19_ALGN_MRKR_LCK(1U)
61913 #define V_LANE18_ALGN_MRKR_LCK(x) ((x) << S_LANE18_ALGN_MRKR_LCK)
61914 #define F_LANE18_ALGN_MRKR_LCK    V_LANE18_ALGN_MRKR_LCK(1U)
61917 #define V_LANE17_ALGN_MRKR_LCK(x) ((x) << S_LANE17_ALGN_MRKR_LCK)
61918 #define F_LANE17_ALGN_MRKR_LCK    V_LANE17_ALGN_MRKR_LCK(1U)
61921 #define V_LANE16_ALGN_MRKR_LCK(x) ((x) << S_LANE16_ALGN_MRKR_LCK)
61922 #define F_LANE16_ALGN_MRKR_LCK    V_LANE16_ALGN_MRKR_LCK(1U)
61925 #define V_LANE15_ALGN_MRKR_LCK(x) ((x) << S_LANE15_ALGN_MRKR_LCK)
61926 #define F_LANE15_ALGN_MRKR_LCK    V_LANE15_ALGN_MRKR_LCK(1U)
61929 #define V_LANE14_ALGN_MRKR_LCK(x) ((x) << S_LANE14_ALGN_MRKR_LCK)
61930 #define F_LANE14_ALGN_MRKR_LCK    V_LANE14_ALGN_MRKR_LCK(1U)
61933 #define V_LANE13_ALGN_MRKR_LCK(x) ((x) << S_LANE13_ALGN_MRKR_LCK)
61934 #define F_LANE13_ALGN_MRKR_LCK    V_LANE13_ALGN_MRKR_LCK(1U)
61937 #define V_LANE12_ALGN_MRKR_LCK(x) ((x) << S_LANE12_ALGN_MRKR_LCK)
61938 #define F_LANE12_ALGN_MRKR_LCK    V_LANE12_ALGN_MRKR_LCK(1U)
61941 #define V_LANE11_ALGN_MRKR_LCK(x) ((x) << S_LANE11_ALGN_MRKR_LCK)
61942 #define F_LANE11_ALGN_MRKR_LCK    V_LANE11_ALGN_MRKR_LCK(1U)
61945 #define V_LANE10_ALGN_MRKR_LCK(x) ((x) << S_LANE10_ALGN_MRKR_LCK)
61946 #define F_LANE10_ALGN_MRKR_LCK    V_LANE10_ALGN_MRKR_LCK(1U)
61948 #define S_LANE9_ALGN_MRKR_LCK    1
61949 #define V_LANE9_ALGN_MRKR_LCK(x) ((x) << S_LANE9_ALGN_MRKR_LCK)
61950 #define F_LANE9_ALGN_MRKR_LCK    V_LANE9_ALGN_MRKR_LCK(1U)
61953 #define V_LANE8_ALGN_MRKR_LCK(x) ((x) << S_LANE8_ALGN_MRKR_LCK)
61954 #define F_LANE8_ALGN_MRKR_LCK    V_LANE8_ALGN_MRKR_LCK(1U)
61959 #define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
61960 #define F_PCS_LPBK    V_PCS_LPBK(1U)
61963 #define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
61964 #define F_SPEED_SEL1    V_SPEED_SEL1(1U)
61967 #define V_LP_MODE(x) ((x) << S_LP_MODE)
61968 #define F_LP_MODE    V_LP_MODE(1U)
61971 #define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
61972 #define F_SPEED_SEL0    V_SPEED_SEL0(1U)
61976 #define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
61977 #define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
61982 #define V_FAULTDET(x) ((x) << S_FAULTDET)
61983 #define F_FAULTDET    V_FAULTDET(1U)
61986 #define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
61987 #define F_RX_LINK_STATUS    V_RX_LINK_STATUS(1U)
61989 #define S_LOPWRABL    1
61990 #define V_LOPWRABL(x) ((x) << S_LOPWRABL)
61991 #define F_LOPWRABL    V_LOPWRABL(1U)
61997 #define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
61998 #define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
62004 #define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
62005 #define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
62010 #define V_100G(x) ((x) << S_100G)
62011 #define F_100G    V_100G(1U)
62014 #define V_40G(x) ((x) << S_40G)
62015 #define F_40G    V_40G(1U)
62017 #define S_10BASE_TL    1
62018 #define V_10BASE_TL(x) ((x) << S_10BASE_TL)
62019 #define F_10BASE_TL    V_10BASE_TL(1U)
62022 #define V_10G(x) ((x) << S_10G)
62023 #define F_10G    V_10G(1U)
62028 #define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
62029 #define F_TC_PRESENT    V_TC_PRESENT(1U)
62032 #define V_DTEXS(x) ((x) << S_DTEXS)
62033 #define F_DTEXS    V_DTEXS(1U)
62036 #define V_PHYXS(x) ((x) << S_PHYXS)
62037 #define F_PHYXS    V_PHYXS(1U)
62040 #define V_PCS(x) ((x) << S_PCS)
62041 #define F_PCS    V_PCS(1U)
62044 #define V_WIS(x) ((x) << S_WIS)
62045 #define F_WIS    V_WIS(1U)
62047 #define S_PMD_PMA    1
62048 #define V_PMD_PMA(x) ((x) << S_PMD_PMA)
62049 #define F_PMD_PMA    V_PMD_PMA(1U)
62052 #define V_CL22(x) ((x) << S_CL22)
62053 #define F_CL22    V_CL22(1U)
62058 #define V_VENDDEV2(x) ((x) << S_VENDDEV2)
62059 #define F_VENDDEV2    V_VENDDEV2(1U)
62062 #define V_VENDDEV1(x) ((x) << S_VENDDEV1)
62063 #define F_VENDDEV1    V_VENDDEV1(1U)
62066 #define V_CL22EXT(x) ((x) << S_CL22EXT)
62067 #define F_CL22EXT    V_CL22EXT(1U)
62073 #define V_PCSTYPE(x) ((x) << S_PCSTYPE)
62074 #define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
62079 #define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
62080 #define F_PCS_STAT2_DEVICE    V_PCS_STAT2_DEVICE(1U)
62083 #define V_TXFAULT(x) ((x) << S_TXFAULT)
62084 #define F_TXFAULT    V_TXFAULT(1U)
62087 #define V_RXFAULT(x) ((x) << S_RXFAULT)
62088 #define F_RXFAULT    V_RXFAULT(1U)
62091 #define V_100BASE_R(x) ((x) << S_100BASE_R)
62092 #define F_100BASE_R    V_100BASE_R(1U)
62095 #define V_40GBASE_R(x) ((x) << S_40GBASE_R)
62096 #define F_40GBASE_R    V_40GBASE_R(1U)
62099 #define V_10GBASE_T(x) ((x) << S_10GBASE_T)
62100 #define F_10GBASE_T    V_10GBASE_T(1U)
62103 #define V_10GBASE_W(x) ((x) << S_10GBASE_W)
62104 #define F_10GBASE_W    V_10GBASE_W(1U)
62106 #define S_10GBASE_X    1
62107 #define V_10GBASE_X(x) ((x) << S_10GBASE_X)
62108 #define F_10GBASE_X    V_10GBASE_X(1U)
62111 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
62112 #define F_10GBASE_R    V_10GBASE_R(1U)
62118 #define V_BIP_ERR_CNTLANE_0(x) ((x) << S_BIP_ERR_CNTLANE_0)
62119 #define G_BIP_ERR_CNTLANE_0(x) (((x) >> S_BIP_ERR_CNTLANE_0) & M_BIP_ERR_CNTLANE_0)
62125 #define V_BIP_ERR_CNTLANE_1(x) ((x) << S_BIP_ERR_CNTLANE_1)
62126 #define G_BIP_ERR_CNTLANE_1(x) (((x) >> S_BIP_ERR_CNTLANE_1) & M_BIP_ERR_CNTLANE_1)
62132 #define V_BIP_ERR_CNTLANE_2(x) ((x) << S_BIP_ERR_CNTLANE_2)
62133 #define G_BIP_ERR_CNTLANE_2(x) (((x) >> S_BIP_ERR_CNTLANE_2) & M_BIP_ERR_CNTLANE_2)
62139 #define V_BIP_ERR_CNTLANE_3(x) ((x) << S_BIP_ERR_CNTLANE_3)
62140 #define G_BIP_ERR_CNTLANE_3(x) (((x) >> S_BIP_ERR_CNTLANE_3) & M_BIP_ERR_CNTLANE_3)
62146 #define V_BIP_ERR_CNTLANE_4(x) ((x) << S_BIP_ERR_CNTLANE_4)
62147 #define G_BIP_ERR_CNTLANE_4(x) (((x) >> S_BIP_ERR_CNTLANE_4) & M_BIP_ERR_CNTLANE_4)
62153 #define V_BIP_ERR_CNTLANE_5(x) ((x) << S_BIP_ERR_CNTLANE_5)
62154 #define G_BIP_ERR_CNTLANE_5(x) (((x) >> S_BIP_ERR_CNTLANE_5) & M_BIP_ERR_CNTLANE_5)
62160 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
62161 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
62167 #define V_BIP_ERR_CNTLANE_6(x) ((x) << S_BIP_ERR_CNTLANE_6)
62168 #define G_BIP_ERR_CNTLANE_6(x) (((x) >> S_BIP_ERR_CNTLANE_6) & M_BIP_ERR_CNTLANE_6)
62174 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
62175 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
62181 #define V_BIP_ERR_CNTLANE_7(x) ((x) << S_BIP_ERR_CNTLANE_7)
62182 #define G_BIP_ERR_CNTLANE_7(x) (((x) >> S_BIP_ERR_CNTLANE_7) & M_BIP_ERR_CNTLANE_7)
62188 #define V_BIP_ERR_CNTLANE_8(x) ((x) << S_BIP_ERR_CNTLANE_8)
62189 #define G_BIP_ERR_CNTLANE_8(x) (((x) >> S_BIP_ERR_CNTLANE_8) & M_BIP_ERR_CNTLANE_8)
62195 #define V_BIP_ERR_CNTLANE_9(x) ((x) << S_BIP_ERR_CNTLANE_9)
62196 #define G_BIP_ERR_CNTLANE_9(x) (((x) >> S_BIP_ERR_CNTLANE_9) & M_BIP_ERR_CNTLANE_9)
62202 #define V_BIP_ERR_CNTLANE_10(x) ((x) << S_BIP_ERR_CNTLANE_10)
62203 #define G_BIP_ERR_CNTLANE_10(x) (((x) >> S_BIP_ERR_CNTLANE_10) & M_BIP_ERR_CNTLANE_10)
62209 #define V_BIP_ERR_CNTLANE_11(x) ((x) << S_BIP_ERR_CNTLANE_11)
62210 #define G_BIP_ERR_CNTLANE_11(x) (((x) >> S_BIP_ERR_CNTLANE_11) & M_BIP_ERR_CNTLANE_11)
62216 #define V_BIP_ERR_CNTLANE_12(x) ((x) << S_BIP_ERR_CNTLANE_12)
62217 #define G_BIP_ERR_CNTLANE_12(x) (((x) >> S_BIP_ERR_CNTLANE_12) & M_BIP_ERR_CNTLANE_12)
62223 #define V_BIP_ERR_CNTLANE_13(x) ((x) << S_BIP_ERR_CNTLANE_13)
62224 #define G_BIP_ERR_CNTLANE_13(x) (((x) >> S_BIP_ERR_CNTLANE_13) & M_BIP_ERR_CNTLANE_13)
62230 #define V_BIP_ERR_CNTLANE_14(x) ((x) << S_BIP_ERR_CNTLANE_14)
62231 #define G_BIP_ERR_CNTLANE_14(x) (((x) >> S_BIP_ERR_CNTLANE_14) & M_BIP_ERR_CNTLANE_14)
62237 #define V_BIP_ERR_CNTLANE_15(x) ((x) << S_BIP_ERR_CNTLANE_15)
62238 #define G_BIP_ERR_CNTLANE_15(x) (((x) >> S_BIP_ERR_CNTLANE_15) & M_BIP_ERR_CNTLANE_15)
62244 #define V_BIP_ERR_CNTLANE_16(x) ((x) << S_BIP_ERR_CNTLANE_16)
62245 #define G_BIP_ERR_CNTLANE_16(x) (((x) >> S_BIP_ERR_CNTLANE_16) & M_BIP_ERR_CNTLANE_16)
62251 #define V_BIP_ERR_CNTLANE_17(x) ((x) << S_BIP_ERR_CNTLANE_17)
62252 #define G_BIP_ERR_CNTLANE_17(x) (((x) >> S_BIP_ERR_CNTLANE_17) & M_BIP_ERR_CNTLANE_17)
62258 #define V_BIP_ERR_CNTLANE_18(x) ((x) << S_BIP_ERR_CNTLANE_18)
62259 #define G_BIP_ERR_CNTLANE_18(x) (((x) >> S_BIP_ERR_CNTLANE_18) & M_BIP_ERR_CNTLANE_18)
62265 #define V_BIP_ERR_CNTLANE_19(x) ((x) << S_BIP_ERR_CNTLANE_19)
62266 #define G_BIP_ERR_CNTLANE_19(x) (((x) >> S_BIP_ERR_CNTLANE_19) & M_BIP_ERR_CNTLANE_19)
62271 #define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
62272 #define F_RXLINKSTATUS    V_RXLINKSTATUS(1U)
62276 #define V_RESEREVED(x) ((x) << S_RESEREVED)
62277 #define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
62280 #define V_10GPRBS9(x) ((x) << S_10GPRBS9)
62281 #define F_10GPRBS9    V_10GPRBS9(1U)
62284 #define V_10GPRBS31(x) ((x) << S_10GPRBS31)
62285 #define F_10GPRBS31    V_10GPRBS31(1U)
62287 #define S_HIBER    1
62288 #define V_HIBER(x) ((x) << S_HIBER)
62289 #define F_HIBER    V_HIBER(1U)
62292 #define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
62293 #define F_BLOCKLOCK    V_BLOCKLOCK(1U)
62298 #define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
62299 #define F_BLOCKLOCKLL    V_BLOCKLOCKLL(1U)
62302 #define V_HIBERLH(x) ((x) << S_HIBERLH)
62303 #define F_HIBERLH    V_HIBERLH(1U)
62307 #define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
62308 #define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
62312 #define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
62313 #define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
62319 #define V_SEEDA(x) ((x) << S_SEEDA)
62320 #define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
62326 #define V_SEEDA1(x) ((x) << S_SEEDA1)
62327 #define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
62333 #define V_SEEDA2(x) ((x) << S_SEEDA2)
62334 #define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
62340 #define V_SEEDA3(x) ((x) << S_SEEDA3)
62341 #define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
62347 #define V_SEEDB(x) ((x) << S_SEEDB)
62348 #define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
62354 #define V_SEEDB1(x) ((x) << S_SEEDB1)
62355 #define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
62361 #define V_SEEDB2(x) ((x) << S_SEEDB2)
62362 #define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
62368 #define V_SEEDB3(x) ((x) << S_SEEDB3)
62369 #define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
62374 #define V_TXPRBS9(x) ((x) << S_TXPRBS9)
62375 #define F_TXPRBS9    V_TXPRBS9(1U)
62378 #define V_RXPRBS31(x) ((x) << S_RXPRBS31)
62379 #define F_RXPRBS31    V_RXPRBS31(1U)
62382 #define V_TXPRBS31(x) ((x) << S_TXPRBS31)
62383 #define F_TXPRBS31    V_TXPRBS31(1U)
62386 #define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
62387 #define F_TXTESTPATEN    V_TXTESTPATEN(1U)
62390 #define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
62391 #define F_RXTESTPATEN    V_RXTESTPATEN(1U)
62393 #define S_TESTPATSEL    1
62394 #define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
62395 #define F_TESTPATSEL    V_TESTPATSEL(1U)
62398 #define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
62399 #define F_DATAPATSEL    V_DATAPATSEL(1U)
62405 #define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
62406 #define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
62412 #define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
62413 #define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
62418 #define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
62419 #define F_HICOUNTPRSNT    V_HICOUNTPRSNT(1U)
62423 #define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
62424 #define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
62429 #define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
62430 #define F_ALIGNSTATUS    V_ALIGNSTATUS(1U)
62433 #define V_LANE7(x) ((x) << S_LANE7)
62434 #define F_LANE7    V_LANE7(1U)
62437 #define V_LANE6(x) ((x) << S_LANE6)
62438 #define F_LANE6    V_LANE6(1U)
62441 #define V_LANE5(x) ((x) << S_LANE5)
62442 #define F_LANE5    V_LANE5(1U)
62445 #define V_LANE4(x) ((x) << S_LANE4)
62446 #define F_LANE4    V_LANE4(1U)
62449 #define V_LANE3(x) ((x) << S_LANE3)
62450 #define F_LANE3    V_LANE3(1U)
62453 #define V_LANE2(x) ((x) << S_LANE2)
62454 #define F_LANE2    V_LANE2(1U)
62456 #define S_LANE1    1
62457 #define V_LANE1(x) ((x) << S_LANE1)
62458 #define F_LANE1    V_LANE1(1U)
62461 #define V_LANE0(x) ((x) << S_LANE0)
62462 #define F_LANE0    V_LANE0(1U)
62467 #define V_LANE19(x) ((x) << S_LANE19)
62468 #define F_LANE19    V_LANE19(1U)
62471 #define V_LANE18(x) ((x) << S_LANE18)
62472 #define F_LANE18    V_LANE18(1U)
62475 #define V_LANE17(x) ((x) << S_LANE17)
62476 #define F_LANE17    V_LANE17(1U)
62479 #define V_LANE16(x) ((x) << S_LANE16)
62480 #define F_LANE16    V_LANE16(1U)
62483 #define V_LANE15(x) ((x) << S_LANE15)
62484 #define F_LANE15    V_LANE15(1U)
62487 #define V_LANE14(x) ((x) << S_LANE14)
62488 #define F_LANE14    V_LANE14(1U)
62491 #define V_LANE13(x) ((x) << S_LANE13)
62492 #define F_LANE13    V_LANE13(1U)
62495 #define V_LANE12(x) ((x) << S_LANE12)
62496 #define F_LANE12    V_LANE12(1U)
62499 #define V_LANE11(x) ((x) << S_LANE11)
62500 #define F_LANE11    V_LANE11(1U)
62503 #define V_LANE10(x) ((x) << S_LANE10)
62504 #define F_LANE10    V_LANE10(1U)
62506 #define S_LANE9    1
62507 #define V_LANE9(x) ((x) << S_LANE9)
62508 #define F_LANE9    V_LANE9(1U)
62511 #define V_LANE8(x) ((x) << S_LANE8)
62512 #define F_LANE8    V_LANE8(1U)
62517 #define V_AMLOCK7(x) ((x) << S_AMLOCK7)
62518 #define F_AMLOCK7    V_AMLOCK7(1U)
62521 #define V_AMLOCK6(x) ((x) << S_AMLOCK6)
62522 #define F_AMLOCK6    V_AMLOCK6(1U)
62525 #define V_AMLOCK5(x) ((x) << S_AMLOCK5)
62526 #define F_AMLOCK5    V_AMLOCK5(1U)
62529 #define V_AMLOCK4(x) ((x) << S_AMLOCK4)
62530 #define F_AMLOCK4    V_AMLOCK4(1U)
62533 #define V_AMLOCK3(x) ((x) << S_AMLOCK3)
62534 #define F_AMLOCK3    V_AMLOCK3(1U)
62537 #define V_AMLOCK2(x) ((x) << S_AMLOCK2)
62538 #define F_AMLOCK2    V_AMLOCK2(1U)
62540 #define S_AMLOCK1    1
62541 #define V_AMLOCK1(x) ((x) << S_AMLOCK1)
62542 #define F_AMLOCK1    V_AMLOCK1(1U)
62545 #define V_AMLOCK0(x) ((x) << S_AMLOCK0)
62546 #define F_AMLOCK0    V_AMLOCK0(1U)
62551 #define V_AMLOCK19(x) ((x) << S_AMLOCK19)
62552 #define F_AMLOCK19    V_AMLOCK19(1U)
62555 #define V_AMLOCK18(x) ((x) << S_AMLOCK18)
62556 #define F_AMLOCK18    V_AMLOCK18(1U)
62559 #define V_AMLOCK17(x) ((x) << S_AMLOCK17)
62560 #define F_AMLOCK17    V_AMLOCK17(1U)
62563 #define V_AMLOCK16(x) ((x) << S_AMLOCK16)
62564 #define F_AMLOCK16    V_AMLOCK16(1U)
62567 #define V_AMLOCK15(x) ((x) << S_AMLOCK15)
62568 #define F_AMLOCK15    V_AMLOCK15(1U)
62571 #define V_AMLOCK14(x) ((x) << S_AMLOCK14)
62572 #define F_AMLOCK14    V_AMLOCK14(1U)
62575 #define V_AMLOCK13(x) ((x) << S_AMLOCK13)
62576 #define F_AMLOCK13    V_AMLOCK13(1U)
62579 #define V_AMLOCK12(x) ((x) << S_AMLOCK12)
62580 #define F_AMLOCK12    V_AMLOCK12(1U)
62583 #define V_AMLOCK11(x) ((x) << S_AMLOCK11)
62584 #define F_AMLOCK11    V_AMLOCK11(1U)
62587 #define V_AMLOCK10(x) ((x) << S_AMLOCK10)
62588 #define F_AMLOCK10    V_AMLOCK10(1U)
62590 #define S_AMLOCK9    1
62591 #define V_AMLOCK9(x) ((x) << S_AMLOCK9)
62592 #define F_AMLOCK9    V_AMLOCK9(1U)
62595 #define V_AMLOCK8(x) ((x) << S_AMLOCK8)
62596 #define F_AMLOCK8    V_AMLOCK8(1U)
62602 #define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
62603 #define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
62628 #define V_MAP(x) ((x) << S_MAP)
62629 #define G_MAP(x) (((x) >> S_MAP) & M_MAP)
62654 #define V_LANE_0_MAPPING(x) ((x) << S_LANE_0_MAPPING)
62655 #define G_LANE_0_MAPPING(x) (((x) >> S_LANE_0_MAPPING) & M_LANE_0_MAPPING)
62661 #define V_LANE_1_MAPPING(x) ((x) << S_LANE_1_MAPPING)
62662 #define G_LANE_1_MAPPING(x) (((x) >> S_LANE_1_MAPPING) & M_LANE_1_MAPPING)
62668 #define V_LANE_2_MAPPING(x) ((x) << S_LANE_2_MAPPING)
62669 #define G_LANE_2_MAPPING(x) (((x) >> S_LANE_2_MAPPING) & M_LANE_2_MAPPING)
62675 #define V_LANE_3_MAPPING(x) ((x) << S_LANE_3_MAPPING)
62676 #define G_LANE_3_MAPPING(x) (((x) >> S_LANE_3_MAPPING) & M_LANE_3_MAPPING)
62682 #define V_LANE_4_MAPPING(x) ((x) << S_LANE_4_MAPPING)
62683 #define G_LANE_4_MAPPING(x) (((x) >> S_LANE_4_MAPPING) & M_LANE_4_MAPPING)
62689 #define V_LANE_5_MAPPING(x) ((x) << S_LANE_5_MAPPING)
62690 #define G_LANE_5_MAPPING(x) (((x) >> S_LANE_5_MAPPING) & M_LANE_5_MAPPING)
62696 #define V_LANE_6_MAPPING(x) ((x) << S_LANE_6_MAPPING)
62697 #define G_LANE_6_MAPPING(x) (((x) >> S_LANE_6_MAPPING) & M_LANE_6_MAPPING)
62703 #define V_LANE_7_MAPPING(x) ((x) << S_LANE_7_MAPPING)
62704 #define G_LANE_7_MAPPING(x) (((x) >> S_LANE_7_MAPPING) & M_LANE_7_MAPPING)
62710 #define V_LANE_8_MAPPING(x) ((x) << S_LANE_8_MAPPING)
62711 #define G_LANE_8_MAPPING(x) (((x) >> S_LANE_8_MAPPING) & M_LANE_8_MAPPING)
62717 #define V_LANE_9_MAPPING(x) ((x) << S_LANE_9_MAPPING)
62718 #define G_LANE_9_MAPPING(x) (((x) >> S_LANE_9_MAPPING) & M_LANE_9_MAPPING)
62724 #define V_LANE_10_MAPPING(x) ((x) << S_LANE_10_MAPPING)
62725 #define G_LANE_10_MAPPING(x) (((x) >> S_LANE_10_MAPPING) & M_LANE_10_MAPPING)
62731 #define V_LANE_11_MAPPING(x) ((x) << S_LANE_11_MAPPING)
62732 #define G_LANE_11_MAPPING(x) (((x) >> S_LANE_11_MAPPING) & M_LANE_11_MAPPING)
62738 #define V_LANE_12_MAPPING(x) ((x) << S_LANE_12_MAPPING)
62739 #define G_LANE_12_MAPPING(x) (((x) >> S_LANE_12_MAPPING) & M_LANE_12_MAPPING)
62745 #define V_LANE_13_MAPPING(x) ((x) << S_LANE_13_MAPPING)
62746 #define G_LANE_13_MAPPING(x) (((x) >> S_LANE_13_MAPPING) & M_LANE_13_MAPPING)
62752 #define V_LANE_14_MAPPING(x) ((x) << S_LANE_14_MAPPING)
62753 #define G_LANE_14_MAPPING(x) (((x) >> S_LANE_14_MAPPING) & M_LANE_14_MAPPING)
62759 #define V_LANE_15_MAPPING(x) ((x) << S_LANE_15_MAPPING)
62760 #define G_LANE_15_MAPPING(x) (((x) >> S_LANE_15_MAPPING) & M_LANE_15_MAPPING)
62766 #define V_LANE_16_MAPPING(x) ((x) << S_LANE_16_MAPPING)
62767 #define G_LANE_16_MAPPING(x) (((x) >> S_LANE_16_MAPPING) & M_LANE_16_MAPPING)
62773 #define V_LANE_17_MAPPING(x) ((x) << S_LANE_17_MAPPING)
62774 #define G_LANE_17_MAPPING(x) (((x) >> S_LANE_17_MAPPING) & M_LANE_17_MAPPING)
62780 #define V_LANE_18_MAPPING(x) ((x) << S_LANE_18_MAPPING)
62781 #define G_LANE_18_MAPPING(x) (((x) >> S_LANE_18_MAPPING) & M_LANE_18_MAPPING)
62787 #define V_LANE_19_MAPPING(x) ((x) << S_LANE_19_MAPPING)
62788 #define G_LANE_19_MAPPING(x) (((x) >> S_LANE_19_MAPPING) & M_LANE_19_MAPPING)
62795 #define V_CORE_REVISION(x) ((x) << S_CORE_REVISION)
62796 #define G_CORE_REVISION(x) (((x) >> S_CORE_REVISION) & M_CORE_REVISION)
62801 #define V_AN_RESET(x) ((x) << S_AN_RESET)
62802 #define F_AN_RESET    V_AN_RESET(1U)
62805 #define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
62806 #define F_EXT_NXP_CTRL    V_EXT_NXP_CTRL(1U)
62809 #define V_BEAN_EN(x) ((x) << S_BEAN_EN)
62810 #define F_BEAN_EN    V_BEAN_EN(1U)
62813 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
62814 #define F_RESTART_BEAN    V_RESTART_BEAN(1U)
62818 #define S_RS_FEC_BYPASS_ERROR_INDICATION    1
62819 #define V_RS_FEC_BYPASS_ERROR_INDICATION(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION)
62820 #define F_RS_FEC_BYPASS_ERROR_INDICATION    V_RS_FEC_BYPASS_ERROR_INDICATION(1U)
62823 #define V_RS_FEC_BYPASS_CORRECTION(x) ((x) << S_RS_FEC_BYPASS_CORRECTION)
62824 #define F_RS_FEC_BYPASS_CORRECTION    V_RS_FEC_BYPASS_CORRECTION(1U)
62829 #define V_PDF(x) ((x) << S_PDF)
62830 #define F_PDF    V_PDF(1U)
62833 #define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
62834 #define F_EXT_NXP_STATUS    V_EXT_NXP_STATUS(1U)
62837 #define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
62838 #define F_PAGE_RCVD    V_PAGE_RCVD(1U)
62841 #define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
62842 #define F_BEAN_COMPLETE    V_BEAN_COMPLETE(1U)
62845 #define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
62846 #define F_REM_FAULT_STATUS    V_REM_FAULT_STATUS(1U)
62849 #define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
62850 #define F_BEAN_ABILITY    V_BEAN_ABILITY(1U)
62853 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
62854 #define F_LP_BEAN_ABILITY    V_LP_BEAN_ABILITY(1U)
62859 #define V_RS_FEC_PCS_ALIGN_STATUS(x) ((x) << S_RS_FEC_PCS_ALIGN_STATUS)
62860 #define F_RS_FEC_PCS_ALIGN_STATUS    V_RS_FEC_PCS_ALIGN_STATUS(1U)
62863 #define V_FEC_ALIGN_STATUS(x) ((x) << S_FEC_ALIGN_STATUS)
62864 #define F_FEC_ALIGN_STATUS    V_FEC_ALIGN_STATUS(1U)
62867 #define V_RS_FEC_HIGH_SER(x) ((x) << S_RS_FEC_HIGH_SER)
62868 #define F_RS_FEC_HIGH_SER    V_RS_FEC_HIGH_SER(1U)
62870 #define S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    1
62871 #define V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY)
62872 #define F_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY    V_RS_FEC_BYPASS_ERROR_INDICATION_ABILITY(1U)
62875 #define V_RS_FEC_BYPASS_CORRECTION_ABILITY(x) ((x) << S_RS_FEC_BYPASS_CORRECTION_ABILITY)
62876 #define F_RS_FEC_BYPASS_CORRECTION_ABILITY    V_RS_FEC_BYPASS_CORRECTION_ABILITY(1U)
62881 #define V_NXP(x) ((x) << S_NXP)
62882 #define F_NXP    V_NXP(1U)
62885 #define V_REM_FAULT(x) ((x) << S_REM_FAULT)
62886 #define F_REM_FAULT    V_REM_FAULT(1U)
62890 #define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
62891 #define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
62895 #define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
62896 #define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
62900 #define V_SELECTOR(x) ((x) << S_SELECTOR)
62901 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
62907 #define V_RS_RS_FEC_CCW_LO(x) ((x) << S_RS_RS_FEC_CCW_LO)
62908 #define G_RS_RS_FEC_CCW_LO(x) (((x) >> S_RS_RS_FEC_CCW_LO) & M_RS_RS_FEC_CCW_LO)
62914 #define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
62915 #define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
62919 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
62920 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
62926 #define V_RS_RS_FEC_CCW_HI(x) ((x) << S_RS_RS_FEC_CCW_HI)
62927 #define G_RS_RS_FEC_CCW_HI(x) (((x) >> S_RS_RS_FEC_CCW_HI) & M_RS_RS_FEC_CCW_HI)
62933 #define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
62934 #define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
62938 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
62939 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
62945 #define V_RS_RS_FEC_NCCW_LO(x) ((x) << S_RS_RS_FEC_NCCW_LO)
62946 #define G_RS_RS_FEC_NCCW_LO(x) (((x) >> S_RS_RS_FEC_NCCW_LO) & M_RS_RS_FEC_NCCW_LO)
62953 #define V_RS_RS_FEC_NCCW_HI(x) ((x) << S_RS_RS_FEC_NCCW_HI)
62954 #define G_RS_RS_FEC_NCCW_HI(x) (((x) >> S_RS_RS_FEC_NCCW_HI) & M_RS_RS_FEC_NCCW_HI)
62961 #define V_PMA_MAPPING(x) ((x) << S_PMA_MAPPING)
62962 #define G_PMA_MAPPING(x) (((x) >> S_PMA_MAPPING) & M_PMA_MAPPING)
62969 #define V_MS_COUNT(x) ((x) << S_MS_COUNT)
62970 #define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
62975 #define V_XNP(x) ((x) << S_XNP)
62976 #define F_XNP    V_XNP(1U)
62979 #define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
62980 #define F_ACKNOWLEDGE    V_ACKNOWLEDGE(1U)
62983 #define V_MP(x) ((x) << S_MP)
62984 #define F_MP    V_MP(1U)
62987 #define V_ACK2(x) ((x) << S_ACK2)
62988 #define F_ACK2    V_ACK2(1U)
62992 #define V_MU(x) ((x) << S_MU)
62993 #define G_MU(x) (((x) >> S_MU) & M_MU)
62999 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
63000 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
63005 #define V_RS_FEC_SYMBLERR0_LO(x) ((x) << S_RS_FEC_SYMBLERR0_LO)
63006 #define F_RS_FEC_SYMBLERR0_LO    V_RS_FEC_SYMBLERR0_LO(1U)
63012 #define V_RS_FEC_SYMBLERR0_HI(x) ((x) << S_RS_FEC_SYMBLERR0_HI)
63013 #define F_RS_FEC_SYMBLERR0_HI    V_RS_FEC_SYMBLERR0_HI(1U)
63019 #define V_RS_FEC_SYMBLERR1_LO(x) ((x) << S_RS_FEC_SYMBLERR1_LO)
63020 #define F_RS_FEC_SYMBLERR1_LO    V_RS_FEC_SYMBLERR1_LO(1U)
63026 #define V_RS_FEC_SYMBLERR1_HI(x) ((x) << S_RS_FEC_SYMBLERR1_HI)
63027 #define F_RS_FEC_SYMBLERR1_HI    V_RS_FEC_SYMBLERR1_HI(1U)
63033 #define V_RS_FEC_SYMBLERR2_LO(x) ((x) << S_RS_FEC_SYMBLERR2_LO)
63034 #define F_RS_FEC_SYMBLERR2_LO    V_RS_FEC_SYMBLERR2_LO(1U)
63039 #define V_100GCR10(x) ((x) << S_100GCR10)
63040 #define F_100GCR10    V_100GCR10(1U)
63043 #define V_40GCR4(x) ((x) << S_40GCR4)
63044 #define F_40GCR4    V_40GCR4(1U)
63047 #define V_40GKR4(x) ((x) << S_40GKR4)
63048 #define F_40GKR4    V_40GKR4(1U)
63051 #define V_FEC(x) ((x) << S_FEC)
63052 #define F_FEC    V_FEC(1U)
63055 #define V_10GKR(x) ((x) << S_10GKR)
63056 #define F_10GKR    V_10GKR(1U)
63059 #define V_10GKX4(x) ((x) << S_10GKX4)
63060 #define F_10GKX4    V_10GKX4(1U)
63062 #define S_1GKX    1
63063 #define V_1GKX(x) ((x) << S_1GKX)
63064 #define F_1GKX    V_1GKX(1U)
63069 #define V_RS_FEC_SYMBLERR2_HI(x) ((x) << S_RS_FEC_SYMBLERR2_HI)
63070 #define F_RS_FEC_SYMBLERR2_HI    V_RS_FEC_SYMBLERR2_HI(1U)
63076 #define V_RS_FEC_SYMBLERR3_LO(x) ((x) << S_RS_FEC_SYMBLERR3_LO)
63077 #define F_RS_FEC_SYMBLERR3_LO    V_RS_FEC_SYMBLERR3_LO(1U)
63083 #define V_RS_FEC_SYMBLERR3_HI(x) ((x) << S_RS_FEC_SYMBLERR3_HI)
63084 #define F_RS_FEC_SYMBLERR3_HI    V_RS_FEC_SYMBLERR3_HI(1U)
63135 #define V_RS_FEC_ENABLED_STATUS(x) ((x) << S_RS_FEC_ENABLED_STATUS)
63136 #define F_RS_FEC_ENABLED_STATUS    V_RS_FEC_ENABLED_STATUS(1U)
63139 #define V_RS_FEC_ENABLE(x) ((x) << S_RS_FEC_ENABLE)
63140 #define F_RS_FEC_ENABLE    V_RS_FEC_ENABLE(1U)
63146 #define V_DESKEW_EMPTY(x) ((x) << S_DESKEW_EMPTY)
63147 #define G_DESKEW_EMPTY(x) (((x) >> S_DESKEW_EMPTY) & M_DESKEW_EMPTY)
63150 #define V_FEC_ALIGN_STATUS_LH(x) ((x) << S_FEC_ALIGN_STATUS_LH)
63151 #define F_FEC_ALIGN_STATUS_LH    V_FEC_ALIGN_STATUS_LH(1U)
63154 #define V_TX_DP_OVERFLOW(x) ((x) << S_TX_DP_OVERFLOW)
63155 #define F_TX_DP_OVERFLOW    V_TX_DP_OVERFLOW(1U)
63158 #define V_RX_DP_OVERFLOW(x) ((x) << S_RX_DP_OVERFLOW)
63159 #define F_RX_DP_OVERFLOW    V_RX_DP_OVERFLOW(1U)
63162 #define V_TX_DATAPATH_RESTART(x) ((x) << S_TX_DATAPATH_RESTART)
63163 #define F_TX_DATAPATH_RESTART    V_TX_DATAPATH_RESTART(1U)
63166 #define V_RX_DATAPATH_RESTART(x) ((x) << S_RX_DATAPATH_RESTART)
63167 #define F_RX_DATAPATH_RESTART    V_RX_DATAPATH_RESTART(1U)
63170 #define V_MARKER_CHECK_RESTART(x) ((x) << S_MARKER_CHECK_RESTART)
63171 #define F_MARKER_CHECK_RESTART    V_MARKER_CHECK_RESTART(1U)
63174 #define V_FEC_ALIGN_STATUS_LL(x) ((x) << S_FEC_ALIGN_STATUS_LL)
63175 #define F_FEC_ALIGN_STATUS_LL    V_FEC_ALIGN_STATUS_LL(1U)
63179 #define V_AMPS_LOCK(x) ((x) << S_AMPS_LOCK)
63180 #define G_AMPS_LOCK(x) (((x) >> S_AMPS_LOCK) & M_AMPS_LOCK)
63187 #define V_RS_FEC_VENDOR_REVISION(x) ((x) << S_RS_FEC_VENDOR_REVISION)
63188 #define G_RS_FEC_VENDOR_REVISION(x) (((x) >> S_RS_FEC_VENDOR_REVISION) & M_RS_FEC_VENDOR_REVISION)
63194 #define V_RS_FEC_VENDOR_TX_TEST_KEY(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_KEY)
63195 #define G_RS_FEC_VENDOR_TX_TEST_KEY(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_KEY) & M_RS_FEC_VENDOR_TX_TEST_KEY)
63201 #define V_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
63202 #define G_RS_FEC_VENDOR_TX_TEST_SYMBOLS(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_SYMBOLS) & M_RS_FEC_VENDOR_TX_TEST_SYMBOLS)
63208 #define V_RS_FEC_VENDOR_TX_TEST_PATTERN(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_PATTERN)
63209 #define G_RS_FEC_VENDOR_TX_TEST_PATTERN(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_PATTERN) & M_RS_FEC_VENDOR_TX_TEST_PATTERN)
63215 #define V_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) ((x) << S_RS_FEC_VENDOR_TX_TEST_TRIGGER)
63216 #define G_RS_FEC_VENDOR_TX_TEST_TRIGGER(x) (((x) >> S_RS_FEC_VENDOR_TX_TEST_TRIGGER) & M_RS_FEC_VENDOR_TX_TEST_TRIGGER)
63220 #define S_ENABLE_TR    1
63221 #define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
63222 #define F_ENABLE_TR    V_ENABLE_TR(1U)
63225 #define V_RESTART_TR(x) ((x) << S_RESTART_TR)
63226 #define F_RESTART_TR    V_RESTART_TR(1U)
63231 #define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
63232 #define F_FECKRSIGDET    V_FECKRSIGDET(1U)
63235 #define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
63236 #define F_TRAIN_FAIL    V_TRAIN_FAIL(1U)
63239 #define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
63240 #define F_STARTUP_STATUS    V_STARTUP_STATUS(1U)
63243 #define V_RX_STATUS(x) ((x) << S_RX_STATUS)
63244 #define F_RX_STATUS    V_RX_STATUS(1U)
63249 #define V_PRESET(x) ((x) << S_PRESET)
63250 #define F_PRESET    V_PRESET(1U)
63253 #define V_INITIALIZE(x) ((x) << S_INITIALIZE)
63254 #define F_INITIALIZE    V_INITIALIZE(1U)
63258 #define V_CP1_UPD(x) ((x) << S_CP1_UPD)
63259 #define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
63263 #define V_C0_UPD(x) ((x) << S_C0_UPD)
63264 #define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
63268 #define V_CN1_UPD(x) ((x) << S_CN1_UPD)
63269 #define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
63274 #define V_RX_READY(x) ((x) << S_RX_READY)
63275 #define F_RX_READY    V_RX_READY(1U)
63279 #define V_CP1_STAT(x) ((x) << S_CP1_STAT)
63280 #define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
63284 #define V_C0_STAT(x) ((x) << S_C0_STAT)
63285 #define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
63289 #define V_CN1_STAT(x) ((x) << S_CN1_STAT)
63290 #define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
63296 #define S_FEC_IND_ABILITY    1
63297 #define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
63298 #define F_FEC_IND_ABILITY    V_FEC_IND_ABILITY(1U)
63301 #define V_ABILITY(x) ((x) << S_ABILITY)
63302 #define F_ABILITY    V_ABILITY(1U)
63306 #define S_BASE_R_FEC_ERROR_INDICATION_ABILITY    1
63307 #define V_BASE_R_FEC_ERROR_INDICATION_ABILITY(x) ((x) << S_BASE_R_FEC_ERROR_INDICATION_ABILITY)
63308 #define F_BASE_R_FEC_ERROR_INDICATION_ABILITY    V_BASE_R_FEC_ERROR_INDICATION_ABILITY(1U)
63311 #define V_BASE_R_FEC_ABILITY(x) ((x) << S_BASE_R_FEC_ABILITY)
63312 #define F_BASE_R_FEC_ABILITY    V_BASE_R_FEC_ABILITY(1U)
63316 #define S_FEC_EN_ERR_IND    1
63317 #define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
63318 #define F_FEC_EN_ERR_IND    V_FEC_EN_ERR_IND(1U)
63321 #define V_FEC_EN(x) ((x) << S_FEC_EN)
63322 #define F_FEC_EN    V_FEC_EN(1U)
63326 #define S_FEC_LOCKED_100    1
63327 #define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
63328 #define F_FEC_LOCKED_100    V_FEC_LOCKED_100(1U)
63331 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
63332 #define F_FEC_LOCKED    V_FEC_LOCKED(1U)
63334 #define S_FEC_LOCKED0    1
63336 #define V_FEC_LOCKED0(x) ((x) << S_FEC_LOCKED0)
63337 #define G_FEC_LOCKED0(x) (((x) >> S_FEC_LOCKED0) & M_FEC_LOCKED0)
63343 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
63344 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
63351 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
63352 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
63359 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
63360 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
63366 #define V_FEC0_NCERR_CNT_0(x) ((x) << S_FEC0_NCERR_CNT_0)
63367 #define G_FEC0_NCERR_CNT_0(x) (((x) >> S_FEC0_NCERR_CNT_0) & M_FEC0_NCERR_CNT_0)
63373 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
63374 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
63380 #define V_FEC0_NCERR_CNT_1(x) ((x) << S_FEC0_NCERR_CNT_1)
63381 #define G_FEC0_NCERR_CNT_1(x) (((x) >> S_FEC0_NCERR_CNT_1) & M_FEC0_NCERR_CNT_1)
63402 #define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
63403 #define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
63407 #define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
63408 #define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
63412 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
63413 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
63417 #define V_T5_RXREQ_C3(x) ((x) << S_T5_RXREQ_C3)
63418 #define G_T5_RXREQ_C3(x) (((x) >> S_T5_RXREQ_C3) & M_T5_RXREQ_C3)
63423 #define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
63424 #define F_T5_AE0_RXSTAT_RDY    V_T5_AE0_RXSTAT_RDY(1U)
63428 #define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
63429 #define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
63433 #define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
63434 #define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
63438 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
63439 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
63442 #define V_T5_AE0_RXSTAT_LSNA(x) ((x) << S_T5_AE0_RXSTAT_LSNA)
63443 #define F_T5_AE0_RXSTAT_LSNA    V_T5_AE0_RXSTAT_LSNA(1U)
63446 #define V_T5_AE0_RXSTAT_FEC(x) ((x) << S_T5_AE0_RXSTAT_FEC)
63447 #define F_T5_AE0_RXSTAT_FEC    V_T5_AE0_RXSTAT_FEC(1U)
63450 #define V_T5_AE0_RXSTAT_TF(x) ((x) << S_T5_AE0_RXSTAT_TF)
63451 #define F_T5_AE0_RXSTAT_TF    V_T5_AE0_RXSTAT_TF(1U)
63455 #define V_T5_AE0_RXSTAT_C3(x) ((x) << S_T5_AE0_RXSTAT_C3)
63456 #define G_T5_AE0_RXSTAT_C3(x) (((x) >> S_T5_AE0_RXSTAT_C3) & M_T5_AE0_RXSTAT_C3)
63462 #define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
63463 #define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
63467 #define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
63468 #define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
63472 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
63473 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
63476 #define V_TXREQ_FEC(x) ((x) << S_TXREQ_FEC)
63477 #define F_TXREQ_FEC    V_TXREQ_FEC(1U)
63481 #define V_T5_TXREQ_C3(x) ((x) << S_T5_TXREQ_C3)
63482 #define G_T5_TXREQ_C3(x) (((x) >> S_T5_TXREQ_C3) & M_T5_TXREQ_C3)
63488 #define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
63489 #define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
63493 #define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
63494 #define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
63498 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
63499 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
63503 #define V_T5_TXSTAT_C3(x) ((x) << S_T5_TXSTAT_C3)
63504 #define G_T5_TXSTAT_C3(x) (((x) >> S_T5_TXSTAT_C3) & M_T5_TXSTAT_C3)
63509 #define V_AET_RSVD(x) ((x) << S_AET_RSVD)
63510 #define F_AET_RSVD    V_AET_RSVD(1U)
63513 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
63514 #define F_AET_ENABLE    V_AET_ENABLE(1U)
63518 #define V_SET_WAIT_TIMER(x) ((x) << S_SET_WAIT_TIMER)
63519 #define G_SET_WAIT_TIMER(x) (((x) >> S_SET_WAIT_TIMER) & M_SET_WAIT_TIMER)
63522 #define V_C2_C3_STATE_SEL(x) ((x) << S_C2_C3_STATE_SEL)
63523 #define F_C2_C3_STATE_SEL    V_C2_C3_STATE_SEL(1U)
63526 #define V_FFE4_EN(x) ((x) << S_FFE4_EN)
63527 #define F_FFE4_EN    V_FFE4_EN(1U)
63530 #define V_FEC_REQUEST(x) ((x) << S_FEC_REQUEST)
63531 #define F_FEC_REQUEST    V_FEC_REQUEST(1U)
63534 #define V_FEC_SUPPORTED(x) ((x) << S_FEC_SUPPORTED)
63535 #define F_FEC_SUPPORTED    V_FEC_SUPPORTED(1U)
63538 #define V_TX_FIXED(x) ((x) << S_TX_FIXED)
63539 #define F_TX_FIXED    V_TX_FIXED(1U)
63545 #define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
63546 #define F_CIN_ENABLE    V_CIN_ENABLE(1U)
63553 #define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
63554 #define F_T5_AE1_RXSTAT_RDY    V_T5_AE1_RXSTAT_RDY(1U)
63558 #define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
63559 #define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
63563 #define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
63564 #define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
63568 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
63569 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
63572 #define V_T5_AE1_RXSTAT_LSNA(x) ((x) << S_T5_AE1_RXSTAT_LSNA)
63573 #define F_T5_AE1_RXSTAT_LSNA    V_T5_AE1_RXSTAT_LSNA(1U)
63576 #define V_T5_AE1_RXSTAT_FEC(x) ((x) << S_T5_AE1_RXSTAT_FEC)
63577 #define F_T5_AE1_RXSTAT_FEC    V_T5_AE1_RXSTAT_FEC(1U)
63580 #define V_T5_AE1_RXSTAT_TF(x) ((x) << S_T5_AE1_RXSTAT_TF)
63581 #define F_T5_AE1_RXSTAT_TF    V_T5_AE1_RXSTAT_TF(1U)
63585 #define V_T5_AE1_RXSTAT_C3(x) ((x) << S_T5_AE1_RXSTAT_C3)
63586 #define G_T5_AE1_RXSTAT_C3(x) (((x) >> S_T5_AE1_RXSTAT_C3) & M_T5_AE1_RXSTAT_C3)
63598 #define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
63599 #define F_T5_AE2_RXSTAT_RDY    V_T5_AE2_RXSTAT_RDY(1U)
63603 #define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
63604 #define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
63608 #define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
63609 #define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
63613 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
63614 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
63617 #define V_T5_AE2_RXSTAT_LSNA(x) ((x) << S_T5_AE2_RXSTAT_LSNA)
63618 #define F_T5_AE2_RXSTAT_LSNA    V_T5_AE2_RXSTAT_LSNA(1U)
63621 #define V_T5_AE2_RXSTAT_FEC(x) ((x) << S_T5_AE2_RXSTAT_FEC)
63622 #define F_T5_AE2_RXSTAT_FEC    V_T5_AE2_RXSTAT_FEC(1U)
63625 #define V_T5_AE2_RXSTAT_TF(x) ((x) << S_T5_AE2_RXSTAT_TF)
63626 #define F_T5_AE2_RXSTAT_TF    V_T5_AE2_RXSTAT_TF(1U)
63630 #define V_T5_AE2_RXSTAT_C3(x) ((x) << S_T5_AE2_RXSTAT_C3)
63631 #define G_T5_AE2_RXSTAT_C3(x) (((x) >> S_T5_AE2_RXSTAT_C3) & M_T5_AE2_RXSTAT_C3)
63643 #define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
63644 #define F_T5_AE3_RXSTAT_RDY    V_T5_AE3_RXSTAT_RDY(1U)
63648 #define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
63649 #define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
63653 #define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
63654 #define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
63658 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
63659 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
63662 #define V_T5_AE3_RXSTAT_LSNA(x) ((x) << S_T5_AE3_RXSTAT_LSNA)
63663 #define F_T5_AE3_RXSTAT_LSNA    V_T5_AE3_RXSTAT_LSNA(1U)
63666 #define V_T5_AE3_RXSTAT_FEC(x) ((x) << S_T5_AE3_RXSTAT_FEC)
63667 #define F_T5_AE3_RXSTAT_FEC    V_T5_AE3_RXSTAT_FEC(1U)
63670 #define V_T5_AE3_RXSTAT_TF(x) ((x) << S_T5_AE3_RXSTAT_TF)
63671 #define F_T5_AE3_RXSTAT_TF    V_T5_AE3_RXSTAT_TF(1U)
63675 #define V_T5_AE3_RXSTAT_C3(x) ((x) << S_T5_AE3_RXSTAT_C3)
63676 #define G_T5_AE3_RXSTAT_C3(x) (((x) >> S_T5_AE3_RXSTAT_C3) & M_T5_AE3_RXSTAT_C3)
63703 #define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
63704 #define F_EN_HOLD_FAIL    V_EN_HOLD_FAIL(1U)
63708 #define V_INIT_METH(x) ((x) << S_INIT_METH)
63709 #define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
63713 #define V_CE_DECS(x) ((x) << S_CE_DECS)
63714 #define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
63717 #define V_EN_ZFE(x) ((x) << S_EN_ZFE)
63718 #define F_EN_ZFE    V_EN_ZFE(1U)
63721 #define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
63722 #define F_EN_GAIN_TOG    V_EN_GAIN_TOG(1U)
63725 #define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
63726 #define F_EN_AI_C1    V_EN_AI_C1(1U)
63729 #define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
63730 #define F_EN_MAX_ST    V_EN_MAX_ST(1U)
63733 #define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
63734 #define F_EN_H1T_EQ    V_EN_H1T_EQ(1U)
63738 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
63739 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
63743 #define V_T6_INIT_METH(x) ((x) << S_T6_INIT_METH)
63744 #define G_T6_INIT_METH(x) (((x) >> S_T6_INIT_METH) & M_T6_INIT_METH)
63748 #define V_INIT_CNT(x) ((x) << S_INIT_CNT)
63749 #define G_INIT_CNT(x) (((x) >> S_INIT_CNT) & M_INIT_CNT)
63752 #define V_EN_AI_N0(x) ((x) << S_EN_AI_N0)
63753 #define F_EN_AI_N0    V_EN_AI_N0(1U)
63759 #define V_GAIN_TH(x) ((x) << S_GAIN_TH)
63760 #define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
63763 #define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
63764 #define F_EN_SD_TH    V_EN_SD_TH(1U)
63767 #define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
63768 #define F_EN_AMIN_TH    V_EN_AMIN_TH(1U)
63772 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
63773 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
63776 #define V_FEC_CNV(x) ((x) << S_FEC_CNV)
63777 #define F_FEC_CNV    V_FEC_CNV(1U)
63780 #define V_EN_RETRY(x) ((x) << S_EN_RETRY)
63781 #define F_EN_RETRY    V_EN_RETRY(1U)
63785 #define V_DPC_METH(x) ((x) << S_DPC_METH)
63786 #define G_DPC_METH(x) (((x) >> S_DPC_METH) & M_DPC_METH)
63789 #define V_EN_P2(x) ((x) << S_EN_P2)
63790 #define F_EN_P2    V_EN_P2(1U)
63796 #define V_ACC_LIM(x) ((x) << S_ACC_LIM)
63797 #define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
63801 #define V_CNV_LIM(x) ((x) << S_CNV_LIM)
63802 #define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
63806 #define V_TOG_LIM(x) ((x) << S_TOG_LIM)
63807 #define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
63813 #define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
63814 #define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
63818 #define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
63819 #define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
63823 #define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
63824 #define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
63828 #define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
63829 #define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
63831 #define S_BOOT_DEC_C0    1
63832 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
63833 #define F_BOOT_DEC_C0    V_BOOT_DEC_C0(1U)
63837 #define V_BOOT_LUT5(x) ((x) << S_BOOT_LUT5)
63838 #define G_BOOT_LUT5(x) (((x) >> S_BOOT_LUT5) & M_BOOT_LUT5)
63844 #define V_AET_STAT(x) ((x) << S_AET_STAT)
63845 #define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
63849 #define V_NEU_STATE(x) ((x) << S_NEU_STATE)
63850 #define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
63854 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
63855 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
63859 #define V_CTRL_STAT(x) ((x) << S_CTRL_STAT)
63860 #define G_CTRL_STAT(x) (((x) >> S_CTRL_STAT) & M_CTRL_STAT)
63864 #define V_T6_NEU_STATE(x) ((x) << S_T6_NEU_STATE)
63865 #define G_T6_NEU_STATE(x) (((x) >> S_T6_NEU_STATE) & M_T6_NEU_STATE)
63869 #define V_T6_CTRL_STATE(x) ((x) << S_T6_CTRL_STATE)
63870 #define G_T6_CTRL_STATE(x) (((x) >> S_T6_CTRL_STATE) & M_T6_CTRL_STATE)
63876 #define V_FRAME_LOCK_CNT(x) ((x) << S_FRAME_LOCK_CNT)
63877 #define G_FRAME_LOCK_CNT(x) (((x) >> S_FRAME_LOCK_CNT) & M_FRAME_LOCK_CNT)
63883 #define V_DPC_TIME_LIM(x) ((x) << S_DPC_TIME_LIM)
63884 #define G_DPC_TIME_LIM(x) (((x) >> S_DPC_TIME_LIM) & M_DPC_TIME_LIM)
63912 #define V_BEAN_REM_FAULT(x) ((x) << S_BEAN_REM_FAULT)
63913 #define F_BEAN_REM_FAULT    V_BEAN_REM_FAULT(1U)
63920 #define V_BEAN_ABL_REM_FAULT(x) ((x) << S_BEAN_ABL_REM_FAULT)
63921 #define F_BEAN_ABL_REM_FAULT    V_BEAN_ABL_REM_FAULT(1U)
63935 #define V_100GCR4(x) ((x) << S_100GCR4)
63936 #define F_100GCR4    V_100GCR4(1U)
63939 #define V_100GKR4(x) ((x) << S_100GKR4)
63940 #define F_100GKR4    V_100GKR4(1U)
63943 #define V_100GKP4(x) ((x) << S_100GKP4)
63944 #define F_100GKP4    V_100GKP4(1U)
63949 #define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
63950 #define F_T5_TX_LINKEN    V_T5_TX_LINKEN(1U)
63953 #define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
63954 #define F_T5_TX_LINKRST    V_T5_TX_LINKRST(1U)
63957 #define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
63958 #define F_T5_TX_CFGWRT    V_T5_TX_CFGWRT(1U)
63962 #define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
63963 #define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
63966 #define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
63967 #define F_T5_TX_CFGEXT    V_T5_TX_CFGEXT(1U)
63970 #define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
63971 #define F_T5_TX_CFGACT    V_T5_TX_CFGACT(1U)
63974 #define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
63975 #define F_T5_TX_RSYNCC    V_T5_TX_RSYNCC(1U)
63979 #define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
63980 #define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
63983 #define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
63984 #define F_T5_TX_EXTC16    V_T5_TX_EXTC16(1U)
63987 #define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
63988 #define F_T5_TX_DCKSEL    V_T5_TX_DCKSEL(1U)
63991 #define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
63992 #define F_T5_TX_RXLOOP    V_T5_TX_RXLOOP(1U)
63995 #define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
63996 #define F_T5_TX_BWSEL    V_T5_TX_BWSEL(1U)
64000 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
64001 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
64004 #define V_T6_T5_TX_RXLOOP(x) ((x) << S_T6_T5_TX_RXLOOP)
64005 #define F_T6_T5_TX_RXLOOP    V_T6_T5_TX_RXLOOP(1U)
64008 #define V_T5_TX_ENFFE4(x) ((x) << S_T5_TX_ENFFE4)
64009 #define F_T5_TX_ENFFE4    V_T5_TX_ENFFE4(1U)
64013 #define V_T6_T5_TX_BWSEL(x) ((x) << S_T6_T5_TX_BWSEL)
64014 #define G_T6_T5_TX_BWSEL(x) (((x) >> S_T6_T5_TX_BWSEL) & M_T6_T5_TX_BWSEL)
64020 #define V_SPSEL(x) ((x) << S_SPSEL)
64021 #define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
64024 #define V_AFDWEN(x) ((x) << S_AFDWEN)
64025 #define F_AFDWEN    V_AFDWEN(1U)
64028 #define V_TPGMD(x) ((x) << S_TPGMD)
64029 #define F_TPGMD    V_TPGMD(1U)
64032 #define V_TC_FRCERR(x) ((x) << S_TC_FRCERR)
64033 #define F_TC_FRCERR    V_TC_FRCERR(1U)
64036 #define V_T6_ERROR(x) ((x) << S_T6_ERROR)
64037 #define F_T6_ERROR    V_T6_ERROR(1U)
64040 #define V_SYNC(x) ((x) << S_SYNC)
64041 #define F_SYNC    V_SYNC(1U)
64044 #define V_P7CHK(x) ((x) << S_P7CHK)
64045 #define F_P7CHK    V_P7CHK(1U)
64050 #define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
64051 #define F_ZCALOVRD    V_ZCALOVRD(1U)
64054 #define V_AMMODE(x) ((x) << S_AMMODE)
64055 #define F_AMMODE    V_AMMODE(1U)
64058 #define V_AEPOL(x) ((x) << S_AEPOL)
64059 #define F_AEPOL    V_AEPOL(1U)
64062 #define V_AESRC(x) ((x) << S_AESRC)
64063 #define F_AESRC    V_AESRC(1U)
64066 #define V_SASMODE(x) ((x) << S_SASMODE)
64067 #define F_SASMODE    V_SASMODE(1U)
64072 #define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
64073 #define F_T5DRVHIZ    V_T5DRVHIZ(1U)
64076 #define V_T5SASIMP(x) ((x) << S_T5SASIMP)
64077 #define F_T5SASIMP    V_T5SASIMP(1U)
64081 #define V_T5SLEW(x) ((x) << S_T5SLEW)
64082 #define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
64087 #define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
64088 #define F_T5C2BUFDCEN    V_T5C2BUFDCEN(1U)
64091 #define V_T5DCCEN(x) ((x) << S_T5DCCEN)
64092 #define F_T5DCCEN    V_T5DCCEN(1U)
64095 #define V_T5REGBYP(x) ((x) << S_T5REGBYP)
64096 #define F_T5REGBYP    V_T5REGBYP(1U)
64099 #define V_T5REGAEN(x) ((x) << S_T5REGAEN)
64100 #define F_T5REGAEN    V_T5REGAEN(1U)
64104 #define V_T5REGAMP(x) ((x) << S_T5REGAMP)
64105 #define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
64110 #define V_RSTEP(x) ((x) << S_RSTEP)
64111 #define F_RSTEP    V_RSTEP(1U)
64114 #define V_RLOCK(x) ((x) << S_RLOCK)
64115 #define F_RLOCK    V_RLOCK(1U)
64119 #define V_RPOS(x) ((x) << S_RPOS)
64120 #define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
64123 #define V_DCLKSAM(x) ((x) << S_DCLKSAM)
64124 #define F_DCLKSAM    V_DCLKSAM(1U)
64130 #define V_CALSSTN(x) ((x) << S_CALSSTN)
64131 #define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
64135 #define V_CALSSTP(x) ((x) << S_CALSSTP)
64136 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
64140 #define V_T6_CALSSTN(x) ((x) << S_T6_CALSSTN)
64141 #define G_T6_CALSSTN(x) (((x) >> S_T6_CALSSTN) & M_T6_CALSSTN)
64145 #define V_T6_CALSSTP(x) ((x) << S_T6_CALSSTP)
64146 #define G_T6_CALSSTP(x) (((x) >> S_T6_CALSSTP) & M_T6_CALSSTP)
64152 #define V_DRTOL(x) ((x) << S_DRTOL)
64153 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
64157 #define V_T6_DRTOL(x) ((x) << S_T6_DRTOL)
64158 #define G_T6_DRTOL(x) (((x) >> S_T6_DRTOL) & M_T6_DRTOL)
64164 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
64165 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
64169 #define V_T6_NXTT0(x) ((x) << S_T6_NXTT0)
64170 #define G_T6_NXTT0(x) (((x) >> S_T6_NXTT0) & M_T6_NXTT0)
64176 #define V_T5NXTT1(x) ((x) << S_T5NXTT1)
64177 #define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
64183 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
64184 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
64188 #define V_T6_NXTT2(x) ((x) << S_T6_NXTT2)
64189 #define G_T6_NXTT2(x) (((x) >> S_T6_NXTT2) & M_T6_NXTT2)
64195 #define V_NXTT3(x) ((x) << S_NXTT3)
64196 #define G_NXTT3(x) (((x) >> S_NXTT3) & M_NXTT3)
64202 #define V_T5TXPWR(x) ((x) << S_T5TXPWR)
64203 #define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
64209 #define V_NXTPOL(x) ((x) << S_NXTPOL)
64210 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
64214 #define V_T6_NXTPOL(x) ((x) << S_T6_NXTPOL)
64215 #define G_T6_NXTPOL(x) (((x) >> S_T6_NXTPOL) & M_T6_NXTPOL)
64220 #define V_CPREST(x) ((x) << S_CPREST)
64221 #define F_CPREST    V_CPREST(1U)
64224 #define V_CINIT(x) ((x) << S_CINIT)
64225 #define F_CINIT    V_CINIT(1U)
64229 #define V_SASCMD(x) ((x) << S_SASCMD)
64230 #define G_SASCMD(x) (((x) >> S_SASCMD) & M_SASCMD)
64234 #define V_T6_C0UPDT(x) ((x) << S_T6_C0UPDT)
64235 #define G_T6_C0UPDT(x) (((x) >> S_T6_C0UPDT) & M_T6_C0UPDT)
64239 #define V_C3UPDT(x) ((x) << S_C3UPDT)
64240 #define G_C3UPDT(x) (((x) >> S_C3UPDT) & M_C3UPDT)
64244 #define V_T6_C2UPDT(x) ((x) << S_T6_C2UPDT)
64245 #define G_T6_C2UPDT(x) (((x) >> S_T6_C2UPDT) & M_T6_C2UPDT)
64249 #define V_T6_C1UPDT(x) ((x) << S_T6_C1UPDT)
64250 #define G_T6_C1UPDT(x) (((x) >> S_T6_C1UPDT) & M_T6_C1UPDT)
64256 #define V_T6_C0STAT(x) ((x) << S_T6_C0STAT)
64257 #define G_T6_C0STAT(x) (((x) >> S_T6_C0STAT) & M_T6_C0STAT)
64261 #define V_C3STAT(x) ((x) << S_C3STAT)
64262 #define G_C3STAT(x) (((x) >> S_C3STAT) & M_C3STAT)
64266 #define V_T6_C2STAT(x) ((x) << S_T6_C2STAT)
64267 #define G_T6_C2STAT(x) (((x) >> S_T6_C2STAT) & M_T6_C2STAT)
64271 #define V_T6_C1STAT(x) ((x) << S_T6_C1STAT)
64272 #define G_T6_C1STAT(x) (((x) >> S_T6_C1STAT) & M_T6_C1STAT)
64279 #define V_AETAP0(x) ((x) << S_AETAP0)
64280 #define G_AETAP0(x) (((x) >> S_AETAP0) & M_AETAP0)
64286 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
64287 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
64293 #define V_AETAP1(x) ((x) << S_AETAP1)
64294 #define G_AETAP1(x) (((x) >> S_AETAP1) & M_AETAP1)
64300 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
64301 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
64307 #define V_AETAP2(x) ((x) << S_AETAP2)
64308 #define G_AETAP2(x) (((x) >> S_AETAP2) & M_AETAP2)
64314 #define V_AETAP3(x) ((x) << S_AETAP3)
64315 #define G_AETAP3(x) (((x) >> S_AETAP3) & M_AETAP3)
64321 #define V_ATUNEN(x) ((x) << S_ATUNEN)
64322 #define G_ATUNEN(x) (((x) >> S_ATUNEN) & M_ATUNEN)
64326 #define V_ATUNEP(x) ((x) << S_ATUNEP)
64327 #define G_ATUNEP(x) (((x) >> S_ATUNEP) & M_ATUNEP)
64332 #define V_DCCCOMPINV(x) ((x) << S_DCCCOMPINV)
64333 #define F_DCCCOMPINV    V_DCCCOMPINV(1U)
64340 #define V_AS4X7(x) ((x) << S_AS4X7)
64341 #define G_AS4X7(x) (((x) >> S_AS4X7) & M_AS4X7)
64345 #define V_AS4X6(x) ((x) << S_AS4X6)
64346 #define G_AS4X6(x) (((x) >> S_AS4X6) & M_AS4X6)
64350 #define V_AS4X5(x) ((x) << S_AS4X5)
64351 #define G_AS4X5(x) (((x) >> S_AS4X5) & M_AS4X5)
64355 #define V_AS4X4(x) ((x) << S_AS4X4)
64356 #define G_AS4X4(x) (((x) >> S_AS4X4) & M_AS4X4)
64360 #define V_AS4X3(x) ((x) << S_AS4X3)
64361 #define G_AS4X3(x) (((x) >> S_AS4X3) & M_AS4X3)
64365 #define V_AS4X2(x) ((x) << S_AS4X2)
64366 #define G_AS4X2(x) (((x) >> S_AS4X2) & M_AS4X2)
64370 #define V_AS4X1(x) ((x) << S_AS4X1)
64371 #define G_AS4X1(x) (((x) >> S_AS4X1) & M_AS4X1)
64375 #define V_AS4X0(x) ((x) << S_AS4X0)
64376 #define G_AS4X0(x) (((x) >> S_AS4X0) & M_AS4X0)
64382 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
64383 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
64389 #define V_AS2X3(x) ((x) << S_AS2X3)
64390 #define G_AS2X3(x) (((x) >> S_AS2X3) & M_AS2X3)
64394 #define V_AS2X2(x) ((x) << S_AS2X2)
64395 #define G_AS2X2(x) (((x) >> S_AS2X2) & M_AS2X2)
64399 #define V_AS2X1(x) ((x) << S_AS2X1)
64400 #define G_AS2X1(x) (((x) >> S_AS2X1) & M_AS2X1)
64404 #define V_AS2X0(x) ((x) << S_AS2X0)
64405 #define G_AS2X0(x) (((x) >> S_AS2X0) & M_AS2X0)
64412 #define V_AS1X7(x) ((x) << S_AS1X7)
64413 #define G_AS1X7(x) (((x) >> S_AS1X7) & M_AS1X7)
64417 #define V_AS1X6(x) ((x) << S_AS1X6)
64418 #define G_AS1X6(x) (((x) >> S_AS1X6) & M_AS1X6)
64422 #define V_AS1X5(x) ((x) << S_AS1X5)
64423 #define G_AS1X5(x) (((x) >> S_AS1X5) & M_AS1X5)
64427 #define V_AS1X4(x) ((x) << S_AS1X4)
64428 #define G_AS1X4(x) (((x) >> S_AS1X4) & M_AS1X4)
64432 #define V_AS1X3(x) ((x) << S_AS1X3)
64433 #define G_AS1X3(x) (((x) >> S_AS1X3) & M_AS1X3)
64437 #define V_AS1X2(x) ((x) << S_AS1X2)
64438 #define G_AS1X2(x) (((x) >> S_AS1X2) & M_AS1X2)
64442 #define V_AS1X1(x) ((x) << S_AS1X1)
64443 #define G_AS1X1(x) (((x) >> S_AS1X1) & M_AS1X1)
64447 #define V_AS1X0(x) ((x) << S_AS1X0)
64448 #define G_AS1X0(x) (((x) >> S_AS1X0) & M_AS1X0)
64454 #define V_AT4X(x) ((x) << S_AT4X)
64455 #define G_AT4X(x) (((x) >> S_AT4X) & M_AT4X)
64461 #define V_MAINSC(x) ((x) << S_MAINSC)
64462 #define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
64466 #define V_POSTSC(x) ((x) << S_POSTSC)
64467 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
64473 #define V_AT2X(x) ((x) << S_AT2X)
64474 #define G_AT2X(x) (((x) >> S_AT2X) & M_AT2X)
64480 #define V_PRESC(x) ((x) << S_PRESC)
64481 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
64487 #define V_ATSIGN(x) ((x) << S_ATSIGN)
64488 #define G_ATSIGN(x) (((x) >> S_ATSIGN) & M_ATSIGN)
64493 #define S_T5XADDR    1
64495 #define V_T5XADDR(x) ((x) << S_T5XADDR)
64496 #define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
64499 #define V_T5XWR(x) ((x) << S_T5XWR)
64500 #define F_T5XWR    V_T5XWR(1U)
64502 #define S_T6_XADDR    1
64504 #define V_T6_XADDR(x) ((x) << S_T6_XADDR)
64505 #define G_T6_XADDR(x) (((x) >> S_T6_XADDR) & M_T6_XADDR)
64511 #define V_XDAT10(x) ((x) << S_XDAT10)
64512 #define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
64518 #define V_XDAT32(x) ((x) << S_XDAT32)
64519 #define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
64525 #define V_XDAT4(x) ((x) << S_XDAT4)
64526 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
64532 #define V_XDAT54(x) ((x) << S_XDAT54)
64533 #define G_XDAT54(x) (((x) >> S_XDAT54) & M_XDAT54)
64538 #define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
64539 #define F_DCCTIMEDOUT    V_DCCTIMEDOUT(1U)
64542 #define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
64543 #define F_DCCTIMEEN    V_DCCTIMEEN(1U)
64546 #define V_DCCLOCK(x) ((x) << S_DCCLOCK)
64547 #define F_DCCLOCK    V_DCCLOCK(1U)
64551 #define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
64552 #define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
64556 #define V_DCCSTEP(x) ((x) << S_DCCSTEP)
64557 #define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
64559 #define S_DCCASTEP    1
64561 #define V_DCCASTEP(x) ((x) << S_DCCASTEP)
64562 #define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
64565 #define V_DCCAEN(x) ((x) << S_DCCAEN)
64566 #define F_DCCAEN    V_DCCAEN(1U)
64572 #define V_XDAT76(x) ((x) << S_XDAT76)
64573 #define G_XDAT76(x) (((x) >> S_XDAT76) & M_XDAT76)
64578 #define V_DCCOUT(x) ((x) << S_DCCOUT)
64579 #define F_DCCOUT    V_DCCOUT(1U)
64582 #define V_DCCCLK(x) ((x) << S_DCCCLK)
64583 #define F_DCCCLK    V_DCCCLK(1U)
64586 #define V_DCCHOLD(x) ((x) << S_DCCHOLD)
64587 #define F_DCCHOLD    V_DCCHOLD(1U)
64591 #define V_DCCSIGN(x) ((x) << S_DCCSIGN)
64592 #define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
64594 #define S_DCCAMP    1
64596 #define V_DCCAMP(x) ((x) << S_DCCAMP)
64597 #define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
64600 #define V_DCCOEN(x) ((x) << S_DCCOEN)
64601 #define F_DCCOEN    V_DCCOEN(1U)
64607 #define V_DCCASIGN(x) ((x) << S_DCCASIGN)
64608 #define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
64612 #define V_DCCAAMP(x) ((x) << S_DCCAAMP)
64613 #define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
64619 #define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
64620 #define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
64625 #define V_LPIDCLK(x) ((x) << S_LPIDCLK)
64626 #define F_LPIDCLK    V_LPIDCLK(1U)
64630 #define V_LPITERM(x) ((x) << S_LPITERM)
64631 #define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
64635 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
64636 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
64642 #define V_T6_DCCTIMEEN(x) ((x) << S_T6_DCCTIMEEN)
64643 #define G_T6_DCCTIMEEN(x) (((x) >> S_T6_DCCTIMEEN) & M_T6_DCCTIMEEN)
64647 #define V_T6_DCCLOCK(x) ((x) << S_T6_DCCLOCK)
64648 #define G_T6_DCCLOCK(x) (((x) >> S_T6_DCCLOCK) & M_T6_DCCLOCK)
64652 #define V_T6_DCCOFFSET(x) ((x) << S_T6_DCCOFFSET)
64653 #define G_T6_DCCOFFSET(x) (((x) >> S_T6_DCCOFFSET) & M_T6_DCCOFFSET)
64657 #define V_TX_LINKA_DCCSTEP_CTL(x) ((x) << S_TX_LINKA_DCCSTEP_CTL)
64658 #define G_TX_LINKA_DCCSTEP_CTL(x) (((x) >> S_TX_LINKA_DCCSTEP_CTL) & M_TX_LINKA_DCCSTEP_CTL)
64667 #define V_OSIGN(x) ((x) << S_OSIGN)
64668 #define G_OSIGN(x) (((x) >> S_OSIGN) & M_OSIGN)
64674 #define V_OS4X7(x) ((x) << S_OS4X7)
64675 #define G_OS4X7(x) (((x) >> S_OS4X7) & M_OS4X7)
64679 #define V_OS4X6(x) ((x) << S_OS4X6)
64680 #define G_OS4X6(x) (((x) >> S_OS4X6) & M_OS4X6)
64684 #define V_OS4X5(x) ((x) << S_OS4X5)
64685 #define G_OS4X5(x) (((x) >> S_OS4X5) & M_OS4X5)
64689 #define V_OS4X4(x) ((x) << S_OS4X4)
64690 #define G_OS4X4(x) (((x) >> S_OS4X4) & M_OS4X4)
64694 #define V_OS4X3(x) ((x) << S_OS4X3)
64695 #define G_OS4X3(x) (((x) >> S_OS4X3) & M_OS4X3)
64699 #define V_OS4X2(x) ((x) << S_OS4X2)
64700 #define G_OS4X2(x) (((x) >> S_OS4X2) & M_OS4X2)
64704 #define V_OS4X1(x) ((x) << S_OS4X1)
64705 #define G_OS4X1(x) (((x) >> S_OS4X1) & M_OS4X1)
64709 #define V_OS4X0(x) ((x) << S_OS4X0)
64710 #define G_OS4X0(x) (((x) >> S_OS4X0) & M_OS4X0)
64716 #define V_OS2X3(x) ((x) << S_OS2X3)
64717 #define G_OS2X3(x) (((x) >> S_OS2X3) & M_OS2X3)
64721 #define V_OS2X2(x) ((x) << S_OS2X2)
64722 #define G_OS2X2(x) (((x) >> S_OS2X2) & M_OS2X2)
64726 #define V_OS2X1(x) ((x) << S_OS2X1)
64727 #define G_OS2X1(x) (((x) >> S_OS2X1) & M_OS2X1)
64731 #define V_OS2X0(x) ((x) << S_OS2X0)
64732 #define G_OS2X0(x) (((x) >> S_OS2X0) & M_OS2X0)
64738 #define V_OS1X7(x) ((x) << S_OS1X7)
64739 #define G_OS1X7(x) (((x) >> S_OS1X7) & M_OS1X7)
64743 #define V_OS1X6(x) ((x) << S_OS1X6)
64744 #define G_OS1X6(x) (((x) >> S_OS1X6) & M_OS1X6)
64748 #define V_OS1X5(x) ((x) << S_OS1X5)
64749 #define G_OS1X5(x) (((x) >> S_OS1X5) & M_OS1X5)
64753 #define V_OS1X4(x) ((x) << S_OS1X4)
64754 #define G_OS1X4(x) (((x) >> S_OS1X4) & M_OS1X4)
64758 #define V_OS1X3(x) ((x) << S_OS1X3)
64759 #define G_OS1X3(x) (((x) >> S_OS1X3) & M_OS1X3)
64763 #define V_OS1X2(x) ((x) << S_OS1X2)
64764 #define G_OS1X2(x) (((x) >> S_OS1X2) & M_OS1X2)
64768 #define V_OS1X1(x) ((x) << S_OS1X1)
64769 #define G_OS1X1(x) (((x) >> S_OS1X1) & M_OS1X1)
64773 #define V_OS1X0(x) ((x) << S_OS1X0)
64774 #define G_OS1X0(x) (((x) >> S_OS1X0) & M_OS1X0)
64780 #define V_OT4X(x) ((x) << S_OT4X)
64781 #define G_OT4X(x) (((x) >> S_OT4X) & M_OT4X)
64787 #define V_OT2X(x) ((x) << S_OT2X)
64788 #define G_OT2X(x) (((x) >> S_OT2X) & M_OT2X)
64794 #define V_OT1X(x) ((x) << S_OT1X)
64795 #define G_OT1X(x) (((x) >> S_OT1X) & M_OT1X)
64800 #define V_ERRORP(x) ((x) << S_ERRORP)
64801 #define F_ERRORP    V_ERRORP(1U)
64804 #define V_ERRORN(x) ((x) << S_ERRORN)
64805 #define F_ERRORN    V_ERRORN(1U)
64808 #define V_TESTENA(x) ((x) << S_TESTENA)
64809 #define F_TESTENA    V_TESTENA(1U)
64813 #define V_TUNEBIT(x) ((x) << S_TUNEBIT)
64814 #define G_TUNEBIT(x) (((x) >> S_TUNEBIT) & M_TUNEBIT)
64818 #define V_DATAPOS(x) ((x) << S_DATAPOS)
64819 #define G_DATAPOS(x) (((x) >> S_DATAPOS) & M_DATAPOS)
64823 #define V_SEGSEL(x) ((x) << S_SEGSEL)
64824 #define G_SEGSEL(x) (((x) >> S_SEGSEL) & M_SEGSEL)
64826 #define S_TAPSEL    1
64828 #define V_TAPSEL(x) ((x) << S_TAPSEL)
64829 #define G_TAPSEL(x) (((x) >> S_TAPSEL) & M_TAPSEL)
64832 #define V_DATASIGN(x) ((x) << S_DATASIGN)
64833 #define F_DATASIGN    V_DATASIGN(1U)
64838 #define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
64839 #define F_SDOVRDEN    V_SDOVRDEN(1U)
64843 #define V_SDOVRD(x) ((x) << S_SDOVRD)
64844 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
64848 #define V_T6_SDOVRD(x) ((x) << S_T6_SDOVRD)
64849 #define G_T6_SDOVRD(x) (((x) >> S_T6_SDOVRD) & M_T6_SDOVRD)
64853 #define S_SLEWCODE    1
64855 #define V_SLEWCODE(x) ((x) << S_SLEWCODE)
64856 #define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
64859 #define V_ASEGEN(x) ((x) << S_ASEGEN)
64860 #define F_ASEGEN    V_ASEGEN(1U)
64864 #define V_WCNT(x) ((x) << S_WCNT)
64865 #define G_WCNT(x) (((x) >> S_WCNT) & M_WCNT)
64870 #define V_AECMDVAL(x) ((x) << S_AECMDVAL)
64871 #define F_AECMDVAL    V_AECMDVAL(1U)
64875 #define V_AECMD1312(x) ((x) << S_AECMD1312)
64876 #define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
64880 #define V_AECMD70(x) ((x) << S_AECMD70)
64881 #define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
64887 #define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
64888 #define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
64892 #define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
64893 #define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
64896 #define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
64897 #define F_ANLGFLSH    V_ANLGFLSH(1U)
64900 #define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
64901 #define F_DCCTSTOUT    V_DCCTSTOUT(1U)
64904 #define V_BSOUT(x) ((x) << S_BSOUT)
64905 #define F_BSOUT    V_BSOUT(1U)
64908 #define V_BSIN(x) ((x) << S_BSIN)
64909 #define F_BSIN    V_BSIN(1U)
64913 #define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
64914 #define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
64917 #define V_JTAGTS(x) ((x) << S_JTAGTS)
64918 #define F_JTAGTS    V_JTAGTS(1U)
64920 #define S_TS    1
64921 #define V_TS(x) ((x) << S_TS)
64922 #define F_TS    V_TS(1U)
64925 #define V_OBS(x) ((x) << S_OBS)
64926 #define F_OBS    V_OBS(1U)
64929 #define V_T6_SDOVRDEN(x) ((x) << S_T6_SDOVRDEN)
64930 #define F_T6_SDOVRDEN    V_T6_SDOVRDEN(1U)
64933 #define V_BSOUTN(x) ((x) << S_BSOUTN)
64934 #define F_BSOUTN    V_BSOUTN(1U)
64937 #define V_BSOUTP(x) ((x) << S_BSOUTP)
64938 #define F_BSOUTP    V_BSOUTP(1U)
64992 #define V_TX_LINKB_DCCSTEP_CTL(x) ((x) << S_TX_LINKB_DCCSTEP_CTL)
64993 #define G_TX_LINKB_DCCSTEP_CTL(x) (((x) >> S_TX_LINKB_DCCSTEP_CTL) & M_TX_LINKB_DCCSTEP_CTL)
65013 #define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
65014 #define F_T5_RX_LINKEN    V_T5_RX_LINKEN(1U)
65017 #define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
65018 #define F_T5_RX_LINKRST    V_T5_RX_LINKRST(1U)
65021 #define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
65022 #define F_T5_RX_CFGWRT    V_T5_RX_CFGWRT(1U)
65026 #define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
65027 #define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
65030 #define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
65031 #define F_T5_RX_CFGEXT    V_T5_RX_CFGEXT(1U)
65034 #define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
65035 #define F_T5_RX_CFGACT    V_T5_RX_CFGACT(1U)
65038 #define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
65039 #define F_T5_RX_AUXCLK    V_T5_RX_AUXCLK(1U)
65043 #define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
65044 #define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
65048 #define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
65049 #define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
65053 #define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
65054 #define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
65058 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
65059 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
65062 #define V_T5_RX_MODE8023AZ(x) ((x) << S_T5_RX_MODE8023AZ)
65063 #define F_T5_RX_MODE8023AZ    V_T5_RX_MODE8023AZ(1U)
65068 #define V_FERRST(x) ((x) << S_FERRST)
65069 #define F_FERRST    V_FERRST(1U)
65072 #define V_ERRST(x) ((x) << S_ERRST)
65073 #define F_ERRST    V_ERRST(1U)
65076 #define V_SYNCST(x) ((x) << S_SYNCST)
65077 #define F_SYNCST    V_SYNCST(1U)
65080 #define V_WRPSM(x) ((x) << S_WRPSM)
65081 #define F_WRPSM    V_WRPSM(1U)
65084 #define V_WPLPEN(x) ((x) << S_WPLPEN)
65085 #define F_WPLPEN    V_WPLPEN(1U)
65088 #define V_WRPMD(x) ((x) << S_WRPMD)
65089 #define F_WRPMD    V_WRPMD(1U)
65093 #define V_PATSEL(x) ((x) << S_PATSEL)
65094 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
65097 #define V_APLYDCD(x) ((x) << S_APLYDCD)
65098 #define F_APLYDCD    V_APLYDCD(1U)
65102 #define V_PPOL(x) ((x) << S_PPOL)
65103 #define G_PPOL(x) (((x) >> S_PPOL) & M_PPOL)
65107 #define V_PCLKSEL(x) ((x) << S_PCLKSEL)
65108 #define G_PCLKSEL(x) (((x) >> S_PCLKSEL) & M_PCLKSEL)
65113 #define V_RSTUCK(x) ((x) << S_RSTUCK)
65114 #define F_RSTUCK    V_RSTUCK(1U)
65117 #define V_FRZFW(x) ((x) << S_FRZFW)
65118 #define F_FRZFW    V_FRZFW(1U)
65120 #define S_RSTFW    1
65121 #define V_RSTFW(x) ((x) << S_RSTFW)
65122 #define F_RSTFW    V_RSTFW(1U)
65125 #define V_SSCEN(x) ((x) << S_SSCEN)
65126 #define F_SSCEN    V_SSCEN(1U)
65132 #define V_H1ANOFST(x) ((x) << S_H1ANOFST)
65133 #define G_H1ANOFST(x) (((x) >> S_H1ANOFST) & M_H1ANOFST)
65137 #define V_T6_TMSCAL(x) ((x) << S_T6_TMSCAL)
65138 #define G_T6_TMSCAL(x) (((x) >> S_T6_TMSCAL) & M_T6_TMSCAL)
65141 #define V_T6_APADJ(x) ((x) << S_T6_APADJ)
65142 #define F_T6_APADJ    V_T6_APADJ(1U)
65145 #define V_T6_RSEL(x) ((x) << S_T6_RSEL)
65146 #define F_T6_RSEL    V_T6_RSEL(1U)
65150 #define V_T6_PHOFFS(x) ((x) << S_T6_PHOFFS)
65151 #define G_T6_PHOFFS(x) (((x) >> S_T6_PHOFFS) & M_T6_PHOFFS)
65157 #define V_ROT00(x) ((x) << S_ROT00)
65158 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
65162 #define V_ROTA(x) ((x) << S_ROTA)
65163 #define G_ROTA(x) (((x) >> S_ROTA) & M_ROTA)
65167 #define V_ROTD(x) ((x) << S_ROTD)
65168 #define G_ROTD(x) (((x) >> S_ROTD) & M_ROTD)
65174 #define V_FREQFW(x) ((x) << S_FREQFW)
65175 #define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
65178 #define V_FWSNAP(x) ((x) << S_FWSNAP)
65179 #define F_FWSNAP    V_FWSNAP(1U)
65183 #define V_ROTE(x) ((x) << S_ROTE)
65184 #define G_ROTE(x) (((x) >> S_ROTE) & M_ROTE)
65190 #define V_RAOFFF(x) ((x) << S_RAOFFF)
65191 #define G_RAOFFF(x) (((x) >> S_RAOFFF) & M_RAOFFF)
65195 #define V_RAOFF(x) ((x) << S_RAOFF)
65196 #define G_RAOFF(x) (((x) >> S_RAOFF) & M_RAOFF)
65202 #define V_RBOOFF(x) ((x) << S_RBOOFF)
65203 #define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
65207 #define V_RBEOFF(x) ((x) << S_RBEOFF)
65208 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
65214 #define V_T6_SPIFMT(x) ((x) << S_T6_SPIFMT)
65215 #define G_T6_SPIFMT(x) (((x) >> S_T6_SPIFMT) & M_T6_SPIFMT)
65221 #define V_T5BYTE1(x) ((x) << S_T5BYTE1)
65222 #define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
65226 #define V_T5BYTE0(x) ((x) << S_T5BYTE0)
65227 #define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
65233 #define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
65234 #define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
65237 #define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
65238 #define F_T5_RX_ADCORR    V_T5_RX_ADCORR(1U)
65241 #define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
65242 #define F_T5_RX_TRAINEN    V_T5_RX_TRAINEN(1U)
65246 #define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
65247 #define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
65251 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
65252 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
65255 #define V_REQWOV(x) ((x) << S_REQWOV)
65256 #define F_REQWOV    V_REQWOV(1U)
65260 #define V_RASEL(x) ((x) << S_RASEL)
65261 #define G_RASEL(x) (((x) >> S_RASEL) & M_RASEL)
65266 #define V_T6_WRAPSEL(x) ((x) << S_T6_WRAPSEL)
65267 #define F_T6_WRAPSEL    V_T6_WRAPSEL(1U)
65270 #define V_ACTL(x) ((x) << S_ACTL)
65271 #define F_ACTL    V_ACTL(1U)
65275 #define V_T6_PEAK(x) ((x) << S_T6_PEAK)
65276 #define G_T6_PEAK(x) (((x) >> S_T6_PEAK) & M_T6_PEAK)
65281 #define V_T5SHORTV(x) ((x) << S_T5SHORTV)
65282 #define F_T5SHORTV    V_T5SHORTV(1U)
65286 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
65287 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
65290 #define V_FVOFFSKP(x) ((x) << S_FVOFFSKP)
65291 #define F_FVOFFSKP    V_FVOFFSKP(1U)
65294 #define V_FGAINCHK(x) ((x) << S_FGAINCHK)
65295 #define F_FGAINCHK    V_FGAINCHK(1U)
65298 #define V_FH1ACAL(x) ((x) << S_FH1ACAL)
65299 #define F_FH1ACAL    V_FH1ACAL(1U)
65303 #define V_FH1AFLTR(x) ((x) << S_FH1AFLTR)
65304 #define G_FH1AFLTR(x) (((x) >> S_FH1AFLTR) & M_FH1AFLTR)
65308 #define V_WGAIN(x) ((x) << S_WGAIN)
65309 #define G_WGAIN(x) (((x) >> S_WGAIN) & M_WGAIN)
65312 #define V_GAIN_STAT(x) ((x) << S_GAIN_STAT)
65313 #define F_GAIN_STAT    V_GAIN_STAT(1U)
65317 #define V_T6_T5VGAIN(x) ((x) << S_T6_T5VGAIN)
65318 #define G_T6_T5VGAIN(x) (((x) >> S_T6_T5VGAIN) & M_T6_T5VGAIN)
65325 #define V_IQSEP(x) ((x) << S_IQSEP)
65326 #define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
65330 #define V_DUTYQ(x) ((x) << S_DUTYQ)
65331 #define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
65335 #define V_DUTYI(x) ((x) << S_DUTYI)
65336 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
65342 #define V_PMCFG(x) ((x) << S_PMCFG)
65343 #define G_PMCFG(x) (((x) >> S_PMCFG) & M_PMCFG)
65347 #define V_PMOFFTIME(x) ((x) << S_PMOFFTIME)
65348 #define G_PMOFFTIME(x) (((x) >> S_PMOFFTIME) & M_PMOFFTIME)
65353 #define V_SELI(x) ((x) << S_SELI)
65354 #define F_SELI    V_SELI(1U)
65358 #define V_SERVREF(x) ((x) << S_SERVREF)
65359 #define G_SERVREF(x) (((x) >> S_SERVREF) & M_SERVREF)
65363 #define V_IQAMP(x) ((x) << S_IQAMP)
65364 #define G_IQAMP(x) (((x) >> S_IQAMP) & M_IQAMP)
65370 #define V_DTHR(x) ((x) << S_DTHR)
65371 #define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
65375 #define V_SNUL(x) ((x) << S_SNUL)
65376 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
65382 #define V_SAVEADAC(x) ((x) << S_SAVEADAC)
65383 #define F_SAVEADAC    V_SAVEADAC(1U)
65386 #define V_LOAD2(x) ((x) << S_LOAD2)
65387 #define F_LOAD2    V_LOAD2(1U)
65390 #define V_LOAD1(x) ((x) << S_LOAD1)
65391 #define F_LOAD1    V_LOAD1(1U)
65394 #define V_WRTACC2(x) ((x) << S_WRTACC2)
65395 #define F_WRTACC2    V_WRTACC2(1U)
65398 #define V_WRTACC1(x) ((x) << S_WRTACC1)
65399 #define F_WRTACC1    V_WRTACC1(1U)
65402 #define V_SELAPAN(x) ((x) << S_SELAPAN)
65403 #define F_SELAPAN    V_SELAPAN(1U)
65407 #define V_DASEL(x) ((x) << S_DASEL)
65408 #define G_DASEL(x) (((x) >> S_DASEL) & M_DASEL)
65416 #define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
65417 #define F_ADSN_READWRITE    V_ADSN_READWRITE(1U)
65420 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
65421 #define F_ADSN_READONLY    V_ADSN_READONLY(1U)
65425 #define V_ADAC2(x) ((x) << S_ADAC2)
65426 #define G_ADAC2(x) (((x) >> S_ADAC2) & M_ADAC2)
65430 #define V_ADAC1(x) ((x) << S_ADAC1)
65431 #define G_ADAC1(x) (((x) >> S_ADAC1) & M_ADAC1)
65436 #define V_FACCPLDYN(x) ((x) << S_FACCPLDYN)
65437 #define F_FACCPLDYN    V_FACCPLDYN(1U)
65441 #define V_ACCPLGAIN(x) ((x) << S_ACCPLGAIN)
65442 #define G_ACCPLGAIN(x) (((x) >> S_ACCPLGAIN) & M_ACCPLGAIN)
65446 #define V_ACCPLREF(x) ((x) << S_ACCPLREF)
65447 #define G_ACCPLREF(x) (((x) >> S_ACCPLREF) & M_ACCPLREF)
65451 #define V_ACCPLSTEP(x) ((x) << S_ACCPLSTEP)
65452 #define G_ACCPLSTEP(x) (((x) >> S_ACCPLSTEP) & M_ACCPLSTEP)
65454 #define S_ACCPLASTEP    1
65456 #define V_ACCPLASTEP(x) ((x) << S_ACCPLASTEP)
65457 #define G_ACCPLASTEP(x) (((x) >> S_ACCPLASTEP) & M_ACCPLASTEP)
65460 #define V_FACCPL(x) ((x) << S_FACCPL)
65461 #define F_FACCPL    V_FACCPL(1U)
65466 #define V_ACCPLMEANS(x) ((x) << S_ACCPLMEANS)
65467 #define F_ACCPLMEANS    V_ACCPLMEANS(1U)
65470 #define V_CDROVREN(x) ((x) << S_CDROVREN)
65471 #define F_CDROVREN    V_CDROVREN(1U)
65475 #define V_ACCPLBIAS(x) ((x) << S_ACCPLBIAS)
65476 #define G_ACCPLBIAS(x) (((x) >> S_ACCPLBIAS) & M_ACCPLBIAS)
65482 #define V_H1O2(x) ((x) << S_H1O2)
65483 #define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
65487 #define V_H1E2(x) ((x) << S_H1E2)
65488 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
65494 #define V_H123CH(x) ((x) << S_H123CH)
65495 #define G_H123CH(x) (((x) >> S_H123CH) & M_H123CH)
65501 #define V_H1O3(x) ((x) << S_H1O3)
65502 #define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
65506 #define V_H1E3(x) ((x) << S_H1E3)
65507 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
65513 #define V_H1OX(x) ((x) << S_H1OX)
65514 #define G_H1OX(x) (((x) >> S_H1OX) & M_H1OX)
65518 #define V_H1EX(x) ((x) << S_H1EX)
65519 #define G_H1EX(x) (((x) >> S_H1EX) & M_H1EX)
65525 #define V_H1O4(x) ((x) << S_H1O4)
65526 #define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
65530 #define V_H1E4(x) ((x) << S_H1E4)
65531 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
65536 #define V_PILOCK(x) ((x) << S_PILOCK)
65537 #define F_PILOCK    V_PILOCK(1U)
65541 #define V_UNPKPKA(x) ((x) << S_UNPKPKA)
65542 #define G_UNPKPKA(x) (((x) >> S_UNPKPKA) & M_UNPKPKA)
65546 #define V_UNPKVGA(x) ((x) << S_UNPKVGA)
65547 #define G_UNPKVGA(x) (((x) >> S_UNPKVGA) & M_UNPKVGA)
65552 #define V_OVRAC(x) ((x) << S_OVRAC)
65553 #define F_OVRAC    V_OVRAC(1U)
65556 #define V_OVRPK(x) ((x) << S_OVRPK)
65557 #define F_OVRPK    V_OVRPK(1U)
65561 #define V_OVRTAILS(x) ((x) << S_OVRTAILS)
65562 #define G_OVRTAILS(x) (((x) >> S_OVRTAILS) & M_OVRTAILS)
65566 #define V_OVRTAILV(x) ((x) << S_OVRTAILV)
65567 #define G_OVRTAILV(x) (((x) >> S_OVRTAILV) & M_OVRTAILV)
65570 #define V_OVRCAP(x) ((x) << S_OVRCAP)
65571 #define F_OVRCAP    V_OVRCAP(1U)
65574 #define V_OVRDCDPRE(x) ((x) << S_OVRDCDPRE)
65575 #define F_OVRDCDPRE    V_OVRDCDPRE(1U)
65578 #define V_OVRDCDPST(x) ((x) << S_OVRDCDPST)
65579 #define F_OVRDCDPST    V_OVRDCDPST(1U)
65582 #define V_DCVSCTMODE(x) ((x) << S_DCVSCTMODE)
65583 #define F_DCVSCTMODE    V_DCVSCTMODE(1U)
65587 #define V_CDRANLGSW(x) ((x) << S_CDRANLGSW)
65588 #define G_CDRANLGSW(x) (((x) >> S_CDRANLGSW) & M_CDRANLGSW)
65594 #define V_PFLAG(x) ((x) << S_PFLAG)
65595 #define G_PFLAG(x) (((x) >> S_PFLAG) & M_PFLAG)
65600 #define V_DPCMD(x) ((x) << S_DPCMD)
65601 #define F_DPCMD    V_DPCMD(1U)
65604 #define V_DACCLIP(x) ((x) << S_DACCLIP)
65605 #define F_DACCLIP    V_DACCLIP(1U)
65608 #define V_DPCFRZ(x) ((x) << S_DPCFRZ)
65609 #define F_DPCFRZ    V_DPCFRZ(1U)
65612 #define V_DPCLKNQ(x) ((x) << S_DPCLKNQ)
65613 #define F_DPCLKNQ    V_DPCLKNQ(1U)
65616 #define V_DPCWDFE(x) ((x) << S_DPCWDFE)
65617 #define F_DPCWDFE    V_DPCWDFE(1U)
65620 #define V_DPCWPK(x) ((x) << S_DPCWPK)
65621 #define F_DPCWPK    V_DPCWPK(1U)
65626 #define V_VIEWSCAN(x) ((x) << S_VIEWSCAN)
65627 #define F_VIEWSCAN    V_VIEWSCAN(1U)
65631 #define V_T6_ODEC(x) ((x) << S_T6_ODEC)
65632 #define G_T6_ODEC(x) (((x) >> S_T6_ODEC) & M_T6_ODEC)
65637 #define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
65638 #define F_T5BER6VAL    V_T5BER6VAL(1U)
65641 #define V_T5BER6(x) ((x) << S_T5BER6)
65642 #define F_T5BER6    V_T5BER6(1U)
65645 #define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
65646 #define F_T5BER3VAL    V_T5BER3VAL(1U)
65649 #define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
65650 #define F_T5TOOFAST    V_T5TOOFAST(1U)
65653 #define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
65654 #define F_T5DPCCMP    V_T5DPCCMP(1U)
65657 #define V_T5DACCMP(x) ((x) << S_T5DACCMP)
65658 #define F_T5DACCMP    V_T5DACCMP(1U)
65661 #define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
65662 #define F_T5DDCCMP    V_T5DDCCMP(1U)
65665 #define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
65666 #define F_T5AERRFLG    V_T5AERRFLG(1U)
65669 #define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
65670 #define F_T5WERRFLG    V_T5WERRFLG(1U)
65673 #define V_T5TRCMP(x) ((x) << S_T5TRCMP)
65674 #define F_T5TRCMP    V_T5TRCMP(1U)
65677 #define V_T5VLCKF(x) ((x) << S_T5VLCKF)
65678 #define F_T5VLCKF    V_T5VLCKF(1U)
65681 #define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
65682 #define F_T5ROCCMP    V_T5ROCCMP(1U)
65684 #define S_T5DQCCCMP    1
65685 #define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
65686 #define F_T5DQCCCMP    V_T5DQCCCMP(1U)
65689 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
65690 #define F_T5OCCMP    V_T5OCCMP(1U)
65693 #define V_RX_LINKA_ACCCMP_RIS(x) ((x) << S_RX_LINKA_ACCCMP_RIS)
65694 #define F_RX_LINKA_ACCCMP_RIS    V_RX_LINKA_ACCCMP_RIS(1U)
65697 #define V_DCCCMP(x) ((x) << S_DCCCMP)
65698 #define F_DCCCMP    V_DCCCMP(1U)
65700 #define S_T5IQCMP    1
65701 #define V_T5IQCMP(x) ((x) << S_T5IQCMP)
65702 #define F_T5IQCMP    V_T5IQCMP(1U)
65706 #define S_FLOFF    1
65707 #define V_FLOFF(x) ((x) << S_FLOFF)
65708 #define F_FLOFF    V_FLOFF(1U)
65713 #define V_H25SPC(x) ((x) << S_H25SPC)
65714 #define F_H25SPC    V_H25SPC(1U)
65717 #define V_FTOOFAST(x) ((x) << S_FTOOFAST)
65718 #define F_FTOOFAST    V_FTOOFAST(1U)
65721 #define V_FINTTRIM(x) ((x) << S_FINTTRIM)
65722 #define F_FINTTRIM    V_FINTTRIM(1U)
65725 #define V_FDINV(x) ((x) << S_FDINV)
65726 #define F_FDINV    V_FDINV(1U)
65729 #define V_FHGS(x) ((x) << S_FHGS)
65730 #define F_FHGS    V_FHGS(1U)
65733 #define V_FH6H12(x) ((x) << S_FH6H12)
65734 #define F_FH6H12    V_FH6H12(1U)
65737 #define V_FH1CAL(x) ((x) << S_FH1CAL)
65738 #define F_FH1CAL    V_FH1CAL(1U)
65741 #define V_FINTCAL(x) ((x) << S_FINTCAL)
65742 #define F_FINTCAL    V_FINTCAL(1U)
65744 #define S_FDCA    1
65745 #define V_FDCA(x) ((x) << S_FDCA)
65746 #define F_FDCA    V_FDCA(1U)
65749 #define V_FDQCC(x) ((x) << S_FDQCC)
65750 #define F_FDQCC    V_FDQCC(1U)
65753 #define V_FDCCAL(x) ((x) << S_FDCCAL)
65754 #define F_FDCCAL    V_FDCCAL(1U)
65757 #define V_FROTCAL(x) ((x) << S_FROTCAL)
65758 #define F_FROTCAL    V_FROTCAL(1U)
65761 #define V_FIQAMP(x) ((x) << S_FIQAMP)
65762 #define F_FIQAMP    V_FIQAMP(1U)
65765 #define V_FRPTCALF(x) ((x) << S_FRPTCALF)
65766 #define F_FRPTCALF    V_FRPTCALF(1U)
65769 #define V_FINTCALGS(x) ((x) << S_FINTCALGS)
65770 #define F_FINTCALGS    V_FINTCALGS(1U)
65773 #define V_FDCC(x) ((x) << S_FDCC)
65774 #define F_FDCC    V_FDCC(1U)
65777 #define V_FDCD(x) ((x) << S_FDCD)
65778 #define F_FDCD    V_FDCD(1U)
65780 #define S_FINTRCALDYN    1
65781 #define V_FINTRCALDYN(x) ((x) << S_FINTRCALDYN)
65782 #define F_FINTRCALDYN    V_FINTRCALDYN(1U)
65785 #define V_FQCC(x) ((x) << S_FQCC)
65786 #define F_FQCC    V_FQCC(1U)
65791 #define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
65792 #define F_LOFE2S_READWRITE    V_LOFE2S_READWRITE(1U)
65796 #define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
65797 #define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
65801 #define V_LOFE2(x) ((x) << S_LOFE2)
65802 #define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
65805 #define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
65806 #define F_LOFE1S_READWRITE    V_LOFE1S_READWRITE(1U)
65809 #define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
65810 #define F_LOFE1S_READONLY    V_LOFE1S_READONLY(1U)
65814 #define V_LOFE1(x) ((x) << S_LOFE1)
65815 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
65820 #define V_QCCIND(x) ((x) << S_QCCIND)
65821 #define F_QCCIND    V_QCCIND(1U)
65825 #define V_DCDIND(x) ((x) << S_DCDIND)
65826 #define G_DCDIND(x) (((x) >> S_DCDIND) & M_DCDIND)
65830 #define V_DCCIND(x) ((x) << S_DCCIND)
65831 #define G_DCCIND(x) (((x) >> S_DCCIND) & M_DCCIND)
65834 #define V_CFSEL(x) ((x) << S_CFSEL)
65835 #define F_CFSEL    V_CFSEL(1U)
65839 #define V_LOFCH(x) ((x) << S_LOFCH)
65840 #define G_LOFCH(x) (((x) >> S_LOFCH) & M_LOFCH)
65845 #define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
65846 #define F_LOFO2S_READWRITE    V_LOFO2S_READWRITE(1U)
65849 #define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
65850 #define F_LOFO2S_READONLY    V_LOFO2S_READONLY(1U)
65854 #define V_LOFO2(x) ((x) << S_LOFO2)
65855 #define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
65858 #define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
65859 #define F_LOFO1S_READWRITE    V_LOFO1S_READWRITE(1U)
65862 #define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
65863 #define F_LOFO1S_READONLY    V_LOFO1S_READONLY(1U)
65867 #define V_LOFO1(x) ((x) << S_LOFO1)
65868 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
65874 #define V_LOFU(x) ((x) << S_LOFU)
65875 #define G_LOFU(x) (((x) >> S_LOFU) & M_LOFU)
65879 #define V_LOFL(x) ((x) << S_LOFL)
65880 #define G_LOFL(x) (((x) >> S_LOFL) & M_LOFL)
65885 #define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
65886 #define F_LOFE4S_READWRITE    V_LOFE4S_READWRITE(1U)
65889 #define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
65890 #define F_LOFE4S_READONLY    V_LOFE4S_READONLY(1U)
65894 #define V_LOFE(x) ((x) << S_LOFE)
65895 #define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
65898 #define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
65899 #define F_LOFE3S_READWRITE    V_LOFE3S_READWRITE(1U)
65902 #define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
65903 #define F_LOFE3S_READONLY    V_LOFE3S_READONLY(1U)
65907 #define V_LOFE3(x) ((x) << S_LOFE3)
65908 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
65913 #define V_HBISTMAN(x) ((x) << S_HBISTMAN)
65914 #define F_HBISTMAN    V_HBISTMAN(1U)
65917 #define V_HBISTRES(x) ((x) << S_HBISTRES)
65918 #define F_HBISTRES    V_HBISTRES(1U)
65922 #define V_HBISTSP(x) ((x) << S_HBISTSP)
65923 #define G_HBISTSP(x) (((x) >> S_HBISTSP) & M_HBISTSP)
65926 #define V_HBISTEN(x) ((x) << S_HBISTEN)
65927 #define F_HBISTEN    V_HBISTEN(1U)
65930 #define V_HBISTRST(x) ((x) << S_HBISTRST)
65931 #define F_HBISTRST    V_HBISTRST(1U)
65934 #define V_HCOMP(x) ((x) << S_HCOMP)
65935 #define F_HCOMP    V_HCOMP(1U)
65938 #define V_HPASS(x) ((x) << S_HPASS)
65939 #define F_HPASS    V_HPASS(1U)
65943 #define V_HSEL(x) ((x) << S_HSEL)
65944 #define G_HSEL(x) (((x) >> S_HSEL) & M_HSEL)
65949 #define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
65950 #define F_LOFO4S_READWRITE    V_LOFO4S_READWRITE(1U)
65953 #define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
65954 #define F_LOFO4S_READONLY    V_LOFO4S_READONLY(1U)
65958 #define V_LOFO4(x) ((x) << S_LOFO4)
65959 #define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
65962 #define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
65963 #define F_LOFO3S_READWRITE    V_LOFO3S_READWRITE(1U)
65966 #define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
65967 #define F_LOFO3S_READONLY    V_LOFO3S_READONLY(1U)
65971 #define V_LOFO3(x) ((x) << S_LOFO3)
65972 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
65977 #define V_RX_LINKA_ACCCMP_BIST(x) ((x) << S_RX_LINKA_ACCCMP_BIST)
65978 #define F_RX_LINKA_ACCCMP_BIST    V_RX_LINKA_ACCCMP_BIST(1U)
65981 #define V_ACCEN(x) ((x) << S_ACCEN)
65982 #define F_ACCEN    V_ACCEN(1U)
65985 #define V_ACCRST(x) ((x) << S_ACCRST)
65986 #define F_ACCRST    V_ACCRST(1U)
65990 #define V_ACCIND(x) ((x) << S_ACCIND)
65991 #define G_ACCIND(x) (((x) >> S_ACCIND) & M_ACCIND)
65995 #define V_ACCRD(x) ((x) << S_ACCRD)
65996 #define G_ACCRD(x) (((x) >> S_ACCRD) & M_ACCRD)
66001 #define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
66002 #define F_T5E1SN_READWRITE    V_T5E1SN_READWRITE(1U)
66005 #define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
66006 #define F_T5E1SN_READONLY    V_T5E1SN_READONLY(1U)
66010 #define V_T5E1AMP(x) ((x) << S_T5E1AMP)
66011 #define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
66014 #define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
66015 #define F_T5E0SN_READWRITE    V_T5E0SN_READWRITE(1U)
66018 #define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
66019 #define F_T5E0SN_READONLY    V_T5E0SN_READONLY(1U)
66023 #define V_T5E0AMP(x) ((x) << S_T5E0AMP)
66024 #define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
66029 #define V_T5LFREG(x) ((x) << S_T5LFREG)
66030 #define F_T5LFREG    V_T5LFREG(1U)
66033 #define V_T5LFRC(x) ((x) << S_T5LFRC)
66034 #define F_T5LFRC    V_T5LFRC(1U)
66038 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
66039 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
66044 #define V_LFREG(x) ((x) << S_LFREG)
66045 #define F_LFREG    V_LFREG(1U)
66048 #define V_LFRC(x) ((x) << S_LFRC)
66049 #define F_LFRC    V_LFRC(1U)
66052 #define V_LGIDLE(x) ((x) << S_LGIDLE)
66053 #define F_LGIDLE    V_LGIDLE(1U)
66057 #define V_LFTGT(x) ((x) << S_LFTGT)
66058 #define G_LFTGT(x) (((x) >> S_LFTGT) & M_LFTGT)
66061 #define V_LGTGT(x) ((x) << S_LGTGT)
66062 #define F_LGTGT    V_LGTGT(1U)
66065 #define V_LRDY(x) ((x) << S_LRDY)
66066 #define F_LRDY    V_LRDY(1U)
66069 #define V_LIDLE(x) ((x) << S_LIDLE)
66070 #define F_LIDLE    V_LIDLE(1U)
66074 #define V_LCURR(x) ((x) << S_LCURR)
66075 #define G_LCURR(x) (((x) >> S_LCURR) & M_LCURR)
66080 #define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
66081 #define F_OFFSN_READWRITE    V_OFFSN_READWRITE(1U)
66084 #define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
66085 #define F_OFFSN_READONLY    V_OFFSN_READONLY(1U)
66089 #define V_OFFAMP(x) ((x) << S_OFFAMP)
66090 #define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
66093 #define V_SDACDC(x) ((x) << S_SDACDC)
66094 #define F_SDACDC    V_SDACDC(1U)
66098 #define V_OFFSN(x) ((x) << S_OFFSN)
66099 #define G_OFFSN(x) (((x) >> S_OFFSN) & M_OFFSN)
66104 #define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
66105 #define F_T5_RX_SETHDIS    V_T5_RX_SETHDIS(1U)
66108 #define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
66109 #define F_T5_RX_PDTERM    V_T5_RX_PDTERM(1U)
66112 #define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
66113 #define F_T5_RX_BYPASS    V_T5_RX_BYPASS(1U)
66116 #define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
66117 #define F_T5_RX_LPFEN    V_T5_RX_LPFEN(1U)
66120 #define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
66121 #define F_T5_RX_VGABOD    V_T5_RX_VGABOD(1U)
66124 #define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
66125 #define F_T5_RX_VTBYP    V_T5_RX_VTBYP(1U)
66129 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
66130 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
66133 #define V_RX_OVRSUMPD(x) ((x) << S_RX_OVRSUMPD)
66134 #define F_RX_OVRSUMPD    V_RX_OVRSUMPD(1U)
66137 #define V_RX_OVRKBPD(x) ((x) << S_RX_OVRKBPD)
66138 #define F_RX_OVRKBPD    V_RX_OVRKBPD(1U)
66141 #define V_RX_OVRDIVPD(x) ((x) << S_RX_OVRDIVPD)
66142 #define F_RX_OVRDIVPD    V_RX_OVRDIVPD(1U)
66145 #define V_RX_OFFVGADIS(x) ((x) << S_RX_OFFVGADIS)
66146 #define F_RX_OFFVGADIS    V_RX_OFFVGADIS(1U)
66149 #define V_RX_OFFACDIS(x) ((x) << S_RX_OFFACDIS)
66150 #define F_RX_OFFACDIS    V_RX_OFFACDIS(1U)
66153 #define V_RX_VTERM(x) ((x) << S_RX_VTERM)
66154 #define F_RX_VTERM    V_RX_VTERM(1U)
66157 #define V_RX_DISSPY2D(x) ((x) << S_RX_DISSPY2D)
66158 #define F_RX_DISSPY2D    V_RX_DISSPY2D(1U)
66161 #define V_RX_OBSOVEN(x) ((x) << S_RX_OBSOVEN)
66162 #define F_RX_OBSOVEN    V_RX_OBSOVEN(1U)
66166 #define V_RX_LINKANLGSW(x) ((x) << S_RX_LINKANLGSW)
66167 #define G_RX_LINKANLGSW(x) (((x) >> S_RX_LINKANLGSW) & M_RX_LINKANLGSW)
66173 #define V_ISTRIMS(x) ((x) << S_ISTRIMS)
66174 #define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
66178 #define V_ISTRIM(x) ((x) << S_ISTRIM)
66179 #define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
66182 #define V_HALF1(x) ((x) << S_HALF1)
66183 #define F_HALF1    V_HALF1(1U)
66186 #define V_HALF2(x) ((x) << S_HALF2)
66187 #define F_HALF2    V_HALF2(1U)
66191 #define V_INTDAC(x) ((x) << S_INTDAC)
66192 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
66196 #define V_INTDACEGS(x) ((x) << S_INTDACEGS)
66197 #define G_INTDACEGS(x) (((x) >> S_INTDACEGS) & M_INTDACEGS)
66201 #define V_INTDACE(x) ((x) << S_INTDACE)
66202 #define G_INTDACE(x) (((x) >> S_INTDACE) & M_INTDACE)
66206 #define V_INTDACGS(x) ((x) << S_INTDACGS)
66207 #define G_INTDACGS(x) (((x) >> S_INTDACGS) & M_INTDACGS)
66213 #define V_MINWDTH(x) ((x) << S_MINWDTH)
66214 #define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
66220 #define V_T5SMQM(x) ((x) << S_T5SMQM)
66221 #define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
66225 #define V_T5SMQ(x) ((x) << S_T5SMQ)
66226 #define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
66230 #define V_T5EMMD(x) ((x) << S_T5EMMD)
66231 #define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
66234 #define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
66235 #define F_T5EMBRDY    V_T5EMBRDY(1U)
66237 #define S_T5EMBUMP    1
66238 #define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
66239 #define F_T5EMBUMP    V_T5EMBUMP(1U)
66242 #define V_T5EMEN(x) ((x) << S_T5EMEN)
66243 #define F_T5EMEN    V_T5EMEN(1U)
66247 #define V_SMQM(x) ((x) << S_SMQM)
66248 #define G_SMQM(x) (((x) >> S_SMQM) & M_SMQM)
66252 #define V_SMQ(x) ((x) << S_SMQ)
66253 #define G_SMQ(x) (((x) >> S_SMQ) & M_SMQ)
66257 #define V_T6_EMMD(x) ((x) << S_T6_EMMD)
66258 #define G_T6_EMMD(x) (((x) >> S_T6_EMMD) & M_T6_EMMD)
66261 #define V_T6_EMBRDY(x) ((x) << S_T6_EMBRDY)
66262 #define F_T6_EMBRDY    V_T6_EMBRDY(1U)
66264 #define S_T6_EMBUMP    1
66265 #define V_T6_EMBUMP(x) ((x) << S_T6_EMBUMP)
66266 #define F_T6_EMBUMP    V_T6_EMBUMP(1U)
66271 #define V_EMF8(x) ((x) << S_EMF8)
66272 #define F_EMF8    V_EMF8(1U)
66276 #define V_EMCNT(x) ((x) << S_EMCNT)
66277 #define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
66280 #define V_EMOFLO(x) ((x) << S_EMOFLO)
66281 #define F_EMOFLO    V_EMOFLO(1U)
66283 #define S_EMCRST    1
66284 #define V_EMCRST(x) ((x) << S_EMCRST)
66285 #define F_EMCRST    V_EMCRST(1U)
66288 #define V_EMCEN(x) ((x) << S_EMCEN)
66289 #define F_EMCEN    V_EMCEN(1U)
66292 #define V_EMSF(x) ((x) << S_EMSF)
66293 #define F_EMSF    V_EMSF(1U)
66296 #define V_EMDATA59(x) ((x) << S_EMDATA59)
66297 #define F_EMDATA59    V_EMDATA59(1U)
66302 #define V_SM2RDY(x) ((x) << S_SM2RDY)
66303 #define F_SM2RDY    V_SM2RDY(1U)
66306 #define V_SM2RST(x) ((x) << S_SM2RST)
66307 #define F_SM2RST    V_SM2RST(1U)
66311 #define V_APDF(x) ((x) << S_APDF)
66312 #define G_APDF(x) (((x) >> S_APDF) & M_APDF)
66318 #define V_SM0LEN(x) ((x) << S_SM0LEN)
66319 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
66324 #define V_FTIMEOUT(x) ((x) << S_FTIMEOUT)
66325 #define F_FTIMEOUT    V_FTIMEOUT(1U)
66328 #define V_FROTCAL4(x) ((x) << S_FROTCAL4)
66329 #define F_FROTCAL4    V_FROTCAL4(1U)
66332 #define V_FDCD2(x) ((x) << S_FDCD2)
66333 #define F_FDCD2    V_FDCD2(1U)
66336 #define V_FPRBSPOLTOG(x) ((x) << S_FPRBSPOLTOG)
66337 #define F_FPRBSPOLTOG    V_FPRBSPOLTOG(1U)
66340 #define V_FPRBSOFF2(x) ((x) << S_FPRBSOFF2)
66341 #define F_FPRBSOFF2    V_FPRBSOFF2(1U)
66344 #define V_FDDCAL2(x) ((x) << S_FDDCAL2)
66345 #define F_FDDCAL2    V_FDDCAL2(1U)
66348 #define V_FDDCFLTR(x) ((x) << S_FDDCFLTR)
66349 #define F_FDDCFLTR    V_FDDCFLTR(1U)
66352 #define V_FDAC6(x) ((x) << S_FDAC6)
66353 #define F_FDAC6    V_FDAC6(1U)
66356 #define V_FDDC5(x) ((x) << S_FDDC5)
66357 #define F_FDDC5    V_FDDC5(1U)
66360 #define V_FDDC3456(x) ((x) << S_FDDC3456)
66361 #define F_FDDC3456    V_FDDC3456(1U)
66364 #define V_FSPY2DATA(x) ((x) << S_FSPY2DATA)
66365 #define F_FSPY2DATA    V_FSPY2DATA(1U)
66368 #define V_FPHSLOCK(x) ((x) << S_FPHSLOCK)
66369 #define F_FPHSLOCK    V_FPHSLOCK(1U)
66372 #define V_FCLKALGN(x) ((x) << S_FCLKALGN)
66373 #define F_FCLKALGN    V_FCLKALGN(1U)
66376 #define V_FCLKALDYN(x) ((x) << S_FCLKALDYN)
66377 #define F_FCLKALDYN    V_FCLKALDYN(1U)
66379 #define S_FDFE    1
66380 #define V_FDFE(x) ((x) << S_FDFE)
66381 #define F_FDFE    V_FDFE(1U)
66384 #define V_FPRBSOFF(x) ((x) << S_FPRBSOFF)
66385 #define F_FPRBSOFF    V_FPRBSOFF(1U)
66389 #define S_H_EN    1
66391 #define V_H_EN(x) ((x) << S_H_EN)
66392 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
66398 #define V_RX_LINKA_INDEX_DFE_TC(x) ((x) << S_RX_LINKA_INDEX_DFE_TC)
66399 #define G_RX_LINKA_INDEX_DFE_TC(x) (((x) >> S_RX_LINKA_INDEX_DFE_TC) & M_RX_LINKA_INDEX_DFE_TC)
66406 #define V_RX_LINKA_INDEX_DFE_TAP(x) ((x) << S_RX_LINKA_INDEX_DFE_TAP)
66407 #define G_RX_LINKA_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKA_INDEX_DFE_TAP) & M_RX_LINKA_INDEX_DFE_TAP)
66412 #define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
66413 #define F_H2OSN_READWRITE    V_H2OSN_READWRITE(1U)
66416 #define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
66417 #define F_H2OSN_READONLY    V_H2OSN_READONLY(1U)
66420 #define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
66421 #define F_H2ESN_READWRITE    V_H2ESN_READWRITE(1U)
66424 #define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
66425 #define F_H2ESN_READONLY    V_H2ESN_READONLY(1U)
66430 #define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
66431 #define F_H3OSN_READWRITE    V_H3OSN_READWRITE(1U)
66434 #define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
66435 #define F_H3OSN_READONLY    V_H3OSN_READONLY(1U)
66438 #define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
66439 #define F_H3ESN_READWRITE    V_H3ESN_READWRITE(1U)
66442 #define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
66443 #define F_H3ESN_READONLY    V_H3ESN_READONLY(1U)
66449 #define V_H4OGS(x) ((x) << S_H4OGS)
66450 #define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
66453 #define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
66454 #define F_H4OSN_READWRITE    V_H4OSN_READWRITE(1U)
66457 #define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
66458 #define F_H4OSN_READONLY    V_H4OSN_READONLY(1U)
66462 #define V_H4EGS(x) ((x) << S_H4EGS)
66463 #define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
66466 #define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
66467 #define F_H4ESN_READWRITE    V_H4ESN_READWRITE(1U)
66470 #define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
66471 #define F_H4ESN_READONLY    V_H4ESN_READONLY(1U)
66477 #define V_H5OGS(x) ((x) << S_H5OGS)
66478 #define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
66481 #define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
66482 #define F_H5OSN_READWRITE    V_H5OSN_READWRITE(1U)
66485 #define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
66486 #define F_H5OSN_READONLY    V_H5OSN_READONLY(1U)
66490 #define V_H5EGS(x) ((x) << S_H5EGS)
66491 #define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
66494 #define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
66495 #define F_H5ESN_READWRITE    V_H5ESN_READWRITE(1U)
66498 #define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
66499 #define F_H5ESN_READONLY    V_H5ESN_READONLY(1U)
66505 #define V_H7GS(x) ((x) << S_H7GS)
66506 #define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
66509 #define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
66510 #define F_H7SN_READWRITE    V_H7SN_READWRITE(1U)
66513 #define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
66514 #define F_H7SN_READONLY    V_H7SN_READONLY(1U)
66518 #define V_H7MAG(x) ((x) << S_H7MAG)
66519 #define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
66523 #define V_H6GS(x) ((x) << S_H6GS)
66524 #define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
66527 #define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
66528 #define F_H6SN_READWRITE    V_H6SN_READWRITE(1U)
66531 #define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
66532 #define F_H6SN_READONLY    V_H6SN_READONLY(1U)
66536 #define V_H6MAG(x) ((x) << S_H6MAG)
66537 #define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
66543 #define V_H9GS(x) ((x) << S_H9GS)
66544 #define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
66547 #define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
66548 #define F_H9SN_READWRITE    V_H9SN_READWRITE(1U)
66551 #define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
66552 #define F_H9SN_READONLY    V_H9SN_READONLY(1U)
66556 #define V_H9MAG(x) ((x) << S_H9MAG)
66557 #define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
66561 #define V_H8GS(x) ((x) << S_H8GS)
66562 #define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
66565 #define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
66566 #define F_H8SN_READWRITE    V_H8SN_READWRITE(1U)
66569 #define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
66570 #define F_H8SN_READONLY    V_H8SN_READONLY(1U)
66574 #define V_H8MAG(x) ((x) << S_H8MAG)
66575 #define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
66581 #define V_H11GS(x) ((x) << S_H11GS)
66582 #define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
66585 #define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
66586 #define F_H11SN_READWRITE    V_H11SN_READWRITE(1U)
66589 #define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
66590 #define F_H11SN_READONLY    V_H11SN_READONLY(1U)
66594 #define V_H11MAG(x) ((x) << S_H11MAG)
66595 #define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
66599 #define V_H10GS(x) ((x) << S_H10GS)
66600 #define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
66603 #define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
66604 #define F_H10SN_READWRITE    V_H10SN_READWRITE(1U)
66607 #define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
66608 #define F_H10SN_READONLY    V_H10SN_READONLY(1U)
66612 #define V_H10MAG(x) ((x) << S_H10MAG)
66613 #define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
66619 #define V_H12GS(x) ((x) << S_H12GS)
66620 #define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
66623 #define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
66624 #define F_H12SN_READWRITE    V_H12SN_READWRITE(1U)
66627 #define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
66628 #define F_H12SN_READONLY    V_H12SN_READONLY(1U)
66632 #define V_H12MAG(x) ((x) << S_H12MAG)
66633 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
66638 #define V_STNDBYSTAT(x) ((x) << S_STNDBYSTAT)
66639 #define F_STNDBYSTAT    V_STNDBYSTAT(1U)
66642 #define V_CALSDONE(x) ((x) << S_CALSDONE)
66643 #define F_CALSDONE    V_CALSDONE(1U)
66646 #define V_ACISRCCMP(x) ((x) << S_ACISRCCMP)
66647 #define F_ACISRCCMP    V_ACISRCCMP(1U)
66650 #define V_PRBSOFFCMP(x) ((x) << S_PRBSOFFCMP)
66651 #define F_PRBSOFFCMP    V_PRBSOFFCMP(1U)
66654 #define V_CLKALGNCMP(x) ((x) << S_CLKALGNCMP)
66655 #define F_CLKALGNCMP    V_CLKALGNCMP(1U)
66658 #define V_ROTFCMP(x) ((x) << S_ROTFCMP)
66659 #define F_ROTFCMP    V_ROTFCMP(1U)
66661 #define S_DCDCMP    1
66662 #define V_DCDCMP(x) ((x) << S_DCDCMP)
66663 #define F_DCDCMP    V_DCDCMP(1U)
66666 #define V_QCCCMP(x) ((x) << S_QCCCMP)
66667 #define F_QCCCMP    V_QCCCMP(1U)
66672 #define V_FCSADJ(x) ((x) << S_FCSADJ)
66673 #define F_FCSADJ    V_FCSADJ(1U)
66677 #define V_CSIND(x) ((x) << S_CSIND)
66678 #define G_CSIND(x) (((x) >> S_CSIND) & M_CSIND)
66682 #define V_CSVAL(x) ((x) << S_CSVAL)
66683 #define G_CSVAL(x) (((x) >> S_CSVAL) & M_CSVAL)
66688 #define V_DCDTMDOUT(x) ((x) << S_DCDTMDOUT)
66689 #define F_DCDTMDOUT    V_DCDTMDOUT(1U)
66692 #define V_DCDTOEN(x) ((x) << S_DCDTOEN)
66693 #define F_DCDTOEN    V_DCDTOEN(1U)
66696 #define V_DCDLOCK(x) ((x) << S_DCDLOCK)
66697 #define F_DCDLOCK    V_DCDLOCK(1U)
66701 #define V_DCDSTEP(x) ((x) << S_DCDSTEP)
66702 #define G_DCDSTEP(x) (((x) >> S_DCDSTEP) & M_DCDSTEP)
66705 #define V_DCDALTWPDIS(x) ((x) << S_DCDALTWPDIS)
66706 #define F_DCDALTWPDIS    V_DCDALTWPDIS(1U)
66709 #define V_DCDOVRDEN(x) ((x) << S_DCDOVRDEN)
66710 #define F_DCDOVRDEN    V_DCDOVRDEN(1U)
66713 #define V_DCCAOVRDEN(x) ((x) << S_DCCAOVRDEN)
66714 #define F_DCCAOVRDEN    V_DCCAOVRDEN(1U)
66718 #define V_DCDSIGN(x) ((x) << S_DCDSIGN)
66719 #define G_DCDSIGN(x) (((x) >> S_DCDSIGN) & M_DCDSIGN)
66723 #define V_DCDAMP(x) ((x) << S_DCDAMP)
66724 #define G_DCDAMP(x) (((x) >> S_DCDAMP) & M_DCDAMP)
66730 #define V_PRBSMODE(x) ((x) << S_PRBSMODE)
66731 #define G_PRBSMODE(x) (((x) >> S_PRBSMODE) & M_PRBSMODE)
66735 #define V_RX_LINKA_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKA_DCCSTEP_RXCTL)
66736 #define G_RX_LINKA_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKA_DCCSTEP_RXCTL) & M_RX_LINKA_DCCSTEP_RXCTL)
66739 #define V_DCCOVRDEN(x) ((x) << S_DCCOVRDEN)
66740 #define F_DCCOVRDEN    V_DCCOVRDEN(1U)
66743 #define V_RX_LINKA_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKA_DCCLOCK_RXCTL)
66744 #define F_RX_LINKA_DCCLOCK_RXCTL    V_RX_LINKA_DCCLOCK_RXCTL(1U)
66749 #define V_DCCQCCMODE(x) ((x) << S_DCCQCCMODE)
66750 #define F_DCCQCCMODE    V_DCCQCCMODE(1U)
66753 #define V_DCCQCCDYN(x) ((x) << S_DCCQCCDYN)
66754 #define F_DCCQCCDYN    V_DCCQCCDYN(1U)
66757 #define V_DCCQCCHOLD(x) ((x) << S_DCCQCCHOLD)
66758 #define F_DCCQCCHOLD    V_DCCQCCHOLD(1U)
66762 #define V_QCCSTEP(x) ((x) << S_QCCSTEP)
66763 #define G_QCCSTEP(x) (((x) >> S_QCCSTEP) & M_QCCSTEP)
66766 #define V_QCCOVRDEN(x) ((x) << S_QCCOVRDEN)
66767 #define F_QCCOVRDEN    V_QCCOVRDEN(1U)
66770 #define V_QCCLOCK(x) ((x) << S_QCCLOCK)
66771 #define F_QCCLOCK    V_QCCLOCK(1U)
66775 #define V_QCCSIGN(x) ((x) << S_QCCSIGN)
66776 #define G_QCCSIGN(x) (((x) >> S_QCCSIGN) & M_QCCSIGN)
66780 #define V_QCDAMP(x) ((x) << S_QCDAMP)
66781 #define G_QCDAMP(x) (((x) >> S_QCDAMP) & M_QCDAMP)
66786 #define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
66787 #define F_DFEDACLSSD    V_DFEDACLSSD(1U)
66790 #define V_SDLSSD(x) ((x) << S_SDLSSD)
66791 #define F_SDLSSD    V_SDLSSD(1U)
66794 #define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
66795 #define F_DFEOBSBIAS    V_DFEOBSBIAS(1U)
66798 #define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
66799 #define F_GBOFSTLSSD    V_GBOFSTLSSD(1U)
66802 #define V_RXDOBS(x) ((x) << S_RXDOBS)
66803 #define F_RXDOBS    V_RXDOBS(1U)
66805 #define S_ACJZPT    1
66806 #define V_ACJZPT(x) ((x) << S_ACJZPT)
66807 #define F_ACJZPT    V_ACJZPT(1U)
66810 #define V_ACJZNT(x) ((x) << S_ACJZNT)
66811 #define F_ACJZNT    V_ACJZNT(1U)
66816 #define V_TSTCMP(x) ((x) << S_TSTCMP)
66817 #define F_TSTCMP    V_TSTCMP(1U)
66822 #define V_PHSLOCK(x) ((x) << S_PHSLOCK)
66823 #define F_PHSLOCK    V_PHSLOCK(1U)
66826 #define V_TESTMODE(x) ((x) << S_TESTMODE)
66827 #define F_TESTMODE    V_TESTMODE(1U)
66830 #define V_CALMODE(x) ((x) << S_CALMODE)
66831 #define F_CALMODE    V_CALMODE(1U)
66834 #define V_AMPSEL(x) ((x) << S_AMPSEL)
66835 #define F_AMPSEL    V_AMPSEL(1U)
66838 #define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
66839 #define F_WHICHNRZ    V_WHICHNRZ(1U)
66842 #define V_BANKA(x) ((x) << S_BANKA)
66843 #define F_BANKA    V_BANKA(1U)
66846 #define V_BANKB(x) ((x) << S_BANKB)
66847 #define F_BANKB    V_BANKB(1U)
66850 #define V_ACJPDP(x) ((x) << S_ACJPDP)
66851 #define F_ACJPDP    V_ACJPDP(1U)
66854 #define V_ACJPDN(x) ((x) << S_ACJPDN)
66855 #define F_ACJPDN    V_ACJPDN(1U)
66857 #define S_LSSDT    1
66858 #define V_LSSDT(x) ((x) << S_LSSDT)
66859 #define F_LSSDT    V_LSSDT(1U)
66862 #define V_MTHOLD(x) ((x) << S_MTHOLD)
66863 #define F_MTHOLD    V_MTHOLD(1U)
66866 #define V_CALMODEEDGE(x) ((x) << S_CALMODEEDGE)
66867 #define F_CALMODEEDGE    V_CALMODEEDGE(1U)
66870 #define V_TESTCAP(x) ((x) << S_TESTCAP)
66871 #define F_TESTCAP    V_TESTCAP(1U)
66874 #define V_SNAPEN(x) ((x) << S_SNAPEN)
66875 #define F_SNAPEN    V_SNAPEN(1U)
66878 #define V_ASYNCDIR(x) ((x) << S_ASYNCDIR)
66879 #define F_ASYNCDIR    V_ASYNCDIR(1U)
66920 #define V_RX_LINKB_ACCCMP_RIS(x) ((x) << S_RX_LINKB_ACCCMP_RIS)
66921 #define F_RX_LINKB_ACCCMP_RIS    V_RX_LINKB_ACCCMP_RIS(1U)
66935 #define V_RX_LINKB_ACCCMP_BIST(x) ((x) << S_RX_LINKB_ACCCMP_BIST)
66936 #define F_RX_LINKB_ACCCMP_BIST    V_RX_LINKB_ACCCMP_BIST(1U)
66955 #define V_RX_LINKB_INDEX_DFE_TC(x) ((x) << S_RX_LINKB_INDEX_DFE_TC)
66956 #define G_RX_LINKB_INDEX_DFE_TC(x) (((x) >> S_RX_LINKB_INDEX_DFE_TC) & M_RX_LINKB_INDEX_DFE_TC)
66963 #define V_RX_LINKB_INDEX_DFE_TAP(x) ((x) << S_RX_LINKB_INDEX_DFE_TAP)
66964 #define G_RX_LINKB_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKB_INDEX_DFE_TAP) & M_RX_LINKB_INDEX_DFE_TAP)
66981 #define V_RX_LINKB_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKB_DCCSTEP_RXCTL)
66982 #define G_RX_LINKB_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKB_DCCSTEP_RXCTL) & M_RX_LINKB_DCCSTEP_RXCTL)
66985 #define V_RX_LINKB_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKB_DCCLOCK_RXCTL)
66986 #define F_RX_LINKB_DCCLOCK_RXCTL    V_RX_LINKB_DCCLOCK_RXCTL(1U)
67044 #define V_TX_LINKC_DCCSTEP_CTL(x) ((x) << S_TX_LINKC_DCCSTEP_CTL)
67045 #define G_TX_LINKC_DCCSTEP_CTL(x) (((x) >> S_TX_LINKC_DCCSTEP_CTL) & M_TX_LINKC_DCCSTEP_CTL)
67114 #define V_TX_LINKD_DCCSTEP_CTL(x) ((x) << S_TX_LINKD_DCCSTEP_CTL)
67115 #define G_TX_LINKD_DCCSTEP_CTL(x) (((x) >> S_TX_LINKD_DCCSTEP_CTL) & M_TX_LINKD_DCCSTEP_CTL)
67171 #define V_RX_LINKC_ACCCMP_RIS(x) ((x) << S_RX_LINKC_ACCCMP_RIS)
67172 #define F_RX_LINKC_ACCCMP_RIS    V_RX_LINKC_ACCCMP_RIS(1U)
67186 #define V_RX_LINKC_ACCCMP_BIST(x) ((x) << S_RX_LINKC_ACCCMP_BIST)
67187 #define F_RX_LINKC_ACCCMP_BIST    V_RX_LINKC_ACCCMP_BIST(1U)
67206 #define V_RX_LINKC_INDEX_DFE_TC(x) ((x) << S_RX_LINKC_INDEX_DFE_TC)
67207 #define G_RX_LINKC_INDEX_DFE_TC(x) (((x) >> S_RX_LINKC_INDEX_DFE_TC) & M_RX_LINKC_INDEX_DFE_TC)
67214 #define V_RX_LINKC_INDEX_DFE_TAP(x) ((x) << S_RX_LINKC_INDEX_DFE_TAP)
67215 #define G_RX_LINKC_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKC_INDEX_DFE_TAP) & M_RX_LINKC_INDEX_DFE_TAP)
67232 #define V_RX_LINKC_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKC_DCCSTEP_RXCTL)
67233 #define G_RX_LINKC_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKC_DCCSTEP_RXCTL) & M_RX_LINKC_DCCSTEP_RXCTL)
67236 #define V_RX_LINKC_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKC_DCCLOCK_RXCTL)
67237 #define F_RX_LINKC_DCCLOCK_RXCTL    V_RX_LINKC_DCCLOCK_RXCTL(1U)
67282 #define V_RX_LINKD_ACCCMP_RIS(x) ((x) << S_RX_LINKD_ACCCMP_RIS)
67283 #define F_RX_LINKD_ACCCMP_RIS    V_RX_LINKD_ACCCMP_RIS(1U)
67297 #define V_RX_LINKD_ACCCMP_BIST(x) ((x) << S_RX_LINKD_ACCCMP_BIST)
67298 #define F_RX_LINKD_ACCCMP_BIST    V_RX_LINKD_ACCCMP_BIST(1U)
67317 #define V_RX_LINKD_INDEX_DFE_TC(x) ((x) << S_RX_LINKD_INDEX_DFE_TC)
67318 #define G_RX_LINKD_INDEX_DFE_TC(x) (((x) >> S_RX_LINKD_INDEX_DFE_TC) & M_RX_LINKD_INDEX_DFE_TC)
67325 #define V_RX_LINKD_INDEX_DFE_TAP(x) ((x) << S_RX_LINKD_INDEX_DFE_TAP)
67326 #define G_RX_LINKD_INDEX_DFE_TAP(x) (((x) >> S_RX_LINKD_INDEX_DFE_TAP) & M_RX_LINKD_INDEX_DFE_TAP)
67343 #define V_RX_LINKD_DCCSTEP_RXCTL(x) ((x) << S_RX_LINKD_DCCSTEP_RXCTL)
67344 #define G_RX_LINKD_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINKD_DCCSTEP_RXCTL) & M_RX_LINKD_DCCSTEP_RXCTL)
67347 #define V_RX_LINKD_DCCLOCK_RXCTL(x) ((x) << S_RX_LINKD_DCCLOCK_RXCTL)
67348 #define F_RX_LINKD_DCCLOCK_RXCTL    V_RX_LINKD_DCCLOCK_RXCTL(1U)
67359 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
67360 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
67366 #define V_REFSEL(x) ((x) << S_REFSEL)
67367 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
67373 #define V_REFISINK(x) ((x) << S_REFISINK)
67374 #define G_REFISINK(x) (((x) >> S_REFISINK) & M_REFISINK)
67380 #define V_REFISRC(x) ((x) << S_REFISRC)
67381 #define G_REFISRC(x) (((x) >> S_REFISRC) & M_REFISRC)
67387 #define V_REFVREG(x) ((x) << S_REFVREG)
67388 #define G_REFVREG(x) (((x) >> S_REFVREG) & M_REFVREG)
67393 #define V_BGCLKSEL(x) ((x) << S_BGCLKSEL)
67394 #define F_BGCLKSEL    V_BGCLKSEL(1U)
67398 #define V_VBGENDOC(x) ((x) << S_VBGENDOC)
67399 #define G_VBGENDOC(x) (((x) >> S_VBGENDOC) & M_VBGENDOC)
67405 #define V_VREFTUNE(x) ((x) << S_VREFTUNE)
67406 #define G_VREFTUNE(x) (((x) >> S_VREFTUNE) & M_VREFTUNE)
67411 #define V_RCCTL1(x) ((x) << S_RCCTL1)
67412 #define F_RCCTL1    V_RCCTL1(1U)
67415 #define V_RCCTL0(x) ((x) << S_RCCTL0)
67416 #define F_RCCTL0    V_RCCTL0(1U)
67419 #define V_RCAMP1(x) ((x) << S_RCAMP1)
67420 #define F_RCAMP1    V_RCAMP1(1U)
67423 #define V_RCAMP0(x) ((x) << S_RCAMP0)
67424 #define F_RCAMP0    V_RCAMP0(1U)
67426 #define S_RCAMPEN    1
67427 #define V_RCAMPEN(x) ((x) << S_RCAMPEN)
67428 #define F_RCAMPEN    V_RCAMPEN(1U)
67431 #define V_RCRST(x) ((x) << S_RCRST)
67432 #define F_RCRST    V_RCRST(1U)
67437 #define V_FRCCAL_COMP(x) ((x) << S_FRCCAL_COMP)
67438 #define F_FRCCAL_COMP    V_FRCCAL_COMP(1U)
67441 #define V_IC_FRCERR(x) ((x) << S_IC_FRCERR)
67442 #define F_IC_FRCERR    V_IC_FRCERR(1U)
67445 #define V_CAL_BISTENAB(x) ((x) << S_CAL_BISTENAB)
67446 #define F_CAL_BISTENAB    V_CAL_BISTENAB(1U)
67449 #define V_RCAL_RESET(x) ((x) << S_RCAL_RESET)
67450 #define F_RCAL_RESET    V_RCAL_RESET(1U)
67454 #define S_RCERR    1
67455 #define V_RCERR(x) ((x) << S_RCERR)
67456 #define F_RCERR    V_RCERR(1U)
67459 #define V_RCCOMP(x) ((x) << S_RCCOMP)
67460 #define F_RCCOMP    V_RCCOMP(1U)
67465 #define V_RCALBENAB(x) ((x) << S_RCALBENAB)
67466 #define F_RCALBENAB    V_RCALBENAB(1U)
67469 #define V_RCALBUSY(x) ((x) << S_RCALBUSY)
67470 #define F_RCALBUSY    V_RCALBUSY(1U)
67472 #define S_RCALERR    1
67473 #define V_RCALERR(x) ((x) << S_RCALERR)
67474 #define F_RCALERR    V_RCALERR(1U)
67477 #define V_RCALCOMP(x) ((x) << S_RCALCOMP)
67478 #define F_RCALCOMP    V_RCALCOMP(1U)
67484 #define V_RESREG2(x) ((x) << S_RESREG2)
67485 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
67491 #define V_T6_RESREG2(x) ((x) << S_T6_RESREG2)
67492 #define G_T6_RESREG2(x) (((x) >> S_T6_RESREG2) & M_T6_RESREG2)
67498 #define V_RESREG3(x) ((x) << S_RESREG3)
67499 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
67505 #define V_T6_RESREG3(x) ((x) << S_T6_RESREG3)
67506 #define G_T6_RESREG3(x) (((x) >> S_T6_RESREG3) & M_T6_RESREG3)
67511 #define V_ISGT(x) ((x) << S_ISGT)
67512 #define F_ISGT    V_ISGT(1U)
67515 #define V_ISLT(x) ((x) << S_ISLT)
67516 #define F_ISLT    V_ISLT(1U)
67519 #define V_ISEQ(x) ((x) << S_ISEQ)
67520 #define F_ISEQ    V_ISEQ(1U)
67524 #define V_ISVAL(x) ((x) << S_ISVAL)
67525 #define G_ISVAL(x) (((x) >> S_ISVAL) & M_ISVAL)
67527 #define S_GTORLT    1
67529 #define V_GTORLT(x) ((x) << S_GTORLT)
67530 #define G_GTORLT(x) (((x) >> S_GTORLT) & M_GTORLT)
67533 #define V_INEQ(x) ((x) << S_INEQ)
67534 #define F_INEQ    V_INEQ(1U)
67540 #define V_LLIM(x) ((x) << S_LLIM)
67541 #define G_LLIM(x) (((x) >> S_LLIM) & M_LLIM)
67547 #define V_LMSK(x) ((x) << S_LMSK)
67548 #define G_LMSK(x) (((x) >> S_LMSK) & M_LMSK)
67554 #define V_HLIM(x) ((x) << S_HLIM)
67555 #define G_HLIM(x) (((x) >> S_HLIM) & M_HLIM)
67561 #define V_HMSK(x) ((x) << S_HMSK)
67562 #define G_HMSK(x) (((x) >> S_HMSK) & M_HMSK)
67567 #define V_LBIST(x) ((x) << S_LBIST)
67568 #define F_LBIST    V_LBIST(1U)
67571 #define V_LOGICTEST(x) ((x) << S_LOGICTEST)
67572 #define F_LOGICTEST    V_LOGICTEST(1U)
67575 #define V_MAVDHI(x) ((x) << S_MAVDHI)
67576 #define F_MAVDHI    V_MAVDHI(1U)
67579 #define V_AUXEN(x) ((x) << S_AUXEN)
67580 #define F_AUXEN    V_AUXEN(1U)
67583 #define V_JTAGMD(x) ((x) << S_JTAGMD)
67584 #define F_JTAGMD    V_JTAGMD(1U)
67587 #define V_RXACMODE(x) ((x) << S_RXACMODE)
67588 #define F_RXACMODE    V_RXACMODE(1U)
67590 #define S_HSSACJPC    1
67591 #define V_HSSACJPC(x) ((x) << S_HSSACJPC)
67592 #define F_HSSACJPC    V_HSSACJPC(1U)
67595 #define V_HSSACJAC(x) ((x) << S_HSSACJAC)
67596 #define F_HSSACJAC    V_HSSACJAC(1U)
67601 #define V_REFVALIDD(x) ((x) << S_REFVALIDD)
67602 #define F_REFVALIDD    V_REFVALIDD(1U)
67605 #define V_REFVALIDC(x) ((x) << S_REFVALIDC)
67606 #define F_REFVALIDC    V_REFVALIDC(1U)
67609 #define V_REFVALIDB(x) ((x) << S_REFVALIDB)
67610 #define F_REFVALIDB    V_REFVALIDB(1U)
67613 #define V_REFVALIDA(x) ((x) << S_REFVALIDA)
67614 #define F_REFVALIDA    V_REFVALIDA(1U)
67617 #define V_REFSELRESET(x) ((x) << S_REFSELRESET)
67618 #define F_REFSELRESET    V_REFSELRESET(1U)
67620 #define S_SOFTRESET    1
67621 #define V_SOFTRESET(x) ((x) << S_SOFTRESET)
67622 #define F_SOFTRESET    V_SOFTRESET(1U)
67625 #define V_MACROTEST(x) ((x) << S_MACROTEST)
67626 #define F_MACROTEST    V_MACROTEST(1U)
67680 #define V_TX_LINK_BCST_DCCSTEP_CTL(x) ((x) << S_TX_LINK_BCST_DCCSTEP_CTL)
67681 #define G_TX_LINK_BCST_DCCSTEP_CTL(x) (((x) >> S_TX_LINK_BCST_DCCSTEP_CTL) & M_TX_LINK_BCST_DCCSTEP_CTL)
67737 #define V_RX_LINK_BCST_ACCCMP_RIS(x) ((x) << S_RX_LINK_BCST_ACCCMP_RIS)
67738 #define F_RX_LINK_BCST_ACCCMP_RIS    V_RX_LINK_BCST_ACCCMP_RIS(1U)
67752 #define V_RX_LINK_BCST_ACCCMP_BIST(x) ((x) << S_RX_LINK_BCST_ACCCMP_BIST)
67753 #define F_RX_LINK_BCST_ACCCMP_BIST    V_RX_LINK_BCST_ACCCMP_BIST(1U)
67772 #define V_RX_LINK_BCST_INDEX_DFE_TC(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TC)
67773 #define G_RX_LINK_BCST_INDEX_DFE_TC(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TC) & M_RX_LINK_BCST_INDEX_DFE_TC)
67780 #define V_RX_LINK_BCST_INDEX_DFE_TAP(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_TAP)
67781 #define G_RX_LINK_BCST_INDEX_DFE_TAP(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_TAP) & M_RX_LINK_BCST_INDEX_DFE_TAP)
67798 #define V_RX_LINK_BCST_DCCSTEP_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCSTEP_RXCTL)
67799 #define G_RX_LINK_BCST_DCCSTEP_RXCTL(x) (((x) >> S_RX_LINK_BCST_DCCSTEP_RXCTL) & M_RX_LINK_BCST_DCCSTEP_RXCTL)
67802 #define V_RX_LINK_BCST_DCCLOCK_RXCTL(x) ((x) << S_RX_LINK_BCST_DCCLOCK_RXCTL)
67803 #define F_RX_LINK_BCST_DCCLOCK_RXCTL    V_RX_LINK_BCST_DCCLOCK_RXCTL(1U)
67816 #define S_SPWRENA    1
67817 #define V_SPWRENA(x) ((x) << S_SPWRENA)
67818 #define F_SPWRENA    V_SPWRENA(1U)
67821 #define V_NPWRENA(x) ((x) << S_NPWRENA)
67822 #define F_NPWRENA    V_NPWRENA(1U)
67828 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
67829 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
67836 #define V_SPEDIV(x) ((x) << S_SPEDIV)
67837 #define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
67841 #define V_PCKSEL(x) ((x) << S_PCKSEL)
67842 #define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
67847 #define V_EMIL(x) ((x) << S_EMIL)
67848 #define F_EMIL    V_EMIL(1U)
67850 #define S_EMID    1
67851 #define V_EMID(x) ((x) << S_EMID)
67852 #define F_EMID    V_EMID(1U)
67855 #define V_EMIS(x) ((x) << S_EMIS)
67856 #define F_EMIS    V_EMIS(1U)
67862 #define V_EMIL1(x) ((x) << S_EMIL1)
67863 #define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
67869 #define V_EMIL2(x) ((x) << S_EMIL2)
67870 #define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
67876 #define V_EMIL3(x) ((x) << S_EMIL3)
67877 #define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
67883 #define V_EMIL4(x) ((x) << S_EMIL4)
67884 #define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
67888 #define S_VBST    1
67890 #define V_VBST(x) ((x) << S_VBST)
67891 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
67894 #define V_PLLDIVA(x) ((x) << S_PLLDIVA)
67895 #define F_PLLDIVA    V_PLLDIVA(1U)
67899 #define V_REFDIV(x) ((x) << S_REFDIV)
67900 #define G_REFDIV(x) (((x) >> S_REFDIV) & M_REFDIV)
67905 #define V_RESYNC(x) ((x) << S_RESYNC)
67906 #define F_RESYNC    V_RESYNC(1U)
67909 #define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
67910 #define F_RXCLKSEL    V_RXCLKSEL(1U)
67913 #define V_FRCBAND(x) ((x) << S_FRCBAND)
67914 #define F_FRCBAND    V_FRCBAND(1U)
67917 #define V_PLLBYP(x) ((x) << S_PLLBYP)
67918 #define F_PLLBYP    V_PLLBYP(1U)
67921 #define V_PDWNP(x) ((x) << S_PDWNP)
67922 #define F_PDWNP    V_PDWNP(1U)
67924 #define S_VCOSEL    1
67925 #define V_VCOSEL(x) ((x) << S_VCOSEL)
67926 #define F_VCOSEL    V_VCOSEL(1U)
67929 #define V_DIVSEL8(x) ((x) << S_DIVSEL8)
67930 #define F_DIVSEL8    V_DIVSEL8(1U)
67936 #define V_DIVSEL(x) ((x) << S_DIVSEL)
67937 #define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
67943 #define V_CONFIG(x) ((x) << S_CONFIG)
67944 #define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
67968 #define V_STEP(x) ((x) << S_STEP)
67969 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
67976 #define V_C0INIT(x) ((x) << S_C0INIT)
67977 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
67981 #define V_C0PRESET(x) ((x) << S_C0PRESET)
67982 #define G_C0PRESET(x) (((x) >> S_C0PRESET) & M_C0PRESET)
67986 #define V_C0INIT1(x) ((x) << S_C0INIT1)
67987 #define G_C0INIT1(x) (((x) >> S_C0INIT1) & M_C0INIT1)
67993 #define V_C0MAX(x) ((x) << S_C0MAX)
67994 #define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
67998 #define V_C0MIN(x) ((x) << S_C0MIN)
67999 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
68005 #define V_T6_C0MAX(x) ((x) << S_T6_C0MAX)
68006 #define G_T6_C0MAX(x) (((x) >> S_T6_C0MAX) & M_T6_C0MAX)
68010 #define V_T6_C0MIN(x) ((x) << S_T6_C0MIN)
68011 #define G_T6_C0MIN(x) (((x) >> S_T6_C0MIN) & M_T6_C0MIN)
68017 #define V_C1INIT(x) ((x) << S_C1INIT)
68018 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
68024 #define V_C1PRESET(x) ((x) << S_C1PRESET)
68025 #define G_C1PRESET(x) (((x) >> S_C1PRESET) & M_C1PRESET)
68029 #define V_C1INIT1(x) ((x) << S_C1INIT1)
68030 #define G_C1INIT1(x) (((x) >> S_C1INIT1) & M_C1INIT1)
68036 #define V_C1MAX(x) ((x) << S_C1MAX)
68037 #define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
68041 #define V_C1MIN(x) ((x) << S_C1MIN)
68042 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
68049 #define V_C2INIT(x) ((x) << S_C2INIT)
68050 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
68056 #define V_C2PRESET(x) ((x) << S_C2PRESET)
68057 #define G_C2PRESET(x) (((x) >> S_C2PRESET) & M_C2PRESET)
68061 #define V_C2INIT1(x) ((x) << S_C2INIT1)
68062 #define G_C2INIT1(x) (((x) >> S_C2INIT1) & M_C2INIT1)
68068 #define V_C2MAX(x) ((x) << S_C2MAX)
68069 #define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
68073 #define V_C2MIN(x) ((x) << S_C2MIN)
68074 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
68080 #define V_T6_C2MAX(x) ((x) << S_T6_C2MAX)
68081 #define G_T6_C2MAX(x) (((x) >> S_T6_C2MAX) & M_T6_C2MAX)
68085 #define V_T6_C2MIN(x) ((x) << S_T6_C2MIN)
68086 #define G_T6_C2MIN(x) (((x) >> S_T6_C2MIN) & M_T6_C2MIN)
68092 #define V_VMMAX(x) ((x) << S_VMMAX)
68093 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
68100 #define V_V2MIN(x) ((x) << S_V2MIN)
68101 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
68108 #define V_C3PRESET(x) ((x) << S_C3PRESET)
68109 #define G_C3PRESET(x) (((x) >> S_C3PRESET) & M_C3PRESET)
68113 #define V_C3INIT1(x) ((x) << S_C3INIT1)
68114 #define G_C3INIT1(x) (((x) >> S_C3INIT1) & M_C3INIT1)
68120 #define V_C3MAX(x) ((x) << S_C3MAX)
68121 #define G_C3MAX(x) (((x) >> S_C3MAX) & M_C3MAX)
68125 #define V_C3MIN(x) ((x) << S_C3MIN)
68126 #define G_C3MIN(x) (((x) >> S_C3MIN) & M_C3MIN)
68132 #define V_C0INIT2(x) ((x) << S_C0INIT2)
68133 #define G_C0INIT2(x) (((x) >> S_C0INIT2) & M_C0INIT2)
68139 #define V_C1INIT2(x) ((x) << S_C1INIT2)
68140 #define G_C1INIT2(x) (((x) >> S_C1INIT2) & M_C1INIT2)
68146 #define V_C2INIT2(x) ((x) << S_C2INIT2)
68147 #define G_C2INIT2(x) (((x) >> S_C2INIT2) & M_C2INIT2)
68153 #define V_C3INIT2(x) ((x) << S_C3INIT2)
68154 #define G_C3INIT2(x) (((x) >> S_C3INIT2) & M_C3INIT2)
68250 #define S_RX_LINKA_INDEX_DFE_EN    1
68252 #define V_RX_LINKA_INDEX_DFE_EN(x) ((x) << S_RX_LINKA_INDEX_DFE_EN)
68253 #define G_RX_LINKA_INDEX_DFE_EN(x) (((x) >> S_RX_LINKA_INDEX_DFE_EN) & M_RX_LINKA_INDEX_DFE_EN)
68259 #define V_T6_H1OSN(x) ((x) << S_T6_H1OSN)
68260 #define G_T6_H1OSN(x) (((x) >> S_T6_H1OSN) & M_T6_H1OSN)
68264 #define V_T6_H1OMAG(x) ((x) << S_T6_H1OMAG)
68265 #define G_T6_H1OMAG(x) (((x) >> S_T6_H1OMAG) & M_T6_H1OMAG)
68273 #define V_H4SN(x) ((x) << S_H4SN)
68274 #define G_H4SN(x) (((x) >> S_H4SN) & M_H4SN)
68278 #define V_H4MAG(x) ((x) << S_H4MAG)
68279 #define G_H4MAG(x) (((x) >> S_H4MAG) & M_H4MAG)
68285 #define V_H5GS(x) ((x) << S_H5GS)
68286 #define G_H5GS(x) (((x) >> S_H5GS) & M_H5GS)
68290 #define V_H5SN(x) ((x) << S_H5SN)
68291 #define G_H5SN(x) (((x) >> S_H5SN) & M_H5SN)
68295 #define V_H5MAG(x) ((x) << S_H5MAG)
68296 #define G_H5MAG(x) (((x) >> S_H5MAG) & M_H5MAG)
68302 #define V_H7SN(x) ((x) << S_H7SN)
68303 #define G_H7SN(x) (((x) >> S_H7SN) & M_H7SN)
68307 #define V_H6SN(x) ((x) << S_H6SN)
68308 #define G_H6SN(x) (((x) >> S_H6SN) & M_H6SN)
68314 #define V_H9SN(x) ((x) << S_H9SN)
68315 #define G_H9SN(x) (((x) >> S_H9SN) & M_H9SN)
68319 #define V_H8SN(x) ((x) << S_H8SN)
68320 #define G_H8SN(x) (((x) >> S_H8SN) & M_H8SN)
68326 #define V_H11SN(x) ((x) << S_H11SN)
68327 #define G_H11SN(x) (((x) >> S_H11SN) & M_H11SN)
68331 #define V_H10SN(x) ((x) << S_H10SN)
68332 #define G_H10SN(x) (((x) >> S_H10SN) & M_H10SN)
68338 #define V_H13GS(x) ((x) << S_H13GS)
68339 #define G_H13GS(x) (((x) >> S_H13GS) & M_H13GS)
68343 #define V_H13SN(x) ((x) << S_H13SN)
68344 #define G_H13SN(x) (((x) >> S_H13SN) & M_H13SN)
68348 #define V_H13MAG(x) ((x) << S_H13MAG)
68349 #define G_H13MAG(x) (((x) >> S_H13MAG) & M_H13MAG)
68353 #define V_H12SN(x) ((x) << S_H12SN)
68354 #define G_H12SN(x) (((x) >> S_H12SN) & M_H12SN)
68360 #define V_H15GS(x) ((x) << S_H15GS)
68361 #define G_H15GS(x) (((x) >> S_H15GS) & M_H15GS)
68365 #define V_H15SN(x) ((x) << S_H15SN)
68366 #define G_H15SN(x) (((x) >> S_H15SN) & M_H15SN)
68370 #define V_H15MAG(x) ((x) << S_H15MAG)
68371 #define G_H15MAG(x) (((x) >> S_H15MAG) & M_H15MAG)
68375 #define V_H14GS(x) ((x) << S_H14GS)
68376 #define G_H14GS(x) (((x) >> S_H14GS) & M_H14GS)
68380 #define V_H14SN(x) ((x) << S_H14SN)
68381 #define G_H14SN(x) (((x) >> S_H14SN) & M_H14SN)
68385 #define V_H14MAG(x) ((x) << S_H14MAG)
68386 #define G_H14MAG(x) (((x) >> S_H14MAG) & M_H14MAG)
68392 #define V_H1ODELTA(x) ((x) << S_H1ODELTA)
68393 #define G_H1ODELTA(x) (((x) >> S_H1ODELTA) & M_H1ODELTA)
68397 #define V_H1EDELTA(x) ((x) << S_H1EDELTA)
68398 #define G_H1EDELTA(x) (((x) >> S_H1EDELTA) & M_H1EDELTA)
68402 #define S_RX_LINKB_INDEX_DFE_EN    1
68404 #define V_RX_LINKB_INDEX_DFE_EN(x) ((x) << S_RX_LINKB_INDEX_DFE_EN)
68405 #define G_RX_LINKB_INDEX_DFE_EN(x) (((x) >> S_RX_LINKB_INDEX_DFE_EN) & M_RX_LINKB_INDEX_DFE_EN)
68420 #define S_RX_LINKC_INDEX_DFE_EN    1
68422 #define V_RX_LINKC_INDEX_DFE_EN(x) ((x) << S_RX_LINKC_INDEX_DFE_EN)
68423 #define G_RX_LINKC_INDEX_DFE_EN(x) (((x) >> S_RX_LINKC_INDEX_DFE_EN) & M_RX_LINKC_INDEX_DFE_EN)
68438 #define S_RX_LINKD_INDEX_DFE_EN    1
68440 #define V_RX_LINKD_INDEX_DFE_EN(x) ((x) << S_RX_LINKD_INDEX_DFE_EN)
68441 #define G_RX_LINKD_INDEX_DFE_EN(x) (((x) >> S_RX_LINKD_INDEX_DFE_EN) & M_RX_LINKD_INDEX_DFE_EN)
68456 #define S_RX_LINK_BCST_INDEX_DFE_EN    1
68458 #define V_RX_LINK_BCST_INDEX_DFE_EN(x) ((x) << S_RX_LINK_BCST_INDEX_DFE_EN)
68459 #define G_RX_LINK_BCST_INDEX_DFE_EN(x) (((x) >> S_RX_LINK_BCST_INDEX_DFE_EN) & M_RX_LINK_BCST_INDEX_DFE_EN)
68480 #define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
68481 #define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
68484 #define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
68485 #define F_NFIFO_NIF1_DIS    V_NFIFO_NIF1_DIS(1U)
68492 #define V_LP_TRIG(x) ((x) << S_LP_TRIG)
68493 #define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
68497 #define S_PARITY_INTR    1
68498 #define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
68499 #define F_PARITY_INTR    V_PARITY_INTR(1U)
68502 #define V_ECC_INTR(x) ((x) << S_ECC_INTR)
68503 #define F_ECC_INTR    V_ECC_INTR(1U)
68509 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
68510 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
68515 #define V_INIT_COMPLETE(x) ((x) << S_INIT_COMPLETE)
68516 #define F_INIT_COMPLETE    V_INIT_COMPLETE(1U)
68519 #define V_SELF_REF_MODE(x) ((x) << S_SELF_REF_MODE)
68520 #define F_SELF_REF_MODE    V_SELF_REF_MODE(1U)
68523 #define V_IDLE(x) ((x) << S_IDLE)
68524 #define F_IDLE    V_IDLE(1U)
68527 #define V_T6_DFI_INIT_COMPLETE(x) ((x) << S_T6_DFI_INIT_COMPLETE)
68528 #define F_T6_DFI_INIT_COMPLETE    V_T6_DFI_INIT_COMPLETE(1U)
68531 #define V_PREFILL_COMPLETE(x) ((x) << S_PREFILL_COMPLETE)
68532 #define F_PREFILL_COMPLETE    V_PREFILL_COMPLETE(1U)
68539 #define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
68540 #define F_CMD_TSTAT    V_CMD_TSTAT(1U)
68545 #define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
68546 #define F_CMD_TSTAT_EN    V_CMD_TSTAT_EN(1U)
68552 #define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
68553 #define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
68559 #define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
68560 #define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
68564 #define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
68565 #define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
68569 #define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
68570 #define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
68574 #define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
68575 #define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
68581 #define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
68582 #define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
68586 #define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
68587 #define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
68591 #define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
68592 #define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
68596 #define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
68597 #define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
68602 #define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
68603 #define F_HW_EXIT_IDLE_EN    V_HW_EXIT_IDLE_EN(1U)
68607 #define V_HW_IDLE(x) ((x) << S_HW_IDLE)
68608 #define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
68612 #define V_SR_IDLE(x) ((x) << S_SR_IDLE)
68613 #define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
68619 #define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
68620 #define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
68624 #define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
68625 #define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
68629 #define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
68630 #define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
68633 #define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
68634 #define F_LPDDR2_S4    V_LPDDR2_S4(1U)
68637 #define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
68638 #define F_STAGGER_CS    V_STAGGER_CS(1U)
68640 #define S_CKE_OR_EN    1
68641 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
68642 #define F_CKE_OR_EN    V_CKE_OR_EN(1U)
68647 #define V_MC_PROTOCOL(x) ((x) << S_MC_PROTOCOL)
68648 #define F_MC_PROTOCOL    V_MC_PROTOCOL(1U)
68651 #define V_DM_ENABLE(x) ((x) << S_DM_ENABLE)
68652 #define F_DM_ENABLE    V_DM_ENABLE(1U)
68655 #define V_T6_ECC_EN(x) ((x) << S_T6_ECC_EN)
68656 #define F_T6_ECC_EN    V_T6_ECC_EN(1U)
68659 #define V_ECC_COR(x) ((x) << S_ECC_COR)
68660 #define F_ECC_COR    V_ECC_COR(1U)
68663 #define V_RDIMM(x) ((x) << S_RDIMM)
68664 #define F_RDIMM    V_RDIMM(1U)
68668 #define V_PMUM(x) ((x) << S_PMUM)
68669 #define G_PMUM(x) (((x) >> S_PMUM) & M_PMUM)
68672 #define V_WIDTH0(x) ((x) << S_WIDTH0)
68673 #define F_WIDTH0    V_WIDTH0(1U)
68676 #define V_PORT_ID_CHK_EN(x) ((x) << S_PORT_ID_CHK_EN)
68677 #define F_PORT_ID_CHK_EN    V_PORT_ID_CHK_EN(1U)
68680 #define V_UIOS(x) ((x) << S_UIOS)
68681 #define F_UIOS    V_UIOS(1U)
68684 #define V_QUADCS_RDIMM(x) ((x) << S_QUADCS_RDIMM)
68685 #define F_QUADCS_RDIMM    V_QUADCS_RDIMM(1U)
68688 #define V_ZQCL_EN(x) ((x) << S_ZQCL_EN)
68689 #define F_ZQCL_EN    V_ZQCL_EN(1U)
68692 #define V_WIDTH1(x) ((x) << S_WIDTH1)
68693 #define F_WIDTH1    V_WIDTH1(1U)
68696 #define V_WD_DLY(x) ((x) << S_WD_DLY)
68697 #define F_WD_DLY    V_WD_DLY(1U)
68701 #define V_QDEPTH(x) ((x) << S_QDEPTH)
68702 #define G_QDEPTH(x) (((x) >> S_QDEPTH) & M_QDEPTH)
68705 #define V_RWOO(x) ((x) << S_RWOO)
68706 #define F_RWOO    V_RWOO(1U)
68709 #define V_WOOO(x) ((x) << S_WOOO)
68710 #define F_WOOO    V_WOOO(1U)
68713 #define V_DCOO(x) ((x) << S_DCOO)
68714 #define F_DCOO    V_DCOO(1U)
68717 #define V_DEF_REF(x) ((x) << S_DEF_REF)
68718 #define F_DEF_REF    V_DEF_REF(1U)
68721 #define V_DEV_TYPE(x) ((x) << S_DEV_TYPE)
68722 #define F_DEV_TYPE    V_DEV_TYPE(1U)
68725 #define V_CA_PTY_DLY(x) ((x) << S_CA_PTY_DLY)
68726 #define F_CA_PTY_DLY    V_CA_PTY_DLY(1U)
68730 #define V_ECC_MUX(x) ((x) << S_ECC_MUX)
68731 #define G_ECC_MUX(x) (((x) >> S_ECC_MUX) & M_ECC_MUX)
68735 #define V_CE_THRESHOLD(x) ((x) << S_CE_THRESHOLD)
68736 #define G_CE_THRESHOLD(x) (((x) >> S_CE_THRESHOLD) & M_CE_THRESHOLD)
68742 #define V_SELF_REF_EN(x) ((x) << S_SELF_REF_EN)
68743 #define F_SELF_REF_EN    V_SELF_REF_EN(1U)
68746 #define V_XSR_PREVENT(x) ((x) << S_XSR_PREVENT)
68747 #define F_XSR_PREVENT    V_XSR_PREVENT(1U)
68750 #define V_INIT_START(x) ((x) << S_INIT_START)
68751 #define F_INIT_START    V_INIT_START(1U)
68754 #define V_MC_ENABLE(x) ((x) << S_MC_ENABLE)
68755 #define F_MC_ENABLE    V_MC_ENABLE(1U)
68759 #define V_CLK_DISABLE(x) ((x) << S_CLK_DISABLE)
68760 #define G_CLK_DISABLE(x) (((x) >> S_CLK_DISABLE) & M_CLK_DISABLE)
68764 #define V_RESET_RANK(x) ((x) << S_RESET_RANK)
68765 #define G_RESET_RANK(x) (((x) >> S_RESET_RANK) & M_RESET_RANK)
68768 #define V_MCIF_COMP_PTY_EN(x) ((x) << S_MCIF_COMP_PTY_EN)
68769 #define F_MCIF_COMP_PTY_EN    V_MCIF_COMP_PTY_EN(1U)
68772 #define V_CKE_OE(x) ((x) << S_CKE_OE)
68773 #define F_CKE_OE    V_CKE_OE(1U)
68776 #define V_RESET_OE(x) ((x) << S_RESET_OE)
68777 #define F_RESET_OE    V_RESET_OE(1U)
68780 #define V_DFI_PHYUD_CNTL(x) ((x) << S_DFI_PHYUD_CNTL)
68781 #define F_DFI_PHYUD_CNTL    V_DFI_PHYUD_CNTL(1U)
68784 #define V_DFI_PHYUD_ACK(x) ((x) << S_DFI_PHYUD_ACK)
68785 #define F_DFI_PHYUD_ACK    V_DFI_PHYUD_ACK(1U)
68788 #define V_T6_DFI_INIT_START(x) ((x) << S_T6_DFI_INIT_START)
68789 #define F_T6_DFI_INIT_START    V_T6_DFI_INIT_START(1U)
68793 #define V_PM_ENABLE(x) ((x) << S_PM_ENABLE)
68794 #define G_PM_ENABLE(x) (((x) >> S_PM_ENABLE) & M_PM_ENABLE)
68798 #define V_RD_DEFREF_CNT(x) ((x) << S_RD_DEFREF_CNT)
68799 #define G_RD_DEFREF_CNT(x) (((x) >> S_RD_DEFREF_CNT) & M_RD_DEFREF_CNT)
68804 #define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
68805 #define F_SELF_REFRESH    V_SELF_REFRESH(1U)
68807 #define S_CLOCK_STOP    1
68808 #define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
68809 #define F_CLOCK_STOP    V_CLOCK_STOP(1U)
68815 #define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
68816 #define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
68820 #define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
68821 #define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
68825 #define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
68826 #define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
68830 #define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
68831 #define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
68836 #define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
68837 #define F_DTU_ERR_B7    V_DTU_ERR_B7(1U)
68856 #define V_T_RFC0(x) ((x) << S_T_RFC0)
68857 #define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
68863 #define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
68864 #define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
68870 #define V_T_RTW0(x) ((x) << S_T_RTW0)
68871 #define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
68884 #define V_T_RTP0(x) ((x) << S_T_RTP0)
68885 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
68891 #define V_ROW_WIDTH(x) ((x) << S_ROW_WIDTH)
68892 #define G_ROW_WIDTH(x) (((x) >> S_ROW_WIDTH) & M_ROW_WIDTH)
68896 #define V_ADDR_MODE(x) ((x) << S_ADDR_MODE)
68897 #define G_ADDR_MODE(x) (((x) >> S_ADDR_MODE) & M_ADDR_MODE)
68900 #define V_MIRROR(x) ((x) << S_MIRROR)
68901 #define F_MIRROR    V_MIRROR(1U)
68904 #define V_RANK_ENABLE(x) ((x) << S_RANK_ENABLE)
68905 #define F_RANK_ENABLE    V_RANK_ENABLE(1U)
68911 #define V_U_T_WR(x) ((x) << S_U_T_WR)
68912 #define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
68918 #define V_T_WTR0(x) ((x) << S_T_WTR0)
68919 #define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
68931 #define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
68932 #define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
68938 #define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
68939 #define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
68946 #define V_T_MOD0(x) ((x) << S_T_MOD0)
68947 #define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
68953 #define V_T_RSTL(x) ((x) << S_T_RSTL)
68954 #define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
68961 #define V_T_MRR(x) ((x) << S_T_MRR)
68962 #define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
68968 #define V_T_CKESR(x) ((x) << S_T_CKESR)
68969 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
68974 #define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE)
68975 #define F_INIT_ENABLE    V_INIT_ENABLE(1U)
68979 #define CXGBE_V_WAIT(x) ((x) << S_WAIT)
68980 #define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT)
68983 #define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL)
68984 #define F_EN_MULTI_RANK_SEL    V_EN_MULTI_RANK_SEL(1U)
68988 #define V_T6_RANK(x) ((x) << S_T6_RANK)
68989 #define G_T6_RANK(x) (((x) >> S_T6_RANK) & M_T6_RANK)
68995 #define V_T_DPD(x) ((x) << S_T_DPD)
68996 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
69002 #define V_CMD(x) ((x) << S_CMD)
69003 #define G_CMD(x) (((x) >> S_CMD) & M_CMD)
69006 #define V_CMD_ACTN(x) ((x) << S_CMD_ACTN)
69007 #define F_CMD_ACTN    V_CMD_ACTN(1U)
69010 #define V_BG1(x) ((x) << S_BG1)
69011 #define F_BG1    V_BG1(1U)
69015 #define V_BANK(x) ((x) << S_BANK)
69016 #define G_BANK(x) (((x) >> S_BANK) & M_BANK)
69038 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
69039 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
69062 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
69063 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
69069 #define V_REFI(x) ((x) << S_REFI)
69070 #define G_REFI(x) (((x) >> S_REFI) & M_REFI)
69074 #define V_T_RFC_XPR(x) ((x) << S_T_RFC_XPR)
69075 #define G_T_RFC_XPR(x) (((x) >> S_T_RFC_XPR) & M_T_RFC_XPR)
69081 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
69082 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
69087 #define V_T_LEADOFF(x) ((x) << S_T_LEADOFF)
69088 #define F_T_LEADOFF    V_T_LEADOFF(1U)
69091 #define V_ODT_DELAY(x) ((x) << S_ODT_DELAY)
69092 #define F_ODT_DELAY    V_ODT_DELAY(1U)
69095 #define V_ODT_WIDTH(x) ((x) << S_ODT_WIDTH)
69096 #define F_ODT_WIDTH    V_ODT_WIDTH(1U)
69100 #define V_T_WTRO(x) ((x) << S_T_WTRO)
69101 #define G_T_WTRO(x) (((x) >> S_T_WTRO) & M_T_WTRO)
69105 #define V_T_RTWO(x) ((x) << S_T_RTWO)
69106 #define G_T_RTWO(x) (((x) >> S_T_RTWO) & M_T_RTWO)
69110 #define V_T_RTW_ADJ(x) ((x) << S_T_RTW_ADJ)
69111 #define G_T_RTW_ADJ(x) (((x) >> S_T_RTW_ADJ) & M_T_RTW_ADJ)
69115 #define V_T_WTWO(x) ((x) << S_T_WTWO)
69116 #define G_T_WTWO(x) (((x) >> S_T_WTWO) & M_T_WTWO)
69120 #define V_T_RTRO(x) ((x) << S_T_RTRO)
69121 #define G_T_RTRO(x) (((x) >> S_T_RTRO) & M_T_RTRO)
69128 #define V_T6_T_CWL(x) ((x) << S_T6_T_CWL)
69129 #define G_T6_T_CWL(x) (((x) >> S_T6_T_CWL) & M_T6_T_CWL)
69133 #define V_T_RCD0(x) ((x) << S_T_RCD0)
69134 #define G_T_RCD0(x) (((x) >> S_T_RCD0) & M_T_RCD0)
69138 #define V_T_PL(x) ((x) << S_T_PL)
69139 #define G_T_PL(x) (((x) >> S_T_PL) & M_T_PL)
69143 #define V_T_RP0(x) ((x) << S_T_RP0)
69144 #define G_T_RP0(x) (((x) >> S_T_RP0) & M_T_RP0)
69147 #define V_T_RP1(x) ((x) << S_T_RP1)
69148 #define F_T_RP1    V_T_RP1(1U)
69151 #define V_T_RCD1(x) ((x) << S_T_RCD1)
69152 #define F_T_RCD1    V_T_RCD1(1U)
69156 #define V_T6_T_RC(x) ((x) << S_T6_T_RC)
69157 #define G_T6_T_RC(x) (((x) >> S_T6_T_RC) & M_T6_T_RC)
69164 #define V_T_WTR_S(x) ((x) << S_T_WTR_S)
69165 #define G_T_WTR_S(x) (((x) >> S_T_WTR_S) & M_T_WTR_S)
69169 #define V_T6_T_WTR(x) ((x) << S_T6_T_WTR)
69170 #define G_T6_T_WTR(x) (((x) >> S_T6_T_WTR) & M_T6_T_WTR)
69174 #define V_FAW_ADJ(x) ((x) << S_FAW_ADJ)
69175 #define G_FAW_ADJ(x) (((x) >> S_FAW_ADJ) & M_FAW_ADJ)
69179 #define V_T6_T_RTP(x) ((x) << S_T6_T_RTP)
69180 #define G_T6_T_RTP(x) (((x) >> S_T6_T_RTP) & M_T6_T_RTP)
69184 #define V_T_RRD_L(x) ((x) << S_T_RRD_L)
69185 #define G_T_RRD_L(x) (((x) >> S_T_RRD_L) & M_T_RRD_L)
69189 #define V_T6_T_RRD(x) ((x) << S_T6_T_RRD)
69190 #define G_T6_T_RRD(x) (((x) >> S_T6_T_RRD) & M_T6_T_RRD)
69194 #define V_T_XSDLL(x) ((x) << S_T_XSDLL)
69195 #define G_T_XSDLL(x) (((x) >> S_T_XSDLL) & M_T_XSDLL)
69202 #define V_T_RDDATA_EN(x) ((x) << S_T_RDDATA_EN)
69203 #define G_T_RDDATA_EN(x) (((x) >> S_T_RDDATA_EN) & M_T_RDDATA_EN)
69207 #define V_T_SYS_RDLAT(x) ((x) << S_T_SYS_RDLAT)
69208 #define G_T_SYS_RDLAT(x) (((x) >> S_T_SYS_RDLAT) & M_T_SYS_RDLAT)
69212 #define V_T_CCD_L(x) ((x) << S_T_CCD_L)
69213 #define G_T_CCD_L(x) (((x) >> S_T_CCD_L) & M_T_CCD_L)
69217 #define V_T_CCD(x) ((x) << S_T_CCD)
69218 #define G_T_CCD(x) (((x) >> S_T_CCD) & M_T_CCD)
69222 #define V_T_CPDED(x) ((x) << S_T_CPDED)
69223 #define G_T_CPDED(x) (((x) >> S_T_CPDED) & M_T_CPDED)
69227 #define V_T6_T_MOD(x) ((x) << S_T6_T_MOD)
69228 #define G_T6_T_MOD(x) (((x) >> S_T6_T_MOD) & M_T6_T_MOD)
69235 #define V_T_PHY_WRDATA(x) ((x) << S_T_PHY_WRDATA)
69236 #define G_T_PHY_WRDATA(x) (((x) >> S_T_PHY_WRDATA) & M_T_PHY_WRDATA)
69240 #define V_T_PHY_WRLAT(x) ((x) << S_T_PHY_WRLAT)
69241 #define G_T_PHY_WRLAT(x) (((x) >> S_T_PHY_WRLAT) & M_T_PHY_WRLAT)
69252 #define V_T_SYS_RDLAT_DBG(x) ((x) << S_T_SYS_RDLAT_DBG)
69253 #define G_T_SYS_RDLAT_DBG(x) (((x) >> S_T_SYS_RDLAT_DBG) & M_T_SYS_RDLAT_DBG)
69263 #define V_EA_ROW0(x) ((x) << S_EA_ROW0)
69264 #define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
69270 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
69271 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
69277 #define V_SMR0_RFU0(x) ((x) << S_SMR0_RFU0)
69278 #define G_SMR0_RFU0(x) (((x) >> S_SMR0_RFU0) & M_SMR0_RFU0)
69281 #define V_PPD(x) ((x) << S_PPD)
69282 #define F_PPD    V_PPD(1U)
69286 #define V_WR_RTP(x) ((x) << S_WR_RTP)
69287 #define G_WR_RTP(x) (((x) >> S_WR_RTP) & M_WR_RTP)
69290 #define V_SMR0_DLL(x) ((x) << S_SMR0_DLL)
69291 #define F_SMR0_DLL    V_SMR0_DLL(1U)
69294 #define V_TM(x) ((x) << S_TM)
69295 #define F_TM    V_TM(1U)
69299 #define V_CL31(x) ((x) << S_CL31)
69300 #define G_CL31(x) (((x) >> S_CL31) & M_CL31)
69303 #define V_RBT(x) ((x) << S_RBT)
69304 #define F_RBT    V_RBT(1U)
69307 #define V_CL0(x) ((x) << S_CL0)
69308 #define F_CL0    V_CL0(1U)
69312 #define V_BL(x) ((x) << S_BL)
69313 #define G_BL(x) (((x) >> S_BL) & M_BL)
69318 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
69319 #define F_RANK3_ODT_WRITE_NSEL    V_RANK3_ODT_WRITE_NSEL(1U)
69324 #define V_QOFF(x) ((x) << S_QOFF)
69325 #define F_QOFF    V_QOFF(1U)
69328 #define V_TDQS(x) ((x) << S_TDQS)
69329 #define F_TDQS    V_TDQS(1U)
69332 #define V_SMR1_RFU0(x) ((x) << S_SMR1_RFU0)
69333 #define F_SMR1_RFU0    V_SMR1_RFU0(1U)
69336 #define V_RTT_NOM0(x) ((x) << S_RTT_NOM0)
69337 #define F_RTT_NOM0    V_RTT_NOM0(1U)
69340 #define V_SMR1_RFU1(x) ((x) << S_SMR1_RFU1)
69341 #define F_SMR1_RFU1    V_SMR1_RFU1(1U)
69344 #define V_WR_LEVEL(x) ((x) << S_WR_LEVEL)
69345 #define F_WR_LEVEL    V_WR_LEVEL(1U)
69348 #define V_RTT_NOM1(x) ((x) << S_RTT_NOM1)
69349 #define F_RTT_NOM1    V_RTT_NOM1(1U)
69352 #define V_DIC0(x) ((x) << S_DIC0)
69353 #define F_DIC0    V_DIC0(1U)
69357 #define V_AL(x) ((x) << S_AL)
69358 #define G_AL(x) (((x) >> S_AL) & M_AL)
69361 #define V_RTT_NOM2(x) ((x) << S_RTT_NOM2)
69362 #define F_RTT_NOM2    V_RTT_NOM2(1U)
69364 #define S_DIC1    1
69365 #define V_DIC1(x) ((x) << S_DIC1)
69366 #define F_DIC1    V_DIC1(1U)
69369 #define V_SMR1_DLL(x) ((x) << S_SMR1_DLL)
69370 #define F_SMR1_DLL    V_SMR1_DLL(1U)
69376 #define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
69377 #define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
69381 #define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
69382 #define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
69386 #define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
69387 #define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
69391 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
69392 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
69397 #define V_WR_CRC(x) ((x) << S_WR_CRC)
69398 #define F_WR_CRC    V_WR_CRC(1U)
69401 #define V_RD_CRC(x) ((x) << S_RD_CRC)
69402 #define F_RD_CRC    V_RD_CRC(1U)
69406 #define V_RTT_WR(x) ((x) << S_RTT_WR)
69407 #define G_RTT_WR(x) (((x) >> S_RTT_WR) & M_RTT_WR)
69410 #define V_SMR2_RFU0(x) ((x) << S_SMR2_RFU0)
69411 #define F_SMR2_RFU0    V_SMR2_RFU0(1U)
69414 #define V_SRT_ASR1(x) ((x) << S_SRT_ASR1)
69415 #define F_SRT_ASR1    V_SRT_ASR1(1U)
69418 #define V_ASR0(x) ((x) << S_ASR0)
69419 #define F_ASR0    V_ASR0(1U)
69423 #define V_CWL(x) ((x) << S_CWL)
69424 #define G_CWL(x) (((x) >> S_CWL) & M_CWL)
69428 #define V_PASR(x) ((x) << S_PASR)
69429 #define G_PASR(x) (((x) >> S_PASR) & M_PASR)
69435 #define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
69436 #define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
69440 #define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
69441 #define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
69445 #define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
69446 #define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
69450 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
69451 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
69457 #define V_MPR_RD_FMT(x) ((x) << S_MPR_RD_FMT)
69458 #define G_MPR_RD_FMT(x) (((x) >> S_MPR_RD_FMT) & M_MPR_RD_FMT)
69462 #define V_SMR3_RFU0(x) ((x) << S_SMR3_RFU0)
69463 #define G_SMR3_RFU0(x) (((x) >> S_SMR3_RFU0) & M_SMR3_RFU0)
69467 #define V_FGR_MODE(x) ((x) << S_FGR_MODE)
69468 #define G_FGR_MODE(x) (((x) >> S_FGR_MODE) & M_FGR_MODE)
69471 #define V_MRS_RDO(x) ((x) << S_MRS_RDO)
69472 #define F_MRS_RDO    V_MRS_RDO(1U)
69475 #define V_DRAM_ADR(x) ((x) << S_DRAM_ADR)
69476 #define F_DRAM_ADR    V_DRAM_ADR(1U)
69479 #define V_GD_MODE(x) ((x) << S_GD_MODE)
69480 #define F_GD_MODE    V_GD_MODE(1U)
69483 #define V_MPR(x) ((x) << S_MPR)
69484 #define F_MPR    V_MPR(1U)
69488 #define V_MPR_SEL(x) ((x) << S_MPR_SEL)
69489 #define G_MPR_SEL(x) (((x) >> S_MPR_SEL) & M_MPR_SEL)
69495 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
69496 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
69501 #define V_WR_PRE(x) ((x) << S_WR_PRE)
69502 #define F_WR_PRE    V_WR_PRE(1U)
69505 #define V_RD_PRE(x) ((x) << S_RD_PRE)
69506 #define F_RD_PRE    V_RD_PRE(1U)
69509 #define V_RPT_MODE(x) ((x) << S_RPT_MODE)
69510 #define F_RPT_MODE    V_RPT_MODE(1U)
69513 #define V_FESR_MODE(x) ((x) << S_FESR_MODE)
69514 #define F_FESR_MODE    V_FESR_MODE(1U)
69518 #define V_CS_LAT_MODE(x) ((x) << S_CS_LAT_MODE)
69519 #define G_CS_LAT_MODE(x) (((x) >> S_CS_LAT_MODE) & M_CS_LAT_MODE)
69522 #define V_ALERT_STAT(x) ((x) << S_ALERT_STAT)
69523 #define F_ALERT_STAT    V_ALERT_STAT(1U)
69526 #define V_IVM_MODE(x) ((x) << S_IVM_MODE)
69527 #define F_IVM_MODE    V_IVM_MODE(1U)
69530 #define V_TCR_MODE(x) ((x) << S_TCR_MODE)
69531 #define F_TCR_MODE    V_TCR_MODE(1U)
69534 #define V_TCR_RANGE(x) ((x) << S_TCR_RANGE)
69535 #define F_TCR_RANGE    V_TCR_RANGE(1U)
69537 #define S_MPD_MODE    1
69538 #define V_MPD_MODE(x) ((x) << S_MPD_MODE)
69539 #define F_MPD_MODE    V_MPD_MODE(1U)
69542 #define V_SMR4_RFU(x) ((x) << S_SMR4_RFU)
69543 #define F_SMR4_RFU    V_SMR4_RFU(1U)
69549 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
69550 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
69555 #define V_RD_DBI(x) ((x) << S_RD_DBI)
69556 #define F_RD_DBI    V_RD_DBI(1U)
69559 #define V_WR_DBI(x) ((x) << S_WR_DBI)
69560 #define F_WR_DBI    V_WR_DBI(1U)
69563 #define V_DM_MODE(x) ((x) << S_DM_MODE)
69564 #define F_DM_MODE    V_DM_MODE(1U)
69568 #define V_RTT_PARK(x) ((x) << S_RTT_PARK)
69569 #define G_RTT_PARK(x) (((x) >> S_RTT_PARK) & M_RTT_PARK)
69572 #define V_SMR5_RFU(x) ((x) << S_SMR5_RFU)
69573 #define F_SMR5_RFU    V_SMR5_RFU(1U)
69576 #define V_PAR_ERR_STAT(x) ((x) << S_PAR_ERR_STAT)
69577 #define F_PAR_ERR_STAT    V_PAR_ERR_STAT(1U)
69580 #define V_CRC_CLEAR(x) ((x) << S_CRC_CLEAR)
69581 #define F_CRC_CLEAR    V_CRC_CLEAR(1U)
69585 #define V_PAR_LAT_MODE(x) ((x) << S_PAR_LAT_MODE)
69586 #define G_PAR_LAT_MODE(x) (((x) >> S_PAR_LAT_MODE) & M_PAR_LAT_MODE)
69592 #define V_TCCD_L(x) ((x) << S_TCCD_L)
69593 #define G_TCCD_L(x) (((x) >> S_TCCD_L) & M_TCCD_L)
69597 #define V_SRM6_RFU(x) ((x) << S_SRM6_RFU)
69598 #define G_SRM6_RFU(x) (((x) >> S_SRM6_RFU) & M_SRM6_RFU)
69601 #define V_VREF_DQ_RANGE(x) ((x) << S_VREF_DQ_RANGE)
69602 #define F_VREF_DQ_RANGE    V_VREF_DQ_RANGE(1U)
69606 #define V_VREF_DQ_VALUE(x) ((x) << S_VREF_DQ_VALUE)
69607 #define G_VREF_DQ_VALUE(x) (((x) >> S_VREF_DQ_VALUE) & M_VREF_DQ_VALUE)
69613 #define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
69614 #define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
69620 #define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
69621 #define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
69627 #define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
69628 #define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
69634 #define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
69635 #define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
69641 #define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
69642 #define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
69648 #define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
69649 #define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
69655 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
69656 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
69661 #define V_RK0W(x) ((x) << S_RK0W)
69662 #define F_RK0W    V_RK0W(1U)
69665 #define V_RK0R(x) ((x) << S_RK0R)
69666 #define F_RK0R    V_RK0R(1U)
69672 #define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
69673 #define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
69679 #define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
69680 #define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
69684 #define S_DFI_PHYUPD_EN    1
69685 #define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
69686 #define F_DFI_PHYUPD_EN    V_DFI_PHYUPD_EN(1U)
69689 #define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
69690 #define F_DFI_CTRLUPD_EN    V_DFI_CTRLUPD_EN(1U)
69696 #define V_TREFMSKI(x) ((x) << S_TREFMSKI)
69697 #define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
69704 #define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
69705 #define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
69709 #define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
69710 #define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
69714 #define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
69715 #define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
69721 #define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
69722 #define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
69726 #define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
69727 #define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
69731 #define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
69732 #define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
69738 #define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
69739 #define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
69745 #define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
69746 #define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
69752 #define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
69753 #define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
69759 #define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
69760 #define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
69764 #define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
69765 #define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
69767 #define S_DFI_INIT_START0    1
69768 #define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
69769 #define F_DFI_INIT_START0    V_DFI_INIT_START0(1U)
69772 #define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
69773 #define F_DFI_INIT_COMPLETE    V_DFI_INIT_COMPLETE(1U)
69778 #define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
69779 #define F_DFI_DATA_BYTE_DISABLE_EN    V_DFI_DATA_BYTE_DISABLE_EN(1U)
69781 #define S_DFI_FREQ_RATIO_EN    1
69782 #define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
69783 #define F_DFI_FREQ_RATIO_EN    V_DFI_FREQ_RATIO_EN(1U)
69786 #define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
69787 #define F_DFI_INIT_START    V_DFI_INIT_START(1U)
69791 #define S_DFI_DRAM_CLK_DISABLE_EN_DPD    1
69792 #define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
69793 #define F_DFI_DRAM_CLK_DISABLE_EN_DPD    V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
69796 #define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
69797 #define F_DFI_DRAM_CLK_DISABLE_EN    V_DFI_DRAM_CLK_DISABLE_EN(1U)
69803 #define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
69804 #define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
69810 #define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
69811 #define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
69815 #define S_PARITY_EN    1
69816 #define V_PARITY_EN(x) ((x) << S_PARITY_EN)
69817 #define F_PARITY_EN    V_PARITY_EN(1U)
69820 #define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
69821 #define F_PARITY_INTR_EN    V_PARITY_INTR_EN(1U)
69825 #define S_PARITY_LOG_CLR    1
69826 #define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
69827 #define F_PARITY_LOG_CLR    V_PARITY_LOG_CLR(1U)
69830 #define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
69831 #define F_PARITY_INTR_CLR    V_PARITY_INTR_CLR(1U)
69838 #define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
69839 #define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
69842 #define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
69843 #define F_DFI_LP_EN_DPD    V_DFI_LP_EN_DPD(1U)
69847 #define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
69848 #define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
69851 #define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
69852 #define F_DFI_LP_EN_SR    V_DFI_LP_EN_SR(1U)
69856 #define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
69857 #define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
69860 #define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
69861 #define F_DFI_LP_EN_PD    V_DFI_LP_EN_PD(1U)
69869 #define V_PHYUPD_ERR(x) ((x) << S_PHYUPD_ERR)
69870 #define G_PHYUPD_ERR(x) (((x) >> S_PHYUPD_ERR) & M_PHYUPD_ERR)
69873 #define V_PHYUPD_BUSY(x) ((x) << S_PHYUPD_BUSY)
69874 #define F_PHYUPD_BUSY    V_PHYUPD_BUSY(1U)
69880 #define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
69881 #define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
69889 #define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
69890 #define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
69898 #define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
69899 #define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
69907 #define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
69908 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
69918 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
69919 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
69925 #define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
69926 #define F_DFITRCMD_START    V_DFITRCMD_START(1U)
69930 #define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
69931 #define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
69935 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
69936 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
69945 #define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
69946 #define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
69949 #define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
69950 #define F_PHY_CALIB_DONE    V_PHY_CALIB_DONE(1U)
69953 #define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
69954 #define F_CTL_CAL_REQ    V_CTL_CAL_REQ(1U)
69957 #define V_CTL_CKE(x) ((x) << S_CTL_CKE)
69958 #define F_CTL_CKE    V_CTL_CKE(1U)
69961 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
69962 #define F_CTL_RST_N    V_CTL_RST_N(1U)
69965 #define V_PHY_CAL_REQ(x) ((x) << S_PHY_CAL_REQ)
69966 #define F_PHY_CAL_REQ    V_PHY_CAL_REQ(1U)
69970 #define V_T6_PHY_DRAM_WL(x) ((x) << S_T6_PHY_DRAM_WL)
69971 #define G_T6_PHY_DRAM_WL(x) (((x) >> S_T6_PHY_DRAM_WL) & M_T6_PHY_DRAM_WL)
69977 #define V_BUF_USE_TH(x) ((x) << S_BUF_USE_TH)
69978 #define G_BUF_USE_TH(x) (((x) >> S_BUF_USE_TH) & M_BUF_USE_TH)
69982 #define V_MC_IDLE_TH(x) ((x) << S_MC_IDLE_TH)
69983 #define G_MC_IDLE_TH(x) (((x) >> S_MC_IDLE_TH) & M_MC_IDLE_TH)
69986 #define V_RMW_DEFER_EN(x) ((x) << S_RMW_DEFER_EN)
69987 #define F_RMW_DEFER_EN    V_RMW_DEFER_EN(1U)
69990 #define V_DDR3_BRBC_MODE(x) ((x) << S_DDR3_BRBC_MODE)
69991 #define F_DDR3_BRBC_MODE    V_DDR3_BRBC_MODE(1U)
69994 #define V_RMW_DWRITE_EN(x) ((x) << S_RMW_DWRITE_EN)
69995 #define F_RMW_DWRITE_EN    V_RMW_DWRITE_EN(1U)
69998 #define V_RMW_MERGE_EN(x) ((x) << S_RMW_MERGE_EN)
69999 #define F_RMW_MERGE_EN    V_RMW_MERGE_EN(1U)
70002 #define V_SYNC_PAB_EN(x) ((x) << S_SYNC_PAB_EN)
70003 #define F_SYNC_PAB_EN    V_SYNC_PAB_EN(1U)
70015 #define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
70016 #define F_STATIC_AWEN    V_STATIC_AWEN(1U)
70020 #define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
70021 #define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
70024 #define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
70025 #define F_STATIC_WLAT    V_STATIC_WLAT(1U)
70028 #define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
70029 #define F_STATIC_ALIGN    V_STATIC_ALIGN(1U)
70033 #define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
70034 #define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
70037 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
70038 #define F_STATIC_LAT    V_STATIC_LAT(1U)
70041 #define V_STATIC_PP64(x) ((x) << S_STATIC_PP64)
70042 #define F_STATIC_PP64    V_STATIC_PP64(1U)
70045 #define V_STATIC_PPEN(x) ((x) << S_STATIC_PPEN)
70046 #define F_STATIC_PPEN    V_STATIC_PPEN(1U)
70049 #define V_STATIC_OOOEN(x) ((x) << S_STATIC_OOOEN)
70050 #define F_STATIC_OOOEN    V_STATIC_OOOEN(1U)
70062 #define S_SLEEPSTATUS    1
70063 #define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
70064 #define F_SLEEPSTATUS    V_SLEEPSTATUS(1U)
70067 #define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
70068 #define F_SLEEPREQ    V_SLEEPREQ(1U)
70076 #define V_ADR_CK_EN(x) ((x) << S_ADR_CK_EN)
70077 #define F_ADR_CK_EN    V_ADR_CK_EN(1U)
70087 #define V_WR_HI_TH(x) ((x) << S_WR_HI_TH)
70088 #define G_WR_HI_TH(x) (((x) >> S_WR_HI_TH) & M_WR_HI_TH)
70092 #define V_WR_MID_TH(x) ((x) << S_WR_MID_TH)
70093 #define G_WR_MID_TH(x) (((x) >> S_WR_MID_TH) & M_WR_MID_TH)
70097 #define V_RD_HI_TH(x) ((x) << S_RD_HI_TH)
70098 #define G_RD_HI_TH(x) (((x) >> S_RD_HI_TH) & M_RD_HI_TH)
70102 #define V_RD_MID_TH(x) ((x) << S_RD_MID_TH)
70103 #define G_RD_MID_TH(x) (((x) >> S_RD_MID_TH) & M_RD_MID_TH)
70109 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
70110 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
70123 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
70124 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
70129 #define V_MASK_128_1(x) ((x) << S_MASK_128_1)
70130 #define F_MASK_128_1    V_MASK_128_1(1U)
70133 #define V_MASK_128_0(x) ((x) << S_MASK_128_0)
70134 #define F_MASK_128_0    V_MASK_128_0(1U)
70138 #define V_USER_MASK_ECC(x) ((x) << S_USER_MASK_ECC)
70139 #define G_USER_MASK_ECC(x) (((x) >> S_USER_MASK_ECC) & M_USER_MASK_ECC)
70149 #define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
70150 #define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
70156 #define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
70157 #define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
70160 #define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
70161 #define F_DFT_FORCE_OUTPUTS    V_DFT_FORCE_OUTPUTS(1U)
70164 #define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
70165 #define F_DFT_PRBS7_GEN_EN    V_DFT_PRBS7_GEN_EN(1U)
70168 #define V_WRAPSEL(x) ((x) << S_WRAPSEL)
70169 #define F_WRAPSEL    V_WRAPSEL(1U)
70172 #define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
70173 #define F_MRS_CMD_DATA_N0    V_MRS_CMD_DATA_N0(1U)
70176 #define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
70177 #define F_MRS_CMD_DATA_N1    V_MRS_CMD_DATA_N1(1U)
70179 #define S_MRS_CMD_DATA_N2    1
70180 #define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
70181 #define F_MRS_CMD_DATA_N2    V_MRS_CMD_DATA_N2(1U)
70184 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
70185 #define F_MRS_CMD_DATA_N3    V_MRS_CMD_DATA_N3(1U)
70188 #define V_DP18_WRAPSEL(x) ((x) << S_DP18_WRAPSEL)
70189 #define F_DP18_WRAPSEL    V_DP18_WRAPSEL(1U)
70192 #define V_HW_VALUE(x) ((x) << S_HW_VALUE)
70193 #define F_HW_VALUE    V_HW_VALUE(1U)
70199 #define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
70200 #define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
70206 #define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
70207 #define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
70210 #define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
70211 #define F_WL_ADVANCE_DISABLE    V_WL_ADVANCE_DISABLE(1U)
70214 #define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
70215 #define F_DISABLE_PING_PONG    V_DISABLE_PING_PONG(1U)
70218 #define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
70219 #define F_DELAY_PING_PONG_HALF    V_DELAY_PING_PONG_HALF(1U)
70222 #define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
70223 #define F_ADVANCE_PING_PONG    V_ADVANCE_PING_PONG(1U)
70226 #define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
70227 #define F_ATEST_MUX_CTL0    V_ATEST_MUX_CTL0(1U)
70230 #define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
70231 #define F_ATEST_MUX_CTL1    V_ATEST_MUX_CTL1(1U)
70233 #define S_ATEST_MUX_CTL2    1
70234 #define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
70235 #define F_ATEST_MUX_CTL2    V_ATEST_MUX_CTL2(1U)
70238 #define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
70239 #define F_ATEST_MUX_CTL3    V_ATEST_MUX_CTL3(1U)
70244 #define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
70245 #define F_QUAD0_CLK16_BIT0    V_QUAD0_CLK16_BIT0(1U)
70248 #define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
70249 #define F_QUAD1_CLK16_BIT1    V_QUAD1_CLK16_BIT1(1U)
70252 #define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
70253 #define F_QUAD2_CLK16_BIT2    V_QUAD2_CLK16_BIT2(1U)
70256 #define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
70257 #define F_QUAD3_CLK16_BIT3    V_QUAD3_CLK16_BIT3(1U)
70260 #define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
70261 #define F_QUAD0_CLK18_BIT4    V_QUAD0_CLK18_BIT4(1U)
70264 #define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
70265 #define F_QUAD1_CLK18_BIT5    V_QUAD1_CLK18_BIT5(1U)
70268 #define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
70269 #define F_QUAD2_CLK20_BIT6    V_QUAD2_CLK20_BIT6(1U)
70272 #define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
70273 #define F_QUAD3_CLK20_BIT7    V_QUAD3_CLK20_BIT7(1U)
70276 #define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
70277 #define F_QUAD2_CLK22_BIT8    V_QUAD2_CLK22_BIT8(1U)
70280 #define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
70281 #define F_QUAD3_CLK22_BIT9    V_QUAD3_CLK22_BIT9(1U)
70284 #define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
70285 #define F_CLK16_SINGLE_ENDED_BIT10    V_CLK16_SINGLE_ENDED_BIT10(1U)
70288 #define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
70289 #define F_CLK18_SINGLE_ENDED_BIT11    V_CLK18_SINGLE_ENDED_BIT11(1U)
70292 #define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
70293 #define F_CLK20_SINGLE_ENDED_BIT12    V_CLK20_SINGLE_ENDED_BIT12(1U)
70296 #define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
70297 #define F_CLK22_SINGLE_ENDED_BIT13    V_CLK22_SINGLE_ENDED_BIT13(1U)
70301 #define S_QUAD2_CLK18_BIT14    1
70302 #define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
70303 #define F_QUAD2_CLK18_BIT14    V_QUAD2_CLK18_BIT14(1U)
70306 #define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
70307 #define F_QUAD3_CLK18_BIT15    V_QUAD3_CLK18_BIT15(1U)
70313 #define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
70314 #define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
70318 #define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
70319 #define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
70323 #define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
70324 #define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
70327 #define V_SXPODVREF(x) ((x) << S_SXPODVREF)
70328 #define F_SXPODVREF    V_SXPODVREF(1U)
70331 #define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
70332 #define F_DISABLE_TERMINATION    V_DISABLE_TERMINATION(1U)
70336 #define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
70337 #define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
70342 #define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
70343 #define F_SYSCLK_PHASE_ALIGN_RESET    V_SYSCLK_PHASE_ALIGN_RESET(1U)
70348 #define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
70349 #define F_DIGITAL_EYE_EN    V_DIGITAL_EYE_EN(1U)
70352 #define V_BUMP(x) ((x) << S_BUMP)
70353 #define F_BUMP    V_BUMP(1U)
70356 #define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
70357 #define F_TRIG_PERIOD    V_TRIG_PERIOD(1U)
70360 #define V_CNTL_POL(x) ((x) << S_CNTL_POL)
70361 #define F_CNTL_POL    V_CNTL_POL(1U)
70364 #define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
70365 #define F_CNTL_SRC    V_CNTL_SRC(1U)
70369 #define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
70370 #define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
70376 #define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
70377 #define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
70381 #define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
70382 #define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
70386 #define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
70387 #define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
70391 #define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
70392 #define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
70396 #define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
70397 #define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
70401 #define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
70402 #define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
70406 #define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
70407 #define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
70411 #define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
70412 #define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
70418 #define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
70419 #define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
70423 #define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
70424 #define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
70430 #define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
70431 #define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
70435 #define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
70436 #define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
70440 #define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
70441 #define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
70445 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
70446 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
70450 #define V_DP18_HS_PROBE_A_SEL(x) ((x) << S_DP18_HS_PROBE_A_SEL)
70451 #define G_DP18_HS_PROBE_A_SEL(x) (((x) >> S_DP18_HS_PROBE_A_SEL) & M_DP18_HS_PROBE_A_SEL)
70455 #define V_DP18_HS_PROBE_B_SEL(x) ((x) << S_DP18_HS_PROBE_B_SEL)
70456 #define G_DP18_HS_PROBE_B_SEL(x) (((x) >> S_DP18_HS_PROBE_B_SEL) & M_DP18_HS_PROBE_B_SEL)
70462 #define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
70463 #define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
70467 #define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
70468 #define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
70475 #define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
70476 #define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
70482 #define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
70483 #define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
70489 #define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
70490 #define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
70496 #define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
70497 #define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
70502 #define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
70503 #define F_DYN_POWER_CNTL_EN    V_DYN_POWER_CNTL_EN(1U)
70506 #define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
70507 #define F_DYN_MCTERM_CNTL_EN    V_DYN_MCTERM_CNTL_EN(1U)
70510 #define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
70511 #define F_DYN_RX_GATE_CNTL_EN    V_DYN_RX_GATE_CNTL_EN(1U)
70514 #define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
70515 #define F_CALGATE_ON    V_CALGATE_ON(1U)
70518 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
70519 #define F_PER_RDCLK_UPDATE_DIS    V_PER_RDCLK_UPDATE_DIS(1U)
70522 #define V_DQS_ALIGN_BY_QUAD(x) ((x) << S_DQS_ALIGN_BY_QUAD)
70523 #define F_DQS_ALIGN_BY_QUAD    V_DQS_ALIGN_BY_QUAD(1U)
70529 #define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
70530 #define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
70534 #define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
70535 #define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
70539 #define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
70540 #define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
70544 #define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
70545 #define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
70550 #define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
70551 #define F_NO_EYE_DETECTED    V_NO_EYE_DETECTED(1U)
70554 #define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
70555 #define F_LEADING_EDGE_FOUND    V_LEADING_EDGE_FOUND(1U)
70558 #define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
70559 #define F_TRAILING_EDGE_FOUND    V_TRAILING_EDGE_FOUND(1U)
70562 #define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
70563 #define F_INCOMPLETE_RD_CAL_N0    V_INCOMPLETE_RD_CAL_N0(1U)
70566 #define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
70567 #define F_INCOMPLETE_RD_CAL_N1    V_INCOMPLETE_RD_CAL_N1(1U)
70570 #define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
70571 #define F_INCOMPLETE_RD_CAL_N2    V_INCOMPLETE_RD_CAL_N2(1U)
70574 #define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
70575 #define F_INCOMPLETE_RD_CAL_N3    V_INCOMPLETE_RD_CAL_N3(1U)
70578 #define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
70579 #define F_COARSE_PATTERN_ERR_N0    V_COARSE_PATTERN_ERR_N0(1U)
70582 #define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
70583 #define F_COARSE_PATTERN_ERR_N1    V_COARSE_PATTERN_ERR_N1(1U)
70586 #define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
70587 #define F_COARSE_PATTERN_ERR_N2    V_COARSE_PATTERN_ERR_N2(1U)
70590 #define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
70591 #define F_COARSE_PATTERN_ERR_N3    V_COARSE_PATTERN_ERR_N3(1U)
70594 #define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
70595 #define F_EYE_CLIPPING    V_EYE_CLIPPING(1U)
70598 #define V_NO_DQS(x) ((x) << S_NO_DQS)
70599 #define F_NO_DQS    V_NO_DQS(1U)
70602 #define V_NO_LOCK(x) ((x) << S_NO_LOCK)
70603 #define F_NO_LOCK    V_NO_LOCK(1U)
70605 #define S_DRIFT_ERROR    1
70606 #define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
70607 #define F_DRIFT_ERROR    V_DRIFT_ERROR(1U)
70610 #define V_MIN_EYE(x) ((x) << S_MIN_EYE)
70611 #define F_MIN_EYE    V_MIN_EYE(1U)
70616 #define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
70617 #define F_NO_EYE_DETECTED_MASK    V_NO_EYE_DETECTED_MASK(1U)
70620 #define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
70621 #define F_LEADING_EDGE_FOUND_MASK    V_LEADING_EDGE_FOUND_MASK(1U)
70624 #define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
70625 #define F_TRAILING_EDGE_FOUND_MASK    V_TRAILING_EDGE_FOUND_MASK(1U)
70628 #define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
70629 #define F_INCOMPLETE_RD_CAL_N0_MASK    V_INCOMPLETE_RD_CAL_N0_MASK(1U)
70632 #define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
70633 #define F_INCOMPLETE_RD_CAL_N1_MASK    V_INCOMPLETE_RD_CAL_N1_MASK(1U)
70636 #define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
70637 #define F_INCOMPLETE_RD_CAL_N2_MASK    V_INCOMPLETE_RD_CAL_N2_MASK(1U)
70640 #define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
70641 #define F_INCOMPLETE_RD_CAL_N3_MASK    V_INCOMPLETE_RD_CAL_N3_MASK(1U)
70644 #define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
70645 #define F_COARSE_PATTERN_ERR_N0_MASK    V_COARSE_PATTERN_ERR_N0_MASK(1U)
70648 #define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
70649 #define F_COARSE_PATTERN_ERR_N1_MASK    V_COARSE_PATTERN_ERR_N1_MASK(1U)
70652 #define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
70653 #define F_COARSE_PATTERN_ERR_N2_MASK    V_COARSE_PATTERN_ERR_N2_MASK(1U)
70656 #define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
70657 #define F_COARSE_PATTERN_ERR_N3_MASK    V_COARSE_PATTERN_ERR_N3_MASK(1U)
70660 #define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
70661 #define F_EYE_CLIPPING_MASK    V_EYE_CLIPPING_MASK(1U)
70664 #define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
70665 #define F_NO_DQS_MASK    V_NO_DQS_MASK(1U)
70668 #define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
70669 #define F_NO_LOCK_MASK    V_NO_LOCK_MASK(1U)
70671 #define S_DRIFT_ERROR_MASK    1
70672 #define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
70673 #define F_DRIFT_ERROR_MASK    V_DRIFT_ERROR_MASK(1U)
70676 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
70677 #define F_MIN_EYE_MASK    V_MIN_EYE_MASK(1U)
70683 #define V_PRBS_WAIT(x) ((x) << S_PRBS_WAIT)
70684 #define G_PRBS_WAIT(x) (((x) >> S_PRBS_WAIT) & M_PRBS_WAIT)
70687 #define V_PRBS_SYNC_EARLY(x) ((x) << S_PRBS_SYNC_EARLY)
70688 #define F_PRBS_SYNC_EARLY    V_PRBS_SYNC_EARLY(1U)
70691 #define V_RD_DELAY_EARLY(x) ((x) << S_RD_DELAY_EARLY)
70692 #define F_RD_DELAY_EARLY    V_RD_DELAY_EARLY(1U)
70695 #define V_SS_QUAD_CAL(x) ((x) << S_SS_QUAD_CAL)
70696 #define F_SS_QUAD_CAL    V_SS_QUAD_CAL(1U)
70700 #define V_SS_QUAD(x) ((x) << S_SS_QUAD)
70701 #define G_SS_QUAD(x) (((x) >> S_SS_QUAD) & M_SS_QUAD)
70704 #define V_SS_RD_DELAY(x) ((x) << S_SS_RD_DELAY)
70705 #define F_SS_RD_DELAY    V_SS_RD_DELAY(1U)
70708 #define V_FORCE_HI_Z(x) ((x) << S_FORCE_HI_Z)
70709 #define F_FORCE_HI_Z    V_FORCE_HI_Z(1U)
70715 #define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
70716 #define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
70719 #define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
70720 #define F_FINE_STEPPING    V_FINE_STEPPING(1U)
70723 #define V_DONE(x) ((x) << S_DONE)
70724 #define F_DONE    V_DONE(1U)
70727 #define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
70728 #define F_WL_ERR_CLK16_ST    V_WL_ERR_CLK16_ST(1U)
70731 #define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
70732 #define F_WL_ERR_CLK18_ST    V_WL_ERR_CLK18_ST(1U)
70735 #define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
70736 #define F_WL_ERR_CLK20_ST    V_WL_ERR_CLK20_ST(1U)
70739 #define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
70740 #define F_WL_ERR_CLK22_ST    V_WL_ERR_CLK22_ST(1U)
70743 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
70744 #define F_ZERO_DETECTED    V_ZERO_DETECTED(1U)
70747 #define V_WR_LVL_DONE(x) ((x) << S_WR_LVL_DONE)
70748 #define F_WR_LVL_DONE    V_WR_LVL_DONE(1U)
70754 #define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
70755 #define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
70758 #define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
70759 #define F_SMALL_STEP_LEFT    V_SMALL_STEP_LEFT(1U)
70762 #define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
70763 #define F_BIG_STEP_RIGHT    V_BIG_STEP_RIGHT(1U)
70766 #define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
70767 #define F_MATCH_STEP_RIGHT    V_MATCH_STEP_RIGHT(1U)
70770 #define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
70771 #define F_JUMP_BACK_RIGHT    V_JUMP_BACK_RIGHT(1U)
70774 #define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
70775 #define F_SMALL_STEP_RIGHT    V_SMALL_STEP_RIGHT(1U)
70778 #define V_DDONE(x) ((x) << S_DDONE)
70779 #define F_DDONE    V_DDONE(1U)
70782 #define V_WR_CNTR_DONE(x) ((x) << S_WR_CNTR_DONE)
70783 #define F_WR_CNTR_DONE    V_WR_CNTR_DONE(1U)
70789 #define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
70790 #define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
70796 #define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
70797 #define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
70802 #define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
70803 #define F_WL_ERR_CLK16    V_WL_ERR_CLK16(1U)
70806 #define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
70807 #define F_WL_ERR_CLK18    V_WL_ERR_CLK18(1U)
70810 #define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
70811 #define F_WL_ERR_CLK20    V_WL_ERR_CLK20(1U)
70814 #define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
70815 #define F_WL_ERR_CLK22    V_WL_ERR_CLK22(1U)
70818 #define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
70819 #define F_VALID_NS_BIG_L    V_VALID_NS_BIG_L(1U)
70822 #define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
70823 #define F_INVALID_NS_SMALL_L    V_INVALID_NS_SMALL_L(1U)
70826 #define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
70827 #define F_VALID_NS_BIG_R    V_VALID_NS_BIG_R(1U)
70830 #define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
70831 #define F_INVALID_NS_BIG_R    V_INVALID_NS_BIG_R(1U)
70834 #define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
70835 #define F_VALID_NS_JUMP_BACK    V_VALID_NS_JUMP_BACK(1U)
70838 #define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
70839 #define F_INVALID_NS_SMALL_R    V_INVALID_NS_SMALL_R(1U)
70841 #define S_OFFSET_ERR    1
70842 #define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
70843 #define F_OFFSET_ERR    V_OFFSET_ERR(1U)
70848 #define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
70849 #define F_WL_ERR_CLK16_MASK    V_WL_ERR_CLK16_MASK(1U)
70852 #define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
70853 #define F_WL_ERR_CLK18_MASK    V_WL_ERR_CLK18_MASK(1U)
70856 #define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
70857 #define F_WL_ERR_CLK20_MASK    V_WL_ERR_CLK20_MASK(1U)
70860 #define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
70861 #define F_WR_ERR_CLK22_MASK    V_WR_ERR_CLK22_MASK(1U)
70864 #define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
70865 #define F_VALID_NS_BIG_L_MASK    V_VALID_NS_BIG_L_MASK(1U)
70868 #define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
70869 #define F_INVALID_NS_SMALL_L_MASK    V_INVALID_NS_SMALL_L_MASK(1U)
70872 #define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
70873 #define F_VALID_NS_BIG_R_MASK    V_VALID_NS_BIG_R_MASK(1U)
70876 #define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
70877 #define F_INVALID_NS_BIG_R_MASK    V_INVALID_NS_BIG_R_MASK(1U)
70880 #define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
70881 #define F_VALID_NS_JUMP_BACK_MASK    V_VALID_NS_JUMP_BACK_MASK(1U)
70884 #define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
70885 #define F_INVALID_NS_SMALL_R_MASK    V_INVALID_NS_SMALL_R_MASK(1U)
70887 #define S_OFFSET_ERR_MASK    1
70888 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
70889 #define F_OFFSET_ERR_MASK    V_OFFSET_ERR_MASK(1U)
70892 #define V_DQS_REC_LOW_POWER(x) ((x) << S_DQS_REC_LOW_POWER)
70893 #define F_DQS_REC_LOW_POWER    V_DQS_REC_LOW_POWER(1U)
70896 #define V_DQ_REC_LOW_POWER(x) ((x) << S_DQ_REC_LOW_POWER)
70897 #define F_DQ_REC_LOW_POWER    V_DQ_REC_LOW_POWER(1U)
70900 #define V_ADVANCE_PR_VALUE(x) ((x) << S_ADVANCE_PR_VALUE)
70901 #define F_ADVANCE_PR_VALUE    V_ADVANCE_PR_VALUE(1U)
70906 #define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
70907 #define F_CHECKER_RESET    V_CHECKER_RESET(1U)
70911 #define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
70912 #define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
70916 #define V_ERROR(x) ((x) << S_ERROR)
70917 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
70920 #define V_CHECKER_ENABLE(x) ((x) << S_CHECKER_ENABLE)
70921 #define F_CHECKER_ENABLE    V_CHECKER_ENABLE(1U)
70925 #define V_DP18_DFT_ERROR(x) ((x) << S_DP18_DFT_ERROR)
70926 #define G_DP18_DFT_ERROR(x) (((x) >> S_DP18_DFT_ERROR) & M_DP18_DFT_ERROR)
70932 #define V_SYSCLK_RDCLK_OFFSET(x) ((x) << S_SYSCLK_RDCLK_OFFSET)
70933 #define G_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_SYSCLK_RDCLK_OFFSET) & M_SYSCLK_RDCLK_OFFSET)
70937 #define V_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_SYSCLK_DQSCLK_OFFSET)
70938 #define G_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_SYSCLK_DQSCLK_OFFSET) & M_SYSCLK_DQSCLK_OFFSET)
70942 #define V_T6_SYSCLK_DQSCLK_OFFSET(x) ((x) << S_T6_SYSCLK_DQSCLK_OFFSET)
70943 #define G_T6_SYSCLK_DQSCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_DQSCLK_OFFSET) & M_T6_SYSCLK_DQSCLK_OFFSET)
70947 #define V_T6_SYSCLK_RDCLK_OFFSET(x) ((x) << S_T6_SYSCLK_RDCLK_OFFSET)
70948 #define G_T6_SYSCLK_RDCLK_OFFSET(x) (((x) >> S_T6_SYSCLK_RDCLK_OFFSET) & M_T6_SYSCLK_RDCLK_OFFSET)
70955 #define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
70956 #define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
70960 #define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
70961 #define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
70968 #define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
70969 #define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
70973 #define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
70974 #define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
70978 #define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
70979 #define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
70983 #define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
70984 #define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
70988 #define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
70989 #define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
70993 #define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
70994 #define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
70998 #define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
70999 #define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
71003 #define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
71004 #define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
71010 #define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
71011 #define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
71015 #define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
71016 #define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
71020 #define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
71021 #define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
71025 #define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
71026 #define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
71030 #define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
71031 #define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
71035 #define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
71036 #define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
71040 #define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
71041 #define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
71045 #define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
71046 #define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
71052 #define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
71053 #define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
71057 #define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
71058 #define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
71062 #define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
71063 #define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
71067 #define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
71068 #define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
71072 #define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
71073 #define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
71077 #define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
71078 #define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
71082 #define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
71083 #define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
71087 #define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
71088 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
71094 #define V_DQS_ALIGN_SM(x) ((x) << S_DQS_ALIGN_SM)
71095 #define G_DQS_ALIGN_SM(x) (((x) >> S_DQS_ALIGN_SM) & M_DQS_ALIGN_SM)
71099 #define V_DQS_ALIGN_CNTR(x) ((x) << S_DQS_ALIGN_CNTR)
71100 #define G_DQS_ALIGN_CNTR(x) (((x) >> S_DQS_ALIGN_CNTR) & M_DQS_ALIGN_CNTR)
71103 #define V_ITERATION_CNTR(x) ((x) << S_ITERATION_CNTR)
71104 #define F_ITERATION_CNTR    V_ITERATION_CNTR(1U)
71108 #define V_DQS_ALIGN_ITER_CNTR(x) ((x) << S_DQS_ALIGN_ITER_CNTR)
71109 #define G_DQS_ALIGN_ITER_CNTR(x) (((x) >> S_DQS_ALIGN_ITER_CNTR) & M_DQS_ALIGN_ITER_CNTR)
71115 #define V_CALIBRATE_BIT(x) ((x) << S_CALIBRATE_BIT)
71116 #define G_CALIBRATE_BIT(x) (((x) >> S_CALIBRATE_BIT) & M_CALIBRATE_BIT)
71120 #define V_DQS_ALIGN_QUAD(x) ((x) << S_DQS_ALIGN_QUAD)
71121 #define G_DQS_ALIGN_QUAD(x) (((x) >> S_DQS_ALIGN_QUAD) & M_DQS_ALIGN_QUAD)
71125 #define V_DQS_QUAD_CONFIG(x) ((x) << S_DQS_QUAD_CONFIG)
71126 #define G_DQS_QUAD_CONFIG(x) (((x) >> S_DQS_QUAD_CONFIG) & M_DQS_QUAD_CONFIG)
71130 #define V_OPERATE_MODE(x) ((x) << S_OPERATE_MODE)
71131 #define G_OPERATE_MODE(x) (((x) >> S_OPERATE_MODE) & M_OPERATE_MODE)
71134 #define V_EN_DQS_OFFSET(x) ((x) << S_EN_DQS_OFFSET)
71135 #define F_EN_DQS_OFFSET    V_EN_DQS_OFFSET(1U)
71138 #define V_DQS_ALIGN_JITTER(x) ((x) << S_DQS_ALIGN_JITTER)
71139 #define F_DQS_ALIGN_JITTER    V_DQS_ALIGN_JITTER(1U)
71141 #define S_DIS_CLK_GATE    1
71142 #define V_DIS_CLK_GATE(x) ((x) << S_DIS_CLK_GATE)
71143 #define F_DIS_CLK_GATE    V_DIS_CLK_GATE(1U)
71146 #define V_MAX_DQS_ITER(x) ((x) << S_MAX_DQS_ITER)
71147 #define F_MAX_DQS_ITER    V_MAX_DQS_ITER(1U)
71153 #define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
71154 #define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
71160 #define V_WR_DELAY(x) ((x) << S_WR_DELAY)
71161 #define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
71190 #define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
71191 #define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
71193 #define S_RD_DELAY_BITS8_14    1
71195 #define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
71196 #define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
71213 #define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
71214 #define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
71218 #define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
71219 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
71225 #define V_WRCLK_CALIB_DONE(x) ((x) << S_WRCLK_CALIB_DONE)
71226 #define F_WRCLK_CALIB_DONE    V_WRCLK_CALIB_DONE(1U)
71229 #define V_VALUE_UPDATED(x) ((x) << S_VALUE_UPDATED)
71230 #define F_VALUE_UPDATED    V_VALUE_UPDATED(1U)
71233 #define V_FAIL_PASS_V(x) ((x) << S_FAIL_PASS_V)
71234 #define F_FAIL_PASS_V    V_FAIL_PASS_V(1U)
71237 #define V_PASS_FAIL_V(x) ((x) << S_PASS_FAIL_V)
71238 #define F_PASS_FAIL_V    V_PASS_FAIL_V(1U)
71241 #define V_FP_PF_EDGE_NF(x) ((x) << S_FP_PF_EDGE_NF)
71242 #define F_FP_PF_EDGE_NF    V_FP_PF_EDGE_NF(1U)
71245 #define V_NON_SYMETRIC(x) ((x) << S_NON_SYMETRIC)
71246 #define F_NON_SYMETRIC    V_NON_SYMETRIC(1U)
71249 #define V_FULL_RANGE(x) ((x) << S_FULL_RANGE)
71250 #define F_FULL_RANGE    V_FULL_RANGE(1U)
71253 #define V_QUAD3_EDGES(x) ((x) << S_QUAD3_EDGES)
71254 #define F_QUAD3_EDGES    V_QUAD3_EDGES(1U)
71257 #define V_QUAD2_EDGES(x) ((x) << S_QUAD2_EDGES)
71258 #define F_QUAD2_EDGES    V_QUAD2_EDGES(1U)
71261 #define V_QUAD1_EDGES(x) ((x) << S_QUAD1_EDGES)
71262 #define F_QUAD1_EDGES    V_QUAD1_EDGES(1U)
71265 #define V_QUAD0_EDGES(x) ((x) << S_QUAD0_EDGES)
71266 #define F_QUAD0_EDGES    V_QUAD0_EDGES(1U)
71269 #define V_QUAD3_CAVEAT(x) ((x) << S_QUAD3_CAVEAT)
71270 #define F_QUAD3_CAVEAT    V_QUAD3_CAVEAT(1U)
71273 #define V_QUAD2_CAVEAT(x) ((x) << S_QUAD2_CAVEAT)
71274 #define F_QUAD2_CAVEAT    V_QUAD2_CAVEAT(1U)
71276 #define S_QUAD1_CAVEAT    1
71277 #define V_QUAD1_CAVEAT(x) ((x) << S_QUAD1_CAVEAT)
71278 #define F_QUAD1_CAVEAT    V_QUAD1_CAVEAT(1U)
71281 #define V_QUAD0_CAVEAT(x) ((x) << S_QUAD0_CAVEAT)
71282 #define F_QUAD0_CAVEAT    V_QUAD0_CAVEAT(1U)
71288 #define V_FAIL_PASS_VALUE(x) ((x) << S_FAIL_PASS_VALUE)
71289 #define G_FAIL_PASS_VALUE(x) (((x) >> S_FAIL_PASS_VALUE) & M_FAIL_PASS_VALUE)
71293 #define V_PASS_FAIL_VALUE(x) ((x) << S_PASS_FAIL_VALUE)
71294 #define G_PASS_FAIL_VALUE(x) (((x) >> S_PASS_FAIL_VALUE) & M_PASS_FAIL_VALUE)
71300 #define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
71301 #define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
71305 #define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
71306 #define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
71323 #define V_DESIRED_EDGE_CNTR_TARGET_HIGH(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_HIGH)
71324 #define G_DESIRED_EDGE_CNTR_TARGET_HIGH(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_HIGH) & M_DESIRED_EDGE_CNTR_TARGET_HIGH)
71328 #define V_DESIRED_EDGE_CNTR_TARGET_LOW(x) ((x) << S_DESIRED_EDGE_CNTR_TARGET_LOW)
71329 #define G_DESIRED_EDGE_CNTR_TARGET_LOW(x) (((x) >> S_DESIRED_EDGE_CNTR_TARGET_LOW) & M_DESIRED_EDGE_CNTR_TARGET_LOW)
71334 #define V_APPROACH_ALIGNMENT(x) ((x) << S_APPROACH_ALIGNMENT)
71335 #define F_APPROACH_ALIGNMENT    V_APPROACH_ALIGNMENT(1U)
71341 #define V_QUAD0_PWR_CTL(x) ((x) << S_QUAD0_PWR_CTL)
71342 #define G_QUAD0_PWR_CTL(x) (((x) >> S_QUAD0_PWR_CTL) & M_QUAD0_PWR_CTL)
71346 #define V_QUAD1_PWR_CTL(x) ((x) << S_QUAD1_PWR_CTL)
71347 #define G_QUAD1_PWR_CTL(x) (((x) >> S_QUAD1_PWR_CTL) & M_QUAD1_PWR_CTL)
71351 #define V_QUAD2_PWR_CTL(x) ((x) << S_QUAD2_PWR_CTL)
71352 #define G_QUAD2_PWR_CTL(x) (((x) >> S_QUAD2_PWR_CTL) & M_QUAD2_PWR_CTL)
71356 #define V_QUAD3_PWR_CTL(x) ((x) << S_QUAD3_PWR_CTL)
71357 #define G_QUAD3_PWR_CTL(x) (((x) >> S_QUAD3_PWR_CTL) & M_QUAD3_PWR_CTL)
71363 #define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
71364 #define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
71368 #define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
71369 #define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
71376 #define V_REFERENCE(x) ((x) << S_REFERENCE)
71377 #define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
71385 #define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
71386 #define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
71390 #define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
71391 #define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
71395 #define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
71396 #define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
71402 #define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
71403 #define F_CE0DLTVCCA    V_CE0DLTVCCA(1U)
71406 #define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
71407 #define F_CE0DLTVCCD1    V_CE0DLTVCCD1(1U)
71410 #define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
71411 #define F_CE0DLTVCCD2    V_CE0DLTVCCD2(1U)
71414 #define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
71415 #define F_S0INSDLYTAP    V_S0INSDLYTAP(1U)
71417 #define S_S1INSDLYTAP    1
71418 #define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
71419 #define F_S1INSDLYTAP    V_S1INSDLYTAP(1U)
71425 #define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
71426 #define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
71433 #define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
71434 #define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
71438 #define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
71439 #define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
71445 #define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
71446 #define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
71450 #define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
71451 #define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
71457 #define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
71458 #define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
71464 #define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
71465 #define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
71471 #define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
71472 #define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
71476 #define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
71477 #define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
71481 #define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
71482 #define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
71486 #define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
71487 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
71492 #define V_EYEDAC_PD(x) ((x) << S_EYEDAC_PD)
71493 #define F_EYEDAC_PD    V_EYEDAC_PD(1U)
71496 #define V_ANALOG_OUTPUT_STAB(x) ((x) << S_ANALOG_OUTPUT_STAB)
71497 #define F_ANALOG_OUTPUT_STAB    V_ANALOG_OUTPUT_STAB(1U)
71501 #define V_DP18_RX_PD(x) ((x) << S_DP18_RX_PD)
71502 #define G_DP18_RX_PD(x) (((x) >> S_DP18_RX_PD) & M_DP18_RX_PD)
71505 #define V_DELAY_LINE_CTL_OVERRIDE(x) ((x) << S_DELAY_LINE_CTL_OVERRIDE)
71506 #define F_DELAY_LINE_CTL_OVERRIDE    V_DELAY_LINE_CTL_OVERRIDE(1U)
71509 #define V_VCC_REG_PD(x) ((x) << S_VCC_REG_PD)
71510 #define F_VCC_REG_PD    V_VCC_REG_PD(1U)
71516 #define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
71517 #define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
71521 #define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
71522 #define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
71527 #define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
71528 #define F_DI_ADR0_ADR1    V_DI_ADR0_ADR1(1U)
71531 #define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
71532 #define F_DI_ADR2_ADR3    V_DI_ADR2_ADR3(1U)
71535 #define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
71536 #define F_DI_ADR4_ADR5    V_DI_ADR4_ADR5(1U)
71539 #define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
71540 #define F_DI_ADR6_ADR7    V_DI_ADR6_ADR7(1U)
71543 #define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
71544 #define F_DI_ADR8_ADR9    V_DI_ADR8_ADR9(1U)
71547 #define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
71548 #define F_DI_ADR10_ADR11    V_DI_ADR10_ADR11(1U)
71551 #define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
71552 #define F_DI_ADR12_ADR13    V_DI_ADR12_ADR13(1U)
71555 #define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
71556 #define F_DI_ADR14_ADR15    V_DI_ADR14_ADR15(1U)
71562 #define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
71563 #define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
71567 #define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
71568 #define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
71581 #define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
71582 #define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
71585 #define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
71586 #define F_ADR_TEST_DATA_EN    V_ADR_TEST_DATA_EN(1U)
71590 #define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
71591 #define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
71594 #define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
71595 #define F_ADR_TEST_4TO1_MODE    V_ADR_TEST_4TO1_MODE(1U)
71598 #define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
71599 #define F_ADR_TEST_RESET    V_ADR_TEST_RESET(1U)
71602 #define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
71603 #define F_ADR_TEST_GEN_EN    V_ADR_TEST_GEN_EN(1U)
71605 #define S_ADR_TEST_CLEAR_ERROR    1
71606 #define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
71607 #define F_ADR_TEST_CLEAR_ERROR    V_ADR_TEST_CLEAR_ERROR(1U)
71610 #define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
71611 #define F_ADR_TEST_CHECK_EN    V_ADR_TEST_CHECK_EN(1U)
71617 #define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
71618 #define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
71622 #define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
71623 #define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
71629 #define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
71630 #define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
71636 #define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
71637 #define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
71643 #define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
71644 #define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
71650 #define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
71651 #define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
71655 #define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
71656 #define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
71665 #define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
71666 #define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
71670 #define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
71671 #define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
71675 #define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
71676 #define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
71680 #define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
71681 #define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
71687 #define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
71688 #define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
71692 #define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
71693 #define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
71697 #define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
71698 #define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
71702 #define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
71703 #define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
71709 #define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
71710 #define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
71714 #define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
71715 #define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
71719 #define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
71720 #define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
71724 #define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
71725 #define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
71729 #define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
71730 #define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
71734 #define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
71735 #define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
71739 #define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
71740 #define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
71744 #define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
71745 #define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
71752 #define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
71753 #define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
71757 #define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
71758 #define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
71762 #define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
71763 #define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
71767 #define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
71768 #define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
71772 #define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
71773 #define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
71777 #define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
71778 #define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
71782 #define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
71783 #define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
71787 #define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
71788 #define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
71795 #define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
71796 #define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
71800 #define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
71801 #define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
71805 #define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
71806 #define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
71810 #define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
71811 #define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
71815 #define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
71816 #define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
71820 #define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
71821 #define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
71825 #define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
71826 #define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
71830 #define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
71831 #define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
71838 #define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
71839 #define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
71843 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
71844 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
71860 #define V_ADR_TEST_MODE(x) ((x) << S_ADR_TEST_MODE)
71861 #define G_ADR_TEST_MODE(x) (((x) >> S_ADR_TEST_MODE) & M_ADR_TEST_MODE)
71884 #define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
71885 #define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
71889 #define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
71890 #define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
71894 #define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
71895 #define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
71899 #define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
71900 #define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
71904 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
71905 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
71912 #define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
71913 #define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
71917 #define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
71918 #define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
71921 #define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
71922 #define F_PLL_TUNEATST    V_PLL_TUNEATST(1U)
71926 #define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
71927 #define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
71930 #define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
71931 #define F_VREG_VREGSPARE    V_VREG_VREGSPARE(1U)
71935 #define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
71936 #define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
71938 #define S_INTERP_SIG_SLEW_0_3    1
71940 #define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
71941 #define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
71944 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
71945 #define F_ANALOG_WRAPON    V_ANALOG_WRAPON(1U)
71951 #define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
71952 #define F_SYSCLK_ENABLE    V_SYSCLK_ENABLE(1U)
71956 #define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
71957 #define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
71960 #define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
71961 #define F_SYSCLK_ROT_OVERRIDE_EN    V_SYSCLK_ROT_OVERRIDE_EN(1U)
71964 #define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
71965 #define F_SYSCLK_PHASE_ALIGN_RESE    V_SYSCLK_PHASE_ALIGN_RESE(1U)
71968 #define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
71969 #define F_SYSCLK_PHASE_CNTL_EN    V_SYSCLK_PHASE_CNTL_EN(1U)
71972 #define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
71973 #define F_SYSCLK_PHASE_DEFAULT_EN    V_SYSCLK_PHASE_DEFAULT_EN(1U)
71976 #define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
71977 #define F_SYSCLK_POS_EDGE_ALIGN    V_SYSCLK_POS_EDGE_ALIGN(1U)
71980 #define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
71981 #define F_CONTINUOUS_UPDATE    V_CONTINUOUS_UPDATE(1U)
71985 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
71986 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
71993 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
71994 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
72000 #define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
72001 #define F_SLEW_LATE_SAMPLE    V_SLEW_LATE_SAMPLE(1U)
72005 #define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
72006 #define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
72009 #define V_BB_LOCK(x) ((x) << S_BB_LOCK)
72010 #define F_BB_LOCK    V_BB_LOCK(1U)
72013 #define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
72014 #define F_SLEW_EARLY_SAMPLE    V_SLEW_EARLY_SAMPLE(1U)
72018 #define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
72019 #define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
72023 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
72024 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
72030 #define V_FLUSH(x) ((x) << S_FLUSH)
72031 #define F_FLUSH    V_FLUSH(1U)
72034 #define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
72035 #define F_GIANT_MUX_TEST_EN    V_GIANT_MUX_TEST_EN(1U)
72038 #define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
72039 #define F_GIANT_MUX_TEST_VAL    V_GIANT_MUX_TEST_VAL(1U)
72043 #define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
72044 #define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
72048 #define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
72049 #define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
72052 #define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
72053 #define F_ATEST1CTL0    V_ATEST1CTL0(1U)
72056 #define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
72057 #define F_ATEST1CTL1    V_ATEST1CTL1(1U)
72059 #define S_ATEST1CTL2    1
72060 #define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
72061 #define F_ATEST1CTL2    V_ATEST1CTL2(1U)
72064 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
72065 #define F_ATEST1CTL3    V_ATEST1CTL3(1U)
72070 #define V_FORCE_EN(x) ((x) << S_FORCE_EN)
72071 #define F_FORCE_EN    V_FORCE_EN(1U)
72075 #define V_AD32S_HS_PROBE_A_SEL(x) ((x) << S_AD32S_HS_PROBE_A_SEL)
72076 #define G_AD32S_HS_PROBE_A_SEL(x) (((x) >> S_AD32S_HS_PROBE_A_SEL) & M_AD32S_HS_PROBE_A_SEL)
72080 #define V_AD32S_HS_PROBE_B_SEL(x) ((x) << S_AD32S_HS_PROBE_B_SEL)
72081 #define G_AD32S_HS_PROBE_B_SEL(x) (((x) >> S_AD32S_HS_PROBE_B_SEL) & M_AD32S_HS_PROBE_B_SEL)
72087 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
72088 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
72094 #define V_OUTPUT_DRIVER_FORCE_VALUE(x) ((x) << S_OUTPUT_DRIVER_FORCE_VALUE)
72095 #define G_OUTPUT_DRIVER_FORCE_VALUE(x) (((x) >> S_OUTPUT_DRIVER_FORCE_VALUE) & M_OUTPUT_DRIVER_FORCE_VALUE)
72102 #define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
72103 #define F_MASTER_PD_CNTL    V_MASTER_PD_CNTL(1U)
72106 #define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
72107 #define F_ANALOG_INPUT_STAB2    V_ANALOG_INPUT_STAB2(1U)
72110 #define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
72111 #define F_ANALOG_INPUT_STAB1    V_ANALOG_INPUT_STAB1(1U)
72115 #define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
72116 #define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
72119 #define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
72120 #define F_WR_FIFO_STAB    V_WR_FIFO_STAB(1U)
72123 #define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
72124 #define F_ADR_RX_PD    V_ADR_RX_PD(1U)
72126 #define S_TX_TRISTATE_CNTL    1
72127 #define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
72128 #define F_TX_TRISTATE_CNTL    V_TX_TRISTATE_CNTL(1U)
72131 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
72132 #define F_DVCC_REG_PD    V_DVCC_REG_PD(1U)
72138 #define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
72139 #define F_SLEW_CAL_ENABLE    V_SLEW_CAL_ENABLE(1U)
72142 #define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
72143 #define F_SLEW_CAL_START    V_SLEW_CAL_START(1U)
72146 #define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
72147 #define F_SLEW_CAL_OVERRIDE_EN    V_SLEW_CAL_OVERRIDE_EN(1U)
72151 #define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
72152 #define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
72156 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
72157 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
72162 #define S_DP18_PLL_LOCK    1
72164 #define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
72165 #define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
72171 #define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
72172 #define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
72178 #define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
72179 #define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
72182 #define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
72183 #define F_RANK_PAIR0_PRI_V    V_RANK_PAIR0_PRI_V(1U)
72187 #define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
72188 #define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
72191 #define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
72192 #define F_RANK_PAIR0_SEC_V    V_RANK_PAIR0_SEC_V(1U)
72196 #define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
72197 #define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
72200 #define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
72201 #define F_RANK_PAIR1_PRI_V    V_RANK_PAIR1_PRI_V(1U)
72203 #define S_RANK_PAIR1_SEC    1
72205 #define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
72206 #define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
72209 #define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
72210 #define F_RANK_PAIR1_SEC_V    V_RANK_PAIR1_SEC_V(1U)
72216 #define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
72217 #define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
72220 #define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
72221 #define F_RANK_PAIR2_PRI_V    V_RANK_PAIR2_PRI_V(1U)
72225 #define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
72226 #define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
72229 #define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
72230 #define F_RANK_PAIR2_SEC_V    V_RANK_PAIR2_SEC_V(1U)
72234 #define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
72235 #define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
72238 #define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
72239 #define F_RANK_PAIR3_PRI_V    V_RANK_PAIR3_PRI_V(1U)
72241 #define S_RANK_PAIR3_SEC    1
72243 #define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
72244 #define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
72247 #define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
72248 #define F_RANK_PAIR3_SEC_V    V_RANK_PAIR3_SEC_V(1U)
72254 #define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
72255 #define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
72260 #define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
72261 #define F_PERIODIC_CAL_REQ_EN    V_PERIODIC_CAL_REQ_EN(1U)
72265 #define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
72266 #define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
72272 #define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
72273 #define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
72279 #define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
72280 #define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
72286 #define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
72287 #define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
72293 #define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
72294 #define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
72301 #define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
72302 #define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
72305 #define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
72306 #define F_PER_ENA_ZCAL    V_PER_ENA_ZCAL(1U)
72309 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
72310 #define F_PER_ENA_SYSCLK_ALIGN    V_PER_ENA_SYSCLK_ALIGN(1U)
72313 #define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
72314 #define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
72317 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
72318 #define F_ENA_PER_RDCLK_ALIGN    V_ENA_PER_RDCLK_ALIGN(1U)
72321 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
72322 #define F_ENA_PER_DQS_ALIGN    V_ENA_PER_DQS_ALIGN(1U)
72326 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
72327 #define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
72330 #define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
72331 #define F_FAST_SIM_PER_CNTR    V_FAST_SIM_PER_CNTR(1U)
72334 #define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
72335 #define F_START_INIT_CAL    V_START_INIT_CAL(1U)
72338 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
72339 #define F_START_PER_CAL    V_START_PER_CAL(1U)
72341 #define S_ABORT_ON_ERR_EN    1
72342 #define V_ABORT_ON_ERR_EN(x) ((x) << S_ABORT_ON_ERR_EN)
72343 #define F_ABORT_ON_ERR_EN    V_ABORT_ON_ERR_EN(1U)
72346 #define V_ENA_PER_RD_CTR(x) ((x) << S_ENA_PER_RD_CTR)
72347 #define F_ENA_PER_RD_CTR    V_ENA_PER_RD_CTR(1U)
72353 #define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
72354 #define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
72357 #define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
72358 #define F_DATA_MUX4_1MODE    V_DATA_MUX4_1MODE(1U)
72361 #define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
72362 #define F_DDR4_CMD_SIG_REDUCTION    V_DDR4_CMD_SIG_REDUCTION(1U)
72365 #define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
72366 #define F_SYSCLK_2X_MEMINTCLKO    V_SYSCLK_2X_MEMINTCLKO(1U)
72369 #define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
72370 #define F_RANK_OVERRIDE    V_RANK_OVERRIDE(1U)
72374 #define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
72375 #define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
72378 #define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
72379 #define F_LOW_LATENCY    V_LOW_LATENCY(1U)
72382 #define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
72383 #define F_DDR4_BANK_REFRESH    V_DDR4_BANK_REFRESH(1U)
72385 #define S_DDR4_VLEVEL_BANK_GROUP    1
72386 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
72387 #define F_DDR4_VLEVEL_BANK_GROUP    V_DDR4_VLEVEL_BANK_GROUP(1U)
72391 #define V_DDRPHY_PROTOCOL(x) ((x) << S_DDRPHY_PROTOCOL)
72392 #define G_DDRPHY_PROTOCOL(x) (((x) >> S_DDRPHY_PROTOCOL) & M_DDRPHY_PROTOCOL)
72395 #define V_SPAM_EN(x) ((x) << S_SPAM_EN)
72396 #define F_SPAM_EN    V_SPAM_EN(1U)
72399 #define V_DDR4_IPW_LOOP_DIS(x) ((x) << S_DDR4_IPW_LOOP_DIS)
72400 #define F_DDR4_IPW_LOOP_DIS    V_DDR4_IPW_LOOP_DIS(1U)
72406 #define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
72407 #define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
72411 #define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
72412 #define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
72415 #define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
72416 #define F_MEMCTL_CIC_FAST    V_MEMCTL_CIC_FAST(1U)
72419 #define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
72420 #define F_MEMCTL_CTRN_IGNORE    V_MEMCTL_CTRN_IGNORE(1U)
72423 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
72424 #define F_DISABLE_MEMCTL_CAL    V_DISABLE_MEMCTL_CAL(1U)
72427 #define V_MEMCTL_CIS_IGNORE(x) ((x) << S_MEMCTL_CIS_IGNORE)
72428 #define F_MEMCTL_CIS_IGNORE    V_MEMCTL_CIS_IGNORE(1U)
72432 #define V_MEMORY_TYPE(x) ((x) << S_MEMORY_TYPE)
72433 #define G_MEMORY_TYPE(x) (((x) >> S_MEMORY_TYPE) & M_MEMORY_TYPE)
72435 #define S_DDR4_PDA_MODE    1
72436 #define V_DDR4_PDA_MODE(x) ((x) << S_DDR4_PDA_MODE)
72437 #define F_DDR4_PDA_MODE    V_DDR4_PDA_MODE(1U)
72442 #define V_PLL_RESET(x) ((x) << S_PLL_RESET)
72443 #define F_PLL_RESET    V_PLL_RESET(1U)
72446 #define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
72447 #define F_SYSCLK_RESET    V_SYSCLK_RESET(1U)
72453 #define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
72454 #define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
72458 #define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
72459 #define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
72462 #define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
72463 #define F_START_PER_ZCAL    V_START_PER_ZCAL(1U)
72468 #define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
72469 #define F_ADDR_MIRROR_RP0_PRI    V_ADDR_MIRROR_RP0_PRI(1U)
72472 #define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
72473 #define F_ADDR_MIRROR_RP0_SEC    V_ADDR_MIRROR_RP0_SEC(1U)
72476 #define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
72477 #define F_ADDR_MIRROR_RP1_PRI    V_ADDR_MIRROR_RP1_PRI(1U)
72480 #define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
72481 #define F_ADDR_MIRROR_RP1_SEC    V_ADDR_MIRROR_RP1_SEC(1U)
72484 #define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
72485 #define F_ADDR_MIRROR_RP2_PRI    V_ADDR_MIRROR_RP2_PRI(1U)
72488 #define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
72489 #define F_ADDR_MIRROR_RP2_SEC    V_ADDR_MIRROR_RP2_SEC(1U)
72492 #define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
72493 #define F_ADDR_MIRROR_RP3_PRI    V_ADDR_MIRROR_RP3_PRI(1U)
72496 #define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
72497 #define F_ADDR_MIRROR_RP3_SEC    V_ADDR_MIRROR_RP3_SEC(1U)
72501 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
72502 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
72505 #define V_ADDR_MIRROR_A3_A4(x) ((x) << S_ADDR_MIRROR_A3_A4)
72506 #define F_ADDR_MIRROR_A3_A4    V_ADDR_MIRROR_A3_A4(1U)
72509 #define V_ADDR_MIRROR_A5_A6(x) ((x) << S_ADDR_MIRROR_A5_A6)
72510 #define F_ADDR_MIRROR_A5_A6    V_ADDR_MIRROR_A5_A6(1U)
72513 #define V_ADDR_MIRROR_A7_A8(x) ((x) << S_ADDR_MIRROR_A7_A8)
72514 #define F_ADDR_MIRROR_A7_A8    V_ADDR_MIRROR_A7_A8(1U)
72517 #define V_ADDR_MIRROR_A11_A13(x) ((x) << S_ADDR_MIRROR_A11_A13)
72518 #define F_ADDR_MIRROR_A11_A13    V_ADDR_MIRROR_A11_A13(1U)
72520 #define S_ADDR_MIRROR_BA0_BA1    1
72521 #define V_ADDR_MIRROR_BA0_BA1(x) ((x) << S_ADDR_MIRROR_BA0_BA1)
72522 #define F_ADDR_MIRROR_BA0_BA1    V_ADDR_MIRROR_BA0_BA1(1U)
72525 #define V_ADDR_MIRROR_BG0_BG1(x) ((x) << S_ADDR_MIRROR_BG0_BG1)
72526 #define F_ADDR_MIRROR_BG0_BG1    V_ADDR_MIRROR_BG0_BG1(1U)
72531 #define V_RC_ERROR(x) ((x) << S_RC_ERROR)
72532 #define F_RC_ERROR    V_RC_ERROR(1U)
72535 #define V_WC_ERROR(x) ((x) << S_WC_ERROR)
72536 #define F_WC_ERROR    V_WC_ERROR(1U)
72539 #define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
72540 #define F_SEQ_ERROR    V_SEQ_ERROR(1U)
72543 #define V_CC_ERROR(x) ((x) << S_CC_ERROR)
72544 #define F_CC_ERROR    V_CC_ERROR(1U)
72547 #define V_APB_ERROR(x) ((x) << S_APB_ERROR)
72548 #define F_APB_ERROR    V_APB_ERROR(1U)
72551 #define V_PC_ERROR(x) ((x) << S_PC_ERROR)
72552 #define F_PC_ERROR    V_PC_ERROR(1U)
72557 #define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
72558 #define F_RC_ERROR_MASK    V_RC_ERROR_MASK(1U)
72561 #define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
72562 #define F_WC_ERROR_MASK    V_WC_ERROR_MASK(1U)
72565 #define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
72566 #define F_SEQ_ERROR_MASK    V_SEQ_ERROR_MASK(1U)
72569 #define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
72570 #define F_CC_ERROR_MASK    V_CC_ERROR_MASK(1U)
72573 #define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
72574 #define F_APB_ERROR_MASK    V_APB_ERROR_MASK(1U)
72577 #define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
72578 #define F_PC_ERROR_MASK    V_PC_ERROR_MASK(1U)
72584 #define V_PVTP(x) ((x) << S_PVTP)
72585 #define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
72589 #define V_PVTN(x) ((x) << S_PVTN)
72590 #define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
72593 #define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
72594 #define F_PVT_OVERRIDE    V_PVT_OVERRIDE(1U)
72597 #define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
72598 #define F_ENABLE_ZCAL    V_ENABLE_ZCAL(1U)
72603 #define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
72604 #define F_VREFDQ0DSGN    V_VREFDQ0DSGN(1U)
72608 #define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
72609 #define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
72612 #define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
72613 #define F_VREFDQ1DSGN    V_VREFDQ1DSGN(1U)
72617 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
72618 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
72621 #define V_EN_ANALOG_PD(x) ((x) << S_EN_ANALOG_PD)
72622 #define F_EN_ANALOG_PD    V_EN_ANALOG_PD(1U)
72625 #define V_ANALOG_PD_DLY(x) ((x) << S_ANALOG_PD_DLY)
72626 #define F_ANALOG_PD_DLY    V_ANALOG_PD_DLY(1U)
72630 #define V_ANALOG_PD_DIV(x) ((x) << S_ANALOG_PD_DIV)
72631 #define G_ANALOG_PD_DIV(x) (((x) >> S_ANALOG_PD_DIV) & M_ANALOG_PD_DIV)
72636 #define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
72637 #define F_ENA_WR_LEVEL    V_ENA_WR_LEVEL(1U)
72640 #define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
72641 #define F_ENA_INITIAL_PAT_WR    V_ENA_INITIAL_PAT_WR(1U)
72644 #define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
72645 #define F_ENA_DQS_ALIGN    V_ENA_DQS_ALIGN(1U)
72648 #define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
72649 #define F_ENA_RDCLK_ALIGN    V_ENA_RDCLK_ALIGN(1U)
72652 #define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
72653 #define F_ENA_READ_CTR    V_ENA_READ_CTR(1U)
72656 #define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
72657 #define F_ENA_WRITE_CTR    V_ENA_WRITE_CTR(1U)
72660 #define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
72661 #define F_ENA_INITIAL_COARSE_WR    V_ENA_INITIAL_COARSE_WR(1U)
72664 #define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
72665 #define F_ENA_COARSE_RD    V_ENA_COARSE_RD(1U)
72668 #define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
72669 #define F_ENA_CUSTOM_RD    V_ENA_CUSTOM_RD(1U)
72672 #define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
72673 #define F_ENA_CUSTOM_WR    V_ENA_CUSTOM_WR(1U)
72676 #define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
72677 #define F_ABORT_ON_CAL_ERROR    V_ABORT_ON_CAL_ERROR(1U)
72680 #define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
72681 #define F_ENA_DIGITAL_EYE    V_ENA_DIGITAL_EYE(1U)
72685 #define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
72686 #define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
72692 #define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
72693 #define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
72697 #define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
72698 #define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
72701 #define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
72702 #define F_REFRESH_ALL_RANKS    V_REFRESH_ALL_RANKS(1U)
72706 #define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
72707 #define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
72712 #define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
72713 #define F_ERROR_WR_LEVEL    V_ERROR_WR_LEVEL(1U)
72716 #define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
72717 #define F_ERROR_INITIAL_PAT_WRITE    V_ERROR_INITIAL_PAT_WRITE(1U)
72720 #define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
72721 #define F_ERROR_DQS_ALIGN    V_ERROR_DQS_ALIGN(1U)
72724 #define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
72725 #define F_ERROR_RDCLK_ALIGN    V_ERROR_RDCLK_ALIGN(1U)
72728 #define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
72729 #define F_ERROR_READ_CTR    V_ERROR_READ_CTR(1U)
72732 #define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
72733 #define F_ERROR_WRITE_CTR    V_ERROR_WRITE_CTR(1U)
72736 #define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
72737 #define F_ERROR_INITIAL_COARSE_WR    V_ERROR_INITIAL_COARSE_WR(1U)
72740 #define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
72741 #define F_ERROR_COARSE_RD    V_ERROR_COARSE_RD(1U)
72744 #define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
72745 #define F_ERROR_CUSTOM_RD    V_ERROR_CUSTOM_RD(1U)
72748 #define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
72749 #define F_ERROR_CUSTOM_WR    V_ERROR_CUSTOM_WR(1U)
72752 #define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
72753 #define F_ERROR_DIGITAL_EYE    V_ERROR_DIGITAL_EYE(1U)
72757 #define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
72758 #define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
72764 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
72765 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
72768 #define V_PER_CAL_ABORT(x) ((x) << S_PER_CAL_ABORT)
72769 #define F_PER_CAL_ABORT    V_PER_CAL_ABORT(1U)
72774 #define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
72775 #define F_ERROR_WR_LEVEL_MASK    V_ERROR_WR_LEVEL_MASK(1U)
72778 #define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
72779 #define F_ERROR_INITIAL_PAT_WRITE_MASK    V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
72782 #define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
72783 #define F_ERROR_DQS_ALIGN_MASK    V_ERROR_DQS_ALIGN_MASK(1U)
72786 #define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
72787 #define F_ERROR_RDCLK_ALIGN_MASK    V_ERROR_RDCLK_ALIGN_MASK(1U)
72790 #define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
72791 #define F_ERROR_READ_CTR_MASK    V_ERROR_READ_CTR_MASK(1U)
72794 #define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
72795 #define F_ERROR_WRITE_CTR_MASK    V_ERROR_WRITE_CTR_MASK(1U)
72798 #define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
72799 #define F_ERROR_INITIAL_COARSE_WR_MASK    V_ERROR_INITIAL_COARSE_WR_MASK(1U)
72802 #define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
72803 #define F_ERROR_COARSE_RD_MASK    V_ERROR_COARSE_RD_MASK(1U)
72806 #define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
72807 #define F_ERROR_CUSTOM_RD_MASK    V_ERROR_CUSTOM_RD_MASK(1U)
72810 #define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
72811 #define F_ERROR_CUSTOM_WR_MASK    V_ERROR_CUSTOM_WR_MASK(1U)
72814 #define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
72815 #define F_ERROR_DIGITAL_EYE_MASK    V_ERROR_DIGITAL_EYE_MASK(1U)
72822 #define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
72823 #define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
72829 #define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
72830 #define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
72836 #define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
72837 #define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
72843 #define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
72844 #define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
72853 #define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
72854 #define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
72860 #define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
72861 #define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
72867 #define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
72868 #define F_MPR_PATTERN_BIT    V_MPR_PATTERN_BIT(1U)
72871 #define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
72872 #define F_TWO_CYCLE_ADDR_EN    V_TWO_CYCLE_ADDR_EN(1U)
72876 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
72877 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
72880 #define V_PARITY_DLY(x) ((x) << S_PARITY_DLY)
72881 #define F_PARITY_DLY    V_PARITY_DLY(1U)
72884 #define V_FORCE_RESERVED(x) ((x) << S_FORCE_RESERVED)
72885 #define F_FORCE_RESERVED    V_FORCE_RESERVED(1U)
72888 #define V_HALT_ROTATION(x) ((x) << S_HALT_ROTATION)
72889 #define F_HALT_ROTATION    V_HALT_ROTATION(1U)
72892 #define V_FORCE_MPR(x) ((x) << S_FORCE_MPR)
72893 #define F_FORCE_MPR    V_FORCE_MPR(1U)
72896 #define V_IPW_SIDEAB_SEL(x) ((x) << S_IPW_SIDEAB_SEL)
72897 #define F_IPW_SIDEAB_SEL    V_IPW_SIDEAB_SEL(1U)
72899 #define S_PARITY_A17_MASK    1
72900 #define V_PARITY_A17_MASK(x) ((x) << S_PARITY_A17_MASK)
72901 #define F_PARITY_A17_MASK    V_PARITY_A17_MASK(1U)
72904 #define V_X16_DEVICE(x) ((x) << S_X16_DEVICE)
72905 #define F_X16_DEVICE    V_X16_DEVICE(1U)
72915 #define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
72916 #define F_MULTIPLE_REQ_ERROR    V_MULTIPLE_REQ_ERROR(1U)
72919 #define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
72920 #define F_INVALID_REQTYPE_ERRO    V_INVALID_REQTYPE_ERRO(1U)
72923 #define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
72924 #define F_EARLY_REQ_ERROR    V_EARLY_REQ_ERROR(1U)
72928 #define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
72929 #define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
72933 #define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
72934 #define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
72938 #define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
72939 #define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
72943 #define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
72944 #define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
72949 #define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
72950 #define F_MULT_REQ_ERR_MASK    V_MULT_REQ_ERR_MASK(1U)
72953 #define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
72954 #define F_INVALID_REQTYPE_ERR_MASK    V_INVALID_REQTYPE_ERR_MASK(1U)
72957 #define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
72958 #define F_EARLY_REQ_ERR_MASK    V_EARLY_REQ_ERR_MASK(1U)
72964 #define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
72965 #define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
72969 #define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
72970 #define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
72979 #define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
72980 #define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
72984 #define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
72985 #define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
72994 #define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
72995 #define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
72999 #define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
73000 #define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
73004 #define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
73005 #define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
73009 #define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
73010 #define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
73016 #define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
73017 #define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
73021 #define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
73022 #define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
73026 #define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
73027 #define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
73031 #define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
73032 #define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
73038 #define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
73039 #define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
73043 #define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
73044 #define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
73048 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
73049 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
73053 #define V_MRS_CMD_SPACE(x) ((x) << S_MRS_CMD_SPACE)
73054 #define G_MRS_CMD_SPACE(x) (((x) >> S_MRS_CMD_SPACE) & M_MRS_CMD_SPACE)
73060 #define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
73061 #define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
73064 #define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
73065 #define F_ADVANCE_RD_VALID    V_ADVANCE_RD_VALID(1U)
73068 #define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
73069 #define F_SINGLE_BIT_MPR_RP0    V_SINGLE_BIT_MPR_RP0(1U)
73072 #define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
73073 #define F_SINGLE_BIT_MPR_RP1    V_SINGLE_BIT_MPR_RP1(1U)
73076 #define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
73077 #define F_SINGLE_BIT_MPR_RP2    V_SINGLE_BIT_MPR_RP2(1U)
73080 #define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
73081 #define F_SINGLE_BIT_MPR_RP3    V_SINGLE_BIT_MPR_RP3(1U)
73084 #define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
73085 #define F_ALIGN_ON_EVEN_CYCLES    V_ALIGN_ON_EVEN_CYCLES(1U)
73087 #define S_PERFORM_RDCLK_ALIGN    1
73088 #define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
73089 #define F_PERFORM_RDCLK_ALIGN    V_PERFORM_RDCLK_ALIGN(1U)
73092 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
73093 #define F_STAGGERED_PATTERN    V_STAGGERED_PATTERN(1U)
73096 #define V_ERS_MODE(x) ((x) << S_ERS_MODE)
73097 #define F_ERS_MODE    V_ERS_MODE(1U)
73103 #define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
73104 #define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
73110 #define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
73111 #define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
73115 #define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
73116 #define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
73119 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
73120 #define F_ALLOW_RD_FIFO_AUTO_R_ESET    V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
73123 #define V_DIS_LOW_PWR_PER_CAL(x) ((x) << S_DIS_LOW_PWR_PER_CAL)
73124 #define F_DIS_LOW_PWR_PER_CAL    V_DIS_LOW_PWR_PER_CAL(1U)
73129 #define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
73130 #define F_RD_CNTL_ERROR    V_RD_CNTL_ERROR(1U)
73135 #define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
73136 #define F_RD_CNTL_ERROR_MASK    V_RD_CNTL_ERROR_MASK(1U)
73142 #define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
73143 #define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
73147 #define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
73148 #define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
73152 #define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
73153 #define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
73157 #define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
73158 #define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
73165 #define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
73166 #define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
73169 #define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
73170 #define F_WL_ONE_DQS_PULSE    V_WL_ONE_DQS_PULSE(1U)
73172 #define S_FW_WR_RD    1
73174 #define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
73175 #define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
73178 #define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
73179 #define F_CUSTOM_INIT_WRITE    V_CUSTOM_INIT_WRITE(1U)
73185 #define V_BIG_STEP(x) ((x) << S_BIG_STEP)
73186 #define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
73190 #define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
73191 #define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
73195 #define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
73196 #define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
73202 #define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
73203 #define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
73207 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
73208 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
73211 #define V_EN_RESET_WR_DELAY_WL(x) ((x) << S_EN_RESET_WR_DELAY_WL)
73212 #define F_EN_RESET_WR_DELAY_WL    V_EN_RESET_WR_DELAY_WL(1U)
73216 #define V_TWR_MPR(x) ((x) << S_TWR_MPR)
73217 #define G_TWR_MPR(x) (((x) >> S_TWR_MPR) & M_TWR_MPR)
73222 #define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
73223 #define F_WR_CNTL_ERROR    V_WR_CNTL_ERROR(1U)
73228 #define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
73229 #define F_WR_CNTL_ERROR_MASK    V_WR_CNTL_ERROR_MASK(1U)
73234 #define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
73235 #define F_DDR4_MRS_CMD_DQ_EN    V_DDR4_MRS_CMD_DQ_EN(1U)
73239 #define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
73240 #define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
73244 #define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
73245 #define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
73250 #define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
73251 #define F_WRCLK_CAL_START    V_WRCLK_CAL_START(1U)
73254 #define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
73255 #define F_WRCLK_CAL_DONE    V_WRCLK_CAL_DONE(1U)
73260 #define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
73261 #define F_DISABLE_PARITY_CHECKER    V_DISABLE_PARITY_CHECKER(1U)
73264 #define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
73265 #define F_GENERATE_EVEN_PARITY    V_GENERATE_EVEN_PARITY(1U)
73268 #define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
73269 #define F_FORCE_ON_CLK_GATE    V_FORCE_ON_CLK_GATE(1U)
73272 #define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
73273 #define F_DEBUG_BUS_SEL_LO    V_DEBUG_BUS_SEL_LO(1U)
73277 #define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
73278 #define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
73283 #define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
73284 #define F_INVALID_ADDRESS    V_INVALID_ADDRESS(1U)
73287 #define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
73288 #define F_WR_PAR_ERR    V_WR_PAR_ERR(1U)
73293 #define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
73294 #define F_INVALID_ADDRESS_MASK    V_INVALID_ADDRESS_MASK(1U)
73297 #define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
73298 #define F_WR_PAR_ERR_MASK    V_WR_PAR_ERR_MASK(1U)
73303 #define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
73304 #define F_DP18_0_POPULATED    V_DP18_0_POPULATED(1U)
73307 #define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
73308 #define F_DP18_1_POPULATED    V_DP18_1_POPULATED(1U)
73311 #define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
73312 #define F_DP18_2_POPULATED    V_DP18_2_POPULATED(1U)
73315 #define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
73316 #define F_DP18_3_POPULATED    V_DP18_3_POPULATED(1U)
73319 #define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
73320 #define F_DP18_4_POPULATED    V_DP18_4_POPULATED(1U)
73323 #define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
73324 #define F_DP18_5_POPULATED    V_DP18_5_POPULATED(1U)
73327 #define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
73328 #define F_DP18_6_POPULATED    V_DP18_6_POPULATED(1U)
73331 #define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
73332 #define F_DP18_7_POPULATED    V_DP18_7_POPULATED(1U)
73335 #define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
73336 #define F_DP18_8_POPULATED    V_DP18_8_POPULATED(1U)
73339 #define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
73340 #define F_DP18_9_POPULATED    V_DP18_9_POPULATED(1U)
73343 #define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
73344 #define F_DP18_10_POPULATED    V_DP18_10_POPULATED(1U)
73347 #define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
73348 #define F_DP18_11_POPULATED    V_DP18_11_POPULATED(1U)
73351 #define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
73352 #define F_DP18_12_POPULATED    V_DP18_12_POPULATED(1U)
73355 #define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
73356 #define F_DP18_13_POPULATED    V_DP18_13_POPULATED(1U)
73358 #define S_DP18_14_POPULATED    1
73359 #define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
73360 #define F_DP18_14_POPULATED    V_DP18_14_POPULATED(1U)
73365 #define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
73366 #define F_ADR16_0_POPULATED    V_ADR16_0_POPULATED(1U)
73369 #define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
73370 #define F_ADR16_1_POPULATED    V_ADR16_1_POPULATED(1U)
73373 #define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
73374 #define F_ADR16_2_POPULATED    V_ADR16_2_POPULATED(1U)
73377 #define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
73378 #define F_ADR16_3_POPULATED    V_ADR16_3_POPULATED(1U)
73381 #define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
73382 #define F_ADR12_0_POPULATED    V_ADR12_0_POPULATED(1U)
73385 #define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
73386 #define F_ADR12_1_POPULATED    V_ADR12_1_POPULATED(1U)
73389 #define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
73390 #define F_ADR12_2_POPULATED    V_ADR12_2_POPULATED(1U)
73393 #define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
73394 #define F_ADR12_3_POPULATED    V_ADR12_3_POPULATED(1U)
73400 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
73401 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
73406 #define V_MT_DATA_MUX4_1MODE(x) ((x) << S_MT_DATA_MUX4_1MODE)
73407 #define F_MT_DATA_MUX4_1MODE    V_MT_DATA_MUX4_1MODE(1U)
73410 #define V_MT_PLL_RESET(x) ((x) << S_MT_PLL_RESET)
73411 #define F_MT_PLL_RESET    V_MT_PLL_RESET(1U)
73414 #define V_MT_SYSCLK_RESET(x) ((x) << S_MT_SYSCLK_RESET)
73415 #define F_MT_SYSCLK_RESET    V_MT_SYSCLK_RESET(1U)
73419 #define V_MT_GLOBAL_PHY_OFFSET(x) ((x) << S_MT_GLOBAL_PHY_OFFSET)
73420 #define G_MT_GLOBAL_PHY_OFFSET(x) (((x) >> S_MT_GLOBAL_PHY_OFFSET) & M_MT_GLOBAL_PHY_OFFSET)
73424 #define V_MT_DQ_SEL_QUAD(x) ((x) << S_MT_DQ_SEL_QUAD)
73425 #define G_MT_DQ_SEL_QUAD(x) (((x) >> S_MT_DQ_SEL_QUAD) & M_MT_DQ_SEL_QUAD)
73428 #define V_MT_PERFORM_RDCLK_ALIGN(x) ((x) << S_MT_PERFORM_RDCLK_ALIGN)
73429 #define F_MT_PERFORM_RDCLK_ALIGN    V_MT_PERFORM_RDCLK_ALIGN(1U)
73432 #define V_MT_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_MT_ALIGN_ON_EVEN_CYCLES)
73433 #define F_MT_ALIGN_ON_EVEN_CYCLES    V_MT_ALIGN_ON_EVEN_CYCLES(1U)
73436 #define V_MT_WRCLK_CAL_START(x) ((x) << S_MT_WRCLK_CAL_START)
73437 #define F_MT_WRCLK_CAL_START    V_MT_WRCLK_CAL_START(1U)
73442 #define V_MT_WPRD_ENABLE(x) ((x) << S_MT_WPRD_ENABLE)
73443 #define F_MT_WPRD_ENABLE    V_MT_WPRD_ENABLE(1U)
73447 #define V_MT_PVTP(x) ((x) << S_MT_PVTP)
73448 #define G_MT_PVTP(x) (((x) >> S_MT_PVTP) & M_MT_PVTP)
73452 #define V_MT_PVTN(x) ((x) << S_MT_PVTN)
73453 #define G_MT_PVTN(x) (((x) >> S_MT_PVTN) & M_MT_PVTN)
73458 #define S_MT_ADR32_PLL_LOCK_SUM    1
73459 #define V_MT_ADR32_PLL_LOCK_SUM(x) ((x) << S_MT_ADR32_PLL_LOCK_SUM)
73460 #define F_MT_ADR32_PLL_LOCK_SUM    V_MT_ADR32_PLL_LOCK_SUM(1U)
73463 #define V_MT_DP18_PLL_LOCK_SUM(x) ((x) << S_MT_DP18_PLL_LOCK_SUM)
73464 #define F_MT_DP18_PLL_LOCK_SUM    V_MT_DP18_PLL_LOCK_SUM(1U)
73475 #define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
73476 #define F_EDC_SLEEPSTATUS    V_EDC_SLEEPSTATUS(1U)
73479 #define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
73480 #define F_EDC_SLEEPREQ    V_EDC_SLEEPREQ(1U)
73483 #define V_PING_PONG(x) ((x) << S_PING_PONG)
73484 #define F_PING_PONG    V_PING_PONG(1U)
73499 #define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
73500 #define F_PERR_PAR_ENABLE    V_PERR_PAR_ENABLE(1U)
73506 #define V_ECC_UE_INT0_CAUSE(x) ((x) << S_ECC_UE_INT0_CAUSE)
73507 #define F_ECC_UE_INT0_CAUSE    V_ECC_UE_INT0_CAUSE(1U)
73510 #define V_ECC_CE_INT0_CAUSE(x) ((x) << S_ECC_CE_INT0_CAUSE)
73511 #define F_ECC_CE_INT0_CAUSE    V_ECC_CE_INT0_CAUSE(1U)
73514 #define V_PERR_INT0_CAUSE(x) ((x) << S_PERR_INT0_CAUSE)
73515 #define F_PERR_INT0_CAUSE    V_PERR_INT0_CAUSE(1U)
73522 #define V_CFG(x) ((x) << S_CFG)
73523 #define G_CFG(x) (((x) >> S_CFG) & M_CFG)
73529 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
73530 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
73544 #define V_TRIG(x) ((x) << S_TRIG)
73545 #define F_TRIG    V_TRIG(1U)
73548 #define V_RW(x) ((x) << S_RW)
73549 #define F_RW    V_RW(1U)
73553 #define V_L_SEL(x) ((x) << S_L_SEL)
73554 #define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
73560 #define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
73561 #define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
73571 #define V_FID(x) ((x) << S_FID)
73572 #define G_FID(x) (((x) >> S_FID) & M_FID)
73575 #define V_NOS(x) ((x) << S_NOS)
73576 #define F_NOS    V_NOS(1U)
73579 #define V_RO(x) ((x) << S_RO)
73580 #define F_RO    V_RO(1U)
73585 #define V_C_REQ(x) ((x) << S_C_REQ)
73586 #define F_C_REQ    V_C_REQ(1U)
73590 #define V_C_FID(x) ((x) << S_C_FID)
73591 #define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
73595 #define V_C_VAL(x) ((x) << S_C_VAL)
73596 #define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
73600 #define V_C_SEL(x) ((x) << S_C_SEL)
73601 #define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
73612 #define V_QDR_CLKPHASE(x) ((x) << S_QDR_CLKPHASE)
73613 #define G_QDR_CLKPHASE(x) (((x) >> S_QDR_CLKPHASE) & M_QDR_CLKPHASE)
73617 #define V_MAXOPSPERTRC(x) ((x) << S_MAXOPSPERTRC)
73618 #define G_MAXOPSPERTRC(x) (((x) >> S_MAXOPSPERTRC) & M_MAXOPSPERTRC)
73622 #define V_NUMPIPESTAGES(x) ((x) << S_NUMPIPESTAGES)
73623 #define G_NUMPIPESTAGES(x) (((x) >> S_NUMPIPESTAGES) & M_NUMPIPESTAGES)
73627 #define V_DRAMREFENABLE(x) ((x) << S_DRAMREFENABLE)
73628 #define G_DRAMREFENABLE(x) (((x) >> S_DRAMREFENABLE) & M_DRAMREFENABLE)
73634 #define V_MCMDADDR(x) ((x) << S_MCMDADDR)
73635 #define G_MCMDADDR(x) (((x) >> S_MCMDADDR) & M_MCMDADDR)
73639 #define V_MCMDLEN(x) ((x) << S_MCMDLEN)
73640 #define G_MCMDLEN(x) (((x) >> S_MCMDLEN) & M_MCMDLEN)
73643 #define V_MCMDNRE(x) ((x) << S_MCMDNRE)
73644 #define F_MCMDNRE    V_MCMDNRE(1U)
73647 #define V_MCMDNRB(x) ((x) << S_MCMDNRB)
73648 #define F_MCMDNRB    V_MCMDNRB(1U)
73651 #define V_MCMDWR(x) ((x) << S_MCMDWR)
73652 #define F_MCMDWR    V_MCMDWR(1U)
73654 #define S_MCMDRDY    1
73655 #define V_MCMDRDY(x) ((x) << S_MCMDRDY)
73656 #define F_MCMDRDY    V_MCMDRDY(1U)
73659 #define V_MCMDVLD(x) ((x) << S_MCMDVLD)
73660 #define F_MCMDVLD    V_MCMDVLD(1U)
73665 #define V_MWDATAVLD(x) ((x) << S_MWDATAVLD)
73666 #define F_MWDATAVLD    V_MWDATAVLD(1U)
73669 #define V_MWDATARDY(x) ((x) << S_MWDATARDY)
73670 #define F_MWDATARDY    V_MWDATARDY(1U)
73674 #define V_MWDATA(x) ((x) << S_MWDATA)
73675 #define G_MWDATA(x) (((x) >> S_MWDATA) & M_MWDATA)
73680 #define V_MRSPVLD(x) ((x) << S_MRSPVLD)
73681 #define F_MRSPVLD    V_MRSPVLD(1U)
73684 #define V_MRSPRDY(x) ((x) << S_MRSPRDY)
73685 #define F_MRSPRDY    V_MRSPRDY(1U)
73689 #define V_MRSPDATA(x) ((x) << S_MRSPDATA)
73690 #define G_MRSPDATA(x) (((x) >> S_MRSPDATA) & M_MRSPDATA)
73696 #define V_BCMDADDR(x) ((x) << S_BCMDADDR)
73697 #define G_BCMDADDR(x) (((x) >> S_BCMDADDR) & M_BCMDADDR)
73701 #define V_BCMDLEN(x) ((x) << S_BCMDLEN)
73702 #define G_BCMDLEN(x) (((x) >> S_BCMDLEN) & M_BCMDLEN)
73705 #define V_BCMDWR(x) ((x) << S_BCMDWR)
73706 #define F_BCMDWR    V_BCMDWR(1U)
73708 #define S_BCMDRDY    1
73709 #define V_BCMDRDY(x) ((x) << S_BCMDRDY)
73710 #define F_BCMDRDY    V_BCMDRDY(1U)
73713 #define V_BCMDVLD(x) ((x) << S_BCMDVLD)
73714 #define F_BCMDVLD    V_BCMDVLD(1U)
73719 #define V_BWDATAVLD(x) ((x) << S_BWDATAVLD)
73720 #define F_BWDATAVLD    V_BWDATAVLD(1U)
73723 #define V_BWDATARDY(x) ((x) << S_BWDATARDY)
73724 #define F_BWDATARDY    V_BWDATARDY(1U)
73728 #define V_BWDATA(x) ((x) << S_BWDATA)
73729 #define G_BWDATA(x) (((x) >> S_BWDATA) & M_BWDATA)
73734 #define V_BRSPVLD(x) ((x) << S_BRSPVLD)
73735 #define F_BRSPVLD    V_BRSPVLD(1U)
73738 #define V_BRSPRDY(x) ((x) << S_BRSPRDY)
73739 #define F_BRSPRDY    V_BRSPRDY(1U)
73743 #define V_BRSPDATA(x) ((x) << S_BRSPDATA)
73744 #define G_BRSPDATA(x) (((x) >> S_BRSPDATA) & M_BRSPDATA)
73750 #define V_EDRAMADDR(x) ((x) << S_EDRAMADDR)
73751 #define G_EDRAMADDR(x) (((x) >> S_EDRAMADDR) & M_EDRAMADDR)
73755 #define V_EDRAMDWSN(x) ((x) << S_EDRAMDWSN)
73756 #define G_EDRAMDWSN(x) (((x) >> S_EDRAMDWSN) & M_EDRAMDWSN)
73760 #define V_EDRAMCRA(x) ((x) << S_EDRAMCRA)
73761 #define G_EDRAMCRA(x) (((x) >> S_EDRAMCRA) & M_EDRAMCRA)
73764 #define V_EDRAMREFENLO(x) ((x) << S_EDRAMREFENLO)
73765 #define F_EDRAMREFENLO    V_EDRAMREFENLO(1U)
73768 #define V_EDRAM1WRENLO(x) ((x) << S_EDRAM1WRENLO)
73769 #define F_EDRAM1WRENLO    V_EDRAM1WRENLO(1U)
73772 #define V_EDRAM1RDENLO(x) ((x) << S_EDRAM1RDENLO)
73773 #define F_EDRAM1RDENLO    V_EDRAM1RDENLO(1U)
73775 #define S_EDRAM0WRENLO    1
73776 #define V_EDRAM0WRENLO(x) ((x) << S_EDRAM0WRENLO)
73777 #define F_EDRAM0WRENLO    V_EDRAM0WRENLO(1U)
73780 #define V_EDRAM0RDENLO(x) ((x) << S_EDRAM0RDENLO)
73781 #define F_EDRAM0RDENLO    V_EDRAM0RDENLO(1U)
73787 #define V_EDRAMWDATA(x) ((x) << S_EDRAMWDATA)
73788 #define G_EDRAMWDATA(x) (((x) >> S_EDRAMWDATA) & M_EDRAMWDATA)
73792 #define V_EDRAMWBYTEEN(x) ((x) << S_EDRAMWBYTEEN)
73793 #define G_EDRAMWBYTEEN(x) (((x) >> S_EDRAMWBYTEEN) & M_EDRAMWBYTEEN)
73819 #define V_RDTAG_NOTFULL(x) ((x) << S_RDTAG_NOTFULL)
73820 #define F_RDTAG_NOTFULL    V_RDTAG_NOTFULL(1U)
73823 #define V_RDTAG_NOTEMPTY(x) ((x) << S_RDTAG_NOTEMPTY)
73824 #define F_RDTAG_NOTEMPTY    V_RDTAG_NOTEMPTY(1U)
73827 #define V_INP_CMDQ_NOTFULL_ARB(x) ((x) << S_INP_CMDQ_NOTFULL_ARB)
73828 #define F_INP_CMDQ_NOTFULL_ARB    V_INP_CMDQ_NOTFULL_ARB(1U)
73831 #define V_INP_CMDQ_NOTEMPTY(x) ((x) << S_INP_CMDQ_NOTEMPTY)
73832 #define F_INP_CMDQ_NOTEMPTY    V_INP_CMDQ_NOTEMPTY(1U)
73835 #define V_INP_WRDQ_WRRDY(x) ((x) << S_INP_WRDQ_WRRDY)
73836 #define F_INP_WRDQ_WRRDY    V_INP_WRDQ_WRRDY(1U)
73839 #define V_INP_WRDQ_NOTEMPTY(x) ((x) << S_INP_WRDQ_NOTEMPTY)
73840 #define F_INP_WRDQ_NOTEMPTY    V_INP_WRDQ_NOTEMPTY(1U)
73843 #define V_INP_BEQ_WRRDY_OPEN(x) ((x) << S_INP_BEQ_WRRDY_OPEN)
73844 #define F_INP_BEQ_WRRDY_OPEN    V_INP_BEQ_WRRDY_OPEN(1U)
73847 #define V_INP_BEQ_NOTEMPTY(x) ((x) << S_INP_BEQ_NOTEMPTY)
73848 #define F_INP_BEQ_NOTEMPTY    V_INP_BEQ_NOTEMPTY(1U)
73851 #define V_RDDQ_NOTFULL_OPEN(x) ((x) << S_RDDQ_NOTFULL_OPEN)
73852 #define F_RDDQ_NOTFULL_OPEN    V_RDDQ_NOTFULL_OPEN(1U)
73856 #define V_RDDQ_RDCNT(x) ((x) << S_RDDQ_RDCNT)
73857 #define G_RDDQ_RDCNT(x) (((x) >> S_RDDQ_RDCNT) & M_RDDQ_RDCNT)
73860 #define V_RDSIDEQ_NOTFULL(x) ((x) << S_RDSIDEQ_NOTFULL)
73861 #define F_RDSIDEQ_NOTFULL    V_RDSIDEQ_NOTFULL(1U)
73864 #define V_RDSIDEQ_NOTEMPTY(x) ((x) << S_RDSIDEQ_NOTEMPTY)
73865 #define F_RDSIDEQ_NOTEMPTY    V_RDSIDEQ_NOTEMPTY(1U)
73867 #define S_STG_CMDQ_NOTEMPTY    1
73868 #define V_STG_CMDQ_NOTEMPTY(x) ((x) << S_STG_CMDQ_NOTEMPTY)
73869 #define F_STG_CMDQ_NOTEMPTY    V_STG_CMDQ_NOTEMPTY(1U)
73872 #define V_STG_WRDQ_NOTEMPTY(x) ((x) << S_STG_WRDQ_NOTEMPTY)
73873 #define F_STG_WRDQ_NOTEMPTY    V_STG_WRDQ_NOTEMPTY(1U)
73878 #define V_CMDSPLITFSM(x) ((x) << S_CMDSPLITFSM)
73879 #define F_CMDSPLITFSM    V_CMDSPLITFSM(1U)
73883 #define V_CMDFSM(x) ((x) << S_CMDFSM)
73884 #define G_CMDFSM(x) (((x) >> S_CMDFSM) & M_CMDFSM)
73889 #define V_STALL_RMW(x) ((x) << S_STALL_RMW)
73890 #define F_STALL_RMW    V_STALL_RMW(1U)
73893 #define V_STALL_EDC_CMD(x) ((x) << S_STALL_EDC_CMD)
73894 #define F_STALL_EDC_CMD    V_STALL_EDC_CMD(1U)
73897 #define V_DEAD_CYCLE0(x) ((x) << S_DEAD_CYCLE0)
73898 #define F_DEAD_CYCLE0    V_DEAD_CYCLE0(1U)
73901 #define V_DEAD_CYCLE1(x) ((x) << S_DEAD_CYCLE1)
73902 #define F_DEAD_CYCLE1    V_DEAD_CYCLE1(1U)
73905 #define V_DEAD_CYCLE0_BBI(x) ((x) << S_DEAD_CYCLE0_BBI)
73906 #define F_DEAD_CYCLE0_BBI    V_DEAD_CYCLE0_BBI(1U)
73909 #define V_DEAD_CYCLE1_BBI(x) ((x) << S_DEAD_CYCLE1_BBI)
73910 #define F_DEAD_CYCLE1_BBI    V_DEAD_CYCLE1_BBI(1U)
73913 #define V_DEAD_CYCLE0_MAX_OP(x) ((x) << S_DEAD_CYCLE0_MAX_OP)
73914 #define F_DEAD_CYCLE0_MAX_OP    V_DEAD_CYCLE0_MAX_OP(1U)
73917 #define V_DEAD_CYCLE1_MAX_OP(x) ((x) << S_DEAD_CYCLE1_MAX_OP)
73918 #define F_DEAD_CYCLE1_MAX_OP    V_DEAD_CYCLE1_MAX_OP(1U)
73921 #define V_DEAD_CYCLE0_PRE_REF(x) ((x) << S_DEAD_CYCLE0_PRE_REF)
73922 #define F_DEAD_CYCLE0_PRE_REF    V_DEAD_CYCLE0_PRE_REF(1U)
73925 #define V_DEAD_CYCLE1_PRE_REF(x) ((x) << S_DEAD_CYCLE1_PRE_REF)
73926 #define F_DEAD_CYCLE1_PRE_REF    V_DEAD_CYCLE1_PRE_REF(1U)
73929 #define V_DEAD_CYCLE0_POST_REF(x) ((x) << S_DEAD_CYCLE0_POST_REF)
73930 #define F_DEAD_CYCLE0_POST_REF    V_DEAD_CYCLE0_POST_REF(1U)
73933 #define V_DEAD_CYCLE1_POST_REF(x) ((x) << S_DEAD_CYCLE1_POST_REF)
73934 #define F_DEAD_CYCLE1_POST_REF    V_DEAD_CYCLE1_POST_REF(1U)
73937 #define V_DEAD_CYCLE0_RMW(x) ((x) << S_DEAD_CYCLE0_RMW)
73938 #define F_DEAD_CYCLE0_RMW    V_DEAD_CYCLE0_RMW(1U)
73941 #define V_DEAD_CYCLE1_RMW(x) ((x) << S_DEAD_CYCLE1_RMW)
73942 #define F_DEAD_CYCLE1_RMW    V_DEAD_CYCLE1_RMW(1U)
73945 #define V_DEAD_CYCLE0_BBI_RMW(x) ((x) << S_DEAD_CYCLE0_BBI_RMW)
73946 #define F_DEAD_CYCLE0_BBI_RMW    V_DEAD_CYCLE0_BBI_RMW(1U)
73949 #define V_DEAD_CYCLE1_BBI_RMW(x) ((x) << S_DEAD_CYCLE1_BBI_RMW)
73950 #define F_DEAD_CYCLE1_BBI_RMW    V_DEAD_CYCLE1_BBI_RMW(1U)
73953 #define V_DEAD_CYCLE0_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE0_PRE_REF_RMW)
73954 #define F_DEAD_CYCLE0_PRE_REF_RMW    V_DEAD_CYCLE0_PRE_REF_RMW(1U)
73957 #define V_DEAD_CYCLE1_PRE_REF_RMW(x) ((x) << S_DEAD_CYCLE1_PRE_REF_RMW)
73958 #define F_DEAD_CYCLE1_PRE_REF_RMW    V_DEAD_CYCLE1_PRE_REF_RMW(1U)
73960 #define S_DEAD_CYCLE0_POST_REF_RMW    1
73961 #define V_DEAD_CYCLE0_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE0_POST_REF_RMW)
73962 #define F_DEAD_CYCLE0_POST_REF_RMW    V_DEAD_CYCLE0_POST_REF_RMW(1U)
73965 #define V_DEAD_CYCLE1_POST_REF_RMW(x) ((x) << S_DEAD_CYCLE1_POST_REF_RMW)
73966 #define F_DEAD_CYCLE1_POST_REF_RMW    V_DEAD_CYCLE1_POST_REF_RMW(1U)
73971 #define V_ECMDNRE(x) ((x) << S_ECMDNRE)
73972 #define F_ECMDNRE    V_ECMDNRE(1U)
73975 #define V_ECMDNRB(x) ((x) << S_ECMDNRB)
73976 #define F_ECMDNRB    V_ECMDNRB(1U)
73979 #define V_ECMDWR(x) ((x) << S_ECMDWR)
73980 #define F_ECMDWR    V_ECMDWR(1U)
73984 #define V_ECMDLEN(x) ((x) << S_ECMDLEN)
73985 #define G_ECMDLEN(x) (((x) >> S_ECMDLEN) & M_ECMDLEN)
73989 #define V_ECMDADDR(x) ((x) << S_ECMDADDR)
73990 #define G_ECMDADDR(x) (((x) >> S_ECMDADDR) & M_ECMDADDR)
73995 #define V_REFDONE(x) ((x) << S_REFDONE)
73996 #define F_REFDONE    V_REFDONE(1U)
73999 #define V_REFCNTEXPR(x) ((x) << S_REFCNTEXPR)
74000 #define F_REFCNTEXPR    V_REFCNTEXPR(1U)
74004 #define V_REFPTR(x) ((x) << S_REFPTR)
74005 #define G_REFPTR(x) (((x) >> S_REFPTR) & M_REFPTR)
74009 #define V_REFCNT(x) ((x) << S_REFCNT)
74010 #define G_REFCNT(x) (((x) >> S_REFCNT) & M_REFCNT)
74015 #define V_STG_CMDQ_PARERR_CAUSE(x) ((x) << S_STG_CMDQ_PARERR_CAUSE)
74016 #define F_STG_CMDQ_PARERR_CAUSE    V_STG_CMDQ_PARERR_CAUSE(1U)
74019 #define V_STG_WRDQ_PARERR_CAUSE(x) ((x) << S_STG_WRDQ_PARERR_CAUSE)
74020 #define F_STG_WRDQ_PARERR_CAUSE    V_STG_WRDQ_PARERR_CAUSE(1U)
74023 #define V_INP_CMDQ_PARERR_CAUSE(x) ((x) << S_INP_CMDQ_PARERR_CAUSE)
74024 #define F_INP_CMDQ_PARERR_CAUSE    V_INP_CMDQ_PARERR_CAUSE(1U)
74027 #define V_INP_WRDQ_PARERR_CAUSE(x) ((x) << S_INP_WRDQ_PARERR_CAUSE)
74028 #define F_INP_WRDQ_PARERR_CAUSE    V_INP_WRDQ_PARERR_CAUSE(1U)
74031 #define V_INP_BEQ_PARERR_CAUSE(x) ((x) << S_INP_BEQ_PARERR_CAUSE)
74032 #define F_INP_BEQ_PARERR_CAUSE    V_INP_BEQ_PARERR_CAUSE(1U)
74035 #define V_ECC_CE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_CE_PAR_ENABLE_CAUSE)
74036 #define F_ECC_CE_PAR_ENABLE_CAUSE    V_ECC_CE_PAR_ENABLE_CAUSE(1U)
74038 #define S_ECC_UE_PAR_ENABLE_CAUSE    1
74039 #define V_ECC_UE_PAR_ENABLE_CAUSE(x) ((x) << S_ECC_UE_PAR_ENABLE_CAUSE)
74040 #define F_ECC_UE_PAR_ENABLE_CAUSE    V_ECC_UE_PAR_ENABLE_CAUSE(1U)
74043 #define V_RDDQ_PARERR_CAUSE(x) ((x) << S_RDDQ_PARERR_CAUSE)
74044 #define F_RDDQ_PARERR_CAUSE    V_RDDQ_PARERR_CAUSE(1U)
74054 #define V_T7_CLIENT_EN(x) ((x) << S_T7_CLIENT_EN)
74055 #define G_T7_CLIENT_EN(x) (((x) >> S_T7_CLIENT_EN) & M_T7_CLIENT_EN)
74059 #define V_TPH(x) ((x) << S_TPH)
74060 #define G_TPH(x) (((x) >> S_TPH) & M_TPH)
74063 #define V_TPH_V(x) ((x) << S_TPH_V)
74064 #define F_TPH_V    V_TPH_V(1U)
74068 #define V_DCA(x) ((x) << S_DCA)
74069 #define G_DCA(x) (((x) >> S_DCA) & M_DCA)
74074 #define V_OP_MODE(x) ((x) << S_OP_MODE)
74075 #define F_OP_MODE    V_OP_MODE(1U)
74078 #define V_GK_ENABLE(x) ((x) << S_GK_ENABLE)
74079 #define F_GK_ENABLE    V_GK_ENABLE(1U)
74082 #define V_DBGCNTRST(x) ((x) << S_DBGCNTRST)
74083 #define F_DBGCNTRST    V_DBGCNTRST(1U)
74088 #define V_INV_ALL(x) ((x) << S_INV_ALL)
74089 #define F_INV_ALL    V_INV_ALL(1U)
74092 #define V_LOCK_ENTRY(x) ((x) << S_LOCK_ENTRY)
74093 #define F_LOCK_ENTRY    V_LOCK_ENTRY(1U)
74097 #define V_E_SEL(x) ((x) << S_E_SEL)
74098 #define G_E_SEL(x) (((x) >> S_E_SEL) & M_E_SEL)
74104 #define V_VA(x) ((x) << S_VA)
74105 #define G_VA(x) (((x) >> S_VA) & M_VA)
74108 #define V_VALID_E(x) ((x) << S_VALID_E)
74109 #define F_VALID_E    V_VALID_E(1U)
74112 #define V_LOCK_HMA(x) ((x) << S_LOCK_HMA)
74113 #define F_LOCK_HMA    V_LOCK_HMA(1U)
74116 #define V_T6_USED(x) ((x) << S_T6_USED)
74117 #define F_T6_USED    V_T6_USED(1U)
74121 #define V_REGION(x) ((x) << S_REGION)
74122 #define G_REGION(x) (((x) >> S_REGION) & M_REGION)
74126 #define V_T7_VA(x) ((x) << S_T7_VA)
74127 #define G_T7_VA(x) (((x) >> S_T7_VA) & M_T7_VA)
74149 #define V_ADDR0_MIN(x) ((x) << S_ADDR0_MIN)
74150 #define G_ADDR0_MIN(x) (((x) >> S_ADDR0_MIN) & M_ADDR0_MIN)
74154 #define V_REG0MINADDR0MIN(x) ((x) << S_REG0MINADDR0MIN)
74155 #define G_REG0MINADDR0MIN(x) (((x) >> S_REG0MINADDR0MIN) & M_REG0MINADDR0MIN)
74161 #define V_ADDR0_MAX(x) ((x) << S_ADDR0_MAX)
74162 #define G_ADDR0_MAX(x) (((x) >> S_ADDR0_MAX) & M_ADDR0_MAX)
74166 #define V_REG0MAXADDR0MAX(x) ((x) << S_REG0MAXADDR0MAX)
74167 #define G_REG0MAXADDR0MAX(x) (((x) >> S_REG0MAXADDR0MAX) & M_REG0MAXADDR0MAX)
74173 #define V_PAGE_SIZE0(x) ((x) << S_PAGE_SIZE0)
74174 #define G_PAGE_SIZE0(x) (((x) >> S_PAGE_SIZE0) & M_PAGE_SIZE0)
74182 #define V_ADDR1_MIN(x) ((x) << S_ADDR1_MIN)
74183 #define G_ADDR1_MIN(x) (((x) >> S_ADDR1_MIN) & M_ADDR1_MIN)
74187 #define V_REG1MINADDR1MIN(x) ((x) << S_REG1MINADDR1MIN)
74188 #define G_REG1MINADDR1MIN(x) (((x) >> S_REG1MINADDR1MIN) & M_REG1MINADDR1MIN)
74194 #define V_ADDR1_MAX(x) ((x) << S_ADDR1_MAX)
74195 #define G_ADDR1_MAX(x) (((x) >> S_ADDR1_MAX) & M_ADDR1_MAX)
74199 #define V_REG1MAXADDR1MAX(x) ((x) << S_REG1MAXADDR1MAX)
74200 #define G_REG1MAXADDR1MAX(x) (((x) >> S_REG1MAXADDR1MAX) & M_REG1MAXADDR1MAX)
74206 #define V_PAGE_SIZE1(x) ((x) << S_PAGE_SIZE1)
74207 #define G_PAGE_SIZE1(x) (((x) >> S_PAGE_SIZE1) & M_PAGE_SIZE1)
74215 #define V_ADDR2_MIN(x) ((x) << S_ADDR2_MIN)
74216 #define G_ADDR2_MIN(x) (((x) >> S_ADDR2_MIN) & M_ADDR2_MIN)
74220 #define V_REG2MINADDR2MIN(x) ((x) << S_REG2MINADDR2MIN)
74221 #define G_REG2MINADDR2MIN(x) (((x) >> S_REG2MINADDR2MIN) & M_REG2MINADDR2MIN)
74227 #define V_ADDR2_MAX(x) ((x) << S_ADDR2_MAX)
74228 #define G_ADDR2_MAX(x) (((x) >> S_ADDR2_MAX) & M_ADDR2_MAX)
74232 #define V_REG2MAXADDR2MAX(x) ((x) << S_REG2MAXADDR2MAX)
74233 #define G_REG2MAXADDR2MAX(x) (((x) >> S_REG2MAXADDR2MAX) & M_REG2MAXADDR2MAX)
74239 #define V_PAGE_SIZE2(x) ((x) << S_PAGE_SIZE2)
74240 #define G_PAGE_SIZE2(x) (((x) >> S_PAGE_SIZE2) & M_PAGE_SIZE2)
74248 #define V_ADDR3_MIN(x) ((x) << S_ADDR3_MIN)
74249 #define G_ADDR3_MIN(x) (((x) >> S_ADDR3_MIN) & M_ADDR3_MIN)
74253 #define V_REG3MINADDR3MIN(x) ((x) << S_REG3MINADDR3MIN)
74254 #define G_REG3MINADDR3MIN(x) (((x) >> S_REG3MINADDR3MIN) & M_REG3MINADDR3MIN)
74260 #define V_ADDR3_MAX(x) ((x) << S_ADDR3_MAX)
74261 #define G_ADDR3_MAX(x) (((x) >> S_ADDR3_MAX) & M_ADDR3_MAX)
74265 #define V_REG3MAXADDR3MAX(x) ((x) << S_REG3MAXADDR3MAX)
74266 #define G_REG3MAXADDR3MAX(x) (((x) >> S_REG3MAXADDR3MAX) & M_REG3MAXADDR3MAX)
74272 #define V_PAGE_SIZE3(x) ((x) << S_PAGE_SIZE3)
74273 #define G_PAGE_SIZE3(x) (((x) >> S_PAGE_SIZE3) & M_PAGE_SIZE3)
74280 #define V_ENTER_SYNC(x) ((x) << S_ENTER_SYNC)
74281 #define F_ENTER_SYNC    V_ENTER_SYNC(1U)
74284 #define V_EXIT_SYNC(x) ((x) << S_EXIT_SYNC)
74285 #define F_EXIT_SYNC    V_EXIT_SYNC(1U)
74291 #define V_MODE_SEL(x) ((x) << S_MODE_SEL)
74292 #define G_MODE_SEL(x) (((x) >> S_MODE_SEL) & M_MODE_SEL)
74295 #define V_FLUSH_REQ(x) ((x) << S_FLUSH_REQ)
74296 #define F_FLUSH_REQ    V_FLUSH_REQ(1U)
74299 #define V_CLEAR_REQ(x) ((x) << S_CLEAR_REQ)
74300 #define F_CLEAR_REQ    V_CLEAR_REQ(1U)
74306 #define V_BASE0_MSB(x) ((x) << S_BASE0_MSB)
74307 #define G_BASE0_MSB(x) (((x) >> S_BASE0_MSB) & M_BASE0_MSB)
74313 #define V_BASE1_MSB(x) ((x) << S_BASE1_MSB)
74314 #define G_BASE1_MSB(x) (((x) >> S_BASE1_MSB) & M_BASE1_MSB)
74320 #define V_BASE2_MSB(x) ((x) << S_BASE2_MSB)
74321 #define G_BASE2_MSB(x) (((x) >> S_BASE2_MSB) & M_BASE2_MSB)
74327 #define V_BASE3_MSB(x) ((x) << S_BASE3_MSB)
74328 #define G_BASE3_MSB(x) (((x) >> S_BASE3_MSB) & M_BASE3_MSB)
74347 #define V_STARTA(x) ((x) << S_STARTA)
74348 #define G_STARTA(x) (((x) >> S_STARTA) & M_STARTA)
74354 #define V_ENDA(x) ((x) << S_ENDA)
74355 #define G_ENDA(x) (((x) >> S_ENDA) & M_ENDA)
74358 #define V_GK_UF_PAR_ENABLE(x) ((x) << S_GK_UF_PAR_ENABLE)
74359 #define F_GK_UF_PAR_ENABLE    V_GK_UF_PAR_ENABLE(1U)
74362 #define V_PCIEMST_PAR_ENABLE(x) ((x) << S_PCIEMST_PAR_ENABLE)
74363 #define F_PCIEMST_PAR_ENABLE    V_PCIEMST_PAR_ENABLE(1U)
74366 #define V_IDTF_INT_ENABLE(x) ((x) << S_IDTF_INT_ENABLE)
74367 #define F_IDTF_INT_ENABLE    V_IDTF_INT_ENABLE(1U)
74370 #define V_OTF_INT_ENABLE(x) ((x) << S_OTF_INT_ENABLE)
74371 #define F_OTF_INT_ENABLE    V_OTF_INT_ENABLE(1U)
74374 #define V_RTF_INT_ENABLE(x) ((x) << S_RTF_INT_ENABLE)
74375 #define F_RTF_INT_ENABLE    V_RTF_INT_ENABLE(1U)
74378 #define V_PCIEMST_INT_ENABLE(x) ((x) << S_PCIEMST_INT_ENABLE)
74379 #define F_PCIEMST_INT_ENABLE    V_PCIEMST_INT_ENABLE(1U)
74381 #define S_MAMST_INT_ENABLE    1
74382 #define V_MAMST_INT_ENABLE(x) ((x) << S_MAMST_INT_ENABLE)
74383 #define F_MAMST_INT_ENABLE    V_MAMST_INT_ENABLE(1U)
74386 #define V_GK_UF_INT_ENABLE(x) ((x) << S_GK_UF_INT_ENABLE)
74387 #define F_GK_UF_INT_ENABLE    V_GK_UF_INT_ENABLE(1U)
74390 #define V_IDTF_INT_CAUSE(x) ((x) << S_IDTF_INT_CAUSE)
74391 #define F_IDTF_INT_CAUSE    V_IDTF_INT_CAUSE(1U)
74394 #define V_OTF_INT_CAUSE(x) ((x) << S_OTF_INT_CAUSE)
74395 #define F_OTF_INT_CAUSE    V_OTF_INT_CAUSE(1U)
74398 #define V_RTF_INT_CAUSE(x) ((x) << S_RTF_INT_CAUSE)
74399 #define F_RTF_INT_CAUSE    V_RTF_INT_CAUSE(1U)
74402 #define V_PCIEMST_INT_CAUSE(x) ((x) << S_PCIEMST_INT_CAUSE)
74403 #define F_PCIEMST_INT_CAUSE    V_PCIEMST_INT_CAUSE(1U)
74405 #define S_MAMST_INT_CAUSE    1
74406 #define V_MAMST_INT_CAUSE(x) ((x) << S_MAMST_INT_CAUSE)
74407 #define F_MAMST_INT_CAUSE    V_MAMST_INT_CAUSE(1U)
74410 #define V_GK_UF_INT_CAUSE(x) ((x) << S_GK_UF_INT_CAUSE)
74411 #define F_GK_UF_INT_CAUSE    V_GK_UF_INT_CAUSE(1U)
74420 #define V_RTF(x) ((x) << S_RTF)
74421 #define F_RTF    V_RTF(1U)
74424 #define V_OTF(x) ((x) << S_OTF)
74425 #define F_OTF    V_OTF(1U)
74428 #define V_IDTF(x) ((x) << S_IDTF)
74429 #define F_IDTF    V_IDTF(1U)
74437 #define V_EDC_FSM(x) ((x) << S_EDC_FSM)
74438 #define G_EDC_FSM(x) (((x) >> S_EDC_FSM) & M_EDC_FSM)
74442 #define V_RAS_FSM_SLV(x) ((x) << S_RAS_FSM_SLV)
74443 #define G_RAS_FSM_SLV(x) (((x) >> S_RAS_FSM_SLV) & M_RAS_FSM_SLV)
74447 #define V_FC_FSM(x) ((x) << S_FC_FSM)
74448 #define G_FC_FSM(x) (((x) >> S_FC_FSM) & M_FC_FSM)
74452 #define V_COOKIE_ARB_FSM(x) ((x) << S_COOKIE_ARB_FSM)
74453 #define G_COOKIE_ARB_FSM(x) (((x) >> S_COOKIE_ARB_FSM) & M_COOKIE_ARB_FSM)
74457 #define V_PCIE_CHUNK_FSM(x) ((x) << S_PCIE_CHUNK_FSM)
74458 #define G_PCIE_CHUNK_FSM(x) (((x) >> S_PCIE_CHUNK_FSM) & M_PCIE_CHUNK_FSM)
74462 #define V_WTRANSFER_FSM(x) ((x) << S_WTRANSFER_FSM)
74463 #define G_WTRANSFER_FSM(x) (((x) >> S_WTRANSFER_FSM) & M_WTRANSFER_FSM)
74467 #define V_WD_FSM(x) ((x) << S_WD_FSM)
74468 #define G_WD_FSM(x) (((x) >> S_WD_FSM) & M_WD_FSM)
74472 #define V_RD_FSM(x) ((x) << S_RD_FSM)
74473 #define G_RD_FSM(x) (((x) >> S_RD_FSM) & M_RD_FSM)
74479 #define V_SYNC_FSM(x) ((x) << S_SYNC_FSM)
74480 #define G_SYNC_FSM(x) (((x) >> S_SYNC_FSM) & M_SYNC_FSM)
74484 #define V_OCHK_FSM(x) ((x) << S_OCHK_FSM)
74485 #define G_OCHK_FSM(x) (((x) >> S_OCHK_FSM) & M_OCHK_FSM)
74489 #define V_TLB_FSM(x) ((x) << S_TLB_FSM)
74490 #define G_TLB_FSM(x) (((x) >> S_TLB_FSM) & M_TLB_FSM)
74494 #define V_PIO_FSM(x) ((x) << S_PIO_FSM)
74495 #define G_PIO_FSM(x) (((x) >> S_PIO_FSM) & M_PIO_FSM)
74500 #define V_T6_H_REQVLD(x) ((x) << S_T6_H_REQVLD)
74501 #define F_T6_H_REQVLD    V_T6_H_REQVLD(1U)
74504 #define V_H_REQFULL(x) ((x) << S_H_REQFULL)
74505 #define F_H_REQFULL    V_H_REQFULL(1U)
74508 #define V_H_REQSOP(x) ((x) << S_H_REQSOP)
74509 #define F_H_REQSOP    V_H_REQSOP(1U)
74512 #define V_H_REQEOP(x) ((x) << S_H_REQEOP)
74513 #define F_H_REQEOP    V_H_REQEOP(1U)
74516 #define V_T6_H_RSPVLD(x) ((x) << S_T6_H_RSPVLD)
74517 #define F_T6_H_RSPVLD    V_T6_H_RSPVLD(1U)
74520 #define V_H_RSPFULL(x) ((x) << S_H_RSPFULL)
74521 #define F_H_RSPFULL    V_H_RSPFULL(1U)
74524 #define V_H_RSPSOP(x) ((x) << S_H_RSPSOP)
74525 #define F_H_RSPSOP    V_H_RSPSOP(1U)
74528 #define V_H_RSPEOP(x) ((x) << S_H_RSPEOP)
74529 #define F_H_RSPEOP    V_H_RSPEOP(1U)
74532 #define V_H_RSPERR(x) ((x) << S_H_RSPERR)
74533 #define F_H_RSPERR    V_H_RSPERR(1U)
74536 #define V_PCIE_CMD_AVAIL(x) ((x) << S_PCIE_CMD_AVAIL)
74537 #define F_PCIE_CMD_AVAIL    V_PCIE_CMD_AVAIL(1U)
74540 #define V_PCIE_CMD_RDY(x) ((x) << S_PCIE_CMD_RDY)
74541 #define F_PCIE_CMD_RDY    V_PCIE_CMD_RDY(1U)
74544 #define V_PCIE_WNR(x) ((x) << S_PCIE_WNR)
74545 #define F_PCIE_WNR    V_PCIE_WNR(1U)
74549 #define V_PCIE_LEN(x) ((x) << S_PCIE_LEN)
74550 #define G_PCIE_LEN(x) (((x) >> S_PCIE_LEN) & M_PCIE_LEN)
74553 #define V_PCIE_TRWDAT_RDY(x) ((x) << S_PCIE_TRWDAT_RDY)
74554 #define F_PCIE_TRWDAT_RDY    V_PCIE_TRWDAT_RDY(1U)
74557 #define V_PCIE_TRWDAT_AVAIL(x) ((x) << S_PCIE_TRWDAT_AVAIL)
74558 #define F_PCIE_TRWDAT_AVAIL    V_PCIE_TRWDAT_AVAIL(1U)
74561 #define V_PCIE_TRWSOP(x) ((x) << S_PCIE_TRWSOP)
74562 #define F_PCIE_TRWSOP    V_PCIE_TRWSOP(1U)
74565 #define V_PCIE_TRWEOP(x) ((x) << S_PCIE_TRWEOP)
74566 #define F_PCIE_TRWEOP    V_PCIE_TRWEOP(1U)
74569 #define V_PCIE_TRRDAT_RDY(x) ((x) << S_PCIE_TRRDAT_RDY)
74570 #define F_PCIE_TRRDAT_RDY    V_PCIE_TRRDAT_RDY(1U)
74573 #define V_PCIE_TRRDAT_AVAIL(x) ((x) << S_PCIE_TRRDAT_AVAIL)
74574 #define F_PCIE_TRRDAT_AVAIL    V_PCIE_TRRDAT_AVAIL(1U)
74577 #define V_PCIE_TRRSOP(x) ((x) << S_PCIE_TRRSOP)
74578 #define F_PCIE_TRRSOP    V_PCIE_TRRSOP(1U)
74580 #define S_PCIE_TRREOP    1
74581 #define V_PCIE_TRREOP(x) ((x) << S_PCIE_TRREOP)
74582 #define F_PCIE_TRREOP    V_PCIE_TRREOP(1U)
74585 #define V_PCIE_TRRERR(x) ((x) << S_PCIE_TRRERR)
74586 #define F_PCIE_TRRERR    V_PCIE_TRRERR(1U)
74594 #define V_REQDATA2(x) ((x) << S_REQDATA2)
74595 #define G_REQDATA2(x) (((x) >> S_REQDATA2) & M_REQDATA2)
74599 #define V_REQDATA1(x) ((x) << S_REQDATA1)
74600 #define G_REQDATA1(x) (((x) >> S_REQDATA1) & M_REQDATA1)
74604 #define V_REQDATA0(x) ((x) << S_REQDATA0)
74605 #define G_REQDATA0(x) (((x) >> S_REQDATA0) & M_REQDATA0)
74611 #define V_RSPDATA3(x) ((x) << S_RSPDATA3)
74612 #define G_RSPDATA3(x) (((x) >> S_RSPDATA3) & M_RSPDATA3)
74616 #define V_RSPDATA2(x) ((x) << S_RSPDATA2)
74617 #define G_RSPDATA2(x) (((x) >> S_RSPDATA2) & M_RSPDATA2)
74621 #define V_RSPDATA1(x) ((x) << S_RSPDATA1)
74622 #define G_RSPDATA1(x) (((x) >> S_RSPDATA1) & M_RSPDATA1)
74626 #define V_RSPDATA0(x) ((x) << S_RSPDATA0)
74627 #define G_RSPDATA0(x) (((x) >> S_RSPDATA0) & M_RSPDATA0)
74632 #define V_MA_CMD_AVAIL(x) ((x) << S_MA_CMD_AVAIL)
74633 #define F_MA_CMD_AVAIL    V_MA_CMD_AVAIL(1U)
74637 #define V_MA_CLNT(x) ((x) << S_MA_CLNT)
74638 #define G_MA_CLNT(x) (((x) >> S_MA_CLNT) & M_MA_CLNT)
74641 #define V_MA_WNR(x) ((x) << S_MA_WNR)
74642 #define F_MA_WNR    V_MA_WNR(1U)
74646 #define V_MA_LEN(x) ((x) << S_MA_LEN)
74647 #define G_MA_LEN(x) (((x) >> S_MA_LEN) & M_MA_LEN)
74650 #define V_MA_MST_RD(x) ((x) << S_MA_MST_RD)
74651 #define F_MA_MST_RD    V_MA_MST_RD(1U)
74654 #define V_MA_MST_VLD(x) ((x) << S_MA_MST_VLD)
74655 #define F_MA_MST_VLD    V_MA_MST_VLD(1U)
74658 #define V_MA_MST_ERR(x) ((x) << S_MA_MST_ERR)
74659 #define F_MA_MST_ERR    V_MA_MST_ERR(1U)
74662 #define V_MAS_TLB_REQ(x) ((x) << S_MAS_TLB_REQ)
74663 #define F_MAS_TLB_REQ    V_MAS_TLB_REQ(1U)
74665 #define S_MAS_TLB_ACK    1
74666 #define V_MAS_TLB_ACK(x) ((x) << S_MAS_TLB_ACK)
74667 #define F_MAS_TLB_ACK    V_MAS_TLB_ACK(1U)
74670 #define V_MAS_TLB_ERR(x) ((x) << S_MAS_TLB_ERR)
74671 #define F_MAS_TLB_ERR    V_MAS_TLB_ERR(1U)
74680 #define V_LKP_REQ_VLD(x) ((x) << S_LKP_REQ_VLD)
74681 #define F_LKP_REQ_VLD    V_LKP_REQ_VLD(1U)
74683 #define S_LKP_DESC_SEL    1
74685 #define V_LKP_DESC_SEL(x) ((x) << S_LKP_DESC_SEL)
74686 #define G_LKP_DESC_SEL(x) (((x) >> S_LKP_DESC_SEL) & M_LKP_DESC_SEL)
74689 #define V_LKP_RSP_VLD(x) ((x) << S_LKP_RSP_VLD)
74690 #define F_LKP_RSP_VLD    V_LKP_RSP_VLD(1U)
74714 #define V_WR_EOP_CNT(x) ((x) << S_WR_EOP_CNT)
74715 #define G_WR_EOP_CNT(x) (((x) >> S_WR_EOP_CNT) & M_WR_EOP_CNT)
74719 #define V_RD_SOP_CNT(x) ((x) << S_RD_SOP_CNT)
74720 #define G_RD_SOP_CNT(x) (((x) >> S_RD_SOP_CNT) & M_RD_SOP_CNT)
74724 #define V_RD_EOP_CNT(x) ((x) << S_RD_EOP_CNT)
74725 #define G_RD_EOP_CNT(x) (((x) >> S_RD_EOP_CNT) & M_RD_EOP_CNT)
74729 #define V_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
74730 #define G_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT)
74734 #define V_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
74735 #define G_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT)
74739 #define V_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) ((x) << S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
74740 #define G_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT(x) (((x) >> S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT) & M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT)
74747 #define V_T7_PORT_MAP(x) ((x) << S_T7_PORT_MAP)
74748 #define G_T7_PORT_MAP(x) (((x) >> S_T7_PORT_MAP) & M_T7_PORT_MAP)
74752 #define V_T7_SMUX_RX_LOOP(x) ((x) << S_T7_SMUX_RX_LOOP)
74753 #define G_T7_SMUX_RX_LOOP(x) (((x) >> S_T7_SMUX_RX_LOOP) & M_T7_SMUX_RX_LOOP)
74756 #define V_T7_SIGNAL_DET(x) ((x) << S_T7_SIGNAL_DET)
74757 #define F_T7_SIGNAL_DET    V_T7_SIGNAL_DET(1U)
74760 #define V_CFG_MAC_2_MPS_FULL(x) ((x) << S_CFG_MAC_2_MPS_FULL)
74761 #define F_CFG_MAC_2_MPS_FULL    V_CFG_MAC_2_MPS_FULL(1U)
74764 #define V_MPS_FULL_SEL(x) ((x) << S_MPS_FULL_SEL)
74765 #define F_MPS_FULL_SEL    V_MPS_FULL_SEL(1U)
74769 #define V_T7_SMUXTXSEL(x) ((x) << S_T7_SMUXTXSEL)
74770 #define G_T7_SMUXTXSEL(x) (((x) >> S_T7_SMUXTXSEL) & M_T7_SMUXTXSEL)
74774 #define V_T7_PORTSPEED(x) ((x) << S_T7_PORTSPEED)
74775 #define G_T7_PORTSPEED(x) (((x) >> S_T7_PORTSPEED) & M_T7_PORTSPEED)
74778 #define V_MTIP_REG_RESET(x) ((x) << S_MTIP_REG_RESET)
74779 #define F_MTIP_REG_RESET    V_MTIP_REG_RESET(1U)
74782 #define V_RESET_REG_CLK_I(x) ((x) << S_RESET_REG_CLK_I)
74783 #define F_RESET_REG_CLK_I    V_RESET_REG_CLK_I(1U)
74787 #define V_T7_LED1_CFG1(x) ((x) << S_T7_LED1_CFG1)
74788 #define G_T7_LED1_CFG1(x) (((x) >> S_T7_LED1_CFG1) & M_T7_LED1_CFG1)
74792 #define V_T7_LED0_CFG1(x) ((x) << S_T7_LED0_CFG1)
74793 #define G_T7_LED0_CFG1(x) (((x) >> S_T7_LED0_CFG1) & M_T7_LED0_CFG1)
74800 #define V_EGR_SE_CNT_ERR(x) ((x) << S_EGR_SE_CNT_ERR)
74801 #define F_EGR_SE_CNT_ERR    V_EGR_SE_CNT_ERR(1U)
74804 #define V_INGR_SE_CNT_ERR(x) ((x) << S_INGR_SE_CNT_ERR)
74805 #define F_INGR_SE_CNT_ERR    V_INGR_SE_CNT_ERR(1U)
74810 #define V_PERR_PCSR_FDM_3(x) ((x) << S_PERR_PCSR_FDM_3)
74811 #define F_PERR_PCSR_FDM_3    V_PERR_PCSR_FDM_3(1U)
74814 #define V_PERR_PCSR_FDM_2(x) ((x) << S_PERR_PCSR_FDM_2)
74815 #define F_PERR_PCSR_FDM_2    V_PERR_PCSR_FDM_2(1U)
74818 #define V_PERR_PCSR_FDM_1(x) ((x) << S_PERR_PCSR_FDM_1)
74819 #define F_PERR_PCSR_FDM_1    V_PERR_PCSR_FDM_1(1U)
74822 #define V_PERR_PCSR_FDM_0(x) ((x) << S_PERR_PCSR_FDM_0)
74823 #define F_PERR_PCSR_FDM_0    V_PERR_PCSR_FDM_0(1U)
74826 #define V_PERR_PCSR_FM_3(x) ((x) << S_PERR_PCSR_FM_3)
74827 #define F_PERR_PCSR_FM_3    V_PERR_PCSR_FM_3(1U)
74830 #define V_PERR_PCSR_FM_2(x) ((x) << S_PERR_PCSR_FM_2)
74831 #define F_PERR_PCSR_FM_2    V_PERR_PCSR_FM_2(1U)
74834 #define V_PERR_PCSR_FM_1(x) ((x) << S_PERR_PCSR_FM_1)
74835 #define F_PERR_PCSR_FM_1    V_PERR_PCSR_FM_1(1U)
74838 #define V_PERR_PCSR_FM_0(x) ((x) << S_PERR_PCSR_FM_0)
74839 #define F_PERR_PCSR_FM_0    V_PERR_PCSR_FM_0(1U)
74842 #define V_PERR_PCSR_DM_1(x) ((x) << S_PERR_PCSR_DM_1)
74843 #define F_PERR_PCSR_DM_1    V_PERR_PCSR_DM_1(1U)
74846 #define V_PERR_PCSR_DM_0(x) ((x) << S_PERR_PCSR_DM_0)
74847 #define F_PERR_PCSR_DM_0    V_PERR_PCSR_DM_0(1U)
74850 #define V_PERR_PCSR_DK_3(x) ((x) << S_PERR_PCSR_DK_3)
74851 #define F_PERR_PCSR_DK_3    V_PERR_PCSR_DK_3(1U)
74854 #define V_PERR_PCSR_DK_2(x) ((x) << S_PERR_PCSR_DK_2)
74855 #define F_PERR_PCSR_DK_2    V_PERR_PCSR_DK_2(1U)
74858 #define V_PERR_PCSR_DK_1(x) ((x) << S_PERR_PCSR_DK_1)
74859 #define F_PERR_PCSR_DK_1    V_PERR_PCSR_DK_1(1U)
74862 #define V_PERR_PCSR_DK_0(x) ((x) << S_PERR_PCSR_DK_0)
74863 #define F_PERR_PCSR_DK_0    V_PERR_PCSR_DK_0(1U)
74866 #define V_PERR_F91RO_1(x) ((x) << S_PERR_F91RO_1)
74867 #define F_PERR_F91RO_1    V_PERR_F91RO_1(1U)
74870 #define V_PERR_F91RO_0(x) ((x) << S_PERR_F91RO_0)
74871 #define F_PERR_F91RO_0    V_PERR_F91RO_0(1U)
74874 #define V_PERR_PCSR_F91DM(x) ((x) << S_PERR_PCSR_F91DM)
74875 #define F_PERR_PCSR_F91DM    V_PERR_PCSR_F91DM(1U)
74878 #define V_PERR_PCSR_F91TI(x) ((x) << S_PERR_PCSR_F91TI)
74879 #define F_PERR_PCSR_F91TI    V_PERR_PCSR_F91TI(1U)
74882 #define V_PERR_PCSR_F91TO(x) ((x) << S_PERR_PCSR_F91TO)
74883 #define F_PERR_PCSR_F91TO    V_PERR_PCSR_F91TO(1U)
74886 #define V_PERR_PCSR_F91M(x) ((x) << S_PERR_PCSR_F91M)
74887 #define F_PERR_PCSR_F91M    V_PERR_PCSR_F91M(1U)
74889 #define S_PERR_PCSR_80_16_1    1
74890 #define V_PERR_PCSR_80_16_1(x) ((x) << S_PERR_PCSR_80_16_1)
74891 #define F_PERR_PCSR_80_16_1    V_PERR_PCSR_80_16_1(1U)
74894 #define V_PERR_PCSR_80_16_0(x) ((x) << S_PERR_PCSR_80_16_0)
74895 #define F_PERR_PCSR_80_16_0    V_PERR_PCSR_80_16_0(1U)
74902 #define V_PEER_DELAY_VAL(x) ((x) << S_PEER_DELAY_VAL)
74903 #define F_PEER_DELAY_VAL    V_PEER_DELAY_VAL(1U)
74905 #define S_PEER_DELAY    1
74907 #define V_PEER_DELAY(x) ((x) << S_PEER_DELAY)
74908 #define G_PEER_DELAY(x) (((x) >> S_PEER_DELAY) & M_PEER_DELAY)
74911 #define V_MODE1S_ENA(x) ((x) << S_MODE1S_ENA)
74912 #define F_MODE1S_ENA    V_MODE1S_ENA(1U)
74917 #define V_TX_STOP(x) ((x) << S_TX_STOP)
74918 #define F_TX_STOP    V_TX_STOP(1U)
74921 #define V_T7_MODE1S_ENA(x) ((x) << S_T7_MODE1S_ENA)
74922 #define F_T7_MODE1S_ENA    V_T7_MODE1S_ENA(1U)
74926 #define V_TX_TS_ID(x) ((x) << S_TX_TS_ID)
74927 #define G_TX_TS_ID(x) (((x) >> S_TX_TS_ID) & M_TX_TS_ID)
74930 #define V_T7_TX_LI_FAULT(x) ((x) << S_T7_TX_LI_FAULT)
74931 #define F_T7_TX_LI_FAULT    V_T7_TX_LI_FAULT(1U)
74935 #define V_XOFF_GEN(x) ((x) << S_XOFF_GEN)
74936 #define G_XOFF_GEN(x) (((x) >> S_XOFF_GEN) & M_XOFF_GEN)
74938 #define S_TX_REM_FAULT    1
74939 #define V_TX_REM_FAULT(x) ((x) << S_TX_REM_FAULT)
74940 #define F_TX_REM_FAULT    V_TX_REM_FAULT(1U)
74943 #define V_TX_LOC_FAULT(x) ((x) << S_TX_LOC_FAULT)
74944 #define F_TX_LOC_FAULT    V_TX_LOC_FAULT(1U)
74950 #define V_FF_TX_RX_TS_NS(x) ((x) << S_FF_TX_RX_TS_NS)
74951 #define G_FF_TX_RX_TS_NS(x) (((x) >> S_FF_TX_RX_TS_NS) & M_FF_TX_RX_TS_NS)
74956 #define V_REG_LOWP(x) ((x) << S_REG_LOWP)
74957 #define F_REG_LOWP    V_REG_LOWP(1U)
74960 #define V_LI_FAULT(x) ((x) << S_LI_FAULT)
74961 #define F_LI_FAULT    V_LI_FAULT(1U)
74964 #define V_TX_ISIDLE(x) ((x) << S_TX_ISIDLE)
74965 #define F_TX_ISIDLE    V_TX_ISIDLE(1U)
74968 #define V_TX_UNDERFLOW(x) ((x) << S_TX_UNDERFLOW)
74969 #define F_TX_UNDERFLOW    V_TX_UNDERFLOW(1U)
74972 #define V_T7_TX_EMPTY(x) ((x) << S_T7_TX_EMPTY)
74973 #define F_T7_TX_EMPTY    V_T7_TX_EMPTY(1U)
74976 #define V_T7_1_REM_FAULT(x) ((x) << S_T7_1_REM_FAULT)
74977 #define F_T7_1_REM_FAULT    V_T7_1_REM_FAULT(1U)
74980 #define V_REG_TS_AVAIL(x) ((x) << S_REG_TS_AVAIL)
74981 #define F_REG_TS_AVAIL    V_REG_TS_AVAIL(1U)
74984 #define V_T7_PHY_TXENA(x) ((x) << S_T7_PHY_TXENA)
74985 #define F_T7_PHY_TXENA    V_T7_PHY_TXENA(1U)
74988 #define V_T7_PFC_MODE(x) ((x) << S_T7_PFC_MODE)
74989 #define F_T7_PFC_MODE    V_T7_PFC_MODE(1U)
74993 #define V_PAUSE_ON(x) ((x) << S_PAUSE_ON)
74994 #define G_PAUSE_ON(x) (((x) >> S_PAUSE_ON) & M_PAUSE_ON)
74997 #define V_MAC_PAUSE_EN(x) ((x) << S_MAC_PAUSE_EN)
74998 #define F_MAC_PAUSE_EN    V_MAC_PAUSE_EN(1U)
75001 #define V_MAC_ENABLE(x) ((x) << S_MAC_ENABLE)
75002 #define F_MAC_ENABLE    V_MAC_ENABLE(1U)
75005 #define V_LOOP_ENA(x) ((x) << S_LOOP_ENA)
75006 #define F_LOOP_ENA    V_LOOP_ENA(1U)
75008 #define S_LOC_FAULT    1
75009 #define V_LOC_FAULT(x) ((x) << S_LOC_FAULT)
75010 #define F_LOC_FAULT    V_LOC_FAULT(1U)
75013 #define V_FF_RX_EMPTY(x) ((x) << S_FF_RX_EMPTY)
75014 #define F_FF_RX_EMPTY    V_FF_RX_EMPTY(1U)
75019 #define V_AN_VAL_AN(x) ((x) << S_AN_VAL_AN)
75020 #define F_AN_VAL_AN    V_AN_VAL_AN(1U)
75023 #define V_AN_TR_DIS_STATUS_AN(x) ((x) << S_AN_TR_DIS_STATUS_AN)
75024 #define F_AN_TR_DIS_STATUS_AN    V_AN_TR_DIS_STATUS_AN(1U)
75027 #define V_AN_STATUS_AN(x) ((x) << S_AN_STATUS_AN)
75028 #define F_AN_STATUS_AN    V_AN_STATUS_AN(1U)
75032 #define V_AN_SELECT_AN(x) ((x) << S_AN_SELECT_AN)
75033 #define G_AN_SELECT_AN(x) (((x) >> S_AN_SELECT_AN) & M_AN_SELECT_AN)
75036 #define V_AN_RS_FEC_ENA_AN(x) ((x) << S_AN_RS_FEC_ENA_AN)
75037 #define F_AN_RS_FEC_ENA_AN    V_AN_RS_FEC_ENA_AN(1U)
75040 #define V_AN_INT_AN(x) ((x) << S_AN_INT_AN)
75041 #define F_AN_INT_AN    V_AN_INT_AN(1U)
75044 #define V_AN_FEC_ENA_AN(x) ((x) << S_AN_FEC_ENA_AN)
75045 #define F_AN_FEC_ENA_AN    V_AN_FEC_ENA_AN(1U)
75048 #define V_AN_DONE_AN(x) ((x) << S_AN_DONE_AN)
75049 #define F_AN_DONE_AN    V_AN_DONE_AN(1U)
75053 #define V_AN_STATE(x) ((x) << S_AN_STATE)
75054 #define G_AN_STATE(x) (((x) >> S_AN_STATE) & M_AN_STATE)
75066 #define V_MAC2MPS_PERR(x) ((x) << S_MAC2MPS_PERR)
75067 #define F_MAC2MPS_PERR    V_MAC2MPS_PERR(1U)
75070 #define V_MAC_PPS_INT_EN(x) ((x) << S_MAC_PPS_INT_EN)
75071 #define F_MAC_PPS_INT_EN    V_MAC_PPS_INT_EN(1U)
75074 #define V_MAC_TX_TS_AVAIL_INT_EN(x) ((x) << S_MAC_TX_TS_AVAIL_INT_EN)
75075 #define F_MAC_TX_TS_AVAIL_INT_EN    V_MAC_TX_TS_AVAIL_INT_EN(1U)
75078 #define V_MAC_SINGLE_ALARM_INT_EN(x) ((x) << S_MAC_SINGLE_ALARM_INT_EN)
75079 #define F_MAC_SINGLE_ALARM_INT_EN    V_MAC_SINGLE_ALARM_INT_EN(1U)
75082 #define V_MAC_PERIODIC_ALARM_INT_EN(x) ((x) << S_MAC_PERIODIC_ALARM_INT_EN)
75083 #define F_MAC_PERIODIC_ALARM_INT_EN    V_MAC_PERIODIC_ALARM_INT_EN(1U)
75086 #define V_MAC_PATDETWAKE_INT_EN(x) ((x) << S_MAC_PATDETWAKE_INT_EN)
75087 #define F_MAC_PATDETWAKE_INT_EN    V_MAC_PATDETWAKE_INT_EN(1U)
75090 #define V_MAC_MAGIC_WAKE_INT_EN(x) ((x) << S_MAC_MAGIC_WAKE_INT_EN)
75091 #define F_MAC_MAGIC_WAKE_INT_EN    V_MAC_MAGIC_WAKE_INT_EN(1U)
75094 #define V_MAC_SIGDETCHG_INT_EN(x) ((x) << S_MAC_SIGDETCHG_INT_EN)
75095 #define F_MAC_SIGDETCHG_INT_EN    V_MAC_SIGDETCHG_INT_EN(1U)
75098 #define V_MAC_PCS_LINK_GOOD_EN(x) ((x) << S_MAC_PCS_LINK_GOOD_EN)
75099 #define F_MAC_PCS_LINK_GOOD_EN    V_MAC_PCS_LINK_GOOD_EN(1U)
75102 #define V_MAC_PCS_LINK_FAIL_EN(x) ((x) << S_MAC_PCS_LINK_FAIL_EN)
75103 #define F_MAC_PCS_LINK_FAIL_EN    V_MAC_PCS_LINK_FAIL_EN(1U)
75106 #define V_MAC_OVRFLOW_INT_EN(x) ((x) << S_MAC_OVRFLOW_INT_EN)
75107 #define F_MAC_OVRFLOW_INT_EN    V_MAC_OVRFLOW_INT_EN(1U)
75110 #define V_MAC_REM_FAULT_INT_EN(x) ((x) << S_MAC_REM_FAULT_INT_EN)
75111 #define F_MAC_REM_FAULT_INT_EN    V_MAC_REM_FAULT_INT_EN(1U)
75114 #define V_MAC_LOC_FAULT_INT_EN(x) ((x) << S_MAC_LOC_FAULT_INT_EN)
75115 #define F_MAC_LOC_FAULT_INT_EN    V_MAC_LOC_FAULT_INT_EN(1U)
75118 #define V_MAC_LINK_DOWN_INT_EN(x) ((x) << S_MAC_LINK_DOWN_INT_EN)
75119 #define F_MAC_LINK_DOWN_INT_EN    V_MAC_LINK_DOWN_INT_EN(1U)
75122 #define V_MAC_LINK_UP_INT_EN(x) ((x) << S_MAC_LINK_UP_INT_EN)
75123 #define F_MAC_LINK_UP_INT_EN    V_MAC_LINK_UP_INT_EN(1U)
75126 #define V_MAC_AN_DONE_INT_EN(x) ((x) << S_MAC_AN_DONE_INT_EN)
75127 #define F_MAC_AN_DONE_INT_EN    V_MAC_AN_DONE_INT_EN(1U)
75130 #define V_MAC_AN_PGRD_INT_EN(x) ((x) << S_MAC_AN_PGRD_INT_EN)
75131 #define F_MAC_AN_PGRD_INT_EN    V_MAC_AN_PGRD_INT_EN(1U)
75133 #define S_MAC_TXFIFO_ERR_INT_EN    1
75134 #define V_MAC_TXFIFO_ERR_INT_EN(x) ((x) << S_MAC_TXFIFO_ERR_INT_EN)
75135 #define F_MAC_TXFIFO_ERR_INT_EN    V_MAC_TXFIFO_ERR_INT_EN(1U)
75138 #define V_MAC_RXFIFO_ERR_INT_EN(x) ((x) << S_MAC_RXFIFO_ERR_INT_EN)
75139 #define F_MAC_RXFIFO_ERR_INT_EN    V_MAC_RXFIFO_ERR_INT_EN(1U)
75144 #define V_MAC2MPS_PERR_CAUSE(x) ((x) << S_MAC2MPS_PERR_CAUSE)
75145 #define F_MAC2MPS_PERR_CAUSE    V_MAC2MPS_PERR_CAUSE(1U)
75148 #define V_MAC_PPS_INT_CAUSE(x) ((x) << S_MAC_PPS_INT_CAUSE)
75149 #define F_MAC_PPS_INT_CAUSE    V_MAC_PPS_INT_CAUSE(1U)
75152 #define V_MAC_TX_TS_AVAIL_INT_CAUSE(x) ((x) << S_MAC_TX_TS_AVAIL_INT_CAUSE)
75153 #define F_MAC_TX_TS_AVAIL_INT_CAUSE    V_MAC_TX_TS_AVAIL_INT_CAUSE(1U)
75156 #define V_MAC_SINGLE_ALARM_INT_CAUSE(x) ((x) << S_MAC_SINGLE_ALARM_INT_CAUSE)
75157 #define F_MAC_SINGLE_ALARM_INT_CAUSE    V_MAC_SINGLE_ALARM_INT_CAUSE(1U)
75160 #define V_MAC_PERIODIC_ALARM_INT_CAUSE(x) ((x) << S_MAC_PERIODIC_ALARM_INT_CAUSE)
75161 #define F_MAC_PERIODIC_ALARM_INT_CAUSE    V_MAC_PERIODIC_ALARM_INT_CAUSE(1U)
75164 #define V_MAC_PATDETWAKE_INT_CAUSE(x) ((x) << S_MAC_PATDETWAKE_INT_CAUSE)
75165 #define F_MAC_PATDETWAKE_INT_CAUSE    V_MAC_PATDETWAKE_INT_CAUSE(1U)
75168 #define V_MAC_MAGIC_WAKE_INT_CAUSE(x) ((x) << S_MAC_MAGIC_WAKE_INT_CAUSE)
75169 #define F_MAC_MAGIC_WAKE_INT_CAUSE    V_MAC_MAGIC_WAKE_INT_CAUSE(1U)
75172 #define V_MAC_SIGDETCHG_INT_CAUSE(x) ((x) << S_MAC_SIGDETCHG_INT_CAUSE)
75173 #define F_MAC_SIGDETCHG_INT_CAUSE    V_MAC_SIGDETCHG_INT_CAUSE(1U)
75176 #define V_MAC_PCS_LINK_GOOD_CAUSE(x) ((x) << S_MAC_PCS_LINK_GOOD_CAUSE)
75177 #define F_MAC_PCS_LINK_GOOD_CAUSE    V_MAC_PCS_LINK_GOOD_CAUSE(1U)
75180 #define V_MAC_PCS_LINK_FAIL_CAUSE(x) ((x) << S_MAC_PCS_LINK_FAIL_CAUSE)
75181 #define F_MAC_PCS_LINK_FAIL_CAUSE    V_MAC_PCS_LINK_FAIL_CAUSE(1U)
75184 #define V_MAC_OVRFLOW_INT_CAUSE(x) ((x) << S_MAC_OVRFLOW_INT_CAUSE)
75185 #define F_MAC_OVRFLOW_INT_CAUSE    V_MAC_OVRFLOW_INT_CAUSE(1U)
75188 #define V_MAC_REM_FAULT_INT_CAUSE(x) ((x) << S_MAC_REM_FAULT_INT_CAUSE)
75189 #define F_MAC_REM_FAULT_INT_CAUSE    V_MAC_REM_FAULT_INT_CAUSE(1U)
75192 #define V_MAC_LOC_FAULT_INT_CAUSE(x) ((x) << S_MAC_LOC_FAULT_INT_CAUSE)
75193 #define F_MAC_LOC_FAULT_INT_CAUSE    V_MAC_LOC_FAULT_INT_CAUSE(1U)
75196 #define V_MAC_LINK_DOWN_INT_CAUSE(x) ((x) << S_MAC_LINK_DOWN_INT_CAUSE)
75197 #define F_MAC_LINK_DOWN_INT_CAUSE    V_MAC_LINK_DOWN_INT_CAUSE(1U)
75200 #define V_MAC_LINK_UP_INT_CAUSE(x) ((x) << S_MAC_LINK_UP_INT_CAUSE)
75201 #define F_MAC_LINK_UP_INT_CAUSE    V_MAC_LINK_UP_INT_CAUSE(1U)
75204 #define V_MAC_AN_DONE_INT_CAUSE(x) ((x) << S_MAC_AN_DONE_INT_CAUSE)
75205 #define F_MAC_AN_DONE_INT_CAUSE    V_MAC_AN_DONE_INT_CAUSE(1U)
75208 #define V_MAC_AN_PGRD_INT_CAUSE(x) ((x) << S_MAC_AN_PGRD_INT_CAUSE)
75209 #define F_MAC_AN_PGRD_INT_CAUSE    V_MAC_AN_PGRD_INT_CAUSE(1U)
75211 #define S_MAC_TXFIFO_ERR_INT_CAUSE    1
75212 #define V_MAC_TXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_TXFIFO_ERR_INT_CAUSE)
75213 #define F_MAC_TXFIFO_ERR_INT_CAUSE    V_MAC_TXFIFO_ERR_INT_CAUSE(1U)
75216 #define V_MAC_RXFIFO_ERR_INT_CAUSE(x) ((x) << S_MAC_RXFIFO_ERR_INT_CAUSE)
75217 #define F_MAC_RXFIFO_ERR_INT_CAUSE    V_MAC_RXFIFO_ERR_INT_CAUSE(1U)
75224 #define S_T7_MEMSEL_PERR    1
75226 #define V_T7_MEMSEL_PERR(x) ((x) << S_T7_MEMSEL_PERR)
75227 #define G_T7_MEMSEL_PERR(x) (((x) >> S_T7_MEMSEL_PERR) & M_T7_MEMSEL_PERR)
75234 #define V_TS_ID_MSB(x) ((x) << S_TS_ID_MSB)
75235 #define F_TS_ID_MSB    V_TS_ID_MSB(1U)
75251 #define S_WOL_ENABLE    1
75252 #define V_WOL_ENABLE(x) ((x) << S_WOL_ENABLE)
75253 #define F_WOL_ENABLE    V_WOL_ENABLE(1U)
75256 #define V_WOL_INDICATOR(x) ((x) << S_WOL_INDICATOR)
75257 #define F_WOL_INDICATOR    V_WOL_INDICATOR(1U)
75263 #define V_INTERRUPT(x) ((x) << S_INTERRUPT)
75264 #define G_INTERRUPT(x) (((x) >> S_INTERRUPT) & M_INTERRUPT)
75272 #define V_VER_10G100G(x) ((x) << S_VER_10G100G)
75273 #define G_VER_10G100G(x) (((x) >> S_VER_10G100G) & M_VER_10G100G)
75277 #define V_REV_10G100G(x) ((x) << S_REV_10G100G)
75278 #define G_REV_10G100G(x) (((x) >> S_REV_10G100G) & M_REV_10G100G)
75284 #define V_NO_PREAM(x) ((x) << S_NO_PREAM)
75285 #define F_NO_PREAM    V_NO_PREAM(1U)
75288 #define V_SHORT_PREAM(x) ((x) << S_SHORT_PREAM)
75289 #define F_SHORT_PREAM    V_SHORT_PREAM(1U)
75292 #define V_FLT_HDL_DIS(x) ((x) << S_FLT_HDL_DIS)
75293 #define F_FLT_HDL_DIS    V_FLT_HDL_DIS(1U)
75296 #define V_TX_FIFO_RESET(x) ((x) << S_TX_FIFO_RESET)
75297 #define F_TX_FIFO_RESET    V_TX_FIFO_RESET(1U)
75306 #define V_RX10G100G_EMPTY(x) ((x) << S_RX10G100G_EMPTY)
75307 #define G_RX10G100G_EMPTY(x) (((x) >> S_RX10G100G_EMPTY) & M_RX10G100G_EMPTY)
75311 #define V_RX10G100G_AVAIL(x) ((x) << S_RX10G100G_AVAIL)
75312 #define G_RX10G100G_AVAIL(x) (((x) >> S_RX10G100G_AVAIL) & M_RX10G100G_AVAIL)
75318 #define V_TX10G100G_EMPTY(x) ((x) << S_TX10G100G_EMPTY)
75319 #define G_TX10G100G_EMPTY(x) (((x) >> S_TX10G100G_EMPTY) & M_TX10G100G_EMPTY)
75323 #define V_TX10G100G_AVAIL(x) ((x) << S_TX10G100G_AVAIL)
75324 #define G_TX10G100G_AVAIL(x) (((x) >> S_TX10G100G_AVAIL) & M_TX10G100G_AVAIL)
75335 #define V_T7_TX_ISIDLE(x) ((x) << S_T7_TX_ISIDLE)
75336 #define F_T7_TX_ISIDLE    V_T7_TX_ISIDLE(1U)
75342 #define V_IPG_COMP_CNT(x) ((x) << S_IPG_COMP_CNT)
75343 #define G_IPG_COMP_CNT(x) (((x) >> S_IPG_COMP_CNT) & M_IPG_COMP_CNT)
75347 #define V_AVG_IPG_LEN(x) ((x) << S_AVG_IPG_LEN)
75348 #define G_AVG_IPG_LEN(x) (((x) >> S_AVG_IPG_LEN) & M_AVG_IPG_LEN)
75351 #define V_DSBL_DIC(x) ((x) << S_DSBL_DIC)
75352 #define F_DSBL_DIC    V_DSBL_DIC(1U)
75368 #define V_RX_CNT_MODE(x) ((x) << S_RX_CNT_MODE)
75369 #define F_RX_CNT_MODE    V_RX_CNT_MODE(1U)
75372 #define V_TS_UPD64_MODE(x) ((x) << S_TS_UPD64_MODE)
75373 #define F_TS_UPD64_MODE    V_TS_UPD64_MODE(1U)
75376 #define V_TS_BINARY_MODE(x) ((x) << S_TS_BINARY_MODE)
75377 #define F_TS_BINARY_MODE    V_TS_BINARY_MODE(1U)
75380 #define V_TS_DELAY_MODE(x) ((x) << S_TS_DELAY_MODE)
75381 #define F_TS_DELAY_MODE    V_TS_DELAY_MODE(1U)
75384 #define V_TS_DELTA_MODE(x) ((x) << S_TS_DELTA_MODE)
75385 #define F_TS_DELTA_MODE    V_TS_DELTA_MODE(1U)
75388 #define V_TX_MAC_RS_ERR(x) ((x) << S_TX_MAC_RS_ERR)
75389 #define F_TX_MAC_RS_ERR    V_TX_MAC_RS_ERR(1U)
75392 #define V_RX_PAUSE_BYPASS(x) ((x) << S_RX_PAUSE_BYPASS)
75393 #define F_RX_PAUSE_BYPASS    V_RX_PAUSE_BYPASS(1U)
75396 #define V_ONE_STEP_ENA(x) ((x) << S_ONE_STEP_ENA)
75397 #define F_ONE_STEP_ENA    V_ONE_STEP_ENA(1U)
75400 #define V_PAUSETIMERX8(x) ((x) << S_PAUSETIMERX8)
75401 #define F_PAUSETIMERX8    V_PAUSETIMERX8(1U)
75404 #define V_XGMII_ENA(x) ((x) << S_XGMII_ENA)
75405 #define F_XGMII_ENA    V_XGMII_ENA(1U)
75411 #define V_CR4_0_RX_LINK_STATUS(x) ((x) << S_CR4_0_RX_LINK_STATUS)
75412 #define F_CR4_0_RX_LINK_STATUS    V_CR4_0_RX_LINK_STATUS(1U)
75418 #define V_CR4_0_DEVICE_ID0(x) ((x) << S_CR4_0_DEVICE_ID0)
75419 #define G_CR4_0_DEVICE_ID0(x) (((x) >> S_CR4_0_DEVICE_ID0) & M_CR4_0_DEVICE_ID0)
75425 #define V_CR4_0_DEVICE_ID1(x) ((x) << S_CR4_0_DEVICE_ID1)
75426 #define G_CR4_0_DEVICE_ID1(x) (((x) >> S_CR4_0_DEVICE_ID1) & M_CR4_0_DEVICE_ID1)
75431 #define V_50G_CAPABLE(x) ((x) << S_50G_CAPABLE)
75432 #define F_50G_CAPABLE    V_50G_CAPABLE(1U)
75435 #define V_25G_CAPABLE(x) ((x) << S_25G_CAPABLE)
75436 #define F_25G_CAPABLE    V_25G_CAPABLE(1U)
75444 #define V_T7_PCS_TYPE_SELECTION(x) ((x) << S_T7_PCS_TYPE_SELECTION)
75445 #define G_T7_PCS_TYPE_SELECTION(x) (((x) >> S_T7_PCS_TYPE_SELECTION) & M_T7_PCS_TYPE_SELECTION)
75450 #define V_50GBASE_R_CAPABLE(x) ((x) << S_50GBASE_R_CAPABLE)
75451 #define F_50GBASE_R_CAPABLE    V_50GBASE_R_CAPABLE(1U)
75454 #define V_25GBASE_R_CAPABLE(x) ((x) << S_25GBASE_R_CAPABLE)
75455 #define F_25GBASE_R_CAPABLE    V_25GBASE_R_CAPABLE(1U)
75462 #define V_50GBASE_R_FW(x) ((x) << S_50GBASE_R_FW)
75463 #define F_50GBASE_R_FW    V_50GBASE_R_FW(1U)
75466 #define V_100GBASE_R_DS(x) ((x) << S_100GBASE_R_DS)
75467 #define F_100GBASE_R_DS    V_100GBASE_R_DS(1U)
75470 #define V_100GBASE_R_FW(x) ((x) << S_100GBASE_R_FW)
75471 #define F_100GBASE_R_FW    V_100GBASE_R_FW(1U)
75474 #define V_25GBASE_R_DS(x) ((x) << S_25GBASE_R_DS)
75475 #define F_25GBASE_R_DS    V_25GBASE_R_DS(1U)
75478 #define V_25GBASE_R_FW(x) ((x) << S_25GBASE_R_FW)
75479 #define F_25GBASE_R_FW    V_25GBASE_R_FW(1U)
75482 #define V_40GBASE_R_DS(x) ((x) << S_40GBASE_R_DS)
75483 #define F_40GBASE_R_DS    V_40GBASE_R_DS(1U)
75486 #define V_40GBASE_R_FW(x) ((x) << S_40GBASE_R_FW)
75487 #define F_40GBASE_R_FW    V_40GBASE_R_FW(1U)
75490 #define V_10GBASE_KE_EEE(x) ((x) << S_10GBASE_KE_EEE)
75491 #define F_10GBASE_KE_EEE    V_10GBASE_KE_EEE(1U)
75493 #define S_FAST_WAKE    1
75495 #define V_FAST_WAKE(x) ((x) << S_FAST_WAKE)
75496 #define G_FAST_WAKE(x) (((x) >> S_FAST_WAKE) & M_FAST_WAKE)
75499 #define V_DEEP_SLEEP(x) ((x) << S_DEEP_SLEEP)
75500 #define F_DEEP_SLEEP    V_DEEP_SLEEP(1U)
75506 #define V_WAKE_ERROR_COUNTER(x) ((x) << S_WAKE_ERROR_COUNTER)
75507 #define G_WAKE_ERROR_COUNTER(x) (((x) >> S_WAKE_ERROR_COUNTER) & M_WAKE_ERROR_COUNTER)
75512 #define V_CR4_0_BR_BLOCK_LOCK(x) ((x) << S_CR4_0_BR_BLOCK_LOCK)
75513 #define F_CR4_0_BR_BLOCK_LOCK    V_CR4_0_BR_BLOCK_LOCK(1U)
75520 #define V_SEED_A_0(x) ((x) << S_SEED_A_0)
75521 #define G_SEED_A_0(x) (((x) >> S_SEED_A_0) & M_SEED_A_0)
75527 #define V_SEED_A_1(x) ((x) << S_SEED_A_1)
75528 #define G_SEED_A_1(x) (((x) >> S_SEED_A_1) & M_SEED_A_1)
75534 #define V_SEED_A_2(x) ((x) << S_SEED_A_2)
75535 #define G_SEED_A_2(x) (((x) >> S_SEED_A_2) & M_SEED_A_2)
75541 #define V_SEED_A_3(x) ((x) << S_SEED_A_3)
75542 #define G_SEED_A_3(x) (((x) >> S_SEED_A_3) & M_SEED_A_3)
75548 #define V_SEED_B_0(x) ((x) << S_SEED_B_0)
75549 #define G_SEED_B_0(x) (((x) >> S_SEED_B_0) & M_SEED_B_0)
75555 #define V_SEED_B_1(x) ((x) << S_SEED_B_1)
75556 #define G_SEED_B_1(x) (((x) >> S_SEED_B_1) & M_SEED_B_1)
75562 #define V_SEED_B_2(x) ((x) << S_SEED_B_2)
75563 #define G_SEED_B_2(x) (((x) >> S_SEED_B_2) & M_SEED_B_2)
75569 #define V_SEED_B_3(x) ((x) << S_SEED_B_3)
75570 #define G_SEED_B_3(x) (((x) >> S_SEED_B_3) & M_SEED_B_3)
75575 #define V_TEST_PATTERN_40G(x) ((x) << S_TEST_PATTERN_40G)
75576 #define F_TEST_PATTERN_40G    V_TEST_PATTERN_40G(1U)
75583 #define V_BASE_R_BER_HIGH_ORDER_CNT(x) ((x) << S_BASE_R_BER_HIGH_ORDER_CNT)
75584 #define G_BASE_R_BER_HIGH_ORDER_CNT(x) (((x) >> S_BASE_R_BER_HIGH_ORDER_CNT) & M_BASE_R_BER_HIGH_ORDER_CNT)
75637 #define V_VL_INTCL(x) ((x) << S_VL_INTCL)
75638 #define G_VL_INTCL(x) (((x) >> S_VL_INTCL) & M_VL_INTCL)
75644 #define V_LANE6_LANE7(x) ((x) << S_LANE6_LANE7)
75645 #define G_LANE6_LANE7(x) (((x) >> S_LANE6_LANE7) & M_LANE6_LANE7)
75649 #define V_LANE4_LANE5(x) ((x) << S_LANE4_LANE5)
75650 #define G_LANE4_LANE5(x) (((x) >> S_LANE4_LANE5) & M_LANE4_LANE5)
75654 #define V_LANE2_LANE3(x) ((x) << S_LANE2_LANE3)
75655 #define G_LANE2_LANE3(x) (((x) >> S_LANE2_LANE3) & M_LANE2_LANE3)
75659 #define V_LANE0_LANE1(x) ((x) << S_LANE0_LANE1)
75660 #define G_LANE0_LANE1(x) (((x) >> S_LANE0_LANE1) & M_LANE0_LANE1)
75666 #define V_M1(x) ((x) << S_M1)
75667 #define G_M1(x) (((x) >> S_M1) & M_M1)
75671 #define V_M0(x) ((x) << S_M0)
75672 #define G_M0(x) (((x) >> S_M0) & M_M0)
75678 #define V_M2(x) ((x) << S_M2)
75679 #define G_M2(x) (((x) >> S_M2) & M_M2)
75690 #define V_ST_DISABLE_MLD(x) ((x) << S_ST_DISABLE_MLD)
75691 #define F_ST_DISABLE_MLD    V_ST_DISABLE_MLD(1U)
75694 #define V_ST_EN_CLAUSE49(x) ((x) << S_ST_EN_CLAUSE49)
75695 #define F_ST_EN_CLAUSE49    V_ST_EN_CLAUSE49(1U)
75698 #define V_HI_BER25(x) ((x) << S_HI_BER25)
75699 #define F_HI_BER25    V_HI_BER25(1U)
75701 #define S_DISABLE_MLD    1
75702 #define V_DISABLE_MLD(x) ((x) << S_DISABLE_MLD)
75703 #define F_DISABLE_MLD    V_DISABLE_MLD(1U)
75706 #define V_ENA_CLAUSE49(x) ((x) << S_ENA_CLAUSE49)
75707 #define F_ENA_CLAUSE49    V_ENA_CLAUSE49(1U)
75745 #define V_CR4_RX_LINK_STATUS_1(x) ((x) << S_CR4_RX_LINK_STATUS_1)
75746 #define F_CR4_RX_LINK_STATUS_1    V_CR4_RX_LINK_STATUS_1(1U)
75752 #define V_CR4_1_DEVICE_ID0(x) ((x) << S_CR4_1_DEVICE_ID0)
75753 #define G_CR4_1_DEVICE_ID0(x) (((x) >> S_CR4_1_DEVICE_ID0) & M_CR4_1_DEVICE_ID0)
75759 #define V_CR4_1_DEVICE_ID1(x) ((x) << S_CR4_1_DEVICE_ID1)
75760 #define G_CR4_1_DEVICE_ID1(x) (((x) >> S_CR4_1_DEVICE_ID1) & M_CR4_1_DEVICE_ID1)
75774 #define V_CR4_1_BR_BLOCK_LOCK(x) ((x) << S_CR4_1_BR_BLOCK_LOCK)
75775 #define F_CR4_1_BR_BLOCK_LOCK    V_CR4_1_BR_BLOCK_LOCK(1U)
75851 #define V_T7_RX_POLARITY_INV(x) ((x) << S_T7_RX_POLARITY_INV)
75852 #define G_T7_RX_POLARITY_INV(x) (((x) >> S_T7_RX_POLARITY_INV) & M_T7_RX_POLARITY_INV)
75856 #define V_T7_TX_POLARITY_INV(x) ((x) << S_T7_TX_POLARITY_INV)
75857 #define G_T7_TX_POLARITY_INV(x) (((x) >> S_T7_TX_POLARITY_INV) & M_T7_TX_POLARITY_INV)
75861 #define V_T7_DEBUG_PORT_SEL(x) ((x) << S_T7_DEBUG_PORT_SEL)
75862 #define G_T7_DEBUG_PORT_SEL(x) (((x) >> S_T7_DEBUG_PORT_SEL) & M_T7_DEBUG_PORT_SEL)
75866 #define V_MAC_SEPTY_CTL(x) ((x) << S_MAC_SEPTY_CTL)
75867 #define G_MAC_SEPTY_CTL(x) (((x) >> S_MAC_SEPTY_CTL) & M_MAC_SEPTY_CTL)
75870 #define V_T7_DEBUG_TX_RX_SEL(x) ((x) << S_T7_DEBUG_TX_RX_SEL)
75871 #define F_T7_DEBUG_TX_RX_SEL    V_T7_DEBUG_TX_RX_SEL(1U)
75875 #define V_MAC_RDY_CTL(x) ((x) << S_MAC_RDY_CTL)
75876 #define G_MAC_RDY_CTL(x) (((x) >> S_MAC_RDY_CTL) & M_MAC_RDY_CTL)
75881 #define V_RESET_F91_REF_CLK_I(x) ((x) << S_RESET_F91_REF_CLK_I)
75882 #define F_RESET_F91_REF_CLK_I    V_RESET_F91_REF_CLK_I(1U)
75885 #define V_RESET_PCS000_REF_CLK_I(x) ((x) << S_RESET_PCS000_REF_CLK_I)
75886 #define F_RESET_PCS000_REF_CLK_I    V_RESET_PCS000_REF_CLK_I(1U)
75889 #define V_RESET_REF_CLK_I(x) ((x) << S_RESET_REF_CLK_I)
75890 #define F_RESET_REF_CLK_I    V_RESET_REF_CLK_I(1U)
75893 #define V_RESET_SD_RX_CLK_I_0(x) ((x) << S_RESET_SD_RX_CLK_I_0)
75894 #define F_RESET_SD_RX_CLK_I_0    V_RESET_SD_RX_CLK_I_0(1U)
75897 #define V_RESET_SD_RX_CLK_I_1(x) ((x) << S_RESET_SD_RX_CLK_I_1)
75898 #define F_RESET_SD_RX_CLK_I_1    V_RESET_SD_RX_CLK_I_1(1U)
75901 #define V_RESET_SD_RX_CLK_I_2(x) ((x) << S_RESET_SD_RX_CLK_I_2)
75902 #define F_RESET_SD_RX_CLK_I_2    V_RESET_SD_RX_CLK_I_2(1U)
75905 #define V_RESET_SD_RX_CLK_I_3(x) ((x) << S_RESET_SD_RX_CLK_I_3)
75906 #define F_RESET_SD_RX_CLK_I_3    V_RESET_SD_RX_CLK_I_3(1U)
75909 #define V_RESET_SD_RX_CLK_I_4(x) ((x) << S_RESET_SD_RX_CLK_I_4)
75910 #define F_RESET_SD_RX_CLK_I_4    V_RESET_SD_RX_CLK_I_4(1U)
75913 #define V_RESET_SD_RX_CLK_I_5(x) ((x) << S_RESET_SD_RX_CLK_I_5)
75914 #define F_RESET_SD_RX_CLK_I_5    V_RESET_SD_RX_CLK_I_5(1U)
75917 #define V_RESET_SD_RX_CLK_I_6(x) ((x) << S_RESET_SD_RX_CLK_I_6)
75918 #define F_RESET_SD_RX_CLK_I_6    V_RESET_SD_RX_CLK_I_6(1U)
75921 #define V_RESET_SD_RX_CLK_I_7(x) ((x) << S_RESET_SD_RX_CLK_I_7)
75922 #define F_RESET_SD_RX_CLK_I_7    V_RESET_SD_RX_CLK_I_7(1U)
75925 #define V_RESET_SD_TX_CLK_I_0(x) ((x) << S_RESET_SD_TX_CLK_I_0)
75926 #define F_RESET_SD_TX_CLK_I_0    V_RESET_SD_TX_CLK_I_0(1U)
75929 #define V_RESET_SD_TX_CLK_I_1(x) ((x) << S_RESET_SD_TX_CLK_I_1)
75930 #define F_RESET_SD_TX_CLK_I_1    V_RESET_SD_TX_CLK_I_1(1U)
75933 #define V_RESET_SD_TX_CLK_I_2(x) ((x) << S_RESET_SD_TX_CLK_I_2)
75934 #define F_RESET_SD_TX_CLK_I_2    V_RESET_SD_TX_CLK_I_2(1U)
75937 #define V_RESET_SD_TX_CLK_I_3(x) ((x) << S_RESET_SD_TX_CLK_I_3)
75938 #define F_RESET_SD_TX_CLK_I_3    V_RESET_SD_TX_CLK_I_3(1U)
75941 #define V_RESET_SD_TX_CLK_I_4(x) ((x) << S_RESET_SD_TX_CLK_I_4)
75942 #define F_RESET_SD_TX_CLK_I_4    V_RESET_SD_TX_CLK_I_4(1U)
75945 #define V_RESET_SD_TX_CLK_I_5(x) ((x) << S_RESET_SD_TX_CLK_I_5)
75946 #define F_RESET_SD_TX_CLK_I_5    V_RESET_SD_TX_CLK_I_5(1U)
75949 #define V_RESET_SD_TX_CLK_I_6(x) ((x) << S_RESET_SD_TX_CLK_I_6)
75950 #define F_RESET_SD_TX_CLK_I_6    V_RESET_SD_TX_CLK_I_6(1U)
75953 #define V_RESET_SD_TX_CLK_I_7(x) ((x) << S_RESET_SD_TX_CLK_I_7)
75954 #define F_RESET_SD_TX_CLK_I_7    V_RESET_SD_TX_CLK_I_7(1U)
75957 #define V_RESET_XPCS_REF_CLK_I_0(x) ((x) << S_RESET_XPCS_REF_CLK_I_0)
75958 #define F_RESET_XPCS_REF_CLK_I_0    V_RESET_XPCS_REF_CLK_I_0(1U)
75961 #define V_RESET_XPCS_REF_CLK_I_1(x) ((x) << S_RESET_XPCS_REF_CLK_I_1)
75962 #define F_RESET_XPCS_REF_CLK_I_1    V_RESET_XPCS_REF_CLK_I_1(1U)
75965 #define V_RESET_FF_RX_CLK_0_I(x) ((x) << S_RESET_FF_RX_CLK_0_I)
75966 #define F_RESET_FF_RX_CLK_0_I    V_RESET_FF_RX_CLK_0_I(1U)
75969 #define V_RESET_FF_TX_CLK_0_I(x) ((x) << S_RESET_FF_TX_CLK_0_I)
75970 #define F_RESET_FF_TX_CLK_0_I    V_RESET_FF_TX_CLK_0_I(1U)
75973 #define V_RESET_RXCLK_0_I(x) ((x) << S_RESET_RXCLK_0_I)
75974 #define F_RESET_RXCLK_0_I    V_RESET_RXCLK_0_I(1U)
75977 #define V_RESET_TXCLK_0_I(x) ((x) << S_RESET_TXCLK_0_I)
75978 #define F_RESET_TXCLK_0_I    V_RESET_TXCLK_0_I(1U)
75981 #define V_RESET_FF_RX_CLK_1_I(x) ((x) << S_RESET_FF_RX_CLK_1_I)
75982 #define F_RESET_FF_RX_CLK_1_I    V_RESET_FF_RX_CLK_1_I(1U)
75985 #define V_RESET_FF_TX_CLK_1_I(x) ((x) << S_RESET_FF_TX_CLK_1_I)
75986 #define F_RESET_FF_TX_CLK_1_I    V_RESET_FF_TX_CLK_1_I(1U)
75989 #define V_RESET_RXCLK_1_I(x) ((x) << S_RESET_RXCLK_1_I)
75990 #define F_RESET_RXCLK_1_I    V_RESET_RXCLK_1_I(1U)
75993 #define V_RESET_TXCLK_1_I(x) ((x) << S_RESET_TXCLK_1_I)
75994 #define F_RESET_TXCLK_1_I    V_RESET_TXCLK_1_I(1U)
75997 #define V_XGMII_CLK_RESET_0(x) ((x) << S_XGMII_CLK_RESET_0)
75998 #define F_XGMII_CLK_RESET_0    V_XGMII_CLK_RESET_0(1U)
76003 #define V_RESET_FF_RX_CLK_2_I(x) ((x) << S_RESET_FF_RX_CLK_2_I)
76004 #define F_RESET_FF_RX_CLK_2_I    V_RESET_FF_RX_CLK_2_I(1U)
76007 #define V_RESET_FF_TX_CLK_2_I(x) ((x) << S_RESET_FF_TX_CLK_2_I)
76008 #define F_RESET_FF_TX_CLK_2_I    V_RESET_FF_TX_CLK_2_I(1U)
76011 #define V_RESET_RXCLK_2_I(x) ((x) << S_RESET_RXCLK_2_I)
76012 #define F_RESET_RXCLK_2_I    V_RESET_RXCLK_2_I(1U)
76015 #define V_RESET_TXCLK_2_I(x) ((x) << S_RESET_TXCLK_2_I)
76016 #define F_RESET_TXCLK_2_I    V_RESET_TXCLK_2_I(1U)
76019 #define V_RESET_FF_RX_CLK_3_I(x) ((x) << S_RESET_FF_RX_CLK_3_I)
76020 #define F_RESET_FF_RX_CLK_3_I    V_RESET_FF_RX_CLK_3_I(1U)
76023 #define V_RESET_FF_TX_CLK_3_I(x) ((x) << S_RESET_FF_TX_CLK_3_I)
76024 #define F_RESET_FF_TX_CLK_3_I    V_RESET_FF_TX_CLK_3_I(1U)
76027 #define V_RESET_RXCLK_3_I(x) ((x) << S_RESET_RXCLK_3_I)
76028 #define F_RESET_RXCLK_3_I    V_RESET_RXCLK_3_I(1U)
76031 #define V_RESET_TXCLK_3_I(x) ((x) << S_RESET_TXCLK_3_I)
76032 #define F_RESET_TXCLK_3_I    V_RESET_TXCLK_3_I(1U)
76035 #define V_RESET_FF_RX_CLK_4_I(x) ((x) << S_RESET_FF_RX_CLK_4_I)
76036 #define F_RESET_FF_RX_CLK_4_I    V_RESET_FF_RX_CLK_4_I(1U)
76039 #define V_RESET_FF_TX_CLK_4_I(x) ((x) << S_RESET_FF_TX_CLK_4_I)
76040 #define F_RESET_FF_TX_CLK_4_I    V_RESET_FF_TX_CLK_4_I(1U)
76043 #define V_RESET_RXCLK_4_I(x) ((x) << S_RESET_RXCLK_4_I)
76044 #define F_RESET_RXCLK_4_I    V_RESET_RXCLK_4_I(1U)
76047 #define V_RESET_TXCLK_4_I(x) ((x) << S_RESET_TXCLK_4_I)
76048 #define F_RESET_TXCLK_4_I    V_RESET_TXCLK_4_I(1U)
76051 #define V_RESET_FF_RX_CLK_5_I(x) ((x) << S_RESET_FF_RX_CLK_5_I)
76052 #define F_RESET_FF_RX_CLK_5_I    V_RESET_FF_RX_CLK_5_I(1U)
76055 #define V_RESET_FF_TX_CLK_5_I(x) ((x) << S_RESET_FF_TX_CLK_5_I)
76056 #define F_RESET_FF_TX_CLK_5_I    V_RESET_FF_TX_CLK_5_I(1U)
76059 #define V_RESET_RXCLK_5_I(x) ((x) << S_RESET_RXCLK_5_I)
76060 #define F_RESET_RXCLK_5_I    V_RESET_RXCLK_5_I(1U)
76063 #define V_RESET_TXCLK_5_I(x) ((x) << S_RESET_TXCLK_5_I)
76064 #define F_RESET_TXCLK_5_I    V_RESET_TXCLK_5_I(1U)
76067 #define V_RESET_SD_RX_CLK_AN_0_I(x) ((x) << S_RESET_SD_RX_CLK_AN_0_I)
76068 #define F_RESET_SD_RX_CLK_AN_0_I    V_RESET_SD_RX_CLK_AN_0_I(1U)
76071 #define V_RESET_SD_TX_CLK_AN_0_I(x) ((x) << S_RESET_SD_TX_CLK_AN_0_I)
76072 #define F_RESET_SD_TX_CLK_AN_0_I    V_RESET_SD_TX_CLK_AN_0_I(1U)
76075 #define V_RESET_SD_RX_CLK_AN_1_I(x) ((x) << S_RESET_SD_RX_CLK_AN_1_I)
76076 #define F_RESET_SD_RX_CLK_AN_1_I    V_RESET_SD_RX_CLK_AN_1_I(1U)
76079 #define V_RESET_SD_TX_CLK_AN_1_I(x) ((x) << S_RESET_SD_TX_CLK_AN_1_I)
76080 #define F_RESET_SD_TX_CLK_AN_1_I    V_RESET_SD_TX_CLK_AN_1_I(1U)
76083 #define V_RESET_SD_RX_CLK_AN_2_I(x) ((x) << S_RESET_SD_RX_CLK_AN_2_I)
76084 #define F_RESET_SD_RX_CLK_AN_2_I    V_RESET_SD_RX_CLK_AN_2_I(1U)
76087 #define V_RESET_SD_TX_CLK_AN_2_I(x) ((x) << S_RESET_SD_TX_CLK_AN_2_I)
76088 #define F_RESET_SD_TX_CLK_AN_2_I    V_RESET_SD_TX_CLK_AN_2_I(1U)
76091 #define V_RESET_SD_RX_CLK_AN_3_I(x) ((x) << S_RESET_SD_RX_CLK_AN_3_I)
76092 #define F_RESET_SD_RX_CLK_AN_3_I    V_RESET_SD_RX_CLK_AN_3_I(1U)
76095 #define V_RESET_SD_TX_CLK_AN_3_I(x) ((x) << S_RESET_SD_TX_CLK_AN_3_I)
76096 #define F_RESET_SD_TX_CLK_AN_3_I    V_RESET_SD_TX_CLK_AN_3_I(1U)
76099 #define V_RESET_SD_RX_CLK_AN_4_I(x) ((x) << S_RESET_SD_RX_CLK_AN_4_I)
76100 #define F_RESET_SD_RX_CLK_AN_4_I    V_RESET_SD_RX_CLK_AN_4_I(1U)
76103 #define V_RESET_SD_TX_CLK_AN_4_I(x) ((x) << S_RESET_SD_TX_CLK_AN_4_I)
76104 #define F_RESET_SD_TX_CLK_AN_4_I    V_RESET_SD_TX_CLK_AN_4_I(1U)
76107 #define V_RESET_SD_RX_CLK_AN_5_I(x) ((x) << S_RESET_SD_RX_CLK_AN_5_I)
76108 #define F_RESET_SD_RX_CLK_AN_5_I    V_RESET_SD_RX_CLK_AN_5_I(1U)
76111 #define V_RESET_SD_TX_CLK_AN_5_I(x) ((x) << S_RESET_SD_TX_CLK_AN_5_I)
76112 #define F_RESET_SD_TX_CLK_AN_5_I    V_RESET_SD_TX_CLK_AN_5_I(1U)
76115 #define V_RESET_SD_RX_CLK_AN_6_I(x) ((x) << S_RESET_SD_RX_CLK_AN_6_I)
76116 #define F_RESET_SD_RX_CLK_AN_6_I    V_RESET_SD_RX_CLK_AN_6_I(1U)
76119 #define V_RESET_SD_TX_CLK_AN_6_I(x) ((x) << S_RESET_SD_TX_CLK_AN_6_I)
76120 #define F_RESET_SD_TX_CLK_AN_6_I    V_RESET_SD_TX_CLK_AN_6_I(1U)
76122 #define S_RESET_SD_RX_CLK_AN_7_I    1
76123 #define V_RESET_SD_RX_CLK_AN_7_I(x) ((x) << S_RESET_SD_RX_CLK_AN_7_I)
76124 #define F_RESET_SD_RX_CLK_AN_7_I    V_RESET_SD_RX_CLK_AN_7_I(1U)
76127 #define V_RESET_SD_TX_CLK_AN_7_I(x) ((x) << S_RESET_SD_TX_CLK_AN_7_I)
76128 #define F_RESET_SD_TX_CLK_AN_7_I    V_RESET_SD_TX_CLK_AN_7_I(1U)
76133 #define V_RESET_SGMII_TXCLK_I_3(x) ((x) << S_RESET_SGMII_TXCLK_I_3)
76134 #define F_RESET_SGMII_TXCLK_I_3    V_RESET_SGMII_TXCLK_I_3(1U)
76137 #define V_RESET_SGMII_RXCLK_I_3(x) ((x) << S_RESET_SGMII_RXCLK_I_3)
76138 #define F_RESET_SGMII_RXCLK_I_3    V_RESET_SGMII_RXCLK_I_3(1U)
76141 #define V_RESET_SGMII_TXCLK_I_2(x) ((x) << S_RESET_SGMII_TXCLK_I_2)
76142 #define F_RESET_SGMII_TXCLK_I_2    V_RESET_SGMII_TXCLK_I_2(1U)
76145 #define V_RESET_SGMII_RXCLK_I_2(x) ((x) << S_RESET_SGMII_RXCLK_I_2)
76146 #define F_RESET_SGMII_RXCLK_I_2    V_RESET_SGMII_RXCLK_I_2(1U)
76149 #define V_RESET_SGMII_TXCLK_I_1(x) ((x) << S_RESET_SGMII_TXCLK_I_1)
76150 #define F_RESET_SGMII_TXCLK_I_1    V_RESET_SGMII_TXCLK_I_1(1U)
76153 #define V_RESET_SGMII_RXCLK_I_1(x) ((x) << S_RESET_SGMII_RXCLK_I_1)
76154 #define F_RESET_SGMII_RXCLK_I_1    V_RESET_SGMII_RXCLK_I_1(1U)
76157 #define V_RESET_SGMII_TXCLK_I_0(x) ((x) << S_RESET_SGMII_TXCLK_I_0)
76158 #define F_RESET_SGMII_TXCLK_I_0    V_RESET_SGMII_TXCLK_I_0(1U)
76161 #define V_RESET_SGMII_RXCLK_I_0(x) ((x) << S_RESET_SGMII_RXCLK_I_0)
76162 #define F_RESET_SGMII_RXCLK_I_0    V_RESET_SGMII_RXCLK_I_0(1U)
76165 #define V_MTIPSD7TXRST(x) ((x) << S_MTIPSD7TXRST)
76166 #define F_MTIPSD7TXRST    V_MTIPSD7TXRST(1U)
76169 #define V_MTIPSD6TXRST(x) ((x) << S_MTIPSD6TXRST)
76170 #define F_MTIPSD6TXRST    V_MTIPSD6TXRST(1U)
76173 #define V_MTIPSD5TXRST(x) ((x) << S_MTIPSD5TXRST)
76174 #define F_MTIPSD5TXRST    V_MTIPSD5TXRST(1U)
76177 #define V_MTIPSD4TXRST(x) ((x) << S_MTIPSD4TXRST)
76178 #define F_MTIPSD4TXRST    V_MTIPSD4TXRST(1U)
76181 #define V_T7_MTIPSD3TXRST(x) ((x) << S_T7_MTIPSD3TXRST)
76182 #define F_T7_MTIPSD3TXRST    V_T7_MTIPSD3TXRST(1U)
76185 #define V_T7_MTIPSD2TXRST(x) ((x) << S_T7_MTIPSD2TXRST)
76186 #define F_T7_MTIPSD2TXRST    V_T7_MTIPSD2TXRST(1U)
76189 #define V_T7_MTIPSD1TXRST(x) ((x) << S_T7_MTIPSD1TXRST)
76190 #define F_T7_MTIPSD1TXRST    V_T7_MTIPSD1TXRST(1U)
76193 #define V_T7_MTIPSD0TXRST(x) ((x) << S_T7_MTIPSD0TXRST)
76194 #define F_T7_MTIPSD0TXRST    V_T7_MTIPSD0TXRST(1U)
76197 #define V_MTIPSD7RXRST(x) ((x) << S_MTIPSD7RXRST)
76198 #define F_MTIPSD7RXRST    V_MTIPSD7RXRST(1U)
76201 #define V_MTIPSD6RXRST(x) ((x) << S_MTIPSD6RXRST)
76202 #define F_MTIPSD6RXRST    V_MTIPSD6RXRST(1U)
76205 #define V_MTIPSD5RXRST(x) ((x) << S_MTIPSD5RXRST)
76206 #define F_MTIPSD5RXRST    V_MTIPSD5RXRST(1U)
76209 #define V_MTIPSD4RXRST(x) ((x) << S_MTIPSD4RXRST)
76210 #define F_MTIPSD4RXRST    V_MTIPSD4RXRST(1U)
76213 #define V_T7_MTIPSD3RXRST(x) ((x) << S_T7_MTIPSD3RXRST)
76214 #define F_T7_MTIPSD3RXRST    V_T7_MTIPSD3RXRST(1U)
76217 #define V_T7_MTIPSD2RXRST(x) ((x) << S_T7_MTIPSD2RXRST)
76218 #define F_T7_MTIPSD2RXRST    V_T7_MTIPSD2RXRST(1U)
76221 #define V_T7_MTIPSD1RXRST(x) ((x) << S_T7_MTIPSD1RXRST)
76222 #define F_T7_MTIPSD1RXRST    V_T7_MTIPSD1RXRST(1U)
76225 #define V_T7_MTIPSD0RXRST(x) ((x) << S_T7_MTIPSD0RXRST)
76226 #define F_T7_MTIPSD0RXRST    V_T7_MTIPSD0RXRST(1U)
76229 #define V_RESET_REG_CLK_AN_0_I(x) ((x) << S_RESET_REG_CLK_AN_0_I)
76230 #define F_RESET_REG_CLK_AN_0_I    V_RESET_REG_CLK_AN_0_I(1U)
76233 #define V_RESET_REG_CLK_AN_1_I(x) ((x) << S_RESET_REG_CLK_AN_1_I)
76234 #define F_RESET_REG_CLK_AN_1_I    V_RESET_REG_CLK_AN_1_I(1U)
76237 #define V_RESET_REG_CLK_AN_2_I(x) ((x) << S_RESET_REG_CLK_AN_2_I)
76238 #define F_RESET_REG_CLK_AN_2_I    V_RESET_REG_CLK_AN_2_I(1U)
76241 #define V_RESET_REG_CLK_AN_3_I(x) ((x) << S_RESET_REG_CLK_AN_3_I)
76242 #define F_RESET_REG_CLK_AN_3_I    V_RESET_REG_CLK_AN_3_I(1U)
76245 #define V_RESET_REG_CLK_AN_4_I(x) ((x) << S_RESET_REG_CLK_AN_4_I)
76246 #define F_RESET_REG_CLK_AN_4_I    V_RESET_REG_CLK_AN_4_I(1U)
76249 #define V_RESET_REG_CLK_AN_5_I(x) ((x) << S_RESET_REG_CLK_AN_5_I)
76250 #define F_RESET_REG_CLK_AN_5_I    V_RESET_REG_CLK_AN_5_I(1U)
76252 #define S_RESET_REG_CLK_AN_6_I    1
76253 #define V_RESET_REG_CLK_AN_6_I(x) ((x) << S_RESET_REG_CLK_AN_6_I)
76254 #define F_RESET_REG_CLK_AN_6_I    V_RESET_REG_CLK_AN_6_I(1U)
76257 #define V_RESET_REG_CLK_AN_7_I(x) ((x) << S_RESET_REG_CLK_AN_7_I)
76258 #define F_RESET_REG_CLK_AN_7_I    V_RESET_REG_CLK_AN_7_I(1U)
76263 #define V_F91_REF_CLK_I_G(x) ((x) << S_F91_REF_CLK_I_G)
76264 #define F_F91_REF_CLK_I_G    V_F91_REF_CLK_I_G(1U)
76267 #define V_PCS000_REF_CLK_I_G(x) ((x) << S_PCS000_REF_CLK_I_G)
76268 #define F_PCS000_REF_CLK_I_G    V_PCS000_REF_CLK_I_G(1U)
76271 #define V_REF_CLK_I_G(x) ((x) << S_REF_CLK_I_G)
76272 #define F_REF_CLK_I_G    V_REF_CLK_I_G(1U)
76275 #define V_SD_RX_CLK_I_0_G(x) ((x) << S_SD_RX_CLK_I_0_G)
76276 #define F_SD_RX_CLK_I_0_G    V_SD_RX_CLK_I_0_G(1U)
76279 #define V_SD_RX_CLK_I_1_G(x) ((x) << S_SD_RX_CLK_I_1_G)
76280 #define F_SD_RX_CLK_I_1_G    V_SD_RX_CLK_I_1_G(1U)
76283 #define V_SD_RX_CLK_I_2_G(x) ((x) << S_SD_RX_CLK_I_2_G)
76284 #define F_SD_RX_CLK_I_2_G    V_SD_RX_CLK_I_2_G(1U)
76287 #define V_SD_RX_CLK_I_3_G(x) ((x) << S_SD_RX_CLK_I_3_G)
76288 #define F_SD_RX_CLK_I_3_G    V_SD_RX_CLK_I_3_G(1U)
76291 #define V_SD_RX_CLK_I_4_G(x) ((x) << S_SD_RX_CLK_I_4_G)
76292 #define F_SD_RX_CLK_I_4_G    V_SD_RX_CLK_I_4_G(1U)
76295 #define V_SD_RX_CLK_I_5_G(x) ((x) << S_SD_RX_CLK_I_5_G)
76296 #define F_SD_RX_CLK_I_5_G    V_SD_RX_CLK_I_5_G(1U)
76299 #define V_SD_RX_CLK_I_6_G(x) ((x) << S_SD_RX_CLK_I_6_G)
76300 #define F_SD_RX_CLK_I_6_G    V_SD_RX_CLK_I_6_G(1U)
76303 #define V_SD_RX_CLK_I_7_G(x) ((x) << S_SD_RX_CLK_I_7_G)
76304 #define F_SD_RX_CLK_I_7_G    V_SD_RX_CLK_I_7_G(1U)
76307 #define V_SD_TX_CLK_I_0_G(x) ((x) << S_SD_TX_CLK_I_0_G)
76308 #define F_SD_TX_CLK_I_0_G    V_SD_TX_CLK_I_0_G(1U)
76311 #define V_SD_TX_CLK_I_1_G(x) ((x) << S_SD_TX_CLK_I_1_G)
76312 #define F_SD_TX_CLK_I_1_G    V_SD_TX_CLK_I_1_G(1U)
76315 #define V_SD_TX_CLK_I_2_G(x) ((x) << S_SD_TX_CLK_I_2_G)
76316 #define F_SD_TX_CLK_I_2_G    V_SD_TX_CLK_I_2_G(1U)
76319 #define V_SD_TX_CLK_I_3_G(x) ((x) << S_SD_TX_CLK_I_3_G)
76320 #define F_SD_TX_CLK_I_3_G    V_SD_TX_CLK_I_3_G(1U)
76323 #define V_SD_TX_CLK_I_4_G(x) ((x) << S_SD_TX_CLK_I_4_G)
76324 #define F_SD_TX_CLK_I_4_G    V_SD_TX_CLK_I_4_G(1U)
76327 #define V_SD_TX_CLK_I_5_G(x) ((x) << S_SD_TX_CLK_I_5_G)
76328 #define F_SD_TX_CLK_I_5_G    V_SD_TX_CLK_I_5_G(1U)
76331 #define V_SD_TX_CLK_I_6_G(x) ((x) << S_SD_TX_CLK_I_6_G)
76332 #define F_SD_TX_CLK_I_6_G    V_SD_TX_CLK_I_6_G(1U)
76335 #define V_SD_TX_CLK_I_7_G(x) ((x) << S_SD_TX_CLK_I_7_G)
76336 #define F_SD_TX_CLK_I_7_G    V_SD_TX_CLK_I_7_G(1U)
76339 #define V_XPCS_REF_CLK_I_0_G(x) ((x) << S_XPCS_REF_CLK_I_0_G)
76340 #define F_XPCS_REF_CLK_I_0_G    V_XPCS_REF_CLK_I_0_G(1U)
76343 #define V_XPCS_REF_CLK_I_1_G(x) ((x) << S_XPCS_REF_CLK_I_1_G)
76344 #define F_XPCS_REF_CLK_I_1_G    V_XPCS_REF_CLK_I_1_G(1U)
76347 #define V_REG_CLK_I_G(x) ((x) << S_REG_CLK_I_G)
76348 #define F_REG_CLK_I_G    V_REG_CLK_I_G(1U)
76351 #define V_FF_RX_CLK_0_I_G(x) ((x) << S_FF_RX_CLK_0_I_G)
76352 #define F_FF_RX_CLK_0_I_G    V_FF_RX_CLK_0_I_G(1U)
76355 #define V_FF_TX_CLK_0_I_G(x) ((x) << S_FF_TX_CLK_0_I_G)
76356 #define F_FF_TX_CLK_0_I_G    V_FF_TX_CLK_0_I_G(1U)
76359 #define V_RXCLK_0_I_G(x) ((x) << S_RXCLK_0_I_G)
76360 #define F_RXCLK_0_I_G    V_RXCLK_0_I_G(1U)
76363 #define V_TXCLK_0_I_G(x) ((x) << S_TXCLK_0_I_G)
76364 #define F_TXCLK_0_I_G    V_TXCLK_0_I_G(1U)
76367 #define V_FF_RX_CLK_1_I_G(x) ((x) << S_FF_RX_CLK_1_I_G)
76368 #define F_FF_RX_CLK_1_I_G    V_FF_RX_CLK_1_I_G(1U)
76371 #define V_FF_TX_CLK_1_I_G(x) ((x) << S_FF_TX_CLK_1_I_G)
76372 #define F_FF_TX_CLK_1_I_G    V_FF_TX_CLK_1_I_G(1U)
76375 #define V_RXCLK_1_I_G(x) ((x) << S_RXCLK_1_I_G)
76376 #define F_RXCLK_1_I_G    V_RXCLK_1_I_G(1U)
76379 #define V_TXCLK_1_I_G(x) ((x) << S_TXCLK_1_I_G)
76380 #define F_TXCLK_1_I_G    V_TXCLK_1_I_G(1U)
76385 #define V_FF_RX_CLK_2_I_G(x) ((x) << S_FF_RX_CLK_2_I_G)
76386 #define F_FF_RX_CLK_2_I_G    V_FF_RX_CLK_2_I_G(1U)
76389 #define V_FF_TX_CLK_2_I_G(x) ((x) << S_FF_TX_CLK_2_I_G)
76390 #define F_FF_TX_CLK_2_I_G    V_FF_TX_CLK_2_I_G(1U)
76393 #define V_RXCLK_2_I_G(x) ((x) << S_RXCLK_2_I_G)
76394 #define F_RXCLK_2_I_G    V_RXCLK_2_I_G(1U)
76397 #define V_TXCLK_2_I_G(x) ((x) << S_TXCLK_2_I_G)
76398 #define F_TXCLK_2_I_G    V_TXCLK_2_I_G(1U)
76401 #define V_FF_RX_CLK_3_I_G(x) ((x) << S_FF_RX_CLK_3_I_G)
76402 #define F_FF_RX_CLK_3_I_G    V_FF_RX_CLK_3_I_G(1U)
76405 #define V_FF_TX_CLK_3_I_G(x) ((x) << S_FF_TX_CLK_3_I_G)
76406 #define F_FF_TX_CLK_3_I_G    V_FF_TX_CLK_3_I_G(1U)
76409 #define V_RXCLK_3_I_G(x) ((x) << S_RXCLK_3_I_G)
76410 #define F_RXCLK_3_I_G    V_RXCLK_3_I_G(1U)
76413 #define V_TXCLK_3_I_G(x) ((x) << S_TXCLK_3_I_G)
76414 #define F_TXCLK_3_I_G    V_TXCLK_3_I_G(1U)
76417 #define V_FF_RX_CLK_4_I_G(x) ((x) << S_FF_RX_CLK_4_I_G)
76418 #define F_FF_RX_CLK_4_I_G    V_FF_RX_CLK_4_I_G(1U)
76421 #define V_FF_TX_CLK_4_I_G(x) ((x) << S_FF_TX_CLK_4_I_G)
76422 #define F_FF_TX_CLK_4_I_G    V_FF_TX_CLK_4_I_G(1U)
76425 #define V_RXCLK_4_I_G(x) ((x) << S_RXCLK_4_I_G)
76426 #define F_RXCLK_4_I_G    V_RXCLK_4_I_G(1U)
76429 #define V_TXCLK_4_I_G(x) ((x) << S_TXCLK_4_I_G)
76430 #define F_TXCLK_4_I_G    V_TXCLK_4_I_G(1U)
76433 #define V_FF_RX_CLK_5_I_G(x) ((x) << S_FF_RX_CLK_5_I_G)
76434 #define F_FF_RX_CLK_5_I_G    V_FF_RX_CLK_5_I_G(1U)
76437 #define V_FF_TX_CLK_5_I_G(x) ((x) << S_FF_TX_CLK_5_I_G)
76438 #define F_FF_TX_CLK_5_I_G    V_FF_TX_CLK_5_I_G(1U)
76441 #define V_RXCLK_5_I_G(x) ((x) << S_RXCLK_5_I_G)
76442 #define F_RXCLK_5_I_G    V_RXCLK_5_I_G(1U)
76445 #define V_TXCLK_5_I_G(x) ((x) << S_TXCLK_5_I_G)
76446 #define F_TXCLK_5_I_G    V_TXCLK_5_I_G(1U)
76449 #define V_SD_RX_CLK_AN_0_I_G(x) ((x) << S_SD_RX_CLK_AN_0_I_G)
76450 #define F_SD_RX_CLK_AN_0_I_G    V_SD_RX_CLK_AN_0_I_G(1U)
76453 #define V_SD_TX_CLK_AN_0_I_G(x) ((x) << S_SD_TX_CLK_AN_0_I_G)
76454 #define F_SD_TX_CLK_AN_0_I_G    V_SD_TX_CLK_AN_0_I_G(1U)
76457 #define V_SD_RX_CLK_AN_1_I_G(x) ((x) << S_SD_RX_CLK_AN_1_I_G)
76458 #define F_SD_RX_CLK_AN_1_I_G    V_SD_RX_CLK_AN_1_I_G(1U)
76461 #define V_SD_TX_CLK_AN_1_I_G(x) ((x) << S_SD_TX_CLK_AN_1_I_G)
76462 #define F_SD_TX_CLK_AN_1_I_G    V_SD_TX_CLK_AN_1_I_G(1U)
76465 #define V_SD_RX_CLK_AN_2_I_G(x) ((x) << S_SD_RX_CLK_AN_2_I_G)
76466 #define F_SD_RX_CLK_AN_2_I_G    V_SD_RX_CLK_AN_2_I_G(1U)
76469 #define V_SD_TX_CLK_AN_2_I_G(x) ((x) << S_SD_TX_CLK_AN_2_I_G)
76470 #define F_SD_TX_CLK_AN_2_I_G    V_SD_TX_CLK_AN_2_I_G(1U)
76473 #define V_SD_RX_CLK_AN_3_I_G(x) ((x) << S_SD_RX_CLK_AN_3_I_G)
76474 #define F_SD_RX_CLK_AN_3_I_G    V_SD_RX_CLK_AN_3_I_G(1U)
76477 #define V_SD_TX_CLK_AN_3_I_G(x) ((x) << S_SD_TX_CLK_AN_3_I_G)
76478 #define F_SD_TX_CLK_AN_3_I_G    V_SD_TX_CLK_AN_3_I_G(1U)
76481 #define V_SD_RX_CLK_AN_4_I_G(x) ((x) << S_SD_RX_CLK_AN_4_I_G)
76482 #define F_SD_RX_CLK_AN_4_I_G    V_SD_RX_CLK_AN_4_I_G(1U)
76485 #define V_SD_TX_CLK_AN_4_I_G(x) ((x) << S_SD_TX_CLK_AN_4_I_G)
76486 #define F_SD_TX_CLK_AN_4_I_G    V_SD_TX_CLK_AN_4_I_G(1U)
76489 #define V_SD_RX_CLK_AN_5_I_G(x) ((x) << S_SD_RX_CLK_AN_5_I_G)
76490 #define F_SD_RX_CLK_AN_5_I_G    V_SD_RX_CLK_AN_5_I_G(1U)
76493 #define V_SD_TX_CLK_AN_5_I_G(x) ((x) << S_SD_TX_CLK_AN_5_I_G)
76494 #define F_SD_TX_CLK_AN_5_I_G    V_SD_TX_CLK_AN_5_I_G(1U)
76497 #define V_SD_RX_CLK_AN_6_I_G(x) ((x) << S_SD_RX_CLK_AN_6_I_G)
76498 #define F_SD_RX_CLK_AN_6_I_G    V_SD_RX_CLK_AN_6_I_G(1U)
76501 #define V_SD_TX_CLK_AN_6_I_G(x) ((x) << S_SD_TX_CLK_AN_6_I_G)
76502 #define F_SD_TX_CLK_AN_6_I_G    V_SD_TX_CLK_AN_6_I_G(1U)
76504 #define S_SD_RX_CLK_AN_7_I_G    1
76505 #define V_SD_RX_CLK_AN_7_I_G(x) ((x) << S_SD_RX_CLK_AN_7_I_G)
76506 #define F_SD_RX_CLK_AN_7_I_G    V_SD_RX_CLK_AN_7_I_G(1U)
76509 #define V_SD_TX_CLK_AN_7_I_G(x) ((x) << S_SD_TX_CLK_AN_7_I_G)
76510 #define F_SD_TX_CLK_AN_7_I_G    V_SD_TX_CLK_AN_7_I_G(1U)
76515 #define V_SD_RX_CLK_0_G(x) ((x) << S_SD_RX_CLK_0_G)
76516 #define F_SD_RX_CLK_0_G    V_SD_RX_CLK_0_G(1U)
76519 #define V_SD_RX_CLK_1_G(x) ((x) << S_SD_RX_CLK_1_G)
76520 #define F_SD_RX_CLK_1_G    V_SD_RX_CLK_1_G(1U)
76523 #define V_SD_RX_CLK_2_G(x) ((x) << S_SD_RX_CLK_2_G)
76524 #define F_SD_RX_CLK_2_G    V_SD_RX_CLK_2_G(1U)
76527 #define V_SD_RX_CLK_3_G(x) ((x) << S_SD_RX_CLK_3_G)
76528 #define F_SD_RX_CLK_3_G    V_SD_RX_CLK_3_G(1U)
76531 #define V_SD_RX_CLK_4_G(x) ((x) << S_SD_RX_CLK_4_G)
76532 #define F_SD_RX_CLK_4_G    V_SD_RX_CLK_4_G(1U)
76535 #define V_SD_RX_CLK_5_G(x) ((x) << S_SD_RX_CLK_5_G)
76536 #define F_SD_RX_CLK_5_G    V_SD_RX_CLK_5_G(1U)
76539 #define V_SD_RX_CLK_6_G(x) ((x) << S_SD_RX_CLK_6_G)
76540 #define F_SD_RX_CLK_6_G    V_SD_RX_CLK_6_G(1U)
76543 #define V_SD_RX_CLK_7_G(x) ((x) << S_SD_RX_CLK_7_G)
76544 #define F_SD_RX_CLK_7_G    V_SD_RX_CLK_7_G(1U)
76547 #define V_SD_TX_CLK_0_G(x) ((x) << S_SD_TX_CLK_0_G)
76548 #define F_SD_TX_CLK_0_G    V_SD_TX_CLK_0_G(1U)
76551 #define V_SD_TX_CLK_1_G(x) ((x) << S_SD_TX_CLK_1_G)
76552 #define F_SD_TX_CLK_1_G    V_SD_TX_CLK_1_G(1U)
76555 #define V_SD_TX_CLK_2_G(x) ((x) << S_SD_TX_CLK_2_G)
76556 #define F_SD_TX_CLK_2_G    V_SD_TX_CLK_2_G(1U)
76559 #define V_SD_TX_CLK_3_G(x) ((x) << S_SD_TX_CLK_3_G)
76560 #define F_SD_TX_CLK_3_G    V_SD_TX_CLK_3_G(1U)
76563 #define V_SD_TX_CLK_4_G(x) ((x) << S_SD_TX_CLK_4_G)
76564 #define F_SD_TX_CLK_4_G    V_SD_TX_CLK_4_G(1U)
76567 #define V_SD_TX_CLK_5_G(x) ((x) << S_SD_TX_CLK_5_G)
76568 #define F_SD_TX_CLK_5_G    V_SD_TX_CLK_5_G(1U)
76571 #define V_SD_TX_CLK_6_G(x) ((x) << S_SD_TX_CLK_6_G)
76572 #define F_SD_TX_CLK_6_G    V_SD_TX_CLK_6_G(1U)
76575 #define V_SD_TX_CLK_7_G(x) ((x) << S_SD_TX_CLK_7_G)
76576 #define F_SD_TX_CLK_7_G    V_SD_TX_CLK_7_G(1U)
76579 #define V_SD_RX_CLK_AEC_0_G(x) ((x) << S_SD_RX_CLK_AEC_0_G)
76580 #define F_SD_RX_CLK_AEC_0_G    V_SD_RX_CLK_AEC_0_G(1U)
76583 #define V_SD_RX_CLK_AEC_1_G(x) ((x) << S_SD_RX_CLK_AEC_1_G)
76584 #define F_SD_RX_CLK_AEC_1_G    V_SD_RX_CLK_AEC_1_G(1U)
76587 #define V_SD_RX_CLK_AEC_2_G(x) ((x) << S_SD_RX_CLK_AEC_2_G)
76588 #define F_SD_RX_CLK_AEC_2_G    V_SD_RX_CLK_AEC_2_G(1U)
76591 #define V_SD_RX_CLK_AEC_3_G(x) ((x) << S_SD_RX_CLK_AEC_3_G)
76592 #define F_SD_RX_CLK_AEC_3_G    V_SD_RX_CLK_AEC_3_G(1U)
76595 #define V_SD_RX_CLK_AEC_4_G(x) ((x) << S_SD_RX_CLK_AEC_4_G)
76596 #define F_SD_RX_CLK_AEC_4_G    V_SD_RX_CLK_AEC_4_G(1U)
76599 #define V_SD_RX_CLK_AEC_5_G(x) ((x) << S_SD_RX_CLK_AEC_5_G)
76600 #define F_SD_RX_CLK_AEC_5_G    V_SD_RX_CLK_AEC_5_G(1U)
76603 #define V_SD_RX_CLK_AEC_6_G(x) ((x) << S_SD_RX_CLK_AEC_6_G)
76604 #define F_SD_RX_CLK_AEC_6_G    V_SD_RX_CLK_AEC_6_G(1U)
76607 #define V_SD_RX_CLK_AEC_7_G(x) ((x) << S_SD_RX_CLK_AEC_7_G)
76608 #define F_SD_RX_CLK_AEC_7_G    V_SD_RX_CLK_AEC_7_G(1U)
76611 #define V_SD_TX_CLK_AEC_0_G(x) ((x) << S_SD_TX_CLK_AEC_0_G)
76612 #define F_SD_TX_CLK_AEC_0_G    V_SD_TX_CLK_AEC_0_G(1U)
76615 #define V_SD_TX_CLK_AEC_1_G(x) ((x) << S_SD_TX_CLK_AEC_1_G)
76616 #define F_SD_TX_CLK_AEC_1_G    V_SD_TX_CLK_AEC_1_G(1U)
76619 #define V_SD_TX_CLK_AEC_2_G(x) ((x) << S_SD_TX_CLK_AEC_2_G)
76620 #define F_SD_TX_CLK_AEC_2_G    V_SD_TX_CLK_AEC_2_G(1U)
76623 #define V_SD_TX_CLK_AEC_3_G(x) ((x) << S_SD_TX_CLK_AEC_3_G)
76624 #define F_SD_TX_CLK_AEC_3_G    V_SD_TX_CLK_AEC_3_G(1U)
76627 #define V_SD_TX_CLK_AEC_4_G(x) ((x) << S_SD_TX_CLK_AEC_4_G)
76628 #define F_SD_TX_CLK_AEC_4_G    V_SD_TX_CLK_AEC_4_G(1U)
76631 #define V_SD_TX_CLK_AEC_5_G(x) ((x) << S_SD_TX_CLK_AEC_5_G)
76632 #define F_SD_TX_CLK_AEC_5_G    V_SD_TX_CLK_AEC_5_G(1U)
76634 #define S_SD_TX_CLK_AEC_6_G    1
76635 #define V_SD_TX_CLK_AEC_6_G(x) ((x) << S_SD_TX_CLK_AEC_6_G)
76636 #define F_SD_TX_CLK_AEC_6_G    V_SD_TX_CLK_AEC_6_G(1U)
76639 #define V_SD_TX_CLK_AEC_7_G(x) ((x) << S_SD_TX_CLK_AEC_7_G)
76640 #define F_SD_TX_CLK_AEC_7_G    V_SD_TX_CLK_AEC_7_G(1U)
76645 #define V_PCS_RX_CLK_0_G(x) ((x) << S_PCS_RX_CLK_0_G)
76646 #define F_PCS_RX_CLK_0_G    V_PCS_RX_CLK_0_G(1U)
76649 #define V_PCS_RX_CLK_1_G(x) ((x) << S_PCS_RX_CLK_1_G)
76650 #define F_PCS_RX_CLK_1_G    V_PCS_RX_CLK_1_G(1U)
76653 #define V_PCS_RX_CLK_2_G(x) ((x) << S_PCS_RX_CLK_2_G)
76654 #define F_PCS_RX_CLK_2_G    V_PCS_RX_CLK_2_G(1U)
76657 #define V_PCS_RX_CLK_3_G(x) ((x) << S_PCS_RX_CLK_3_G)
76658 #define F_PCS_RX_CLK_3_G    V_PCS_RX_CLK_3_G(1U)
76661 #define V_PCS_RX_CLK_4_G(x) ((x) << S_PCS_RX_CLK_4_G)
76662 #define F_PCS_RX_CLK_4_G    V_PCS_RX_CLK_4_G(1U)
76665 #define V_PCS_RX_CLK_5_G(x) ((x) << S_PCS_RX_CLK_5_G)
76666 #define F_PCS_RX_CLK_5_G    V_PCS_RX_CLK_5_G(1U)
76669 #define V_PCS_RX_CLK_6_G(x) ((x) << S_PCS_RX_CLK_6_G)
76670 #define F_PCS_RX_CLK_6_G    V_PCS_RX_CLK_6_G(1U)
76673 #define V_PCS_RX_CLK_7_G(x) ((x) << S_PCS_RX_CLK_7_G)
76674 #define F_PCS_RX_CLK_7_G    V_PCS_RX_CLK_7_G(1U)
76677 #define V_PCS_TX_CLK_0_G(x) ((x) << S_PCS_TX_CLK_0_G)
76678 #define F_PCS_TX_CLK_0_G    V_PCS_TX_CLK_0_G(1U)
76681 #define V_PCS_TX_CLK_1_G(x) ((x) << S_PCS_TX_CLK_1_G)
76682 #define F_PCS_TX_CLK_1_G    V_PCS_TX_CLK_1_G(1U)
76685 #define V_PCS_TX_CLK_2_G(x) ((x) << S_PCS_TX_CLK_2_G)
76686 #define F_PCS_TX_CLK_2_G    V_PCS_TX_CLK_2_G(1U)
76689 #define V_PCS_TX_CLK_3_G(x) ((x) << S_PCS_TX_CLK_3_G)
76690 #define F_PCS_TX_CLK_3_G    V_PCS_TX_CLK_3_G(1U)
76693 #define V_PCS_TX_CLK_4_G(x) ((x) << S_PCS_TX_CLK_4_G)
76694 #define F_PCS_TX_CLK_4_G    V_PCS_TX_CLK_4_G(1U)
76697 #define V_PCS_TX_CLK_5_G(x) ((x) << S_PCS_TX_CLK_5_G)
76698 #define F_PCS_TX_CLK_5_G    V_PCS_TX_CLK_5_G(1U)
76701 #define V_PCS_TX_CLK_6_G(x) ((x) << S_PCS_TX_CLK_6_G)
76702 #define F_PCS_TX_CLK_6_G    V_PCS_TX_CLK_6_G(1U)
76705 #define V_PCS_TX_CLK_7_G(x) ((x) << S_PCS_TX_CLK_7_G)
76706 #define F_PCS_TX_CLK_7_G    V_PCS_TX_CLK_7_G(1U)
76709 #define V_SD_RX_CLK_EN_0(x) ((x) << S_SD_RX_CLK_EN_0)
76710 #define F_SD_RX_CLK_EN_0    V_SD_RX_CLK_EN_0(1U)
76713 #define V_SD_RX_CLK_EN_1(x) ((x) << S_SD_RX_CLK_EN_1)
76714 #define F_SD_RX_CLK_EN_1    V_SD_RX_CLK_EN_1(1U)
76717 #define V_SD_RX_CLK_EN_2(x) ((x) << S_SD_RX_CLK_EN_2)
76718 #define F_SD_RX_CLK_EN_2    V_SD_RX_CLK_EN_2(1U)
76721 #define V_SD_RX_CLK_EN_3(x) ((x) << S_SD_RX_CLK_EN_3)
76722 #define F_SD_RX_CLK_EN_3    V_SD_RX_CLK_EN_3(1U)
76725 #define V_SD_RX_CLK_EN_4(x) ((x) << S_SD_RX_CLK_EN_4)
76726 #define F_SD_RX_CLK_EN_4    V_SD_RX_CLK_EN_4(1U)
76729 #define V_SD_RX_CLK_EN_5(x) ((x) << S_SD_RX_CLK_EN_5)
76730 #define F_SD_RX_CLK_EN_5    V_SD_RX_CLK_EN_5(1U)
76733 #define V_SD_RX_CLK_EN_6(x) ((x) << S_SD_RX_CLK_EN_6)
76734 #define F_SD_RX_CLK_EN_6    V_SD_RX_CLK_EN_6(1U)
76737 #define V_SD_RX_CLK_EN_7(x) ((x) << S_SD_RX_CLK_EN_7)
76738 #define F_SD_RX_CLK_EN_7    V_SD_RX_CLK_EN_7(1U)
76741 #define V_SD_TX_CLK_EN_0(x) ((x) << S_SD_TX_CLK_EN_0)
76742 #define F_SD_TX_CLK_EN_0    V_SD_TX_CLK_EN_0(1U)
76745 #define V_SD_TX_CLK_EN_1(x) ((x) << S_SD_TX_CLK_EN_1)
76746 #define F_SD_TX_CLK_EN_1    V_SD_TX_CLK_EN_1(1U)
76749 #define V_SD_TX_CLK_EN_2(x) ((x) << S_SD_TX_CLK_EN_2)
76750 #define F_SD_TX_CLK_EN_2    V_SD_TX_CLK_EN_2(1U)
76753 #define V_SD_TX_CLK_EN_3(x) ((x) << S_SD_TX_CLK_EN_3)
76754 #define F_SD_TX_CLK_EN_3    V_SD_TX_CLK_EN_3(1U)
76757 #define V_SD_TX_CLK_EN_4(x) ((x) << S_SD_TX_CLK_EN_4)
76758 #define F_SD_TX_CLK_EN_4    V_SD_TX_CLK_EN_4(1U)
76761 #define V_SD_TX_CLK_EN_5(x) ((x) << S_SD_TX_CLK_EN_5)
76762 #define F_SD_TX_CLK_EN_5    V_SD_TX_CLK_EN_5(1U)
76764 #define S_SD_TX_CLK_EN_6    1
76765 #define V_SD_TX_CLK_EN_6(x) ((x) << S_SD_TX_CLK_EN_6)
76766 #define F_SD_TX_CLK_EN_6    V_SD_TX_CLK_EN_6(1U)
76769 #define V_SD_TX_CLK_EN_7(x) ((x) << S_SD_TX_CLK_EN_7)
76770 #define F_SD_TX_CLK_EN_7    V_SD_TX_CLK_EN_7(1U)
76775 #define V_SGMII_TX_CLK_0_G(x) ((x) << S_SGMII_TX_CLK_0_G)
76776 #define F_SGMII_TX_CLK_0_G    V_SGMII_TX_CLK_0_G(1U)
76779 #define V_SGMII_TX_CLK_1_G(x) ((x) << S_SGMII_TX_CLK_1_G)
76780 #define F_SGMII_TX_CLK_1_G    V_SGMII_TX_CLK_1_G(1U)
76783 #define V_SGMII_TX_CLK_2_G(x) ((x) << S_SGMII_TX_CLK_2_G)
76784 #define F_SGMII_TX_CLK_2_G    V_SGMII_TX_CLK_2_G(1U)
76787 #define V_SGMII_TX_CLK_3_G(x) ((x) << S_SGMII_TX_CLK_3_G)
76788 #define F_SGMII_TX_CLK_3_G    V_SGMII_TX_CLK_3_G(1U)
76791 #define V_SGMII_RX_CLK_0_G(x) ((x) << S_SGMII_RX_CLK_0_G)
76792 #define F_SGMII_RX_CLK_0_G    V_SGMII_RX_CLK_0_G(1U)
76795 #define V_SGMII_RX_CLK_1_G(x) ((x) << S_SGMII_RX_CLK_1_G)
76796 #define F_SGMII_RX_CLK_1_G    V_SGMII_RX_CLK_1_G(1U)
76798 #define S_SGMII_RX_CLK_2_G    1
76799 #define V_SGMII_RX_CLK_2_G(x) ((x) << S_SGMII_RX_CLK_2_G)
76800 #define F_SGMII_RX_CLK_2_G    V_SGMII_RX_CLK_2_G(1U)
76803 #define V_SGMII_RX_CLK_3_G(x) ((x) << S_SGMII_RX_CLK_3_G)
76804 #define F_SGMII_RX_CLK_3_G    V_SGMII_RX_CLK_3_G(1U)
76810 #define V_KP_MODE_IN(x) ((x) << S_KP_MODE_IN)
76811 #define G_KP_MODE_IN(x) (((x) >> S_KP_MODE_IN) & M_KP_MODE_IN)
76815 #define V_FEC91_ENA_IN(x) ((x) << S_FEC91_ENA_IN)
76816 #define G_FEC91_ENA_IN(x) (((x) >> S_FEC91_ENA_IN) & M_FEC91_ENA_IN)
76820 #define V_SD_8X(x) ((x) << S_SD_8X)
76821 #define G_SD_8X(x) (((x) >> S_SD_8X) & M_SD_8X)
76825 #define V_SD_N2(x) ((x) << S_SD_N2)
76826 #define G_SD_N2(x) (((x) >> S_SD_N2) & M_SD_N2)
76832 #define V_FAST_1LANE_MODE(x) ((x) << S_FAST_1LANE_MODE)
76833 #define G_FAST_1LANE_MODE(x) (((x) >> S_FAST_1LANE_MODE) & M_FAST_1LANE_MODE)
76837 #define V_PACER_10G(x) ((x) << S_PACER_10G)
76838 #define G_PACER_10G(x) (((x) >> S_PACER_10G) & M_PACER_10G)
76842 #define V_PCS400_ENA_IN(x) ((x) << S_PCS400_ENA_IN)
76843 #define G_PCS400_ENA_IN(x) (((x) >> S_PCS400_ENA_IN) & M_PCS400_ENA_IN)
76846 #define V_MODE40_ENA_IN4(x) ((x) << S_MODE40_ENA_IN4)
76847 #define F_MODE40_ENA_IN4    V_MODE40_ENA_IN4(1U)
76850 #define V_MODE40_ENA_IN0(x) ((x) << S_MODE40_ENA_IN0)
76851 #define F_MODE40_ENA_IN0    V_MODE40_ENA_IN0(1U)
76854 #define V_PCS100_ENA_IN6(x) ((x) << S_PCS100_ENA_IN6)
76855 #define F_PCS100_ENA_IN6    V_PCS100_ENA_IN6(1U)
76858 #define V_PCS100_ENA_IN4(x) ((x) << S_PCS100_ENA_IN4)
76859 #define F_PCS100_ENA_IN4    V_PCS100_ENA_IN4(1U)
76862 #define V_PCS100_ENA_IN2(x) ((x) << S_PCS100_ENA_IN2)
76863 #define F_PCS100_ENA_IN2    V_PCS100_ENA_IN2(1U)
76866 #define V_PCS100_ENA_IN0(x) ((x) << S_PCS100_ENA_IN0)
76867 #define F_PCS100_ENA_IN0    V_PCS100_ENA_IN0(1U)
76870 #define V_RXLAUI_ENA_IN6(x) ((x) << S_RXLAUI_ENA_IN6)
76871 #define F_RXLAUI_ENA_IN6    V_RXLAUI_ENA_IN6(1U)
76874 #define V_RXLAUI_ENA_IN4(x) ((x) << S_RXLAUI_ENA_IN4)
76875 #define F_RXLAUI_ENA_IN4    V_RXLAUI_ENA_IN4(1U)
76878 #define V_RXLAUI_ENA_IN2(x) ((x) << S_RXLAUI_ENA_IN2)
76879 #define F_RXLAUI_ENA_IN2    V_RXLAUI_ENA_IN2(1U)
76882 #define V_RXLAUI_ENA_IN0(x) ((x) << S_RXLAUI_ENA_IN0)
76883 #define F_RXLAUI_ENA_IN0    V_RXLAUI_ENA_IN0(1U)
76886 #define V_FEC91_LANE_IN6(x) ((x) << S_FEC91_LANE_IN6)
76887 #define F_FEC91_LANE_IN6    V_FEC91_LANE_IN6(1U)
76890 #define V_FEC91_LANE_IN4(x) ((x) << S_FEC91_LANE_IN4)
76891 #define F_FEC91_LANE_IN4    V_FEC91_LANE_IN4(1U)
76893 #define S_FEC91_LANE_IN2    1
76894 #define V_FEC91_LANE_IN2(x) ((x) << S_FEC91_LANE_IN2)
76895 #define F_FEC91_LANE_IN2    V_FEC91_LANE_IN2(1U)
76898 #define V_FEC91_LANE_IN0(x) ((x) << S_FEC91_LANE_IN0)
76899 #define F_FEC91_LANE_IN0    V_FEC91_LANE_IN0(1U)
76904 #define V_SGPCS_EN_3(x) ((x) << S_SGPCS_EN_3)
76905 #define F_SGPCS_EN_3    V_SGPCS_EN_3(1U)
76908 #define V_SGPCS_EN_2(x) ((x) << S_SGPCS_EN_2)
76909 #define F_SGPCS_EN_2    V_SGPCS_EN_2(1U)
76912 #define V_SGPCS_EN_1(x) ((x) << S_SGPCS_EN_1)
76913 #define F_SGPCS_EN_1    V_SGPCS_EN_1(1U)
76916 #define V_SGPCS_EN_0(x) ((x) << S_SGPCS_EN_0)
76917 #define F_SGPCS_EN_0    V_SGPCS_EN_0(1U)
76921 #define V_CFG_CLOCK_RATE(x) ((x) << S_CFG_CLOCK_RATE)
76922 #define G_CFG_CLOCK_RATE(x) (((x) >> S_CFG_CLOCK_RATE) & M_CFG_CLOCK_RATE)
76926 #define V_FEC_ERR_ENA(x) ((x) << S_FEC_ERR_ENA)
76927 #define G_FEC_ERR_ENA(x) (((x) >> S_FEC_ERR_ENA) & M_FEC_ERR_ENA)
76931 #define V_FEC_ENA(x) ((x) << S_FEC_ENA)
76932 #define G_FEC_ENA(x) (((x) >> S_FEC_ENA) & M_FEC_ENA)
76936 #define V_PCS001_TX_AM_SF(x) ((x) << S_PCS001_TX_AM_SF)
76937 #define G_PCS001_TX_AM_SF(x) (((x) >> S_PCS001_TX_AM_SF) & M_PCS001_TX_AM_SF)
76941 #define V_PCS000_TX_AM_SF(x) ((x) << S_PCS000_TX_AM_SF)
76942 #define G_PCS000_TX_AM_SF(x) (((x) >> S_PCS000_TX_AM_SF) & M_PCS000_TX_AM_SF)
76948 #define V_PCS000_ALIGN_LOCK(x) ((x) << S_PCS000_ALIGN_LOCK)
76949 #define G_PCS000_ALIGN_LOCK(x) (((x) >> S_PCS000_ALIGN_LOCK) & M_PCS000_ALIGN_LOCK)
76953 #define V_PCS000_HI_SER(x) ((x) << S_PCS000_HI_SER)
76954 #define G_PCS000_HI_SER(x) (((x) >> S_PCS000_HI_SER) & M_PCS000_HI_SER)
76958 #define V_BER_TIMER_DONE(x) ((x) << S_BER_TIMER_DONE)
76959 #define G_BER_TIMER_DONE(x) (((x) >> S_BER_TIMER_DONE) & M_BER_TIMER_DONE)
76963 #define V_T7_AMPS_LOCK(x) ((x) << S_T7_AMPS_LOCK)
76964 #define G_T7_AMPS_LOCK(x) (((x) >> S_T7_AMPS_LOCK) & M_T7_AMPS_LOCK)
76968 #define V_T7_ALIGN_DONE(x) ((x) << S_T7_ALIGN_DONE)
76969 #define G_T7_ALIGN_DONE(x) (((x) >> S_T7_ALIGN_DONE) & M_T7_ALIGN_DONE)
76976 #define V_RSFEC_ALIGNED(x) ((x) << S_RSFEC_ALIGNED)
76977 #define G_RSFEC_ALIGNED(x) (((x) >> S_RSFEC_ALIGNED) & M_RSFEC_ALIGNED)
76981 #define V_T7_FEC_LOCKED(x) ((x) << S_T7_FEC_LOCKED)
76982 #define G_T7_FEC_LOCKED(x) (((x) >> S_T7_FEC_LOCKED) & M_T7_FEC_LOCKED)
76986 #define V_T7_BLOCK_LOCK(x) ((x) << S_T7_BLOCK_LOCK)
76987 #define G_T7_BLOCK_LOCK(x) (((x) >> S_T7_BLOCK_LOCK) & M_T7_BLOCK_LOCK)
76993 #define V_FEC_NCERR(x) ((x) << S_FEC_NCERR)
76994 #define G_FEC_NCERR(x) (((x) >> S_FEC_NCERR) & M_FEC_NCERR)
76998 #define V_FEC_CERR(x) ((x) << S_FEC_CERR)
76999 #define G_FEC_CERR(x) (((x) >> S_FEC_CERR) & M_FEC_CERR)
77005 #define V_MAC1_RES_SPEED(x) ((x) << S_MAC1_RES_SPEED)
77006 #define G_MAC1_RES_SPEED(x) (((x) >> S_MAC1_RES_SPEED) & M_MAC1_RES_SPEED)
77010 #define V_MAC0_RES_SPEED(x) ((x) << S_MAC0_RES_SPEED)
77011 #define G_MAC0_RES_SPEED(x) (((x) >> S_MAC0_RES_SPEED) & M_MAC0_RES_SPEED)
77015 #define V_PCS400_ENA_IN_REF(x) ((x) << S_PCS400_ENA_IN_REF)
77016 #define G_PCS400_ENA_IN_REF(x) (((x) >> S_PCS400_ENA_IN_REF) & M_PCS400_ENA_IN_REF)
77020 #define V_PCS000_DEGRADE_SER(x) ((x) << S_PCS000_DEGRADE_SER)
77021 #define G_PCS000_DEGRADE_SER(x) (((x) >> S_PCS000_DEGRADE_SER) & M_PCS000_DEGRADE_SER)
77025 #define V_P4X_SIGNAL_OK(x) ((x) << S_P4X_SIGNAL_OK)
77026 #define G_P4X_SIGNAL_OK(x) (((x) >> S_P4X_SIGNAL_OK) & M_P4X_SIGNAL_OK)
77029 #define V_MODE200_IND_REF(x) ((x) << S_MODE200_IND_REF)
77030 #define F_MODE200_IND_REF    V_MODE200_IND_REF(1U)
77033 #define V_MODE200_8X26_IND_REF(x) ((x) << S_MODE200_8X26_IND_REF)
77034 #define F_MODE200_8X26_IND_REF    V_MODE200_8X26_IND_REF(1U)
77038 #define V_PCS001_RX_AM_SF(x) ((x) << S_PCS001_RX_AM_SF)
77039 #define G_PCS001_RX_AM_SF(x) (((x) >> S_PCS001_RX_AM_SF) & M_PCS001_RX_AM_SF)
77043 #define V_PCS000_RX_AM_SF(x) ((x) << S_PCS000_RX_AM_SF)
77044 #define G_PCS000_RX_AM_SF(x) (((x) >> S_PCS000_RX_AM_SF) & M_PCS000_RX_AM_SF)
77050 #define V_MAC5_RES_SPEED(x) ((x) << S_MAC5_RES_SPEED)
77051 #define G_MAC5_RES_SPEED(x) (((x) >> S_MAC5_RES_SPEED) & M_MAC5_RES_SPEED)
77055 #define V_MAC4_RES_SPEED(x) ((x) << S_MAC4_RES_SPEED)
77056 #define G_MAC4_RES_SPEED(x) (((x) >> S_MAC4_RES_SPEED) & M_MAC4_RES_SPEED)
77060 #define V_MAC3_RES_SPEED(x) ((x) << S_MAC3_RES_SPEED)
77061 #define G_MAC3_RES_SPEED(x) (((x) >> S_MAC3_RES_SPEED) & M_MAC3_RES_SPEED)
77065 #define V_MAC2_RES_SPEED(x) ((x) << S_MAC2_RES_SPEED)
77066 #define G_MAC2_RES_SPEED(x) (((x) >> S_MAC2_RES_SPEED) & M_MAC2_RES_SPEED)
77072 #define V_MARKER_INS_CNT_100_00(x) ((x) << S_MARKER_INS_CNT_100_00)
77073 #define G_MARKER_INS_CNT_100_00(x) (((x) >> S_MARKER_INS_CNT_100_00) & M_MARKER_INS_CNT_100_00)
77077 #define V_MAC7_RES_SPEED(x) ((x) << S_MAC7_RES_SPEED)
77078 #define G_MAC7_RES_SPEED(x) (((x) >> S_MAC7_RES_SPEED) & M_MAC7_RES_SPEED)
77082 #define V_MAC6_RES_SPEED(x) ((x) << S_MAC6_RES_SPEED)
77083 #define G_MAC6_RES_SPEED(x) (((x) >> S_MAC6_RES_SPEED) & M_MAC6_RES_SPEED)
77089 #define V_PCS000_LINK_STATUS(x) ((x) << S_PCS000_LINK_STATUS)
77090 #define G_PCS000_LINK_STATUS(x) (((x) >> S_PCS000_LINK_STATUS) & M_PCS000_LINK_STATUS)
77094 #define V_MARKER_INS_CNT_100_02(x) ((x) << S_MARKER_INS_CNT_100_02)
77095 #define G_MARKER_INS_CNT_100_02(x) (((x) >> S_MARKER_INS_CNT_100_02) & M_MARKER_INS_CNT_100_02)
77099 #define V_MARKER_INS_CNT_100_01(x) ((x) << S_MARKER_INS_CNT_100_01)
77100 #define G_MARKER_INS_CNT_100_01(x) (((x) >> S_MARKER_INS_CNT_100_01) & M_MARKER_INS_CNT_100_01)
77106 #define V_MARKER_INS_CNT_25_1(x) ((x) << S_MARKER_INS_CNT_25_1)
77107 #define G_MARKER_INS_CNT_25_1(x) (((x) >> S_MARKER_INS_CNT_25_1) & M_MARKER_INS_CNT_25_1)
77111 #define V_MARKER_INS_CNT_100_03(x) ((x) << S_MARKER_INS_CNT_100_03)
77112 #define G_MARKER_INS_CNT_100_03(x) (((x) >> S_MARKER_INS_CNT_100_03) & M_MARKER_INS_CNT_100_03)
77118 #define V_MARKER_INS_CNT_25_5(x) ((x) << S_MARKER_INS_CNT_25_5)
77119 #define G_MARKER_INS_CNT_25_5(x) (((x) >> S_MARKER_INS_CNT_25_5) & M_MARKER_INS_CNT_25_5)
77123 #define V_MARKER_INS_CNT_25_3(x) ((x) << S_MARKER_INS_CNT_25_3)
77124 #define G_MARKER_INS_CNT_25_3(x) (((x) >> S_MARKER_INS_CNT_25_3) & M_MARKER_INS_CNT_25_3)
77130 #define V_MARKER_INS_CNT_25_50_2(x) ((x) << S_MARKER_INS_CNT_25_50_2)
77131 #define G_MARKER_INS_CNT_25_50_2(x) (((x) >> S_MARKER_INS_CNT_25_50_2) & M_MARKER_INS_CNT_25_50_2)
77135 #define V_MARKER_INS_CNT_25_50_0(x) ((x) << S_MARKER_INS_CNT_25_50_0)
77136 #define G_MARKER_INS_CNT_25_50_0(x) (((x) >> S_MARKER_INS_CNT_25_50_0) & M_MARKER_INS_CNT_25_50_0)
77142 #define V_MARKER_INS_CNT_25_50_6(x) ((x) << S_MARKER_INS_CNT_25_50_6)
77143 #define G_MARKER_INS_CNT_25_50_6(x) (((x) >> S_MARKER_INS_CNT_25_50_6) & M_MARKER_INS_CNT_25_50_6)
77147 #define V_MARKER_INS_CNT_25_50_4(x) ((x) << S_MARKER_INS_CNT_25_50_4)
77148 #define G_MARKER_INS_CNT_25_50_4(x) (((x) >> S_MARKER_INS_CNT_25_50_4) & M_MARKER_INS_CNT_25_50_4)
77154 #define V_T7_LINK_STATUS(x) ((x) << S_T7_LINK_STATUS)
77155 #define G_T7_LINK_STATUS(x) (((x) >> S_T7_LINK_STATUS) & M_T7_LINK_STATUS)
77159 #define V_T7_HI_BER(x) ((x) << S_T7_HI_BER)
77160 #define G_T7_HI_BER(x) (((x) >> S_T7_HI_BER) & M_T7_HI_BER)
77164 #define V_MARKER_INS_CNT_25_7(x) ((x) << S_MARKER_INS_CNT_25_7)
77165 #define G_MARKER_INS_CNT_25_7(x) (((x) >> S_MARKER_INS_CNT_25_7) & M_MARKER_INS_CNT_25_7)
77171 #define V_FF_TX_CRC_OVR(x) ((x) << S_FF_TX_CRC_OVR)
77172 #define F_FF_TX_CRC_OVR    V_FF_TX_CRC_OVR(1U)
77175 #define V_TX_SMHOLD(x) ((x) << S_TX_SMHOLD)
77176 #define F_TX_SMHOLD    V_TX_SMHOLD(1U)
77184 #define V_FRC_DELTA(x) ((x) << S_FRC_DELTA)
77185 #define G_FRC_DELTA(x) (((x) >> S_FRC_DELTA) & M_FRC_DELTA)
77190 #define V_T7_LOOP_ENA(x) ((x) << S_T7_LOOP_ENA)
77191 #define F_T7_LOOP_ENA    V_T7_LOOP_ENA(1U)
77194 #define V_T7_LOC_FAULT(x) ((x) << S_T7_LOC_FAULT)
77195 #define F_T7_LOC_FAULT    V_T7_LOC_FAULT(1U)
77198 #define V_FRM_DROP(x) ((x) << S_FRM_DROP)
77199 #define F_FRM_DROP    V_FRM_DROP(1U)
77201 #define S_FF_TX_CREDIT    1
77202 #define V_FF_TX_CREDIT(x) ((x) << S_FF_TX_CREDIT)
77203 #define F_FF_TX_CREDIT    V_FF_TX_CREDIT(1U)
77215 #define V_T7_AN_DATA_CTL(x) ((x) << S_T7_AN_DATA_CTL)
77216 #define G_T7_AN_DATA_CTL(x) (((x) >> S_T7_AN_DATA_CTL) & M_T7_AN_DATA_CTL)
77220 #define V_T7_AN_ENA(x) ((x) << S_T7_AN_ENA)
77221 #define G_T7_AN_ENA(x) (((x) >> S_T7_AN_ENA) & M_T7_AN_ENA)
77226 #define V_AN_DIS_TIMER_AN_7(x) ((x) << S_AN_DIS_TIMER_AN_7)
77227 #define F_AN_DIS_TIMER_AN_7    V_AN_DIS_TIMER_AN_7(1U)
77230 #define V_AN_DIS_TIMER_AN_6(x) ((x) << S_AN_DIS_TIMER_AN_6)
77231 #define F_AN_DIS_TIMER_AN_6    V_AN_DIS_TIMER_AN_6(1U)
77234 #define V_AN_DIS_TIMER_AN_5(x) ((x) << S_AN_DIS_TIMER_AN_5)
77235 #define F_AN_DIS_TIMER_AN_5    V_AN_DIS_TIMER_AN_5(1U)
77238 #define V_AN_DIS_TIMER_AN_4(x) ((x) << S_AN_DIS_TIMER_AN_4)
77239 #define F_AN_DIS_TIMER_AN_4    V_AN_DIS_TIMER_AN_4(1U)
77242 #define V_AN_DIS_TIMER_AN_3(x) ((x) << S_AN_DIS_TIMER_AN_3)
77243 #define F_AN_DIS_TIMER_AN_3    V_AN_DIS_TIMER_AN_3(1U)
77246 #define V_AN_DIS_TIMER_AN_2(x) ((x) << S_AN_DIS_TIMER_AN_2)
77247 #define F_AN_DIS_TIMER_AN_2    V_AN_DIS_TIMER_AN_2(1U)
77249 #define S_AN_DIS_TIMER_AN_1    1
77250 #define V_AN_DIS_TIMER_AN_1(x) ((x) << S_AN_DIS_TIMER_AN_1)
77251 #define F_AN_DIS_TIMER_AN_1    V_AN_DIS_TIMER_AN_1(1U)
77254 #define V_AN_DIS_TIMER_AN_0(x) ((x) << S_AN_DIS_TIMER_AN_0)
77255 #define F_AN_DIS_TIMER_AN_0    V_AN_DIS_TIMER_AN_0(1U)
77260 #define V_AN_SD25_TX_ENA_7(x) ((x) << S_AN_SD25_TX_ENA_7)
77261 #define F_AN_SD25_TX_ENA_7    V_AN_SD25_TX_ENA_7(1U)
77264 #define V_AN_SD25_TX_ENA_6(x) ((x) << S_AN_SD25_TX_ENA_6)
77265 #define F_AN_SD25_TX_ENA_6    V_AN_SD25_TX_ENA_6(1U)
77268 #define V_AN_SD25_TX_ENA_5(x) ((x) << S_AN_SD25_TX_ENA_5)
77269 #define F_AN_SD25_TX_ENA_5    V_AN_SD25_TX_ENA_5(1U)
77272 #define V_AN_SD25_TX_ENA_4(x) ((x) << S_AN_SD25_TX_ENA_4)
77273 #define F_AN_SD25_TX_ENA_4    V_AN_SD25_TX_ENA_4(1U)
77276 #define V_AN_SD25_TX_ENA_3(x) ((x) << S_AN_SD25_TX_ENA_3)
77277 #define F_AN_SD25_TX_ENA_3    V_AN_SD25_TX_ENA_3(1U)
77280 #define V_AN_SD25_TX_ENA_2(x) ((x) << S_AN_SD25_TX_ENA_2)
77281 #define F_AN_SD25_TX_ENA_2    V_AN_SD25_TX_ENA_2(1U)
77284 #define V_AN_SD25_TX_ENA_1(x) ((x) << S_AN_SD25_TX_ENA_1)
77285 #define F_AN_SD25_TX_ENA_1    V_AN_SD25_TX_ENA_1(1U)
77288 #define V_AN_SD25_TX_ENA_0(x) ((x) << S_AN_SD25_TX_ENA_0)
77289 #define F_AN_SD25_TX_ENA_0    V_AN_SD25_TX_ENA_0(1U)
77292 #define V_AN_SD25_RX_ENA_7(x) ((x) << S_AN_SD25_RX_ENA_7)
77293 #define F_AN_SD25_RX_ENA_7    V_AN_SD25_RX_ENA_7(1U)
77296 #define V_AN_SD25_RX_ENA_6(x) ((x) << S_AN_SD25_RX_ENA_6)
77297 #define F_AN_SD25_RX_ENA_6    V_AN_SD25_RX_ENA_6(1U)
77300 #define V_AN_SD25_RX_ENA_5(x) ((x) << S_AN_SD25_RX_ENA_5)
77301 #define F_AN_SD25_RX_ENA_5    V_AN_SD25_RX_ENA_5(1U)
77304 #define V_AN_SD25_RX_ENA_4(x) ((x) << S_AN_SD25_RX_ENA_4)
77305 #define F_AN_SD25_RX_ENA_4    V_AN_SD25_RX_ENA_4(1U)
77308 #define V_AN_SD25_RX_ENA_3(x) ((x) << S_AN_SD25_RX_ENA_3)
77309 #define F_AN_SD25_RX_ENA_3    V_AN_SD25_RX_ENA_3(1U)
77312 #define V_AN_SD25_RX_ENA_2(x) ((x) << S_AN_SD25_RX_ENA_2)
77313 #define F_AN_SD25_RX_ENA_2    V_AN_SD25_RX_ENA_2(1U)
77315 #define S_AN_SD25_RX_ENA_1    1
77316 #define V_AN_SD25_RX_ENA_1(x) ((x) << S_AN_SD25_RX_ENA_1)
77317 #define F_AN_SD25_RX_ENA_1    V_AN_SD25_RX_ENA_1(1U)
77320 #define V_AN_SD25_RX_ENA_0(x) ((x) << S_AN_SD25_RX_ENA_0)
77321 #define F_AN_SD25_RX_ENA_0    V_AN_SD25_RX_ENA_0(1U)
77326 #define V_USE_RX_CDR_CLK_FOR_TX(x) ((x) << S_USE_RX_CDR_CLK_FOR_TX)
77327 #define F_USE_RX_CDR_CLK_FOR_TX    V_USE_RX_CDR_CLK_FOR_TX(1U)
77331 #define V_HSSPLLSEL0(x) ((x) << S_HSSPLLSEL0)
77332 #define G_HSSPLLSEL0(x) (((x) >> S_HSSPLLSEL0) & M_HSSPLLSEL0)
77336 #define V_HSSTXDIV2CLK_SEL0(x) ((x) << S_HSSTXDIV2CLK_SEL0)
77337 #define G_HSSTXDIV2CLK_SEL0(x) (((x) >> S_HSSTXDIV2CLK_SEL0) & M_HSSTXDIV2CLK_SEL0)
77340 #define V_HSS_RESET0(x) ((x) << S_HSS_RESET0)
77341 #define F_HSS_RESET0    V_HSS_RESET0(1U)
77343 #define S_APB_RESET0    1
77344 #define V_APB_RESET0(x) ((x) << S_APB_RESET0)
77345 #define F_APB_RESET0    V_APB_RESET0(1U)
77348 #define V_HSSCLK32DIV2_RESET0(x) ((x) << S_HSSCLK32DIV2_RESET0)
77349 #define F_HSSCLK32DIV2_RESET0    V_HSSCLK32DIV2_RESET0(1U)
77355 #define V_HSSPLLSEL1(x) ((x) << S_HSSPLLSEL1)
77356 #define G_HSSPLLSEL1(x) (((x) >> S_HSSPLLSEL1) & M_HSSPLLSEL1)
77360 #define V_HSSTXDIV2CLK_SEL1(x) ((x) << S_HSSTXDIV2CLK_SEL1)
77361 #define G_HSSTXDIV2CLK_SEL1(x) (((x) >> S_HSSTXDIV2CLK_SEL1) & M_HSSTXDIV2CLK_SEL1)
77364 #define V_HSS_RESET1(x) ((x) << S_HSS_RESET1)
77365 #define F_HSS_RESET1    V_HSS_RESET1(1U)
77367 #define S_APB_RESET1    1
77368 #define V_APB_RESET1(x) ((x) << S_APB_RESET1)
77369 #define F_APB_RESET1    V_APB_RESET1(1U)
77372 #define V_HSSCLK32DIV2_RESET1(x) ((x) << S_HSSCLK32DIV2_RESET1)
77373 #define F_HSSCLK32DIV2_RESET1    V_HSSCLK32DIV2_RESET1(1U)
77379 #define V_HSSPLLSEL2(x) ((x) << S_HSSPLLSEL2)
77380 #define G_HSSPLLSEL2(x) (((x) >> S_HSSPLLSEL2) & M_HSSPLLSEL2)
77384 #define V_HSSTXDIV2CLK_SEL2(x) ((x) << S_HSSTXDIV2CLK_SEL2)
77385 #define G_HSSTXDIV2CLK_SEL2(x) (((x) >> S_HSSTXDIV2CLK_SEL2) & M_HSSTXDIV2CLK_SEL2)
77388 #define V_HSS_RESET2(x) ((x) << S_HSS_RESET2)
77389 #define F_HSS_RESET2    V_HSS_RESET2(1U)
77391 #define S_APB_RESET2    1
77392 #define V_APB_RESET2(x) ((x) << S_APB_RESET2)
77393 #define F_APB_RESET2    V_APB_RESET2(1U)
77396 #define V_HSSCLK32DIV2_RESET2(x) ((x) << S_HSSCLK32DIV2_RESET2)
77397 #define F_HSSCLK32DIV2_RESET2    V_HSSCLK32DIV2_RESET2(1U)
77403 #define V_HSSPLLSEL3(x) ((x) << S_HSSPLLSEL3)
77404 #define G_HSSPLLSEL3(x) (((x) >> S_HSSPLLSEL3) & M_HSSPLLSEL3)
77408 #define V_HSSTXDIV2CLK_SEL3(x) ((x) << S_HSSTXDIV2CLK_SEL3)
77409 #define G_HSSTXDIV2CLK_SEL3(x) (((x) >> S_HSSTXDIV2CLK_SEL3) & M_HSSTXDIV2CLK_SEL3)
77412 #define V_HSS_RESET3(x) ((x) << S_HSS_RESET3)
77413 #define F_HSS_RESET3    V_HSS_RESET3(1U)
77415 #define S_APB_RESET3    1
77416 #define V_APB_RESET3(x) ((x) << S_APB_RESET3)
77417 #define F_APB_RESET3    V_APB_RESET3(1U)
77420 #define V_HSSCLK32DIV2_RESET3(x) ((x) << S_HSSCLK32DIV2_RESET3)
77421 #define F_HSSCLK32DIV2_RESET3    V_HSSCLK32DIV2_RESET3(1U)
77427 #define V_TX_LANE_PLL_SEL_3(x) ((x) << S_TX_LANE_PLL_SEL_3)
77428 #define G_TX_LANE_PLL_SEL_3(x) (((x) >> S_TX_LANE_PLL_SEL_3) & M_TX_LANE_PLL_SEL_3)
77432 #define V_TX_LANE_PLL_SEL_2(x) ((x) << S_TX_LANE_PLL_SEL_2)
77433 #define G_TX_LANE_PLL_SEL_2(x) (((x) >> S_TX_LANE_PLL_SEL_2) & M_TX_LANE_PLL_SEL_2)
77437 #define V_TX_LANE_PLL_SEL_1(x) ((x) << S_TX_LANE_PLL_SEL_1)
77438 #define G_TX_LANE_PLL_SEL_1(x) (((x) >> S_TX_LANE_PLL_SEL_1) & M_TX_LANE_PLL_SEL_1)
77442 #define V_TX_LANE_PLL_SEL_0(x) ((x) << S_TX_LANE_PLL_SEL_0)
77443 #define G_TX_LANE_PLL_SEL_0(x) (((x) >> S_TX_LANE_PLL_SEL_0) & M_TX_LANE_PLL_SEL_0)
77446 #define V_HSSPLLLOCKB_HSS3(x) ((x) << S_HSSPLLLOCKB_HSS3)
77447 #define F_HSSPLLLOCKB_HSS3    V_HSSPLLLOCKB_HSS3(1U)
77450 #define V_HSSPLLLOCKA_HSS3(x) ((x) << S_HSSPLLLOCKA_HSS3)
77451 #define F_HSSPLLLOCKA_HSS3    V_HSSPLLLOCKA_HSS3(1U)
77454 #define V_HSSPLLLOCKB_HSS2(x) ((x) << S_HSSPLLLOCKB_HSS2)
77455 #define F_HSSPLLLOCKB_HSS2    V_HSSPLLLOCKB_HSS2(1U)
77458 #define V_HSSPLLLOCKA_HSS2(x) ((x) << S_HSSPLLLOCKA_HSS2)
77459 #define F_HSSPLLLOCKA_HSS2    V_HSSPLLLOCKA_HSS2(1U)
77462 #define V_HSSPLLLOCKB_HSS1(x) ((x) << S_HSSPLLLOCKB_HSS1)
77463 #define F_HSSPLLLOCKB_HSS1    V_HSSPLLLOCKB_HSS1(1U)
77466 #define V_HSSPLLLOCKA_HSS1(x) ((x) << S_HSSPLLLOCKA_HSS1)
77467 #define F_HSSPLLLOCKA_HSS1    V_HSSPLLLOCKA_HSS1(1U)
77469 #define S_HSSPLLLOCKB_HSS0    1
77470 #define V_HSSPLLLOCKB_HSS0(x) ((x) << S_HSSPLLLOCKB_HSS0)
77471 #define F_HSSPLLLOCKB_HSS0    V_HSSPLLLOCKB_HSS0(1U)
77474 #define V_HSSPLLLOCKA_HSS0(x) ((x) << S_HSSPLLLOCKA_HSS0)
77475 #define F_HSSPLLLOCKA_HSS0    V_HSSPLLLOCKA_HSS0(1U)
77481 #define V_HSS3_SIGDET(x) ((x) << S_HSS3_SIGDET)
77482 #define G_HSS3_SIGDET(x) (((x) >> S_HSS3_SIGDET) & M_HSS3_SIGDET)
77486 #define V_HSS2_SIGDET(x) ((x) << S_HSS2_SIGDET)
77487 #define G_HSS2_SIGDET(x) (((x) >> S_HSS2_SIGDET) & M_HSS2_SIGDET)
77491 #define V_HSS1_SIGDET(x) ((x) << S_HSS1_SIGDET)
77492 #define G_HSS1_SIGDET(x) (((x) >> S_HSS1_SIGDET) & M_HSS1_SIGDET)
77496 #define V_HSS0_SIGDET(x) ((x) << S_HSS0_SIGDET)
77497 #define G_HSS0_SIGDET(x) (((x) >> S_HSS0_SIGDET) & M_HSS0_SIGDET)
77504 #define V_SIGNAL_DETECT(x) ((x) << S_SIGNAL_DETECT)
77505 #define G_SIGNAL_DETECT(x) (((x) >> S_SIGNAL_DETECT) & M_SIGNAL_DETECT)
77511 #define V_AN3_RATE_SELECT(x) ((x) << S_AN3_RATE_SELECT)
77512 #define G_AN3_RATE_SELECT(x) (((x) >> S_AN3_RATE_SELECT) & M_AN3_RATE_SELECT)
77515 #define V_AN3_STATUS(x) ((x) << S_AN3_STATUS)
77516 #define F_AN3_STATUS    V_AN3_STATUS(1U)
77520 #define V_AN2_RATE_SELECT(x) ((x) << S_AN2_RATE_SELECT)
77521 #define G_AN2_RATE_SELECT(x) (((x) >> S_AN2_RATE_SELECT) & M_AN2_RATE_SELECT)
77524 #define V_AN2_STATUS(x) ((x) << S_AN2_STATUS)
77525 #define F_AN2_STATUS    V_AN2_STATUS(1U)
77529 #define V_AN1_RATE_SELECT(x) ((x) << S_AN1_RATE_SELECT)
77530 #define G_AN1_RATE_SELECT(x) (((x) >> S_AN1_RATE_SELECT) & M_AN1_RATE_SELECT)
77533 #define V_AN1_STATUS(x) ((x) << S_AN1_STATUS)
77534 #define F_AN1_STATUS    V_AN1_STATUS(1U)
77536 #define S_AN0_RATE_SELECT    1
77538 #define V_AN0_RATE_SELECT(x) ((x) << S_AN0_RATE_SELECT)
77539 #define G_AN0_RATE_SELECT(x) (((x) >> S_AN0_RATE_SELECT) & M_AN0_RATE_SELECT)
77542 #define V_AN0_STATUS(x) ((x) << S_AN0_STATUS)
77543 #define F_AN0_STATUS    V_AN0_STATUS(1U)
77549 #define V_AN7_RATE_SELECT(x) ((x) << S_AN7_RATE_SELECT)
77550 #define G_AN7_RATE_SELECT(x) (((x) >> S_AN7_RATE_SELECT) & M_AN7_RATE_SELECT)
77553 #define V_AN7_STATUS(x) ((x) << S_AN7_STATUS)
77554 #define F_AN7_STATUS    V_AN7_STATUS(1U)
77558 #define V_AN6_RATE_SELECT(x) ((x) << S_AN6_RATE_SELECT)
77559 #define G_AN6_RATE_SELECT(x) (((x) >> S_AN6_RATE_SELECT) & M_AN6_RATE_SELECT)
77562 #define V_AN6_STATUS(x) ((x) << S_AN6_STATUS)
77563 #define F_AN6_STATUS    V_AN6_STATUS(1U)
77567 #define V_AN5_RATE_SELECT(x) ((x) << S_AN5_RATE_SELECT)
77568 #define G_AN5_RATE_SELECT(x) (((x) >> S_AN5_RATE_SELECT) & M_AN5_RATE_SELECT)
77571 #define V_AN5_STATUS(x) ((x) << S_AN5_STATUS)
77572 #define F_AN5_STATUS    V_AN5_STATUS(1U)
77574 #define S_AN4_RATE_SELECT    1
77576 #define V_AN4_RATE_SELECT(x) ((x) << S_AN4_RATE_SELECT)
77577 #define G_AN4_RATE_SELECT(x) (((x) >> S_AN4_RATE_SELECT) & M_AN4_RATE_SELECT)
77580 #define V_AN4_STATUS(x) ((x) << S_AN4_STATUS)
77581 #define F_AN4_STATUS    V_AN4_STATUS(1U)
77586 #define V_HSS3PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_EN)
77587 #define F_HSS3PLL1_LOCK_LOST_INT_EN    V_HSS3PLL1_LOCK_LOST_INT_EN(1U)
77590 #define V_HSS3PLL1_LOCK_INT_EN(x) ((x) << S_HSS3PLL1_LOCK_INT_EN)
77591 #define F_HSS3PLL1_LOCK_INT_EN    V_HSS3PLL1_LOCK_INT_EN(1U)
77594 #define V_HSS3PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_EN)
77595 #define F_HSS3PLL0_LOCK_LOST_INT_EN    V_HSS3PLL0_LOCK_LOST_INT_EN(1U)
77598 #define V_HSS3PLL0_LOCK_INT_EN(x) ((x) << S_HSS3PLL0_LOCK_INT_EN)
77599 #define F_HSS3PLL0_LOCK_INT_EN    V_HSS3PLL0_LOCK_INT_EN(1U)
77602 #define V_HSS2PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_LOST_INT_EN)
77603 #define F_HSS2PLL1_LOCK_LOST_INT_EN    V_HSS2PLL1_LOCK_LOST_INT_EN(1U)
77606 #define V_HSS2PLL1_LOCK_INT_EN(x) ((x) << S_HSS2PLL1_LOCK_INT_EN)
77607 #define F_HSS2PLL1_LOCK_INT_EN    V_HSS2PLL1_LOCK_INT_EN(1U)
77610 #define V_HSS2PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_EN)
77611 #define F_HSS2PLL0_LOCK_LOST_INT_EN    V_HSS2PLL0_LOCK_LOST_INT_EN(1U)
77614 #define V_HSS2PLL0_LOCK_INT_EN(x) ((x) << S_HSS2PLL0_LOCK_INT_EN)
77615 #define F_HSS2PLL0_LOCK_INT_EN    V_HSS2PLL0_LOCK_INT_EN(1U)
77618 #define V_HSS1PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_EN)
77619 #define F_HSS1PLL1_LOCK_LOST_INT_EN    V_HSS1PLL1_LOCK_LOST_INT_EN(1U)
77622 #define V_HSS1PLL1_LOCK_INT_EN(x) ((x) << S_HSS1PLL1_LOCK_INT_EN)
77623 #define F_HSS1PLL1_LOCK_INT_EN    V_HSS1PLL1_LOCK_INT_EN(1U)
77626 #define V_HSS1PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_EN)
77627 #define F_HSS1PLL0_LOCK_LOST_INT_EN    V_HSS1PLL0_LOCK_LOST_INT_EN(1U)
77630 #define V_HSS1PLL0_LOCK_INT_EN(x) ((x) << S_HSS1PLL0_LOCK_INT_EN)
77631 #define F_HSS1PLL0_LOCK_INT_EN    V_HSS1PLL0_LOCK_INT_EN(1U)
77634 #define V_HSS0PLL1_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_EN)
77635 #define F_HSS0PLL1_LOCK_LOST_INT_EN    V_HSS0PLL1_LOCK_LOST_INT_EN(1U)
77638 #define V_HSS0PLL1_LOCK_INT_EN(x) ((x) << S_HSS0PLL1_LOCK_INT_EN)
77639 #define F_HSS0PLL1_LOCK_INT_EN    V_HSS0PLL1_LOCK_INT_EN(1U)
77642 #define V_HSS0PLL0_LOCK_LOST_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_EN)
77643 #define F_HSS0PLL0_LOCK_LOST_INT_EN    V_HSS0PLL0_LOCK_LOST_INT_EN(1U)
77646 #define V_HSS0PLL0_LOCK_INT_EN(x) ((x) << S_HSS0PLL0_LOCK_INT_EN)
77647 #define F_HSS0PLL0_LOCK_INT_EN    V_HSS0PLL0_LOCK_INT_EN(1U)
77650 #define V_FLOCK_ASSERTED(x) ((x) << S_FLOCK_ASSERTED)
77651 #define F_FLOCK_ASSERTED    V_FLOCK_ASSERTED(1U)
77654 #define V_FLOCK_LOST(x) ((x) << S_FLOCK_LOST)
77655 #define F_FLOCK_LOST    V_FLOCK_LOST(1U)
77658 #define V_PHASE_LOCK_ASSERTED(x) ((x) << S_PHASE_LOCK_ASSERTED)
77659 #define F_PHASE_LOCK_ASSERTED    V_PHASE_LOCK_ASSERTED(1U)
77662 #define V_PHASE_LOCK_LOST(x) ((x) << S_PHASE_LOCK_LOST)
77663 #define F_PHASE_LOCK_LOST    V_PHASE_LOCK_LOST(1U)
77665 #define S_LOCK_ASSERTED    1
77666 #define V_LOCK_ASSERTED(x) ((x) << S_LOCK_ASSERTED)
77667 #define F_LOCK_ASSERTED    V_LOCK_ASSERTED(1U)
77670 #define V_LOCK_LOST(x) ((x) << S_LOCK_LOST)
77671 #define F_LOCK_LOST    V_LOCK_LOST(1U)
77676 #define V_HSS3PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_LOST_INT_CAUSE)
77677 #define F_HSS3PLL1_LOCK_LOST_INT_CAUSE    V_HSS3PLL1_LOCK_LOST_INT_CAUSE(1U)
77680 #define V_HSS3PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL1_LOCK_INT_CAUSE)
77681 #define F_HSS3PLL1_LOCK_INT_CAUSE    V_HSS3PLL1_LOCK_INT_CAUSE(1U)
77684 #define V_HSS3PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_LOST_INT_CAUSE)
77685 #define F_HSS3PLL0_LOCK_LOST_INT_CAUSE    V_HSS3PLL0_LOCK_LOST_INT_CAUSE(1U)
77688 #define V_HSS3PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS3PLL0_LOCK_INT_CAUSE)
77689 #define F_HSS3PLL0_LOCK_INT_CAUSE    V_HSS3PLL0_LOCK_INT_CAUSE(1U)
77692 #define V_HSS2PLL1_LOCK_LOST_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_LOST_CAUSE)
77693 #define F_HSS2PLL1_LOCK_LOST_CAUSE    V_HSS2PLL1_LOCK_LOST_CAUSE(1U)
77696 #define V_HSS2PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL1_LOCK_INT_CAUSE)
77697 #define F_HSS2PLL1_LOCK_INT_CAUSE    V_HSS2PLL1_LOCK_INT_CAUSE(1U)
77700 #define V_HSS2PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_LOST_INT_CAUSE)
77701 #define F_HSS2PLL0_LOCK_LOST_INT_CAUSE    V_HSS2PLL0_LOCK_LOST_INT_CAUSE(1U)
77704 #define V_HSS2PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS2PLL0_LOCK_INT_CAUSE)
77705 #define F_HSS2PLL0_LOCK_INT_CAUSE    V_HSS2PLL0_LOCK_INT_CAUSE(1U)
77708 #define V_HSS1PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_LOST_INT_CAUSE)
77709 #define F_HSS1PLL1_LOCK_LOST_INT_CAUSE    V_HSS1PLL1_LOCK_LOST_INT_CAUSE(1U)
77712 #define V_HSS1PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL1_LOCK_INT_CAUSE)
77713 #define F_HSS1PLL1_LOCK_INT_CAUSE    V_HSS1PLL1_LOCK_INT_CAUSE(1U)
77716 #define V_HSS1PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_LOST_INT_CAUSE)
77717 #define F_HSS1PLL0_LOCK_LOST_INT_CAUSE    V_HSS1PLL0_LOCK_LOST_INT_CAUSE(1U)
77720 #define V_HSS1PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS1PLL0_LOCK_INT_CAUSE)
77721 #define F_HSS1PLL0_LOCK_INT_CAUSE    V_HSS1PLL0_LOCK_INT_CAUSE(1U)
77724 #define V_HSS0PLL1_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_LOST_INT_CAUSE)
77725 #define F_HSS0PLL1_LOCK_LOST_INT_CAUSE    V_HSS0PLL1_LOCK_LOST_INT_CAUSE(1U)
77728 #define V_HSS0PLL1_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL1_LOCK_INT_CAUSE)
77729 #define F_HSS0PLL1_LOCK_INT_CAUSE    V_HSS0PLL1_LOCK_INT_CAUSE(1U)
77732 #define V_HSS0PLL0_LOCK_LOST_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_LOST_INT_CAUSE)
77733 #define F_HSS0PLL0_LOCK_LOST_INT_CAUSE    V_HSS0PLL0_LOCK_LOST_INT_CAUSE(1U)
77736 #define V_HSS0PLL0_LOCK_INT_CAUSE(x) ((x) << S_HSS0PLL0_LOCK_INT_CAUSE)
77737 #define F_HSS0PLL0_LOCK_INT_CAUSE    V_HSS0PLL0_LOCK_INT_CAUSE(1U)
77742 #define V_PERR_MAC0_TX(x) ((x) << S_PERR_MAC0_TX)
77743 #define F_PERR_MAC0_TX    V_PERR_MAC0_TX(1U)
77746 #define V_PERR_MAC1_TX(x) ((x) << S_PERR_MAC1_TX)
77747 #define F_PERR_MAC1_TX    V_PERR_MAC1_TX(1U)
77750 #define V_PERR_MAC2_TX(x) ((x) << S_PERR_MAC2_TX)
77751 #define F_PERR_MAC2_TX    V_PERR_MAC2_TX(1U)
77754 #define V_PERR_MAC3_TX(x) ((x) << S_PERR_MAC3_TX)
77755 #define F_PERR_MAC3_TX    V_PERR_MAC3_TX(1U)
77758 #define V_PERR_MAC4_TX(x) ((x) << S_PERR_MAC4_TX)
77759 #define F_PERR_MAC4_TX    V_PERR_MAC4_TX(1U)
77762 #define V_PERR_MAC5_TX(x) ((x) << S_PERR_MAC5_TX)
77763 #define F_PERR_MAC5_TX    V_PERR_MAC5_TX(1U)
77766 #define V_PERR_MAC0_RX(x) ((x) << S_PERR_MAC0_RX)
77767 #define F_PERR_MAC0_RX    V_PERR_MAC0_RX(1U)
77770 #define V_PERR_MAC1_RX(x) ((x) << S_PERR_MAC1_RX)
77771 #define F_PERR_MAC1_RX    V_PERR_MAC1_RX(1U)
77774 #define V_PERR_MAC2_RX(x) ((x) << S_PERR_MAC2_RX)
77775 #define F_PERR_MAC2_RX    V_PERR_MAC2_RX(1U)
77778 #define V_PERR_MAC3_RX(x) ((x) << S_PERR_MAC3_RX)
77779 #define F_PERR_MAC3_RX    V_PERR_MAC3_RX(1U)
77782 #define V_PERR_MAC4_RX(x) ((x) << S_PERR_MAC4_RX)
77783 #define F_PERR_MAC4_RX    V_PERR_MAC4_RX(1U)
77786 #define V_PERR_MAC5_RX(x) ((x) << S_PERR_MAC5_RX)
77787 #define F_PERR_MAC5_RX    V_PERR_MAC5_RX(1U)
77790 #define V_PERR_MAC_STAT2_RX(x) ((x) << S_PERR_MAC_STAT2_RX)
77791 #define F_PERR_MAC_STAT2_RX    V_PERR_MAC_STAT2_RX(1U)
77794 #define V_PERR_MAC_STAT3_RX(x) ((x) << S_PERR_MAC_STAT3_RX)
77795 #define F_PERR_MAC_STAT3_RX    V_PERR_MAC_STAT3_RX(1U)
77798 #define V_PERR_MAC_STAT4_RX(x) ((x) << S_PERR_MAC_STAT4_RX)
77799 #define F_PERR_MAC_STAT4_RX    V_PERR_MAC_STAT4_RX(1U)
77802 #define V_PERR_MAC_STAT5_RX(x) ((x) << S_PERR_MAC_STAT5_RX)
77803 #define F_PERR_MAC_STAT5_RX    V_PERR_MAC_STAT5_RX(1U)
77806 #define V_PERR_MAC_STAT2_TX(x) ((x) << S_PERR_MAC_STAT2_TX)
77807 #define F_PERR_MAC_STAT2_TX    V_PERR_MAC_STAT2_TX(1U)
77810 #define V_PERR_MAC_STAT3_TX(x) ((x) << S_PERR_MAC_STAT3_TX)
77811 #define F_PERR_MAC_STAT3_TX    V_PERR_MAC_STAT3_TX(1U)
77813 #define S_PERR_MAC_STAT4_TX    1
77814 #define V_PERR_MAC_STAT4_TX(x) ((x) << S_PERR_MAC_STAT4_TX)
77815 #define F_PERR_MAC_STAT4_TX    V_PERR_MAC_STAT4_TX(1U)
77818 #define V_PERR_MAC_STAT5_TX(x) ((x) << S_PERR_MAC_STAT5_TX)
77819 #define F_PERR_MAC_STAT5_TX    V_PERR_MAC_STAT5_TX(1U)
77824 #define V_PERR_MAC_STAT_RX(x) ((x) << S_PERR_MAC_STAT_RX)
77825 #define F_PERR_MAC_STAT_RX    V_PERR_MAC_STAT_RX(1U)
77828 #define V_PERR_MAC_STAT_TX(x) ((x) << S_PERR_MAC_STAT_TX)
77829 #define F_PERR_MAC_STAT_TX    V_PERR_MAC_STAT_TX(1U)
77832 #define V_PERR_MAC_STAT_CAP(x) ((x) << S_PERR_MAC_STAT_CAP)
77833 #define F_PERR_MAC_STAT_CAP    V_PERR_MAC_STAT_CAP(1U)
77839 #define V_SEQ_ENA_3(x) ((x) << S_SEQ_ENA_3)
77840 #define F_SEQ_ENA_3    V_SEQ_ENA_3(1U)
77843 #define V_SEQ_ENA_2(x) ((x) << S_SEQ_ENA_2)
77844 #define F_SEQ_ENA_2    V_SEQ_ENA_2(1U)
77847 #define V_SEQ_ENA_1(x) ((x) << S_SEQ_ENA_1)
77848 #define F_SEQ_ENA_1    V_SEQ_ENA_1(1U)
77851 #define V_SEQ_ENA_0(x) ((x) << S_SEQ_ENA_0)
77852 #define F_SEQ_ENA_0    V_SEQ_ENA_0(1U)
77856 #define V_TX_LANE_THRESH_3(x) ((x) << S_TX_LANE_THRESH_3)
77857 #define G_TX_LANE_THRESH_3(x) (((x) >> S_TX_LANE_THRESH_3) & M_TX_LANE_THRESH_3)
77861 #define V_TX_LANE_THRESH_2(x) ((x) << S_TX_LANE_THRESH_2)
77862 #define G_TX_LANE_THRESH_2(x) (((x) >> S_TX_LANE_THRESH_2) & M_TX_LANE_THRESH_2)
77866 #define V_TX_LANE_THRESH_1(x) ((x) << S_TX_LANE_THRESH_1)
77867 #define G_TX_LANE_THRESH_1(x) (((x) >> S_TX_LANE_THRESH_1) & M_TX_LANE_THRESH_1)
77871 #define V_TX_LANE_THRESH_0(x) ((x) << S_TX_LANE_THRESH_0)
77872 #define G_TX_LANE_THRESH_0(x) (((x) >> S_TX_LANE_THRESH_0) & M_TX_LANE_THRESH_0)
77878 #define V_TX_LANE_CKMULT_3(x) ((x) << S_TX_LANE_CKMULT_3)
77879 #define G_TX_LANE_CKMULT_3(x) (((x) >> S_TX_LANE_CKMULT_3) & M_TX_LANE_CKMULT_3)
77883 #define V_TX_LANE_CKMULT_2(x) ((x) << S_TX_LANE_CKMULT_2)
77884 #define G_TX_LANE_CKMULT_2(x) (((x) >> S_TX_LANE_CKMULT_2) & M_TX_LANE_CKMULT_2)
77888 #define V_TX_LANE_CKMULT_1(x) ((x) << S_TX_LANE_CKMULT_1)
77889 #define G_TX_LANE_CKMULT_1(x) (((x) >> S_TX_LANE_CKMULT_1) & M_TX_LANE_CKMULT_1)
77893 #define V_TX_LANE_CKMULT_0(x) ((x) << S_TX_LANE_CKMULT_0)
77894 #define G_TX_LANE_CKMULT_0(x) (((x) >> S_TX_LANE_CKMULT_0) & M_TX_LANE_CKMULT_0)
77919 #define S_STSOUTSEL    1
77920 #define V_STSOUTSEL(x) ((x) << S_STSOUTSEL)
77921 #define F_STSOUTSEL    V_STSOUTSEL(1U)
77924 #define V_STSINSEL(x) ((x) << S_STSINSEL)
77925 #define F_STSINSEL    V_STSINSEL(1U)
77930 #define V_CERR_MAC0_TX(x) ((x) << S_CERR_MAC0_TX)
77931 #define F_CERR_MAC0_TX    V_CERR_MAC0_TX(1U)
77934 #define V_CERR_MAC1_TX(x) ((x) << S_CERR_MAC1_TX)
77935 #define F_CERR_MAC1_TX    V_CERR_MAC1_TX(1U)
77938 #define V_CERR_MAC2_TX(x) ((x) << S_CERR_MAC2_TX)
77939 #define F_CERR_MAC2_TX    V_CERR_MAC2_TX(1U)
77942 #define V_CERR_MAC3_TX(x) ((x) << S_CERR_MAC3_TX)
77943 #define F_CERR_MAC3_TX    V_CERR_MAC3_TX(1U)
77946 #define V_CERR_MAC4_TX(x) ((x) << S_CERR_MAC4_TX)
77947 #define F_CERR_MAC4_TX    V_CERR_MAC4_TX(1U)
77950 #define V_CERR_MAC5_TX(x) ((x) << S_CERR_MAC5_TX)
77951 #define F_CERR_MAC5_TX    V_CERR_MAC5_TX(1U)
77954 #define V_CERR_MAC0_RX(x) ((x) << S_CERR_MAC0_RX)
77955 #define F_CERR_MAC0_RX    V_CERR_MAC0_RX(1U)
77958 #define V_CERR_MAC1_RX(x) ((x) << S_CERR_MAC1_RX)
77959 #define F_CERR_MAC1_RX    V_CERR_MAC1_RX(1U)
77962 #define V_CERR_MAC2_RX(x) ((x) << S_CERR_MAC2_RX)
77963 #define F_CERR_MAC2_RX    V_CERR_MAC2_RX(1U)
77966 #define V_CERR_MAC3_RX(x) ((x) << S_CERR_MAC3_RX)
77967 #define F_CERR_MAC3_RX    V_CERR_MAC3_RX(1U)
77969 #define S_CERR_MAC4_RX    1
77970 #define V_CERR_MAC4_RX(x) ((x) << S_CERR_MAC4_RX)
77971 #define F_CERR_MAC4_RX    V_CERR_MAC4_RX(1U)
77974 #define V_CERR_MAC5_RX(x) ((x) << S_CERR_MAC5_RX)
77975 #define F_CERR_MAC5_RX    V_CERR_MAC5_RX(1U)
77981 #define V_1G_PCS0_LOOPBACK(x) ((x) << S_1G_PCS0_LOOPBACK)
77982 #define F_1G_PCS0_LOOPBACK    V_1G_PCS0_LOOPBACK(1U)
77985 #define V_1G_PCS0_LINK_STATUS(x) ((x) << S_1G_PCS0_LINK_STATUS)
77986 #define F_1G_PCS0_LINK_STATUS    V_1G_PCS0_LINK_STATUS(1U)
77989 #define V_1G_PCS0_RX_SYNC(x) ((x) << S_1G_PCS0_RX_SYNC)
77990 #define F_1G_PCS0_RX_SYNC    V_1G_PCS0_RX_SYNC(1U)
77993 #define V_1G_PCS0_AN_DONE(x) ((x) << S_1G_PCS0_AN_DONE)
77994 #define F_1G_PCS0_AN_DONE    V_1G_PCS0_AN_DONE(1U)
77997 #define V_1G_PCS0_PGRCVD(x) ((x) << S_1G_PCS0_PGRCVD)
77998 #define F_1G_PCS0_PGRCVD    V_1G_PCS0_PGRCVD(1U)
78002 #define V_1G_PCS0_SPEED_SEL(x) ((x) << S_1G_PCS0_SPEED_SEL)
78003 #define G_1G_PCS0_SPEED_SEL(x) (((x) >> S_1G_PCS0_SPEED_SEL) & M_1G_PCS0_SPEED_SEL)
78006 #define V_1G_PCS0_HALF_DUPLEX(x) ((x) << S_1G_PCS0_HALF_DUPLEX)
78007 #define F_1G_PCS0_HALF_DUPLEX    V_1G_PCS0_HALF_DUPLEX(1U)
78010 #define V_1G_PCS0_TX_MODE_QUIET(x) ((x) << S_1G_PCS0_TX_MODE_QUIET)
78011 #define F_1G_PCS0_TX_MODE_QUIET    V_1G_PCS0_TX_MODE_QUIET(1U)
78014 #define V_1G_PCS0_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_TX_LPI_ACTIVE)
78015 #define F_1G_PCS0_TX_LPI_ACTIVE    V_1G_PCS0_TX_LPI_ACTIVE(1U)
78018 #define V_1G_PCS0_RX_MODE_QUIET(x) ((x) << S_1G_PCS0_RX_MODE_QUIET)
78019 #define F_1G_PCS0_RX_MODE_QUIET    V_1G_PCS0_RX_MODE_QUIET(1U)
78021 #define S_1G_PCS0_RX_LPI_ACTIVE    1
78022 #define V_1G_PCS0_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS0_RX_LPI_ACTIVE)
78023 #define F_1G_PCS0_RX_LPI_ACTIVE    V_1G_PCS0_RX_LPI_ACTIVE(1U)
78026 #define V_1G_PCS0_RX_WAKE_ERR(x) ((x) << S_1G_PCS0_RX_WAKE_ERR)
78027 #define F_1G_PCS0_RX_WAKE_ERR    V_1G_PCS0_RX_WAKE_ERR(1U)
78032 #define V_1G_PCS1_LOOPBACK(x) ((x) << S_1G_PCS1_LOOPBACK)
78033 #define F_1G_PCS1_LOOPBACK    V_1G_PCS1_LOOPBACK(1U)
78036 #define V_1G_PCS1_LINK_STATUS(x) ((x) << S_1G_PCS1_LINK_STATUS)
78037 #define F_1G_PCS1_LINK_STATUS    V_1G_PCS1_LINK_STATUS(1U)
78040 #define V_1G_PCS1_RX_SYNC(x) ((x) << S_1G_PCS1_RX_SYNC)
78041 #define F_1G_PCS1_RX_SYNC    V_1G_PCS1_RX_SYNC(1U)
78044 #define V_1G_PCS1_AN_DONE(x) ((x) << S_1G_PCS1_AN_DONE)
78045 #define F_1G_PCS1_AN_DONE    V_1G_PCS1_AN_DONE(1U)
78048 #define V_1G_PCS1_PGRCVD(x) ((x) << S_1G_PCS1_PGRCVD)
78049 #define F_1G_PCS1_PGRCVD    V_1G_PCS1_PGRCVD(1U)
78053 #define V_1G_PCS1_SPEED_SEL(x) ((x) << S_1G_PCS1_SPEED_SEL)
78054 #define G_1G_PCS1_SPEED_SEL(x) (((x) >> S_1G_PCS1_SPEED_SEL) & M_1G_PCS1_SPEED_SEL)
78057 #define V_1G_PCS1_HALF_DUPLEX(x) ((x) << S_1G_PCS1_HALF_DUPLEX)
78058 #define F_1G_PCS1_HALF_DUPLEX    V_1G_PCS1_HALF_DUPLEX(1U)
78061 #define V_1G_PCS1_TX_MODE_QUIET(x) ((x) << S_1G_PCS1_TX_MODE_QUIET)
78062 #define F_1G_PCS1_TX_MODE_QUIET    V_1G_PCS1_TX_MODE_QUIET(1U)
78065 #define V_1G_PCS1_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_TX_LPI_ACTIVE)
78066 #define F_1G_PCS1_TX_LPI_ACTIVE    V_1G_PCS1_TX_LPI_ACTIVE(1U)
78069 #define V_1G_PCS1_RX_MODE_QUIET(x) ((x) << S_1G_PCS1_RX_MODE_QUIET)
78070 #define F_1G_PCS1_RX_MODE_QUIET    V_1G_PCS1_RX_MODE_QUIET(1U)
78072 #define S_1G_PCS1_RX_LPI_ACTIVE    1
78073 #define V_1G_PCS1_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS1_RX_LPI_ACTIVE)
78074 #define F_1G_PCS1_RX_LPI_ACTIVE    V_1G_PCS1_RX_LPI_ACTIVE(1U)
78077 #define V_1G_PCS1_RX_WAKE_ERR(x) ((x) << S_1G_PCS1_RX_WAKE_ERR)
78078 #define F_1G_PCS1_RX_WAKE_ERR    V_1G_PCS1_RX_WAKE_ERR(1U)
78083 #define V_1G_PCS2_LOOPBACK(x) ((x) << S_1G_PCS2_LOOPBACK)
78084 #define F_1G_PCS2_LOOPBACK    V_1G_PCS2_LOOPBACK(1U)
78087 #define V_1G_PCS2_LINK_STATUS(x) ((x) << S_1G_PCS2_LINK_STATUS)
78088 #define F_1G_PCS2_LINK_STATUS    V_1G_PCS2_LINK_STATUS(1U)
78091 #define V_1G_PCS2_RX_SYNC(x) ((x) << S_1G_PCS2_RX_SYNC)
78092 #define F_1G_PCS2_RX_SYNC    V_1G_PCS2_RX_SYNC(1U)
78095 #define V_1G_PCS2_AN_DONE(x) ((x) << S_1G_PCS2_AN_DONE)
78096 #define F_1G_PCS2_AN_DONE    V_1G_PCS2_AN_DONE(1U)
78099 #define V_1G_PCS2_PGRCVD(x) ((x) << S_1G_PCS2_PGRCVD)
78100 #define F_1G_PCS2_PGRCVD    V_1G_PCS2_PGRCVD(1U)
78104 #define V_1G_PCS2_SPEED_SEL(x) ((x) << S_1G_PCS2_SPEED_SEL)
78105 #define G_1G_PCS2_SPEED_SEL(x) (((x) >> S_1G_PCS2_SPEED_SEL) & M_1G_PCS2_SPEED_SEL)
78108 #define V_1G_PCS2_HALF_DUPLEX(x) ((x) << S_1G_PCS2_HALF_DUPLEX)
78109 #define F_1G_PCS2_HALF_DUPLEX    V_1G_PCS2_HALF_DUPLEX(1U)
78112 #define V_1G_PCS2_TX_MODE_QUIET(x) ((x) << S_1G_PCS2_TX_MODE_QUIET)
78113 #define F_1G_PCS2_TX_MODE_QUIET    V_1G_PCS2_TX_MODE_QUIET(1U)
78116 #define V_1G_PCS2_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_TX_LPI_ACTIVE)
78117 #define F_1G_PCS2_TX_LPI_ACTIVE    V_1G_PCS2_TX_LPI_ACTIVE(1U)
78120 #define V_1G_PCS2_RX_MODE_QUIET(x) ((x) << S_1G_PCS2_RX_MODE_QUIET)
78121 #define F_1G_PCS2_RX_MODE_QUIET    V_1G_PCS2_RX_MODE_QUIET(1U)
78123 #define S_1G_PCS2_RX_LPI_ACTIVE    1
78124 #define V_1G_PCS2_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS2_RX_LPI_ACTIVE)
78125 #define F_1G_PCS2_RX_LPI_ACTIVE    V_1G_PCS2_RX_LPI_ACTIVE(1U)
78128 #define V_1G_PCS2_RX_WAKE_ERR(x) ((x) << S_1G_PCS2_RX_WAKE_ERR)
78129 #define F_1G_PCS2_RX_WAKE_ERR    V_1G_PCS2_RX_WAKE_ERR(1U)
78134 #define V_1G_PCS3_LOOPBACK(x) ((x) << S_1G_PCS3_LOOPBACK)
78135 #define F_1G_PCS3_LOOPBACK    V_1G_PCS3_LOOPBACK(1U)
78138 #define V_1G_PCS3_LINK_STATUS(x) ((x) << S_1G_PCS3_LINK_STATUS)
78139 #define F_1G_PCS3_LINK_STATUS    V_1G_PCS3_LINK_STATUS(1U)
78142 #define V_1G_PCS3_RX_SYNC(x) ((x) << S_1G_PCS3_RX_SYNC)
78143 #define F_1G_PCS3_RX_SYNC    V_1G_PCS3_RX_SYNC(1U)
78146 #define V_1G_PCS3_AN_DONE(x) ((x) << S_1G_PCS3_AN_DONE)
78147 #define F_1G_PCS3_AN_DONE    V_1G_PCS3_AN_DONE(1U)
78150 #define V_1G_PCS3_PGRCVD(x) ((x) << S_1G_PCS3_PGRCVD)
78151 #define F_1G_PCS3_PGRCVD    V_1G_PCS3_PGRCVD(1U)
78155 #define V_1G_PCS3_SPEED_SEL(x) ((x) << S_1G_PCS3_SPEED_SEL)
78156 #define G_1G_PCS3_SPEED_SEL(x) (((x) >> S_1G_PCS3_SPEED_SEL) & M_1G_PCS3_SPEED_SEL)
78159 #define V_1G_PCS3_HALF_DUPLEX(x) ((x) << S_1G_PCS3_HALF_DUPLEX)
78160 #define F_1G_PCS3_HALF_DUPLEX    V_1G_PCS3_HALF_DUPLEX(1U)
78163 #define V_1G_PCS3_TX_MODE_QUIET(x) ((x) << S_1G_PCS3_TX_MODE_QUIET)
78164 #define F_1G_PCS3_TX_MODE_QUIET    V_1G_PCS3_TX_MODE_QUIET(1U)
78167 #define V_1G_PCS3_TX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_TX_LPI_ACTIVE)
78168 #define F_1G_PCS3_TX_LPI_ACTIVE    V_1G_PCS3_TX_LPI_ACTIVE(1U)
78171 #define V_1G_PCS3_RX_MODE_QUIET(x) ((x) << S_1G_PCS3_RX_MODE_QUIET)
78172 #define F_1G_PCS3_RX_MODE_QUIET    V_1G_PCS3_RX_MODE_QUIET(1U)
78174 #define S_1G_PCS3_RX_LPI_ACTIVE    1
78175 #define V_1G_PCS3_RX_LPI_ACTIVE(x) ((x) << S_1G_PCS3_RX_LPI_ACTIVE)
78176 #define F_1G_PCS3_RX_LPI_ACTIVE    V_1G_PCS3_RX_LPI_ACTIVE(1U)
78179 #define V_1G_PCS3_RX_WAKE_ERR(x) ((x) << S_1G_PCS3_RX_WAKE_ERR)
78180 #define F_1G_PCS3_RX_WAKE_ERR    V_1G_PCS3_RX_WAKE_ERR(1U)
78186 #define V_TX_LPI_STATE(x) ((x) << S_TX_LPI_STATE)
78187 #define G_TX_LPI_STATE(x) (((x) >> S_TX_LPI_STATE) & M_TX_LPI_STATE)
78193 #define V_TX_LPI_MODE(x) ((x) << S_TX_LPI_MODE)
78194 #define G_TX_LPI_MODE(x) (((x) >> S_TX_LPI_MODE) & M_TX_LPI_MODE)
78200 #define V_RX_LPI_MODE(x) ((x) << S_RX_LPI_MODE)
78201 #define G_RX_LPI_MODE(x) (((x) >> S_RX_LPI_MODE) & M_RX_LPI_MODE)
78205 #define V_RX_LPI_STATE(x) ((x) << S_RX_LPI_STATE)
78206 #define G_RX_LPI_STATE(x) (((x) >> S_RX_LPI_STATE) & M_RX_LPI_STATE)
78212 #define V_T7_RX_LPI_ACTIVE(x) ((x) << S_T7_RX_LPI_ACTIVE)
78213 #define G_T7_RX_LPI_ACTIVE(x) (((x) >> S_T7_RX_LPI_ACTIVE) & M_T7_RX_LPI_ACTIVE)
78234 #define V_CML_MUX_SEL(x) ((x) << S_CML_MUX_SEL)
78235 #define F_CML_MUX_SEL    V_CML_MUX_SEL(1U)
78238 #define V_CMOS_OUT_EN(x) ((x) << S_CMOS_OUT_EN)
78239 #define F_CMOS_OUT_EN    V_CMOS_OUT_EN(1U)
78242 #define V_CML_OUT_EN(x) ((x) << S_CML_OUT_EN)
78243 #define F_CML_OUT_EN    V_CML_OUT_EN(1U)
78247 #define V_LOC_FAULT_PORT_SEL(x) ((x) << S_LOC_FAULT_PORT_SEL)
78248 #define G_LOC_FAULT_PORT_SEL(x) (((x) >> S_LOC_FAULT_PORT_SEL) & M_LOC_FAULT_PORT_SEL)
78252 #define V_TX_CDR_LANE_SEL(x) ((x) << S_TX_CDR_LANE_SEL)
78253 #define G_TX_CDR_LANE_SEL(x) (((x) >> S_TX_CDR_LANE_SEL) & M_TX_CDR_LANE_SEL)
78257 #define V_RX_CDR_LANE_SEL(x) ((x) << S_RX_CDR_LANE_SEL)
78258 #define G_RX_CDR_LANE_SEL(x) (((x) >> S_RX_CDR_LANE_SEL) & M_RX_CDR_LANE_SEL)
78264 #define V_SIGNAL_DET_LN7(x) ((x) << S_SIGNAL_DET_LN7)
78265 #define F_SIGNAL_DET_LN7    V_SIGNAL_DET_LN7(1U)
78268 #define V_SIGNAL_DET_LN6(x) ((x) << S_SIGNAL_DET_LN6)
78269 #define F_SIGNAL_DET_LN6    V_SIGNAL_DET_LN6(1U)
78272 #define V_SIGNAL_DET_LN5(x) ((x) << S_SIGNAL_DET_LN5)
78273 #define F_SIGNAL_DET_LN5    V_SIGNAL_DET_LN5(1U)
78276 #define V_SIGNAL_DET_LN4(x) ((x) << S_SIGNAL_DET_LN4)
78277 #define F_SIGNAL_DET_LN4    V_SIGNAL_DET_LN4(1U)
78280 #define V_SIGNAL_DET_LN3(x) ((x) << S_SIGNAL_DET_LN3)
78281 #define F_SIGNAL_DET_LN3    V_SIGNAL_DET_LN3(1U)
78284 #define V_SIGNAL_DET_LN2(x) ((x) << S_SIGNAL_DET_LN2)
78285 #define F_SIGNAL_DET_LN2    V_SIGNAL_DET_LN2(1U)
78288 #define V_SIGNAL_DET_LN1(x) ((x) << S_SIGNAL_DET_LN1)
78289 #define F_SIGNAL_DET_LN1    V_SIGNAL_DET_LN1(1U)
78292 #define V_SIGNAL_DET_LN0(x) ((x) << S_SIGNAL_DET_LN0)
78293 #define F_SIGNAL_DET_LN0    V_SIGNAL_DET_LN0(1U)
78296 #define V_SIGDETCTRL_LN7(x) ((x) << S_SIGDETCTRL_LN7)
78297 #define F_SIGDETCTRL_LN7    V_SIGDETCTRL_LN7(1U)
78300 #define V_SIGDETCTRL_LN6(x) ((x) << S_SIGDETCTRL_LN6)
78301 #define F_SIGDETCTRL_LN6    V_SIGDETCTRL_LN6(1U)
78304 #define V_SIGDETCTRL_LN5(x) ((x) << S_SIGDETCTRL_LN5)
78305 #define F_SIGDETCTRL_LN5    V_SIGDETCTRL_LN5(1U)
78308 #define V_SIGDETCTRL_LN4(x) ((x) << S_SIGDETCTRL_LN4)
78309 #define F_SIGDETCTRL_LN4    V_SIGDETCTRL_LN4(1U)
78312 #define V_SIGDETCTRL_LN3(x) ((x) << S_SIGDETCTRL_LN3)
78313 #define F_SIGDETCTRL_LN3    V_SIGDETCTRL_LN3(1U)
78316 #define V_SIGDETCTRL_LN2(x) ((x) << S_SIGDETCTRL_LN2)
78317 #define F_SIGDETCTRL_LN2    V_SIGDETCTRL_LN2(1U)
78319 #define S_SIGDETCTRL_LN1    1
78320 #define V_SIGDETCTRL_LN1(x) ((x) << S_SIGDETCTRL_LN1)
78321 #define F_SIGDETCTRL_LN1    V_SIGDETCTRL_LN1(1U)
78324 #define V_SIGDETCTRL_LN0(x) ((x) << S_SIGDETCTRL_LN0)
78325 #define F_SIGDETCTRL_LN0    V_SIGDETCTRL_LN0(1U)
78330 #define V_SFP3_RX_LOS(x) ((x) << S_SFP3_RX_LOS)
78331 #define F_SFP3_RX_LOS    V_SFP3_RX_LOS(1U)
78334 #define V_SFP3_TX_FAULT(x) ((x) << S_SFP3_TX_FAULT)
78335 #define F_SFP3_TX_FAULT    V_SFP3_TX_FAULT(1U)
78338 #define V_SFP3_MOD_PRES(x) ((x) << S_SFP3_MOD_PRES)
78339 #define F_SFP3_MOD_PRES    V_SFP3_MOD_PRES(1U)
78342 #define V_SFP2_RX_LOS(x) ((x) << S_SFP2_RX_LOS)
78343 #define F_SFP2_RX_LOS    V_SFP2_RX_LOS(1U)
78346 #define V_SFP2_TX_FAULT(x) ((x) << S_SFP2_TX_FAULT)
78347 #define F_SFP2_TX_FAULT    V_SFP2_TX_FAULT(1U)
78350 #define V_SFP2_MOD_PRES(x) ((x) << S_SFP2_MOD_PRES)
78351 #define F_SFP2_MOD_PRES    V_SFP2_MOD_PRES(1U)
78354 #define V_SFP1_RX_LOS(x) ((x) << S_SFP1_RX_LOS)
78355 #define F_SFP1_RX_LOS    V_SFP1_RX_LOS(1U)
78358 #define V_SFP1_TX_FAULT(x) ((x) << S_SFP1_TX_FAULT)
78359 #define F_SFP1_TX_FAULT    V_SFP1_TX_FAULT(1U)
78362 #define V_SFP1_MOD_PRES(x) ((x) << S_SFP1_MOD_PRES)
78363 #define F_SFP1_MOD_PRES    V_SFP1_MOD_PRES(1U)
78366 #define V_SFP0_RX_LOS(x) ((x) << S_SFP0_RX_LOS)
78367 #define F_SFP0_RX_LOS    V_SFP0_RX_LOS(1U)
78370 #define V_SFP0_TX_FAULT(x) ((x) << S_SFP0_TX_FAULT)
78371 #define F_SFP0_TX_FAULT    V_SFP0_TX_FAULT(1U)
78374 #define V_SFP0_MOD_PRES(x) ((x) << S_SFP0_MOD_PRES)
78375 #define F_SFP0_MOD_PRES    V_SFP0_MOD_PRES(1U)
78378 #define V_QSFP1_INT_L(x) ((x) << S_QSFP1_INT_L)
78379 #define F_QSFP1_INT_L    V_QSFP1_INT_L(1U)
78382 #define V_QSFP1_MOD_PRES(x) ((x) << S_QSFP1_MOD_PRES)
78383 #define F_QSFP1_MOD_PRES    V_QSFP1_MOD_PRES(1U)
78385 #define S_QSFP0_INT_L    1
78386 #define V_QSFP0_INT_L(x) ((x) << S_QSFP0_INT_L)
78387 #define F_QSFP0_INT_L    V_QSFP0_INT_L(1U)
78390 #define V_QSFP0_MOD_PRES(x) ((x) << S_QSFP0_MOD_PRES)
78391 #define F_QSFP0_MOD_PRES    V_QSFP0_MOD_PRES(1U)
78397 #define V_T7_1_LB_MODE(x) ((x) << S_T7_1_LB_MODE)
78398 #define G_T7_1_LB_MODE(x) (((x) >> S_T7_1_LB_MODE) & M_T7_1_LB_MODE)
78401 #define V_SFP3_TX_DISABLE(x) ((x) << S_SFP3_TX_DISABLE)
78402 #define F_SFP3_TX_DISABLE    V_SFP3_TX_DISABLE(1U)
78405 #define V_SFP2_TX_DISABLE(x) ((x) << S_SFP2_TX_DISABLE)
78406 #define F_SFP2_TX_DISABLE    V_SFP2_TX_DISABLE(1U)
78409 #define V_SFP1_TX_DISABLE(x) ((x) << S_SFP1_TX_DISABLE)
78410 #define F_SFP1_TX_DISABLE    V_SFP1_TX_DISABLE(1U)
78413 #define V_SFP0_TX_DISABLE(x) ((x) << S_SFP0_TX_DISABLE)
78414 #define F_SFP0_TX_DISABLE    V_SFP0_TX_DISABLE(1U)
78417 #define V_QSFP1_LPMODE(x) ((x) << S_QSFP1_LPMODE)
78418 #define F_QSFP1_LPMODE    V_QSFP1_LPMODE(1U)
78421 #define V_QSFP1_MODSEL_L(x) ((x) << S_QSFP1_MODSEL_L)
78422 #define F_QSFP1_MODSEL_L    V_QSFP1_MODSEL_L(1U)
78425 #define V_QSFP1_RESET_L(x) ((x) << S_QSFP1_RESET_L)
78426 #define F_QSFP1_RESET_L    V_QSFP1_RESET_L(1U)
78429 #define V_QSFP0_LPMODE(x) ((x) << S_QSFP0_LPMODE)
78430 #define F_QSFP0_LPMODE    V_QSFP0_LPMODE(1U)
78432 #define S_QSFP0_MODSEL_L    1
78433 #define V_QSFP0_MODSEL_L(x) ((x) << S_QSFP0_MODSEL_L)
78434 #define F_QSFP0_MODSEL_L    V_QSFP0_MODSEL_L(1U)
78437 #define V_QSFP0_RESET_L(x) ((x) << S_QSFP0_RESET_L)
78438 #define F_QSFP0_RESET_L    V_QSFP0_RESET_L(1U)
78443 #define V_PORT3_FPGA_LINK_UP(x) ((x) << S_PORT3_FPGA_LINK_UP)
78444 #define F_PORT3_FPGA_LINK_UP    V_PORT3_FPGA_LINK_UP(1U)
78447 #define V_PORT2_FPGA_LINK_UP(x) ((x) << S_PORT2_FPGA_LINK_UP)
78448 #define F_PORT2_FPGA_LINK_UP    V_PORT2_FPGA_LINK_UP(1U)
78450 #define S_PORT1_FPGA_LINK_UP    1
78451 #define V_PORT1_FPGA_LINK_UP(x) ((x) << S_PORT1_FPGA_LINK_UP)
78452 #define F_PORT1_FPGA_LINK_UP    V_PORT1_FPGA_LINK_UP(1U)
78455 #define V_PORT0_FPGA_LINK_UP(x) ((x) << S_PORT0_FPGA_LINK_UP)
78456 #define F_PORT0_FPGA_LINK_UP    V_PORT0_FPGA_LINK_UP(1U)
78462 #define V_MTIP_REV_400G_0(x) ((x) << S_MTIP_REV_400G_0)
78463 #define G_MTIP_REV_400G_0(x) (((x) >> S_MTIP_REV_400G_0) & M_MTIP_REV_400G_0)
78469 #define V_INV_LOOP(x) ((x) << S_INV_LOOP)
78470 #define F_INV_LOOP    V_INV_LOOP(1U)
78473 #define V_TX_FLUSH_ENABLE_400G_0(x) ((x) << S_TX_FLUSH_ENABLE_400G_0)
78474 #define F_TX_FLUSH_ENABLE_400G_0    V_TX_FLUSH_ENABLE_400G_0(1U)
78477 #define V_PHY_LOOPBACK_EN_400G(x) ((x) << S_PHY_LOOPBACK_EN_400G)
78478 #define F_PHY_LOOPBACK_EN_400G    V_PHY_LOOPBACK_EN_400G(1U)
78493 #define V_T7_IPG(x) ((x) << S_T7_IPG)
78494 #define G_T7_IPG(x) (((x) >> S_T7_IPG) & M_T7_IPG)
78504 #define V_CL1_PAUSE_QUANTA_THRESH(x) ((x) << S_CL1_PAUSE_QUANTA_THRESH)
78505 #define G_CL1_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL1_PAUSE_QUANTA_THRESH) & M_CL1_PAUSE_QUANTA_THRESH)
78509 #define V_CL0_PAUSE_QUANTA_THRESH(x) ((x) << S_CL0_PAUSE_QUANTA_THRESH)
78510 #define G_CL0_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL0_PAUSE_QUANTA_THRESH) & M_CL0_PAUSE_QUANTA_THRESH)
78516 #define V_CL3_PAUSE_QUANTA_THRESH(x) ((x) << S_CL3_PAUSE_QUANTA_THRESH)
78517 #define G_CL3_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL3_PAUSE_QUANTA_THRESH) & M_CL3_PAUSE_QUANTA_THRESH)
78521 #define V_CL2_PAUSE_QUANTA_THRESH(x) ((x) << S_CL2_PAUSE_QUANTA_THRESH)
78522 #define G_CL2_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL2_PAUSE_QUANTA_THRESH) & M_CL2_PAUSE_QUANTA_THRESH)
78528 #define V_CL5_PAUSE_QUANTA_THRESH(x) ((x) << S_CL5_PAUSE_QUANTA_THRESH)
78529 #define G_CL5_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL5_PAUSE_QUANTA_THRESH) & M_CL5_PAUSE_QUANTA_THRESH)
78533 #define V_CL4_PAUSE_QUANTA_THRESH(x) ((x) << S_CL4_PAUSE_QUANTA_THRESH)
78534 #define G_CL4_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL4_PAUSE_QUANTA_THRESH) & M_CL4_PAUSE_QUANTA_THRESH)
78540 #define V_CL7_PAUSE_QUANTA_THRESH(x) ((x) << S_CL7_PAUSE_QUANTA_THRESH)
78541 #define G_CL7_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL7_PAUSE_QUANTA_THRESH) & M_CL7_PAUSE_QUANTA_THRESH)
78545 #define V_CL6_PAUSE_QUANTA_THRESH(x) ((x) << S_CL6_PAUSE_QUANTA_THRESH)
78546 #define G_CL6_PAUSE_QUANTA_THRESH(x) (((x) >> S_CL6_PAUSE_QUANTA_THRESH) & M_CL6_PAUSE_QUANTA_THRESH)
78552 #define V_RX_PAUSE_STATUS(x) ((x) << S_RX_PAUSE_STATUS)
78553 #define G_RX_PAUSE_STATUS(x) (((x) >> S_RX_PAUSE_STATUS) & M_RX_PAUSE_STATUS)
78561 #define V_MTIP_REV_400G_1(x) ((x) << S_MTIP_REV_400G_1)
78562 #define G_MTIP_REV_400G_1(x) (((x) >> S_MTIP_REV_400G_1) & M_MTIP_REV_400G_1)
78568 #define V_TX_FLUSH_ENABLE_400G_1(x) ((x) << S_TX_FLUSH_ENABLE_400G_1)
78569 #define F_TX_FLUSH_ENABLE_400G_1    V_TX_FLUSH_ENABLE_400G_1(1U)
78572 #define V_PHY_LOOPBACK_EN_400G_1(x) ((x) << S_PHY_LOOPBACK_EN_400G_1)
78573 #define F_PHY_LOOPBACK_EN_400G_1    V_PHY_LOOPBACK_EN_400G_1(1U)
78585 #define V_ENABLE_MCAST_RX_400G_1(x) ((x) << S_ENABLE_MCAST_RX_400G_1)
78586 #define F_ENABLE_MCAST_RX_400G_1    V_ENABLE_MCAST_RX_400G_1(1U)
78590 #define V_HASHTABLE_ADDR_400G_1(x) ((x) << S_HASHTABLE_ADDR_400G_1)
78591 #define G_HASHTABLE_ADDR_400G_1(x) (((x) >> S_HASHTABLE_ADDR_400G_1) & M_HASHTABLE_ADDR_400G_1)
78609 #define V_T7_SPEED_SELECTION(x) ((x) << S_T7_SPEED_SELECTION)
78610 #define F_T7_SPEED_SELECTION    V_T7_SPEED_SELECTION(1U)
78615 #define V_400G_RX_LINK_STATUS(x) ((x) << S_400G_RX_LINK_STATUS)
78616 #define F_400G_RX_LINK_STATUS    V_400G_RX_LINK_STATUS(1U)
78622 #define V_400G_DEVICE_ID0_0(x) ((x) << S_400G_DEVICE_ID0_0)
78623 #define G_400G_DEVICE_ID0_0(x) (((x) >> S_400G_DEVICE_ID0_0) & M_400G_DEVICE_ID0_0)
78629 #define V_400G_DEVICE_ID1_0(x) ((x) << S_400G_DEVICE_ID1_0)
78630 #define G_400G_DEVICE_ID1_0(x) (((x) >> S_400G_DEVICE_ID1_0) & M_400G_DEVICE_ID1_0)
78635 #define V_400G_CAPABLE_0(x) ((x) << S_400G_CAPABLE_0)
78636 #define F_400G_CAPABLE_0    V_400G_CAPABLE_0(1U)
78639 #define V_200G_CAPABLE_0(x) ((x) << S_200G_CAPABLE_0)
78640 #define F_200G_CAPABLE_0    V_200G_CAPABLE_0(1U)
78645 #define V_DEVICE_PACKAGE(x) ((x) << S_DEVICE_PACKAGE)
78646 #define F_DEVICE_PACKAGE    V_DEVICE_PACKAGE(1U)
78653 #define V_400G_PCS_TYPE_SELECTION_0(x) ((x) << S_400G_PCS_TYPE_SELECTION_0)
78654 #define G_400G_PCS_TYPE_SELECTION_0(x) (((x) >> S_400G_PCS_TYPE_SELECTION_0) & M_400G_PCS_TYPE_SELECTION_0)
78661 #define V_T7_DEVICE_PRESENT(x) ((x) << S_T7_DEVICE_PRESENT)
78662 #define G_T7_DEVICE_PRESENT(x) (((x) >> S_T7_DEVICE_PRESENT) & M_T7_DEVICE_PRESENT)
78664 #define S_400GBASE_R    1
78665 #define V_400GBASE_R(x) ((x) << S_400GBASE_R)
78666 #define F_400GBASE_R    V_400GBASE_R(1U)
78669 #define V_200GBASE_R(x) ((x) << S_200GBASE_R)
78670 #define F_200GBASE_R    V_200GBASE_R(1U)
78682 #define V_HIGH_ORDER(x) ((x) << S_HIGH_ORDER)
78683 #define F_HIGH_ORDER    V_HIGH_ORDER(1U)
78687 #define V_ERROR_BLOCK_COUNTER(x) ((x) << S_ERROR_BLOCK_COUNTER)
78688 #define G_ERROR_BLOCK_COUNTER(x) (((x) >> S_ERROR_BLOCK_COUNTER) & M_ERROR_BLOCK_COUNTER)
78698 #define V_T7_LANE_0_MAPPING(x) ((x) << S_T7_LANE_0_MAPPING)
78699 #define G_T7_LANE_0_MAPPING(x) (((x) >> S_T7_LANE_0_MAPPING) & M_T7_LANE_0_MAPPING)
78705 #define V_T7_LANE_1_MAPPING(x) ((x) << S_T7_LANE_1_MAPPING)
78706 #define G_T7_LANE_1_MAPPING(x) (((x) >> S_T7_LANE_1_MAPPING) & M_T7_LANE_1_MAPPING)
78712 #define V_T7_LANE_2_MAPPING(x) ((x) << S_T7_LANE_2_MAPPING)
78713 #define G_T7_LANE_2_MAPPING(x) (((x) >> S_T7_LANE_2_MAPPING) & M_T7_LANE_2_MAPPING)
78719 #define V_T7_LANE_3_MAPPING(x) ((x) << S_T7_LANE_3_MAPPING)
78720 #define G_T7_LANE_3_MAPPING(x) (((x) >> S_T7_LANE_3_MAPPING) & M_T7_LANE_3_MAPPING)
78726 #define V_T7_LANE_4_MAPPING(x) ((x) << S_T7_LANE_4_MAPPING)
78727 #define G_T7_LANE_4_MAPPING(x) (((x) >> S_T7_LANE_4_MAPPING) & M_T7_LANE_4_MAPPING)
78733 #define V_T7_LANE_5_MAPPING(x) ((x) << S_T7_LANE_5_MAPPING)
78734 #define G_T7_LANE_5_MAPPING(x) (((x) >> S_T7_LANE_5_MAPPING) & M_T7_LANE_5_MAPPING)
78740 #define V_T7_LANE_6_MAPPING(x) ((x) << S_T7_LANE_6_MAPPING)
78741 #define G_T7_LANE_6_MAPPING(x) (((x) >> S_T7_LANE_6_MAPPING) & M_T7_LANE_6_MAPPING)
78747 #define V_T7_LANE_7_MAPPING(x) ((x) << S_T7_LANE_7_MAPPING)
78748 #define G_T7_LANE_7_MAPPING(x) (((x) >> S_T7_LANE_7_MAPPING) & M_T7_LANE_7_MAPPING)
78754 #define V_T7_LANE_8_MAPPING(x) ((x) << S_T7_LANE_8_MAPPING)
78755 #define G_T7_LANE_8_MAPPING(x) (((x) >> S_T7_LANE_8_MAPPING) & M_T7_LANE_8_MAPPING)
78761 #define V_T7_LANE_9_MAPPING(x) ((x) << S_T7_LANE_9_MAPPING)
78762 #define G_T7_LANE_9_MAPPING(x) (((x) >> S_T7_LANE_9_MAPPING) & M_T7_LANE_9_MAPPING)
78768 #define V_T7_LANE_10_MAPPING(x) ((x) << S_T7_LANE_10_MAPPING)
78769 #define G_T7_LANE_10_MAPPING(x) (((x) >> S_T7_LANE_10_MAPPING) & M_T7_LANE_10_MAPPING)
78775 #define V_T7_LANE_11_MAPPING(x) ((x) << S_T7_LANE_11_MAPPING)
78776 #define G_T7_LANE_11_MAPPING(x) (((x) >> S_T7_LANE_11_MAPPING) & M_T7_LANE_11_MAPPING)
78782 #define V_T7_LANE_12_MAPPING(x) ((x) << S_T7_LANE_12_MAPPING)
78783 #define G_T7_LANE_12_MAPPING(x) (((x) >> S_T7_LANE_12_MAPPING) & M_T7_LANE_12_MAPPING)
78789 #define V_T7_LANE_13_MAPPING(x) ((x) << S_T7_LANE_13_MAPPING)
78790 #define G_T7_LANE_13_MAPPING(x) (((x) >> S_T7_LANE_13_MAPPING) & M_T7_LANE_13_MAPPING)
78796 #define V_T7_LANE_14_MAPPING(x) ((x) << S_T7_LANE_14_MAPPING)
78797 #define G_T7_LANE_14_MAPPING(x) (((x) >> S_T7_LANE_14_MAPPING) & M_T7_LANE_14_MAPPING)
78803 #define V_T7_LANE_15_MAPPING(x) ((x) << S_T7_LANE_15_MAPPING)
78804 #define G_T7_LANE_15_MAPPING(x) (((x) >> S_T7_LANE_15_MAPPING) & M_T7_LANE_15_MAPPING)
78812 #define V_T7_VL_INTVL(x) ((x) << S_T7_VL_INTVL)
78813 #define G_T7_VL_INTVL(x) (((x) >> S_T7_VL_INTVL) & M_T7_VL_INTVL)
78819 #define V_TX_LANE_THRESH(x) ((x) << S_TX_LANE_THRESH)
78820 #define G_TX_LANE_THRESH(x) (((x) >> S_TX_LANE_THRESH) & M_TX_LANE_THRESH)
78826 #define V_TX_CDMII_PACE(x) ((x) << S_TX_CDMII_PACE)
78827 #define G_TX_CDMII_PACE(x) (((x) >> S_TX_CDMII_PACE) & M_TX_CDMII_PACE)
78833 #define V_AM_0(x) ((x) << S_AM_0)
78834 #define G_AM_0(x) (((x) >> S_AM_0) & M_AM_0)
78840 #define V_AM_1(x) ((x) << S_AM_1)
78841 #define G_AM_1(x) (((x) >> S_AM_1) & M_AM_1)
78847 #define V_DBGINFO0(x) ((x) << S_DBGINFO0)
78848 #define G_DBGINFO0(x) (((x) >> S_DBGINFO0) & M_DBGINFO0)
78854 #define V_DBGINFO1(x) ((x) << S_DBGINFO1)
78855 #define G_DBGINFO1(x) (((x) >> S_DBGINFO1) & M_DBGINFO1)
78861 #define V_DBGINFO2(x) ((x) << S_DBGINFO2)
78862 #define G_DBGINFO2(x) (((x) >> S_DBGINFO2) & M_DBGINFO2)
78868 #define V_DBGINFO3(x) ((x) << S_DBGINFO3)
78869 #define G_DBGINFO3(x) (((x) >> S_DBGINFO3) & M_DBGINFO3)
78875 #define V_400G_RX_LINK_STATUS_1(x) ((x) << S_400G_RX_LINK_STATUS_1)
78876 #define F_400G_RX_LINK_STATUS_1    V_400G_RX_LINK_STATUS_1(1U)
78882 #define V_400G_DEVICE_ID0_1(x) ((x) << S_400G_DEVICE_ID0_1)
78883 #define G_400G_DEVICE_ID0_1(x) (((x) >> S_400G_DEVICE_ID0_1) & M_400G_DEVICE_ID0_1)
78889 #define V_400G_DEVICE_ID1_1(x) ((x) << S_400G_DEVICE_ID1_1)
78890 #define G_400G_DEVICE_ID1_1(x) (((x) >> S_400G_DEVICE_ID1_1) & M_400G_DEVICE_ID1_1)
78895 #define V_400G_CAPABLE_1(x) ((x) << S_400G_CAPABLE_1)
78896 #define F_400G_CAPABLE_1    V_400G_CAPABLE_1(1U)
78899 #define V_200G_CAPABLE_1(x) ((x) << S_200G_CAPABLE_1)
78900 #define F_200G_CAPABLE_1    V_200G_CAPABLE_1(1U)
78908 #define V_400G_PCS_TYPE_SELECTION_1(x) ((x) << S_400G_PCS_TYPE_SELECTION_1)
78909 #define G_400G_PCS_TYPE_SELECTION_1(x) (((x) >> S_400G_PCS_TYPE_SELECTION_1) & M_400G_PCS_TYPE_SELECTION_1)
78955 #define V_TC_PAD_ALTER(x) ((x) << S_TC_PAD_ALTER)
78956 #define F_TC_PAD_ALTER    V_TC_PAD_ALTER(1U)
78959 #define V_TC_PAD_VALUE(x) ((x) << S_TC_PAD_VALUE)
78960 #define F_TC_PAD_VALUE    V_TC_PAD_VALUE(1U)
78963 #define V_KP_ENABLE(x) ((x) << S_KP_ENABLE)
78964 #define F_KP_ENABLE    V_KP_ENABLE(1U)
78967 #define V_AM16_COPY_DIS(x) ((x) << S_AM16_COPY_DIS)
78968 #define F_AM16_COPY_DIS    V_AM16_COPY_DIS(1U)
78971 #define V_RS_FEC_DEGRADE_OPTION_ENA(x) ((x) << S_RS_FEC_DEGRADE_OPTION_ENA)
78972 #define F_RS_FEC_DEGRADE_OPTION_ENA    V_RS_FEC_DEGRADE_OPTION_ENA(1U)
78977 #define V_FEC_STATUS_0_14(x) ((x) << S_FEC_STATUS_0_14)
78978 #define F_FEC_STATUS_0_14    V_FEC_STATUS_0_14(1U)
78982 #define V_FEC_STATUS_0_11(x) ((x) << S_FEC_STATUS_0_11)
78983 #define G_FEC_STATUS_0_11(x) (((x) >> S_FEC_STATUS_0_11) & M_FEC_STATUS_0_11)
78986 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_0)
78987 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_0    V_RS_FEC_DEGRADE_SER_RECEIVED0_0(1U)
78990 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_1)
78991 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_1    V_RS_FEC_DEGRADE_SER_RECEIVED0_1(1U)
78994 #define V_RS_FEC_DEGRADE_SER_RECEIVED0_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED0_2)
78995 #define F_RS_FEC_DEGRADE_SER_RECEIVED0_2    V_RS_FEC_DEGRADE_SER_RECEIVED0_2(1U)
78998 #define V_FEC_STATUS_0_4(x) ((x) << S_FEC_STATUS_0_4)
78999 #define F_FEC_STATUS_0_4    V_FEC_STATUS_0_4(1U)
79002 #define V_FEC_STATUS_0_3(x) ((x) << S_FEC_STATUS_0_3)
79003 #define F_FEC_STATUS_0_3    V_FEC_STATUS_0_3(1U)
79006 #define V_FEC_STATUS_0_2(x) ((x) << S_FEC_STATUS_0_2)
79007 #define F_FEC_STATUS_0_2    V_FEC_STATUS_0_2(1U)
79009 #define S_FEC_STATUS_0_1    1
79010 #define V_FEC_STATUS_0_1(x) ((x) << S_FEC_STATUS_0_1)
79011 #define F_FEC_STATUS_0_1    V_FEC_STATUS_0_1(1U)
79014 #define V_FEC_STATUS_0_0(x) ((x) << S_FEC_STATUS_0_0)
79015 #define F_FEC_STATUS_0_0    V_FEC_STATUS_0_0(1U)
79026 #define V_DEC_TRESH(x) ((x) << S_DEC_TRESH)
79027 #define G_DEC_TRESH(x) (((x) >> S_DEC_TRESH) & M_DEC_TRESH)
79033 #define V_FEC_STATUS_1_14(x) ((x) << S_FEC_STATUS_1_14)
79034 #define F_FEC_STATUS_1_14    V_FEC_STATUS_1_14(1U)
79038 #define V_FEC_STATUS_1_11(x) ((x) << S_FEC_STATUS_1_11)
79039 #define G_FEC_STATUS_1_11(x) (((x) >> S_FEC_STATUS_1_11) & M_FEC_STATUS_1_11)
79042 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_0)
79043 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_0    V_RS_FEC_DEGRADE_SER_RECEIVED1_0(1U)
79046 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_1)
79047 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_1    V_RS_FEC_DEGRADE_SER_RECEIVED1_1(1U)
79050 #define V_RS_FEC_DEGRADE_SER_RECEIVED1_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED1_2)
79051 #define F_RS_FEC_DEGRADE_SER_RECEIVED1_2    V_RS_FEC_DEGRADE_SER_RECEIVED1_2(1U)
79054 #define V_FEC_STATUS_1_4(x) ((x) << S_FEC_STATUS_1_4)
79055 #define F_FEC_STATUS_1_4    V_FEC_STATUS_1_4(1U)
79058 #define V_FEC_STATUS_1_3(x) ((x) << S_FEC_STATUS_1_3)
79059 #define F_FEC_STATUS_1_3    V_FEC_STATUS_1_3(1U)
79062 #define V_FEC_STATUS_1_2(x) ((x) << S_FEC_STATUS_1_2)
79063 #define F_FEC_STATUS_1_2    V_FEC_STATUS_1_2(1U)
79065 #define S_FEC_STATUS_1_1    1
79066 #define V_FEC_STATUS_1_1(x) ((x) << S_FEC_STATUS_1_1)
79067 #define F_FEC_STATUS_1_1    V_FEC_STATUS_1_1(1U)
79070 #define V_FEC_STATUS_1_0(x) ((x) << S_FEC_STATUS_1_0)
79071 #define F_FEC_STATUS_1_0    V_FEC_STATUS_1_0(1U)
79083 #define V_FEC_STATUS_2_14(x) ((x) << S_FEC_STATUS_2_14)
79084 #define F_FEC_STATUS_2_14    V_FEC_STATUS_2_14(1U)
79088 #define V_FEC_STATUS_2_11(x) ((x) << S_FEC_STATUS_2_11)
79089 #define G_FEC_STATUS_2_11(x) (((x) >> S_FEC_STATUS_2_11) & M_FEC_STATUS_2_11)
79092 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_0)
79093 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_0    V_RS_FEC_DEGRADE_SER_RECEIVED2_0(1U)
79096 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_1)
79097 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_1    V_RS_FEC_DEGRADE_SER_RECEIVED2_1(1U)
79100 #define V_RS_FEC_DEGRADE_SER_RECEIVED2_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED2_2)
79101 #define F_RS_FEC_DEGRADE_SER_RECEIVED2_2    V_RS_FEC_DEGRADE_SER_RECEIVED2_2(1U)
79104 #define V_FEC_STATUS_2_4(x) ((x) << S_FEC_STATUS_2_4)
79105 #define F_FEC_STATUS_2_4    V_FEC_STATUS_2_4(1U)
79108 #define V_FEC_STATUS_2_3(x) ((x) << S_FEC_STATUS_2_3)
79109 #define F_FEC_STATUS_2_3    V_FEC_STATUS_2_3(1U)
79112 #define V_FEC_STATUS_2_2(x) ((x) << S_FEC_STATUS_2_2)
79113 #define F_FEC_STATUS_2_2    V_FEC_STATUS_2_2(1U)
79115 #define S_FEC_STATUS_2_1    1
79116 #define V_FEC_STATUS_2_1(x) ((x) << S_FEC_STATUS_2_1)
79117 #define F_FEC_STATUS_2_1    V_FEC_STATUS_2_1(1U)
79120 #define V_FEC_STATUS_2_0(x) ((x) << S_FEC_STATUS_2_0)
79121 #define F_FEC_STATUS_2_0    V_FEC_STATUS_2_0(1U)
79133 #define V_FEC_STATUS_3_14(x) ((x) << S_FEC_STATUS_3_14)
79134 #define F_FEC_STATUS_3_14    V_FEC_STATUS_3_14(1U)
79138 #define V_FEC_STATUS_3_11(x) ((x) << S_FEC_STATUS_3_11)
79139 #define G_FEC_STATUS_3_11(x) (((x) >> S_FEC_STATUS_3_11) & M_FEC_STATUS_3_11)
79142 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_0)
79143 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_0    V_RS_FEC_DEGRADE_SER_RECEIVED3_0(1U)
79146 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_1)
79147 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_1    V_RS_FEC_DEGRADE_SER_RECEIVED3_1(1U)
79150 #define V_RS_FEC_DEGRADE_SER_RECEIVED3_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED3_2)
79151 #define F_RS_FEC_DEGRADE_SER_RECEIVED3_2    V_RS_FEC_DEGRADE_SER_RECEIVED3_2(1U)
79154 #define V_FEC_STATUS_3_4(x) ((x) << S_FEC_STATUS_3_4)
79155 #define F_FEC_STATUS_3_4    V_FEC_STATUS_3_4(1U)
79158 #define V_FEC_STATUS_3_3(x) ((x) << S_FEC_STATUS_3_3)
79159 #define F_FEC_STATUS_3_3    V_FEC_STATUS_3_3(1U)
79162 #define V_FEC_STATUS_3_2(x) ((x) << S_FEC_STATUS_3_2)
79163 #define F_FEC_STATUS_3_2    V_FEC_STATUS_3_2(1U)
79165 #define S_FEC_STATUS_3_1    1
79166 #define V_FEC_STATUS_3_1(x) ((x) << S_FEC_STATUS_3_1)
79167 #define F_FEC_STATUS_3_1    V_FEC_STATUS_3_1(1U)
79170 #define V_FEC_STATUS_3_0(x) ((x) << S_FEC_STATUS_3_0)
79171 #define F_FEC_STATUS_3_0    V_FEC_STATUS_3_0(1U)
79183 #define V_FEC_STATUS_4_14(x) ((x) << S_FEC_STATUS_4_14)
79184 #define F_FEC_STATUS_4_14    V_FEC_STATUS_4_14(1U)
79188 #define V_FEC_STATUS_4_11(x) ((x) << S_FEC_STATUS_4_11)
79189 #define G_FEC_STATUS_4_11(x) (((x) >> S_FEC_STATUS_4_11) & M_FEC_STATUS_4_11)
79192 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_0)
79193 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_0    V_RS_FEC_DEGRADE_SER_RECEIVED4_0(1U)
79196 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_1)
79197 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_1    V_RS_FEC_DEGRADE_SER_RECEIVED4_1(1U)
79200 #define V_RS_FEC_DEGRADE_SER_RECEIVED4_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED4_2)
79201 #define F_RS_FEC_DEGRADE_SER_RECEIVED4_2    V_RS_FEC_DEGRADE_SER_RECEIVED4_2(1U)
79204 #define V_FEC_STATUS_4_4(x) ((x) << S_FEC_STATUS_4_4)
79205 #define F_FEC_STATUS_4_4    V_FEC_STATUS_4_4(1U)
79208 #define V_FEC_STATUS_4_3(x) ((x) << S_FEC_STATUS_4_3)
79209 #define F_FEC_STATUS_4_3    V_FEC_STATUS_4_3(1U)
79212 #define V_FEC_STATUS_4_2(x) ((x) << S_FEC_STATUS_4_2)
79213 #define F_FEC_STATUS_4_2    V_FEC_STATUS_4_2(1U)
79215 #define S_FEC_STATUS_4_1    1
79216 #define V_FEC_STATUS_4_1(x) ((x) << S_FEC_STATUS_4_1)
79217 #define F_FEC_STATUS_4_1    V_FEC_STATUS_4_1(1U)
79220 #define V_FEC_STATUS_4_0(x) ((x) << S_FEC_STATUS_4_0)
79221 #define F_FEC_STATUS_4_0    V_FEC_STATUS_4_0(1U)
79233 #define V_FEC_STATUS_5_14(x) ((x) << S_FEC_STATUS_5_14)
79234 #define F_FEC_STATUS_5_14    V_FEC_STATUS_5_14(1U)
79238 #define V_FEC_STATUS_5_11(x) ((x) << S_FEC_STATUS_5_11)
79239 #define G_FEC_STATUS_5_11(x) (((x) >> S_FEC_STATUS_5_11) & M_FEC_STATUS_5_11)
79242 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_0)
79243 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_0    V_RS_FEC_DEGRADE_SER_RECEIVED5_0(1U)
79246 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_1)
79247 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_1    V_RS_FEC_DEGRADE_SER_RECEIVED5_1(1U)
79250 #define V_RS_FEC_DEGRADE_SER_RECEIVED5_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED5_2)
79251 #define F_RS_FEC_DEGRADE_SER_RECEIVED5_2    V_RS_FEC_DEGRADE_SER_RECEIVED5_2(1U)
79254 #define V_FEC_STATUS_5_4(x) ((x) << S_FEC_STATUS_5_4)
79255 #define F_FEC_STATUS_5_4    V_FEC_STATUS_5_4(1U)
79258 #define V_FEC_STATUS_5_3(x) ((x) << S_FEC_STATUS_5_3)
79259 #define F_FEC_STATUS_5_3    V_FEC_STATUS_5_3(1U)
79262 #define V_FEC_STATUS_5_2(x) ((x) << S_FEC_STATUS_5_2)
79263 #define F_FEC_STATUS_5_2    V_FEC_STATUS_5_2(1U)
79265 #define S_FEC_STATUS_5_1    1
79266 #define V_FEC_STATUS_5_1(x) ((x) << S_FEC_STATUS_5_1)
79267 #define F_FEC_STATUS_5_1    V_FEC_STATUS_5_1(1U)
79270 #define V_FEC_STATUS_5_0(x) ((x) << S_FEC_STATUS_5_0)
79271 #define F_FEC_STATUS_5_0    V_FEC_STATUS_5_0(1U)
79283 #define V_FEC_STATUS_6_14(x) ((x) << S_FEC_STATUS_6_14)
79284 #define F_FEC_STATUS_6_14    V_FEC_STATUS_6_14(1U)
79288 #define V_FEC_STATUS_6_11(x) ((x) << S_FEC_STATUS_6_11)
79289 #define G_FEC_STATUS_6_11(x) (((x) >> S_FEC_STATUS_6_11) & M_FEC_STATUS_6_11)
79292 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_0)
79293 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_0    V_RS_FEC_DEGRADE_SER_RECEIVED6_0(1U)
79296 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_1)
79297 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_1    V_RS_FEC_DEGRADE_SER_RECEIVED6_1(1U)
79300 #define V_RS_FEC_DEGRADE_SER_RECEIVED6_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED6_2)
79301 #define F_RS_FEC_DEGRADE_SER_RECEIVED6_2    V_RS_FEC_DEGRADE_SER_RECEIVED6_2(1U)
79304 #define V_FEC_STATUS_6_4(x) ((x) << S_FEC_STATUS_6_4)
79305 #define F_FEC_STATUS_6_4    V_FEC_STATUS_6_4(1U)
79308 #define V_FEC_STATUS_6_3(x) ((x) << S_FEC_STATUS_6_3)
79309 #define F_FEC_STATUS_6_3    V_FEC_STATUS_6_3(1U)
79312 #define V_FEC_STATUS_6_2(x) ((x) << S_FEC_STATUS_6_2)
79313 #define F_FEC_STATUS_6_2    V_FEC_STATUS_6_2(1U)
79315 #define S_FEC_STATUS_6_1    1
79316 #define V_FEC_STATUS_6_1(x) ((x) << S_FEC_STATUS_6_1)
79317 #define F_FEC_STATUS_6_1    V_FEC_STATUS_6_1(1U)
79320 #define V_FEC_STATUS_6_0(x) ((x) << S_FEC_STATUS_6_0)
79321 #define F_FEC_STATUS_6_0    V_FEC_STATUS_6_0(1U)
79333 #define V_FEC_STATUS_7_14(x) ((x) << S_FEC_STATUS_7_14)
79334 #define F_FEC_STATUS_7_14    V_FEC_STATUS_7_14(1U)
79338 #define V_FEC_STATUS_7_11(x) ((x) << S_FEC_STATUS_7_11)
79339 #define G_FEC_STATUS_7_11(x) (((x) >> S_FEC_STATUS_7_11) & M_FEC_STATUS_7_11)
79342 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_0(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_0)
79343 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_0    V_RS_FEC_DEGRADE_SER_RECEIVED7_0(1U)
79346 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_1(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_1)
79347 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_1    V_RS_FEC_DEGRADE_SER_RECEIVED7_1(1U)
79350 #define V_RS_FEC_DEGRADE_SER_RECEIVED7_2(x) ((x) << S_RS_FEC_DEGRADE_SER_RECEIVED7_2)
79351 #define F_RS_FEC_DEGRADE_SER_RECEIVED7_2    V_RS_FEC_DEGRADE_SER_RECEIVED7_2(1U)
79354 #define V_FEC_STATUS_7_4(x) ((x) << S_FEC_STATUS_7_4)
79355 #define F_FEC_STATUS_7_4    V_FEC_STATUS_7_4(1U)
79358 #define V_FEC_STATUS_7_3(x) ((x) << S_FEC_STATUS_7_3)
79359 #define F_FEC_STATUS_7_3    V_FEC_STATUS_7_3(1U)
79362 #define V_FEC_STATUS_7_2(x) ((x) << S_FEC_STATUS_7_2)
79363 #define F_FEC_STATUS_7_2    V_FEC_STATUS_7_2(1U)
79365 #define S_FEC_STATUS_7_1    1
79366 #define V_FEC_STATUS_7_1(x) ((x) << S_FEC_STATUS_7_1)
79367 #define F_FEC_STATUS_7_1    V_FEC_STATUS_7_1(1U)
79370 #define V_FEC_STATUS_7_0(x) ((x) << S_FEC_STATUS_7_0)
79371 #define F_FEC_STATUS_7_0    V_FEC_STATUS_7_0(1U)
79383 #define V_HISER_CW(x) ((x) << S_HISER_CW)
79384 #define G_HISER_CW(x) (((x) >> S_HISER_CW) & M_HISER_CW)
79390 #define V_HISER_THRESH(x) ((x) << S_HISER_THRESH)
79391 #define G_HISER_THRESH(x) (((x) >> S_HISER_THRESH) & M_HISER_THRESH)
79397 #define V_HISER_TIME(x) ((x) << S_HISER_TIME)
79398 #define G_HISER_TIME(x) (((x) >> S_HISER_TIME) & M_HISER_TIME)
79404 #define V_DEGRADE_SET_CW(x) ((x) << S_DEGRADE_SET_CW)
79405 #define G_DEGRADE_SET_CW(x) (((x) >> S_DEGRADE_SET_CW) & M_DEGRADE_SET_CW)
79411 #define V_DEGRADE_SET_CW_HI(x) ((x) << S_DEGRADE_SET_CW_HI)
79412 #define G_DEGRADE_SET_CW_HI(x) (((x) >> S_DEGRADE_SET_CW_HI) & M_DEGRADE_SET_CW_HI)
79418 #define V_DEGRADE_SET_THRESH(x) ((x) << S_DEGRADE_SET_THRESH)
79419 #define G_DEGRADE_SET_THRESH(x) (((x) >> S_DEGRADE_SET_THRESH) & M_DEGRADE_SET_THRESH)
79425 #define V_DEGRADE_SET_THRESH_HI(x) ((x) << S_DEGRADE_SET_THRESH_HI)
79426 #define G_DEGRADE_SET_THRESH_HI(x) (((x) >> S_DEGRADE_SET_THRESH_HI) & M_DEGRADE_SET_THRESH_HI)
79432 #define V_DEGRADE_SET_CLEAR(x) ((x) << S_DEGRADE_SET_CLEAR)
79433 #define G_DEGRADE_SET_CLEAR(x) (((x) >> S_DEGRADE_SET_CLEAR) & M_DEGRADE_SET_CLEAR)
79439 #define V_DEGRADE_SET_CLEAR_HI(x) ((x) << S_DEGRADE_SET_CLEAR_HI)
79440 #define G_DEGRADE_SET_CLEAR_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_HI) & M_DEGRADE_SET_CLEAR_HI)
79446 #define V_DEGRADE_SET_CLEAR_THRESH(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH)
79447 #define G_DEGRADE_SET_CLEAR_THRESH(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH) & M_DEGRADE_SET_CLEAR_THRESH)
79453 #define V_DEGRADE_SET_CLEAR_THRESH_HI(x) ((x) << S_DEGRADE_SET_CLEAR_THRESH_HI)
79454 #define G_DEGRADE_SET_CLEAR_THRESH_HI(x) (((x) >> S_DEGRADE_SET_CLEAR_THRESH_HI) & M_DEGRADE_SET_CLEAR_THRESH_HI)
79499 #define V_RS_FEC_SYMBLERR4_LO(x) ((x) << S_RS_FEC_SYMBLERR4_LO)
79500 #define F_RS_FEC_SYMBLERR4_LO    V_RS_FEC_SYMBLERR4_LO(1U)
79505 #define V_RS_FEC_SYMBLERR4_HI(x) ((x) << S_RS_FEC_SYMBLERR4_HI)
79506 #define F_RS_FEC_SYMBLERR4_HI    V_RS_FEC_SYMBLERR4_HI(1U)
79511 #define V_RS_FEC_SYMBLERR5_LO(x) ((x) << S_RS_FEC_SYMBLERR5_LO)
79512 #define F_RS_FEC_SYMBLERR5_LO    V_RS_FEC_SYMBLERR5_LO(1U)
79517 #define V_RS_FEC_SYMBLERR5_HI(x) ((x) << S_RS_FEC_SYMBLERR5_HI)
79518 #define F_RS_FEC_SYMBLERR5_HI    V_RS_FEC_SYMBLERR5_HI(1U)
79523 #define V_RS_FEC_SYMBLERR6_LO(x) ((x) << S_RS_FEC_SYMBLERR6_LO)
79524 #define F_RS_FEC_SYMBLERR6_LO    V_RS_FEC_SYMBLERR6_LO(1U)
79529 #define V_RS_FEC_SYMBLERR6_HI(x) ((x) << S_RS_FEC_SYMBLERR6_HI)
79530 #define F_RS_FEC_SYMBLERR6_HI    V_RS_FEC_SYMBLERR6_HI(1U)
79535 #define V_RS_FEC_SYMBLERR7_LO(x) ((x) << S_RS_FEC_SYMBLERR7_LO)
79536 #define F_RS_FEC_SYMBLERR7_LO    V_RS_FEC_SYMBLERR7_LO(1U)
79541 #define V_RS_FEC_SYMBLERR7_HI(x) ((x) << S_RS_FEC_SYMBLERR7_HI)
79542 #define F_RS_FEC_SYMBLERR7_HI    V_RS_FEC_SYMBLERR7_HI(1U)
79547 #define V_RS_FEC_SYMBLERR8_LO(x) ((x) << S_RS_FEC_SYMBLERR8_LO)
79548 #define F_RS_FEC_SYMBLERR8_LO    V_RS_FEC_SYMBLERR8_LO(1U)
79553 #define V_RS_FEC_SYMBLERR8_HI(x) ((x) << S_RS_FEC_SYMBLERR8_HI)
79554 #define F_RS_FEC_SYMBLERR8_HI    V_RS_FEC_SYMBLERR8_HI(1U)
79559 #define V_RS_FEC_SYMBLERR9_LO(x) ((x) << S_RS_FEC_SYMBLERR9_LO)
79560 #define F_RS_FEC_SYMBLERR9_LO    V_RS_FEC_SYMBLERR9_LO(1U)
79565 #define V_RS_FEC_SYMBLERR9_HI(x) ((x) << S_RS_FEC_SYMBLERR9_HI)
79566 #define F_RS_FEC_SYMBLERR9_HI    V_RS_FEC_SYMBLERR9_HI(1U)
79571 #define V_RS_FEC_SYMBLERR10_LO(x) ((x) << S_RS_FEC_SYMBLERR10_LO)
79572 #define F_RS_FEC_SYMBLERR10_LO    V_RS_FEC_SYMBLERR10_LO(1U)
79577 #define V_RS_FEC_SYMBLERR10_HI(x) ((x) << S_RS_FEC_SYMBLERR10_HI)
79578 #define F_RS_FEC_SYMBLERR10_HI    V_RS_FEC_SYMBLERR10_HI(1U)
79583 #define V_RS_FEC_SYMBLERR11_LO(x) ((x) << S_RS_FEC_SYMBLERR11_LO)
79584 #define F_RS_FEC_SYMBLERR11_LO    V_RS_FEC_SYMBLERR11_LO(1U)
79589 #define V_RS_FEC_SYMBLERR11_HI(x) ((x) << S_RS_FEC_SYMBLERR11_HI)
79590 #define F_RS_FEC_SYMBLERR11_HI    V_RS_FEC_SYMBLERR11_HI(1U)
79595 #define V_RS_FEC_SYMBLERR12_LO(x) ((x) << S_RS_FEC_SYMBLERR12_LO)
79596 #define F_RS_FEC_SYMBLERR12_LO    V_RS_FEC_SYMBLERR12_LO(1U)
79601 #define V_RS_FEC_SYMBLERR12_HI(x) ((x) << S_RS_FEC_SYMBLERR12_HI)
79602 #define F_RS_FEC_SYMBLERR12_HI    V_RS_FEC_SYMBLERR12_HI(1U)
79607 #define V_RS_FEC_SYMBLERR13_LO(x) ((x) << S_RS_FEC_SYMBLERR13_LO)
79608 #define F_RS_FEC_SYMBLERR13_LO    V_RS_FEC_SYMBLERR13_LO(1U)
79613 #define V_RS_FEC_SYMBLERR13_HI(x) ((x) << S_RS_FEC_SYMBLERR13_HI)
79614 #define F_RS_FEC_SYMBLERR13_HI    V_RS_FEC_SYMBLERR13_HI(1U)
79619 #define V_RS_FEC_SYMBLERR14_LO(x) ((x) << S_RS_FEC_SYMBLERR14_LO)
79620 #define F_RS_FEC_SYMBLERR14_LO    V_RS_FEC_SYMBLERR14_LO(1U)
79625 #define V_RS_FEC_SYMBLERR14_HI(x) ((x) << S_RS_FEC_SYMBLERR14_HI)
79626 #define F_RS_FEC_SYMBLERR14_HI    V_RS_FEC_SYMBLERR14_HI(1U)
79631 #define V_RS_FEC_SYMBLERR15_LO(x) ((x) << S_RS_FEC_SYMBLERR15_LO)
79632 #define F_RS_FEC_SYMBLERR15_LO    V_RS_FEC_SYMBLERR15_LO(1U)
79637 #define V_RS_FEC_SYMBLERR15_HI(x) ((x) << S_RS_FEC_SYMBLERR15_HI)
79638 #define F_RS_FEC_SYMBLERR15_HI    V_RS_FEC_SYMBLERR15_HI(1U)
79644 #define V_VENDOR_INFO_1_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_1_AMPS_LOCK)
79645 #define F_VENDOR_INFO_1_AMPS_LOCK    V_VENDOR_INFO_1_AMPS_LOCK(1U)
79651 #define V_VENDOR_INFO_2_AMPS_LOCK(x) ((x) << S_VENDOR_INFO_2_AMPS_LOCK)
79652 #define G_VENDOR_INFO_2_AMPS_LOCK(x) (((x) >> S_VENDOR_INFO_2_AMPS_LOCK) & M_VENDOR_INFO_2_AMPS_LOCK)
79659 #define V_RS_FEC_VENDOR_ALIGN_STATUS(x) ((x) << S_RS_FEC_VENDOR_ALIGN_STATUS)
79660 #define G_RS_FEC_VENDOR_ALIGN_STATUS(x) (((x) >> S_RS_FEC_VENDOR_ALIGN_STATUS) & M_RS_FEC_VENDOR_ALIGN_STATUS)
79664 #define S_FEC74_FEC_ABILITY_0_B1    1
79665 #define V_FEC74_FEC_ABILITY_0_B1(x) ((x) << S_FEC74_FEC_ABILITY_0_B1)
79666 #define F_FEC74_FEC_ABILITY_0_B1    V_FEC74_FEC_ABILITY_0_B1(1U)
79669 #define V_FEC74_FEC_ABILITY_0_B0(x) ((x) << S_FEC74_FEC_ABILITY_0_B0)
79670 #define F_FEC74_FEC_ABILITY_0_B0    V_FEC74_FEC_ABILITY_0_B0(1U)
79674 #define S_FEC_ENABLE_ERROR_INDICATION    1
79675 #define V_FEC_ENABLE_ERROR_INDICATION(x) ((x) << S_FEC_ENABLE_ERROR_INDICATION)
79676 #define F_FEC_ENABLE_ERROR_INDICATION    V_FEC_ENABLE_ERROR_INDICATION(1U)
79679 #define V_T7_FEC_ENABLE(x) ((x) << S_T7_FEC_ENABLE)
79680 #define F_T7_FEC_ENABLE    V_T7_FEC_ENABLE(1U)
79684 #define S_FEC_LOCKED_1    1
79685 #define V_FEC_LOCKED_1(x) ((x) << S_FEC_LOCKED_1)
79686 #define F_FEC_LOCKED_1    V_FEC_LOCKED_1(1U)
79692 #define V_VL0_CCW_LO(x) ((x) << S_VL0_CCW_LO)
79693 #define G_VL0_CCW_LO(x) (((x) >> S_VL0_CCW_LO) & M_VL0_CCW_LO)
79699 #define V_VL0_NCCW_LO(x) ((x) << S_VL0_NCCW_LO)
79700 #define G_VL0_NCCW_LO(x) (((x) >> S_VL0_NCCW_LO) & M_VL0_NCCW_LO)
79706 #define V_VL1_CCW_LO(x) ((x) << S_VL1_CCW_LO)
79707 #define G_VL1_CCW_LO(x) (((x) >> S_VL1_CCW_LO) & M_VL1_CCW_LO)
79713 #define V_VL1_NCCW_LO(x) ((x) << S_VL1_NCCW_LO)
79714 #define G_VL1_NCCW_LO(x) (((x) >> S_VL1_NCCW_LO) & M_VL1_NCCW_LO)
79720 #define V_COUNTER_HI(x) ((x) << S_COUNTER_HI)
79721 #define G_COUNTER_HI(x) (((x) >> S_COUNTER_HI) & M_COUNTER_HI)
79725 #define S_FEC74_FEC_ABILITY_1_B1    1
79726 #define V_FEC74_FEC_ABILITY_1_B1(x) ((x) << S_FEC74_FEC_ABILITY_1_B1)
79727 #define F_FEC74_FEC_ABILITY_1_B1    V_FEC74_FEC_ABILITY_1_B1(1U)
79730 #define V_FEC74_FEC_ABILITY_1_B0(x) ((x) << S_FEC74_FEC_ABILITY_1_B0)
79731 #define F_FEC74_FEC_ABILITY_1_B0    V_FEC74_FEC_ABILITY_1_B0(1U)
79742 #define S_FEC74_FEC_ABILITY_2_B1    1
79743 #define V_FEC74_FEC_ABILITY_2_B1(x) ((x) << S_FEC74_FEC_ABILITY_2_B1)
79744 #define F_FEC74_FEC_ABILITY_2_B1    V_FEC74_FEC_ABILITY_2_B1(1U)
79747 #define V_FEC74_FEC_ABILITY_2_B0(x) ((x) << S_FEC74_FEC_ABILITY_2_B0)
79748 #define F_FEC74_FEC_ABILITY_2_B0    V_FEC74_FEC_ABILITY_2_B0(1U)
79759 #define S_FEC74_FEC_ABILITY_3_B1    1
79760 #define V_FEC74_FEC_ABILITY_3_B1(x) ((x) << S_FEC74_FEC_ABILITY_3_B1)
79761 #define F_FEC74_FEC_ABILITY_3_B1    V_FEC74_FEC_ABILITY_3_B1(1U)
79764 #define V_FEC74_FEC_ABILITY_3_B0(x) ((x) << S_FEC74_FEC_ABILITY_3_B0)
79765 #define F_FEC74_FEC_ABILITY_3_B0    V_FEC74_FEC_ABILITY_3_B0(1U)
79776 #define S_FEC74_FEC_ABILITY_4_B1    1
79777 #define V_FEC74_FEC_ABILITY_4_B1(x) ((x) << S_FEC74_FEC_ABILITY_4_B1)
79778 #define F_FEC74_FEC_ABILITY_4_B1    V_FEC74_FEC_ABILITY_4_B1(1U)
79781 #define V_FEC74_FEC_ABILITY_4_B0(x) ((x) << S_FEC74_FEC_ABILITY_4_B0)
79782 #define F_FEC74_FEC_ABILITY_4_B0    V_FEC74_FEC_ABILITY_4_B0(1U)
79793 #define S_FEC74_FEC_ABILITY_5_B1    1
79794 #define V_FEC74_FEC_ABILITY_5_B1(x) ((x) << S_FEC74_FEC_ABILITY_5_B1)
79795 #define F_FEC74_FEC_ABILITY_5_B1    V_FEC74_FEC_ABILITY_5_B1(1U)
79798 #define V_FEC74_FEC_ABILITY_5_B0(x) ((x) << S_FEC74_FEC_ABILITY_5_B0)
79799 #define F_FEC74_FEC_ABILITY_5_B0    V_FEC74_FEC_ABILITY_5_B0(1U)
79810 #define S_FEC74_FEC_ABILITY_6_B1    1
79811 #define V_FEC74_FEC_ABILITY_6_B1(x) ((x) << S_FEC74_FEC_ABILITY_6_B1)
79812 #define F_FEC74_FEC_ABILITY_6_B1    V_FEC74_FEC_ABILITY_6_B1(1U)
79815 #define V_FEC74_FEC_ABILITY_6_B0(x) ((x) << S_FEC74_FEC_ABILITY_6_B0)
79816 #define F_FEC74_FEC_ABILITY_6_B0    V_FEC74_FEC_ABILITY_6_B0(1U)
79827 #define S_FEC74_FEC_ABILITY_7_B1    1
79828 #define V_FEC74_FEC_ABILITY_7_B1(x) ((x) << S_FEC74_FEC_ABILITY_7_B1)
79829 #define F_FEC74_FEC_ABILITY_7_B1    V_FEC74_FEC_ABILITY_7_B1(1U)
79832 #define V_FEC74_FEC_ABILITY_7_B0(x) ((x) << S_FEC74_FEC_ABILITY_7_B0)
79833 #define F_FEC74_FEC_ABILITY_7_B0    V_FEC74_FEC_ABILITY_7_B0(1U)
79847 #define V_BEAN0_REM_FAULT(x) ((x) << S_BEAN0_REM_FAULT)
79848 #define F_BEAN0_REM_FAULT    V_BEAN0_REM_FAULT(1U)
79855 #define V_BEAN0_AB_2_15_12(x) ((x) << S_BEAN0_AB_2_15_12)
79856 #define G_BEAN0_AB_2_15_12(x) (((x) >> S_BEAN0_AB_2_15_12) & M_BEAN0_AB_2_15_12)
79860 #define V_BEAN0_AB_2_11_0(x) ((x) << S_BEAN0_AB_2_11_0)
79861 #define G_BEAN0_AB_2_11_0(x) (((x) >> S_BEAN0_AB_2_11_0) & M_BEAN0_AB_2_11_0)
79866 #define V_BEAN0_ABL_REM_FAULT(x) ((x) << S_BEAN0_ABL_REM_FAULT)
79867 #define F_BEAN0_ABL_REM_FAULT    V_BEAN0_ABL_REM_FAULT(1U)
79874 #define V_BEAN0_REM_AB_15_12(x) ((x) << S_BEAN0_REM_AB_15_12)
79875 #define G_BEAN0_REM_AB_15_12(x) (((x) >> S_BEAN0_REM_AB_15_12) & M_BEAN0_REM_AB_15_12)
79879 #define V_BEAN0_REM_AB_11_0(x) ((x) << S_BEAN0_REM_AB_11_0)
79880 #define G_BEAN0_REM_AB_11_0(x) (((x) >> S_BEAN0_REM_AB_11_0) & M_BEAN0_REM_AB_11_0)
79892 #define V_5GKR(x) ((x) << S_5GKR)
79893 #define F_5GKR    V_5GKR(1U)
79896 #define V_2P5GKX(x) ((x) << S_2P5GKX)
79897 #define F_2P5GKX    V_2P5GKX(1U)
79900 #define V_25G_KR(x) ((x) << S_25G_KR)
79901 #define F_25G_KR    V_25G_KR(1U)
79904 #define V_25G_KR_S(x) ((x) << S_25G_KR_S)
79905 #define F_25G_KR_S    V_25G_KR_S(1U)
79908 #define V_RS_FEC(x) ((x) << S_RS_FEC)
79909 #define F_RS_FEC    V_RS_FEC(1U)
79912 #define V_FC_FEC(x) ((x) << S_FC_FEC)
79913 #define F_FC_FEC    V_FC_FEC(1U)
79918 #define V_RS_FEC_NEGOTIATED(x) ((x) << S_RS_FEC_NEGOTIATED)
79919 #define F_RS_FEC_NEGOTIATED    V_RS_FEC_NEGOTIATED(1U)
79922 #define V_400GKR4CR4(x) ((x) << S_400GKR4CR4)
79923 #define F_400GKR4CR4    V_400GKR4CR4(1U)
79926 #define V_200GKR2CR2(x) ((x) << S_200GKR2CR2)
79927 #define F_200GKR2CR2    V_200GKR2CR2(1U)
79930 #define V_100GKR1CR1(x) ((x) << S_100GKR1CR1)
79931 #define F_100GKR1CR1    V_100GKR1CR1(1U)
79934 #define V_200GKR4CR4(x) ((x) << S_200GKR4CR4)
79935 #define F_200GKR4CR4    V_200GKR4CR4(1U)
79937 #define S_100GKR2CR2    1
79938 #define V_100GKR2CR2(x) ((x) << S_100GKR2CR2)
79939 #define F_100GKR2CR2    V_100GKR2CR2(1U)
79942 #define V_50GKRCR(x) ((x) << S_50GKRCR)
79943 #define F_50GKRCR    V_50GKRCR(1U)
79950 #define V_BEAN1_REM_FAULT(x) ((x) << S_BEAN1_REM_FAULT)
79951 #define F_BEAN1_REM_FAULT    V_BEAN1_REM_FAULT(1U)
79958 #define V_BEAN1_AB_2_15_12(x) ((x) << S_BEAN1_AB_2_15_12)
79959 #define G_BEAN1_AB_2_15_12(x) (((x) >> S_BEAN1_AB_2_15_12) & M_BEAN1_AB_2_15_12)
79963 #define V_BEAN1_AB_2_11_0(x) ((x) << S_BEAN1_AB_2_11_0)
79964 #define G_BEAN1_AB_2_11_0(x) (((x) >> S_BEAN1_AB_2_11_0) & M_BEAN1_AB_2_11_0)
79969 #define V_BEAN1_ABL_REM_FAULT(x) ((x) << S_BEAN1_ABL_REM_FAULT)
79970 #define F_BEAN1_ABL_REM_FAULT    V_BEAN1_ABL_REM_FAULT(1U)
79977 #define V_BEAN1_REM_AB_15_12(x) ((x) << S_BEAN1_REM_AB_15_12)
79978 #define G_BEAN1_REM_AB_15_12(x) (((x) >> S_BEAN1_REM_AB_15_12) & M_BEAN1_REM_AB_15_12)
79982 #define V_BEAN1_REM_AB_11_0(x) ((x) << S_BEAN1_REM_AB_11_0)
79983 #define G_BEAN1_REM_AB_11_0(x) (((x) >> S_BEAN1_REM_AB_11_0) & M_BEAN1_REM_AB_11_0)
79999 #define V_BEAN2_REM_FAULT(x) ((x) << S_BEAN2_REM_FAULT)
80000 #define F_BEAN2_REM_FAULT    V_BEAN2_REM_FAULT(1U)
80007 #define V_BEAN2_AB_2_15_12(x) ((x) << S_BEAN2_AB_2_15_12)
80008 #define G_BEAN2_AB_2_15_12(x) (((x) >> S_BEAN2_AB_2_15_12) & M_BEAN2_AB_2_15_12)
80012 #define V_BEAN2_AB_2_11_0(x) ((x) << S_BEAN2_AB_2_11_0)
80013 #define G_BEAN2_AB_2_11_0(x) (((x) >> S_BEAN2_AB_2_11_0) & M_BEAN2_AB_2_11_0)
80018 #define V_BEAN2_ABL_REM_FAULT(x) ((x) << S_BEAN2_ABL_REM_FAULT)
80019 #define F_BEAN2_ABL_REM_FAULT    V_BEAN2_ABL_REM_FAULT(1U)
80026 #define V_BEAN2_REM_AB_15_12(x) ((x) << S_BEAN2_REM_AB_15_12)
80027 #define G_BEAN2_REM_AB_15_12(x) (((x) >> S_BEAN2_REM_AB_15_12) & M_BEAN2_REM_AB_15_12)
80031 #define V_BEAN2_REM_AB_11_0(x) ((x) << S_BEAN2_REM_AB_11_0)
80032 #define G_BEAN2_REM_AB_11_0(x) (((x) >> S_BEAN2_REM_AB_11_0) & M_BEAN2_REM_AB_11_0)
80048 #define V_BEAN3_REM_FAULT(x) ((x) << S_BEAN3_REM_FAULT)
80049 #define F_BEAN3_REM_FAULT    V_BEAN3_REM_FAULT(1U)
80056 #define V_BEAN3_AB_2_15_12(x) ((x) << S_BEAN3_AB_2_15_12)
80057 #define G_BEAN3_AB_2_15_12(x) (((x) >> S_BEAN3_AB_2_15_12) & M_BEAN3_AB_2_15_12)
80061 #define V_BEAN3_AB_2_11_0(x) ((x) << S_BEAN3_AB_2_11_0)
80062 #define G_BEAN3_AB_2_11_0(x) (((x) >> S_BEAN3_AB_2_11_0) & M_BEAN3_AB_2_11_0)
80067 #define V_BEAN3_ABL_REM_FAULT(x) ((x) << S_BEAN3_ABL_REM_FAULT)
80068 #define F_BEAN3_ABL_REM_FAULT    V_BEAN3_ABL_REM_FAULT(1U)
80075 #define V_BEAN3_REM_AB_15_12(x) ((x) << S_BEAN3_REM_AB_15_12)
80076 #define G_BEAN3_REM_AB_15_12(x) (((x) >> S_BEAN3_REM_AB_15_12) & M_BEAN3_REM_AB_15_12)
80080 #define V_BEAN3_REM_AB_11_0(x) ((x) << S_BEAN3_REM_AB_11_0)
80081 #define G_BEAN3_REM_AB_11_0(x) (((x) >> S_BEAN3_REM_AB_11_0) & M_BEAN3_REM_AB_11_0)
80097 #define V_BEAN4_REM_FAULT(x) ((x) << S_BEAN4_REM_FAULT)
80098 #define F_BEAN4_REM_FAULT    V_BEAN4_REM_FAULT(1U)
80105 #define V_BEAN4_AB_2_15_12(x) ((x) << S_BEAN4_AB_2_15_12)
80106 #define G_BEAN4_AB_2_15_12(x) (((x) >> S_BEAN4_AB_2_15_12) & M_BEAN4_AB_2_15_12)
80110 #define V_BEAN4_AB_2_11_0(x) ((x) << S_BEAN4_AB_2_11_0)
80111 #define G_BEAN4_AB_2_11_0(x) (((x) >> S_BEAN4_AB_2_11_0) & M_BEAN4_AB_2_11_0)
80116 #define V_BEAN4_ABL_REM_FAULT(x) ((x) << S_BEAN4_ABL_REM_FAULT)
80117 #define F_BEAN4_ABL_REM_FAULT    V_BEAN4_ABL_REM_FAULT(1U)
80124 #define V_BEAN4_REM_AB_15_12(x) ((x) << S_BEAN4_REM_AB_15_12)
80125 #define G_BEAN4_REM_AB_15_12(x) (((x) >> S_BEAN4_REM_AB_15_12) & M_BEAN4_REM_AB_15_12)
80129 #define V_BEAN4_REM_AB_11_0(x) ((x) << S_BEAN4_REM_AB_11_0)
80130 #define G_BEAN4_REM_AB_11_0(x) (((x) >> S_BEAN4_REM_AB_11_0) & M_BEAN4_REM_AB_11_0)
80146 #define V_BEAN5_REM_FAULT(x) ((x) << S_BEAN5_REM_FAULT)
80147 #define F_BEAN5_REM_FAULT    V_BEAN5_REM_FAULT(1U)
80154 #define V_BEAN5_AB_2_15_12(x) ((x) << S_BEAN5_AB_2_15_12)
80155 #define G_BEAN5_AB_2_15_12(x) (((x) >> S_BEAN5_AB_2_15_12) & M_BEAN5_AB_2_15_12)
80159 #define V_BEAN5_AB_2_11_0(x) ((x) << S_BEAN5_AB_2_11_0)
80160 #define G_BEAN5_AB_2_11_0(x) (((x) >> S_BEAN5_AB_2_11_0) & M_BEAN5_AB_2_11_0)
80165 #define V_BEAN5_ABL_REM_FAULT(x) ((x) << S_BEAN5_ABL_REM_FAULT)
80166 #define F_BEAN5_ABL_REM_FAULT    V_BEAN5_ABL_REM_FAULT(1U)
80173 #define V_BEAN5_REM_AB_15_12(x) ((x) << S_BEAN5_REM_AB_15_12)
80174 #define G_BEAN5_REM_AB_15_12(x) (((x) >> S_BEAN5_REM_AB_15_12) & M_BEAN5_REM_AB_15_12)
80178 #define V_BEAN5_REM_AB_11_0(x) ((x) << S_BEAN5_REM_AB_11_0)
80179 #define G_BEAN5_REM_AB_11_0(x) (((x) >> S_BEAN5_REM_AB_11_0) & M_BEAN5_REM_AB_11_0)
80195 #define V_BEAN6_REM_FAULT(x) ((x) << S_BEAN6_REM_FAULT)
80196 #define F_BEAN6_REM_FAULT    V_BEAN6_REM_FAULT(1U)
80203 #define V_BEAN6_AB_2_15_12(x) ((x) << S_BEAN6_AB_2_15_12)
80204 #define G_BEAN6_AB_2_15_12(x) (((x) >> S_BEAN6_AB_2_15_12) & M_BEAN6_AB_2_15_12)
80208 #define V_BEAN6_AB_2_11_0(x) ((x) << S_BEAN6_AB_2_11_0)
80209 #define G_BEAN6_AB_2_11_0(x) (((x) >> S_BEAN6_AB_2_11_0) & M_BEAN6_AB_2_11_0)
80214 #define V_BEAN6_ABL_REM_FAULT(x) ((x) << S_BEAN6_ABL_REM_FAULT)
80215 #define F_BEAN6_ABL_REM_FAULT    V_BEAN6_ABL_REM_FAULT(1U)
80222 #define V_BEAN6_REM_AB_15_12(x) ((x) << S_BEAN6_REM_AB_15_12)
80223 #define G_BEAN6_REM_AB_15_12(x) (((x) >> S_BEAN6_REM_AB_15_12) & M_BEAN6_REM_AB_15_12)
80227 #define V_BEAN6_REM_AB_11_0(x) ((x) << S_BEAN6_REM_AB_11_0)
80228 #define G_BEAN6_REM_AB_11_0(x) (((x) >> S_BEAN6_REM_AB_11_0) & M_BEAN6_REM_AB_11_0)
80244 #define V_BEAN7_REM_FAULT(x) ((x) << S_BEAN7_REM_FAULT)
80245 #define F_BEAN7_REM_FAULT    V_BEAN7_REM_FAULT(1U)
80252 #define V_BEAN7_AB_2_15_12(x) ((x) << S_BEAN7_AB_2_15_12)
80253 #define G_BEAN7_AB_2_15_12(x) (((x) >> S_BEAN7_AB_2_15_12) & M_BEAN7_AB_2_15_12)
80257 #define V_BEAN7_AB_2_11_0(x) ((x) << S_BEAN7_AB_2_11_0)
80258 #define G_BEAN7_AB_2_11_0(x) (((x) >> S_BEAN7_AB_2_11_0) & M_BEAN7_AB_2_11_0)
80263 #define V_BEAN7_ABL_REM_FAULT(x) ((x) << S_BEAN7_ABL_REM_FAULT)
80264 #define F_BEAN7_ABL_REM_FAULT    V_BEAN7_ABL_REM_FAULT(1U)
80271 #define V_BEAN7_REM_AB_15_12(x) ((x) << S_BEAN7_REM_AB_15_12)
80272 #define G_BEAN7_REM_AB_15_12(x) (((x) >> S_BEAN7_REM_AB_15_12) & M_BEAN7_REM_AB_15_12)
80276 #define V_BEAN7_REM_AB_11_0(x) ((x) << S_BEAN7_REM_AB_11_0)
80277 #define G_BEAN7_REM_AB_11_0(x) (((x) >> S_BEAN7_REM_AB_11_0) & M_BEAN7_REM_AB_11_0)
80293 #define V_T7_RESET(x) ((x) << S_T7_RESET)
80294 #define F_T7_RESET    V_T7_RESET(1U)
80299 #define V_CMD_CLEAR_TX(x) ((x) << S_CMD_CLEAR_TX)
80300 #define F_CMD_CLEAR_TX    V_CMD_CLEAR_TX(1U)
80303 #define V_CMD_CLEAR_RX(x) ((x) << S_CMD_CLEAR_RX)
80304 #define F_CMD_CLEAR_RX    V_CMD_CLEAR_RX(1U)
80307 #define V_CLEAR_PRE(x) ((x) << S_CLEAR_PRE)
80308 #define F_CLEAR_PRE    V_CLEAR_PRE(1U)
80311 #define V_CMD_CAPTURE_TX(x) ((x) << S_CMD_CAPTURE_TX)
80312 #define F_CMD_CAPTURE_TX    V_CMD_CAPTURE_TX(1U)
80315 #define V_CMD_CAPTURE_RX(x) ((x) << S_CMD_CAPTURE_RX)
80316 #define F_CMD_CAPTURE_RX    V_CMD_CAPTURE_RX(1U)
80320 #define V_PORTMASK(x) ((x) << S_PORTMASK)
80321 #define G_PORTMASK(x) (((x) >> S_PORTMASK) & M_PORTMASK)
80326 #define V_STATN_CLEARVALUE_LO(x) ((x) << S_STATN_CLEARVALUE_LO)
80327 #define F_STATN_CLEARVALUE_LO    V_STATN_CLEARVALUE_LO(1U)
80332 #define V_STATN_CLEARVALUE_HI(x) ((x) << S_STATN_CLEARVALUE_HI)
80333 #define F_STATN_CLEARVALUE_HI    V_STATN_CLEARVALUE_HI(1U)
80619 #define V_SUB_BLOCK_SEL(x) ((x) << S_SUB_BLOCK_SEL)
80620 #define G_SUB_BLOCK_SEL(x) (((x) >> S_SUB_BLOCK_SEL) & M_SUB_BLOCK_SEL)
80623 #define V_QUAD_BROADCAST_EN(x) ((x) << S_QUAD_BROADCAST_EN)
80624 #define F_QUAD_BROADCAST_EN    V_QUAD_BROADCAST_EN(1U)
80627 #define V_AUTO_INCR(x) ((x) << S_AUTO_INCR)
80628 #define F_AUTO_INCR    V_AUTO_INCR(1U)
80632 #define V_T7_2_ADDR(x) ((x) << S_T7_2_ADDR)
80633 #define G_T7_2_ADDR(x) (((x) >> S_T7_2_ADDR) & M_T7_2_ADDR)
80639 #define V_BGR_RSTN(x) ((x) << S_BGR_RSTN)
80640 #define F_BGR_RSTN    V_BGR_RSTN(1U)
80645 #define V_SOC_REFCLK_EN(x) ((x) << S_SOC_REFCLK_EN)
80646 #define F_SOC_REFCLK_EN    V_SOC_REFCLK_EN(1U)
80651 #define V_QUAD0_CH3_RSTN(x) ((x) << S_QUAD0_CH3_RSTN)
80652 #define F_QUAD0_CH3_RSTN    V_QUAD0_CH3_RSTN(1U)
80655 #define V_QUAD0_CH2_RSTN(x) ((x) << S_QUAD0_CH2_RSTN)
80656 #define F_QUAD0_CH2_RSTN    V_QUAD0_CH2_RSTN(1U)
80659 #define V_QUAD0_CH1_RSTN(x) ((x) << S_QUAD0_CH1_RSTN)
80660 #define F_QUAD0_CH1_RSTN    V_QUAD0_CH1_RSTN(1U)
80663 #define V_QUAD0_CH0_RSTN(x) ((x) << S_QUAD0_CH0_RSTN)
80664 #define F_QUAD0_CH0_RSTN    V_QUAD0_CH0_RSTN(1U)
80666 #define S_QUAD0_RSTN    1
80667 #define V_QUAD0_RSTN(x) ((x) << S_QUAD0_RSTN)
80668 #define F_QUAD0_RSTN    V_QUAD0_RSTN(1U)
80671 #define V_PLL0_RSTN(x) ((x) << S_PLL0_RSTN)
80672 #define F_PLL0_RSTN    V_PLL0_RSTN(1U)
80677 #define V_QUAD1_CH3_RSTN(x) ((x) << S_QUAD1_CH3_RSTN)
80678 #define F_QUAD1_CH3_RSTN    V_QUAD1_CH3_RSTN(1U)
80681 #define V_QUAD1_CH2_RSTN(x) ((x) << S_QUAD1_CH2_RSTN)
80682 #define F_QUAD1_CH2_RSTN    V_QUAD1_CH2_RSTN(1U)
80685 #define V_QUAD1_CH1_RSTN(x) ((x) << S_QUAD1_CH1_RSTN)
80686 #define F_QUAD1_CH1_RSTN    V_QUAD1_CH1_RSTN(1U)
80689 #define V_QUAD1_CH0_RSTN(x) ((x) << S_QUAD1_CH0_RSTN)
80690 #define F_QUAD1_CH0_RSTN    V_QUAD1_CH0_RSTN(1U)
80692 #define S_QUAD1_RSTN    1
80693 #define V_QUAD1_RSTN(x) ((x) << S_QUAD1_RSTN)
80694 #define F_QUAD1_RSTN    V_QUAD1_RSTN(1U)
80697 #define V_PLL1_RSTN(x) ((x) << S_PLL1_RSTN)
80698 #define F_PLL1_RSTN    V_PLL1_RSTN(1U)
80705 #define S_DATA0    1
80707 #define V_DATA0(x) ((x) << S_DATA0)
80708 #define G_DATA0(x) (((x) >> S_DATA0) & M_DATA0)
80711 #define V_I2C_MODE(x) ((x) << S_I2C_MODE)
80712 #define F_I2C_MODE    V_I2C_MODE(1U)
80722 #define V_DBG_CLK_MUX_GPIO(x) ((x) << S_DBG_CLK_MUX_GPIO)
80723 #define F_DBG_CLK_MUX_GPIO    V_DBG_CLK_MUX_GPIO(1U)
80727 #define V_DBG_CLK_MUX_SEL(x) ((x) << S_DBG_CLK_MUX_SEL)
80728 #define G_DBG_CLK_MUX_SEL(x) (((x) >> S_DBG_CLK_MUX_SEL) & M_DBG_CLK_MUX_SEL)
80733 #define V_Q0_MAILBOX_INT_ASSERT(x) ((x) << S_Q0_MAILBOX_INT_ASSERT)
80734 #define F_Q0_MAILBOX_INT_ASSERT    V_Q0_MAILBOX_INT_ASSERT(1U)
80737 #define V_Q0_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_3_ASSERT)
80738 #define F_Q0_TRAINING_FAILURE_3_ASSERT    V_Q0_TRAINING_FAILURE_3_ASSERT(1U)
80741 #define V_Q0_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_2_ASSERT)
80742 #define F_Q0_TRAINING_FAILURE_2_ASSERT    V_Q0_TRAINING_FAILURE_2_ASSERT(1U)
80745 #define V_Q0_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_1_ASSERT)
80746 #define F_Q0_TRAINING_FAILURE_1_ASSERT    V_Q0_TRAINING_FAILURE_1_ASSERT(1U)
80749 #define V_Q0_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q0_TRAINING_FAILURE_0_ASSERT)
80750 #define F_Q0_TRAINING_FAILURE_0_ASSERT    V_Q0_TRAINING_FAILURE_0_ASSERT(1U)
80753 #define V_Q0_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_3_ASSERT)
80754 #define F_Q0_TRAINING_COMPLETE_3_ASSERT    V_Q0_TRAINING_COMPLETE_3_ASSERT(1U)
80757 #define V_Q0_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_2_ASSERT)
80758 #define F_Q0_TRAINING_COMPLETE_2_ASSERT    V_Q0_TRAINING_COMPLETE_2_ASSERT(1U)
80761 #define V_Q0_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_1_ASSERT)
80762 #define F_Q0_TRAINING_COMPLETE_1_ASSERT    V_Q0_TRAINING_COMPLETE_1_ASSERT(1U)
80765 #define V_Q0_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q0_TRAINING_COMPLETE_0_ASSERT)
80766 #define F_Q0_TRAINING_COMPLETE_0_ASSERT    V_Q0_TRAINING_COMPLETE_0_ASSERT(1U)
80769 #define V_Q0_AN_TX_INT_3_ASSERT(x) ((x) << S_Q0_AN_TX_INT_3_ASSERT)
80770 #define F_Q0_AN_TX_INT_3_ASSERT    V_Q0_AN_TX_INT_3_ASSERT(1U)
80773 #define V_Q0_AN_TX_INT_2_ASSERT(x) ((x) << S_Q0_AN_TX_INT_2_ASSERT)
80774 #define F_Q0_AN_TX_INT_2_ASSERT    V_Q0_AN_TX_INT_2_ASSERT(1U)
80777 #define V_Q0_AN_TX_INT_1_ASSERT(x) ((x) << S_Q0_AN_TX_INT_1_ASSERT)
80778 #define F_Q0_AN_TX_INT_1_ASSERT    V_Q0_AN_TX_INT_1_ASSERT(1U)
80781 #define V_Q0_AN_TX_INT_0_ASSERT(x) ((x) << S_Q0_AN_TX_INT_0_ASSERT)
80782 #define F_Q0_AN_TX_INT_0_ASSERT    V_Q0_AN_TX_INT_0_ASSERT(1U)
80785 #define V_Q0_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_3_ASSERT)
80786 #define F_Q0_SIGNAL_DETECT_3_ASSERT    V_Q0_SIGNAL_DETECT_3_ASSERT(1U)
80789 #define V_Q0_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_2_ASSERT)
80790 #define F_Q0_SIGNAL_DETECT_2_ASSERT    V_Q0_SIGNAL_DETECT_2_ASSERT(1U)
80793 #define V_Q0_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_1_ASSERT)
80794 #define F_Q0_SIGNAL_DETECT_1_ASSERT    V_Q0_SIGNAL_DETECT_1_ASSERT(1U)
80797 #define V_Q0_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q0_SIGNAL_DETECT_0_ASSERT)
80798 #define F_Q0_SIGNAL_DETECT_0_ASSERT    V_Q0_SIGNAL_DETECT_0_ASSERT(1U)
80801 #define V_Q0_CDR_LOL_3_ASSERT(x) ((x) << S_Q0_CDR_LOL_3_ASSERT)
80802 #define F_Q0_CDR_LOL_3_ASSERT    V_Q0_CDR_LOL_3_ASSERT(1U)
80805 #define V_Q0_CDR_LOL_2_ASSERT(x) ((x) << S_Q0_CDR_LOL_2_ASSERT)
80806 #define F_Q0_CDR_LOL_2_ASSERT    V_Q0_CDR_LOL_2_ASSERT(1U)
80809 #define V_Q0_CDR_LOL_1_ASSERT(x) ((x) << S_Q0_CDR_LOL_1_ASSERT)
80810 #define F_Q0_CDR_LOL_1_ASSERT    V_Q0_CDR_LOL_1_ASSERT(1U)
80813 #define V_Q0_CDR_LOL_0_ASSERT(x) ((x) << S_Q0_CDR_LOL_0_ASSERT)
80814 #define F_Q0_CDR_LOL_0_ASSERT    V_Q0_CDR_LOL_0_ASSERT(1U)
80817 #define V_Q0_LOS_3_ASSERT(x) ((x) << S_Q0_LOS_3_ASSERT)
80818 #define F_Q0_LOS_3_ASSERT    V_Q0_LOS_3_ASSERT(1U)
80821 #define V_Q0_LOS_2_ASSERT(x) ((x) << S_Q0_LOS_2_ASSERT)
80822 #define F_Q0_LOS_2_ASSERT    V_Q0_LOS_2_ASSERT(1U)
80824 #define S_Q0_LOS_1_ASSERT    1
80825 #define V_Q0_LOS_1_ASSERT(x) ((x) << S_Q0_LOS_1_ASSERT)
80826 #define F_Q0_LOS_1_ASSERT    V_Q0_LOS_1_ASSERT(1U)
80829 #define V_Q0_LOS_0_ASSERT(x) ((x) << S_Q0_LOS_0_ASSERT)
80830 #define F_Q0_LOS_0_ASSERT    V_Q0_LOS_0_ASSERT(1U)
80836 #define V_Q1_MAILBOX_INT_ASSERT(x) ((x) << S_Q1_MAILBOX_INT_ASSERT)
80837 #define F_Q1_MAILBOX_INT_ASSERT    V_Q1_MAILBOX_INT_ASSERT(1U)
80840 #define V_Q1_TRAINING_FAILURE_3_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_3_ASSERT)
80841 #define F_Q1_TRAINING_FAILURE_3_ASSERT    V_Q1_TRAINING_FAILURE_3_ASSERT(1U)
80844 #define V_Q1_TRAINING_FAILURE_2_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_2_ASSERT)
80845 #define F_Q1_TRAINING_FAILURE_2_ASSERT    V_Q1_TRAINING_FAILURE_2_ASSERT(1U)
80848 #define V_Q1_TRAINING_FAILURE_1_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_1_ASSERT)
80849 #define F_Q1_TRAINING_FAILURE_1_ASSERT    V_Q1_TRAINING_FAILURE_1_ASSERT(1U)
80852 #define V_Q1_TRAINING_FAILURE_0_ASSERT(x) ((x) << S_Q1_TRAINING_FAILURE_0_ASSERT)
80853 #define F_Q1_TRAINING_FAILURE_0_ASSERT    V_Q1_TRAINING_FAILURE_0_ASSERT(1U)
80856 #define V_Q1_TRAINING_COMPLETE_3_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_3_ASSERT)
80857 #define F_Q1_TRAINING_COMPLETE_3_ASSERT    V_Q1_TRAINING_COMPLETE_3_ASSERT(1U)
80860 #define V_Q1_TRAINING_COMPLETE_2_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_2_ASSERT)
80861 #define F_Q1_TRAINING_COMPLETE_2_ASSERT    V_Q1_TRAINING_COMPLETE_2_ASSERT(1U)
80864 #define V_Q1_TRAINING_COMPLETE_1_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_1_ASSERT)
80865 #define F_Q1_TRAINING_COMPLETE_1_ASSERT    V_Q1_TRAINING_COMPLETE_1_ASSERT(1U)
80868 #define V_Q1_TRAINING_COMPLETE_0_ASSERT(x) ((x) << S_Q1_TRAINING_COMPLETE_0_ASSERT)
80869 #define F_Q1_TRAINING_COMPLETE_0_ASSERT    V_Q1_TRAINING_COMPLETE_0_ASSERT(1U)
80872 #define V_Q1_AN_TX_INT_3_ASSERT(x) ((x) << S_Q1_AN_TX_INT_3_ASSERT)
80873 #define F_Q1_AN_TX_INT_3_ASSERT    V_Q1_AN_TX_INT_3_ASSERT(1U)
80876 #define V_Q1_AN_TX_INT_2_ASSERT(x) ((x) << S_Q1_AN_TX_INT_2_ASSERT)
80877 #define F_Q1_AN_TX_INT_2_ASSERT    V_Q1_AN_TX_INT_2_ASSERT(1U)
80880 #define V_Q1_AN_TX_INT_1_ASSERT(x) ((x) << S_Q1_AN_TX_INT_1_ASSERT)
80881 #define F_Q1_AN_TX_INT_1_ASSERT    V_Q1_AN_TX_INT_1_ASSERT(1U)
80884 #define V_Q1_AN_TX_INT_0_ASSERT(x) ((x) << S_Q1_AN_TX_INT_0_ASSERT)
80885 #define F_Q1_AN_TX_INT_0_ASSERT    V_Q1_AN_TX_INT_0_ASSERT(1U)
80888 #define V_Q1_SIGNAL_DETECT_3_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_3_ASSERT)
80889 #define F_Q1_SIGNAL_DETECT_3_ASSERT    V_Q1_SIGNAL_DETECT_3_ASSERT(1U)
80892 #define V_Q1_SIGNAL_DETECT_2_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_2_ASSERT)
80893 #define F_Q1_SIGNAL_DETECT_2_ASSERT    V_Q1_SIGNAL_DETECT_2_ASSERT(1U)
80896 #define V_Q1_SIGNAL_DETECT_1_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_1_ASSERT)
80897 #define F_Q1_SIGNAL_DETECT_1_ASSERT    V_Q1_SIGNAL_DETECT_1_ASSERT(1U)
80900 #define V_Q1_SIGNAL_DETECT_0_ASSERT(x) ((x) << S_Q1_SIGNAL_DETECT_0_ASSERT)
80901 #define F_Q1_SIGNAL_DETECT_0_ASSERT    V_Q1_SIGNAL_DETECT_0_ASSERT(1U)
80904 #define V_Q1_CDR_LOL_3_ASSERT(x) ((x) << S_Q1_CDR_LOL_3_ASSERT)
80905 #define F_Q1_CDR_LOL_3_ASSERT    V_Q1_CDR_LOL_3_ASSERT(1U)
80908 #define V_Q1_CDR_LOL_2_ASSERT(x) ((x) << S_Q1_CDR_LOL_2_ASSERT)
80909 #define F_Q1_CDR_LOL_2_ASSERT    V_Q1_CDR_LOL_2_ASSERT(1U)
80912 #define V_Q1_CDR_LOL_1_ASSERT(x) ((x) << S_Q1_CDR_LOL_1_ASSERT)
80913 #define F_Q1_CDR_LOL_1_ASSERT    V_Q1_CDR_LOL_1_ASSERT(1U)
80916 #define V_Q1_CDR_LOL_0_ASSERT(x) ((x) << S_Q1_CDR_LOL_0_ASSERT)
80917 #define F_Q1_CDR_LOL_0_ASSERT    V_Q1_CDR_LOL_0_ASSERT(1U)
80920 #define V_Q1_LOS_3_ASSERT(x) ((x) << S_Q1_LOS_3_ASSERT)
80921 #define F_Q1_LOS_3_ASSERT    V_Q1_LOS_3_ASSERT(1U)
80924 #define V_Q1_LOS_2_ASSERT(x) ((x) << S_Q1_LOS_2_ASSERT)
80925 #define F_Q1_LOS_2_ASSERT    V_Q1_LOS_2_ASSERT(1U)
80927 #define S_Q1_LOS_1_ASSERT    1
80928 #define V_Q1_LOS_1_ASSERT(x) ((x) << S_Q1_LOS_1_ASSERT)
80929 #define F_Q1_LOS_1_ASSERT    V_Q1_LOS_1_ASSERT(1U)
80932 #define V_Q1_LOS_0_ASSERT(x) ((x) << S_Q1_LOS_0_ASSERT)
80933 #define F_Q1_LOS_0_ASSERT    V_Q1_LOS_0_ASSERT(1U)
80939 #define V_SPEED_SEL_1(x) ((x) << S_SPEED_SEL_1)
80940 #define F_SPEED_SEL_1    V_SPEED_SEL_1(1U)
80943 #define V_AUTO_NEG_ENA(x) ((x) << S_AUTO_NEG_ENA)
80944 #define F_AUTO_NEG_ENA    V_AUTO_NEG_ENA(1U)
80947 #define V_T7_POWER_DOWN(x) ((x) << S_T7_POWER_DOWN)
80948 #define F_T7_POWER_DOWN    V_T7_POWER_DOWN(1U)
80951 #define V_RESTART_AUTO_NEG(x) ((x) << S_RESTART_AUTO_NEG)
80952 #define F_RESTART_AUTO_NEG    V_RESTART_AUTO_NEG(1U)
80955 #define V_SPEED_SEL_0(x) ((x) << S_SPEED_SEL_0)
80956 #define F_SPEED_SEL_0    V_SPEED_SEL_0(1U)
80961 #define V_100BASE_T4(x) ((x) << S_100BASE_T4)
80962 #define F_100BASE_T4    V_100BASE_T4(1U)
80965 #define V_100BASE_X_FULL_DUPLEX(x) ((x) << S_100BASE_X_FULL_DUPLEX)
80966 #define F_100BASE_X_FULL_DUPLEX    V_100BASE_X_FULL_DUPLEX(1U)
80969 #define V_100BASE_X_HALF_DUPLEX(x) ((x) << S_100BASE_X_HALF_DUPLEX)
80970 #define F_100BASE_X_HALF_DUPLEX    V_100BASE_X_HALF_DUPLEX(1U)
80973 #define V_10MBPS_FULL_DUPLEX(x) ((x) << S_10MBPS_FULL_DUPLEX)
80974 #define F_10MBPS_FULL_DUPLEX    V_10MBPS_FULL_DUPLEX(1U)
80977 #define V_10MBPS_HALF_DUPLEX(x) ((x) << S_10MBPS_HALF_DUPLEX)
80978 #define F_10MBPS_HALF_DUPLEX    V_10MBPS_HALF_DUPLEX(1U)
80981 #define V_100BASE_T2_HALF_DUPLEX1(x) ((x) << S_100BASE_T2_HALF_DUPLEX1)
80982 #define F_100BASE_T2_HALF_DUPLEX1    V_100BASE_T2_HALF_DUPLEX1(1U)
80985 #define V_100BASE_T2_HALF_DUPLEX0(x) ((x) << S_100BASE_T2_HALF_DUPLEX0)
80986 #define F_100BASE_T2_HALF_DUPLEX0    V_100BASE_T2_HALF_DUPLEX0(1U)
80989 #define V_T7_EXTENDED_STATUS(x) ((x) << S_T7_EXTENDED_STATUS)
80990 #define F_T7_EXTENDED_STATUS    V_T7_EXTENDED_STATUS(1U)
80993 #define V_AUTO_NEG_COMPLETE(x) ((x) << S_AUTO_NEG_COMPLETE)
80994 #define F_AUTO_NEG_COMPLETE    V_AUTO_NEG_COMPLETE(1U)
80997 #define V_T7_REMOTE_FAULT(x) ((x) << S_T7_REMOTE_FAULT)
80998 #define F_T7_REMOTE_FAULT    V_T7_REMOTE_FAULT(1U)
81001 #define V_AUTO_NEG_ABILITY(x) ((x) << S_AUTO_NEG_ABILITY)
81002 #define F_AUTO_NEG_ABILITY    V_AUTO_NEG_ABILITY(1U)
81004 #define S_JABBER_DETECT    1
81005 #define V_JABBER_DETECT(x) ((x) << S_JABBER_DETECT)
81006 #define F_JABBER_DETECT    V_JABBER_DETECT(1U)
81009 #define V_EXTENDED_CAPABILITY(x) ((x) << S_EXTENDED_CAPABILITY)
81010 #define F_EXTENDED_CAPABILITY    V_EXTENDED_CAPABILITY(1U)
81017 #define V_EEE_CLOCK_STOP_ENABLE(x) ((x) << S_EEE_CLOCK_STOP_ENABLE)
81018 #define F_EEE_CLOCK_STOP_ENABLE    V_EEE_CLOCK_STOP_ENABLE(1U)
81023 #define V_COPPER_LINK_STATUS(x) ((x) << S_COPPER_LINK_STATUS)
81024 #define F_COPPER_LINK_STATUS    V_COPPER_LINK_STATUS(1U)
81027 #define V_COPPER_DUPLEX_STATUS(x) ((x) << S_COPPER_DUPLEX_STATUS)
81028 #define F_COPPER_DUPLEX_STATUS    V_COPPER_DUPLEX_STATUS(1U)
81032 #define V_COPPER_SPEED(x) ((x) << S_COPPER_SPEED)
81033 #define G_COPPER_SPEED(x) (((x) >> S_COPPER_SPEED) & M_COPPER_SPEED)
81036 #define V_EEE_CAPABILITY(x) ((x) << S_EEE_CAPABILITY)
81037 #define F_EEE_CAPABILITY    V_EEE_CAPABILITY(1U)
81040 #define V_EEE_CLOCK_STOP_CAPABILITY(x) ((x) << S_EEE_CLOCK_STOP_CAPABILITY)
81041 #define F_EEE_CLOCK_STOP_CAPABILITY    V_EEE_CLOCK_STOP_CAPABILITY(1U)
81049 #define V_T7_DATA(x) ((x) << S_T7_DATA)
81050 #define G_T7_DATA(x) (((x) >> S_T7_DATA) & M_T7_DATA)
81059 #define V_LINK_TIMER_VAL(x) ((x) << S_LINK_TIMER_VAL)
81060 #define G_LINK_TIMER_VAL(x) (((x) >> S_LINK_TIMER_VAL) & M_LINK_TIMER_VAL)
81066 #define V_T7_LINK_TIMER_VAL(x) ((x) << S_T7_LINK_TIMER_VAL)
81067 #define G_T7_LINK_TIMER_VAL(x) (((x) >> S_T7_LINK_TIMER_VAL) & M_T7_LINK_TIMER_VAL)
81074 #define V_SGPCS_ENA_ST(x) ((x) << S_SGPCS_ENA_ST)
81075 #define F_SGPCS_ENA_ST    V_SGPCS_ENA_ST(1U)
81079 #define V_T7_CFG_CLOCK_RATE(x) ((x) << S_T7_CFG_CLOCK_RATE)
81080 #define G_T7_CFG_CLOCK_RATE(x) (((x) >> S_T7_CFG_CLOCK_RATE) & M_T7_CFG_CLOCK_RATE)
81083 #define V_SGPCS_ENA_R(x) ((x) << S_SGPCS_ENA_R)
81084 #define F_SGPCS_ENA_R    V_SGPCS_ENA_R(1U)
81090 #define V_SD_BIT_SLIP(x) ((x) << S_SD_BIT_SLIP)
81091 #define G_SD_BIT_SLIP(x) (((x) >> S_SD_BIT_SLIP) & M_SD_BIT_SLIP)
81150 #define V_LOCAL_FAULT_OVRD(x) ((x) << S_LOCAL_FAULT_OVRD)
81151 #define F_LOCAL_FAULT_OVRD    V_LOCAL_FAULT_OVRD(1U)
81154 #define V_LOCAL_FAULT_HOLD_EN(x) ((x) << S_LOCAL_FAULT_HOLD_EN)
81155 #define F_LOCAL_FAULT_HOLD_EN    V_LOCAL_FAULT_HOLD_EN(1U)
81158 #define V_DPLL_RST(x) ((x) << S_DPLL_RST)
81159 #define F_DPLL_RST    V_DPLL_RST(1U)
81163 #define V_CNTOFFSET(x) ((x) << S_CNTOFFSET)
81164 #define G_CNTOFFSET(x) (((x) >> S_CNTOFFSET) & M_CNTOFFSET)
81170 #define V_DELAYK(x) ((x) << S_DELAYK)
81171 #define G_DELAYK(x) (((x) >> S_DELAYK) & M_DELAYK)
81177 #define V_DIVFFB(x) ((x) << S_DIVFFB)
81178 #define G_DIVFFB(x) (((x) >> S_DIVFFB) & M_DIVFFB)
81182 #define V_DIVFIN(x) ((x) << S_DIVFIN)
81183 #define G_DIVFIN(x) (((x) >> S_DIVFIN) & M_DIVFIN)
81189 #define V_ISHIFT_HOLD(x) ((x) << S_ISHIFT_HOLD)
81190 #define G_ISHIFT_HOLD(x) (((x) >> S_ISHIFT_HOLD) & M_ISHIFT_HOLD)
81194 #define V_ISHIFT(x) ((x) << S_ISHIFT)
81195 #define G_ISHIFT(x) (((x) >> S_ISHIFT) & M_ISHIFT)
81199 #define V_INT_PRESET(x) ((x) << S_INT_PRESET)
81200 #define G_INT_PRESET(x) (((x) >> S_INT_PRESET) & M_INT_PRESET)
81204 #define V_FMI(x) ((x) << S_FMI)
81205 #define G_FMI(x) (((x) >> S_FMI) & M_FMI)
81208 #define V_DPLL_PROGRAM(x) ((x) << S_DPLL_PROGRAM)
81209 #define F_DPLL_PROGRAM    V_DPLL_PROGRAM(1U)
81212 #define V_PRESET_EN(x) ((x) << S_PRESET_EN)
81213 #define F_PRESET_EN    V_PRESET_EN(1U)
81215 #define S_ONTARGETOV    1
81216 #define V_ONTARGETOV(x) ((x) << S_ONTARGETOV)
81217 #define F_ONTARGETOV    V_ONTARGETOV(1U)
81220 #define V_FDONLY(x) ((x) << S_FDONLY)
81221 #define F_FDONLY    V_FDONLY(1U)
81227 #define V_FKI(x) ((x) << S_FKI)
81228 #define G_FKI(x) (((x) >> S_FKI) & M_FKI)
81232 #define V_FRAC_PRESET(x) ((x) << S_FRAC_PRESET)
81233 #define G_FRAC_PRESET(x) (((x) >> S_FRAC_PRESET) & M_FRAC_PRESET)
81239 #define V_PH_STEP_CNT_HOLD(x) ((x) << S_PH_STEP_CNT_HOLD)
81240 #define G_PH_STEP_CNT_HOLD(x) (((x) >> S_PH_STEP_CNT_HOLD) & M_PH_STEP_CNT_HOLD)
81243 #define V_CFG_RESET(x) ((x) << S_CFG_RESET)
81244 #define F_CFG_RESET    V_CFG_RESET(1U)
81248 #define V_PH_STEP_CNT(x) ((x) << S_PH_STEP_CNT)
81249 #define G_PH_STEP_CNT(x) (((x) >> S_PH_STEP_CNT) & M_PH_STEP_CNT)
81253 #define V_OTDLY(x) ((x) << S_OTDLY)
81254 #define G_OTDLY(x) (((x) >> S_OTDLY) & M_OTDLY)
81260 #define V_TARGETCNT(x) ((x) << S_TARGETCNT)
81261 #define G_TARGETCNT(x) (((x) >> S_TARGETCNT) & M_TARGETCNT)
81265 #define V_PKP(x) ((x) << S_PKP)
81266 #define G_PKP(x) (((x) >> S_PKP) & M_PKP)
81270 #define V_PMP(x) ((x) << S_PMP)
81271 #define G_PMP(x) (((x) >> S_PMP) & M_PMP)
81278 #define V_FRAC(x) ((x) << S_FRAC)
81279 #define G_FRAC(x) (((x) >> S_FRAC) & M_FRAC)
81285 #define V_FRAC_PD_OUT(x) ((x) << S_FRAC_PD_OUT)
81286 #define G_FRAC_PD_OUT(x) (((x) >> S_FRAC_PD_OUT) & M_FRAC_PD_OUT)
81292 #define V_INT(x) ((x) << S_INT)
81293 #define G_INT(x) (((x) >> S_INT) & M_INT)
81297 #define V_INT_PD_OUT(x) ((x) << S_INT_PD_OUT)
81298 #define G_INT_PD_OUT(x) (((x) >> S_INT_PD_OUT) & M_INT_PD_OUT)
81304 #define V_FRAC_N_DSKEWCALCNT(x) ((x) << S_FRAC_N_DSKEWCALCNT)
81305 #define G_FRAC_N_DSKEWCALCNT(x) (((x) >> S_FRAC_N_DSKEWCALCNT) & M_FRAC_N_DSKEWCALCNT)
81308 #define V_PLLEN(x) ((x) << S_PLLEN)
81309 #define F_PLLEN    V_PLLEN(1U)
81313 #define V_T7_BYPASS(x) ((x) << S_T7_BYPASS)
81314 #define G_T7_BYPASS(x) (((x) >> S_T7_BYPASS) & M_T7_BYPASS)
81318 #define V_POSTDIV3A(x) ((x) << S_POSTDIV3A)
81319 #define G_POSTDIV3A(x) (((x) >> S_POSTDIV3A) & M_POSTDIV3A)
81323 #define V_POSTDIV3B(x) ((x) << S_POSTDIV3B)
81324 #define G_POSTDIV3B(x) (((x) >> S_POSTDIV3B) & M_POSTDIV3B)
81328 #define V_POSTDIV2A(x) ((x) << S_POSTDIV2A)
81329 #define G_POSTDIV2A(x) (((x) >> S_POSTDIV2A) & M_POSTDIV2A)
81333 #define V_POSTDIV2B(x) ((x) << S_POSTDIV2B)
81334 #define G_POSTDIV2B(x) (((x) >> S_POSTDIV2B) & M_POSTDIV2B)
81338 #define V_POSTDIV1A(x) ((x) << S_POSTDIV1A)
81339 #define G_POSTDIV1A(x) (((x) >> S_POSTDIV1A) & M_POSTDIV1A)
81343 #define V_POSTDIV1B(x) ((x) << S_POSTDIV1B)
81344 #define G_POSTDIV1B(x) (((x) >> S_POSTDIV1B) & M_POSTDIV1B)
81348 #define V_POSTDIV0A(x) ((x) << S_POSTDIV0A)
81349 #define G_POSTDIV0A(x) (((x) >> S_POSTDIV0A) & M_POSTDIV0A)
81353 #define V_POSTDIV0B(x) ((x) << S_POSTDIV0B)
81354 #define G_POSTDIV0B(x) (((x) >> S_POSTDIV0B) & M_POSTDIV0B)
81360 #define V_FRAC_N_FRAC_N_FOUTEN(x) ((x) << S_FRAC_N_FRAC_N_FOUTEN)
81361 #define G_FRAC_N_FRAC_N_FOUTEN(x) (((x) >> S_FRAC_N_FRAC_N_FOUTEN) & M_FRAC_N_FRAC_N_FOUTEN)
81365 #define V_FRAC_N_DSKEWCALIN(x) ((x) << S_FRAC_N_DSKEWCALIN)
81366 #define G_FRAC_N_DSKEWCALIN(x) (((x) >> S_FRAC_N_DSKEWCALIN) & M_FRAC_N_DSKEWCALIN)
81370 #define V_FRAC_N_REFDIV(x) ((x) << S_FRAC_N_REFDIV)
81371 #define G_FRAC_N_REFDIV(x) (((x) >> S_FRAC_N_REFDIV) & M_FRAC_N_REFDIV)
81374 #define V_FRAC_N_DSMEN(x) ((x) << S_FRAC_N_DSMEN)
81375 #define F_FRAC_N_DSMEN    V_FRAC_N_DSMEN(1U)
81378 #define V_FRAC_N_PLLEN(x) ((x) << S_FRAC_N_PLLEN)
81379 #define F_FRAC_N_PLLEN    V_FRAC_N_PLLEN(1U)
81382 #define V_FRAC_N_DACEN(x) ((x) << S_FRAC_N_DACEN)
81383 #define F_FRAC_N_DACEN    V_FRAC_N_DACEN(1U)
81386 #define V_FRAC_N_POSTDIV0PRE(x) ((x) << S_FRAC_N_POSTDIV0PRE)
81387 #define F_FRAC_N_POSTDIV0PRE    V_FRAC_N_POSTDIV0PRE(1U)
81390 #define V_FRAC_N_DSKEWCALBYP(x) ((x) << S_FRAC_N_DSKEWCALBYP)
81391 #define F_FRAC_N_DSKEWCALBYP    V_FRAC_N_DSKEWCALBYP(1U)
81394 #define V_FRAC_N_DSKEWFASTCAL(x) ((x) << S_FRAC_N_DSKEWFASTCAL)
81395 #define F_FRAC_N_DSKEWFASTCAL    V_FRAC_N_DSKEWFASTCAL(1U)
81398 #define V_FRAC_N_DSKEWCALEN(x) ((x) << S_FRAC_N_DSKEWCALEN)
81399 #define F_FRAC_N_DSKEWCALEN    V_FRAC_N_DSKEWCALEN(1U)
81402 #define V_FRAC_N_FREFCMLEN(x) ((x) << S_FRAC_N_FREFCMLEN)
81403 #define F_FRAC_N_FREFCMLEN    V_FRAC_N_FREFCMLEN(1U)
81408 #define V_DSKEWCALLOCK(x) ((x) << S_DSKEWCALLOCK)
81409 #define F_DSKEWCALLOCK    V_DSKEWCALLOCK(1U)
81413 #define V_DSKEWCALOUT(x) ((x) << S_DSKEWCALOUT)
81414 #define G_DSKEWCALOUT(x) (((x) >> S_DSKEWCALOUT) & M_DSKEWCALOUT)
81420 #define V_XLGMII7_TX_TSU(x) ((x) << S_XLGMII7_TX_TSU)
81421 #define G_XLGMII7_TX_TSU(x) (((x) >> S_XLGMII7_TX_TSU) & M_XLGMII7_TX_TSU)
81425 #define V_XLGMII6_TX_TSU(x) ((x) << S_XLGMII6_TX_TSU)
81426 #define G_XLGMII6_TX_TSU(x) (((x) >> S_XLGMII6_TX_TSU) & M_XLGMII6_TX_TSU)
81430 #define V_XLGMII5_TX_TSU(x) ((x) << S_XLGMII5_TX_TSU)
81431 #define G_XLGMII5_TX_TSU(x) (((x) >> S_XLGMII5_TX_TSU) & M_XLGMII5_TX_TSU)
81435 #define V_XLGMII4_TX_TSU(x) ((x) << S_XLGMII4_TX_TSU)
81436 #define G_XLGMII4_TX_TSU(x) (((x) >> S_XLGMII4_TX_TSU) & M_XLGMII4_TX_TSU)
81440 #define V_XLGMII3_TX_TSU(x) ((x) << S_XLGMII3_TX_TSU)
81441 #define G_XLGMII3_TX_TSU(x) (((x) >> S_XLGMII3_TX_TSU) & M_XLGMII3_TX_TSU)
81445 #define V_XLGMII2_TX_TSU(x) ((x) << S_XLGMII2_TX_TSU)
81446 #define G_XLGMII2_TX_TSU(x) (((x) >> S_XLGMII2_TX_TSU) & M_XLGMII2_TX_TSU)
81450 #define V_XLGMII1_TX_TSU(x) ((x) << S_XLGMII1_TX_TSU)
81451 #define G_XLGMII1_TX_TSU(x) (((x) >> S_XLGMII1_TX_TSU) & M_XLGMII1_TX_TSU)
81455 #define V_XLGMII0_TX_TSU(x) ((x) << S_XLGMII0_TX_TSU)
81456 #define G_XLGMII0_TX_TSU(x) (((x) >> S_XLGMII0_TX_TSU) & M_XLGMII0_TX_TSU)
81460 #define V_CGMII3_TX_TSU(x) ((x) << S_CGMII3_TX_TSU)
81461 #define G_CGMII3_TX_TSU(x) (((x) >> S_CGMII3_TX_TSU) & M_CGMII3_TX_TSU)
81465 #define V_CGMII2_TX_TSU(x) ((x) << S_CGMII2_TX_TSU)
81466 #define G_CGMII2_TX_TSU(x) (((x) >> S_CGMII2_TX_TSU) & M_CGMII2_TX_TSU)
81470 #define V_CGMII1_TX_TSU(x) ((x) << S_CGMII1_TX_TSU)
81471 #define G_CGMII1_TX_TSU(x) (((x) >> S_CGMII1_TX_TSU) & M_CGMII1_TX_TSU)
81475 #define V_CGMII0_TX_TSU(x) ((x) << S_CGMII0_TX_TSU)
81476 #define G_CGMII0_TX_TSU(x) (((x) >> S_CGMII0_TX_TSU) & M_CGMII0_TX_TSU)
81482 #define V_CDMII1_RX_TSU(x) ((x) << S_CDMII1_RX_TSU)
81483 #define G_CDMII1_RX_TSU(x) (((x) >> S_CDMII1_RX_TSU) & M_CDMII1_RX_TSU)
81487 #define V_CDMII0_RX_TSU(x) ((x) << S_CDMII0_RX_TSU)
81488 #define G_CDMII0_RX_TSU(x) (((x) >> S_CDMII0_RX_TSU) & M_CDMII0_RX_TSU)
81492 #define V_XLGMII7_RX_TSU(x) ((x) << S_XLGMII7_RX_TSU)
81493 #define G_XLGMII7_RX_TSU(x) (((x) >> S_XLGMII7_RX_TSU) & M_XLGMII7_RX_TSU)
81497 #define V_XLGMII6_RX_TSU(x) ((x) << S_XLGMII6_RX_TSU)
81498 #define G_XLGMII6_RX_TSU(x) (((x) >> S_XLGMII6_RX_TSU) & M_XLGMII6_RX_TSU)
81502 #define V_XLGMII5_RX_TSU(x) ((x) << S_XLGMII5_RX_TSU)
81503 #define G_XLGMII5_RX_TSU(x) (((x) >> S_XLGMII5_RX_TSU) & M_XLGMII5_RX_TSU)
81507 #define V_XLGMII4_RX_TSU(x) ((x) << S_XLGMII4_RX_TSU)
81508 #define G_XLGMII4_RX_TSU(x) (((x) >> S_XLGMII4_RX_TSU) & M_XLGMII4_RX_TSU)
81512 #define V_XLGMII3_RX_TSU(x) ((x) << S_XLGMII3_RX_TSU)
81513 #define G_XLGMII3_RX_TSU(x) (((x) >> S_XLGMII3_RX_TSU) & M_XLGMII3_RX_TSU)
81517 #define V_XLGMII2_RX_TSU(x) ((x) << S_XLGMII2_RX_TSU)
81518 #define G_XLGMII2_RX_TSU(x) (((x) >> S_XLGMII2_RX_TSU) & M_XLGMII2_RX_TSU)
81522 #define V_XLGMII1_RX_TSU(x) ((x) << S_XLGMII1_RX_TSU)
81523 #define G_XLGMII1_RX_TSU(x) (((x) >> S_XLGMII1_RX_TSU) & M_XLGMII1_RX_TSU)
81527 #define V_XLGMII0_RX_TSU(x) ((x) << S_XLGMII0_RX_TSU)
81528 #define G_XLGMII0_RX_TSU(x) (((x) >> S_XLGMII0_RX_TSU) & M_XLGMII0_RX_TSU)
81532 #define V_CGMII3_RX_TSU(x) ((x) << S_CGMII3_RX_TSU)
81533 #define G_CGMII3_RX_TSU(x) (((x) >> S_CGMII3_RX_TSU) & M_CGMII3_RX_TSU)
81537 #define V_CGMII2_RX_TSU(x) ((x) << S_CGMII2_RX_TSU)
81538 #define G_CGMII2_RX_TSU(x) (((x) >> S_CGMII2_RX_TSU) & M_CGMII2_RX_TSU)
81542 #define V_CGMII1_RX_TSU(x) ((x) << S_CGMII1_RX_TSU)
81543 #define G_CGMII1_RX_TSU(x) (((x) >> S_CGMII1_RX_TSU) & M_CGMII1_RX_TSU)
81547 #define V_CGMII0_RX_TSU(x) ((x) << S_CGMII0_RX_TSU)
81548 #define G_CGMII0_RX_TSU(x) (((x) >> S_CGMII0_RX_TSU) & M_CGMII0_RX_TSU)
81554 #define V_SD_BIT_SLIP_0(x) ((x) << S_SD_BIT_SLIP_0)
81555 #define G_SD_BIT_SLIP_0(x) (((x) >> S_SD_BIT_SLIP_0) & M_SD_BIT_SLIP_0)
81561 #define V_SD_BIT_SLIP_1(x) ((x) << S_SD_BIT_SLIP_1)
81562 #define G_SD_BIT_SLIP_1(x) (((x) >> S_SD_BIT_SLIP_1) & M_SD_BIT_SLIP_1)
81568 #define V_TSU_RX_SD(x) ((x) << S_TSU_RX_SD)
81569 #define G_TSU_RX_SD(x) (((x) >> S_TSU_RX_SD) & M_TSU_RX_SD)
81575 #define V_RSFEC_XSTATS_STRB(x) ((x) << S_RSFEC_XSTATS_STRB)
81576 #define G_RSFEC_XSTATS_STRB(x) (((x) >> S_RSFEC_XSTATS_STRB) & M_RSFEC_XSTATS_STRB)
81584 #define V_TSV_XON_STB_2(x) ((x) << S_TSV_XON_STB_2)
81585 #define G_TSV_XON_STB_2(x) (((x) >> S_TSV_XON_STB_2) & M_TSV_XON_STB_2)
81589 #define V_TSV_XOFF_STB_2(x) ((x) << S_TSV_XOFF_STB_2)
81590 #define G_TSV_XOFF_STB_2(x) (((x) >> S_TSV_XOFF_STB_2) & M_TSV_XOFF_STB_2)
81594 #define V_RSV_XON_STB_2(x) ((x) << S_RSV_XON_STB_2)
81595 #define G_RSV_XON_STB_2(x) (((x) >> S_RSV_XON_STB_2) & M_RSV_XON_STB_2)
81599 #define V_RSV_XOFF_STB_2(x) ((x) << S_RSV_XOFF_STB_2)
81600 #define G_RSV_XOFF_STB_2(x) (((x) >> S_RSV_XOFF_STB_2) & M_RSV_XOFF_STB_2)
81606 #define V_TSV_XON_STB_3(x) ((x) << S_TSV_XON_STB_3)
81607 #define G_TSV_XON_STB_3(x) (((x) >> S_TSV_XON_STB_3) & M_TSV_XON_STB_3)
81611 #define V_TSV_XOFF_STB_3(x) ((x) << S_TSV_XOFF_STB_3)
81612 #define G_TSV_XOFF_STB_3(x) (((x) >> S_TSV_XOFF_STB_3) & M_TSV_XOFF_STB_3)
81616 #define V_RSV_XON_STB_3(x) ((x) << S_RSV_XON_STB_3)
81617 #define G_RSV_XON_STB_3(x) (((x) >> S_RSV_XON_STB_3) & M_RSV_XON_STB_3)
81621 #define V_RSV_XOFF_STB_3(x) ((x) << S_RSV_XOFF_STB_3)
81622 #define G_RSV_XOFF_STB_3(x) (((x) >> S_RSV_XOFF_STB_3) & M_RSV_XOFF_STB_3)
81628 #define V_TSV_XON_STB_4(x) ((x) << S_TSV_XON_STB_4)
81629 #define G_TSV_XON_STB_4(x) (((x) >> S_TSV_XON_STB_4) & M_TSV_XON_STB_4)
81633 #define V_TSV_XOFF_STB_4(x) ((x) << S_TSV_XOFF_STB_4)
81634 #define G_TSV_XOFF_STB_4(x) (((x) >> S_TSV_XOFF_STB_4) & M_TSV_XOFF_STB_4)
81638 #define V_RSV_XON_STB_4(x) ((x) << S_RSV_XON_STB_4)
81639 #define G_RSV_XON_STB_4(x) (((x) >> S_RSV_XON_STB_4) & M_RSV_XON_STB_4)
81643 #define V_RSV_XOFF_STB_4(x) ((x) << S_RSV_XOFF_STB_4)
81644 #define G_RSV_XOFF_STB_4(x) (((x) >> S_RSV_XOFF_STB_4) & M_RSV_XOFF_STB_4)
81650 #define V_TSV_XON_STB_5(x) ((x) << S_TSV_XON_STB_5)
81651 #define G_TSV_XON_STB_5(x) (((x) >> S_TSV_XON_STB_5) & M_TSV_XON_STB_5)
81655 #define V_TSV_XOFF_STB_5(x) ((x) << S_TSV_XOFF_STB_5)
81656 #define G_TSV_XOFF_STB_5(x) (((x) >> S_TSV_XOFF_STB_5) & M_TSV_XOFF_STB_5)
81660 #define V_RSV_XON_STB_5(x) ((x) << S_RSV_XON_STB_5)
81661 #define G_RSV_XON_STB_5(x) (((x) >> S_RSV_XON_STB_5) & M_RSV_XON_STB_5)
81665 #define V_RSV_XOFF_STB_5(x) ((x) << S_RSV_XOFF_STB_5)
81666 #define G_RSV_XOFF_STB_5(x) (((x) >> S_RSV_XOFF_STB_5) & M_RSV_XOFF_STB_5)
81671 #define V_TX_SFD_O_5(x) ((x) << S_TX_SFD_O_5)
81672 #define F_TX_SFD_O_5    V_TX_SFD_O_5(1U)
81675 #define V_TX_SFD_O_4(x) ((x) << S_TX_SFD_O_4)
81676 #define F_TX_SFD_O_4    V_TX_SFD_O_4(1U)
81679 #define V_TX_SFD_O_3(x) ((x) << S_TX_SFD_O_3)
81680 #define F_TX_SFD_O_3    V_TX_SFD_O_3(1U)
81683 #define V_TX_SFD_O_2(x) ((x) << S_TX_SFD_O_2)
81684 #define F_TX_SFD_O_2    V_TX_SFD_O_2(1U)
81687 #define V_RX_SFD_O_5(x) ((x) << S_RX_SFD_O_5)
81688 #define F_RX_SFD_O_5    V_RX_SFD_O_5(1U)
81691 #define V_RX_SFD_O_4(x) ((x) << S_RX_SFD_O_4)
81692 #define F_RX_SFD_O_4    V_RX_SFD_O_4(1U)
81695 #define V_RX_SFD_O_3(x) ((x) << S_RX_SFD_O_3)
81696 #define F_RX_SFD_O_3    V_RX_SFD_O_3(1U)
81699 #define V_RX_SFD_O_2(x) ((x) << S_RX_SFD_O_2)
81700 #define F_RX_SFD_O_2    V_RX_SFD_O_2(1U)
81703 #define V_RX_SFD_SHIFT_O_5(x) ((x) << S_RX_SFD_SHIFT_O_5)
81704 #define F_RX_SFD_SHIFT_O_5    V_RX_SFD_SHIFT_O_5(1U)
81707 #define V_RX_SFD_SHIFT_O_4(x) ((x) << S_RX_SFD_SHIFT_O_4)
81708 #define F_RX_SFD_SHIFT_O_4    V_RX_SFD_SHIFT_O_4(1U)
81711 #define V_RX_SFD_SHIFT_O_3(x) ((x) << S_RX_SFD_SHIFT_O_3)
81712 #define F_RX_SFD_SHIFT_O_3    V_RX_SFD_SHIFT_O_3(1U)
81715 #define V_RX_SFD_SHIFT_O_2(x) ((x) << S_RX_SFD_SHIFT_O_2)
81716 #define F_RX_SFD_SHIFT_O_2    V_RX_SFD_SHIFT_O_2(1U)
81719 #define V_TX_SFD_SHIFT_O_5(x) ((x) << S_TX_SFD_SHIFT_O_5)
81720 #define F_TX_SFD_SHIFT_O_5    V_TX_SFD_SHIFT_O_5(1U)
81723 #define V_TX_SFD_SHIFT_O_4(x) ((x) << S_TX_SFD_SHIFT_O_4)
81724 #define F_TX_SFD_SHIFT_O_4    V_TX_SFD_SHIFT_O_4(1U)
81727 #define V_TX_SFD_SHIFT_O_3(x) ((x) << S_TX_SFD_SHIFT_O_3)
81728 #define F_TX_SFD_SHIFT_O_3    V_TX_SFD_SHIFT_O_3(1U)
81731 #define V_TX_SFD_SHIFT_O_2(x) ((x) << S_TX_SFD_SHIFT_O_2)
81732 #define F_TX_SFD_SHIFT_O_2    V_TX_SFD_SHIFT_O_2(1U)
81735 #define V_TS_SFD_ENA_5(x) ((x) << S_TS_SFD_ENA_5)
81736 #define F_TS_SFD_ENA_5    V_TS_SFD_ENA_5(1U)
81739 #define V_TS_SFD_ENA_4(x) ((x) << S_TS_SFD_ENA_4)
81740 #define F_TS_SFD_ENA_4    V_TS_SFD_ENA_4(1U)
81742 #define S_TS_SFD_ENA_3    1
81743 #define V_TS_SFD_ENA_3(x) ((x) << S_TS_SFD_ENA_3)
81744 #define F_TS_SFD_ENA_3    V_TS_SFD_ENA_3(1U)
81747 #define V_TS_SFD_ENA_2(x) ((x) << S_TS_SFD_ENA_2)
81748 #define F_TS_SFD_ENA_2    V_TS_SFD_ENA_2(1U)
81753 #define V_STS_ENA(x) ((x) << S_STS_ENA)
81754 #define F_STS_ENA    V_STS_ENA(1U)
81757 #define V_N_PPS_ENA(x) ((x) << S_N_PPS_ENA)
81758 #define F_N_PPS_ENA    V_N_PPS_ENA(1U)
81761 #define V_STS_RESET(x) ((x) << S_STS_RESET)
81762 #define F_STS_RESET    V_STS_RESET(1U)
81766 #define V_DEBOUNCE_CNT(x) ((x) << S_DEBOUNCE_CNT)
81767 #define G_DEBOUNCE_CNT(x) (((x) >> S_DEBOUNCE_CNT) & M_DEBOUNCE_CNT)
81778 #define V_MAC_BGR_BGR_REG_APB_SEL(x) ((x) << S_MAC_BGR_BGR_REG_APB_SEL)
81779 #define F_MAC_BGR_BGR_REG_APB_SEL    V_MAC_BGR_BGR_REG_APB_SEL(1U)
81784 #define V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(x) ((x) << S_MAC_BGR_BGR_REFCLK_CTRL_BYPASS)
81785 #define F_MAC_BGR_BGR_REFCLK_CTRL_BYPASS    V_MAC_BGR_BGR_REFCLK_CTRL_BYPASS(1U)
81788 #define V_MAC_BGR_BGR_COREREFCLK_SEL(x) ((x) << S_MAC_BGR_BGR_COREREFCLK_SEL)
81789 #define F_MAC_BGR_BGR_COREREFCLK_SEL    V_MAC_BGR_BGR_COREREFCLK_SEL(1U)
81793 #define V_MAC_BGR_BGR_TEST_CLK_DIV(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_DIV)
81794 #define G_MAC_BGR_BGR_TEST_CLK_DIV(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_DIV) & M_MAC_BGR_BGR_TEST_CLK_DIV)
81797 #define V_MAC_BGR_BGR_TEST_CLK_EN(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_EN)
81798 #define F_MAC_BGR_BGR_TEST_CLK_EN    V_MAC_BGR_BGR_TEST_CLK_EN(1U)
81802 #define V_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_BGRSEL)
81803 #define G_MAC_BGR_BGR_TEST_CLK_BGRSEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_BGRSEL) & M_MAC_BGR_BGR_TEST_CLK_BGRSEL)
81807 #define V_MAC_BGR_BGR_TEST_CLK_SEL(x) ((x) << S_MAC_BGR_BGR_TEST_CLK_SEL)
81808 #define G_MAC_BGR_BGR_TEST_CLK_SEL(x) (((x) >> S_MAC_BGR_BGR_TEST_CLK_SEL) & M_MAC_BGR_BGR_TEST_CLK_SEL)
81813 #define V_MAC_BGR_BGR_REG_PRG_EN(x) ((x) << S_MAC_BGR_BGR_REG_PRG_EN)
81814 #define F_MAC_BGR_BGR_REG_PRG_EN    V_MAC_BGR_BGR_REG_PRG_EN(1U)
81819 #define V_MAC_BGR_BGR_REG_GPO(x) ((x) << S_MAC_BGR_BGR_REG_GPO)
81820 #define F_MAC_BGR_BGR_REG_GPO    V_MAC_BGR_BGR_REG_GPO(1U)
81826 #define V_MAC_BGR_CUREFCLKSEL1(x) ((x) << S_MAC_BGR_CUREFCLKSEL1)
81827 #define G_MAC_BGR_CUREFCLKSEL1(x) (((x) >> S_MAC_BGR_CUREFCLKSEL1) & M_MAC_BGR_CUREFCLKSEL1)
81832 #define V_MAC_BGR_IM_CUREFCLKLR_EN(x) ((x) << S_MAC_BGR_IM_CUREFCLKLR_EN)
81833 #define F_MAC_BGR_IM_CUREFCLKLR_EN    V_MAC_BGR_IM_CUREFCLKLR_EN(1U)
81838 #define V_MAC_BGR_IM_REF_EN(x) ((x) << S_MAC_BGR_IM_REF_EN)
81839 #define F_MAC_BGR_IM_REF_EN    V_MAC_BGR_IM_REF_EN(1U)
81844 #define V_MAC_PLL0_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL2_LOCK_STATUS)
81845 #define F_MAC_PLL0_PLL2_LOCK_STATUS    V_MAC_PLL0_PLL2_LOCK_STATUS(1U)
81847 #define S_MAC_PLL0_PLL1_LOCK_STATUS    1
81848 #define V_MAC_PLL0_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL1_LOCK_STATUS)
81849 #define F_MAC_PLL0_PLL1_LOCK_STATUS    V_MAC_PLL0_PLL1_LOCK_STATUS(1U)
81852 #define V_MAC_PLL0_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL0_PLL0_LOCK_STATUS)
81853 #define F_MAC_PLL0_PLL0_LOCK_STATUS    V_MAC_PLL0_PLL0_LOCK_STATUS(1U)
81859 #define V_MAC_PLL0_PLL_PRG_EN(x) ((x) << S_MAC_PLL0_PLL_PRG_EN)
81860 #define G_MAC_PLL0_PLL_PRG_EN(x) (((x) >> S_MAC_PLL0_PLL_PRG_EN) & M_MAC_PLL0_PLL_PRG_EN)
81866 #define V_MAC_PLL0_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL0_PMA_MACRO_SELECT)
81867 #define G_MAC_PLL0_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL0_PMA_MACRO_SELECT) & M_MAC_PLL0_PMA_MACRO_SELECT)
81872 #define V_MAC_PLL1_PLL2_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL2_LOCK_STATUS)
81873 #define F_MAC_PLL1_PLL2_LOCK_STATUS    V_MAC_PLL1_PLL2_LOCK_STATUS(1U)
81875 #define S_MAC_PLL1_PLL1_LOCK_STATUS    1
81876 #define V_MAC_PLL1_PLL1_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL1_LOCK_STATUS)
81877 #define F_MAC_PLL1_PLL1_LOCK_STATUS    V_MAC_PLL1_PLL1_LOCK_STATUS(1U)
81880 #define V_MAC_PLL1_PLL0_LOCK_STATUS(x) ((x) << S_MAC_PLL1_PLL0_LOCK_STATUS)
81881 #define F_MAC_PLL1_PLL0_LOCK_STATUS    V_MAC_PLL1_PLL0_LOCK_STATUS(1U)
81887 #define V_MAC_PLL1_PLL_PRG_EN(x) ((x) << S_MAC_PLL1_PLL_PRG_EN)
81888 #define G_MAC_PLL1_PLL_PRG_EN(x) (((x) >> S_MAC_PLL1_PLL_PRG_EN) & M_MAC_PLL1_PLL_PRG_EN)
81894 #define V_MAC_PLL1_PMA_MACRO_SELECT(x) ((x) << S_MAC_PLL1_PMA_MACRO_SELECT)
81895 #define G_MAC_PLL1_PMA_MACRO_SELECT(x) (((x) >> S_MAC_PLL1_PMA_MACRO_SELECT) & M_MAC_PLL1_PMA_MACRO_SELECT)
81904 #define V_SMALL_LEN_THRESH(x) ((x) << S_SMALL_LEN_THRESH)
81905 #define G_SMALL_LEN_THRESH(x) (((x) >> S_SMALL_LEN_THRESH) & M_SMALL_LEN_THRESH)
81909 #define V_CIPH0_CTL_SEL(x) ((x) << S_CIPH0_CTL_SEL)
81910 #define G_CIPH0_CTL_SEL(x) (((x) >> S_CIPH0_CTL_SEL) & M_CIPH0_CTL_SEL)
81914 #define V_CIPHN_CTL_SEL(x) ((x) << S_CIPHN_CTL_SEL)
81915 #define G_CIPHN_CTL_SEL(x) (((x) >> S_CIPHN_CTL_SEL) & M_CIPHN_CTL_SEL)
81919 #define V_MAC_CTL_SEL(x) ((x) << S_MAC_CTL_SEL)
81920 #define G_MAC_CTL_SEL(x) (((x) >> S_MAC_CTL_SEL) & M_MAC_CTL_SEL)
81923 #define V_CIPH0_XOR_SEL(x) ((x) << S_CIPH0_XOR_SEL)
81924 #define F_CIPH0_XOR_SEL    V_CIPH0_XOR_SEL(1U)
81927 #define V_CIPHN_XOR_SEL(x) ((x) << S_CIPHN_XOR_SEL)
81928 #define F_CIPHN_XOR_SEL    V_CIPHN_XOR_SEL(1U)
81931 #define V_MAC_XOR_SEL(x) ((x) << S_MAC_XOR_SEL)
81932 #define F_MAC_XOR_SEL    V_MAC_XOR_SEL(1U)
81935 #define V_CIPH0_DP_SEL(x) ((x) << S_CIPH0_DP_SEL)
81936 #define F_CIPH0_DP_SEL    V_CIPH0_DP_SEL(1U)
81938 #define S_CIPHN_DP_SEL    1
81939 #define V_CIPHN_DP_SEL(x) ((x) << S_CIPHN_DP_SEL)
81940 #define F_CIPHN_DP_SEL    V_CIPHN_DP_SEL(1U)
81943 #define V_MAC_DP_SEL(x) ((x) << S_MAC_DP_SEL)
81944 #define F_MAC_DP_SEL    V_MAC_DP_SEL(1U)
81950 #define V_KEYLENERR(x) ((x) << S_KEYLENERR)
81951 #define F_KEYLENERR    V_KEYLENERR(1U)
81954 #define V_INTF1_PERR(x) ((x) << S_INTF1_PERR)
81955 #define F_INTF1_PERR    V_INTF1_PERR(1U)
81957 #define S_INTF0_PERR    1
81958 #define V_INTF0_PERR(x) ((x) << S_INTF0_PERR)
81959 #define F_INTF0_PERR    V_INTF0_PERR(1U)
81964 #define V_KEX_CERR(x) ((x) << S_KEX_CERR)
81965 #define F_KEX_CERR    V_KEX_CERR(1U)
81975 #define V_T7_TIMEOUT(x) ((x) << S_T7_TIMEOUT)
81976 #define G_T7_TIMEOUT(x) (((x) >> S_T7_TIMEOUT) & M_T7_TIMEOUT)
81980 #define S_DBG_STEP_CTRL    1
81981 #define V_DBG_STEP_CTRL(x) ((x) << S_DBG_STEP_CTRL)
81982 #define F_DBG_STEP_CTRL    V_DBG_STEP_CTRL(1U)
81985 #define V_DBG_STEP_EN(x) ((x) << S_DBG_STEP_EN)
81986 #define F_DBG_STEP_EN    V_DBG_STEP_EN(1U)
81994 #define V_QUIC_EN(x) ((x) << S_QUIC_EN)
81995 #define F_QUIC_EN    V_QUIC_EN(1U)
81997 #define S_IPSEC_IDX_UPD_EN    1
81998 #define V_IPSEC_IDX_UPD_EN(x) ((x) << S_IPSEC_IDX_UPD_EN)
81999 #define F_IPSEC_IDX_UPD_EN    V_IPSEC_IDX_UPD_EN(1U)
82002 #define V_IPSEC_IDX_CTL(x) ((x) << S_IPSEC_IDX_CTL)
82003 #define F_IPSEC_IDX_CTL    V_IPSEC_IDX_CTL(1U)
82009 #define V_CHCGEN(x) ((x) << S_CHCGEN)
82010 #define G_CHCGEN(x) (((x) >> S_CHCGEN) & M_CHCGEN)
82016 #define V_T7_3_ADDR(x) ((x) << S_T7_3_ADDR)
82017 #define G_T7_3_ADDR(x) (((x) >> S_T7_3_ADDR) & M_T7_3_ADDR)
82029 #define V_DIS_IF_ERR(x) ((x) << S_DIS_IF_ERR)
82030 #define F_DIS_IF_ERR    V_DIS_IF_ERR(1U)
82033 #define V_DIS_ERR_MSG(x) ((x) << S_DIS_ERR_MSG)
82034 #define F_DIS_ERR_MSG    V_DIS_ERR_MSG(1U)
82037 #define V_DIS_BP_SEQF(x) ((x) << S_DIS_BP_SEQF)
82038 #define F_DIS_BP_SEQF    V_DIS_BP_SEQF(1U)
82041 #define V_DIS_BP_LENF(x) ((x) << S_DIS_BP_LENF)
82042 #define F_DIS_BP_LENF    V_DIS_BP_LENF(1U)
82045 #define V_DIS_KEX_ERR(x) ((x) << S_DIS_KEX_ERR)
82046 #define F_DIS_KEX_ERR    V_DIS_KEX_ERR(1U)
82049 #define V_CLR_STS(x) ((x) << S_CLR_STS)
82050 #define F_CLR_STS    V_CLR_STS(1U)
82053 #define V_TGL_CNT(x) ((x) << S_TGL_CNT)
82054 #define F_TGL_CNT    V_TGL_CNT(1U)
82057 #define V_ENB_PAZ(x) ((x) << S_ENB_PAZ)
82058 #define F_ENB_PAZ    V_ENB_PAZ(1U)
82061 #define V_DIS_NOP(x) ((x) << S_DIS_NOP)
82062 #define F_DIS_NOP    V_DIS_NOP(1U)
82064 #define S_DIS_CPL_ERR    1
82065 #define V_DIS_CPL_ERR(x) ((x) << S_DIS_CPL_ERR)
82066 #define F_DIS_CPL_ERR    V_DIS_CPL_ERR(1U)
82069 #define V_DIS_OFF_ERR(x) ((x) << S_DIS_OFF_ERR)
82070 #define F_DIS_OFF_ERR    V_DIS_OFF_ERR(1U)
82102 #define S_ESNWIN    1
82104 #define V_ESNWIN(x) ((x) << S_ESNWIN)
82105 #define G_ESNWIN(x) (((x) >> S_ESNWIN) & M_ESNWIN)
82108 #define V_INGKEY96(x) ((x) << S_INGKEY96)
82109 #define F_INGKEY96    V_INGKEY96(1U)
82113 #define S_CORE1RST    1
82114 #define V_CORE1RST(x) ((x) << S_CORE1RST)
82115 #define F_CORE1RST    V_CORE1RST(1U)
82118 #define V_CORE0RST(x) ((x) << S_CORE0RST)
82119 #define F_CORE0RST    V_CORE0RST(1U)
82124 #define V_MA_FIFO_PERR(x) ((x) << S_MA_FIFO_PERR)
82125 #define F_MA_FIFO_PERR    V_MA_FIFO_PERR(1U)
82128 #define V_MA_RSP_PERR(x) ((x) << S_MA_RSP_PERR)
82129 #define F_MA_RSP_PERR    V_MA_RSP_PERR(1U)
82132 #define V_ING_CACHE_DATA_PERR(x) ((x) << S_ING_CACHE_DATA_PERR)
82133 #define F_ING_CACHE_DATA_PERR    V_ING_CACHE_DATA_PERR(1U)
82136 #define V_ING_CACHE_TAG_PERR(x) ((x) << S_ING_CACHE_TAG_PERR)
82137 #define F_ING_CACHE_TAG_PERR    V_ING_CACHE_TAG_PERR(1U)
82140 #define V_LKP_KEY_REQ_PERR(x) ((x) << S_LKP_KEY_REQ_PERR)
82141 #define F_LKP_KEY_REQ_PERR    V_LKP_KEY_REQ_PERR(1U)
82144 #define V_LKP_CLIP_TCAM_PERR(x) ((x) << S_LKP_CLIP_TCAM_PERR)
82145 #define F_LKP_CLIP_TCAM_PERR    V_LKP_CLIP_TCAM_PERR(1U)
82148 #define V_LKP_MAIN_TCAM_PERR(x) ((x) << S_LKP_MAIN_TCAM_PERR)
82149 #define F_LKP_MAIN_TCAM_PERR    V_LKP_MAIN_TCAM_PERR(1U)
82152 #define V_EGR_KEY_REQ_PERR(x) ((x) << S_EGR_KEY_REQ_PERR)
82153 #define F_EGR_KEY_REQ_PERR    V_EGR_KEY_REQ_PERR(1U)
82156 #define V_EGR_CACHE_DATA_PERR(x) ((x) << S_EGR_CACHE_DATA_PERR)
82157 #define F_EGR_CACHE_DATA_PERR    V_EGR_CACHE_DATA_PERR(1U)
82160 #define V_EGR_CACHE_TAG_PERR(x) ((x) << S_EGR_CACHE_TAG_PERR)
82161 #define F_EGR_CACHE_TAG_PERR    V_EGR_CACHE_TAG_PERR(1U)
82164 #define V_CIM_PERR(x) ((x) << S_CIM_PERR)
82165 #define F_CIM_PERR    V_CIM_PERR(1U)
82168 #define V_MA_INV_RSP_TAG(x) ((x) << S_MA_INV_RSP_TAG)
82169 #define F_MA_INV_RSP_TAG    V_MA_INV_RSP_TAG(1U)
82172 #define V_ING_KEY_RANGE_ERR(x) ((x) << S_ING_KEY_RANGE_ERR)
82173 #define F_ING_KEY_RANGE_ERR    V_ING_KEY_RANGE_ERR(1U)
82176 #define V_ING_MFIFO_OVFL(x) ((x) << S_ING_MFIFO_OVFL)
82177 #define F_ING_MFIFO_OVFL    V_ING_MFIFO_OVFL(1U)
82180 #define V_LKP_REQ_OVFL(x) ((x) << S_LKP_REQ_OVFL)
82181 #define F_LKP_REQ_OVFL    V_LKP_REQ_OVFL(1U)
82184 #define V_EOK_WAIT_ERR(x) ((x) << S_EOK_WAIT_ERR)
82185 #define F_EOK_WAIT_ERR    V_EOK_WAIT_ERR(1U)
82188 #define V_EGR_KEY_RANGE_ERR(x) ((x) << S_EGR_KEY_RANGE_ERR)
82189 #define F_EGR_KEY_RANGE_ERR    V_EGR_KEY_RANGE_ERR(1U)
82192 #define V_EGR_MFIFO_OVFL(x) ((x) << S_EGR_MFIFO_OVFL)
82193 #define F_EGR_MFIFO_OVFL    V_EGR_MFIFO_OVFL(1U)
82196 #define V_SEQ_WRAP_HP_OVFL(x) ((x) << S_SEQ_WRAP_HP_OVFL)
82197 #define F_SEQ_WRAP_HP_OVFL    V_SEQ_WRAP_HP_OVFL(1U)
82200 #define V_SEQ_WRAP_LP_OVFL(x) ((x) << S_SEQ_WRAP_LP_OVFL)
82201 #define F_SEQ_WRAP_LP_OVFL    V_SEQ_WRAP_LP_OVFL(1U)
82203 #define S_EGR_SEQ_WRAP_HP    1
82204 #define V_EGR_SEQ_WRAP_HP(x) ((x) << S_EGR_SEQ_WRAP_HP)
82205 #define F_EGR_SEQ_WRAP_HP    V_EGR_SEQ_WRAP_HP(1U)
82208 #define V_EGR_SEQ_WRAP_LP(x) ((x) << S_EGR_SEQ_WRAP_LP)
82209 #define F_EGR_SEQ_WRAP_LP    V_EGR_SEQ_WRAP_LP(1U)
82216 #define V_KEY_VALID(x) ((x) << S_KEY_VALID)
82217 #define F_KEY_VALID    V_KEY_VALID(1U)
82221 #define V_KEY_ID(x) ((x) << S_KEY_ID)
82222 #define G_KEY_ID(x) (((x) >> S_KEY_ID) & M_KEY_ID)
82232 #define V_SRCHMHIT(x) ((x) << S_SRCHMHIT)
82233 #define F_SRCHMHIT    V_SRCHMHIT(1U)
82236 #define V_T7_BUSY(x) ((x) << S_T7_BUSY)
82237 #define F_T7_BUSY    V_T7_BUSY(1U)
82240 #define V_SRCHHIT(x) ((x) << S_SRCHHIT)
82241 #define F_SRCHHIT    V_SRCHHIT(1U)
82244 #define V_IPVERSION(x) ((x) << S_IPVERSION)
82245 #define F_IPVERSION    V_IPVERSION(1U)
82248 #define V_BITSEL(x) ((x) << S_BITSEL)
82249 #define F_BITSEL    V_BITSEL(1U)
82252 #define V_TCAMSEL(x) ((x) << S_TCAMSEL)
82253 #define F_TCAMSEL    V_TCAMSEL(1U)
82257 #define V_CMDTYPE(x) ((x) << S_CMDTYPE)
82258 #define G_CMDTYPE(x) (((x) >> S_CMDTYPE) & M_CMDTYPE)
82262 #define V_TCAMINDEX(x) ((x) << S_TCAMINDEX)
82263 #define G_TCAMINDEX(x) (((x) >> S_TCAMINDEX) & M_TCAMINDEX)
82268 #define V_T7_CLTCAMDEEPSLEEP_STAT(x) ((x) << S_T7_CLTCAMDEEPSLEEP_STAT)
82269 #define F_T7_CLTCAMDEEPSLEEP_STAT    V_T7_CLTCAMDEEPSLEEP_STAT(1U)
82272 #define V_T7_TCAMDEEPSLEEP_STAT(x) ((x) << S_T7_TCAMDEEPSLEEP_STAT)
82273 #define F_T7_TCAMDEEPSLEEP_STAT    V_T7_TCAMDEEPSLEEP_STAT(1U)
82275 #define S_T7_CLTCAMDEEPSLEEP    1
82276 #define V_T7_CLTCAMDEEPSLEEP(x) ((x) << S_T7_CLTCAMDEEPSLEEP)
82277 #define F_T7_CLTCAMDEEPSLEEP    V_T7_CLTCAMDEEPSLEEP(1U)
82280 #define V_T7_TCAMDEEPSLEEP(x) ((x) << S_T7_TCAMDEEPSLEEP)
82281 #define F_T7_TCAMDEEPSLEEP    V_T7_TCAMDEEPSLEEP(1U)
82290 #define V_TNL_MAX(x) ((x) << S_TNL_MAX)
82291 #define G_TNL_MAX(x) (((x) >> S_TNL_MAX) & M_TNL_MAX)
82295 #define V_TRN_MAX(x) ((x) << S_TRN_MAX)
82296 #define G_TRN_MAX(x) (((x) >> S_TRN_MAX) & M_TRN_MAX)
82301 #define V_ESN(x) ((x) << S_ESN)
82302 #define F_ESN    V_ESN(1U)
82306 #define V_SEQHI(x) ((x) << S_SEQHI)
82307 #define G_SEQHI(x) (((x) >> S_SEQHI) & M_SEQHI)
82311 #define V_KEYID(x) ((x) << S_KEYID)
82312 #define G_KEYID(x) (((x) >> S_KEYID) & M_KEYID)
82320 #define V_MAXKEYS(x) ((x) << S_MAXKEYS)
82321 #define G_MAXKEYS(x) (((x) >> S_MAXKEYS) & M_MAXKEYS)
82331 #define V_SEL_OVR_EN(x) ((x) << S_SEL_OVR_EN)
82332 #define F_SEL_OVR_EN    V_SEL_OVR_EN(1U)
82336 #define V_T7_1_SELH(x) ((x) << S_T7_1_SELH)
82337 #define G_T7_1_SELH(x) (((x) >> S_T7_1_SELH) & M_T7_1_SELH)
82341 #define V_T7_1_SELL(x) ((x) << S_T7_1_SELL)
82342 #define G_T7_1_SELL(x) (((x) >> S_T7_1_SELL) & M_T7_1_SELL)
82353 #define V_CPUPORRSTN3(x) ((x) << S_CPUPORRSTN3)
82354 #define F_CPUPORRSTN3    V_CPUPORRSTN3(1U)
82357 #define V_CPUPORRSTN2(x) ((x) << S_CPUPORRSTN2)
82358 #define F_CPUPORRSTN2    V_CPUPORRSTN2(1U)
82360 #define S_CPUPORRSTN1    1
82361 #define V_CPUPORRSTN1(x) ((x) << S_CPUPORRSTN1)
82362 #define F_CPUPORRSTN1    V_CPUPORRSTN1(1U)
82365 #define V_CPUPORRSTN0(x) ((x) << S_CPUPORRSTN0)
82366 #define F_CPUPORRSTN0    V_CPUPORRSTN0(1U)
82371 #define V_CPUCORERSTN3(x) ((x) << S_CPUCORERSTN3)
82372 #define F_CPUCORERSTN3    V_CPUCORERSTN3(1U)
82375 #define V_CPUCORERSTN2(x) ((x) << S_CPUCORERSTN2)
82376 #define F_CPUCORERSTN2    V_CPUCORERSTN2(1U)
82378 #define S_CPUCORERSTN1    1
82379 #define V_CPUCORERSTN1(x) ((x) << S_CPUCORERSTN1)
82380 #define F_CPUCORERSTN1    V_CPUCORERSTN1(1U)
82383 #define V_CPUCORERSTN0(x) ((x) << S_CPUCORERSTN0)
82384 #define F_CPUCORERSTN0    V_CPUCORERSTN0(1U)
82389 #define V_CPUWARMRSTREQ3(x) ((x) << S_CPUWARMRSTREQ3)
82390 #define F_CPUWARMRSTREQ3    V_CPUWARMRSTREQ3(1U)
82393 #define V_CPUWARMRSTREQ2(x) ((x) << S_CPUWARMRSTREQ2)
82394 #define F_CPUWARMRSTREQ2    V_CPUWARMRSTREQ2(1U)
82396 #define S_CPUWARMRSTREQ1    1
82397 #define V_CPUWARMRSTREQ1(x) ((x) << S_CPUWARMRSTREQ1)
82398 #define F_CPUWARMRSTREQ1    V_CPUWARMRSTREQ1(1U)
82401 #define V_CPUWARMRSTREQ0(x) ((x) << S_CPUWARMRSTREQ0)
82402 #define F_CPUWARMRSTREQ0    V_CPUWARMRSTREQ0(1U)
82407 #define V_CPUL2RSTN(x) ((x) << S_CPUL2RSTN)
82408 #define F_CPUL2RSTN    V_CPUL2RSTN(1U)
82413 #define V_CPUL2RSTDISABLE(x) ((x) << S_CPUL2RSTDISABLE)
82414 #define F_CPUL2RSTDISABLE    V_CPUL2RSTDISABLE(1U)
82419 #define V_CPUPRESETDBGN(x) ((x) << S_CPUPRESETDBGN)
82420 #define F_CPUPRESETDBGN    V_CPUPRESETDBGN(1U)
82426 #define V_PL_DMA_AW_OFFSET(x) ((x) << S_PL_DMA_AW_OFFSET)
82427 #define G_PL_DMA_AW_OFFSET(x) (((x) >> S_PL_DMA_AW_OFFSET) & M_PL_DMA_AW_OFFSET)
82433 #define V_PL_DMA_AR_OFFSET(x) ((x) << S_PL_DMA_AR_OFFSET)
82434 #define G_PL_DMA_AR_OFFSET(x) (((x) >> S_PL_DMA_AR_OFFSET) & M_PL_DMA_AR_OFFSET)
82441 #define V_CPURESETVECBA1(x) ((x) << S_CPURESETVECBA1)
82442 #define G_CPURESETVECBA1(x) (((x) >> S_CPURESETVECBA1) & M_CPURESETVECBA1)
82448 #define V_CPUPMUEVENT(x) ((x) << S_CPUPMUEVENT)
82449 #define G_CPUPMUEVENT(x) (((x) >> S_CPUPMUEVENT) & M_CPUPMUEVENT)
82454 #define V_DMA_PL_RST_N(x) ((x) << S_DMA_PL_RST_N)
82455 #define F_DMA_PL_RST_N    V_DMA_PL_RST_N(1U)
82464 #define V_RC_INT_STATUS_REG(x) ((x) << S_RC_INT_STATUS_REG)
82465 #define G_RC_INT_STATUS_REG(x) (((x) >> S_RC_INT_STATUS_REG) & M_RC_INT_STATUS_REG)
82470 #define V_CPUDBGPWRUPREQ3(x) ((x) << S_CPUDBGPWRUPREQ3)
82471 #define F_CPUDBGPWRUPREQ3    V_CPUDBGPWRUPREQ3(1U)
82474 #define V_CPUDBGPWRUPREQ2(x) ((x) << S_CPUDBGPWRUPREQ2)
82475 #define F_CPUDBGPWRUPREQ2    V_CPUDBGPWRUPREQ2(1U)
82477 #define S_CPUDBGPWRUPREQ1    1
82478 #define V_CPUDBGPWRUPREQ1(x) ((x) << S_CPUDBGPWRUPREQ1)
82479 #define F_CPUDBGPWRUPREQ1    V_CPUDBGPWRUPREQ1(1U)
82482 #define V_CPUDBGPWRUPREQ0(x) ((x) << S_CPUDBGPWRUPREQ0)
82483 #define F_CPUDBGPWRUPREQ0    V_CPUDBGPWRUPREQ0(1U)
82488 #define V_CPUSTANDBYWFIL2(x) ((x) << S_CPUSTANDBYWFIL2)
82489 #define F_CPUSTANDBYWFIL2    V_CPUSTANDBYWFIL2(1U)
82492 #define V_CPUSTANDBYWFI3(x) ((x) << S_CPUSTANDBYWFI3)
82493 #define F_CPUSTANDBYWFI3    V_CPUSTANDBYWFI3(1U)
82496 #define V_CPUSTANDBYWFI2(x) ((x) << S_CPUSTANDBYWFI2)
82497 #define F_CPUSTANDBYWFI2    V_CPUSTANDBYWFI2(1U)
82500 #define V_CPUSTANDBYWFI1(x) ((x) << S_CPUSTANDBYWFI1)
82501 #define F_CPUSTANDBYWFI1    V_CPUSTANDBYWFI1(1U)
82504 #define V_CPUSTANDBYWFI0(x) ((x) << S_CPUSTANDBYWFI0)
82505 #define F_CPUSTANDBYWFI0    V_CPUSTANDBYWFI0(1U)
82508 #define V_CPUSTANDBYWFE3(x) ((x) << S_CPUSTANDBYWFE3)
82509 #define F_CPUSTANDBYWFE3    V_CPUSTANDBYWFE3(1U)
82512 #define V_CPUSTANDBYWFE2(x) ((x) << S_CPUSTANDBYWFE2)
82513 #define F_CPUSTANDBYWFE2    V_CPUSTANDBYWFE2(1U)
82515 #define S_CPUSTANDBYWFE1    1
82516 #define V_CPUSTANDBYWFE1(x) ((x) << S_CPUSTANDBYWFE1)
82517 #define F_CPUSTANDBYWFE1    V_CPUSTANDBYWFE1(1U)
82520 #define V_CPUSTANDBYWFE0(x) ((x) << S_CPUSTANDBYWFE0)
82521 #define F_CPUSTANDBYWFE0    V_CPUSTANDBYWFE0(1U)
82526 #define V_CPUSMPEN3(x) ((x) << S_CPUSMPEN3)
82527 #define F_CPUSMPEN3    V_CPUSMPEN3(1U)
82530 #define V_CPUSMPEN2(x) ((x) << S_CPUSMPEN2)
82531 #define F_CPUSMPEN2    V_CPUSMPEN2(1U)
82533 #define S_CPUSMPEN1    1
82534 #define V_CPUSMPEN1(x) ((x) << S_CPUSMPEN1)
82535 #define F_CPUSMPEN1    V_CPUSMPEN1(1U)
82538 #define V_CPUSMPEN0(x) ((x) << S_CPUSMPEN0)
82539 #define F_CPUSMPEN0    V_CPUSMPEN0(1U)
82544 #define V_CPUQACTIVE3(x) ((x) << S_CPUQACTIVE3)
82545 #define F_CPUQACTIVE3    V_CPUQACTIVE3(1U)
82548 #define V_CPUQACTIVE2(x) ((x) << S_CPUQACTIVE2)
82549 #define F_CPUQACTIVE2    V_CPUQACTIVE2(1U)
82551 #define S_CPUQACTIVE1    1
82552 #define V_CPUQACTIVE1(x) ((x) << S_CPUQACTIVE1)
82553 #define F_CPUQACTIVE1    V_CPUQACTIVE1(1U)
82556 #define V_CPUQACTIVE0(x) ((x) << S_CPUQACTIVE0)
82557 #define F_CPUQACTIVE0    V_CPUQACTIVE0(1U)
82562 #define V_CPUL2FLUSHREQ(x) ((x) << S_CPUL2FLUSHREQ)
82563 #define F_CPUL2FLUSHREQ    V_CPUL2FLUSHREQ(1U)
82566 #define V_CPUL2QREQN(x) ((x) << S_CPUL2QREQN)
82567 #define F_CPUL2QREQN    V_CPUL2QREQN(1U)
82570 #define V_CPUQREQ3N(x) ((x) << S_CPUQREQ3N)
82571 #define F_CPUQREQ3N    V_CPUQREQ3N(1U)
82574 #define V_CPUQREQ2N(x) ((x) << S_CPUQREQ2N)
82575 #define F_CPUQREQ2N    V_CPUQREQ2N(1U)
82577 #define S_CPUQREQ1N    1
82578 #define V_CPUQREQ1N(x) ((x) << S_CPUQREQ1N)
82579 #define F_CPUQREQ1N    V_CPUQREQ1N(1U)
82582 #define V_CPUQREQ0N(x) ((x) << S_CPUQREQ0N)
82583 #define F_CPUQREQ0N    V_CPUQREQ0N(1U)
82588 #define V_CPUL2FLUSHDONE(x) ((x) << S_CPUL2FLUSHDONE)
82589 #define F_CPUL2FLUSHDONE    V_CPUL2FLUSHDONE(1U)
82592 #define V_CPUL2QDENY(x) ((x) << S_CPUL2QDENY)
82593 #define F_CPUL2QDENY    V_CPUL2QDENY(1U)
82596 #define V_CPUL2QACCEPTN(x) ((x) << S_CPUL2QACCEPTN)
82597 #define F_CPUL2QACCEPTN    V_CPUL2QACCEPTN(1U)
82600 #define V_CPUQDENY3(x) ((x) << S_CPUQDENY3)
82601 #define F_CPUQDENY3    V_CPUQDENY3(1U)
82604 #define V_CPUQDENY2(x) ((x) << S_CPUQDENY2)
82605 #define F_CPUQDENY2    V_CPUQDENY2(1U)
82608 #define V_CPUQDENY1(x) ((x) << S_CPUQDENY1)
82609 #define F_CPUQDENY1    V_CPUQDENY1(1U)
82612 #define V_CPUQDENY0(x) ((x) << S_CPUQDENY0)
82613 #define F_CPUQDENY0    V_CPUQDENY0(1U)
82616 #define V_CPUQACCEPT3N(x) ((x) << S_CPUQACCEPT3N)
82617 #define F_CPUQACCEPT3N    V_CPUQACCEPT3N(1U)
82620 #define V_CPUQACCEPT2N(x) ((x) << S_CPUQACCEPT2N)
82621 #define F_CPUQACCEPT2N    V_CPUQACCEPT2N(1U)
82623 #define S_CPUQACCEPT1N    1
82624 #define V_CPUQACCEPT1N(x) ((x) << S_CPUQACCEPT1N)
82625 #define F_CPUQACCEPT1N    V_CPUQACCEPT1N(1U)
82628 #define V_CPUQACCEPT0N(x) ((x) << S_CPUQACCEPT0N)
82629 #define F_CPUQACCEPT0N    V_CPUQACCEPT0N(1U)
82634 #define V_CPUDBGL1RSTDISABLE(x) ((x) << S_CPUDBGL1RSTDISABLE)
82635 #define F_CPUDBGL1RSTDISABLE    V_CPUDBGL1RSTDISABLE(1U)
82638 #define V_CPUDBGRSTREQ3(x) ((x) << S_CPUDBGRSTREQ3)
82639 #define F_CPUDBGRSTREQ3    V_CPUDBGRSTREQ3(1U)
82642 #define V_CPUDBGRSTREQ2(x) ((x) << S_CPUDBGRSTREQ2)
82643 #define F_CPUDBGRSTREQ2    V_CPUDBGRSTREQ2(1U)
82646 #define V_CPUDBGRSTREQ1(x) ((x) << S_CPUDBGRSTREQ1)
82647 #define F_CPUDBGRSTREQ1    V_CPUDBGRSTREQ1(1U)
82650 #define V_CPUDBGRSTREQ0(x) ((x) << S_CPUDBGRSTREQ0)
82651 #define F_CPUDBGRSTREQ0    V_CPUDBGRSTREQ0(1U)
82654 #define V_CPUDBGPWRDUP3(x) ((x) << S_CPUDBGPWRDUP3)
82655 #define F_CPUDBGPWRDUP3    V_CPUDBGPWRDUP3(1U)
82658 #define V_CPUDBGPWRDUP2(x) ((x) << S_CPUDBGPWRDUP2)
82659 #define F_CPUDBGPWRDUP2    V_CPUDBGPWRDUP2(1U)
82662 #define V_CPUDBGPWRDUP1(x) ((x) << S_CPUDBGPWRDUP1)
82663 #define F_CPUDBGPWRDUP1    V_CPUDBGPWRDUP1(1U)
82666 #define V_CPUDBGPWRDUP0(x) ((x) << S_CPUDBGPWRDUP0)
82667 #define F_CPUDBGPWRDUP0    V_CPUDBGPWRDUP0(1U)
82670 #define V_CPUEXTDBGREQ3(x) ((x) << S_CPUEXTDBGREQ3)
82671 #define F_CPUEXTDBGREQ3    V_CPUEXTDBGREQ3(1U)
82674 #define V_CPUEXTDBGREQ2(x) ((x) << S_CPUEXTDBGREQ2)
82675 #define F_CPUEXTDBGREQ2    V_CPUEXTDBGREQ2(1U)
82678 #define V_CPUEXTDBGREQ1(x) ((x) << S_CPUEXTDBGREQ1)
82679 #define F_CPUEXTDBGREQ1    V_CPUEXTDBGREQ1(1U)
82682 #define V_CPUEXTDBGREQ0(x) ((x) << S_CPUEXTDBGREQ0)
82683 #define F_CPUEXTDBGREQ0    V_CPUEXTDBGREQ0(1U)
82686 #define V_CPUSPNIDEN3(x) ((x) << S_CPUSPNIDEN3)
82687 #define F_CPUSPNIDEN3    V_CPUSPNIDEN3(1U)
82690 #define V_CPUSPNIDEN2(x) ((x) << S_CPUSPNIDEN2)
82691 #define F_CPUSPNIDEN2    V_CPUSPNIDEN2(1U)
82694 #define V_CPUSPNIDEN1(x) ((x) << S_CPUSPNIDEN1)
82695 #define F_CPUSPNIDEN1    V_CPUSPNIDEN1(1U)
82698 #define V_CPUSPNIDEN0(x) ((x) << S_CPUSPNIDEN0)
82699 #define F_CPUSPNIDEN0    V_CPUSPNIDEN0(1U)
82702 #define V_CPUSPDBGEN3(x) ((x) << S_CPUSPDBGEN3)
82703 #define F_CPUSPDBGEN3    V_CPUSPDBGEN3(1U)
82706 #define V_CPUSPDBGEN2(x) ((x) << S_CPUSPDBGEN2)
82707 #define F_CPUSPDBGEN2    V_CPUSPDBGEN2(1U)
82710 #define V_CPUSPDBGEN1(x) ((x) << S_CPUSPDBGEN1)
82711 #define F_CPUSPDBGEN1    V_CPUSPDBGEN1(1U)
82714 #define V_CPUSPDBGEN0(x) ((x) << S_CPUSPDBGEN0)
82715 #define F_CPUSPDBGEN0    V_CPUSPDBGEN0(1U)
82718 #define V_CPUNIDEN3(x) ((x) << S_CPUNIDEN3)
82719 #define F_CPUNIDEN3    V_CPUNIDEN3(1U)
82722 #define V_CPUNIDEN2(x) ((x) << S_CPUNIDEN2)
82723 #define F_CPUNIDEN2    V_CPUNIDEN2(1U)
82726 #define V_CPUNIDEN1(x) ((x) << S_CPUNIDEN1)
82727 #define F_CPUNIDEN1    V_CPUNIDEN1(1U)
82730 #define V_CPUNIDEN0(x) ((x) << S_CPUNIDEN0)
82731 #define F_CPUNIDEN0    V_CPUNIDEN0(1U)
82734 #define V_CPUDBGEN3(x) ((x) << S_CPUDBGEN3)
82735 #define F_CPUDBGEN3    V_CPUDBGEN3(1U)
82738 #define V_CPUDBGEN2(x) ((x) << S_CPUDBGEN2)
82739 #define F_CPUDBGEN2    V_CPUDBGEN2(1U)
82741 #define S_CPUDBGEN1    1
82742 #define V_CPUDBGEN1(x) ((x) << S_CPUDBGEN1)
82743 #define F_CPUDBGEN1    V_CPUDBGEN1(1U)
82746 #define V_CPUDBGEN0(x) ((x) << S_CPUDBGEN0)
82747 #define F_CPUDBGEN0    V_CPUDBGEN0(1U)
82752 #define V_CPUDBGNOPWRDWN3(x) ((x) << S_CPUDBGNOPWRDWN3)
82753 #define F_CPUDBGNOPWRDWN3    V_CPUDBGNOPWRDWN3(1U)
82756 #define V_CPUDBGNOPWRDWN2(x) ((x) << S_CPUDBGNOPWRDWN2)
82757 #define F_CPUDBGNOPWRDWN2    V_CPUDBGNOPWRDWN2(1U)
82760 #define V_CPUDBGNOPWRDWN1(x) ((x) << S_CPUDBGNOPWRDWN1)
82761 #define F_CPUDBGNOPWRDWN1    V_CPUDBGNOPWRDWN1(1U)
82764 #define V_CPUDBGNOPWRDWN0(x) ((x) << S_CPUDBGNOPWRDWN0)
82765 #define F_CPUDBGNOPWRDWN0    V_CPUDBGNOPWRDWN0(1U)
82768 #define V_CPUDGNRSTREQ3(x) ((x) << S_CPUDGNRSTREQ3)
82769 #define F_CPUDGNRSTREQ3    V_CPUDGNRSTREQ3(1U)
82772 #define V_CPUDGNRSTREQ2(x) ((x) << S_CPUDGNRSTREQ2)
82773 #define F_CPUDGNRSTREQ2    V_CPUDGNRSTREQ2(1U)
82776 #define V_CPUDGNRSTREQ1(x) ((x) << S_CPUDGNRSTREQ1)
82777 #define F_CPUDGNRSTREQ1    V_CPUDGNRSTREQ1(1U)
82780 #define V_CPUDGNRSTREQ0(x) ((x) << S_CPUDGNRSTREQ0)
82781 #define F_CPUDGNRSTREQ0    V_CPUDGNRSTREQ0(1U)
82784 #define V_CPUDBGACK3(x) ((x) << S_CPUDBGACK3)
82785 #define F_CPUDBGACK3    V_CPUDBGACK3(1U)
82788 #define V_CPUDBGACK2(x) ((x) << S_CPUDBGACK2)
82789 #define F_CPUDBGACK2    V_CPUDBGACK2(1U)
82791 #define S_CPUDBGACK1    1
82792 #define V_CPUDBGACK1(x) ((x) << S_CPUDBGACK1)
82793 #define F_CPUDBGACK1    V_CPUDBGACK1(1U)
82796 #define V_CPUDBGACK0(x) ((x) << S_CPUDBGACK0)
82797 #define F_CPUDBGACK0    V_CPUDBGACK0(1U)
82802 #define V_CPUPMUSNAPSHOTREQ3(x) ((x) << S_CPUPMUSNAPSHOTREQ3)
82803 #define F_CPUPMUSNAPSHOTREQ3    V_CPUPMUSNAPSHOTREQ3(1U)
82806 #define V_CPUPMUSNAPSHOTREQ2(x) ((x) << S_CPUPMUSNAPSHOTREQ2)
82807 #define F_CPUPMUSNAPSHOTREQ2    V_CPUPMUSNAPSHOTREQ2(1U)
82809 #define S_CPUPMUSNAPSHOTREQ1    1
82810 #define V_CPUPMUSNAPSHOTREQ1(x) ((x) << S_CPUPMUSNAPSHOTREQ1)
82811 #define F_CPUPMUSNAPSHOTREQ1    V_CPUPMUSNAPSHOTREQ1(1U)
82814 #define V_CPUPMUSNAPSHOTREQ0(x) ((x) << S_CPUPMUSNAPSHOTREQ0)
82815 #define F_CPUPMUSNAPSHOTREQ0    V_CPUPMUSNAPSHOTREQ0(1U)
82820 #define V_CPUPMUSNAPSHOTACK3(x) ((x) << S_CPUPMUSNAPSHOTACK3)
82821 #define F_CPUPMUSNAPSHOTACK3    V_CPUPMUSNAPSHOTACK3(1U)
82824 #define V_CPUPMUSNAPSHOTACK2(x) ((x) << S_CPUPMUSNAPSHOTACK2)
82825 #define F_CPUPMUSNAPSHOTACK2    V_CPUPMUSNAPSHOTACK2(1U)
82827 #define S_CPUPMUSNAPSHOTACK1    1
82828 #define V_CPUPMUSNAPSHOTACK1(x) ((x) << S_CPUPMUSNAPSHOTACK1)
82829 #define F_CPUPMUSNAPSHOTACK1    V_CPUPMUSNAPSHOTACK1(1U)
82832 #define V_CPUPMUSNAPSHOTACK0(x) ((x) << S_CPUPMUSNAPSHOTACK0)
82833 #define F_CPUPMUSNAPSHOTACK0    V_CPUPMUSNAPSHOTACK0(1U)
82839 #define V_EMMC_DATA_P2(x) ((x) << S_EMMC_DATA_P2)
82840 #define G_EMMC_DATA_P2(x) (((x) >> S_EMMC_DATA_P2) & M_EMMC_DATA_P2)
82844 #define V_EMMC_DATA_P1(x) ((x) << S_EMMC_DATA_P1)
82845 #define G_EMMC_DATA_P1(x) (((x) >> S_EMMC_DATA_P1) & M_EMMC_DATA_P1)
82848 #define V_EMMC_CMD_P2(x) ((x) << S_EMMC_CMD_P2)
82849 #define F_EMMC_CMD_P2    V_EMMC_CMD_P2(1U)
82852 #define V_EMMC_CMD_P1(x) ((x) << S_EMMC_CMD_P1)
82853 #define F_EMMC_CMD_P1    V_EMMC_CMD_P1(1U)
82856 #define V_EMMC_RST_P2(x) ((x) << S_EMMC_RST_P2)
82857 #define F_EMMC_RST_P2    V_EMMC_RST_P2(1U)
82860 #define V_EMMC_RST_P1(x) ((x) << S_EMMC_RST_P1)
82861 #define F_EMMC_RST_P1    V_EMMC_RST_P1(1U)
82865 #define V_EMMC_GP_IN_P2(x) ((x) << S_EMMC_GP_IN_P2)
82866 #define G_EMMC_GP_IN_P2(x) (((x) >> S_EMMC_GP_IN_P2) & M_EMMC_GP_IN_P2)
82870 #define V_EMMC_GP_IN_P1(x) ((x) << S_EMMC_GP_IN_P1)
82871 #define G_EMMC_GP_IN_P1(x) (((x) >> S_EMMC_GP_IN_P1) & M_EMMC_GP_IN_P1)
82875 #define V_EMMC_CLK_SEL(x) ((x) << S_EMMC_CLK_SEL)
82876 #define G_EMMC_CLK_SEL(x) (((x) >> S_EMMC_CLK_SEL) & M_EMMC_CLK_SEL)
82881 #define V_CPUSYSBARDISABLE(x) ((x) << S_CPUSYSBARDISABLE)
82882 #define F_CPUSYSBARDISABLE    V_CPUSYSBARDISABLE(1U)
82885 #define V_CPUBROADCACHEMAIN(x) ((x) << S_CPUBROADCACHEMAIN)
82886 #define F_CPUBROADCACHEMAIN    V_CPUBROADCACHEMAIN(1U)
82889 #define V_CPUBROADOUTER(x) ((x) << S_CPUBROADOUTER)
82890 #define F_CPUBROADOUTER    V_CPUBROADOUTER(1U)
82893 #define V_CPUBROADINNER(x) ((x) << S_CPUBROADINNER)
82894 #define F_CPUBROADINNER    V_CPUBROADINNER(1U)
82897 #define V_CPUCRYPTODISABLE3(x) ((x) << S_CPUCRYPTODISABLE3)
82898 #define F_CPUCRYPTODISABLE3    V_CPUCRYPTODISABLE3(1U)
82901 #define V_CPUCRYPTODISABLE2(x) ((x) << S_CPUCRYPTODISABLE2)
82902 #define F_CPUCRYPTODISABLE2    V_CPUCRYPTODISABLE2(1U)
82905 #define V_CPUCRYPTODISABLE1(x) ((x) << S_CPUCRYPTODISABLE1)
82906 #define F_CPUCRYPTODISABLE1    V_CPUCRYPTODISABLE1(1U)
82909 #define V_CPUCRYPTODISABLE0(x) ((x) << S_CPUCRYPTODISABLE0)
82910 #define F_CPUCRYPTODISABLE0    V_CPUCRYPTODISABLE0(1U)
82913 #define V_CPUAA64NAA323(x) ((x) << S_CPUAA64NAA323)
82914 #define F_CPUAA64NAA323    V_CPUAA64NAA323(1U)
82917 #define V_CPUAA64NAA322(x) ((x) << S_CPUAA64NAA322)
82918 #define F_CPUAA64NAA322    V_CPUAA64NAA322(1U)
82921 #define V_CPUAA64NAA321(x) ((x) << S_CPUAA64NAA321)
82922 #define F_CPUAA64NAA321    V_CPUAA64NAA321(1U)
82925 #define V_CPUAA64NAA320(x) ((x) << S_CPUAA64NAA320)
82926 #define F_CPUAA64NAA320    V_CPUAA64NAA320(1U)
82929 #define V_CPUCFGTE3(x) ((x) << S_CPUCFGTE3)
82930 #define F_CPUCFGTE3    V_CPUCFGTE3(1U)
82933 #define V_CPUCFGTE2(x) ((x) << S_CPUCFGTE2)
82934 #define F_CPUCFGTE2    V_CPUCFGTE2(1U)
82937 #define V_CPUCFGTE1(x) ((x) << S_CPUCFGTE1)
82938 #define F_CPUCFGTE1    V_CPUCFGTE1(1U)
82941 #define V_CPUCFGTE0(x) ((x) << S_CPUCFGTE0)
82942 #define F_CPUCFGTE0    V_CPUCFGTE0(1U)
82945 #define V_CPUVINIHI3(x) ((x) << S_CPUVINIHI3)
82946 #define F_CPUVINIHI3    V_CPUVINIHI3(1U)
82949 #define V_CPUVINIHI2(x) ((x) << S_CPUVINIHI2)
82950 #define F_CPUVINIHI2    V_CPUVINIHI2(1U)
82953 #define V_CPUVINIHI1(x) ((x) << S_CPUVINIHI1)
82954 #define F_CPUVINIHI1    V_CPUVINIHI1(1U)
82957 #define V_CPUVINIHI0(x) ((x) << S_CPUVINIHI0)
82958 #define F_CPUVINIHI0    V_CPUVINIHI0(1U)
82961 #define V_CPUCFGEND3(x) ((x) << S_CPUCFGEND3)
82962 #define F_CPUCFGEND3    V_CPUCFGEND3(1U)
82965 #define V_CPUCFGEND2(x) ((x) << S_CPUCFGEND2)
82966 #define F_CPUCFGEND2    V_CPUCFGEND2(1U)
82968 #define S_CPUCFGEND1    1
82969 #define V_CPUCFGEND1(x) ((x) << S_CPUCFGEND1)
82970 #define F_CPUCFGEND1    V_CPUCFGEND1(1U)
82973 #define V_CPUCFGEND0(x) ((x) << S_CPUCFGEND0)
82974 #define F_CPUCFGEND0    V_CPUCFGEND0(1U)
82979 #define V_CPUCP15SDISABLE3(x) ((x) << S_CPUCP15SDISABLE3)
82980 #define F_CPUCP15SDISABLE3    V_CPUCP15SDISABLE3(1U)
82983 #define V_CPUCP15SDISABLE2(x) ((x) << S_CPUCP15SDISABLE2)
82984 #define F_CPUCP15SDISABLE2    V_CPUCP15SDISABLE2(1U)
82986 #define S_CPUCP15SDISABLE1    1
82987 #define V_CPUCP15SDISABLE1(x) ((x) << S_CPUCP15SDISABLE1)
82988 #define F_CPUCP15SDISABLE1    V_CPUCP15SDISABLE1(1U)
82991 #define V_CPUCP15SDISABLE0(x) ((x) << S_CPUCP15SDISABLE0)
82992 #define F_CPUCP15SDISABLE0    V_CPUCP15SDISABLE0(1U)
82998 #define V_CPUCLUSTERIDAFF2(x) ((x) << S_CPUCLUSTERIDAFF2)
82999 #define G_CPUCLUSTERIDAFF2(x) (((x) >> S_CPUCLUSTERIDAFF2) & M_CPUCLUSTERIDAFF2)
83003 #define V_CPUCLUSTERIDAFF1(x) ((x) << S_CPUCLUSTERIDAFF1)
83004 #define G_CPUCLUSTERIDAFF1(x) (((x) >> S_CPUCLUSTERIDAFF1) & M_CPUCLUSTERIDAFF1)
83008 #define S_CPUACINACTIVEM    1
83009 #define V_CPUACINACTIVEM(x) ((x) << S_CPUACINACTIVEM)
83010 #define F_CPUACINACTIVEM    V_CPUACINACTIVEM(1U)
83013 #define V_CPUACLKENM(x) ((x) << S_CPUACLKENM)
83014 #define F_CPUACLKENM    V_CPUACLKENM(1U)
83019 #define V_INVALID_BRESP(x) ((x) << S_INVALID_BRESP)
83020 #define F_INVALID_BRESP    V_INVALID_BRESP(1U)
83023 #define V_DATA_LEN_OF(x) ((x) << S_DATA_LEN_OF)
83024 #define F_DATA_LEN_OF    V_DATA_LEN_OF(1U)
83026 #define S_INVALID_EMU_ADDR    1
83027 #define V_INVALID_EMU_ADDR(x) ((x) << S_INVALID_EMU_ADDR)
83028 #define F_INVALID_EMU_ADDR    V_INVALID_EMU_ADDR(1U)
83031 #define V_INVALID_AXI_ADDR_CFG(x) ((x) << S_INVALID_AXI_ADDR_CFG)
83032 #define F_INVALID_AXI_ADDR_CFG    V_INVALID_AXI_ADDR_CFG(1U)
83037 #define V_ATCLKEN(x) ((x) << S_ATCLKEN)
83038 #define F_ATCLKEN    V_ATCLKEN(1U)
83041 #define V_CXAPBICRSTN(x) ((x) << S_CXAPBICRSTN)
83042 #define F_CXAPBICRSTN    V_CXAPBICRSTN(1U)
83045 #define V_CSDBGEN(x) ((x) << S_CSDBGEN)
83046 #define F_CSDBGEN    V_CSDBGEN(1U)
83049 #define V_JTAGNPOTRST(x) ((x) << S_JTAGNPOTRST)
83050 #define F_JTAGNPOTRST    V_JTAGNPOTRST(1U)
83053 #define V_JTAGNTRST(x) ((x) << S_JTAGNTRST)
83054 #define F_JTAGNTRST    V_JTAGNTRST(1U)
83057 #define V_PADDR31S0(x) ((x) << S_PADDR31S0)
83058 #define F_PADDR31S0    V_PADDR31S0(1U)
83061 #define V_CTICLKEN(x) ((x) << S_CTICLKEN)
83062 #define F_CTICLKEN    V_CTICLKEN(1U)
83065 #define V_PCLKENDBG(x) ((x) << S_PCLKENDBG)
83066 #define F_PCLKENDBG    V_PCLKENDBG(1U)
83068 #define S_CPU_NIDEN    1
83069 #define V_CPU_NIDEN(x) ((x) << S_CPU_NIDEN)
83070 #define F_CPU_NIDEN    V_CPU_NIDEN(1U)
83073 #define V_CPU_DBGEN(x) ((x) << S_CPU_DBGEN)
83074 #define F_CPU_DBGEN    V_CPU_DBGEN(1U)
83082 #define V_DFTMBISTADDR(x) ((x) << S_DFTMBISTADDR)
83083 #define G_DFTMBISTADDR(x) (((x) >> S_DFTMBISTADDR) & M_DFTMBISTADDR)
83086 #define V_DFTMTESTON(x) ((x) << S_DFTMTESTON)
83087 #define F_DFTMTESTON    V_DFTMTESTON(1U)
83090 #define V_DFTMBISTCE(x) ((x) << S_DFTMBISTCE)
83091 #define F_DFTMBISTCE    V_DFTMBISTCE(1U)
83093 #define S_DFTMBITWR    1
83094 #define V_DFTMBITWR(x) ((x) << S_DFTMBITWR)
83095 #define F_DFTMBITWR    V_DFTMBITWR(1U)
83098 #define V_DFTSE(x) ((x) << S_DFTSE)
83099 #define F_DFTSE    V_DFTSE(1U)
83106 #define V_CPUEVENTI(x) ((x) << S_CPUEVENTI)
83107 #define F_CPUEVENTI    V_CPUEVENTI(1U)
83112 #define V_CPUEVENTO(x) ((x) << S_CPUEVENTO)
83113 #define F_CPUEVENTO    V_CPUEVENTO(1U)
83118 #define V_CPUCLREXMONREQ(x) ((x) << S_CPUCLREXMONREQ)
83119 #define F_CPUCLREXMONREQ    V_CPUCLREXMONREQ(1U)
83124 #define V_CPUCLREXMONACK(x) ((x) << S_CPUCLREXMONACK)
83125 #define F_CPUCLREXMONACK    V_CPUCLREXMONACK(1U)
83131 #define V_UART_MSTR_RXC(x) ((x) << S_UART_MSTR_RXC)
83132 #define F_UART_MSTR_RXC    V_UART_MSTR_RXC(1U)
83137 #define S_T7_INT    1
83138 #define V_T7_INT(x) ((x) << S_T7_INT)
83139 #define F_T7_INT    V_T7_INT(1U)
83142 #define V_UART_MSTC_TXC(x) ((x) << S_UART_MSTC_TXC)
83143 #define F_UART_MSTC_TXC    V_UART_MSTC_TXC(1U)
83148 #define V_UART_SLV_SEL(x) ((x) << S_UART_SLV_SEL)
83149 #define F_UART_SLV_SEL    V_UART_SLV_SEL(1U)
83159 #define V_RSV1(x) ((x) << S_RSV1)
83160 #define G_RSV1(x) (((x) >> S_RSV1) & M_RSV1)
83163 #define V_RXFRMERR(x) ((x) << S_RXFRMERR)
83164 #define F_RXFRMERR    V_RXFRMERR(1U)
83167 #define V_RXPARERR(x) ((x) << S_RXPARERR)
83168 #define F_RXPARERR    V_RXPARERR(1U)
83171 #define V_RXOVRN(x) ((x) << S_RXOVRN)
83172 #define F_RXOVRN    V_RXOVRN(1U)
83175 #define V_CTL_RXRDY(x) ((x) << S_CTL_RXRDY)
83176 #define F_CTL_RXRDY    V_CTL_RXRDY(1U)
83178 #define S_TXOVRN    1
83179 #define V_TXOVRN(x) ((x) << S_TXOVRN)
83180 #define F_TXOVRN    V_TXOVRN(1U)
83183 #define V_CTL_TXRDY(x) ((x) << S_CTL_TXRDY)
83184 #define F_CTL_TXRDY    V_CTL_TXRDY(1U)
83190 #define V_TX_DATA(x) ((x) << S_TX_DATA)
83191 #define G_TX_DATA(x) (((x) >> S_TX_DATA) & M_TX_DATA)
83197 #define V_RX_DATA(x) ((x) << S_RX_DATA)
83198 #define G_RX_DATA(x) (((x) >> S_RX_DATA) & M_RX_DATA)
83208 #define S_RX_FIFO_NOT_EMPTY    1
83209 #define V_RX_FIFO_NOT_EMPTY(x) ((x) << S_RX_FIFO_NOT_EMPTY)
83210 #define F_RX_FIFO_NOT_EMPTY    V_RX_FIFO_NOT_EMPTY(1U)
83213 #define V_TX_FIFO_EMPTY(x) ((x) << S_TX_FIFO_EMPTY)
83214 #define F_TX_FIFO_EMPTY    V_TX_FIFO_EMPTY(1U)
83218 #define S_RX_FIFO_INT_NOT_EMPTY    1
83219 #define V_RX_FIFO_INT_NOT_EMPTY(x) ((x) << S_RX_FIFO_INT_NOT_EMPTY)
83220 #define F_RX_FIFO_INT_NOT_EMPTY    V_RX_FIFO_INT_NOT_EMPTY(1U)
83223 #define V_TX_FIFO_INT_EMPTY(x) ((x) << S_TX_FIFO_INT_EMPTY)
83224 #define F_TX_FIFO_INT_EMPTY    V_TX_FIFO_INT_EMPTY(1U)
83228 #define S_PC_SEL    1
83230 #define V_PC_SEL(x) ((x) << S_PC_SEL)
83231 #define G_PC_SEL(x) (((x) >> S_PC_SEL) & M_PC_SEL)
83234 #define V_UART_GPIO_SEL(x) ((x) << S_UART_GPIO_SEL)
83235 #define F_UART_GPIO_SEL    V_UART_GPIO_SEL(1U)
83243 #define V_INIC_WRDATA_FIFO_PERR(x) ((x) << S_INIC_WRDATA_FIFO_PERR)
83244 #define F_INIC_WRDATA_FIFO_PERR    V_INIC_WRDATA_FIFO_PERR(1U)
83247 #define V_INIC_RDATA_FIFO_PERR(x) ((x) << S_INIC_RDATA_FIFO_PERR)
83248 #define F_INIC_RDATA_FIFO_PERR    V_INIC_RDATA_FIFO_PERR(1U)
83251 #define V_MSI_MEM_PERR(x) ((x) << S_MSI_MEM_PERR)
83252 #define F_MSI_MEM_PERR    V_MSI_MEM_PERR(1U)
83256 #define V_ARM_DB_SRAM_PERR(x) ((x) << S_ARM_DB_SRAM_PERR)
83257 #define G_ARM_DB_SRAM_PERR(x) (((x) >> S_ARM_DB_SRAM_PERR) & M_ARM_DB_SRAM_PERR)
83260 #define V_EMMC_FIFOPARINT(x) ((x) << S_EMMC_FIFOPARINT)
83261 #define F_EMMC_FIFOPARINT    V_EMMC_FIFOPARINT(1U)
83264 #define V_ICB_RAM_PERR(x) ((x) << S_ICB_RAM_PERR)
83265 #define F_ICB_RAM_PERR    V_ICB_RAM_PERR(1U)
83268 #define V_MESS2AXI4_WRFIFO_PERR(x) ((x) << S_MESS2AXI4_WRFIFO_PERR)
83269 #define F_MESS2AXI4_WRFIFO_PERR    V_MESS2AXI4_WRFIFO_PERR(1U)
83272 #define V_RC_WFIFO_OUTPERR(x) ((x) << S_RC_WFIFO_OUTPERR)
83273 #define F_RC_WFIFO_OUTPERR    V_RC_WFIFO_OUTPERR(1U)
83277 #define V_RC_SRAM_PERR(x) ((x) << S_RC_SRAM_PERR)
83278 #define G_RC_SRAM_PERR(x) (((x) >> S_RC_SRAM_PERR) & M_RC_SRAM_PERR)
83281 #define V_MSI_FIFO_PAR_ERR(x) ((x) << S_MSI_FIFO_PAR_ERR)
83282 #define F_MSI_FIFO_PAR_ERR    V_MSI_FIFO_PAR_ERR(1U)
83285 #define V_INIC2MA_INTFPERR(x) ((x) << S_INIC2MA_INTFPERR)
83286 #define F_INIC2MA_INTFPERR    V_INIC2MA_INTFPERR(1U)
83289 #define V_RDATAFIFO0_PERR(x) ((x) << S_RDATAFIFO0_PERR)
83290 #define F_RDATAFIFO0_PERR    V_RDATAFIFO0_PERR(1U)
83293 #define V_RDATAFIFO1_PERR(x) ((x) << S_RDATAFIFO1_PERR)
83294 #define F_RDATAFIFO1_PERR    V_RDATAFIFO1_PERR(1U)
83297 #define V_WRDATAFIFO0_PERR(x) ((x) << S_WRDATAFIFO0_PERR)
83298 #define F_WRDATAFIFO0_PERR    V_WRDATAFIFO0_PERR(1U)
83301 #define V_WRDATAFIFO1_PERR(x) ((x) << S_WRDATAFIFO1_PERR)
83302 #define F_WRDATAFIFO1_PERR    V_WRDATAFIFO1_PERR(1U)
83305 #define V_WR512DATAFIFO0_PERR(x) ((x) << S_WR512DATAFIFO0_PERR)
83306 #define F_WR512DATAFIFO0_PERR    V_WR512DATAFIFO0_PERR(1U)
83309 #define V_WR512DATAFIFO1_PERR(x) ((x) << S_WR512DATAFIFO1_PERR)
83310 #define F_WR512DATAFIFO1_PERR    V_WR512DATAFIFO1_PERR(1U)
83313 #define V_ROBUFF_PARERR3(x) ((x) << S_ROBUFF_PARERR3)
83314 #define F_ROBUFF_PARERR3    V_ROBUFF_PARERR3(1U)
83317 #define V_ROBUFF_PARERR2(x) ((x) << S_ROBUFF_PARERR2)
83318 #define F_ROBUFF_PARERR2    V_ROBUFF_PARERR2(1U)
83321 #define V_ROBUFF_PARERR1(x) ((x) << S_ROBUFF_PARERR1)
83322 #define F_ROBUFF_PARERR1    V_ROBUFF_PARERR1(1U)
83325 #define V_ROBUFF_PARERR0(x) ((x) << S_ROBUFF_PARERR0)
83326 #define F_ROBUFF_PARERR0    V_ROBUFF_PARERR0(1U)
83329 #define V_MA2AXI_REQDATAPARERR(x) ((x) << S_MA2AXI_REQDATAPARERR)
83330 #define F_MA2AXI_REQDATAPARERR    V_MA2AXI_REQDATAPARERR(1U)
83333 #define V_MA2AXI_REQCTLPARERR(x) ((x) << S_MA2AXI_REQCTLPARERR)
83334 #define F_MA2AXI_REQCTLPARERR    V_MA2AXI_REQCTLPARERR(1U)
83337 #define V_MA_RSPPERR(x) ((x) << S_MA_RSPPERR)
83338 #define F_MA_RSPPERR    V_MA_RSPPERR(1U)
83341 #define V_PCIE2MA_REQCTLPARERR(x) ((x) << S_PCIE2MA_REQCTLPARERR)
83342 #define F_PCIE2MA_REQCTLPARERR    V_PCIE2MA_REQCTLPARERR(1U)
83345 #define V_PCIE2MA_REQDATAPARERR(x) ((x) << S_PCIE2MA_REQDATAPARERR)
83346 #define F_PCIE2MA_REQDATAPARERR    V_PCIE2MA_REQDATAPARERR(1U)
83349 #define V_INIC2MA_REQCTLPARERR(x) ((x) << S_INIC2MA_REQCTLPARERR)
83350 #define F_INIC2MA_REQCTLPARERR    V_INIC2MA_REQCTLPARERR(1U)
83353 #define V_INIC2MA_REQDATAPARERR(x) ((x) << S_INIC2MA_REQDATAPARERR)
83354 #define F_INIC2MA_REQDATAPARERR    V_INIC2MA_REQDATAPARERR(1U)
83356 #define S_MA_RSPUE    1
83357 #define V_MA_RSPUE(x) ((x) << S_MA_RSPUE)
83358 #define F_MA_RSPUE    V_MA_RSPUE(1U)
83361 #define V_APB2PL_RSPDATAPERR(x) ((x) << S_APB2PL_RSPDATAPERR)
83362 #define F_APB2PL_RSPDATAPERR    V_APB2PL_RSPDATAPERR(1U)
83368 #define V_ECO_43187(x) ((x) << S_ECO_43187)
83369 #define F_ECO_43187    V_ECO_43187(1U)
83373 #define V_TIMER_SEL(x) ((x) << S_TIMER_SEL)
83374 #define G_TIMER_SEL(x) (((x) >> S_TIMER_SEL) & M_TIMER_SEL)
83378 #define V_TIMER(x) ((x) << S_TIMER)
83379 #define G_TIMER(x) (((x) >> S_TIMER) & M_TIMER)
83383 #define V_T7_1_INT(x) ((x) << S_T7_1_INT)
83384 #define G_T7_1_INT(x) (((x) >> S_T7_1_INT) & M_T7_1_INT)
83389 #define V_INIC_WSTRB_FIFO_PERR(x) ((x) << S_INIC_WSTRB_FIFO_PERR)
83390 #define F_INIC_WSTRB_FIFO_PERR    V_INIC_WSTRB_FIFO_PERR(1U)
83393 #define V_INIC_BID_FIFO_PERR(x) ((x) << S_INIC_BID_FIFO_PERR)
83394 #define F_INIC_BID_FIFO_PERR    V_INIC_BID_FIFO_PERR(1U)
83397 #define V_CC_SRAM_PKA_PERR(x) ((x) << S_CC_SRAM_PKA_PERR)
83398 #define F_CC_SRAM_PKA_PERR    V_CC_SRAM_PKA_PERR(1U)
83401 #define V_CC_SRAM_SEC_PERR(x) ((x) << S_CC_SRAM_SEC_PERR)
83402 #define F_CC_SRAM_SEC_PERR    V_CC_SRAM_SEC_PERR(1U)
83405 #define V_MESS2AXI4_PARERR(x) ((x) << S_MESS2AXI4_PARERR)
83406 #define F_MESS2AXI4_PARERR    V_MESS2AXI4_PARERR(1U)
83409 #define V_CCI2INIC_INTF_PARERR(x) ((x) << S_CCI2INIC_INTF_PARERR)
83410 #define F_CCI2INIC_INTF_PARERR    V_CCI2INIC_INTF_PARERR(1U)
83415 #define V_AWLOCKR1(x) ((x) << S_AWLOCKR1)
83416 #define F_AWLOCKR1    V_AWLOCKR1(1U)
83420 #define V_AWCACHER1(x) ((x) << S_AWCACHER1)
83421 #define G_AWCACHER1(x) (((x) >> S_AWCACHER1) & M_AWCACHER1)
83425 #define V_AWPROTR1(x) ((x) << S_AWPROTR1)
83426 #define G_AWPROTR1(x) (((x) >> S_AWPROTR1) & M_AWPROTR1)
83430 #define V_AWSNOOPR1(x) ((x) << S_AWSNOOPR1)
83431 #define G_AWSNOOPR1(x) (((x) >> S_AWSNOOPR1) & M_AWSNOOPR1)
83435 #define V_AWDOMAINR1(x) ((x) << S_AWDOMAINR1)
83436 #define G_AWDOMAINR1(x) (((x) >> S_AWDOMAINR1) & M_AWDOMAINR1)
83439 #define V_AWLOCKR0(x) ((x) << S_AWLOCKR0)
83440 #define F_AWLOCKR0    V_AWLOCKR0(1U)
83444 #define V_AWCACHER0(x) ((x) << S_AWCACHER0)
83445 #define G_AWCACHER0(x) (((x) >> S_AWCACHER0) & M_AWCACHER0)
83449 #define V_AWPROTR0(x) ((x) << S_AWPROTR0)
83450 #define G_AWPROTR0(x) (((x) >> S_AWPROTR0) & M_AWPROTR0)
83454 #define V_AWSNOOPR0(x) ((x) << S_AWSNOOPR0)
83455 #define G_AWSNOOPR0(x) (((x) >> S_AWSNOOPR0) & M_AWSNOOPR0)
83459 #define V_AWDOMAINR0(x) ((x) << S_AWDOMAINR0)
83460 #define G_AWDOMAINR0(x) (((x) >> S_AWDOMAINR0) & M_AWDOMAINR0)
83465 #define V_ARLOCKR1(x) ((x) << S_ARLOCKR1)
83466 #define F_ARLOCKR1    V_ARLOCKR1(1U)
83470 #define V_ARCACHER1(x) ((x) << S_ARCACHER1)
83471 #define G_ARCACHER1(x) (((x) >> S_ARCACHER1) & M_ARCACHER1)
83475 #define V_ARPROTR1(x) ((x) << S_ARPROTR1)
83476 #define G_ARPROTR1(x) (((x) >> S_ARPROTR1) & M_ARPROTR1)
83480 #define V_ARSNOOPR1(x) ((x) << S_ARSNOOPR1)
83481 #define G_ARSNOOPR1(x) (((x) >> S_ARSNOOPR1) & M_ARSNOOPR1)
83485 #define V_ARDOMAINR1(x) ((x) << S_ARDOMAINR1)
83486 #define G_ARDOMAINR1(x) (((x) >> S_ARDOMAINR1) & M_ARDOMAINR1)
83489 #define V_ARLOCKR0(x) ((x) << S_ARLOCKR0)
83490 #define F_ARLOCKR0    V_ARLOCKR0(1U)
83494 #define V_ARCACHER0(x) ((x) << S_ARCACHER0)
83495 #define G_ARCACHER0(x) (((x) >> S_ARCACHER0) & M_ARCACHER0)
83499 #define V_ARPROTR0(x) ((x) << S_ARPROTR0)
83500 #define G_ARPROTR0(x) (((x) >> S_ARPROTR0) & M_ARPROTR0)
83504 #define V_ARSNOOPR0(x) ((x) << S_ARSNOOPR0)
83505 #define G_ARSNOOPR0(x) (((x) >> S_ARSNOOPR0) & M_ARSNOOPR0)
83509 #define V_ARDOMAINR0(x) ((x) << S_ARDOMAINR0)
83510 #define G_ARDOMAINR0(x) (((x) >> S_ARDOMAINR0) & M_ARDOMAINR0)
83516 #define V_SNOOP_END(x) ((x) << S_SNOOP_END)
83517 #define G_SNOOP_END(x) (((x) >> S_SNOOP_END) & M_SNOOP_END)
83521 #define V_SNOOP_START(x) ((x) << S_SNOOP_START)
83522 #define G_SNOOP_START(x) (((x) >> S_SNOOP_START) & M_SNOOP_START)
83527 #define V_TIMER_INT(x) ((x) << S_TIMER_INT)
83528 #define F_TIMER_INT    V_TIMER_INT(1U)
83531 #define V_NVME_INT(x) ((x) << S_NVME_INT)
83532 #define F_NVME_INT    V_NVME_INT(1U)
83535 #define V_EMMC_WAKEUP_INT(x) ((x) << S_EMMC_WAKEUP_INT)
83536 #define F_EMMC_WAKEUP_INT    V_EMMC_WAKEUP_INT(1U)
83539 #define V_EMMC_INT(x) ((x) << S_EMMC_INT)
83540 #define F_EMMC_INT    V_EMMC_INT(1U)
83542 #define S_USB_MC_INT    1
83543 #define V_USB_MC_INT(x) ((x) << S_USB_MC_INT)
83544 #define F_USB_MC_INT    V_USB_MC_INT(1U)
83547 #define V_USB_DMA_INT(x) ((x) << S_USB_DMA_INT)
83548 #define F_USB_DMA_INT    V_USB_DMA_INT(1U)
83554 #define V_PAD4(x) ((x) << S_PAD4)
83555 #define G_PAD4(x) (((x) >> S_PAD4) & M_PAD4)
83559 #define V_ARM_DB_CNT(x) ((x) << S_ARM_DB_CNT)
83560 #define G_ARM_DB_CNT(x) (((x) >> S_ARM_DB_CNT) & M_ARM_DB_CNT)
83569 #define V_WINDOW_EN(x) ((x) << S_WINDOW_EN)
83570 #define F_WINDOW_EN    V_WINDOW_EN(1U)
83573 #define V_RGN2_INT_EN(x) ((x) << S_RGN2_INT_EN)
83574 #define F_RGN2_INT_EN    V_RGN2_INT_EN(1U)
83577 #define V_RGN1_INT_EN(x) ((x) << S_RGN1_INT_EN)
83578 #define F_RGN1_INT_EN    V_RGN1_INT_EN(1U)
83580 #define S_QUEUE_EN    1
83581 #define V_QUEUE_EN(x) ((x) << S_QUEUE_EN)
83582 #define F_QUEUE_EN    V_QUEUE_EN(1U)
83585 #define V_RGN0_INT_EN(x) ((x) << S_RGN0_INT_EN)
83586 #define F_RGN0_INT_EN    V_RGN0_INT_EN(1U)
83592 #define V_DEVICE_SIZE(x) ((x) << S_DEVICE_SIZE)
83593 #define G_DEVICE_SIZE(x) (((x) >> S_DEVICE_SIZE) & M_DEVICE_SIZE)
83597 #define V_RGN1_SIZE(x) ((x) << S_RGN1_SIZE)
83598 #define G_RGN1_SIZE(x) (((x) >> S_RGN1_SIZE) & M_RGN1_SIZE)
83602 #define V_RGN0_SIZE(x) ((x) << S_RGN0_SIZE)
83603 #define G_RGN0_SIZE(x) (((x) >> S_RGN0_SIZE) & M_RGN0_SIZE)
83609 #define V_T7_4_ADDR(x) ((x) << S_T7_4_ADDR)
83610 #define G_T7_4_ADDR(x) (((x) >> S_T7_4_ADDR) & M_T7_4_ADDR)
83618 #define V_T7_CID(x) ((x) << S_T7_CID)
83619 #define G_T7_CID(x) (((x) >> S_T7_CID) & M_T7_CID)
83624 #define V_INT_EN(x) ((x) << S_INT_EN)
83625 #define F_INT_EN    V_INT_EN(1U)
83629 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
83630 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
83634 #define V_T7_1_SIZE(x) ((x) << S_T7_1_SIZE)
83635 #define G_T7_1_SIZE(x) (((x) >> S_T7_1_SIZE) & M_T7_1_SIZE)
83646 #define V_WRDATA_FIFO0_CERR(x) ((x) << S_WRDATA_FIFO0_CERR)
83647 #define F_WRDATA_FIFO0_CERR    V_WRDATA_FIFO0_CERR(1U)
83650 #define V_WRDATA_FIFO1_CERR(x) ((x) << S_WRDATA_FIFO1_CERR)
83651 #define F_WRDATA_FIFO1_CERR    V_WRDATA_FIFO1_CERR(1U)
83654 #define V_WR512DATAFIFO0_CERR(x) ((x) << S_WR512DATAFIFO0_CERR)
83655 #define F_WR512DATAFIFO0_CERR    V_WR512DATAFIFO0_CERR(1U)
83658 #define V_WR512DATAFIFO1_CERR(x) ((x) << S_WR512DATAFIFO1_CERR)
83659 #define F_WR512DATAFIFO1_CERR    V_WR512DATAFIFO1_CERR(1U)
83662 #define V_RDATAFIFO0_CERR(x) ((x) << S_RDATAFIFO0_CERR)
83663 #define F_RDATAFIFO0_CERR    V_RDATAFIFO0_CERR(1U)
83666 #define V_RDATAFIFO1_CERR(x) ((x) << S_RDATAFIFO1_CERR)
83667 #define F_RDATAFIFO1_CERR    V_RDATAFIFO1_CERR(1U)
83670 #define V_ROBUFF_CORERR0(x) ((x) << S_ROBUFF_CORERR0)
83671 #define F_ROBUFF_CORERR0    V_ROBUFF_CORERR0(1U)
83674 #define V_ROBUFF_CORERR1(x) ((x) << S_ROBUFF_CORERR1)
83675 #define F_ROBUFF_CORERR1    V_ROBUFF_CORERR1(1U)
83678 #define V_ROBUFF_CORERR2(x) ((x) << S_ROBUFF_CORERR2)
83679 #define F_ROBUFF_CORERR2    V_ROBUFF_CORERR2(1U)
83682 #define V_ROBUFF_CORERR3(x) ((x) << S_ROBUFF_CORERR3)
83683 #define F_ROBUFF_CORERR3    V_ROBUFF_CORERR3(1U)
83686 #define V_MA2AXI_RSPDATACORERR(x) ((x) << S_MA2AXI_RSPDATACORERR)
83687 #define F_MA2AXI_RSPDATACORERR    V_MA2AXI_RSPDATACORERR(1U)
83691 #define V_RC_SRAM_CERR(x) ((x) << S_RC_SRAM_CERR)
83692 #define G_RC_SRAM_CERR(x) (((x) >> S_RC_SRAM_CERR) & M_RC_SRAM_CERR)
83695 #define V_RC_WFIFO_OUTCERR(x) ((x) << S_RC_WFIFO_OUTCERR)
83696 #define F_RC_WFIFO_OUTCERR    V_RC_WFIFO_OUTCERR(1U)
83699 #define V_RC_RSPFIFO_CERR(x) ((x) << S_RC_RSPFIFO_CERR)
83700 #define F_RC_RSPFIFO_CERR    V_RC_RSPFIFO_CERR(1U)
83703 #define V_MSI_MEM_CERR(x) ((x) << S_MSI_MEM_CERR)
83704 #define F_MSI_MEM_CERR    V_MSI_MEM_CERR(1U)
83707 #define V_INIC_WRDATA_FIFO_CERR(x) ((x) << S_INIC_WRDATA_FIFO_CERR)
83708 #define F_INIC_WRDATA_FIFO_CERR    V_INIC_WRDATA_FIFO_CERR(1U)
83711 #define V_INIC_RDATAFIFO_CERR(x) ((x) << S_INIC_RDATAFIFO_CERR)
83712 #define F_INIC_RDATAFIFO_CERR    V_INIC_RDATAFIFO_CERR(1U)
83716 #define V_ARM_DB_SRAM_CERR(x) ((x) << S_ARM_DB_SRAM_CERR)
83717 #define G_ARM_DB_SRAM_CERR(x) (((x) >> S_ARM_DB_SRAM_CERR) & M_ARM_DB_SRAM_CERR)
83720 #define V_ICB_RAM_CERR(x) ((x) << S_ICB_RAM_CERR)
83721 #define F_ICB_RAM_CERR    V_ICB_RAM_CERR(1U)
83724 #define V_CC_SRAM_PKA_CERR(x) ((x) << S_CC_SRAM_PKA_CERR)
83725 #define F_CC_SRAM_PKA_CERR    V_CC_SRAM_PKA_CERR(1U)
83728 #define V_CC_SRAM_SEC_CERR(x) ((x) << S_CC_SRAM_SEC_CERR)
83729 #define F_CC_SRAM_SEC_CERR    V_CC_SRAM_SEC_CERR(1U)
83734 #define V_INTERRUPT_CLEAR(x) ((x) << S_INTERRUPT_CLEAR)
83735 #define F_INTERRUPT_CLEAR    V_INTERRUPT_CLEAR(1U)
83743 #define V_CPUDBGROMADDR0(x) ((x) << S_CPUDBGROMADDR0)
83744 #define G_CPUDBGROMADDR0(x) (((x) >> S_CPUDBGROMADDR0) & M_CPUDBGROMADDR0)
83750 #define V_CPUDBGROMADDR1(x) ((x) << S_CPUDBGROMADDR1)
83751 #define G_CPUDBGROMADDR1(x) (((x) >> S_CPUDBGROMADDR1) & M_CPUDBGROMADDR1)
83756 #define V_CPUDBGROMADDRVALID(x) ((x) << S_CPUDBGROMADDRVALID)
83757 #define F_CPUDBGROMADDRVALID    V_CPUDBGROMADDRVALID(1U)
83765 #define V_CPUMBISTREQ(x) ((x) << S_CPUMBISTREQ)
83766 #define F_CPUMBISTREQ    V_CPUMBISTREQ(1U)
83769 #define V_CPUMBISTRSTN(x) ((x) << S_CPUMBISTRSTN)
83770 #define F_CPUMBISTRSTN    V_CPUMBISTRSTN(1U)
83773 #define V_CPUDFTDFTSE(x) ((x) << S_CPUDFTDFTSE)
83774 #define F_CPUDFTDFTSE    V_CPUDFTDFTSE(1U)
83777 #define V_CPUDFTRSTDISABLE(x) ((x) << S_CPUDFTRSTDISABLE)
83778 #define F_CPUDFTRSTDISABLE    V_CPUDFTRSTDISABLE(1U)
83781 #define V_CPUDFTRAMDISABLE(x) ((x) << S_CPUDFTRAMDISABLE)
83782 #define F_CPUDFTRAMDISABLE    V_CPUDFTRAMDISABLE(1U)
83785 #define V_CPUDFTMCPDISABLE(x) ((x) << S_CPUDFTMCPDISABLE)
83786 #define F_CPUDFTMCPDISABLE    V_CPUDFTMCPDISABLE(1U)
83789 #define V_CPUDFTL2CLKDISABLE(x) ((x) << S_CPUDFTL2CLKDISABLE)
83790 #define F_CPUDFTL2CLKDISABLE    V_CPUDFTL2CLKDISABLE(1U)
83793 #define V_CPUDFTCLKDISABLE3(x) ((x) << S_CPUDFTCLKDISABLE3)
83794 #define F_CPUDFTCLKDISABLE3    V_CPUDFTCLKDISABLE3(1U)
83797 #define V_CPUDFTCLKDISABLE2(x) ((x) << S_CPUDFTCLKDISABLE2)
83798 #define F_CPUDFTCLKDISABLE2    V_CPUDFTCLKDISABLE2(1U)
83801 #define V_CPUDFTCLKDISABLE1(x) ((x) << S_CPUDFTCLKDISABLE1)
83802 #define F_CPUDFTCLKDISABLE1    V_CPUDFTCLKDISABLE1(1U)
83804 #define S_CPUDFTCLKDISABLE0    1
83805 #define V_CPUDFTCLKDISABLE0(x) ((x) << S_CPUDFTCLKDISABLE0)
83806 #define F_CPUDFTCLKDISABLE0    V_CPUDFTCLKDISABLE0(1U)
83809 #define V_CPUDFTCLKBYPASS(x) ((x) << S_CPUDFTCLKBYPASS)
83810 #define F_CPUDFTCLKBYPASS    V_CPUDFTCLKBYPASS(1U)
83816 #define V_APB_CFG(x) ((x) << S_APB_CFG)
83817 #define G_APB_CFG(x) (((x) >> S_APB_CFG) & M_APB_CFG)
83823 #define V_EMMC_BUFS_OEN(x) ((x) << S_EMMC_BUFS_OEN)
83824 #define G_EMMC_BUFS_OEN(x) (((x) >> S_EMMC_BUFS_OEN) & M_EMMC_BUFS_OEN)
83828 #define V_EMMC_BUFS_I(x) ((x) << S_EMMC_BUFS_I)
83829 #define G_EMMC_BUFS_I(x) (((x) >> S_EMMC_BUFS_I) & M_EMMC_BUFS_I)
83835 #define V_ADBPWRDWNREQN(x) ((x) << S_ADBPWRDWNREQN)
83836 #define F_ADBPWRDWNREQN    V_ADBPWRDWNREQN(1U)
83842 #define V_CPU_GIC_USER(x) ((x) << S_CPU_GIC_USER)
83843 #define G_CPU_GIC_USER(x) (((x) >> S_CPU_GIC_USER) & M_CPU_GIC_USER)
83849 #define V_DBPROC_TH_ADDR(x) ((x) << S_DBPROC_TH_ADDR)
83850 #define G_DBPROC_TH_ADDR(x) (((x) >> S_DBPROC_TH_ADDR) & M_DBPROC_TH_ADDR)
83864 #define V_SWP_EN_2(x) ((x) << S_SWP_EN_2)
83865 #define G_SWP_EN_2(x) (((x) >> S_SWP_EN_2) & M_SWP_EN_2)
83869 #define S_ECC_FATAL    1
83870 #define V_ECC_FATAL(x) ((x) << S_ECC_FATAL)
83871 #define F_ECC_FATAL    V_ECC_FATAL(1U)
83874 #define V_AXIM_ERR(x) ((x) << S_AXIM_ERR)
83875 #define F_AXIM_ERR    V_AXIM_ERR(1U)
83880 #define V_CPU_L2_QACTIVE(x) ((x) << S_CPU_L2_QACTIVE)
83881 #define F_CPU_L2_QACTIVE    V_CPU_L2_QACTIVE(1U)
83884 #define V_WAKEUPM_O_ADB(x) ((x) << S_WAKEUPM_O_ADB)
83885 #define F_WAKEUPM_O_ADB    V_WAKEUPM_O_ADB(1U)
83888 #define V_PWRQACTIVEM_ADB(x) ((x) << S_PWRQACTIVEM_ADB)
83889 #define F_PWRQACTIVEM_ADB    V_PWRQACTIVEM_ADB(1U)
83892 #define V_CLKQACTIVEM_ADB(x) ((x) << S_CLKQACTIVEM_ADB)
83893 #define F_CLKQACTIVEM_ADB    V_CLKQACTIVEM_ADB(1U)
83896 #define V_CLKQDENYM_ADB(x) ((x) << S_CLKQDENYM_ADB)
83897 #define F_CLKQDENYM_ADB    V_CLKQDENYM_ADB(1U)
83900 #define V_CLKQACCEPTNM_ADB(x) ((x) << S_CLKQACCEPTNM_ADB)
83901 #define F_CLKQACCEPTNM_ADB    V_CLKQACCEPTNM_ADB(1U)
83904 #define V_WAKEUPS_O_ADB(x) ((x) << S_WAKEUPS_O_ADB)
83905 #define F_WAKEUPS_O_ADB    V_WAKEUPS_O_ADB(1U)
83908 #define V_PWRQACTIVES_ADB(x) ((x) << S_PWRQACTIVES_ADB)
83909 #define F_PWRQACTIVES_ADB    V_PWRQACTIVES_ADB(1U)
83912 #define V_CLKQACTIVES_ADB(x) ((x) << S_CLKQACTIVES_ADB)
83913 #define F_CLKQACTIVES_ADB    V_CLKQACTIVES_ADB(1U)
83916 #define V_CLKQDENYS_ADB(x) ((x) << S_CLKQDENYS_ADB)
83917 #define F_CLKQDENYS_ADB    V_CLKQDENYS_ADB(1U)
83920 #define V_CLKQACCEPTNS_ADB(x) ((x) << S_CLKQACCEPTNS_ADB)
83921 #define F_CLKQACCEPTNS_ADB    V_CLKQACCEPTNS_ADB(1U)
83923 #define S_PWRQDENYS_ADB    1
83924 #define V_PWRQDENYS_ADB(x) ((x) << S_PWRQDENYS_ADB)
83925 #define F_PWRQDENYS_ADB    V_PWRQDENYS_ADB(1U)
83928 #define V_PWRQACCEPTNS_ADB(x) ((x) << S_PWRQACCEPTNS_ADB)
83929 #define F_PWRQACCEPTNS_ADB    V_PWRQACCEPTNS_ADB(1U)
83935 #define V_DEBUG_INT_WRITE_DATA(x) ((x) << S_DEBUG_INT_WRITE_DATA)
83936 #define G_DEBUG_INT_WRITE_DATA(x) (((x) >> S_DEBUG_INT_WRITE_DATA) & M_DEBUG_INT_WRITE_DATA)
83942 #define V_DEBUG_INT_STATUS_REG(x) ((x) << S_DEBUG_INT_STATUS_REG)
83943 #define G_DEBUG_INT_STATUS_REG(x) (((x) >> S_DEBUG_INT_STATUS_REG) & M_DEBUG_INT_STATUS_REG)
83949 #define V_ARM_DEBUG_STAT(x) ((x) << S_ARM_DEBUG_STAT)
83950 #define G_ARM_DEBUG_STAT(x) (((x) >> S_ARM_DEBUG_STAT) & M_ARM_DEBUG_STAT)
83956 #define V_ARM_SIZE_STAT(x) ((x) << S_ARM_SIZE_STAT)
83957 #define G_ARM_SIZE_STAT(x) (((x) >> S_ARM_SIZE_STAT) & M_ARM_SIZE_STAT)
83963 #define V_CCIBROADCASTCACHEMAINT(x) ((x) << S_CCIBROADCASTCACHEMAINT)
83964 #define G_CCIBROADCASTCACHEMAINT(x) (((x) >> S_CCIBROADCASTCACHEMAINT) & M_CCIBROADCASTCACHEMAINT)
83968 #define V_CCISTRIPINGGRANULE(x) ((x) << S_CCISTRIPINGGRANULE)
83969 #define G_CCISTRIPINGGRANULE(x) (((x) >> S_CCISTRIPINGGRANULE) & M_CCISTRIPINGGRANULE)
83973 #define V_CCIPERIPHBASE(x) ((x) << S_CCIPERIPHBASE)
83974 #define G_CCIPERIPHBASE(x) (((x) >> S_CCIPERIPHBASE) & M_CCIPERIPHBASE)
83979 #define V_CCIDFTRSTDISABLE(x) ((x) << S_CCIDFTRSTDISABLE)
83980 #define F_CCIDFTRSTDISABLE    V_CCIDFTRSTDISABLE(1U)
83983 #define V_CCISPNIDEN(x) ((x) << S_CCISPNIDEN)
83984 #define F_CCISPNIDEN    V_CCISPNIDEN(1U)
83987 #define V_CCINIDEN(x) ((x) << S_CCINIDEN)
83988 #define F_CCINIDEN    V_CCINIDEN(1U)
83992 #define V_CCIACCHANNELN(x) ((x) << S_CCIACCHANNELN)
83993 #define G_CCIACCHANNELN(x) (((x) >> S_CCIACCHANNELN) & M_CCIACCHANNELN)
83997 #define V_CCIQOSOVERRIDE(x) ((x) << S_CCIQOSOVERRIDE)
83998 #define G_CCIQOSOVERRIDE(x) (((x) >> S_CCIQOSOVERRIDE) & M_CCIQOSOVERRIDE)
84002 #define V_CCIBUFFERABLEOVERRIDE(x) ((x) << S_CCIBUFFERABLEOVERRIDE)
84003 #define G_CCIBUFFERABLEOVERRIDE(x) (((x) >> S_CCIBUFFERABLEOVERRIDE) & M_CCIBUFFERABLEOVERRIDE)
84007 #define V_CCIBARRIERTERMINATE(x) ((x) << S_CCIBARRIERTERMINATE)
84008 #define G_CCIBARRIERTERMINATE(x) (((x) >> S_CCIBARRIERTERMINATE) & M_CCIBARRIERTERMINATE)
84014 #define V_CCIADDRMAP15(x) ((x) << S_CCIADDRMAP15)
84015 #define G_CCIADDRMAP15(x) (((x) >> S_CCIADDRMAP15) & M_CCIADDRMAP15)
84019 #define V_CCIADDRMAP14(x) ((x) << S_CCIADDRMAP14)
84020 #define G_CCIADDRMAP14(x) (((x) >> S_CCIADDRMAP14) & M_CCIADDRMAP14)
84024 #define V_CCIADDRMAP13(x) ((x) << S_CCIADDRMAP13)
84025 #define G_CCIADDRMAP13(x) (((x) >> S_CCIADDRMAP13) & M_CCIADDRMAP13)
84029 #define V_CCIADDRMAP12(x) ((x) << S_CCIADDRMAP12)
84030 #define G_CCIADDRMAP12(x) (((x) >> S_CCIADDRMAP12) & M_CCIADDRMAP12)
84034 #define V_CCIADDRMAP11(x) ((x) << S_CCIADDRMAP11)
84035 #define G_CCIADDRMAP11(x) (((x) >> S_CCIADDRMAP11) & M_CCIADDRMAP11)
84039 #define V_CCIADDRMAP10(x) ((x) << S_CCIADDRMAP10)
84040 #define G_CCIADDRMAP10(x) (((x) >> S_CCIADDRMAP10) & M_CCIADDRMAP10)
84044 #define V_CCIADDRMAP9(x) ((x) << S_CCIADDRMAP9)
84045 #define G_CCIADDRMAP9(x) (((x) >> S_CCIADDRMAP9) & M_CCIADDRMAP9)
84049 #define V_CCIADDRMAP8(x) ((x) << S_CCIADDRMAP8)
84050 #define G_CCIADDRMAP8(x) (((x) >> S_CCIADDRMAP8) & M_CCIADDRMAP8)
84054 #define V_CCIADDRMAP7(x) ((x) << S_CCIADDRMAP7)
84055 #define G_CCIADDRMAP7(x) (((x) >> S_CCIADDRMAP7) & M_CCIADDRMAP7)
84059 #define V_CCIADDRMAP6(x) ((x) << S_CCIADDRMAP6)
84060 #define G_CCIADDRMAP6(x) (((x) >> S_CCIADDRMAP6) & M_CCIADDRMAP6)
84064 #define V_CCIADDRMAP5(x) ((x) << S_CCIADDRMAP5)
84065 #define G_CCIADDRMAP5(x) (((x) >> S_CCIADDRMAP5) & M_CCIADDRMAP5)
84069 #define V_CCIADDRMAP4(x) ((x) << S_CCIADDRMAP4)
84070 #define G_CCIADDRMAP4(x) (((x) >> S_CCIADDRMAP4) & M_CCIADDRMAP4)
84074 #define V_CCIADDRMAP3(x) ((x) << S_CCIADDRMAP3)
84075 #define G_CCIADDRMAP3(x) (((x) >> S_CCIADDRMAP3) & M_CCIADDRMAP3)
84079 #define V_CCIADDRMAP2(x) ((x) << S_CCIADDRMAP2)
84080 #define G_CCIADDRMAP2(x) (((x) >> S_CCIADDRMAP2) & M_CCIADDRMAP2)
84084 #define V_CCIADDRMAP1(x) ((x) << S_CCIADDRMAP1)
84085 #define G_CCIADDRMAP1(x) (((x) >> S_CCIADDRMAP1) & M_CCIADDRMAP1)
84089 #define V_CCIADDRMAP0(x) ((x) << S_CCIADDRMAP0)
84090 #define G_CCIADDRMAP0(x) (((x) >> S_CCIADDRMAP0) & M_CCIADDRMAP0)
84095 #define V_CCICACTIVE(x) ((x) << S_CCICACTIVE)
84096 #define F_CCICACTIVE    V_CCICACTIVE(1U)
84099 #define V_CCICSYSACK(x) ((x) << S_CCICSYSACK)
84100 #define F_CCICSYSACK    V_CCICSYSACK(1U)
84104 #define V_CCINEVNTCNTOVERFLOW(x) ((x) << S_CCINEVNTCNTOVERFLOW)
84105 #define G_CCINEVNTCNTOVERFLOW(x) (((x) >> S_CCINEVNTCNTOVERFLOW) & M_CCINEVNTCNTOVERFLOW)
84110 #define V_CCIVWREADYVN3M(x) ((x) << S_CCIVWREADYVN3M)
84111 #define F_CCIVWREADYVN3M    V_CCIVWREADYVN3M(1U)
84114 #define V_CCIVAWREADYVN3M(x) ((x) << S_CCIVAWREADYVN3M)
84115 #define F_CCIVAWREADYVN3M    V_CCIVAWREADYVN3M(1U)
84118 #define V_CCIVARREADYVN3M(x) ((x) << S_CCIVARREADYVN3M)
84119 #define F_CCIVARREADYVN3M    V_CCIVARREADYVN3M(1U)
84122 #define V_CCIVWREADYVN2M(x) ((x) << S_CCIVWREADYVN2M)
84123 #define F_CCIVWREADYVN2M    V_CCIVWREADYVN2M(1U)
84126 #define V_CCIVAWREADYVN2M(x) ((x) << S_CCIVAWREADYVN2M)
84127 #define F_CCIVAWREADYVN2M    V_CCIVAWREADYVN2M(1U)
84130 #define V_CCIVARREADYVN2M(x) ((x) << S_CCIVARREADYVN2M)
84131 #define F_CCIVARREADYVN2M    V_CCIVARREADYVN2M(1U)
84134 #define V_CCIVWREADYVN1M(x) ((x) << S_CCIVWREADYVN1M)
84135 #define F_CCIVWREADYVN1M    V_CCIVWREADYVN1M(1U)
84138 #define V_CCIVAWREADYVN1M(x) ((x) << S_CCIVAWREADYVN1M)
84139 #define F_CCIVAWREADYVN1M    V_CCIVAWREADYVN1M(1U)
84142 #define V_CCIVARREADYVN1M(x) ((x) << S_CCIVARREADYVN1M)
84143 #define F_CCIVARREADYVN1M    V_CCIVARREADYVN1M(1U)
84146 #define V_CCIVWREADYVN0M(x) ((x) << S_CCIVWREADYVN0M)
84147 #define F_CCIVWREADYVN0M    V_CCIVWREADYVN0M(1U)
84150 #define V_CCIVAWREADYVN0M(x) ((x) << S_CCIVAWREADYVN0M)
84151 #define F_CCIVAWREADYVN0M    V_CCIVAWREADYVN0M(1U)
84154 #define V_CCIVARREADYVN0M(x) ((x) << S_CCIVARREADYVN0M)
84155 #define F_CCIVARREADYVN0M    V_CCIVARREADYVN0M(1U)
84159 #define V_CCIQVNPREALLOCWM(x) ((x) << S_CCIQVNPREALLOCWM)
84160 #define G_CCIQVNPREALLOCWM(x) (((x) >> S_CCIQVNPREALLOCWM) & M_CCIQVNPREALLOCWM)
84162 #define S_CCIQVNPREALLOCRM    1
84164 #define V_CCIQVNPREALLOCRM(x) ((x) << S_CCIQVNPREALLOCRM)
84165 #define G_CCIQVNPREALLOCRM(x) (((x) >> S_CCIQVNPREALLOCRM) & M_CCIQVNPREALLOCRM)
84168 #define V_CCIQVNENABLEM(x) ((x) << S_CCIQVNENABLEM)
84169 #define F_CCIQVNENABLEM    V_CCIQVNENABLEM(1U)
84174 #define V_CCIVWVALIDN3M(x) ((x) << S_CCIVWVALIDN3M)
84175 #define F_CCIVWVALIDN3M    V_CCIVWVALIDN3M(1U)
84178 #define V_CCIVAWVALIDN3M(x) ((x) << S_CCIVAWVALIDN3M)
84179 #define F_CCIVAWVALIDN3M    V_CCIVAWVALIDN3M(1U)
84182 #define V_CCIVAWQOSN3M(x) ((x) << S_CCIVAWQOSN3M)
84183 #define F_CCIVAWQOSN3M    V_CCIVAWQOSN3M(1U)
84186 #define V_CCIVARVALIDN3M(x) ((x) << S_CCIVARVALIDN3M)
84187 #define F_CCIVARVALIDN3M    V_CCIVARVALIDN3M(1U)
84191 #define V_CCIVARQOSN3M(x) ((x) << S_CCIVARQOSN3M)
84192 #define G_CCIVARQOSN3M(x) (((x) >> S_CCIVARQOSN3M) & M_CCIVARQOSN3M)
84195 #define V_CCIVWVALIDN2M(x) ((x) << S_CCIVWVALIDN2M)
84196 #define F_CCIVWVALIDN2M    V_CCIVWVALIDN2M(1U)
84199 #define V_CCIVAWVALIDN2M(x) ((x) << S_CCIVAWVALIDN2M)
84200 #define F_CCIVAWVALIDN2M    V_CCIVAWVALIDN2M(1U)
84203 #define V_CCIVAWQOSN2M(x) ((x) << S_CCIVAWQOSN2M)
84204 #define F_CCIVAWQOSN2M    V_CCIVAWQOSN2M(1U)
84207 #define V_CCIVARVALIDN2M(x) ((x) << S_CCIVARVALIDN2M)
84208 #define F_CCIVARVALIDN2M    V_CCIVARVALIDN2M(1U)
84212 #define V_CCIVARQOSN2M(x) ((x) << S_CCIVARQOSN2M)
84213 #define G_CCIVARQOSN2M(x) (((x) >> S_CCIVARQOSN2M) & M_CCIVARQOSN2M)
84216 #define V_CCIVWVALIDN1M(x) ((x) << S_CCIVWVALIDN1M)
84217 #define F_CCIVWVALIDN1M    V_CCIVWVALIDN1M(1U)
84220 #define V_CCIVAWVALIDN1M(x) ((x) << S_CCIVAWVALIDN1M)
84221 #define F_CCIVAWVALIDN1M    V_CCIVAWVALIDN1M(1U)
84224 #define V_CCIVAWQOSN1M(x) ((x) << S_CCIVAWQOSN1M)
84225 #define F_CCIVAWQOSN1M    V_CCIVAWQOSN1M(1U)
84228 #define V_CCIVARVALIDN1M(x) ((x) << S_CCIVARVALIDN1M)
84229 #define F_CCIVARVALIDN1M    V_CCIVARVALIDN1M(1U)
84233 #define V_CCIVARQOSN1M(x) ((x) << S_CCIVARQOSN1M)
84234 #define G_CCIVARQOSN1M(x) (((x) >> S_CCIVARQOSN1M) & M_CCIVARQOSN1M)
84237 #define V_CCIVWVALIDN0M(x) ((x) << S_CCIVWVALIDN0M)
84238 #define F_CCIVWVALIDN0M    V_CCIVWVALIDN0M(1U)
84241 #define V_CCIVAWVALIDN0M(x) ((x) << S_CCIVAWVALIDN0M)
84242 #define F_CCIVAWVALIDN0M    V_CCIVAWVALIDN0M(1U)
84245 #define V_CCIVAWQOSN0M(x) ((x) << S_CCIVAWQOSN0M)
84246 #define F_CCIVAWQOSN0M    V_CCIVAWQOSN0M(1U)
84249 #define V_CCIVARVALIDN0M(x) ((x) << S_CCIVARVALIDN0M)
84250 #define F_CCIVARVALIDN0M    V_CCIVARVALIDN0M(1U)
84254 #define V_CCIVARQOSN0M(x) ((x) << S_CCIVARQOSN0M)
84255 #define G_CCIVARQOSN0M(x) (((x) >> S_CCIVARQOSN0M) & M_CCIVARQOSN0M)
84261 #define V_CCIQVNVNETS(x) ((x) << S_CCIQVNVNETS)
84262 #define G_CCIQVNVNETS(x) (((x) >> S_CCIQVNVNETS) & M_CCIQVNVNETS)
84268 #define V_CCIEVNTAWQOS(x) ((x) << S_CCIEVNTAWQOS)
84269 #define G_CCIEVNTAWQOS(x) (((x) >> S_CCIEVNTAWQOS) & M_CCIEVNTAWQOS)
84273 #define V_CCIEVNTARQOS(x) ((x) << S_CCIEVNTARQOS)
84274 #define G_CCIEVNTARQOS(x) (((x) >> S_CCIEVNTARQOS) & M_CCIEVNTARQOS)
84280 #define V_CCIRSTN(x) ((x) << S_CCIRSTN)
84281 #define F_CCIRSTN    V_CCIRSTN(1U)
84286 #define V_CCICSYSREQ(x) ((x) << S_CCICSYSREQ)
84287 #define F_CCICSYSREQ    V_CCICSYSREQ(1U)
84293 #define V_CCIS0RCNT(x) ((x) << S_CCIS0RCNT)
84294 #define G_CCIS0RCNT(x) (((x) >> S_CCIS0RCNT) & M_CCIS0RCNT)
84298 #define V_CCIS0ARCNT(x) ((x) << S_CCIS0ARCNT)
84299 #define G_CCIS0ARCNT(x) (((x) >> S_CCIS0ARCNT) & M_CCIS0ARCNT)
84303 #define V_CCIS0WCNT(x) ((x) << S_CCIS0WCNT)
84304 #define G_CCIS0WCNT(x) (((x) >> S_CCIS0WCNT) & M_CCIS0WCNT)
84308 #define V_CCIS0AWCNT(x) ((x) << S_CCIS0AWCNT)
84309 #define G_CCIS0AWCNT(x) (((x) >> S_CCIS0AWCNT) & M_CCIS0AWCNT)
84315 #define V_CCIS1RCNT(x) ((x) << S_CCIS1RCNT)
84316 #define G_CCIS1RCNT(x) (((x) >> S_CCIS1RCNT) & M_CCIS1RCNT)
84320 #define V_CCIS1ARCNT(x) ((x) << S_CCIS1ARCNT)
84321 #define G_CCIS1ARCNT(x) (((x) >> S_CCIS1ARCNT) & M_CCIS1ARCNT)
84325 #define V_CCIS1WCNT(x) ((x) << S_CCIS1WCNT)
84326 #define G_CCIS1WCNT(x) (((x) >> S_CCIS1WCNT) & M_CCIS1WCNT)
84330 #define V_CCIS1AWCNT(x) ((x) << S_CCIS1AWCNT)
84331 #define G_CCIS1AWCNT(x) (((x) >> S_CCIS1AWCNT) & M_CCIS1AWCNT)
84337 #define V_CCIS2RCNT(x) ((x) << S_CCIS2RCNT)
84338 #define G_CCIS2RCNT(x) (((x) >> S_CCIS2RCNT) & M_CCIS2RCNT)
84342 #define V_CCIS2ARCNT(x) ((x) << S_CCIS2ARCNT)
84343 #define G_CCIS2ARCNT(x) (((x) >> S_CCIS2ARCNT) & M_CCIS2ARCNT)
84347 #define V_CCIS2WCNT(x) ((x) << S_CCIS2WCNT)
84348 #define G_CCIS2WCNT(x) (((x) >> S_CCIS2WCNT) & M_CCIS2WCNT)
84352 #define V_CCIS2AWCNT(x) ((x) << S_CCIS2AWCNT)
84353 #define G_CCIS2AWCNT(x) (((x) >> S_CCIS2AWCNT) & M_CCIS2AWCNT)
84359 #define V_CCIS3RCNT(x) ((x) << S_CCIS3RCNT)
84360 #define G_CCIS3RCNT(x) (((x) >> S_CCIS3RCNT) & M_CCIS3RCNT)
84364 #define V_CCIS3ARCNT(x) ((x) << S_CCIS3ARCNT)
84365 #define G_CCIS3ARCNT(x) (((x) >> S_CCIS3ARCNT) & M_CCIS3ARCNT)
84369 #define V_CCIS3WCNT(x) ((x) << S_CCIS3WCNT)
84370 #define G_CCIS3WCNT(x) (((x) >> S_CCIS3WCNT) & M_CCIS3WCNT)
84374 #define V_CCIS3AWCNT(x) ((x) << S_CCIS3AWCNT)
84375 #define G_CCIS3AWCNT(x) (((x) >> S_CCIS3AWCNT) & M_CCIS3AWCNT)
84381 #define V_CCIS4RCNT(x) ((x) << S_CCIS4RCNT)
84382 #define G_CCIS4RCNT(x) (((x) >> S_CCIS4RCNT) & M_CCIS4RCNT)
84386 #define V_CCIS4ARCNT(x) ((x) << S_CCIS4ARCNT)
84387 #define G_CCIS4ARCNT(x) (((x) >> S_CCIS4ARCNT) & M_CCIS4ARCNT)
84391 #define V_CCIS4WCNT(x) ((x) << S_CCIS4WCNT)
84392 #define G_CCIS4WCNT(x) (((x) >> S_CCIS4WCNT) & M_CCIS4WCNT)
84396 #define V_CCIS4AWCNT(x) ((x) << S_CCIS4AWCNT)
84397 #define G_CCIS4AWCNT(x) (((x) >> S_CCIS4AWCNT) & M_CCIS4AWCNT)
84403 #define V_CCIS4RSPCNT(x) ((x) << S_CCIS4RSPCNT)
84404 #define G_CCIS4RSPCNT(x) (((x) >> S_CCIS4RSPCNT) & M_CCIS4RSPCNT)
84408 #define V_CCIS4ACCNT(x) ((x) << S_CCIS4ACCNT)
84409 #define G_CCIS4ACCNT(x) (((x) >> S_CCIS4ACCNT) & M_CCIS4ACCNT)
84413 #define V_CCIS3RSPCNT(x) ((x) << S_CCIS3RSPCNT)
84414 #define G_CCIS3RSPCNT(x) (((x) >> S_CCIS3RSPCNT) & M_CCIS3RSPCNT)
84418 #define V_CCIS3ACCNT(x) ((x) << S_CCIS3ACCNT)
84419 #define G_CCIS3ACCNT(x) (((x) >> S_CCIS3ACCNT) & M_CCIS3ACCNT)
84425 #define V_CCIM0RCNT(x) ((x) << S_CCIM0RCNT)
84426 #define G_CCIM0RCNT(x) (((x) >> S_CCIM0RCNT) & M_CCIM0RCNT)
84430 #define V_CCIM0ARCNT(x) ((x) << S_CCIM0ARCNT)
84431 #define G_CCIM0ARCNT(x) (((x) >> S_CCIM0ARCNT) & M_CCIM0ARCNT)
84435 #define V_CCIM0WCNT(x) ((x) << S_CCIM0WCNT)
84436 #define G_CCIM0WCNT(x) (((x) >> S_CCIM0WCNT) & M_CCIM0WCNT)
84440 #define V_CCIM0AWCNT(x) ((x) << S_CCIM0AWCNT)
84441 #define G_CCIM0AWCNT(x) (((x) >> S_CCIM0AWCNT) & M_CCIM0AWCNT)
84447 #define V_CCIM1RCNT(x) ((x) << S_CCIM1RCNT)
84448 #define G_CCIM1RCNT(x) (((x) >> S_CCIM1RCNT) & M_CCIM1RCNT)
84452 #define V_CCIM1ARCNT(x) ((x) << S_CCIM1ARCNT)
84453 #define G_CCIM1ARCNT(x) (((x) >> S_CCIM1ARCNT) & M_CCIM1ARCNT)
84457 #define V_CCIM1WCNT(x) ((x) << S_CCIM1WCNT)
84458 #define G_CCIM1WCNT(x) (((x) >> S_CCIM1WCNT) & M_CCIM1WCNT)
84462 #define V_CCIM1AWCNT(x) ((x) << S_CCIM1AWCNT)
84463 #define G_CCIM1AWCNT(x) (((x) >> S_CCIM1AWCNT) & M_CCIM1AWCNT)
84469 #define V_CCIM2RCNT(x) ((x) << S_CCIM2RCNT)
84470 #define G_CCIM2RCNT(x) (((x) >> S_CCIM2RCNT) & M_CCIM2RCNT)
84474 #define V_CCIM2ARCNT(x) ((x) << S_CCIM2ARCNT)
84475 #define G_CCIM2ARCNT(x) (((x) >> S_CCIM2ARCNT) & M_CCIM2ARCNT)
84479 #define V_CCIM2WCNT(x) ((x) << S_CCIM2WCNT)
84480 #define G_CCIM2WCNT(x) (((x) >> S_CCIM2WCNT) & M_CCIM2WCNT)
84484 #define V_CCIM2AWCNT(x) ((x) << S_CCIM2AWCNT)
84485 #define G_CCIM2AWCNT(x) (((x) >> S_CCIM2AWCNT) & M_CCIM2AWCNT)
84491 #define V_MA1_RD_CNT(x) ((x) << S_MA1_RD_CNT)
84492 #define G_MA1_RD_CNT(x) (((x) >> S_MA1_RD_CNT) & M_MA1_RD_CNT)
84496 #define V_MA1_WR_CNT(x) ((x) << S_MA1_WR_CNT)
84497 #define G_MA1_WR_CNT(x) (((x) >> S_MA1_WR_CNT) & M_MA1_WR_CNT)
84501 #define V_MA0_RD_CNT(x) ((x) << S_MA0_RD_CNT)
84502 #define G_MA0_RD_CNT(x) (((x) >> S_MA0_RD_CNT) & M_MA0_RD_CNT)
84506 #define V_MA0_WR_CNT(x) ((x) << S_MA0_WR_CNT)
84507 #define G_MA0_WR_CNT(x) (((x) >> S_MA0_WR_CNT) & M_MA0_WR_CNT)
84513 #define V_GP_INT(x) ((x) << S_GP_INT)
84514 #define G_GP_INT(x) (((x) >> S_GP_INT) & M_GP_INT)
84521 #define V_DMABOOTPERIPHNS(x) ((x) << S_DMABOOTPERIPHNS)
84522 #define G_DMABOOTPERIPHNS(x) (((x) >> S_DMABOOTPERIPHNS) & M_DMABOOTPERIPHNS)
84526 #define V_DMABOOTIRQNS(x) ((x) << S_DMABOOTIRQNS)
84527 #define G_DMABOOTIRQNS(x) (((x) >> S_DMABOOTIRQNS) & M_DMABOOTIRQNS)
84529 #define S_DMABOOTMANAGERNS    1
84530 #define V_DMABOOTMANAGERNS(x) ((x) << S_DMABOOTMANAGERNS)
84531 #define F_DMABOOTMANAGERNS    V_DMABOOTMANAGERNS(1U)
84534 #define V_DMABOOTFROMPC(x) ((x) << S_DMABOOTFROMPC)
84535 #define F_DMABOOTFROMPC    V_DMABOOTFROMPC(1U)
84540 #define V_MESSAGEBYPASS_DATA(x) ((x) << S_MESSAGEBYPASS_DATA)
84541 #define F_MESSAGEBYPASS_DATA    V_MESSAGEBYPASS_DATA(1U)
84543 #define S_MESSAGEBYPASS    1
84544 #define V_MESSAGEBYPASS(x) ((x) << S_MESSAGEBYPASS)
84545 #define F_MESSAGEBYPASS    V_MESSAGEBYPASS(1U)
84548 #define V_PCIEBYPASS(x) ((x) << S_PCIEBYPASS)
84549 #define F_PCIEBYPASS    V_PCIEBYPASS(1U)
84557 #define V_ADDRREG0(x) ((x) << S_ADDRREG0)
84558 #define G_ADDRREG0(x) (((x) >> S_ADDRREG0) & M_ADDRREG0)
84564 #define V_ADDRREG1(x) ((x) << S_ADDRREG1)
84565 #define G_ADDRREG1(x) (((x) >> S_ADDRREG1) & M_ADDRREG1)
84571 #define V_ADDRREG2(x) ((x) << S_ADDRREG2)
84572 #define G_ADDRREG2(x) (((x) >> S_ADDRREG2) & M_ADDRREG2)
84578 #define V_ADDRREG3(x) ((x) << S_ADDRREG3)
84579 #define G_ADDRREG3(x) (((x) >> S_ADDRREG3) & M_ADDRREG3)
84585 #define V_ADDRREG4(x) ((x) << S_ADDRREG4)
84586 #define G_ADDRREG4(x) (((x) >> S_ADDRREG4) & M_ADDRREG4)
84592 #define V_ADDRREG5(x) ((x) << S_ADDRREG5)
84593 #define G_ADDRREG5(x) (((x) >> S_ADDRREG5) & M_ADDRREG5)
84599 #define V_ADDRREG6(x) ((x) << S_ADDRREG6)
84600 #define G_ADDRREG6(x) (((x) >> S_ADDRREG6) & M_ADDRREG6)
84606 #define V_ADDRREG7(x) ((x) << S_ADDRREG7)
84607 #define G_ADDRREG7(x) (((x) >> S_ADDRREG7) & M_ADDRREG7)
84613 #define V_INT_GEN(x) ((x) << S_INT_GEN)
84614 #define G_INT_GEN(x) (((x) >> S_INT_GEN) & M_INT_GEN)
84620 #define V_INT_CLEAR(x) ((x) << S_INT_CLEAR)
84621 #define G_INT_CLEAR(x) (((x) >> S_INT_CLEAR) & M_INT_CLEAR)
84628 #define V_NO_OF_INTERRUPTS(x) ((x) << S_NO_OF_INTERRUPTS)
84629 #define G_NO_OF_INTERRUPTS(x) (((x) >> S_NO_OF_INTERRUPTS) & M_NO_OF_INTERRUPTS)
84634 #define V_ARWFIFO0_PERR(x) ((x) << S_ARWFIFO0_PERR)
84635 #define F_ARWFIFO0_PERR    V_ARWFIFO0_PERR(1U)
84638 #define V_ARWFIFO1_PERR(x) ((x) << S_ARWFIFO1_PERR)
84639 #define F_ARWFIFO1_PERR    V_ARWFIFO1_PERR(1U)
84642 #define V_ARWIDFIFO0_PERR(x) ((x) << S_ARWIDFIFO0_PERR)
84643 #define F_ARWIDFIFO0_PERR    V_ARWIDFIFO0_PERR(1U)
84646 #define V_ARWIDFIFO1_PERR(x) ((x) << S_ARWIDFIFO1_PERR)
84647 #define F_ARWIDFIFO1_PERR    V_ARWIDFIFO1_PERR(1U)
84650 #define V_ARIDFIFO0_PERR(x) ((x) << S_ARIDFIFO0_PERR)
84651 #define F_ARIDFIFO0_PERR    V_ARIDFIFO0_PERR(1U)
84654 #define V_ARIDFIFO1_PERR(x) ((x) << S_ARIDFIFO1_PERR)
84655 #define F_ARIDFIFO1_PERR    V_ARIDFIFO1_PERR(1U)
84658 #define V_RRSPADDR_FIFO0_PERR(x) ((x) << S_RRSPADDR_FIFO0_PERR)
84659 #define F_RRSPADDR_FIFO0_PERR    V_RRSPADDR_FIFO0_PERR(1U)
84662 #define V_RRSPADDR_FIFO1_PERR(x) ((x) << S_RRSPADDR_FIFO1_PERR)
84663 #define F_RRSPADDR_FIFO1_PERR    V_RRSPADDR_FIFO1_PERR(1U)
84666 #define V_WRSTRB_FIFO0_PERR(x) ((x) << S_WRSTRB_FIFO0_PERR)
84667 #define F_WRSTRB_FIFO0_PERR    V_WRSTRB_FIFO0_PERR(1U)
84670 #define V_WRSTRB_FIFO1_PERR(x) ((x) << S_WRSTRB_FIFO1_PERR)
84671 #define F_WRSTRB_FIFO1_PERR    V_WRSTRB_FIFO1_PERR(1U)
84674 #define V_MA2AXI_RSPDATAPARERR(x) ((x) << S_MA2AXI_RSPDATAPARERR)
84675 #define F_MA2AXI_RSPDATAPARERR    V_MA2AXI_RSPDATAPARERR(1U)
84678 #define V_MA2AXI_DATA_PAR_ERR(x) ((x) << S_MA2AXI_DATA_PAR_ERR)
84679 #define F_MA2AXI_DATA_PAR_ERR    V_MA2AXI_DATA_PAR_ERR(1U)
84682 #define V_MA2AXI_WR_ORD_FIFO_PARERR(x) ((x) << S_MA2AXI_WR_ORD_FIFO_PARERR)
84683 #define F_MA2AXI_WR_ORD_FIFO_PARERR    V_MA2AXI_WR_ORD_FIFO_PARERR(1U)
84686 #define V_NVME_DB_EMU_TRACKER_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_TRACKER_FIFO_PERR)
84687 #define F_NVME_DB_EMU_TRACKER_FIFO_PERR    V_NVME_DB_EMU_TRACKER_FIFO_PERR(1U)
84690 #define V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR)
84691 #define F_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR    V_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR(1U)
84694 #define V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(x) ((x) << S_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR)
84695 #define F_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR    V_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR(1U)
84698 #define V_NVME_DB_EMU_ID_FIFO0_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO0_PERR)
84699 #define F_NVME_DB_EMU_ID_FIFO0_PERR    V_NVME_DB_EMU_ID_FIFO0_PERR(1U)
84702 #define V_NVME_DB_EMU_ID_FIFO1_PERR(x) ((x) << S_NVME_DB_EMU_ID_FIFO1_PERR)
84703 #define F_NVME_DB_EMU_ID_FIFO1_PERR    V_NVME_DB_EMU_ID_FIFO1_PERR(1U)
84706 #define V_RC_ARWFIFO_PERR(x) ((x) << S_RC_ARWFIFO_PERR)
84707 #define F_RC_ARWFIFO_PERR    V_RC_ARWFIFO_PERR(1U)
84710 #define V_RC_ARIDBURSTADDRFIFO_PERR(x) ((x) << S_RC_ARIDBURSTADDRFIFO_PERR)
84711 #define F_RC_ARIDBURSTADDRFIFO_PERR    V_RC_ARIDBURSTADDRFIFO_PERR(1U)
84714 #define V_RC_CFG_FIFO_PERR(x) ((x) << S_RC_CFG_FIFO_PERR)
84715 #define F_RC_CFG_FIFO_PERR    V_RC_CFG_FIFO_PERR(1U)
84718 #define V_RC_RSPFIFO_PERR(x) ((x) << S_RC_RSPFIFO_PERR)
84719 #define F_RC_RSPFIFO_PERR    V_RC_RSPFIFO_PERR(1U)
84722 #define V_INIC_ARIDFIFO_PERR(x) ((x) << S_INIC_ARIDFIFO_PERR)
84723 #define F_INIC_ARIDFIFO_PERR    V_INIC_ARIDFIFO_PERR(1U)
84726 #define V_INIC_ARWFIFO_PERR(x) ((x) << S_INIC_ARWFIFO_PERR)
84727 #define F_INIC_ARWFIFO_PERR    V_INIC_ARWFIFO_PERR(1U)
84730 #define V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR)
84731 #define F_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR(1U)
84734 #define V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(x) ((x) << S_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR)
84735 #define F_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR    V_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR(1U)
84738 #define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR)
84739 #define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR(1U)
84742 #define V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(x) ((x) << S_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR)
84743 #define F_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR    V_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR(1U)
84746 #define V_ARM_MA_512B_ARB_FIFO_PERR(x) ((x) << S_ARM_MA_512B_ARB_FIFO_PERR)
84747 #define F_ARM_MA_512B_ARB_FIFO_PERR    V_ARM_MA_512B_ARB_FIFO_PERR(1U)
84750 #define V_PCIE_INIC_MA_ARB_FIFO_PERR(x) ((x) << S_PCIE_INIC_MA_ARB_FIFO_PERR)
84751 #define F_PCIE_INIC_MA_ARB_FIFO_PERR    V_PCIE_INIC_MA_ARB_FIFO_PERR(1U)
84753 #define S_PCIE_INIC_ARB_RSPPERR    1
84754 #define V_PCIE_INIC_ARB_RSPPERR(x) ((x) << S_PCIE_INIC_ARB_RSPPERR)
84755 #define F_PCIE_INIC_ARB_RSPPERR    V_PCIE_INIC_ARB_RSPPERR(1U)
84758 #define V_ITE_CACHE_PERR(x) ((x) << S_ITE_CACHE_PERR)
84759 #define F_ITE_CACHE_PERR    V_ITE_CACHE_PERR(1U)
84768 #define V_ADDRREGDST(x) ((x) << S_ADDRREGDST)
84769 #define G_ADDRREGDST(x) (((x) >> S_ADDRREGDST) & M_ADDRREGDST)
84774 #define V_STRB0_ERROR(x) ((x) << S_STRB0_ERROR)
84775 #define F_STRB0_ERROR    V_STRB0_ERROR(1U)
84778 #define V_STRB1_ERROR(x) ((x) << S_STRB1_ERROR)
84779 #define F_STRB1_ERROR    V_STRB1_ERROR(1U)
84782 #define V_PCIE_INIC_MA_ARB_INV_RSP_TAG(x) ((x) << S_PCIE_INIC_MA_ARB_INV_RSP_TAG)
84783 #define F_PCIE_INIC_MA_ARB_INV_RSP_TAG    V_PCIE_INIC_MA_ARB_INV_RSP_TAG(1U)
84786 #define V_ERROR0_NOCMD_DATA(x) ((x) << S_ERROR0_NOCMD_DATA)
84787 #define F_ERROR0_NOCMD_DATA    V_ERROR0_NOCMD_DATA(1U)
84790 #define V_ERROR1_NOCMD_DATA(x) ((x) << S_ERROR1_NOCMD_DATA)
84791 #define F_ERROR1_NOCMD_DATA    V_ERROR1_NOCMD_DATA(1U)
84794 #define V_INIC_STRB_ERROR(x) ((x) << S_INIC_STRB_ERROR)
84795 #define F_INIC_STRB_ERROR    V_INIC_STRB_ERROR(1U)
84806 #define V_BASEADDRESS(x) ((x) << S_BASEADDRESS)
84807 #define G_BASEADDRESS(x) (((x) >> S_BASEADDRESS) & M_BASEADDRESS)
84813 #define V_WATERMARK(x) ((x) << S_WATERMARK)
84814 #define G_WATERMARK(x) (((x) >> S_WATERMARK) & M_WATERMARK)
84818 #define V_SIZEMAX(x) ((x) << S_SIZEMAX)
84819 #define G_SIZEMAX(x) (((x) >> S_SIZEMAX) & M_SIZEMAX)
84826 #define V_CPUREADADDRESS(x) ((x) << S_CPUREADADDRESS)
84827 #define G_CPUREADADDRESS(x) (((x) >> S_CPUREADADDRESS) & M_CPUREADADDRESS)
84832 #define V_CPUREADADDRESSVLD(x) ((x) << S_CPUREADADDRESSVLD)
84833 #define F_CPUREADADDRESSVLD    V_CPUREADADDRESSVLD(1U)
84848 #define V_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) ((x) << S_ARM_APB2MSI_INT_PRIORITY_LEVEL)
84849 #define G_ARM_APB2MSI_INT_PRIORITY_LEVEL(x) (((x) >> S_ARM_APB2MSI_INT_PRIORITY_LEVEL) & M_ARM_APB2MSI_INT_PRIORITY_LEVEL)
84855 #define V_ARM_APB2MSI_MEM_READ_ADDR(x) ((x) << S_ARM_APB2MSI_MEM_READ_ADDR)
84856 #define G_ARM_APB2MSI_MEM_READ_ADDR(x) (((x) >> S_ARM_APB2MSI_MEM_READ_ADDR) & M_ARM_APB2MSI_MEM_READ_ADDR)
84863 #define V_CONFIGDONE(x) ((x) << S_CONFIGDONE)
84864 #define F_CONFIGDONE    V_CONFIGDONE(1U)
84870 #define V_ARMMA2AXI1ARTRTYPE(x) ((x) << S_ARMMA2AXI1ARTRTYPE)
84871 #define F_ARMMA2AXI1ARTRTYPE    V_ARMMA2AXI1ARTRTYPE(1U)
84874 #define V_ARMMA2AXI1AWTRTYPE(x) ((x) << S_ARMMA2AXI1AWTRTYPE)
84875 #define F_ARMMA2AXI1AWTRTYPE    V_ARMMA2AXI1AWTRTYPE(1U)
84877 #define S_ARMMA2AXI0ARTRTYPE    1
84878 #define V_ARMMA2AXI0ARTRTYPE(x) ((x) << S_ARMMA2AXI0ARTRTYPE)
84879 #define F_ARMMA2AXI0ARTRTYPE    V_ARMMA2AXI0ARTRTYPE(1U)
84882 #define V_ARMMA2AXI0AWTRTYPE(x) ((x) << S_ARMMA2AXI0AWTRTYPE)
84883 #define F_ARMMA2AXI0AWTRTYPE    V_ARMMA2AXI0AWTRTYPE(1U)
84889 #define V_T7_VENDORID(x) ((x) << S_T7_VENDORID)
84890 #define G_T7_VENDORID(x) (((x) >> S_T7_VENDORID) & M_T7_VENDORID)
84894 #define V_OBFFCODE(x) ((x) << S_OBFFCODE)
84895 #define G_OBFFCODE(x) (((x) >> S_OBFFCODE) & M_OBFFCODE)
84901 #define V_ARM_CLUSTER_SEL(x) ((x) << S_ARM_CLUSTER_SEL)
84902 #define F_ARM_CLUSTER_SEL    V_ARM_CLUSTER_SEL(1U)
84906 #define S_PWRQ_PERMIT_DENY_SAR    1
84907 #define V_PWRQ_PERMIT_DENY_SAR(x) ((x) << S_PWRQ_PERMIT_DENY_SAR)
84908 #define F_PWRQ_PERMIT_DENY_SAR    V_PWRQ_PERMIT_DENY_SAR(1U)
84911 #define V_PWRQREQNS_ADB(x) ((x) << S_PWRQREQNS_ADB)
84912 #define F_PWRQREQNS_ADB    V_PWRQREQNS_ADB(1U)
84917 #define V_CLKQREQNS_ADB(x) ((x) << S_CLKQREQNS_ADB)
84918 #define F_CLKQREQNS_ADB    V_CLKQREQNS_ADB(1U)
84923 #define V_DFTRSTDISABLEM_ADB(x) ((x) << S_DFTRSTDISABLEM_ADB)
84924 #define F_DFTRSTDISABLEM_ADB    V_DFTRSTDISABLEM_ADB(1U)
84926 #define S_DFTRSTDISABLES_ADB    1
84927 #define V_DFTRSTDISABLES_ADB(x) ((x) << S_DFTRSTDISABLES_ADB)
84928 #define F_DFTRSTDISABLES_ADB    V_DFTRSTDISABLES_ADB(1U)
84931 #define V_WAKEUPM_I_ADB(x) ((x) << S_WAKEUPM_I_ADB)
84932 #define F_WAKEUPM_I_ADB    V_WAKEUPM_I_ADB(1U)
84937 #define V_CC_DFTSCANMODE(x) ((x) << S_CC_DFTSCANMODE)
84938 #define F_CC_DFTSCANMODE    V_CC_DFTSCANMODE(1U)
84941 #define V_CC_OTP_FILTERING_DISABLE(x) ((x) << S_CC_OTP_FILTERING_DISABLE)
84942 #define F_CC_OTP_FILTERING_DISABLE    V_CC_OTP_FILTERING_DISABLE(1U)
84946 #define V_CC_APB_FILTERING(x) ((x) << S_CC_APB_FILTERING)
84947 #define G_CC_APB_FILTERING(x) (((x) >> S_CC_APB_FILTERING) & M_CC_APB_FILTERING)
84960 #define V_CC_SEC_DEBUG_RESET(x) ((x) << S_CC_SEC_DEBUG_RESET)
84961 #define F_CC_SEC_DEBUG_RESET    V_CC_SEC_DEBUG_RESET(1U)
84964 #define V_CC_DFTSE(x) ((x) << S_CC_DFTSE)
84965 #define F_CC_DFTSE    V_CC_DFTSE(1U)
84968 #define V_CC_DFTCGEN(x) ((x) << S_CC_DFTCGEN)
84969 #define F_CC_DFTCGEN    V_CC_DFTCGEN(1U)
84972 #define V_CC_DFTRAMHOLD(x) ((x) << S_CC_DFTRAMHOLD)
84973 #define F_CC_DFTRAMHOLD    V_CC_DFTRAMHOLD(1U)
84977 #define V_CC_LOCK_BITS(x) ((x) << S_CC_LOCK_BITS)
84978 #define G_CC_LOCK_BITS(x) (((x) >> S_CC_LOCK_BITS) & M_CC_LOCK_BITS)
84981 #define V_CC_LCS_IS_VALID(x) ((x) << S_CC_LCS_IS_VALID)
84982 #define F_CC_LCS_IS_VALID    V_CC_LCS_IS_VALID(1U)
84986 #define V_CC_LCS(x) ((x) << S_CC_LCS)
84987 #define G_CC_LCS(x) (((x) >> S_CC_LCS) & M_CC_LCS)
84991 #define V_CC_GPPC(x) ((x) << S_CC_GPPC)
84992 #define G_CC_GPPC(x) (((x) >> S_CC_GPPC) & M_CC_GPPC)
84997 #define V_EMMC_CARD_CLK_EN(x) ((x) << S_EMMC_CARD_CLK_EN)
84998 #define F_EMMC_CARD_CLK_EN    V_EMMC_CARD_CLK_EN(1U)
85001 #define V_EMMC_LED_CONTROL(x) ((x) << S_EMMC_LED_CONTROL)
85002 #define F_EMMC_LED_CONTROL    V_EMMC_LED_CONTROL(1U)
85005 #define V_EMMC_UHS1_SWVOLT_EN(x) ((x) << S_EMMC_UHS1_SWVOLT_EN)
85006 #define F_EMMC_UHS1_SWVOLT_EN    V_EMMC_UHS1_SWVOLT_EN(1U)
85010 #define V_EMMC_UHS1_DRV_STH(x) ((x) << S_EMMC_UHS1_DRV_STH)
85011 #define G_EMMC_UHS1_DRV_STH(x) (((x) >> S_EMMC_UHS1_DRV_STH) & M_EMMC_UHS1_DRV_STH)
85014 #define V_EMMC_SD_VDD1_ON(x) ((x) << S_EMMC_SD_VDD1_ON)
85015 #define F_EMMC_SD_VDD1_ON    V_EMMC_SD_VDD1_ON(1U)
85019 #define V_EMMC_SD_VDD1_SEL(x) ((x) << S_EMMC_SD_VDD1_SEL)
85020 #define G_EMMC_SD_VDD1_SEL(x) (((x) >> S_EMMC_SD_VDD1_SEL) & M_EMMC_SD_VDD1_SEL)
85023 #define V_EMMC_INTCLK_EN(x) ((x) << S_EMMC_INTCLK_EN)
85024 #define F_EMMC_INTCLK_EN    V_EMMC_INTCLK_EN(1U)
85028 #define V_EMMC_CARD_CLK_FREQ_SEL(x) ((x) << S_EMMC_CARD_CLK_FREQ_SEL)
85029 #define G_EMMC_CARD_CLK_FREQ_SEL(x) (((x) >> S_EMMC_CARD_CLK_FREQ_SEL) & M_EMMC_CARD_CLK_FREQ_SEL)
85032 #define V_EMMC_CARD_CLK_GEN_SEL(x) ((x) << S_EMMC_CARD_CLK_GEN_SEL)
85033 #define F_EMMC_CARD_CLK_GEN_SEL    V_EMMC_CARD_CLK_GEN_SEL(1U)
85036 #define V_EMMC_CLK2CARD_ON(x) ((x) << S_EMMC_CLK2CARD_ON)
85037 #define F_EMMC_CLK2CARD_ON    V_EMMC_CLK2CARD_ON(1U)
85040 #define V_EMMC_CARD_CLK_STABLE(x) ((x) << S_EMMC_CARD_CLK_STABLE)
85041 #define F_EMMC_CARD_CLK_STABLE    V_EMMC_CARD_CLK_STABLE(1U)
85044 #define V_EMMC_INT_BCLK_STABLE(x) ((x) << S_EMMC_INT_BCLK_STABLE)
85045 #define F_EMMC_INT_BCLK_STABLE    V_EMMC_INT_BCLK_STABLE(1U)
85048 #define V_EMMC_INT_ACLK_STABLE(x) ((x) << S_EMMC_INT_ACLK_STABLE)
85049 #define F_EMMC_INT_ACLK_STABLE    V_EMMC_INT_ACLK_STABLE(1U)
85052 #define V_EMMC_INT_TMCLK_STABLE(x) ((x) << S_EMMC_INT_TMCLK_STABLE)
85053 #define F_EMMC_INT_TMCLK_STABLE    V_EMMC_INT_TMCLK_STABLE(1U)
85056 #define V_EMMC_HOST_REG_VOL_STABLE(x) ((x) << S_EMMC_HOST_REG_VOL_STABLE)
85057 #define F_EMMC_HOST_REG_VOL_STABLE    V_EMMC_HOST_REG_VOL_STABLE(1U)
85060 #define V_EMMC_CARD_DETECT_N(x) ((x) << S_EMMC_CARD_DETECT_N)
85061 #define F_EMMC_CARD_DETECT_N    V_EMMC_CARD_DETECT_N(1U)
85064 #define V_EMMC_CARD_WRITE_PROT(x) ((x) << S_EMMC_CARD_WRITE_PROT)
85065 #define F_EMMC_CARD_WRITE_PROT    V_EMMC_CARD_WRITE_PROT(1U)
85068 #define V_EMMC_GP_IN(x) ((x) << S_EMMC_GP_IN)
85069 #define F_EMMC_GP_IN    V_EMMC_GP_IN(1U)
85071 #define S_EMMC_TEST_SCAN_MODE    1
85072 #define V_EMMC_TEST_SCAN_MODE(x) ((x) << S_EMMC_TEST_SCAN_MODE)
85073 #define F_EMMC_TEST_SCAN_MODE    V_EMMC_TEST_SCAN_MODE(1U)
85076 #define V_EMMC_FIFOINJDATAERR(x) ((x) << S_EMMC_FIFOINJDATAERR)
85077 #define F_EMMC_FIFOINJDATAERR    V_EMMC_FIFOINJDATAERR(1U)
85082 #define V_WAKEUPS_I_ADB(x) ((x) << S_WAKEUPS_I_ADB)
85083 #define F_WAKEUPS_I_ADB    V_WAKEUPS_I_ADB(1U)
85088 #define V_CLKQREQNM_ADB(x) ((x) << S_CLKQREQNM_ADB)
85089 #define F_CLKQREQNM_ADB    V_CLKQREQNM_ADB(1U)
85098 #define V_TCAM_WRITE_DATA(x) ((x) << S_TCAM_WRITE_DATA)
85099 #define G_TCAM_WRITE_DATA(x) (((x) >> S_TCAM_WRITE_DATA) & M_TCAM_WRITE_DATA)
85105 #define V_TCAM_WRITE_ADDR(x) ((x) << S_TCAM_WRITE_ADDR)
85106 #define G_TCAM_WRITE_ADDR(x) (((x) >> S_TCAM_WRITE_ADDR) & M_TCAM_WRITE_ADDR)
85112 #define V_TCAM_READ_ADDR(x) ((x) << S_TCAM_READ_ADDR)
85113 #define G_TCAM_READ_ADDR(x) (((x) >> S_TCAM_READ_ADDR) & M_TCAM_READ_ADDR)
85118 #define V_TCAMCBBUSY(x) ((x) << S_TCAMCBBUSY)
85119 #define F_TCAMCBBUSY    V_TCAMCBBUSY(1U)
85122 #define V_TCAMCBPASS(x) ((x) << S_TCAMCBPASS)
85123 #define F_TCAMCBPASS    V_TCAMCBPASS(1U)
85126 #define V_TCAMCBSTART(x) ((x) << S_TCAMCBSTART)
85127 #define F_TCAMCBSTART    V_TCAMCBSTART(1U)
85130 #define V_TCAMRSTCB(x) ((x) << S_TCAMRSTCB)
85131 #define F_TCAMRSTCB    V_TCAMRSTCB(1U)
85134 #define V_TCAM_REQBITPOS(x) ((x) << S_TCAM_REQBITPOS)
85135 #define F_TCAM_REQBITPOS    V_TCAM_REQBITPOS(1U)
85137 #define S_TCAM_WRITE    1
85138 #define V_TCAM_WRITE(x) ((x) << S_TCAM_WRITE)
85139 #define F_TCAM_WRITE    V_TCAM_WRITE(1U)
85142 #define V_TCAM_ENABLE(x) ((x) << S_TCAM_ENABLE)
85143 #define F_TCAM_ENABLE    V_TCAM_ENABLE(1U)
85149 #define V_TCAM_READ_DATA(x) ((x) << S_TCAM_READ_DATA)
85150 #define G_TCAM_READ_DATA(x) (((x) >> S_TCAM_READ_DATA) & M_TCAM_READ_DATA)
85156 #define V_SRAM1_WRITE_DATA(x) ((x) << S_SRAM1_WRITE_DATA)
85157 #define G_SRAM1_WRITE_DATA(x) (((x) >> S_SRAM1_WRITE_DATA) & M_SRAM1_WRITE_DATA)
85163 #define V_SRAM1_WRITE_ADDR(x) ((x) << S_SRAM1_WRITE_ADDR)
85164 #define G_SRAM1_WRITE_ADDR(x) (((x) >> S_SRAM1_WRITE_ADDR) & M_SRAM1_WRITE_ADDR)
85170 #define V_SRAM1_READ_ADDR(x) ((x) << S_SRAM1_READ_ADDR)
85171 #define G_SRAM1_READ_ADDR(x) (((x) >> S_SRAM1_READ_ADDR) & M_SRAM1_READ_ADDR)
85175 #define S_SRAM1_WRITE    1
85176 #define V_SRAM1_WRITE(x) ((x) << S_SRAM1_WRITE)
85177 #define F_SRAM1_WRITE    V_SRAM1_WRITE(1U)
85180 #define V_SRAM1_ENABLE(x) ((x) << S_SRAM1_ENABLE)
85181 #define F_SRAM1_ENABLE    V_SRAM1_ENABLE(1U)
85187 #define V_SRAM1_READ_DATA(x) ((x) << S_SRAM1_READ_DATA)
85188 #define G_SRAM1_READ_DATA(x) (((x) >> S_SRAM1_READ_DATA) & M_SRAM1_READ_DATA)
85197 #define V_SRAM2_WRITE_ADDR(x) ((x) << S_SRAM2_WRITE_ADDR)
85198 #define G_SRAM2_WRITE_ADDR(x) (((x) >> S_SRAM2_WRITE_ADDR) & M_SRAM2_WRITE_ADDR)
85204 #define V_SRAM2_READ_ADDR(x) ((x) << S_SRAM2_READ_ADDR)
85205 #define G_SRAM2_READ_ADDR(x) (((x) >> S_SRAM2_READ_ADDR) & M_SRAM2_READ_ADDR)
85209 #define S_SRAM2_WRITE    1
85210 #define V_SRAM2_WRITE(x) ((x) << S_SRAM2_WRITE)
85211 #define F_SRAM2_WRITE    V_SRAM2_WRITE(1U)
85214 #define V_SRAM2_ENABLE(x) ((x) << S_SRAM2_ENABLE)
85215 #define F_SRAM2_ENABLE    V_SRAM2_ENABLE(1U)
85223 #define V_DBPROC_RD_EN(x) ((x) << S_DBPROC_RD_EN)
85224 #define F_DBPROC_RD_EN    V_DBPROC_RD_EN(1U)
85230 #define V_DBPROC_RD_ADDR(x) ((x) << S_DBPROC_RD_ADDR)
85231 #define G_DBPROC_RD_ADDR(x) (((x) >> S_DBPROC_RD_ADDR) & M_DBPROC_RD_ADDR)
85242 #define V_SPIDEN(x) ((x) << S_SPIDEN)
85243 #define F_SPIDEN    V_SPIDEN(1U)
85249 #define V_RC_INT_STATUS_WRITE_DATA(x) ((x) << S_RC_INT_STATUS_WRITE_DATA)
85250 #define G_RC_INT_STATUS_WRITE_DATA(x) (((x) >> S_RC_INT_STATUS_WRITE_DATA) & M_RC_INT_STATUS_WRITE_DATA)
85255 #define V_MBISTREQ(x) ((x) << S_MBISTREQ)
85256 #define F_MBISTREQ    V_MBISTREQ(1U)
85259 #define V_MBISTRESETN(x) ((x) << S_MBISTRESETN)
85260 #define F_MBISTRESETN    V_MBISTRESETN(1U)
85262 #define S_DFTRAMHOLD    1
85263 #define V_DFTRAMHOLD(x) ((x) << S_DFTRAMHOLD)
85264 #define F_DFTRAMHOLD    V_DFTRAMHOLD(1U)
85267 #define V_DFTCGEN(x) ((x) << S_DFTCGEN)
85268 #define F_DFTCGEN    V_DFTCGEN(1U)
85272 #define S_DBPROC_TH_WR_EN    1
85273 #define V_DBPROC_TH_WR_EN(x) ((x) << S_DBPROC_TH_WR_EN)
85274 #define F_DBPROC_TH_WR_EN    V_DBPROC_TH_WR_EN(1U)
85277 #define V_DBPROC_TH_RD_EN(x) ((x) << S_DBPROC_TH_RD_EN)
85278 #define F_DBPROC_TH_RD_EN    V_DBPROC_TH_RD_EN(1U)
85283 #define V_MBISTACK(x) ((x) << S_MBISTACK)
85284 #define F_MBISTACK    V_MBISTACK(1U)
85290 #define V_MBISTADDR(x) ((x) << S_MBISTADDR)
85291 #define G_MBISTADDR(x) (((x) >> S_MBISTADDR) & M_MBISTADDR)
85296 #define V_MBISTREADEN(x) ((x) << S_MBISTREADEN)
85297 #define F_MBISTREADEN    V_MBISTREADEN(1U)
85302 #define V_MBISTWRITEEN(x) ((x) << S_MBISTWRITEEN)
85303 #define F_MBISTWRITEEN    V_MBISTWRITEEN(1U)
85309 #define V_MBISTARRAY(x) ((x) << S_MBISTARRAY)
85310 #define G_MBISTARRAY(x) (((x) >> S_MBISTARRAY) & M_MBISTARRAY)
85315 #define V_MBISTCFG(x) ((x) << S_MBISTCFG)
85316 #define F_MBISTCFG    V_MBISTCFG(1U)
85325 #define V_NVME_DB_EN(x) ((x) << S_NVME_DB_EN)
85326 #define F_NVME_DB_EN    V_NVME_DB_EN(1U)
85335 #define V_T7_AUTOINCR(x) ((x) << S_T7_AUTOINCR)
85336 #define G_T7_AUTOINCR(x) (((x) >> S_T7_AUTOINCR) & M_T7_AUTOINCR)
85340 #define V_IND_ADDR_ADDR(x) ((x) << S_IND_ADDR_ADDR)
85341 #define G_IND_ADDR_ADDR(x) (((x) >> S_IND_ADDR_ADDR) & M_IND_ADDR_ADDR)
85352 #define V_BISTECCHBWCTL(x) ((x) << S_BISTECCHBWCTL)
85353 #define G_BISTECCHBWCTL(x) (((x) >> S_BISTECCHBWCTL) & M_BISTECCHBWCTL)
85356 #define V_BISTTESTMODE(x) ((x) << S_BISTTESTMODE)
85357 #define F_BISTTESTMODE    V_BISTTESTMODE(1U)
85361 #define V_RMW_CTL_CFG(x) ((x) << S_RMW_CTL_CFG)
85362 #define G_RMW_CTL_CFG(x) (((x) >> S_RMW_CTL_CFG) & M_RMW_CTL_CFG)
85367 #define V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE)
85368 #define F_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_DCH1_ENABLE(1U)
85371 #define V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_DCH1_ENABLE)
85372 #define F_HIF_RDATA_CRC_ERR_DCH1_ENABLE    V_HIF_RDATA_CRC_ERR_DCH1_ENABLE(1U)
85375 #define V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_DCH1_ENABLE)
85376 #define F_HIF_RDATA_ADDR_ERR_DCH1_ENABLE    V_HIF_RDATA_ADDR_ERR_DCH1_ENABLE(1U)
85379 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE)
85380 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_ENABLE(1U)
85382 #define S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    1
85383 #define V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE)
85384 #define F_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_ENABLE(1U)
85387 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE)
85388 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE(1U)
85393 #define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85394 #define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85397 #define V_WR_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH1_CAUSE)
85398 #define F_WR_CRC_ERR_INTR_DCH1_CAUSE    V_WR_CRC_ERR_INTR_DCH1_CAUSE(1U)
85401 #define V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85402 #define F_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85405 #define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE)
85406 #define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH1_CAUSE(1U)
85409 #define V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE)
85410 #define F_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH1_CAUSE(1U)
85413 #define V_SWCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH1_CAUSE)
85414 #define F_SWCMD_ERR_INTR_DCH1_CAUSE    V_SWCMD_ERR_INTR_DCH1_CAUSE(1U)
85417 #define V_DUCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH1_CAUSE)
85418 #define F_DUCMD_ERR_INTR_DCH1_CAUSE    V_DUCMD_ERR_INTR_DCH1_CAUSE(1U)
85421 #define V_LCCMD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH1_CAUSE)
85422 #define F_LCCMD_ERR_INTR_DCH1_CAUSE    V_LCCMD_ERR_INTR_DCH1_CAUSE(1U)
85425 #define V_CTRLUPD_ERR_INTR_DCH1_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH1_CAUSE)
85426 #define F_CTRLUPD_ERR_INTR_DCH1_CAUSE    V_CTRLUPD_ERR_INTR_DCH1_CAUSE(1U)
85429 #define V_RFM_ALERT_INTR_DCH1_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH1_CAUSE)
85430 #define F_RFM_ALERT_INTR_DCH1_CAUSE    V_RFM_ALERT_INTR_DCH1_CAUSE(1U)
85433 #define V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85434 #define F_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_WR_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85437 #define V_WR_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_WR_CRC_ERR_INTR_DCH0_CAUSE)
85438 #define F_WR_CRC_ERR_INTR_DCH0_CAUSE    V_WR_CRC_ERR_INTR_DCH0_CAUSE(1U)
85441 #define V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85442 #define F_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_CAPAR_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85445 #define V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(x) ((x) << S_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE)
85446 #define F_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE    V_RD_CRC_ERR_MAX_REACHED_INTR_DCH0_CAUSE(1U)
85449 #define V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(x) ((x) << S_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE)
85450 #define F_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE    V_DERATE_TEMP_LIMIT_INTR_DCH0_CAUSE(1U)
85453 #define V_SWCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_SWCMD_ERR_INTR_DCH0_CAUSE)
85454 #define F_SWCMD_ERR_INTR_DCH0_CAUSE    V_SWCMD_ERR_INTR_DCH0_CAUSE(1U)
85457 #define V_DUCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_DUCMD_ERR_INTR_DCH0_CAUSE)
85458 #define F_DUCMD_ERR_INTR_DCH0_CAUSE    V_DUCMD_ERR_INTR_DCH0_CAUSE(1U)
85461 #define V_LCCMD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_LCCMD_ERR_INTR_DCH0_CAUSE)
85462 #define F_LCCMD_ERR_INTR_DCH0_CAUSE    V_LCCMD_ERR_INTR_DCH0_CAUSE(1U)
85465 #define V_CTRLUPD_ERR_INTR_DCH0_CAUSE(x) ((x) << S_CTRLUPD_ERR_INTR_DCH0_CAUSE)
85466 #define F_CTRLUPD_ERR_INTR_DCH0_CAUSE    V_CTRLUPD_ERR_INTR_DCH0_CAUSE(1U)
85469 #define V_RFM_ALERT_INTR_DCH0_CAUSE(x) ((x) << S_RFM_ALERT_INTR_DCH0_CAUSE)
85470 #define F_RFM_ALERT_INTR_DCH0_CAUSE    V_RFM_ALERT_INTR_DCH0_CAUSE(1U)
85473 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE)
85474 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH1_CAUSE(1U)
85477 #define V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE)
85478 #define F_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH1_CAUSE(1U)
85481 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE)
85482 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH1_CAUSE(1U)
85485 #define V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE)
85486 #define F_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_WDATA_PTR_ADDR_ERR_INTR_DCH0_CAUSE(1U)
85488 #define S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    1
85489 #define V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE)
85490 #define F_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_CRC_ERR_INTR_DCH0_CAUSE(1U)
85493 #define V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(x) ((x) << S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE)
85494 #define F_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    V_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE(1U)
85499 #define V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_ENABLE)
85500 #define F_HIF_WDATA_Q_PARERR_DCH1_ENABLE    V_HIF_WDATA_Q_PARERR_DCH1_ENABLE(1U)
85503 #define V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_ENABLE)
85504 #define F_DDRCTL_ECC_CE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH1_ENABLE(1U)
85507 #define V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_ENABLE)
85508 #define F_DDRCTL_ECC_CE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_CE_PAR_DCH0_ENABLE(1U)
85511 #define V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_ENABLE)
85512 #define F_DDRCTL_ECC_UE_PAR_DCH1_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH1_ENABLE(1U)
85515 #define V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_ENABLE)
85516 #define F_DDRCTL_ECC_UE_PAR_DCH0_ENABLE    V_DDRCTL_ECC_UE_PAR_DCH0_ENABLE(1U)
85519 #define V_WDATARAM_PARERR_DCH1_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH1_ENABLE)
85520 #define F_WDATARAM_PARERR_DCH1_ENABLE    V_WDATARAM_PARERR_DCH1_ENABLE(1U)
85523 #define V_WDATARAM_PARERR_DCH0_ENABLE(x) ((x) << S_WDATARAM_PARERR_DCH0_ENABLE)
85524 #define F_WDATARAM_PARERR_DCH0_ENABLE    V_WDATARAM_PARERR_DCH0_ENABLE(1U)
85527 #define V_BIST_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_ENABLE)
85528 #define F_BIST_ADDR_FIFO_PARERR_ENABLE    V_BIST_ADDR_FIFO_PARERR_ENABLE(1U)
85531 #define V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_ENABLE)
85532 #define F_BIST_ERR_ADDR_FIFO_PARERR_ENABLE    V_BIST_ERR_ADDR_FIFO_PARERR_ENABLE(1U)
85535 #define V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_ENABLE)
85536 #define F_HIF_WDATA_Q_PARERR_DCH0_ENABLE    V_HIF_WDATA_Q_PARERR_DCH0_ENABLE(1U)
85539 #define V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE)
85540 #define F_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH1_ENABLE(1U)
85543 #define V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE)
85544 #define F_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE    V_HIF_RSPDATA_Q_PARERR_DCH0_ENABLE(1U)
85546 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    1
85547 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE)
85548 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_ENABLE(1U)
85551 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE)
85552 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE(1U)
85557 #define V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH1_CAUSE)
85558 #define F_HIF_WDATA_Q_PARERR_DCH1_CAUSE    V_HIF_WDATA_Q_PARERR_DCH1_CAUSE(1U)
85561 #define V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH1_CAUSE)
85562 #define F_DDRCTL_ECC_CE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH1_CAUSE(1U)
85565 #define V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_CE_PAR_DCH0_CAUSE)
85566 #define F_DDRCTL_ECC_CE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_CE_PAR_DCH0_CAUSE(1U)
85569 #define V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH1_CAUSE)
85570 #define F_DDRCTL_ECC_UE_PAR_DCH1_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH1_CAUSE(1U)
85573 #define V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(x) ((x) << S_DDRCTL_ECC_UE_PAR_DCH0_CAUSE)
85574 #define F_DDRCTL_ECC_UE_PAR_DCH0_CAUSE    V_DDRCTL_ECC_UE_PAR_DCH0_CAUSE(1U)
85577 #define V_WDATARAM_PARERR_DCH1_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH1_CAUSE)
85578 #define F_WDATARAM_PARERR_DCH1_CAUSE    V_WDATARAM_PARERR_DCH1_CAUSE(1U)
85581 #define V_WDATARAM_PARERR_DCH0_CAUSE(x) ((x) << S_WDATARAM_PARERR_DCH0_CAUSE)
85582 #define F_WDATARAM_PARERR_DCH0_CAUSE    V_WDATARAM_PARERR_DCH0_CAUSE(1U)
85585 #define V_BIST_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ADDR_FIFO_PARERR_CAUSE)
85586 #define F_BIST_ADDR_FIFO_PARERR_CAUSE    V_BIST_ADDR_FIFO_PARERR_CAUSE(1U)
85589 #define V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(x) ((x) << S_BIST_ERR_ADDR_FIFO_PARERR_CAUSE)
85590 #define F_BIST_ERR_ADDR_FIFO_PARERR_CAUSE    V_BIST_ERR_ADDR_FIFO_PARERR_CAUSE(1U)
85593 #define V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_Q_PARERR_DCH0_CAUSE)
85594 #define F_HIF_WDATA_Q_PARERR_DCH0_CAUSE    V_HIF_WDATA_Q_PARERR_DCH0_CAUSE(1U)
85597 #define V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE)
85598 #define F_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH1_CAUSE(1U)
85601 #define V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE)
85602 #define F_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE    V_HIF_RSPDATA_Q_PARERR_DCH0_CAUSE(1U)
85604 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    1
85605 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE)
85606 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH1_CAUSE(1U)
85609 #define V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(x) ((x) << S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE)
85610 #define F_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    V_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE(1U)
85615 #define V_DDRPHY_INT_ENABLE(x) ((x) << S_DDRPHY_INT_ENABLE)
85616 #define F_DDRPHY_INT_ENABLE    V_DDRPHY_INT_ENABLE(1U)
85619 #define V_DDRCTL_INT_ENABLE(x) ((x) << S_DDRCTL_INT_ENABLE)
85620 #define F_DDRCTL_INT_ENABLE    V_DDRCTL_INT_ENABLE(1U)
85623 #define V_T7_ECC_CE_INT_ENABLE(x) ((x) << S_T7_ECC_CE_INT_ENABLE)
85624 #define F_T7_ECC_CE_INT_ENABLE    V_T7_ECC_CE_INT_ENABLE(1U)
85626 #define S_T7_ECC_UE_INT_ENABLE    1
85627 #define V_T7_ECC_UE_INT_ENABLE(x) ((x) << S_T7_ECC_UE_INT_ENABLE)
85628 #define F_T7_ECC_UE_INT_ENABLE    V_T7_ECC_UE_INT_ENABLE(1U)
85633 #define V_DDRPHY_INT_CAUSE(x) ((x) << S_DDRPHY_INT_CAUSE)
85634 #define F_DDRPHY_INT_CAUSE    V_DDRPHY_INT_CAUSE(1U)
85637 #define V_DDRCTL_INT_CAUSE(x) ((x) << S_DDRCTL_INT_CAUSE)
85638 #define F_DDRCTL_INT_CAUSE    V_DDRCTL_INT_CAUSE(1U)
85641 #define V_T7_ECC_CE_INT_CAUSE(x) ((x) << S_T7_ECC_CE_INT_CAUSE)
85642 #define F_T7_ECC_CE_INT_CAUSE    V_T7_ECC_CE_INT_CAUSE(1U)
85644 #define S_T7_ECC_UE_INT_CAUSE    1
85645 #define V_T7_ECC_UE_INT_CAUSE(x) ((x) << S_T7_ECC_UE_INT_CAUSE)
85646 #define F_T7_ECC_UE_INT_CAUSE    V_T7_ECC_UE_INT_CAUSE(1U)
85651 #define V_BIST_RSP_SRAM_UERR_ENABLE(x) ((x) << S_BIST_RSP_SRAM_UERR_ENABLE)
85652 #define F_BIST_RSP_SRAM_UERR_ENABLE    V_BIST_RSP_SRAM_UERR_ENABLE(1U)
85657 #define V_BIST_RSP_SRAM_UERR_CAUSE(x) ((x) << S_BIST_RSP_SRAM_UERR_CAUSE)
85658 #define F_BIST_RSP_SRAM_UERR_CAUSE    V_BIST_RSP_SRAM_UERR_CAUSE(1U)
85665 #define V_DFIFREQRATIO(x) ((x) << S_DFIFREQRATIO)
85666 #define F_DFIFREQRATIO    V_DFIFREQRATIO(1U)
85669 #define V_STATIC_DDR5_HBW_CHANNEL(x) ((x) << S_STATIC_DDR5_HBW_CHANNEL)
85670 #define F_STATIC_DDR5_HBW_CHANNEL    V_STATIC_DDR5_HBW_CHANNEL(1U)
85673 #define V_STATIC_DDR5_HBW(x) ((x) << S_STATIC_DDR5_HBW)
85674 #define F_STATIC_DDR5_HBW    V_STATIC_DDR5_HBW(1U)
85676 #define S_T7_STATIC_WIDTH    1
85677 #define V_T7_STATIC_WIDTH(x) ((x) << S_T7_STATIC_WIDTH)
85678 #define F_T7_STATIC_WIDTH    V_T7_STATIC_WIDTH(1U)
85693 #define S_ENABLE_DCH1    1
85694 #define V_ENABLE_DCH1(x) ((x) << S_ENABLE_DCH1)
85695 #define F_ENABLE_DCH1    V_ENABLE_DCH1(1U)
85698 #define V_ENABLE_DCH0(x) ((x) << S_ENABLE_DCH0)
85699 #define F_ENABLE_DCH0    V_ENABLE_DCH0(1U)
85709 #define V_FIFO_ERROR_FLAG(x) ((x) << S_FIFO_ERROR_FLAG)
85710 #define F_FIFO_ERROR_FLAG    V_FIFO_ERROR_FLAG(1U)
85716 #define V_T7_VALUE(x) ((x) << S_T7_VALUE)
85717 #define G_T7_VALUE(x) (((x) >> S_T7_VALUE) & M_T7_VALUE)
85724 #define V_DATA_TYPE(x) ((x) << S_DATA_TYPE)
85725 #define G_DATA_TYPE(x) (((x) >> S_DATA_TYPE) & M_DATA_TYPE)
85733 #define V_ERROR_ADDR(x) ((x) << S_ERROR_ADDR)
85734 #define G_ERROR_ADDR(x) (((x) >> S_ERROR_ADDR) & M_ERROR_ADDR)
85740 #define V_OPT_VPRW_SCH(x) ((x) << S_OPT_VPRW_SCH)
85741 #define F_OPT_VPRW_SCH    V_OPT_VPRW_SCH(1U)
85744 #define V_DIS_SPECULATIVE_ACT(x) ((x) << S_DIS_SPECULATIVE_ACT)
85745 #define F_DIS_SPECULATIVE_ACT    V_DIS_SPECULATIVE_ACT(1U)
85748 #define V_OPT_ACT_LAT(x) ((x) << S_OPT_ACT_LAT)
85749 #define F_OPT_ACT_LAT    V_OPT_ACT_LAT(1U)
85753 #define V_LPR_NUM_ENTRIES(x) ((x) << S_LPR_NUM_ENTRIES)
85754 #define G_LPR_NUM_ENTRIES(x) (((x) >> S_LPR_NUM_ENTRIES) & M_LPR_NUM_ENTRIES)
85757 #define V_AUTOPRE_RMW(x) ((x) << S_AUTOPRE_RMW)
85758 #define F_AUTOPRE_RMW    V_AUTOPRE_RMW(1U)
85761 #define V_DIS_OPT_NTT_BY_PRE(x) ((x) << S_DIS_OPT_NTT_BY_PRE)
85762 #define F_DIS_OPT_NTT_BY_PRE    V_DIS_OPT_NTT_BY_PRE(1U)
85765 #define V_DIS_OPT_NTT_BY_ACT(x) ((x) << S_DIS_OPT_NTT_BY_ACT)
85766 #define F_DIS_OPT_NTT_BY_ACT    V_DIS_OPT_NTT_BY_ACT(1U)
85769 #define V_OPT_WRCAM_FILL_LEVEL(x) ((x) << S_OPT_WRCAM_FILL_LEVEL)
85770 #define F_OPT_WRCAM_FILL_LEVEL    V_OPT_WRCAM_FILL_LEVEL(1U)
85773 #define V_PAGECLOSE(x) ((x) << S_PAGECLOSE)
85774 #define F_PAGECLOSE    V_PAGECLOSE(1U)
85776 #define S_PREFER_WRITE    1
85777 #define V_PREFER_WRITE(x) ((x) << S_PREFER_WRITE)
85778 #define F_PREFER_WRITE    V_PREFER_WRITE(1U)
85783 #define V_DIS_SCRUB(x) ((x) << S_DIS_SCRUB)
85784 #define F_DIS_SCRUB    V_DIS_SCRUB(1U)
85788 #define V_ECC_TYPE(x) ((x) << S_ECC_TYPE)
85789 #define G_ECC_TYPE(x) (((x) >> S_ECC_TYPE) & M_ECC_TYPE)
85792 #define V_TEST_MODE(x) ((x) << S_TEST_MODE)
85793 #define F_TEST_MODE    V_TEST_MODE(1U)
85797 #define V_ECC_MODE(x) ((x) << S_ECC_MODE)
85798 #define G_ECC_MODE(x) (((x) >> S_ECC_MODE) & M_ECC_MODE)
85802 #define S_DATA_POISON_BIT    1
85803 #define V_DATA_POISON_BIT(x) ((x) << S_DATA_POISON_BIT)
85804 #define F_DATA_POISON_BIT    V_DATA_POISON_BIT(1U)
85807 #define V_DATA_POISON_EN(x) ((x) << S_DATA_POISON_EN)
85808 #define F_DATA_POISON_EN    V_DATA_POISON_EN(1U)
85814 #define V_ECC_UNCORRECTED_ERR(x) ((x) << S_ECC_UNCORRECTED_ERR)
85815 #define G_ECC_UNCORRECTED_ERR(x) (((x) >> S_ECC_UNCORRECTED_ERR) & M_ECC_UNCORRECTED_ERR)
85819 #define V_ECC_CORRECTED_ERR(x) ((x) << S_ECC_CORRECTED_ERR)
85820 #define G_ECC_CORRECTED_ERR(x) (((x) >> S_ECC_CORRECTED_ERR) & M_ECC_CORRECTED_ERR)
85824 #define V_ECC_CORRECTED_BIT_NUM(x) ((x) << S_ECC_CORRECTED_BIT_NUM)
85825 #define G_ECC_CORRECTED_BIT_NUM(x) (((x) >> S_ECC_CORRECTED_BIT_NUM) & M_ECC_CORRECTED_BIT_NUM)
85830 #define V_ECC_UNCORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_FORCE)
85831 #define F_ECC_UNCORRECTED_ERR_INTR_FORCE    V_ECC_UNCORRECTED_ERR_INTR_FORCE(1U)
85834 #define V_ECC_CORRECTED_ERR_INTR_FORCE(x) ((x) << S_ECC_CORRECTED_ERR_INTR_FORCE)
85835 #define F_ECC_CORRECTED_ERR_INTR_FORCE    V_ECC_CORRECTED_ERR_INTR_FORCE(1U)
85838 #define V_ECC_UNCORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_UNCORRECTED_ERR_INTR_EN)
85839 #define F_ECC_UNCORRECTED_ERR_INTR_EN    V_ECC_UNCORRECTED_ERR_INTR_EN(1U)
85842 #define V_ECC_CORRECTED_ERR_INTR_EN(x) ((x) << S_ECC_CORRECTED_ERR_INTR_EN)
85843 #define F_ECC_CORRECTED_ERR_INTR_EN    V_ECC_CORRECTED_ERR_INTR_EN(1U)
85846 #define V_ECC_UNCORR_ERR_CNT_CLR(x) ((x) << S_ECC_UNCORR_ERR_CNT_CLR)
85847 #define F_ECC_UNCORR_ERR_CNT_CLR    V_ECC_UNCORR_ERR_CNT_CLR(1U)
85850 #define V_ECC_CORR_ERR_CNT_CLR(x) ((x) << S_ECC_CORR_ERR_CNT_CLR)
85851 #define F_ECC_CORR_ERR_CNT_CLR    V_ECC_CORR_ERR_CNT_CLR(1U)
85853 #define S_ECC_UNCORRECTED_ERR_CLR    1
85854 #define V_ECC_UNCORRECTED_ERR_CLR(x) ((x) << S_ECC_UNCORRECTED_ERR_CLR)
85855 #define F_ECC_UNCORRECTED_ERR_CLR    V_ECC_UNCORRECTED_ERR_CLR(1U)
85858 #define V_ECC_CORRECTED_ERR_CLR(x) ((x) << S_ECC_CORRECTED_ERR_CLR)
85859 #define F_ECC_CORRECTED_ERR_CLR    V_ECC_CORRECTED_ERR_CLR(1U)
85865 #define V_ECC_UNCORR_ERR_CNT(x) ((x) << S_ECC_UNCORR_ERR_CNT)
85866 #define G_ECC_UNCORR_ERR_CNT(x) (((x) >> S_ECC_UNCORR_ERR_CNT) & M_ECC_UNCORR_ERR_CNT)
85870 #define V_ECC_CORR_ERR_CNT(x) ((x) << S_ECC_CORR_ERR_CNT)
85871 #define G_ECC_CORR_ERR_CNT(x) (((x) >> S_ECC_CORR_ERR_CNT) & M_ECC_CORR_ERR_CNT)
85876 #define V_ECC_CORR_RANK(x) ((x) << S_ECC_CORR_RANK)
85877 #define F_ECC_CORR_RANK    V_ECC_CORR_RANK(1U)
85881 #define V_ECC_CORR_ROW(x) ((x) << S_ECC_CORR_ROW)
85882 #define G_ECC_CORR_ROW(x) (((x) >> S_ECC_CORR_ROW) & M_ECC_CORR_ROW)
85888 #define V_ECC_CORR_BG(x) ((x) << S_ECC_CORR_BG)
85889 #define G_ECC_CORR_BG(x) (((x) >> S_ECC_CORR_BG) & M_ECC_CORR_BG)
85893 #define V_ECC_CORR_BANK(x) ((x) << S_ECC_CORR_BANK)
85894 #define G_ECC_CORR_BANK(x) (((x) >> S_ECC_CORR_BANK) & M_ECC_CORR_BANK)
85898 #define V_ECC_CORR_COL(x) ((x) << S_ECC_CORR_COL)
85899 #define G_ECC_CORR_COL(x) (((x) >> S_ECC_CORR_COL) & M_ECC_CORR_COL)
85907 #define V_CB_CORR_SYNDROME(x) ((x) << S_CB_CORR_SYNDROME)
85908 #define G_CB_CORR_SYNDROME(x) (((x) >> S_CB_CORR_SYNDROME) & M_CB_CORR_SYNDROME)
85912 #define V_ECC_CORR_SYNDROMES_71_64(x) ((x) << S_ECC_CORR_SYNDROMES_71_64)
85913 #define G_ECC_CORR_SYNDROMES_71_64(x) (((x) >> S_ECC_CORR_SYNDROMES_71_64) & M_ECC_CORR_SYNDROMES_71_64)
85921 #define V_ECC_CORR_BIT_MASK_71_64(x) ((x) << S_ECC_CORR_BIT_MASK_71_64)
85922 #define G_ECC_CORR_BIT_MASK_71_64(x) (((x) >> S_ECC_CORR_BIT_MASK_71_64) & M_ECC_CORR_BIT_MASK_71_64)
85927 #define V_ECC_UNCORR_RANK(x) ((x) << S_ECC_UNCORR_RANK)
85928 #define F_ECC_UNCORR_RANK    V_ECC_UNCORR_RANK(1U)
85932 #define V_ECC_UNCORR_ROW(x) ((x) << S_ECC_UNCORR_ROW)
85933 #define G_ECC_UNCORR_ROW(x) (((x) >> S_ECC_UNCORR_ROW) & M_ECC_UNCORR_ROW)
85939 #define V_ECC_UNCORR_BG(x) ((x) << S_ECC_UNCORR_BG)
85940 #define G_ECC_UNCORR_BG(x) (((x) >> S_ECC_UNCORR_BG) & M_ECC_UNCORR_BG)
85944 #define V_ECC_UNCORR_BANK(x) ((x) << S_ECC_UNCORR_BANK)
85945 #define G_ECC_UNCORR_BANK(x) (((x) >> S_ECC_UNCORR_BANK) & M_ECC_UNCORR_BANK)
85949 #define V_ECC_UNCORR_COL(x) ((x) << S_ECC_UNCORR_COL)
85950 #define G_ECC_UNCORR_COL(x) (((x) >> S_ECC_UNCORR_COL) & M_ECC_UNCORR_COL)
85958 #define V_CB_UNCORR_SYNDROME(x) ((x) << S_CB_UNCORR_SYNDROME)
85959 #define G_CB_UNCORR_SYNDROME(x) (((x) >> S_CB_UNCORR_SYNDROME) & M_CB_UNCORR_SYNDROME)
85963 #define V_ECC_UNCORR_SYNDROMES_71_64(x) ((x) << S_ECC_UNCORR_SYNDROMES_71_64)
85964 #define G_ECC_UNCORR_SYNDROMES_71_64(x) (((x) >> S_ECC_UNCORR_SYNDROMES_71_64) & M_ECC_UNCORR_SYNDROMES_71_64)
85969 #define V_ECC_POISON_RANK(x) ((x) << S_ECC_POISON_RANK)
85970 #define F_ECC_POISON_RANK    V_ECC_POISON_RANK(1U)
85974 #define V_ECC_POISON_COL(x) ((x) << S_ECC_POISON_COL)
85975 #define G_ECC_POISON_COL(x) (((x) >> S_ECC_POISON_COL) & M_ECC_POISON_COL)
85981 #define V_ECC_POISON_BG(x) ((x) << S_ECC_POISON_BG)
85982 #define G_ECC_POISON_BG(x) (((x) >> S_ECC_POISON_BG) & M_ECC_POISON_BG)
85986 #define V_ECC_POISON_BANK(x) ((x) << S_ECC_POISON_BANK)
85987 #define G_ECC_POISON_BANK(x) (((x) >> S_ECC_POISON_BANK) & M_ECC_POISON_BANK)
85991 #define V_ECC_POISON_ROW(x) ((x) << S_ECC_POISON_ROW)
85992 #define G_ECC_POISON_ROW(x) (((x) >> S_ECC_POISON_ROW) & M_ECC_POISON_ROW)
86000 #define V_ECC_POISON_DATA_71_64(x) ((x) << S_ECC_POISON_DATA_71_64)
86001 #define G_ECC_POISON_DATA_71_64(x) (((x) >> S_ECC_POISON_DATA_71_64) & M_ECC_POISON_DATA_71_64)
86007 #define V_FLIP_BIT_POS1(x) ((x) << S_FLIP_BIT_POS1)
86008 #define G_FLIP_BIT_POS1(x) (((x) >> S_FLIP_BIT_POS1) & M_FLIP_BIT_POS1)
86012 #define V_FLIP_BIT_POS0(x) ((x) << S_FLIP_BIT_POS0)
86013 #define G_FLIP_BIT_POS0(x) (((x) >> S_FLIP_BIT_POS0) & M_FLIP_BIT_POS0)
86033 #define V_PHYSTICKYUNLOCKEN(x) ((x) << S_PHYSTICKYUNLOCKEN)
86034 #define F_PHYSTICKYUNLOCKEN    V_PHYSTICKYUNLOCKEN(1U)
86037 #define V_PHYBSIEN(x) ((x) << S_PHYBSIEN)
86038 #define F_PHYBSIEN    V_PHYBSIEN(1U)
86041 #define V_PHYANIBRCVERREN(x) ((x) << S_PHYANIBRCVERREN)
86042 #define F_PHYANIBRCVERREN    V_PHYANIBRCVERREN(1U)
86045 #define V_PHYD5ACSM1PARITYEN(x) ((x) << S_PHYD5ACSM1PARITYEN)
86046 #define F_PHYD5ACSM1PARITYEN    V_PHYD5ACSM1PARITYEN(1U)
86049 #define V_PHYD5ACSM0PARITYEN(x) ((x) << S_PHYD5ACSM0PARITYEN)
86050 #define F_PHYD5ACSM0PARITYEN    V_PHYD5ACSM0PARITYEN(1U)
86053 #define V_PHYRXFIFOCHECKEN(x) ((x) << S_PHYRXFIFOCHECKEN)
86054 #define F_PHYRXFIFOCHECKEN    V_PHYRXFIFOCHECKEN(1U)
86057 #define V_PHYTXPPTEN(x) ((x) << S_PHYTXPPTEN)
86058 #define F_PHYTXPPTEN    V_PHYTXPPTEN(1U)
86061 #define V_PHYECCEN(x) ((x) << S_PHYECCEN)
86062 #define F_PHYECCEN    V_PHYECCEN(1U)
86066 #define V_PHYFWRESERVEDEN(x) ((x) << S_PHYFWRESERVEDEN)
86067 #define G_PHYFWRESERVEDEN(x) (((x) >> S_PHYFWRESERVEDEN) & M_PHYFWRESERVEDEN)
86070 #define V_PHYTRNGFAILEN(x) ((x) << S_PHYTRNGFAILEN)
86071 #define F_PHYTRNGFAILEN    V_PHYTRNGFAILEN(1U)
86073 #define S_PHYINITCMPLTEN    1
86074 #define V_PHYINITCMPLTEN(x) ((x) << S_PHYINITCMPLTEN)
86075 #define F_PHYINITCMPLTEN    V_PHYINITCMPLTEN(1U)
86078 #define V_PHYTRNGCMPLTEN(x) ((x) << S_PHYTRNGCMPLTEN)
86079 #define F_PHYTRNGCMPLTEN    V_PHYTRNGCMPLTEN(1U)
86085 #define V_PHYFWRESERVEDFW(x) ((x) << S_PHYFWRESERVEDFW)
86086 #define G_PHYFWRESERVEDFW(x) (((x) >> S_PHYFWRESERVEDFW) & M_PHYFWRESERVEDFW)
86089 #define V_PHYTRNGFAILFW(x) ((x) << S_PHYTRNGFAILFW)
86090 #define F_PHYTRNGFAILFW    V_PHYTRNGFAILFW(1U)
86092 #define S_PHYINITCMPLTFW    1
86093 #define V_PHYINITCMPLTFW(x) ((x) << S_PHYINITCMPLTFW)
86094 #define F_PHYINITCMPLTFW    V_PHYINITCMPLTFW(1U)
86097 #define V_PHYTRNGCMPLTFW(x) ((x) << S_PHYTRNGCMPLTFW)
86098 #define F_PHYTRNGCMPLTFW    V_PHYTRNGCMPLTFW(1U)
86103 #define V_PHYSTICKYUNLOCKMSK(x) ((x) << S_PHYSTICKYUNLOCKMSK)
86104 #define F_PHYSTICKYUNLOCKMSK    V_PHYSTICKYUNLOCKMSK(1U)
86107 #define V_PHYBSIMSK(x) ((x) << S_PHYBSIMSK)
86108 #define F_PHYBSIMSK    V_PHYBSIMSK(1U)
86111 #define V_PHYANIBRCVERRMSK(x) ((x) << S_PHYANIBRCVERRMSK)
86112 #define F_PHYANIBRCVERRMSK    V_PHYANIBRCVERRMSK(1U)
86115 #define V_PHYD5ACSM1PARITYMSK(x) ((x) << S_PHYD5ACSM1PARITYMSK)
86116 #define F_PHYD5ACSM1PARITYMSK    V_PHYD5ACSM1PARITYMSK(1U)
86119 #define V_PHYD5ACSM0PARITYMSK(x) ((x) << S_PHYD5ACSM0PARITYMSK)
86120 #define F_PHYD5ACSM0PARITYMSK    V_PHYD5ACSM0PARITYMSK(1U)
86123 #define V_PHYRXFIFOCHECKMSK(x) ((x) << S_PHYRXFIFOCHECKMSK)
86124 #define F_PHYRXFIFOCHECKMSK    V_PHYRXFIFOCHECKMSK(1U)
86127 #define V_PHYTXPPTMSK(x) ((x) << S_PHYTXPPTMSK)
86128 #define F_PHYTXPPTMSK    V_PHYTXPPTMSK(1U)
86131 #define V_PHYECCMSK(x) ((x) << S_PHYECCMSK)
86132 #define F_PHYECCMSK    V_PHYECCMSK(1U)
86136 #define V_PHYFWRESERVEDMSK(x) ((x) << S_PHYFWRESERVEDMSK)
86137 #define G_PHYFWRESERVEDMSK(x) (((x) >> S_PHYFWRESERVEDMSK) & M_PHYFWRESERVEDMSK)
86140 #define V_PHYTRNGFAILMSK(x) ((x) << S_PHYTRNGFAILMSK)
86141 #define F_PHYTRNGFAILMSK    V_PHYTRNGFAILMSK(1U)
86143 #define S_PHYINITCMPLTMSK    1
86144 #define V_PHYINITCMPLTMSK(x) ((x) << S_PHYINITCMPLTMSK)
86145 #define F_PHYINITCMPLTMSK    V_PHYINITCMPLTMSK(1U)
86148 #define V_PHYTRNGCMPLTMSK(x) ((x) << S_PHYTRNGCMPLTMSK)
86149 #define F_PHYTRNGCMPLTMSK    V_PHYTRNGCMPLTMSK(1U)
86154 #define V_PHYSTICKYUNLOCKCLR(x) ((x) << S_PHYSTICKYUNLOCKCLR)
86155 #define F_PHYSTICKYUNLOCKCLR    V_PHYSTICKYUNLOCKCLR(1U)
86158 #define V_PHYBSICLR(x) ((x) << S_PHYBSICLR)
86159 #define F_PHYBSICLR    V_PHYBSICLR(1U)
86162 #define V_PHYANIBRCVERRCLR(x) ((x) << S_PHYANIBRCVERRCLR)
86163 #define F_PHYANIBRCVERRCLR    V_PHYANIBRCVERRCLR(1U)
86166 #define V_PHYD5ACSM1PARITYCLR(x) ((x) << S_PHYD5ACSM1PARITYCLR)
86167 #define F_PHYD5ACSM1PARITYCLR    V_PHYD5ACSM1PARITYCLR(1U)
86170 #define V_PHYD5ACSM0PARITYCLR(x) ((x) << S_PHYD5ACSM0PARITYCLR)
86171 #define F_PHYD5ACSM0PARITYCLR    V_PHYD5ACSM0PARITYCLR(1U)
86174 #define V_PHYRXFIFOCHECKCLR(x) ((x) << S_PHYRXFIFOCHECKCLR)
86175 #define F_PHYRXFIFOCHECKCLR    V_PHYRXFIFOCHECKCLR(1U)
86178 #define V_PHYTXPPTCLR(x) ((x) << S_PHYTXPPTCLR)
86179 #define F_PHYTXPPTCLR    V_PHYTXPPTCLR(1U)
86182 #define V_PHYECCCLR(x) ((x) << S_PHYECCCLR)
86183 #define F_PHYECCCLR    V_PHYECCCLR(1U)
86187 #define V_PHYFWRESERVEDCLR(x) ((x) << S_PHYFWRESERVEDCLR)
86188 #define G_PHYFWRESERVEDCLR(x) (((x) >> S_PHYFWRESERVEDCLR) & M_PHYFWRESERVEDCLR)
86191 #define V_PHYTRNGFAILCLR(x) ((x) << S_PHYTRNGFAILCLR)
86192 #define F_PHYTRNGFAILCLR    V_PHYTRNGFAILCLR(1U)
86194 #define S_PHYINITCMPLTCLR    1
86195 #define V_PHYINITCMPLTCLR(x) ((x) << S_PHYINITCMPLTCLR)
86196 #define F_PHYINITCMPLTCLR    V_PHYINITCMPLTCLR(1U)
86199 #define V_PHYTRNGCMPLTCLR(x) ((x) << S_PHYTRNGCMPLTCLR)
86200 #define F_PHYTRNGCMPLTCLR    V_PHYTRNGCMPLTCLR(1U)
86205 #define V_PHYSTICKYUNLOCKERR(x) ((x) << S_PHYSTICKYUNLOCKERR)
86206 #define F_PHYSTICKYUNLOCKERR    V_PHYSTICKYUNLOCKERR(1U)
86209 #define V_PHYBSIINT(x) ((x) << S_PHYBSIINT)
86210 #define F_PHYBSIINT    V_PHYBSIINT(1U)
86213 #define V_PHYANIBRCVERR(x) ((x) << S_PHYANIBRCVERR)
86214 #define F_PHYANIBRCVERR    V_PHYANIBRCVERR(1U)
86217 #define V_PHYD5ACSM1PARITYERR(x) ((x) << S_PHYD5ACSM1PARITYERR)
86218 #define F_PHYD5ACSM1PARITYERR    V_PHYD5ACSM1PARITYERR(1U)
86221 #define V_PHYD5ACSM0PARITYERR(x) ((x) << S_PHYD5ACSM0PARITYERR)
86222 #define F_PHYD5ACSM0PARITYERR    V_PHYD5ACSM0PARITYERR(1U)
86225 #define V_PHYRXFIFOCHECKERR(x) ((x) << S_PHYRXFIFOCHECKERR)
86226 #define F_PHYRXFIFOCHECKERR    V_PHYRXFIFOCHECKERR(1U)
86229 #define V_PHYRXTXPPTERR(x) ((x) << S_PHYRXTXPPTERR)
86230 #define F_PHYRXTXPPTERR    V_PHYRXTXPPTERR(1U)
86233 #define V_PHYECCERR(x) ((x) << S_PHYECCERR)
86234 #define F_PHYECCERR    V_PHYECCERR(1U)
86238 #define V_PHYFWRESERVED(x) ((x) << S_PHYFWRESERVED)
86239 #define G_PHYFWRESERVED(x) (((x) >> S_PHYFWRESERVED) & M_PHYFWRESERVED)
86242 #define V_PHYTRNGFAIL(x) ((x) << S_PHYTRNGFAIL)
86243 #define F_PHYTRNGFAIL    V_PHYTRNGFAIL(1U)
86245 #define S_PHYINITCMPLT    1
86246 #define V_PHYINITCMPLT(x) ((x) << S_PHYINITCMPLT)
86247 #define F_PHYINITCMPLT    V_PHYINITCMPLT(1U)
86250 #define V_PHYTRNGCMPLT(x) ((x) << S_PHYTRNGCMPLT)
86251 #define F_PHYTRNGCMPLT    V_PHYTRNGCMPLT(1U)
86257 #define V_PHYINTERRUPTOVERRIDE(x) ((x) << S_PHYINTERRUPTOVERRIDE)
86258 #define G_PHYINTERRUPTOVERRIDE(x) (((x) >> S_PHYINTERRUPTOVERRIDE) & M_PHYINTERRUPTOVERRIDE)
86269 #define V_GC_MA_RSP(x) ((x) << S_GC_MA_RSP)
86270 #define F_GC_MA_RSP    V_GC_MA_RSP(1U)
86275 #define V_REGION_EN1(x) ((x) << S_REGION_EN1)
86276 #define F_REGION_EN1    V_REGION_EN1(1U)
86279 #define V_EDC_REGION1(x) ((x) << S_EDC_REGION1)
86280 #define F_EDC_REGION1    V_EDC_REGION1(1U)
86283 #define V_CACHE_REGION1(x) ((x) << S_CACHE_REGION1)
86284 #define F_CACHE_REGION1    V_CACHE_REGION1(1U)
86288 #define V_END1(x) ((x) << S_END1)
86289 #define G_END1(x) (((x) >> S_END1) & M_END1)
86294 #define V_REGION_EN2(x) ((x) << S_REGION_EN2)
86295 #define F_REGION_EN2    V_REGION_EN2(1U)
86298 #define V_EDC_REGION2(x) ((x) << S_EDC_REGION2)
86299 #define F_EDC_REGION2    V_EDC_REGION2(1U)
86302 #define V_CACHE_REGION2(x) ((x) << S_CACHE_REGION2)
86303 #define F_CACHE_REGION2    V_CACHE_REGION2(1U)
86307 #define V_END2(x) ((x) << S_END2)
86308 #define G_END2(x) (((x) >> S_END2) & M_END2)
86313 #define V_REGION_EN3(x) ((x) << S_REGION_EN3)
86314 #define F_REGION_EN3    V_REGION_EN3(1U)
86317 #define V_EDC_REGION3(x) ((x) << S_EDC_REGION3)
86318 #define F_EDC_REGION3    V_EDC_REGION3(1U)
86321 #define V_CACHE_REGION3(x) ((x) << S_CACHE_REGION3)
86322 #define F_CACHE_REGION3    V_CACHE_REGION3(1U)
86326 #define V_END3(x) ((x) << S_END3)
86327 #define G_END3(x) (((x) >> S_END3) & M_END3)
86332 #define V_REGION_EN4(x) ((x) << S_REGION_EN4)
86333 #define F_REGION_EN4    V_REGION_EN4(1U)
86336 #define V_EDC_REGION4(x) ((x) << S_EDC_REGION4)
86337 #define F_EDC_REGION4    V_EDC_REGION4(1U)
86340 #define V_CACHE_REGION4(x) ((x) << S_CACHE_REGION4)
86341 #define F_CACHE_REGION4    V_CACHE_REGION4(1U)
86345 #define V_END4(x) ((x) << S_END4)
86346 #define G_END4(x) (((x) >> S_END4) & M_END4)
86351 #define V_REGION_EN5(x) ((x) << S_REGION_EN5)
86352 #define F_REGION_EN5    V_REGION_EN5(1U)
86355 #define V_EDC_REGION5(x) ((x) << S_EDC_REGION5)
86356 #define F_EDC_REGION5    V_EDC_REGION5(1U)
86359 #define V_CACHE_REGION5(x) ((x) << S_CACHE_REGION5)
86360 #define F_CACHE_REGION5    V_CACHE_REGION5(1U)
86364 #define V_END5(x) ((x) << S_END5)
86365 #define G_END5(x) (((x) >> S_END5) & M_END5)
86370 #define V_REGION_EN6(x) ((x) << S_REGION_EN6)
86371 #define F_REGION_EN6    V_REGION_EN6(1U)
86374 #define V_EDC_REGION6(x) ((x) << S_EDC_REGION6)
86375 #define F_EDC_REGION6    V_EDC_REGION6(1U)
86378 #define V_CACHE_REGION6(x) ((x) << S_CACHE_REGION6)
86379 #define F_CACHE_REGION6    V_CACHE_REGION6(1U)
86383 #define V_END6(x) ((x) << S_END6)
86384 #define G_END6(x) (((x) >> S_END6) & M_END6)
86389 #define V_REGION_EN7(x) ((x) << S_REGION_EN7)
86390 #define F_REGION_EN7    V_REGION_EN7(1U)
86393 #define V_EDC_REGION7(x) ((x) << S_EDC_REGION7)
86394 #define F_EDC_REGION7    V_EDC_REGION7(1U)
86397 #define V_CACHE_REGION7(x) ((x) << S_CACHE_REGION7)
86398 #define F_CACHE_REGION7    V_CACHE_REGION7(1U)
86402 #define V_END7(x) ((x) << S_END7)
86403 #define G_END7(x) (((x) >> S_END7) & M_END7)
86408 #define V_REGION_EN8(x) ((x) << S_REGION_EN8)
86409 #define F_REGION_EN8    V_REGION_EN8(1U)
86412 #define V_EDC_REGION8(x) ((x) << S_EDC_REGION8)
86413 #define F_EDC_REGION8    V_EDC_REGION8(1U)
86416 #define V_CACHE_REGION8(x) ((x) << S_CACHE_REGION8)
86417 #define F_CACHE_REGION8    V_CACHE_REGION8(1U)
86421 #define V_END8(x) ((x) << S_END8)
86422 #define G_END8(x) (((x) >> S_END8) & M_END8)
86429 #define V_START1(x) ((x) << S_START1)
86430 #define G_START1(x) (((x) >> S_START1) & M_START1)
86436 #define V_START2(x) ((x) << S_START2)
86437 #define G_START2(x) (((x) >> S_START2) & M_START2)
86443 #define V_START3(x) ((x) << S_START3)
86444 #define G_START3(x) (((x) >> S_START3) & M_START3)
86450 #define V_START4(x) ((x) << S_START4)
86451 #define G_START4(x) (((x) >> S_START4) & M_START4)
86457 #define V_START5(x) ((x) << S_START5)
86458 #define G_START5(x) (((x) >> S_START5) & M_START5)
86464 #define V_START6(x) ((x) << S_START6)
86465 #define G_START6(x) (((x) >> S_START6) & M_START6)
86471 #define V_START7(x) ((x) << S_START7)
86472 #define G_START7(x) (((x) >> S_START7) & M_START7)
86478 #define V_START8(x) ((x) << S_START8)
86479 #define G_START8(x) (((x) >> S_START8) & M_START8)
86500 #define S_MC1_EN    1
86501 #define V_MC1_EN(x) ((x) << S_MC1_EN)
86502 #define F_MC1_EN    V_MC1_EN(1U)
86505 #define V_HMA_EN(x) ((x) << S_HMA_EN)
86506 #define F_HMA_EN    V_HMA_EN(1U)
86521 #define S_HMA_2MB    1
86522 #define V_HMA_2MB(x) ((x) << S_HMA_2MB)
86523 #define F_HMA_2MB    V_HMA_2MB(1U)
86526 #define V_MC0_2MB(x) ((x) << S_MC0_2MB)
86527 #define F_MC0_2MB    V_MC0_2MB(1U)
86533 #define V_CLIENT_HINT_EN(x) ((x) << S_CLIENT_HINT_EN)
86534 #define G_CLIENT_HINT_EN(x) (((x) >> S_CLIENT_HINT_EN) & M_CLIENT_HINT_EN)
86537 #define V_HINT_ADDR_SPLIT_EN(x) ((x) << S_HINT_ADDR_SPLIT_EN)
86538 #define F_HINT_ADDR_SPLIT_EN    V_HINT_ADDR_SPLIT_EN(1U)
86541 #define V_TP_HINT_HMA_MC(x) ((x) << S_TP_HINT_HMA_MC)
86542 #define F_TP_HINT_HMA_MC    V_TP_HINT_HMA_MC(1U)
86544 #define S_CIM_HINT_HMA_MC    1
86545 #define V_CIM_HINT_HMA_MC(x) ((x) << S_CIM_HINT_HMA_MC)
86546 #define F_CIM_HINT_HMA_MC    V_CIM_HINT_HMA_MC(1U)
86549 #define V_LE_HINT_HMA_MC(x) ((x) << S_LE_HINT_HMA_MC)
86550 #define F_LE_HINT_HMA_MC    V_LE_HINT_HMA_MC(1U)
86555 #define V_PERF_CLEAR_GC1(x) ((x) << S_PERF_CLEAR_GC1)
86556 #define F_PERF_CLEAR_GC1    V_PERF_CLEAR_GC1(1U)
86559 #define V_PERF_CLEAR_GC0(x) ((x) << S_PERF_CLEAR_GC0)
86560 #define F_PERF_CLEAR_GC0    V_PERF_CLEAR_GC0(1U)
86562 #define S_PERF_EN_GC1    1
86563 #define V_PERF_EN_GC1(x) ((x) << S_PERF_EN_GC1)
86564 #define F_PERF_EN_GC1    V_PERF_EN_GC1(1U)
86567 #define V_PERF_EN_GC0(x) ((x) << S_PERF_EN_GC0)
86568 #define F_PERF_EN_GC0    V_PERF_EN_GC0(1U)
86585 #define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
86586 #define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
86589 #define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE)
86590 #define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_CAUSE(1U)
86593 #define V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_CAUSE)
86594 #define F_GC1_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC1_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
86597 #define V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_CAUSE)
86598 #define F_GC0_WQDATA_FIFO_PERR_PAR_CAUSE    V_GC0_WQDATA_FIFO_PERR_PAR_CAUSE(1U)
86601 #define V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE)
86602 #define F_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86605 #define V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE)
86606 #define F_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86609 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
86610 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86613 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE)
86614 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_CAUSE(1U)
86617 #define V_GC1_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC1_RSP_PERR_PAR_CAUSE)
86618 #define F_GC1_RSP_PERR_PAR_CAUSE    V_GC1_RSP_PERR_PAR_CAUSE(1U)
86621 #define V_GC0_RSP_PERR_PAR_CAUSE(x) ((x) << S_GC0_RSP_PERR_PAR_CAUSE)
86622 #define F_GC0_RSP_PERR_PAR_CAUSE    V_GC0_RSP_PERR_PAR_CAUSE(1U)
86625 #define V_GC1_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_UERR_PAR_CAUSE)
86626 #define F_GC1_LRU_UERR_PAR_CAUSE    V_GC1_LRU_UERR_PAR_CAUSE(1U)
86629 #define V_GC0_LRU_UERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_UERR_PAR_CAUSE)
86630 #define F_GC0_LRU_UERR_PAR_CAUSE    V_GC0_LRU_UERR_PAR_CAUSE(1U)
86633 #define V_GC1_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_UERR_PAR_CAUSE)
86634 #define F_GC1_TAG_UERR_PAR_CAUSE    V_GC1_TAG_UERR_PAR_CAUSE(1U)
86637 #define V_GC0_TAG_UERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_UERR_PAR_CAUSE)
86638 #define F_GC0_TAG_UERR_PAR_CAUSE    V_GC0_TAG_UERR_PAR_CAUSE(1U)
86641 #define V_GC1_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC1_LRU_CERR_PAR_CAUSE)
86642 #define F_GC1_LRU_CERR_PAR_CAUSE    V_GC1_LRU_CERR_PAR_CAUSE(1U)
86645 #define V_GC0_LRU_CERR_PAR_CAUSE(x) ((x) << S_GC0_LRU_CERR_PAR_CAUSE)
86646 #define F_GC0_LRU_CERR_PAR_CAUSE    V_GC0_LRU_CERR_PAR_CAUSE(1U)
86649 #define V_GC1_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC1_TAG_CERR_PAR_CAUSE)
86650 #define F_GC1_TAG_CERR_PAR_CAUSE    V_GC1_TAG_CERR_PAR_CAUSE(1U)
86653 #define V_GC0_TAG_CERR_PAR_CAUSE(x) ((x) << S_GC0_TAG_CERR_PAR_CAUSE)
86654 #define F_GC0_TAG_CERR_PAR_CAUSE    V_GC0_TAG_CERR_PAR_CAUSE(1U)
86657 #define V_GC1_CE_PAR_CAUSE(x) ((x) << S_GC1_CE_PAR_CAUSE)
86658 #define F_GC1_CE_PAR_CAUSE    V_GC1_CE_PAR_CAUSE(1U)
86661 #define V_GC0_CE_PAR_CAUSE(x) ((x) << S_GC0_CE_PAR_CAUSE)
86662 #define F_GC0_CE_PAR_CAUSE    V_GC0_CE_PAR_CAUSE(1U)
86665 #define V_GC1_UE_PAR_CAUSE(x) ((x) << S_GC1_UE_PAR_CAUSE)
86666 #define F_GC1_UE_PAR_CAUSE    V_GC1_UE_PAR_CAUSE(1U)
86669 #define V_GC0_UE_PAR_CAUSE(x) ((x) << S_GC0_UE_PAR_CAUSE)
86670 #define F_GC0_UE_PAR_CAUSE    V_GC0_UE_PAR_CAUSE(1U)
86673 #define V_GC1_CMD_PAR_CAUSE(x) ((x) << S_GC1_CMD_PAR_CAUSE)
86674 #define F_GC1_CMD_PAR_CAUSE    V_GC1_CMD_PAR_CAUSE(1U)
86677 #define V_GC1_DATA_PAR_CAUSE(x) ((x) << S_GC1_DATA_PAR_CAUSE)
86678 #define F_GC1_DATA_PAR_CAUSE    V_GC1_DATA_PAR_CAUSE(1U)
86681 #define V_GC0_CMD_PAR_CAUSE(x) ((x) << S_GC0_CMD_PAR_CAUSE)
86682 #define F_GC0_CMD_PAR_CAUSE    V_GC0_CMD_PAR_CAUSE(1U)
86685 #define V_GC0_DATA_PAR_CAUSE(x) ((x) << S_GC0_DATA_PAR_CAUSE)
86686 #define F_GC0_DATA_PAR_CAUSE    V_GC0_DATA_PAR_CAUSE(1U)
86688 #define S_ILLADDRACCESS1_PAR_CAUSE    1
86689 #define V_ILLADDRACCESS1_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS1_PAR_CAUSE)
86690 #define F_ILLADDRACCESS1_PAR_CAUSE    V_ILLADDRACCESS1_PAR_CAUSE(1U)
86693 #define V_ILLADDRACCESS0_PAR_CAUSE(x) ((x) << S_ILLADDRACCESS0_PAR_CAUSE)
86694 #define F_ILLADDRACCESS0_PAR_CAUSE    V_ILLADDRACCESS0_PAR_CAUSE(1U)
86699 #define V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
86700 #define F_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
86703 #define V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE)
86704 #define F_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_PAR_ENABLE(1U)
86707 #define V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_PAR_ENABLE)
86708 #define F_GC1_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC1_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
86711 #define V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_PAR_ENABLE)
86712 #define F_GC0_WQDATA_FIFO_PERR_PAR_ENABLE    V_GC0_WQDATA_FIFO_PERR_PAR_ENABLE(1U)
86715 #define V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE)
86716 #define F_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86719 #define V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE)
86720 #define F_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86723 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
86724 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86727 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE)
86728 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_PAR_ENABLE(1U)
86731 #define V_GC1_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC1_RSP_PERR_PAR_ENABLE)
86732 #define F_GC1_RSP_PERR_PAR_ENABLE    V_GC1_RSP_PERR_PAR_ENABLE(1U)
86735 #define V_GC0_RSP_PERR_PAR_ENABLE(x) ((x) << S_GC0_RSP_PERR_PAR_ENABLE)
86736 #define F_GC0_RSP_PERR_PAR_ENABLE    V_GC0_RSP_PERR_PAR_ENABLE(1U)
86739 #define V_GC1_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_UERR_PAR_ENABLE)
86740 #define F_GC1_LRU_UERR_PAR_ENABLE    V_GC1_LRU_UERR_PAR_ENABLE(1U)
86743 #define V_GC0_LRU_UERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_UERR_PAR_ENABLE)
86744 #define F_GC0_LRU_UERR_PAR_ENABLE    V_GC0_LRU_UERR_PAR_ENABLE(1U)
86747 #define V_GC1_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_UERR_PAR_ENABLE)
86748 #define F_GC1_TAG_UERR_PAR_ENABLE    V_GC1_TAG_UERR_PAR_ENABLE(1U)
86751 #define V_GC0_TAG_UERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_UERR_PAR_ENABLE)
86752 #define F_GC0_TAG_UERR_PAR_ENABLE    V_GC0_TAG_UERR_PAR_ENABLE(1U)
86755 #define V_GC1_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC1_LRU_CERR_PAR_ENABLE)
86756 #define F_GC1_LRU_CERR_PAR_ENABLE    V_GC1_LRU_CERR_PAR_ENABLE(1U)
86759 #define V_GC0_LRU_CERR_PAR_ENABLE(x) ((x) << S_GC0_LRU_CERR_PAR_ENABLE)
86760 #define F_GC0_LRU_CERR_PAR_ENABLE    V_GC0_LRU_CERR_PAR_ENABLE(1U)
86763 #define V_GC1_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC1_TAG_CERR_PAR_ENABLE)
86764 #define F_GC1_TAG_CERR_PAR_ENABLE    V_GC1_TAG_CERR_PAR_ENABLE(1U)
86767 #define V_GC0_TAG_CERR_PAR_ENABLE(x) ((x) << S_GC0_TAG_CERR_PAR_ENABLE)
86768 #define F_GC0_TAG_CERR_PAR_ENABLE    V_GC0_TAG_CERR_PAR_ENABLE(1U)
86771 #define V_GC1_CE_PAR_ENABLE(x) ((x) << S_GC1_CE_PAR_ENABLE)
86772 #define F_GC1_CE_PAR_ENABLE    V_GC1_CE_PAR_ENABLE(1U)
86775 #define V_GC0_CE_PAR_ENABLE(x) ((x) << S_GC0_CE_PAR_ENABLE)
86776 #define F_GC0_CE_PAR_ENABLE    V_GC0_CE_PAR_ENABLE(1U)
86779 #define V_GC1_UE_PAR_ENABLE(x) ((x) << S_GC1_UE_PAR_ENABLE)
86780 #define F_GC1_UE_PAR_ENABLE    V_GC1_UE_PAR_ENABLE(1U)
86783 #define V_GC0_UE_PAR_ENABLE(x) ((x) << S_GC0_UE_PAR_ENABLE)
86784 #define F_GC0_UE_PAR_ENABLE    V_GC0_UE_PAR_ENABLE(1U)
86787 #define V_GC1_CMD_PAR_ENABLE(x) ((x) << S_GC1_CMD_PAR_ENABLE)
86788 #define F_GC1_CMD_PAR_ENABLE    V_GC1_CMD_PAR_ENABLE(1U)
86791 #define V_GC1_DATA_PAR_ENABLE(x) ((x) << S_GC1_DATA_PAR_ENABLE)
86792 #define F_GC1_DATA_PAR_ENABLE    V_GC1_DATA_PAR_ENABLE(1U)
86795 #define V_GC0_CMD_PAR_ENABLE(x) ((x) << S_GC0_CMD_PAR_ENABLE)
86796 #define F_GC0_CMD_PAR_ENABLE    V_GC0_CMD_PAR_ENABLE(1U)
86799 #define V_GC0_DATA_PAR_ENABLE(x) ((x) << S_GC0_DATA_PAR_ENABLE)
86800 #define F_GC0_DATA_PAR_ENABLE    V_GC0_DATA_PAR_ENABLE(1U)
86802 #define S_ILLADDRACCESS1_PAR_ENABLE    1
86803 #define V_ILLADDRACCESS1_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS1_PAR_ENABLE)
86804 #define F_ILLADDRACCESS1_PAR_ENABLE    V_ILLADDRACCESS1_PAR_ENABLE(1U)
86807 #define V_ILLADDRACCESS0_PAR_ENABLE(x) ((x) << S_ILLADDRACCESS0_PAR_ENABLE)
86808 #define F_ILLADDRACCESS0_PAR_ENABLE    V_ILLADDRACCESS0_PAR_ENABLE(1U)
86813 #define V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
86814 #define F_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
86817 #define V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE)
86818 #define F_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_ENABLE(1U)
86821 #define V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_ENABLE)
86822 #define F_GC1_WQDATA_FIFO_PERR_INT_ENABLE    V_GC1_WQDATA_FIFO_PERR_INT_ENABLE(1U)
86825 #define V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_ENABLE)
86826 #define F_GC0_WQDATA_FIFO_PERR_INT_ENABLE    V_GC0_WQDATA_FIFO_PERR_INT_ENABLE(1U)
86829 #define V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_ENABLE)
86830 #define F_GC1_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86833 #define V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_ENABLE)
86834 #define F_GC0_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86837 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
86838 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86841 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE)
86842 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_ENABLE(1U)
86845 #define V_GC1_RSP_PERR_INT_ENABLE(x) ((x) << S_GC1_RSP_PERR_INT_ENABLE)
86846 #define F_GC1_RSP_PERR_INT_ENABLE    V_GC1_RSP_PERR_INT_ENABLE(1U)
86849 #define V_GC0_RSP_PERR_INT_ENABLE(x) ((x) << S_GC0_RSP_PERR_INT_ENABLE)
86850 #define F_GC0_RSP_PERR_INT_ENABLE    V_GC0_RSP_PERR_INT_ENABLE(1U)
86853 #define V_GC1_LRU_UERR_INT_ENABLE(x) ((x) << S_GC1_LRU_UERR_INT_ENABLE)
86854 #define F_GC1_LRU_UERR_INT_ENABLE    V_GC1_LRU_UERR_INT_ENABLE(1U)
86857 #define V_GC0_LRU_UERR_INT_ENABLE(x) ((x) << S_GC0_LRU_UERR_INT_ENABLE)
86858 #define F_GC0_LRU_UERR_INT_ENABLE    V_GC0_LRU_UERR_INT_ENABLE(1U)
86861 #define V_GC1_TAG_UERR_INT_ENABLE(x) ((x) << S_GC1_TAG_UERR_INT_ENABLE)
86862 #define F_GC1_TAG_UERR_INT_ENABLE    V_GC1_TAG_UERR_INT_ENABLE(1U)
86865 #define V_GC0_TAG_UERR_INT_ENABLE(x) ((x) << S_GC0_TAG_UERR_INT_ENABLE)
86866 #define F_GC0_TAG_UERR_INT_ENABLE    V_GC0_TAG_UERR_INT_ENABLE(1U)
86869 #define V_GC1_LRU_CERR_INT_ENABLE(x) ((x) << S_GC1_LRU_CERR_INT_ENABLE)
86870 #define F_GC1_LRU_CERR_INT_ENABLE    V_GC1_LRU_CERR_INT_ENABLE(1U)
86873 #define V_GC0_LRU_CERR_INT_ENABLE(x) ((x) << S_GC0_LRU_CERR_INT_ENABLE)
86874 #define F_GC0_LRU_CERR_INT_ENABLE    V_GC0_LRU_CERR_INT_ENABLE(1U)
86877 #define V_GC1_TAG_CERR_INT_ENABLE(x) ((x) << S_GC1_TAG_CERR_INT_ENABLE)
86878 #define F_GC1_TAG_CERR_INT_ENABLE    V_GC1_TAG_CERR_INT_ENABLE(1U)
86881 #define V_GC0_TAG_CERR_INT_ENABLE(x) ((x) << S_GC0_TAG_CERR_INT_ENABLE)
86882 #define F_GC0_TAG_CERR_INT_ENABLE    V_GC0_TAG_CERR_INT_ENABLE(1U)
86885 #define V_GC1_CE_INT_ENABLE(x) ((x) << S_GC1_CE_INT_ENABLE)
86886 #define F_GC1_CE_INT_ENABLE    V_GC1_CE_INT_ENABLE(1U)
86889 #define V_GC0_CE_INT_ENABLE(x) ((x) << S_GC0_CE_INT_ENABLE)
86890 #define F_GC0_CE_INT_ENABLE    V_GC0_CE_INT_ENABLE(1U)
86893 #define V_GC1_UE_INT_ENABLE(x) ((x) << S_GC1_UE_INT_ENABLE)
86894 #define F_GC1_UE_INT_ENABLE    V_GC1_UE_INT_ENABLE(1U)
86897 #define V_GC0_UE_INT_ENABLE(x) ((x) << S_GC0_UE_INT_ENABLE)
86898 #define F_GC0_UE_INT_ENABLE    V_GC0_UE_INT_ENABLE(1U)
86901 #define V_GC1_CMD_PAR_INT_ENABLE(x) ((x) << S_GC1_CMD_PAR_INT_ENABLE)
86902 #define F_GC1_CMD_PAR_INT_ENABLE    V_GC1_CMD_PAR_INT_ENABLE(1U)
86905 #define V_GC1_DATA_PAR_INT_ENABLE(x) ((x) << S_GC1_DATA_PAR_INT_ENABLE)
86906 #define F_GC1_DATA_PAR_INT_ENABLE    V_GC1_DATA_PAR_INT_ENABLE(1U)
86909 #define V_GC0_CMD_PAR_INT_ENABLE(x) ((x) << S_GC0_CMD_PAR_INT_ENABLE)
86910 #define F_GC0_CMD_PAR_INT_ENABLE    V_GC0_CMD_PAR_INT_ENABLE(1U)
86913 #define V_GC0_DATA_PAR_INT_ENABLE(x) ((x) << S_GC0_DATA_PAR_INT_ENABLE)
86914 #define F_GC0_DATA_PAR_INT_ENABLE    V_GC0_DATA_PAR_INT_ENABLE(1U)
86916 #define S_ILLADDRACCESS1_INT_ENABLE    1
86917 #define V_ILLADDRACCESS1_INT_ENABLE(x) ((x) << S_ILLADDRACCESS1_INT_ENABLE)
86918 #define F_ILLADDRACCESS1_INT_ENABLE    V_ILLADDRACCESS1_INT_ENABLE(1U)
86921 #define V_ILLADDRACCESS0_INT_ENABLE(x) ((x) << S_ILLADDRACCESS0_INT_ENABLE)
86922 #define F_ILLADDRACCESS0_INT_ENABLE    V_ILLADDRACCESS0_INT_ENABLE(1U)
86927 #define V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
86928 #define F_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC1_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
86931 #define V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE)
86932 #define F_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE    V_GC0_SRAM_RSP_DATAQ_PERR_INT_CAUSE(1U)
86935 #define V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC1_WQDATA_FIFO_PERR_INT_CAUSE)
86936 #define F_GC1_WQDATA_FIFO_PERR_INT_CAUSE    V_GC1_WQDATA_FIFO_PERR_INT_CAUSE(1U)
86939 #define V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(x) ((x) << S_GC0_WQDATA_FIFO_PERR_INT_CAUSE)
86940 #define F_GC0_WQDATA_FIFO_PERR_INT_CAUSE    V_GC0_WQDATA_FIFO_PERR_INT_CAUSE(1U)
86943 #define V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_RDTAG_QUEUE_PERR_INT_CAUSE)
86944 #define F_GC1_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86947 #define V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_RDTAG_QUEUE_PERR_INT_CAUSE)
86948 #define F_GC0_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86951 #define V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
86952 #define F_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC1_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86955 #define V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(x) ((x) << S_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE)
86956 #define F_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE    V_GC0_SRAM_RDTAG_QUEUE_PERR_INT_CAUSE(1U)
86959 #define V_GC1_RSP_PERR_INT_CAUSE(x) ((x) << S_GC1_RSP_PERR_INT_CAUSE)
86960 #define F_GC1_RSP_PERR_INT_CAUSE    V_GC1_RSP_PERR_INT_CAUSE(1U)
86963 #define V_GC0_RSP_PERR_INT_CAUSE(x) ((x) << S_GC0_RSP_PERR_INT_CAUSE)
86964 #define F_GC0_RSP_PERR_INT_CAUSE    V_GC0_RSP_PERR_INT_CAUSE(1U)
86967 #define V_GC1_LRU_UERR_INT_CAUSE(x) ((x) << S_GC1_LRU_UERR_INT_CAUSE)
86968 #define F_GC1_LRU_UERR_INT_CAUSE    V_GC1_LRU_UERR_INT_CAUSE(1U)
86971 #define V_GC0_LRU_UERR_INT_CAUSE(x) ((x) << S_GC0_LRU_UERR_INT_CAUSE)
86972 #define F_GC0_LRU_UERR_INT_CAUSE    V_GC0_LRU_UERR_INT_CAUSE(1U)
86975 #define V_GC1_TAG_UERR_INT_CAUSE(x) ((x) << S_GC1_TAG_UERR_INT_CAUSE)
86976 #define F_GC1_TAG_UERR_INT_CAUSE    V_GC1_TAG_UERR_INT_CAUSE(1U)
86979 #define V_GC0_TAG_UERR_INT_CAUSE(x) ((x) << S_GC0_TAG_UERR_INT_CAUSE)
86980 #define F_GC0_TAG_UERR_INT_CAUSE    V_GC0_TAG_UERR_INT_CAUSE(1U)
86983 #define V_GC1_LRU_CERR_INT_CAUSE(x) ((x) << S_GC1_LRU_CERR_INT_CAUSE)
86984 #define F_GC1_LRU_CERR_INT_CAUSE    V_GC1_LRU_CERR_INT_CAUSE(1U)
86987 #define V_GC0_LRU_CERR_INT_CAUSE(x) ((x) << S_GC0_LRU_CERR_INT_CAUSE)
86988 #define F_GC0_LRU_CERR_INT_CAUSE    V_GC0_LRU_CERR_INT_CAUSE(1U)
86991 #define V_GC1_TAG_CERR_INT_CAUSE(x) ((x) << S_GC1_TAG_CERR_INT_CAUSE)
86992 #define F_GC1_TAG_CERR_INT_CAUSE    V_GC1_TAG_CERR_INT_CAUSE(1U)
86995 #define V_GC0_TAG_CERR_INT_CAUSE(x) ((x) << S_GC0_TAG_CERR_INT_CAUSE)
86996 #define F_GC0_TAG_CERR_INT_CAUSE    V_GC0_TAG_CERR_INT_CAUSE(1U)
86999 #define V_GC1_CE_INT_CAUSE(x) ((x) << S_GC1_CE_INT_CAUSE)
87000 #define F_GC1_CE_INT_CAUSE    V_GC1_CE_INT_CAUSE(1U)
87003 #define V_GC0_CE_INT_CAUSE(x) ((x) << S_GC0_CE_INT_CAUSE)
87004 #define F_GC0_CE_INT_CAUSE    V_GC0_CE_INT_CAUSE(1U)
87007 #define V_GC1_UE_INT_CAUSE(x) ((x) << S_GC1_UE_INT_CAUSE)
87008 #define F_GC1_UE_INT_CAUSE    V_GC1_UE_INT_CAUSE(1U)
87011 #define V_GC0_UE_INT_CAUSE(x) ((x) << S_GC0_UE_INT_CAUSE)
87012 #define F_GC0_UE_INT_CAUSE    V_GC0_UE_INT_CAUSE(1U)
87015 #define V_GC1_CMD_PAR_INT_CAUSE(x) ((x) << S_GC1_CMD_PAR_INT_CAUSE)
87016 #define F_GC1_CMD_PAR_INT_CAUSE    V_GC1_CMD_PAR_INT_CAUSE(1U)
87019 #define V_GC1_DATA_PAR_INT_CAUSE(x) ((x) << S_GC1_DATA_PAR_INT_CAUSE)
87020 #define F_GC1_DATA_PAR_INT_CAUSE    V_GC1_DATA_PAR_INT_CAUSE(1U)
87023 #define V_GC0_CMD_PAR_INT_CAUSE(x) ((x) << S_GC0_CMD_PAR_INT_CAUSE)
87024 #define F_GC0_CMD_PAR_INT_CAUSE    V_GC0_CMD_PAR_INT_CAUSE(1U)
87027 #define V_GC0_DATA_PAR_INT_CAUSE(x) ((x) << S_GC0_DATA_PAR_INT_CAUSE)
87028 #define F_GC0_DATA_PAR_INT_CAUSE    V_GC0_DATA_PAR_INT_CAUSE(1U)
87030 #define S_ILLADDRACCESS1_INT_CAUSE    1
87031 #define V_ILLADDRACCESS1_INT_CAUSE(x) ((x) << S_ILLADDRACCESS1_INT_CAUSE)
87032 #define F_ILLADDRACCESS1_INT_CAUSE    V_ILLADDRACCESS1_INT_CAUSE(1U)
87035 #define V_ILLADDRACCESS0_INT_CAUSE(x) ((x) << S_ILLADDRACCESS0_INT_CAUSE)
87036 #define F_ILLADDRACCESS0_INT_CAUSE    V_ILLADDRACCESS0_INT_CAUSE(1U)
87041 #define V_DBG_SEL_CTRLSEL_OVR_EN(x) ((x) << S_DBG_SEL_CTRLSEL_OVR_EN)
87042 #define F_DBG_SEL_CTRLSEL_OVR_EN    V_DBG_SEL_CTRLSEL_OVR_EN(1U)
87045 #define V_T7_DEBUG_HI(x) ((x) << S_T7_DEBUG_HI)
87046 #define F_T7_DEBUG_HI    V_T7_DEBUG_HI(1U)
87050 #define V_DBG_SEL_CTRLSELH(x) ((x) << S_DBG_SEL_CTRLSELH)
87051 #define G_DBG_SEL_CTRLSELH(x) (((x) >> S_DBG_SEL_CTRLSELH) & M_DBG_SEL_CTRLSELH)
87055 #define V_DBG_SEL_CTRLSELL(x) ((x) << S_DBG_SEL_CTRLSELL)
87056 #define G_DBG_SEL_CTRLSELL(x) (((x) >> S_DBG_SEL_CTRLSELL) & M_DBG_SEL_CTRLSELL)