Lines Matching +full:0 +full:xe14

36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
63 #define PF_STRIDE 0x400
67 #define VF_SGE_BASE 0x0
70 #define VF_MPS_BASE 0x100
73 #define VF_PL_BASE 0x200
76 #define VF_MBDATA_BASE 0x240
79 #define VF_CIM_BASE 0x300
82 #define MYPORT_BASE 0x1c000
85 #define PORT0_BASE 0x20000
88 #define PORT1_BASE 0x22000
91 #define PORT2_BASE 0x24000
94 #define PORT3_BASE 0x26000
97 #define PORT_STRIDE 0x2000
269 #define T5_MYPORT_BASE 0x2c000
272 #define T5_PORT0_BASE 0x30000
275 #define T5_PORT1_BASE 0x34000
278 #define T5_PORT2_BASE 0x38000
281 #define T5_PORT3_BASE 0x3c000
284 #define T5_PORT_STRIDE 0x4000
511 #define SGE_BASE_ADDR 0x1000
513 #define A_SGE_PF_KDOORBELL 0x0
516 #define M_QID    0x1ffffU
524 #define S_PIDX    0
525 #define M_PIDX    0x3fffU
529 #define A_SGE_VF_KDOORBELL 0x0
535 #define S_PIDX_T5    0
536 #define M_PIDX_T5    0x1fffU
544 #define A_SGE_PF_GTS 0x4
547 #define M_INGRESSQID    0xffffU
552 #define M_TIMERREG    0x7U
560 #define S_CIDXINC    0
561 #define M_CIDXINC    0xfffU
565 #define A_SGE_VF_GTS 0x4
566 #define A_SGE_PF_KTIMESTAMP_LO 0x8
567 #define A_SGE_VF_KTIMESTAMP_LO 0x8
568 #define A_SGE_PF_KTIMESTAMP_HI 0xc
570 #define S_TSTAMPVAL    0
571 #define M_TSTAMPVAL    0xfffffffU
575 #define A_SGE_VF_KTIMESTAMP_HI 0xc
576 #define A_SGE_CONTROL 0x1008
583 #define M_FLSPLITMIN    0x1ffU
588 #define M_FLSPLITMODE    0x3U
617 #define M_PKTSHIFT    0x7U
622 #define M_INGPCIEBOUNDARY    0x7U
627 #define M_INGPADBOUNDARY    0x7U
632 #define M_EGRPCIEBOUNDARY    0x7U
636 #define S_GLOBALENABLE    0
640 #define A_SGE_HOST_PAGE_SIZE 0x100c
643 #define M_HOSTPAGESIZEPF7    0xfU
648 #define M_HOSTPAGESIZEPF6    0xfU
653 #define M_HOSTPAGESIZEPF5    0xfU
658 #define M_HOSTPAGESIZEPF4    0xfU
663 #define M_HOSTPAGESIZEPF3    0xfU
668 #define M_HOSTPAGESIZEPF2    0xfU
673 #define M_HOSTPAGESIZEPF1    0xfU
677 #define S_HOSTPAGESIZEPF0    0
678 #define M_HOSTPAGESIZEPF0    0xfU
682 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
685 #define M_QUEUESPERPAGEPF7    0xfU
690 #define M_QUEUESPERPAGEPF6    0xfU
695 #define M_QUEUESPERPAGEPF5    0xfU
700 #define M_QUEUESPERPAGEPF4    0xfU
705 #define M_QUEUESPERPAGEPF3    0xfU
710 #define M_QUEUESPERPAGEPF2    0xfU
715 #define M_QUEUESPERPAGEPF1    0xfU
719 #define S_QUEUESPERPAGEPF0    0
720 #define M_QUEUESPERPAGEPF0    0xfU
724 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
727 #define M_QUEUESPERPAGEVFPF7    0xfU
732 #define M_QUEUESPERPAGEVFPF6    0xfU
737 #define M_QUEUESPERPAGEVFPF5    0xfU
742 #define M_QUEUESPERPAGEVFPF4    0xfU
747 #define M_QUEUESPERPAGEVFPF3    0xfU
752 #define M_QUEUESPERPAGEVFPF2    0xfU
757 #define M_QUEUESPERPAGEVFPF1    0xfU
761 #define S_QUEUESPERPAGEVFPF0    0
762 #define M_QUEUESPERPAGEVFPF0    0xfU
766 #define A_SGE_USER_MODE_LIMITS 0x1018
769 #define M_OPCODE_MIN    0xffU
774 #define M_OPCODE_MAX    0xffU
779 #define M_LENGTH_MIN    0xffU
783 #define S_LENGTH_MAX    0
784 #define M_LENGTH_MAX    0xffU
788 #define A_SGE_WR_ERROR 0x101c
790 #define S_WR_ERROR_OPCODE    0
791 #define M_WR_ERROR_OPCODE    0xffU
795 #define A_SGE_PERR_INJECT 0x1020
798 #define M_MEMSEL    0x1fU
802 #define S_INJECTDATAERR    0
806 #define A_SGE_INT_CAUSE1 0x1024
928 #define S_PERR_EGR_CTXT_MIFRSP    0
944 #define A_SGE_INT_ENABLE1 0x1028
945 #define A_SGE_PERR_ENABLE1 0x102c
946 #define A_SGE_INT_CAUSE2 0x1030
1068 #define S_PERR_BASE_SIZE    0
1108 #define A_SGE_INT_ENABLE2 0x1034
1109 #define A_SGE_PERR_ENABLE2 0x1038
1110 #define A_SGE_INT_CAUSE3 0x103c
1236 #define S_ERR_INV_CTXT0    0
1248 #define A_SGE_INT_ENABLE3 0x1040
1249 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1252 #define CXGBE_M_SIZE    0xfffffffU
1257 #define M_T6_SIZE    0xfffffU
1261 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1264 #define M_T6_SIZE    0xfffffU
1268 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1271 #define M_T6_SIZE    0xfffffU
1275 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1278 #define M_T6_SIZE    0xfffffU
1282 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1285 #define M_T6_SIZE    0xfffffU
1289 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1292 #define M_T6_SIZE    0xfffffU
1296 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1299 #define M_T6_SIZE    0xfffffU
1303 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1306 #define M_T6_SIZE    0xfffffU
1310 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1313 #define M_T6_SIZE    0xfffffU
1317 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1320 #define M_T6_SIZE    0xfffffU
1324 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1327 #define M_T6_SIZE    0xfffffU
1331 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1334 #define M_T6_SIZE    0xfffffU
1338 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1341 #define M_T6_SIZE    0xfffffU
1345 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1348 #define M_T6_SIZE    0xfffffU
1352 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1355 #define M_T6_SIZE    0xfffffU
1359 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1362 #define M_T6_SIZE    0xfffffU
1366 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1369 #define M_BASEADDR    0x1fffffffU
1373 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1374 #define A_SGE_FLM_CACHE_BADDR 0x108c
1375 #define A_SGE_FLM_CFG 0x1090
1378 #define M_OPMODE    0x3fU
1387 #define M_CACHEPTRCNT    0x3U
1392 #define M_EDRAMPTRCNT    0x3U
1397 #define M_HDRSTARTFLQ    0x7U
1402 #define M_FETCHTHRESH    0x1fU
1407 #define M_CREDITCNT    0x3U
1411 #define S_NOEDRAM    0
1416 #define M_CREDITCNTPACKING    0x3U
1421 #define M_NULLPTR    0xfU
1429 #define A_SGE_CONM_CTRL 0x1094
1432 #define M_EGRTHRESHOLD    0x3fU
1437 #define M_INGTHRESHOLD    0x3fU
1445 #define S_TP_ENABLE    0
1450 #define M_EGRTHRESHOLDPACKING    0x3fU
1455 #define M_T6_EGRTHRESHOLDPACKING    0xffU
1460 #define M_T6_EGRTHRESHOLD    0xffU
1464 #define A_SGE_TIMESTAMP_LO 0x1098
1465 #define A_SGE_TIMESTAMP_HI 0x109c
1468 #define M_TSOP    0x3U
1472 #define S_TSVAL    0
1473 #define M_TSVAL    0xfffffffU
1477 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1480 #define M_THRESHOLD_0    0x3fU
1485 #define M_THRESHOLD_1    0x3fU
1490 #define M_THRESHOLD_2    0x3fU
1494 #define S_THRESHOLD_3    0
1495 #define M_THRESHOLD_3    0x3fU
1499 #define A_SGE_DBFIFO_STATUS 0x10a4
1502 #define M_HP_INT_THRESH    0xfU
1507 #define M_HP_COUNT    0x7ffU
1512 #define M_LP_INT_THRESH    0xfU
1516 #define S_LP_COUNT    0
1517 #define M_LP_COUNT    0x7ffU
1530 #define M_LP_INT_THRESH_T5    0xfffU
1534 #define S_LP_COUNT_T5    0
1535 #define M_LP_COUNT_T5    0x3ffffU
1540 #define M_VFIFO_CNT    0x1ffffU
1545 #define M_COAL_CTL_FIFO_CNT    0x3fU
1549 #define S_MERGE_FIFO_CNT    0
1550 #define M_MERGE_FIFO_CNT    0x3fU
1554 #define A_SGE_DOORBELL_CONTROL 0x10a8
1557 #define M_HINTDEPTHCTL    0x1fU
1566 #define M_HP_WEIGHT    0x3U
1615 #define M_DROP_TIMEOUT    0xfffU
1619 #define S_DROPPED_DB    0
1624 #define M_T6_DROP_TIMEOUT    0x3fU
1641 #define M_GTS_DBG_TIMER_REG    0x7U
1645 #define S_GTS_DBG_EN    0
1649 #define A_SGE_DROPPED_DOORBELL 0x10ac
1650 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1653 #define M_THROTTLE_COUNT    0xfffU
1657 #define S_THROTTLE_ENABLE    0
1662 #define M_BAR2THROTTLECOUNT    0xffU
1678 #define A_SGE_ITP_CONTROL 0x10b4
1681 #define M_CRITICAL_TIME    0x7fffU
1686 #define M_LL_EMPTY    0x3fU
1690 #define S_LL_READ_WAIT_DISABLE    0
1695 #define M_TSCALE    0xfU
1699 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1702 #define M_TIMERVALUE0    0xffffU
1706 #define S_TIMERVALUE1    0
1707 #define M_TIMERVALUE1    0xffffU
1711 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1714 #define M_TIMERVALUE2    0xffffU
1718 #define S_TIMERVALUE3    0
1719 #define M_TIMERVALUE3    0xffffU
1723 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1726 #define M_TIMERVALUE4    0xffffU
1730 #define S_TIMERVALUE5    0
1731 #define M_TIMERVALUE5    0xffffU
1735 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1742 #define M_MAXTAG0    0x7fU
1747 #define M_MAXRSPCNT0    0xffU
1756 #define M_MAXTAG1    0x7fU
1760 #define S_MAXRSPCNT1    0
1761 #define M_MAXRSPCNT1    0xffU
1765 #define A_SGE_GK_CONTROL 0x10c4
1772 #define M_FL_PROG_THRESH    0x1ffU
1789 #define M_DB_PROG_THRESH    0x1ffU
1793 #define S_100NS_TIMER    0
1794 #define M_100NS_TIMER    0xffU
1798 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1805 #define M_MAXTAG2    0x7fU
1810 #define M_MAXRSPCNT2    0xffU
1819 #define M_MAXTAG3    0x7fU
1823 #define S_MAXRSPCNT3    0
1824 #define M_MAXRSPCNT3    0xffU
1828 #define A_SGE_GK_CONTROL2 0x10c8
1831 #define M_DBQ_TIMER_TICK    0xffffU
1836 #define M_FL_MERGE_CNT_THRESH    0xfU
1840 #define S_MERGE_CNT_THRESH    0
1841 #define M_MERGE_CNT_THRESH    0x3fU
1845 #define A_SGE_DEBUG_INDEX 0x10cc
1846 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1847 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1848 #define A_SGE_REVISION 0x10d8
1849 #define A_SGE_INT_CAUSE4 0x10dc
1883 #define S_ERR_UNEXPECTED_TIMER    0
1995 #define A_SGE_INT_ENABLE4 0x10e0
1996 #define A_SGE_STAT_TOTAL 0x10e4
1997 #define A_SGE_STAT_MATCH 0x10e8
1998 #define A_SGE_STAT_CFG 0x10ec
2005 #define M_EGRCTXTOPMODE    0x3U
2010 #define M_INGCTXTOPMODE    0x3U
2015 #define M_STATMODE    0x3U
2019 #define S_STATSOURCE    0
2020 #define M_STATSOURCE    0x3U
2025 #define M_STATSOURCE_T5    0xfU
2029 #define S_T6_STATMODE    0
2030 #define M_T6_STATMODE    0xfU
2034 #define A_SGE_HINT_CFG 0x10f0
2037 #define M_HINTSALLOWEDNOHDR    0x3fU
2041 #define S_HINTSALLOWEDHDR    0
2042 #define M_HINTSALLOWEDHDR    0x3fU
2047 #define M_UPCUTOFFTHRESHLP    0x7ffU
2051 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
2052 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
2053 #define A_SGE_PD_WRR_CONFIG 0x10fc
2055 #define S_EDMA_WEIGHT    0
2056 #define M_EDMA_WEIGHT    0x3fU
2060 #define A_SGE_ERROR_STATS 0x1100
2070 #define S_ERROR_QID    0
2071 #define M_ERROR_QID    0x1ffffU
2076 #define M_CAUSE_REGISTER    0x7U
2081 #define M_CAUSE_BIT    0x1fU
2085 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
2088 #define M_MINTAG3    0xffU
2093 #define M_MINTAG2    0xffU
2098 #define M_MINTAG1    0xffU
2102 #define S_MINTAG0    0
2103 #define M_MINTAG0    0xffU
2107 #define A_SGE_IDMA0_DROP_CNT 0x1104
2108 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
2110 #define S_TAGPOOLTOTAL    0
2111 #define M_TAGPOOLTOTAL    0xffU
2115 #define A_SGE_IDMA1_DROP_CNT 0x1108
2116 #define A_SGE_INT_CAUSE5 0x110c
2242 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2246 #define A_SGE_INT_ENABLE5 0x1110
2247 #define A_SGE_PERR_ENABLE5 0x1114
2248 #define A_SGE_DBFIFO_STATUS2 0x1118
2251 #define M_FL_INT_THRESH    0xfU
2256 #define M_FL_COUNT    0x3ffU
2261 #define M_HP_INT_THRESH_T5    0xfU
2265 #define S_HP_COUNT_T5    0
2266 #define M_HP_COUNT_T5    0x3ffU
2270 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2273 #define M_FETCHBURSTMAX0    0x3ffU
2277 #define S_FETCHBURSTMAX1    0
2278 #define M_FETCHBURSTMAX1    0x3ffU
2282 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2285 #define M_FETCHBURSTMAX2    0x3ffU
2289 #define S_FETCHBURSTMAX3    0
2290 #define M_FETCHBURSTMAX3    0x3ffU
2294 #define A_SGE_CONTROL2 0x1124
2309 #define M_INGPACKBOUNDARY    0x7U
2342 #define M_HINTDEPTHCTLFL    0x1fU
2358 #define S_TX_COALESCE_PRI    0
2362 #define A_SGE_DEEP_SLEEP 0x1128
2408 #define S_EDMA0_SLEEP_REQ    0
2412 #define A_SGE_INT_CAUSE6 0x1128
2483 #define M_FATAL_DEQ_DRDY    0x3U
2488 #define M_FATAL_OUTP_DRDY    0x3U
2492 #define S_FATAL_DEQ    0
2496 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
2499 #define M_THROTTLE_THRESHOLD_FL    0xfU
2504 #define M_THROTTLE_THRESHOLD_HP    0xfU
2508 #define S_THROTTLE_THRESHOLD_LP    0
2509 #define M_THROTTLE_THRESHOLD_LP    0xfffU
2513 #define A_SGE_INT_ENABLE6 0x112c
2514 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2517 #define M_DBP_FETCH_THRESHOLD_FL    0xfU
2522 #define M_DBP_FETCH_THRESHOLD_HP    0xfU
2527 #define M_DBP_FETCH_THRESHOLD_LP    0xfffU
2547 #define S_DBP_FETCH_THRESHOLD_EN0    0
2551 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2554 #define M_DBP_FETCH_THRESHOLD_IQ1    0xffffU
2558 #define S_DBP_FETCH_THRESHOLD_IQ0    0
2559 #define M_DBP_FETCH_THRESHOLD_IQ0    0xffffU
2563 #define A_SGE_DBVFIFO_BADDR 0x1138
2564 #define A_SGE_DBVFIFO_SIZE 0x113c
2567 #define M_DBVFIFO_SIZE    0xfffU
2571 #define S_T6_DBVFIFO_SIZE    0
2572 #define M_T6_DBVFIFO_SIZE    0x1fffU
2576 #define A_SGE_DBFIFO_STATUS3 0x1140
2587 #define M_FL_INT_THRESH_LOW    0xfU
2592 #define M_HP_INT_THRESH_LOW    0xfU
2596 #define S_LP_INT_THRESH_LOW    0
2597 #define M_LP_INT_THRESH_LOW    0xfffU
2601 #define A_SGE_CHANGESET 0x1144
2602 #define A_SGE_PC_RSP_ERROR 0x1148
2603 #define A_SGE_TBUF_CONTROL 0x114c
2606 #define M_DBPTBUFRSV1    0x1ffU
2610 #define S_DBPTBUFRSV0    0
2611 #define M_DBPTBUFRSV0    0x1ffU
2615 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2616 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2617 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2618 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2619 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2620 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2621 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2622 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2623 #define A_SGE_CTXT_CMD 0x11fc
2630 #define M_CTXTOP    0x3U
2635 #define M_CTXTTYPE    0x3U
2639 #define S_CTXTQID    0
2640 #define M_CTXTQID    0x1ffffU
2644 #define A_SGE_CTXT_DATA0 0x1200
2645 #define A_SGE_CTXT_DATA1 0x1204
2646 #define A_SGE_CTXT_DATA2 0x1208
2647 #define A_SGE_CTXT_DATA3 0x120c
2648 #define A_SGE_CTXT_DATA4 0x1210
2649 #define A_SGE_CTXT_DATA5 0x1214
2650 #define A_SGE_CTXT_DATA6 0x1218
2651 #define A_SGE_CTXT_DATA7 0x121c
2652 #define A_SGE_CTXT_MASK0 0x1220
2653 #define A_SGE_CTXT_MASK1 0x1224
2654 #define A_SGE_CTXT_MASK2 0x1228
2655 #define A_SGE_CTXT_MASK3 0x122c
2656 #define A_SGE_CTXT_MASK4 0x1230
2657 #define A_SGE_CTXT_MASK5 0x1234
2658 #define A_SGE_CTXT_MASK6 0x1238
2659 #define A_SGE_CTXT_MASK7 0x123c
2660 #define A_SGE_QBASE_MAP0 0x1240
2663 #define M_EGRESS0_SIZE    0x1fU
2668 #define M_EGRESS1_SIZE    0x1fU
2673 #define M_INGRESS0_SIZE    0x1fU
2677 #define A_SGE_QBASE_MAP1 0x1244
2679 #define S_EGRESS0_BASE    0
2680 #define M_EGRESS0_BASE    0x1ffffU
2684 #define A_SGE_QBASE_MAP2 0x1248
2686 #define S_EGRESS1_BASE    0
2687 #define M_EGRESS1_BASE    0x1ffffU
2691 #define A_SGE_QBASE_MAP3 0x124c
2694 #define M_INGRESS1_BASE_256VF    0xffffU
2698 #define S_INGRESS0_BASE    0
2699 #define M_INGRESS0_BASE    0xffffU
2703 #define A_SGE_QBASE_INDEX 0x1250
2705 #define S_QIDX    0
2706 #define M_QIDX    0x1ffU
2710 #define A_SGE_CONM_CTRL2 0x1254
2713 #define M_FLMTHRESHPACK    0x7fU
2717 #define S_FLMTHRESH    0
2718 #define M_FLMTHRESH    0x7fU
2722 #define A_SGE_DEBUG_CONM 0x1258
2725 #define M_MPS_CH_CNG    0xffffU
2730 #define M_TP_CH_CNG    0x3U
2735 #define M_ST_CONG    0x3U
2743 #define S_LAST_QID    0
2744 #define M_LAST_QID    0x3ffU
2748 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
2758 #define S_DB_GTS_QID    0
2759 #define M_DB_GTS_QID    0x1ffffU
2763 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
2764 #define A_SGE_DBG_QUEUE_STAT0 0x1264
2765 #define A_SGE_DBG_QUEUE_STAT1 0x1268
2766 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
2767 #define A_SGE_DBG_DB_PKT_CNT 0x1270
2768 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
2769 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2772 #define M_CIM_WM    0x3U
2777 #define M_DEBUG_UP_SOP_CNT    0xfU
2782 #define M_DEBUG_UP_EOP_CNT    0xfU
2787 #define M_DEBUG_CIM_SOP1_CNT    0xfU
2792 #define M_DEBUG_CIM_EOP1_CNT    0xfU
2797 #define M_DEBUG_CIM_SOP0_CNT    0xfU
2801 #define S_DEBUG_CIM_EOP0_CNT    0
2802 #define M_DEBUG_CIM_EOP0_CNT    0xfU
2807 #define M_DEBUG_BAR2_SOP_CNT    0xfU
2812 #define M_DEBUG_BAR2_EOP_CNT    0xfU
2816 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2819 #define M_DEBUG_T_RX_SOP1_CNT    0xfU
2824 #define M_DEBUG_T_RX_EOP1_CNT    0xfU
2829 #define M_DEBUG_T_RX_SOP0_CNT    0xfU
2834 #define M_DEBUG_T_RX_EOP0_CNT    0xfU
2839 #define M_DEBUG_U_RX_SOP1_CNT    0xfU
2844 #define M_DEBUG_U_RX_EOP1_CNT    0xfU
2849 #define M_DEBUG_U_RX_SOP0_CNT    0xfU
2853 #define S_DEBUG_U_RX_EOP0_CNT    0
2854 #define M_DEBUG_U_RX_EOP0_CNT    0xfU
2858 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2861 #define M_DEBUG_UD_RX_SOP3_CNT    0xfU
2866 #define M_DEBUG_UD_RX_EOP3_CNT    0xfU
2871 #define M_DEBUG_UD_RX_SOP2_CNT    0xfU
2876 #define M_DEBUG_UD_RX_EOP2_CNT    0xfU
2881 #define M_DEBUG_UD_RX_SOP1_CNT    0xfU
2886 #define M_DEBUG_UD_RX_EOP1_CNT    0xfU
2891 #define M_DEBUG_UD_RX_SOP0_CNT    0xfU
2895 #define S_DEBUG_UD_RX_EOP0_CNT    0
2896 #define M_DEBUG_UD_RX_EOP0_CNT    0xfU
2901 #define M_DBG_TBUF_USED1    0x1ffU
2905 #define S_DBG_TBUF_USED0    0
2906 #define M_DBG_TBUF_USED0    0x1ffU
2910 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2913 #define M_DEBUG_U_TX_SOP3_CNT    0xfU
2918 #define M_DEBUG_U_TX_EOP3_CNT    0xfU
2923 #define M_DEBUG_U_TX_SOP2_CNT    0xfU
2928 #define M_DEBUG_U_TX_EOP2_CNT    0xfU
2933 #define M_DEBUG_U_TX_SOP1_CNT    0xfU
2938 #define M_DEBUG_U_TX_EOP1_CNT    0xfU
2943 #define M_DEBUG_U_TX_SOP0_CNT    0xfU
2947 #define S_DEBUG_U_TX_EOP0_CNT    0
2948 #define M_DEBUG_U_TX_EOP0_CNT    0xfU
2952 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
2955 #define M_WR_DEQ_CNT    0xfU
2960 #define M_WR_ENQ_CNT    0xfU
2965 #define M_FL_DEQ_CNT    0xfU
2969 #define S_FL_ENQ_CNT    0
2970 #define M_FL_ENQ_CNT    0xfU
2974 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2977 #define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
2982 #define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
2987 #define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
2992 #define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
2997 #define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
3002 #define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
3007 #define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
3011 #define S_DEBUG_PC_REQ_EOP0_CNT    0
3012 #define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
3016 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
3019 #define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
3024 #define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
3029 #define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
3034 #define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
3039 #define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
3044 #define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
3049 #define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
3053 #define S_DEBUG_PD_RDREQ_EOP0_CNT    0
3054 #define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
3058 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
3061 #define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
3066 #define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
3071 #define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
3076 #define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
3081 #define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
3086 #define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
3091 #define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
3095 #define S_DEBUG_PD_RDRSP_EOP0_CNT    0
3096 #define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
3100 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
3103 #define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
3108 #define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
3113 #define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
3118 #define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
3123 #define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
3128 #define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
3133 #define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
3137 #define S_DEBUG_PD_WRREQ_EOP0_CNT    0
3138 #define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
3143 #define M_DEBUG_PC_RSP_SOP_CNT    0xfU
3148 #define M_DEBUG_PC_RSP_EOP_CNT    0xfU
3153 #define M_DEBUG_PC_REQ_SOP_CNT    0xfU
3158 #define M_DEBUG_PC_REQ_EOP_CNT    0xfU
3162 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
3169 #define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
3174 #define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
3215 #define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
3220 #define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
3225 #define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
3229 #define S_DEBUG_PD_WRREQ_INT0_CNT    0
3230 #define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
3242 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
3245 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
3250 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3255 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3260 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3265 #define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3270 #define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3275 #define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3279 #define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3280 #define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3284 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3287 #define M_DEBUG_T_RXAFULL_D    0x3U
3292 #define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3297 #define M_DEBUG_PD_RDREQAFULL_D    0xfU
3302 #define M_DEBUG_PD_WRREQAFULL_D    0xfU
3307 #define M_DEBUG_PC_RSPAFULL_D    0x7U
3312 #define M_DEBUG_PC_REQAFULL_D    0x7U
3317 #define M_DEBUG_U_TXAFULL_D    0xfU
3322 #define M_DEBUG_UD_RXAFULL_D    0xfU
3327 #define M_DEBUG_U_RXAFULL_D    0x3U
3331 #define S_DEBUG_CIM_AFULL_D    0
3332 #define M_DEBUG_CIM_AFULL_D    0x3U
3337 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3370 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3403 #define M_T6_DEBUG_T_RXAFULL_D    0x3U
3408 #define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3420 #define S_T6_DEBUG_CIM_AFULL_D    0
3424 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3443 #define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3448 #define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3469 #define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3473 #define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3474 #define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3478 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3481 #define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3486 #define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3491 #define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3496 #define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3501 #define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3506 #define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3511 #define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3515 #define S_DEBUG_PC_REQ_EOP2_CNT    0
3516 #define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3521 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3525 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3526 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3530 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3531 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3532 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3533 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3536 #define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3541 #define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3546 #define M_DEBUG_ST_IMSG_CTXT    0x7U
3551 #define M_DEBUG_ST_IMSG    0x1fU
3556 #define M_DEBUG_ST_IDMA1_IALN    0x3U
3561 #define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3566 #define M_DEBUG_ST_IDMA0_IALN    0x3U
3570 #define S_DEBUG_ST_IDMA0_IDMA_SM    0
3571 #define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
3583 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
3586 #define M_DEBUG_ITP_EMPTY    0x3fU
3591 #define M_DEBUG_ITP_EXPIRED    0x3fU
3607 #define S_DEBUG_ITP_EVR_STATE    0
3608 #define M_DEBUG_ITP_EVR_STATE    0x7U
3612 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
3615 #define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
3620 #define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
3625 #define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
3630 #define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
3635 #define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
3639 #define S_DEBUG_ST_DBP_THREAD0_MAIN    0
3640 #define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
3645 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
3649 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
3652 #define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
3661 #define M_DEBUG_ST_DBP_CTXT    0x7U
3666 #define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
3670 #define S_DEBUG_ST_DBP_THREAD3_MAIN    0
3671 #define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
3675 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
3678 #define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
3683 #define M_DEBUG_ST_EDMA3_ALIGN    0x3U
3688 #define M_DEBUG_ST_EDMA3_REQ    0x7U
3693 #define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
3698 #define M_DEBUG_ST_EDMA2_ALIGN    0x3U
3703 #define M_DEBUG_ST_EDMA2_REQ    0x7U
3708 #define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
3713 #define M_DEBUG_ST_EDMA1_ALIGN    0x3U
3718 #define M_DEBUG_ST_EDMA1_REQ    0x7U
3723 #define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
3728 #define M_DEBUG_ST_EDMA0_ALIGN    0x3U
3732 #define S_DEBUG_ST_EDMA0_REQ    0
3733 #define M_DEBUG_ST_EDMA0_REQ    0x7U
3737 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
3740 #define M_DEBUG_ST_FLM_DBPTR    0x3U
3745 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
3750 #define M_DEBUG_FLM_CACHE_AGENT    0x7U
3755 #define M_DEBUG_ST_FLM_CACHE    0xfU
3763 #define S_DEBUG_FLM_DBPTR_QID    0
3764 #define M_DEBUG_FLM_DBPTR_QID    0xfffU
3768 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
3771 #define M_THREAD_ST_MAIN    0x3fU
3776 #define M_THREAD_ST_CIMFL    0xfU
3781 #define M_THREAD_CMDOP    0xfU
3785 #define S_THREAD_QID    0
3786 #define M_THREAD_QID    0x1ffffU
3790 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
3792 #define S_DEBUG_DBP_THREAD0_QID    0
3793 #define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
3797 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
3799 #define S_DEBUG_DBP_THREAD1_QID    0
3800 #define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
3804 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
3806 #define S_DEBUG_DBP_THREAD2_QID    0
3807 #define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
3811 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
3813 #define S_DEBUG_DBP_THREAD3_QID    0
3814 #define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
3818 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
3821 #define M_DEBUG_IMSG_CPL    0xffU
3825 #define S_DEBUG_IMSG_QID    0
3826 #define M_DEBUG_IMSG_QID    0xffffU
3830 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
3833 #define M_DEBUG_IDMA1_QID    0xffffU
3837 #define S_DEBUG_IDMA0_QID    0
3838 #define M_DEBUG_IDMA0_QID    0xffffU
3842 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
3845 #define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
3849 #define S_DEBUG_IDMA0_FLM_REQ_QID    0
3850 #define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
3854 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
3855 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
3856 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
3857 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
3860 #define M_EGRESS_LOG2SIZE    0x1fU
3865 #define M_EGRESS_BASE    0x1ffffU
3870 #define M_INGRESS2_LOG2SIZE    0x1fU
3874 #define S_INGRESS1_LOG2SIZE    0
3875 #define M_INGRESS1_LOG2SIZE    0x1fU
3880 #define M_EGRESS_SIZE    0x1fU
3885 #define M_INGRESS2_SIZE    0x1fU
3889 #define S_INGRESS1_SIZE    0
3890 #define M_INGRESS1_SIZE    0x1fU
3894 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
3897 #define M_PFIQSPERPAGE    0xfU
3902 #define M_PFEQSPERPAGE    0xfU
3907 #define M_PFWCQSPERPAGE    0xfU
3916 #define M_PFMAXWCSIZE    0x3U
3920 #define S_PFWCOFFSET    0
3921 #define M_PFWCOFFSET    0x1ffffU
3925 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
3928 #define M_INGRESS2_BASE    0xffffU
3932 #define S_INGRESS1_BASE    0
3933 #define M_INGRESS1_BASE    0xffffU
3937 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
3940 #define M_VFIQSPERPAGE    0xfU
3945 #define M_VFEQSPERPAGE    0xfU
3950 #define M_VFWCQSPERPAGE    0xfU
3959 #define M_VFMAXWCSIZE    0x3U
3963 #define S_VFWCOFFSET    0
3964 #define M_VFWCOFFSET    0x1ffffU
3968 #define A_SGE_LA_RDPTR_0 0x1800
3969 #define A_SGE_LA_RDDATA_0 0x1804
3970 #define A_SGE_LA_WRPTR_0 0x1808
3971 #define A_SGE_LA_RESERVED_0 0x180c
3972 #define A_SGE_LA_RDPTR_1 0x1810
3973 #define A_SGE_LA_RDDATA_1 0x1814
3974 #define A_SGE_LA_WRPTR_1 0x1818
3975 #define A_SGE_LA_RESERVED_1 0x181c
3976 #define A_SGE_LA_RDPTR_2 0x1820
3977 #define A_SGE_LA_RDDATA_2 0x1824
3978 #define A_SGE_LA_WRPTR_2 0x1828
3979 #define A_SGE_LA_RESERVED_2 0x182c
3980 #define A_SGE_LA_RDPTR_3 0x1830
3981 #define A_SGE_LA_RDDATA_3 0x1834
3982 #define A_SGE_LA_WRPTR_3 0x1838
3983 #define A_SGE_LA_RESERVED_3 0x183c
3984 #define A_SGE_LA_RDPTR_4 0x1840
3985 #define A_SGE_LA_RDDATA_4 0x1844
3986 #define A_SGE_LA_WRPTR_4 0x1848
3987 #define A_SGE_LA_RESERVED_4 0x184c
3988 #define A_SGE_LA_RDPTR_5 0x1850
3989 #define A_SGE_LA_RDDATA_5 0x1854
3990 #define A_SGE_LA_WRPTR_5 0x1858
3991 #define A_SGE_LA_RESERVED_5 0x185c
3992 #define A_SGE_LA_RDPTR_6 0x1860
3993 #define A_SGE_LA_RDDATA_6 0x1864
3994 #define A_SGE_LA_WRPTR_6 0x1868
3995 #define A_SGE_LA_RESERVED_6 0x186c
3996 #define A_SGE_LA_RDPTR_7 0x1870
3997 #define A_SGE_LA_RDDATA_7 0x1874
3998 #define A_SGE_LA_WRPTR_7 0x1878
3999 #define A_SGE_LA_RESERVED_7 0x187c
4000 #define A_SGE_LA_RDPTR_8 0x1880
4001 #define A_SGE_LA_RDDATA_8 0x1884
4002 #define A_SGE_LA_WRPTR_8 0x1888
4003 #define A_SGE_LA_RESERVED_8 0x188c
4004 #define A_SGE_LA_RDPTR_9 0x1890
4005 #define A_SGE_LA_RDDATA_9 0x1894
4006 #define A_SGE_LA_WRPTR_9 0x1898
4007 #define A_SGE_LA_RESERVED_9 0x189c
4008 #define A_SGE_LA_RDPTR_10 0x18a0
4009 #define A_SGE_LA_RDDATA_10 0x18a4
4010 #define A_SGE_LA_WRPTR_10 0x18a8
4011 #define A_SGE_LA_RESERVED_10 0x18ac
4012 #define A_SGE_LA_RDPTR_11 0x18b0
4013 #define A_SGE_LA_RDDATA_11 0x18b4
4014 #define A_SGE_LA_WRPTR_11 0x18b8
4015 #define A_SGE_LA_RESERVED_11 0x18bc
4016 #define A_SGE_LA_RDPTR_12 0x18c0
4017 #define A_SGE_LA_RDDATA_12 0x18c4
4018 #define A_SGE_LA_WRPTR_12 0x18c8
4019 #define A_SGE_LA_RESERVED_12 0x18cc
4020 #define A_SGE_LA_RDPTR_13 0x18d0
4021 #define A_SGE_LA_RDDATA_13 0x18d4
4022 #define A_SGE_LA_WRPTR_13 0x18d8
4023 #define A_SGE_LA_RESERVED_13 0x18dc
4024 #define A_SGE_LA_RDPTR_14 0x18e0
4025 #define A_SGE_LA_RDDATA_14 0x18e4
4026 #define A_SGE_LA_WRPTR_14 0x18e8
4027 #define A_SGE_LA_RESERVED_14 0x18ec
4028 #define A_SGE_LA_RDPTR_15 0x18f0
4029 #define A_SGE_LA_RDDATA_15 0x18f4
4030 #define A_SGE_LA_WRPTR_15 0x18f8
4031 #define A_SGE_LA_RESERVED_15 0x18fc
4034 #define PCIE_BASE_ADDR 0x3000
4036 #define A_PCIE_PF_CFG 0x40
4051 #define M_AIVEC    0x3ffU
4056 #define M_INTXTYPE    0x3U
4064 #define S_CLIDECEN    0
4068 #define A_PCIE_PF_CLI 0x44
4069 #define A_PCIE_PF_GEN_MSG 0x48
4071 #define S_MSGTYPE    0
4072 #define M_MSGTYPE    0xffU
4076 #define A_PCIE_PF_EXPROM_OFST 0x4c
4079 #define M_OFFSET    0x3fffU
4083 #define A_PCIE_INT_ENABLE 0x3000
4205 #define S_MSIADDRLPERR    0
4293 #define S_MSTGRPPERR    0
4297 #define A_PCIE_INT_CAUSE 0x3004
4298 #define A_PCIE_PERR_ENABLE 0x3008
4299 #define A_PCIE_PERR_INJECT 0x300c
4301 #define S_IDE    0
4306 #define M_MEMSEL_PCIE    0x1fU
4310 #define A_PCIE_NONFAT_ERR 0x3010
4348 #define S_CFGSNP    0
4444 #define A_PCIE_CFG 0x3014
4447 #define M_CFGDMAXPYLDSZRX    0x7U
4452 #define M_CFGDMAXPYLDSZTX    0x7U
4457 #define M_CFGDMAXRDREQSZ    0x7U
4506 #define M_AI_TCVAL    0x7U
4530 #define S_LINKDNRSTEN    0
4539 #define M_DIAGCTRLBUS    0x7U
4552 #define M_CFGDMAXPYLDSZ    0x7U
4565 #define M_T5VPDREQPROTECT    0x3U
4589 #define A_PCIE_DMA_CTRL 0x3018
4595 #define A_PCIE_CFG2 0x3018
4598 #define M_VPDTIMER    0xffffU
4603 #define M_BAR2TIMER    0xfffU
4611 #define S_TOTMAXTAG    0
4612 #define M_TOTMAXTAG    0x3U
4616 #define S_T6_TOTMAXTAG    0
4617 #define M_T6_TOTMAXTAG    0x7U
4621 #define A_PCIE_DMA_CFG 0x301c
4624 #define M_MAXPYLDSIZE    0x7U
4629 #define M_MAXRDREQSIZE    0x7U
4634 #define M_DMA_MAXRSPCNT    0x1ffU
4639 #define M_DMA_MAXREQCNT    0xffU
4643 #define S_MAXTAG    0
4644 #define M_MAXTAG    0x7fU
4648 #define A_PCIE_CFG3 0x301c
4655 #define M_FLRPNDCPLMODE    0x3U
4667 #define S_DMADCASTFIRSTONLY    0
4671 #define A_PCIE_DMA_STAT 0x3020
4674 #define M_STATEREQ    0xfU
4679 #define M_DMA_RSPCNT    0xfffU
4684 #define M_STATEAREQ    0x7U
4692 #define S_DMA_REQCNT    0
4693 #define M_DMA_REQCNT    0x7ffU
4697 #define A_PCIE_CFG4 0x3020
4715 #define S_GENPME    0
4716 #define M_GENPME    0xffU
4720 #define A_PCIE_CFG5 0x3024
4730 #define S_HOLDCPLENTERINGL1    0
4734 #define A_PCIE_CFG6 0x3028
4737 #define M_PERSTTIMERCOUNT    0x3fffU
4745 #define S_PERSTTIMER    0
4746 #define M_PERSTTIMER    0xfU
4750 #define A_PCIE_CFG7 0x302c
4751 #define A_PCIE_CMD_CTRL 0x303c
4752 #define A_PCIE_CMD_CFG 0x3040
4755 #define M_MAXRSPCNT    0xfU
4760 #define M_MAXREQCNT    0x1fU
4764 #define A_PCIE_CMD_STAT 0x3044
4767 #define M_RSPCNT    0x7fU
4771 #define S_REQCNT    0
4772 #define M_REQCNT    0xffU
4776 #define A_PCIE_HMA_CTRL 0x3050
4779 #define M_IPLTSSM    0xfU
4784 #define M_IPCONFIGDOWN    0x7U
4788 #define A_PCIE_HMA_CFG 0x3054
4791 #define M_HMA_MAXRSPCNT    0x1fU
4795 #define A_PCIE_HMA_STAT 0x3058
4798 #define M_HMA_RSPCNT    0xffU
4802 #define A_PCIE_PIO_FIFO_CFG 0x305c
4805 #define M_CPLCONFIG    0xffffU
4821 #define S_FORCEPROGRESSCNT    0
4822 #define M_FORCEPROGRESSCNT    0x3ffU
4826 #define A_PCIE_CFG_SPACE_REQ 0x3060
4841 #define M_BUS    0xffU
4846 #define M_DEVICE    0x1fU
4851 #define M_FUNCTION    0x7U
4856 #define M_EXTREGISTER    0xfU
4860 #define S_REGISTER    0
4861 #define M_REGISTER    0xffU
4870 #define M_WRBE    0xfU
4879 #define M_CFG_SPACE_RVF    0x7fU
4884 #define M_CFG_SPACE_PF    0x7U
4901 #define M_T6_WRBE    0xfU
4910 #define M_T6_CFG_SPACE_RVF    0xffU
4914 #define A_PCIE_CFG_SPACE_DATA 0x3064
4915 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
4918 #define M_PCIEOFST    0x3fffffU
4923 #define M_BIR    0x3U
4927 #define S_WINDOW    0
4928 #define M_WINDOW    0xffU
4932 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
4935 #define M_MEMOFST    0x1ffffffU
4939 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
4942 #define M_MBOXPCIEOFST    0x3ffffffU
4947 #define M_MBOXBIR    0x3U
4951 #define S_MBOXWIN    0
4952 #define M_MBOXWIN    0x3U
4956 #define A_PCIE_MAILBOX_OFFSET 0x30ac
4957 #define A_PCIE_MA_CTRL 0x30b0
4964 #define M_MA_MAXRSPCNT    0x1fU
4969 #define M_MA_MAXREQCNT    0x1fU
4978 #define M_MA_MAXPYLDSIZE    0x7U
4983 #define M_MA_MAXRDREQSIZE    0x7U
4987 #define S_MA_MAXTAG    0
4988 #define M_MA_MAXTAG    0x1fU
4993 #define M_T5_MA_MAXREQCNT    0x7fU
4998 #define M_MA_MAXREQSIZE    0x7U
5002 #define A_PCIE_MA_SYNC 0x30b4
5003 #define A_PCIE_FW 0x30b8
5004 #define A_PCIE_FW_PF 0x30bc
5005 #define A_PCIE_PIO_PAUSE 0x30dc
5012 #define M_PIOPAUSETIME    0xffffffU
5016 #define S_PIOPAUSE    0
5028 #define A_PCIE_SYS_CFG_READY 0x30e0
5029 #define A_PCIE_MA_STAT 0x30e0
5030 #define A_PCIE_STATIC_CFG1 0x30e4
5041 #define M_IN_RD_CPLSIZE    0x7U
5046 #define M_IN_RD_BUFMODE    0x3U
5051 #define M_GBIF_NPTRANS_TOT    0x3U
5056 #define M_IN_PDAT_TOT    0x7U
5061 #define M_PCIE_NPTRANS_TOT    0x7U
5066 #define M_OUT_PDAT_TOT    0x7U
5071 #define M_GBIF_MAX_WRSIZE    0x7U
5076 #define M_GBIF_MAX_RDSIZE    0x7U
5080 #define S_PCIE_MAX_RDSIZE    0
5081 #define M_PCIE_MAX_RDSIZE    0x7U
5089 #define A_PCIE_STATIC_CFG2 0x30e8
5092 #define M_PL_CONTROL    0xffffU
5096 #define S_STATIC_SPARE3    0
5097 #define M_STATIC_SPARE3    0x3fffU
5101 #define A_PCIE_DBG_INDIR_REQ 0x30ec
5112 #define M_POINTER    0xffffU
5116 #define S_SELECT    0
5117 #define M_SELECT    0xfU
5121 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
5122 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
5123 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
5124 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
5125 #define A_PCIE_FUNC_INT_CFG 0x3100
5128 #define M_PBAOFST    0xfU
5133 #define M_TABOFST    0xfU
5138 #define M_VECNUM    0x3ffU
5142 #define S_VECBASE    0
5143 #define M_VECBASE    0x7ffU
5147 #define A_PCIE_FUNC_CTL_STAT 0x3104
5162 #define M_PNDTXNS    0x3ffU
5170 #define S_PFNUM    0
5171 #define M_PFNUM    0x7U
5175 #define A_PCIE_PF_INT_CFG 0x3140
5176 #define A_PCIE_PF_INT_CFG2 0x3144
5177 #define A_PCIE_VF_INT_CFG 0x3180
5178 #define A_PCIE_VF_INT_CFG2 0x3184
5179 #define A_PCIE_PF_MSI_EN 0x35a8
5181 #define S_PFMSIEN_7_0    0
5182 #define M_PFMSIEN_7_0    0xffU
5186 #define A_PCIE_VF_MSI_EN_0 0x35ac
5187 #define A_PCIE_VF_MSI_EN_1 0x35b0
5188 #define A_PCIE_VF_MSI_EN_2 0x35b4
5189 #define A_PCIE_VF_MSI_EN_3 0x35b8
5190 #define A_PCIE_PF_MSIX_EN 0x35bc
5192 #define S_PFMSIXEN_7_0    0
5193 #define M_PFMSIXEN_7_0    0xffU
5197 #define A_PCIE_VF_MSIX_EN_0 0x35c0
5198 #define A_PCIE_VF_MSIX_EN_1 0x35c4
5199 #define A_PCIE_VF_MSIX_EN_2 0x35c8
5200 #define A_PCIE_VF_MSIX_EN_3 0x35cc
5201 #define A_PCIE_FID_VFID_SEL 0x35ec
5203 #define S_FID_VFID_SEL_SELECT    0
5204 #define M_FID_VFID_SEL_SELECT    0x3U
5208 #define A_PCIE_FID_VFID 0x3600
5211 #define M_FID_VFID_SELECT    0x3U
5220 #define M_FID_VFID_VFID    0xffU
5225 #define M_FID_VFID_TC    0x7U
5234 #define M_FID_VFID_PF    0x7U
5238 #define S_FID_VFID_RVF    0
5239 #define M_FID_VFID_RVF    0x7fU
5244 #define M_T6_FID_VFID_VFID    0x1ffU
5249 #define M_T6_FID_VFID_TC    0x7U
5258 #define M_T6_FID_VFID_PF    0x7U
5262 #define S_T6_FID_VFID_RVF    0
5263 #define M_T6_FID_VFID_RVF    0xffU
5267 #define A_PCIE_FID 0x3900
5274 #define M_TC    0x7U
5278 #define S_FUNC    0
5279 #define M_FUNC    0xffU
5283 #define A_PCIE_COOKIE_STAT 0x5600
5286 #define M_COOKIEB    0x3ffU
5290 #define S_COOKIEA    0
5291 #define M_COOKIEA    0x3ffU
5295 #define A_PCIE_FLR_PIO 0x5620
5298 #define M_RCVDBAR2COOKIE    0xffU
5303 #define M_RCVDMARSPCOOKIE    0xffU
5308 #define M_RCVDPIORSPCOOKIE    0xffU
5312 #define S_EXPDCOOKIE    0
5313 #define M_EXPDCOOKIE    0xffU
5317 #define A_PCIE_FLR_PIO2 0x5624
5320 #define M_RCVDMAREQCOOKIE    0xffU
5325 #define M_RCVDPIOREQCOOKIE    0xffU
5330 #define M_RCVDVDMRXCOOKIE    0xffU
5335 #define M_RCVDVDMTXCOOKIE    0xffU
5340 #define M_T6_RCVDMAREQCOOKIE    0xffU
5344 #define S_T6_RCVDPIOREQCOOKIE    0
5345 #define M_T6_RCVDPIOREQCOOKIE    0xffU
5349 #define A_PCIE_VC0_CDTS0 0x56cc
5352 #define M_CPLD0    0xfffU
5357 #define M_PH0    0xffU
5361 #define S_PD0    0
5362 #define M_PD0    0xfffU
5366 #define A_PCIE_VC0_CDTS1 0x56d0
5369 #define M_CPLH0    0xffU
5374 #define M_NPH0    0xffU
5378 #define S_NPD0    0
5379 #define M_NPD0    0xfffU
5383 #define A_PCIE_VC1_CDTS0 0x56d4
5386 #define M_CPLD1    0xfffU
5391 #define M_PH1    0xffU
5395 #define S_PD1    0
5396 #define M_PD1    0xfffU
5400 #define A_PCIE_VC1_CDTS1 0x56d8
5403 #define M_CPLH1    0xffU
5408 #define M_NPH1    0xffU
5412 #define S_NPD1    0
5413 #define M_NPD1    0xfffU
5417 #define A_PCIE_FLR_PF_STATUS 0x56dc
5418 #define A_PCIE_FLR_VF0_STATUS 0x56e0
5419 #define A_PCIE_FLR_VF1_STATUS 0x56e4
5420 #define A_PCIE_FLR_VF2_STATUS 0x56e8
5421 #define A_PCIE_FLR_VF3_STATUS 0x56ec
5422 #define A_PCIE_STAT 0x56f4
5425 #define M_PM_STATUS    0xffU
5430 #define M_PM_CURRENTSTATE    0x7U
5439 #define M_STATECFGINITF    0x7fU
5443 #define S_STATECFGINIT    0
5444 #define M_STATECFGINIT    0xfU
5453 #define M_STATECFGINITF_PCIE    0xffU
5457 #define S_STATECFGINIT_PCIE    0
5458 #define M_STATECFGINIT_PCIE    0xfU
5462 #define A_PCIE_CRS 0x56f8
5464 #define S_CRS_ENABLE    0
5468 #define A_PCIE_LTSSM 0x56fc
5470 #define S_LTSSM_ENABLE    0
5478 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
5481 #define M_REPLAY_TIME_LIMIT    0xffffU
5485 #define S_ACK_LATENCY_TIMER_LIMIT    0
5486 #define M_ACK_LATENCY_TIMER_LIMIT    0xffffU
5490 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
5491 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
5494 #define M_LOW_POWER_ENTRANCE_COUNT    0xffU
5499 #define M_LINK_STATE    0x3fU
5507 #define S_LINK_NUMBER    0
5508 #define M_LINK_NUMBER    0xffU
5512 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
5519 #define M_L1_ENTRANCE_LATENCY    0x7U
5524 #define M_L0S_ENTRANCE_LATENCY    0x7U
5529 #define M_COMMON_CLOCK_N_FTS    0xffU
5534 #define M_N_FTS    0xffU
5538 #define S_ACK_FREQUENCY    0
5539 #define M_ACK_FREQUENCY    0xffU
5543 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
5554 #define M_LINK_MODE_ENABLE    0x3fU
5578 #define S_VENDOR_SPECIFIC_DLLP_REQUEST    0
5582 #define A_PCIE_CORE_LANE_SKEW 0x5714
5596 #define S_INSERT_TXSKEW    0
5597 #define M_INSERT_TXSKEW    0xffffffU
5601 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
5604 #define M_FLOW_CONTROL_TIMER_MODIFIER    0x1fU
5609 #define M_ACK_NAK_TIMER_MODIFIER    0x1fU
5614 #define M_REPLAY_TIMER_MODIFIER    0x1fU
5618 #define S_MAXFUNC    0
5619 #define M_MAXFUNC    0x7U
5623 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
5626 #define M_MASK_RADM_FILTER    0xffffU
5634 #define S_SKP_INTERVAL    0
5635 #define M_SKP_INTERVAL    0x7ffU
5639 #define A_PCIE_CORE_FILTER_MASK2 0x5720
5640 #define A_PCIE_CORE_DEBUG_0 0x5728
5641 #define A_PCIE_CORE_DEBUG_1 0x572c
5642 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
5645 #define M_TXPH_FC    0xffU
5649 #define S_TXPD_FC    0
5650 #define M_TXPD_FC    0xfffU
5654 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
5657 #define M_TXNPH_FC    0xffU
5661 #define S_TXNPD_FC    0
5662 #define M_TXNPD_FC    0xfffU
5666 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
5669 #define M_TXCPLH_FC    0xffU
5673 #define S_TXCPLD_FC    0
5674 #define M_TXCPLD_FC    0xfffU
5678 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
5688 #define S_RXTLP_FC_NOT_RETURNED    0
5692 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
5695 #define M_VC3_WRR    0xffU
5700 #define M_VC2_WRR    0xffU
5705 #define M_VC1_WRR    0xffU
5709 #define S_VC0_WRR    0
5710 #define M_VC0_WRR    0xffU
5714 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
5717 #define M_VC7_WRR    0xffU
5722 #define M_VC6_WRR    0xffU
5727 #define M_VC5_WRR    0xffU
5731 #define S_VC4_WRR    0
5732 #define M_VC4_WRR    0xffU
5736 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
5747 #define M_VC0_PTLP_QUEUE_MODE    0x7U
5752 #define M_VC0_PH_CREDITS    0xffU
5756 #define S_VC0_PD_CREDITS    0
5757 #define M_VC0_PD_CREDITS    0xfffU
5761 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
5764 #define M_VC0_NPTLP_QUEUE_MODE    0x7U
5769 #define M_VC0_NPH_CREDITS    0xffU
5773 #define S_VC0_NPD_CREDITS    0
5774 #define M_VC0_NPD_CREDITS    0xfffU
5778 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
5781 #define M_VC0_CPLTLP_QUEUE_MODE    0x7U
5786 #define M_VC0_CPLH_CREDITS    0xffU
5790 #define S_VC0_CPLD_CREDITS    0
5791 #define M_VC0_CPLD_CREDITS    0xfffU
5795 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
5802 #define M_VC1_PTLP_QUEUE_MODE    0x7U
5807 #define M_VC1_PH_CREDITS    0xffU
5811 #define S_VC1_PD_CREDITS    0
5812 #define M_VC1_PD_CREDITS    0xfffU
5816 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
5819 #define M_VC1_NPTLP_QUEUE_MODE    0x7U
5824 #define M_VC1_NPH_CREDITS    0xffU
5828 #define S_VC1_NPD_CREDITS    0
5829 #define M_VC1_NPD_CREDITS    0xfffU
5833 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
5836 #define M_VC1_CPLTLP_QUEUE_MODE    0x7U
5841 #define M_VC1_CPLH_CREDITS    0xffU
5845 #define S_VC1_CPLD_CREDITS    0
5846 #define M_VC1_CPLD_CREDITS    0xfffU
5850 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
5869 #define M_NUM_LANES    0x1ffU
5873 #define S_NFTS_GEN2_3    0
5874 #define M_NFTS_GEN2_3    0xffU
5883 #define M_T6_NUM_LANES    0x1fU
5887 #define A_PCIE_CORE_PHY_STATUS 0x5810
5888 #define A_PCIE_CORE_PHY_CONTROL 0x5814
5889 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
5919 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
5922 #define M_FULL_SWING    0x3fU
5926 #define S_LOW_FREQUENCY    0
5927 #define M_LOW_FREQUENCY    0x3fU
5931 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
5934 #define M_POSTCURSOR    0x3fU
5939 #define M_CURSOR    0x3fU
5943 #define S_PRECURSOR    0
5944 #define M_PRECURSOR    0x3fU
5948 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
5950 #define S_INDEX    0
5951 #define M_INDEX    0xfU
5955 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
5957 #define S_LEGALITY_STATUS    0
5961 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
5968 #define M_PRESET_REQUEST_VECTOR    0xffffU
5980 #define S_FEEDBACK_MODE    0
5981 #define M_FEEDBACK_MODE    0xfU
5985 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
5988 #define M_WINAPERTURE_CPLUS1    0xfU
5993 #define M_WINAPERTURE_CMINS1    0xfU
5998 #define M_CONVERGENCE_WINDEPTH    0x1fU
6002 #define S_EQMASTERPHASE_MINTIME    0
6003 #define M_EQMASTERPHASE_MINTIME    0x1fU
6007 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
6009 #define S_PIPE_LOOPBACK_EN    0
6017 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
6019 #define S_READONLY_WRITEEN    0
6023 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
6109 #define S_CRMC    0
6110 #define M_CRMC    0x7U
6114 #define A_PCIE_CORE_UTL_STATUS 0x5904
6148 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
6174 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
6196 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
6218 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
6221 #define M_SBRS    0x7U
6226 #define M_OTWS    0x7U
6230 #define A_PCIE_CORE_REVISION_ID 0x5924
6233 #define M_RVID    0xfffU
6238 #define M_BRVN    0xffU
6242 #define A_PCIE_T5_DMA_CFG 0x5940
6245 #define M_T5_DMA_MAXREQCNT    0xffU
6250 #define M_T5_DMA_MAXRDREQSIZE    0x7U
6255 #define M_T5_DMA_MAXRSPCNT    0x1ffU
6263 #define S_MINTAG    0
6264 #define M_MINTAG    0x7fU
6269 #define M_T6_T5_DMA_MAXREQCNT    0x7fU
6274 #define M_T6_T5_DMA_MAXRSPCNT    0xffU
6282 #define S_T6_MINTAG    0
6283 #define M_T6_MINTAG    0xffU
6287 #define A_PCIE_T5_DMA_STAT 0x5944
6290 #define M_DMA_RESPCNT    0xfffU
6295 #define M_DMA_RDREQCNT    0xffU
6299 #define S_DMA_WRREQCNT    0
6300 #define M_DMA_WRREQCNT    0x7ffU
6305 #define M_T6_DMA_RESPCNT    0x3ffU
6310 #define M_T6_DMA_RDREQCNT    0x3fU
6314 #define S_T6_DMA_WRREQCNT    0
6315 #define M_T6_DMA_WRREQCNT    0x1ffU
6319 #define A_PCIE_T5_DMA_STAT2 0x5948
6322 #define M_COOKIECNT    0xfU
6327 #define M_RDSEQNUMUPDCNT    0xfU
6332 #define M_SIREQCNT    0xfU
6341 #define M_WRSOPCNT    0xfU
6345 #define S_RDSOPCNT    0
6346 #define M_RDSOPCNT    0xffU
6350 #define A_PCIE_T5_DMA_STAT3 0x594c
6353 #define M_ATMREQSOPCNT    0xffU
6366 #define M_RSPERRCNT    0xffU
6370 #define S_RSPSOPCNT    0
6371 #define M_RSPSOPCNT    0xffU
6375 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
6378 #define M_OP0H    0xfU
6383 #define M_OP1H    0xfU
6388 #define M_OP2H    0xfU
6392 #define S_OP3H    0
6393 #define M_OP3H    0xfU
6397 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
6400 #define M_OP0D    0x7fU
6405 #define M_OP1D    0x7fU
6410 #define M_OP2D    0x7fU
6414 #define S_OP3D    0
6415 #define M_OP3D    0x7fU
6419 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
6422 #define M_IP0H    0x3fU
6427 #define M_IP1H    0x3fU
6432 #define M_IP2H    0x3fU
6436 #define S_IP3H    0
6437 #define M_IP3H    0x3fU
6441 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
6444 #define M_IP0D    0xffU
6449 #define M_IP1D    0xffU
6454 #define M_IP2D    0xffU
6458 #define S_IP3D    0
6459 #define M_IP3D    0xffU
6463 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
6466 #define M_ON0H    0xfU
6471 #define M_ON1H    0xfU
6476 #define M_ON2H    0xfU
6480 #define S_ON3H    0
6481 #define M_ON3H    0xfU
6485 #define A_PCIE_T5_CMD_CFG 0x5980
6488 #define M_T5_CMD_MAXRDREQSIZE    0x7U
6493 #define M_T5_CMD_MAXRSPCNT    0xffU
6502 #define M_T6_T5_CMD_MAXRSPCNT    0x3fU
6510 #define S_T6_MINTAG    0
6511 #define M_T6_MINTAG    0xffU
6515 #define A_PCIE_T5_CMD_STAT 0x5984
6518 #define M_T5_STAT_RSPCNT    0x7ffU
6523 #define M_RDREQCNT    0x1fU
6528 #define M_T6_T5_STAT_RSPCNT    0xffU
6533 #define M_T6_RDREQCNT    0xfU
6537 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
6540 #define M_IN0H    0x3fU
6545 #define M_IN1H    0x3fU
6550 #define M_IN2H    0x3fU
6554 #define S_IN3H    0
6555 #define M_IN3H    0x3fU
6559 #define A_PCIE_T5_CMD_STAT2 0x5988
6560 #define A_PCIE_T5_CMD_STAT3 0x598c
6561 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
6564 #define M_OC0T    0xffU
6569 #define M_OC1T    0xffU
6574 #define M_OC2T    0xffU
6578 #define S_OC3T    0
6579 #define M_OC3T    0xffU
6583 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
6586 #define M_IC0T    0x3fU
6591 #define M_IC1T    0x3fU
6596 #define M_IC2T    0x3fU
6600 #define S_IC3T    0
6601 #define M_IC3T    0x3fU
6605 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
6652 #define M_RTOS    0xfU
6656 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
6710 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
6760 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
6798 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
6844 #define A_PCIE_T5_HMA_CFG 0x59b0
6847 #define M_HMA_MAXREQCNT    0x1fU
6852 #define M_T5_HMA_MAXRDREQSIZE    0x7U
6857 #define M_T5_HMA_MAXRSPCNT    0x1fU
6862 #define M_T6_HMA_MAXREQCNT    0x7fU
6867 #define M_T6_T5_HMA_MAXRSPCNT    0xffU
6875 #define S_T6_MINTAG    0
6876 #define M_T6_MINTAG    0xffU
6880 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
6926 #define A_PCIE_T5_HMA_STAT 0x59b4
6929 #define M_HMA_RESPCNT    0x1ffU
6934 #define M_HMA_RDREQCNT    0x3fU
6938 #define S_HMA_WRREQCNT    0
6939 #define M_HMA_WRREQCNT    0x1ffU
6944 #define M_T6_HMA_RESPCNT    0x3ffU
6948 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
6994 #define A_PCIE_T5_HMA_STAT2 0x59b8
6995 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
7037 #define A_PCIE_T5_HMA_STAT3 0x59bc
7038 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
7112 #define A_PCIE_CGEN 0x59c0
7186 #define S_STI_SLEEPREQ    0
7190 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
7232 #define A_PCIE_MA_RSP 0x59c4
7235 #define M_TIMERVALUE    0xffffffU
7243 #define S_MARSPTIMEREN    0
7247 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
7269 #define A_PCIE_HPRD 0x59c8
7272 #define M_NPH_CREDITSAVAILVC0    0x3U
7277 #define M_NPD_CREDITSAVAILVC0    0x3U
7282 #define M_NPH_CREDITSAVAILVC1    0x3U
7287 #define M_NPD_CREDITSAVAILVC1    0x3U
7292 #define M_NPH_CREDITSREQUIRED    0x3U
7297 #define M_NPD_CREDITSREQUIRED    0x3U
7302 #define M_REQBURSTCOUNT    0xfU
7307 #define M_REQBURSTFREQUENCY    0xfU
7311 #define S_ENABLEVC1    0
7315 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
7318 #define M_CPM0    0x3U
7323 #define M_CPM1    0x3U
7328 #define M_CPM2    0x3U
7333 #define M_CPM3    0x3U
7338 #define M_CPM4    0x3U
7343 #define M_CPM5    0x3U
7348 #define M_CPM6    0x3U
7353 #define M_CPM7    0x3U
7358 #define M_OPM0    0x3U
7363 #define M_OPM1    0x3U
7368 #define M_OPM2    0x3U
7373 #define M_OPM3    0x3U
7378 #define M_OPM4    0x3U
7383 #define M_OPM5    0x3U
7388 #define M_OPM6    0x3U
7392 #define S_OPM7    0
7393 #define M_OPM7    0x3U
7397 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
7398 #define A_PCIE_PERR_GROUP 0x59d0
7500 #define S_PIOCPL_PLMRSPPERR    0
7524 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
7525 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
7563 #define S_REQUNDERFLRLOGEN    0
7567 #define A_PCIE_RSP_ERR_LOG1 0x59d8
7570 #define M_REQTAG    0x7fU
7575 #define M_CID    0x7U
7580 #define M_CHNUM    0x7U
7585 #define M_BYTELEN    0x1fffU
7590 #define M_REASON    0x7U
7594 #define S_CPLSTATUS    0
7595 #define M_CPLSTATUS    0x7U
7599 #define A_PCIE_RSP_ERR_LOG2 0x59dc
7606 #define M_ADDR10B    0x3ffU
7610 #define S_REQVFID    0
7611 #define M_REQVFID    0xffU
7616 #define M_T6_ADDR10B    0x3ffU
7620 #define S_T6_REQVFID    0
7621 #define M_T6_REQVFID    0x1ffU
7625 #define A_PCIE_CHANGESET 0x59fc
7626 #define A_PCIE_REVISION 0x5a00
7627 #define A_PCIE_PDEBUG_INDEX 0x5a04
7630 #define M_PDEBUGSELH    0x3fU
7634 #define S_PDEBUGSELL    0
7635 #define M_PDEBUGSELL    0x3fU
7640 #define M_T6_PDEBUGSELH    0x7fU
7644 #define S_T6_PDEBUGSELL    0
7645 #define M_T6_PDEBUGSELL    0x7fU
7649 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
7650 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
7651 #define A_PCIE_CDEBUG_INDEX 0x5a10
7654 #define M_CDEBUGSELH    0xffU
7658 #define S_CDEBUGSELL    0
7659 #define M_CDEBUGSELL    0xffU
7663 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
7664 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
7665 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
7668 #define M_CH3    0xffU
7673 #define M_CH2    0xffU
7678 #define M_CH1    0xffU
7682 #define S_CH0    0
7683 #define M_CH0    0xffU
7687 #define A_PCIE_DMAW_EOP_CNT 0x5a20
7688 #define A_PCIE_DMAR_REQ_CNT 0x5a24
7689 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
7690 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
7691 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
7692 #define A_PCIE_DMAI_CNT 0x5a34
7693 #define A_PCIE_CMDW_CNT 0x5a38
7696 #define M_CH1_EOP    0xffU
7701 #define M_CH1_SOP    0xffU
7706 #define M_CH0_EOP    0xffU
7710 #define S_CH0_SOP    0
7711 #define M_CH0_SOP    0xffU
7715 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
7716 #define A_PCIE_CMDR_RSP_CNT 0x5a40
7717 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
7718 #define A_PCIE_HMA_REQ_CNT 0x5a48
7721 #define M_CH0_READ    0xffU
7726 #define M_CH0_WEOP    0xffU
7730 #define S_CH0_WSOP    0
7731 #define M_CH0_WSOP    0xffU
7735 #define A_PCIE_HMA_RSP_CNT 0x5a4c
7736 #define A_PCIE_DMA10_RSP_FREE 0x5a50
7739 #define M_CH1_RSP_FREE    0xfffU
7743 #define S_CH0_RSP_FREE    0
7744 #define M_CH0_RSP_FREE    0xfffU
7748 #define A_PCIE_DMA32_RSP_FREE 0x5a54
7751 #define M_CH3_RSP_FREE    0xfffU
7755 #define S_CH2_RSP_FREE    0
7756 #define M_CH2_RSP_FREE    0xfffU
7760 #define A_PCIE_CMD_RSP_FREE 0x5a58
7763 #define M_CMD_CH1_RSP_FREE    0x7fU
7767 #define S_CMD_CH0_RSP_FREE    0
7768 #define M_CMD_CH0_RSP_FREE    0x7fU
7772 #define A_PCIE_HMA_RSP_FREE 0x5a5c
7773 #define A_PCIE_BUS_MST_STAT_0 0x5a60
7774 #define A_PCIE_BUS_MST_STAT_1 0x5a64
7775 #define A_PCIE_BUS_MST_STAT_2 0x5a68
7776 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
7777 #define A_PCIE_BUS_MST_STAT_4 0x5a70
7779 #define S_BUSMST_135_128    0
7780 #define M_BUSMST_135_128    0xffU
7784 #define A_PCIE_BUS_MST_STAT_5 0x5a74
7785 #define A_PCIE_BUS_MST_STAT_6 0x5a78
7786 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
7787 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
7788 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
7789 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
7790 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
7791 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
7793 #define S_RSPERR_135_128    0
7794 #define M_RSPERR_135_128    0xffU
7798 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
7799 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
7801 #define S_DBI_TIMER    0
7802 #define M_DBI_TIMER    0xffffU
7806 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
7807 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
7808 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
7809 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
7812 #define M_SOURCE    0x3U
7817 #define M_DBI_WRITE    0xfU
7826 #define M_DBI_PF    0x7U
7834 #define S_PL_TOVF    0
7835 #define M_PL_TOVF    0x7fU
7840 #define M_T6_SOURCE    0x3U
7845 #define M_T6_DBI_WRITE    0xfU
7854 #define M_T6_DBI_PF    0x7U
7862 #define S_T6_PL_TOVF    0
7863 #define M_T6_PL_TOVF    0xffU
7867 #define A_PCIE_MSI_EN_0 0x5aa0
7868 #define A_PCIE_MSI_EN_1 0x5aa4
7869 #define A_PCIE_MSI_EN_2 0x5aa8
7870 #define A_PCIE_MSI_EN_3 0x5aac
7871 #define A_PCIE_MSI_EN_4 0x5ab0
7872 #define A_PCIE_MSI_EN_5 0x5ab4
7873 #define A_PCIE_MSI_EN_6 0x5ab8
7874 #define A_PCIE_MSI_EN_7 0x5abc
7875 #define A_PCIE_MSIX_EN_0 0x5ac0
7876 #define A_PCIE_MSIX_EN_1 0x5ac4
7877 #define A_PCIE_MSIX_EN_2 0x5ac8
7878 #define A_PCIE_MSIX_EN_3 0x5acc
7879 #define A_PCIE_MSIX_EN_4 0x5ad0
7880 #define A_PCIE_MSIX_EN_5 0x5ad4
7881 #define A_PCIE_MSIX_EN_6 0x5ad8
7882 #define A_PCIE_MSIX_EN_7 0x5adc
7883 #define A_PCIE_DMA_BUF_CTL 0x5ae0
7886 #define M_BUFRDCNT    0x3fffU
7891 #define M_BUFWRCNT    0x1ffU
7895 #define S_MAXBUFWRREQ    0
7896 #define M_MAXBUFWRREQ    0x1ffU
7900 #define A_PCIE_PB_CTL 0x5b94
7903 #define M_PB_SEL    0xffU
7908 #define M_PB_SELREG    0xffU
7912 #define S_PB_FUNC    0
7913 #define M_PB_FUNC    0x7U
7917 #define A_PCIE_PB_DATA 0x5b98
7918 #define A_PCIE_CUR_LINK 0x5b9c
7957 #define M_NEGOTIATEDWIDTH    0x3fU
7961 #define S_ACTIVELANES    0
7962 #define M_ACTIVELANES    0xffU
7966 #define A_PCIE_PHY_REQRXPWR 0x5ba0
7977 #define M_LNH_RXPWRSTATE    0x3U
7990 #define M_LNG_RXPWRSTATE    0x3U
8003 #define M_LNF_RXPWRSTATE    0x3U
8016 #define M_LNE_RXPWRSTATE    0x3U
8029 #define M_LND_RXPWRSTATE    0x3U
8042 #define M_LNC_RXPWRSTATE    0x3U
8055 #define M_LNB_RXPWRSTATE    0x3U
8067 #define S_LNA_RXPWRSTATE    0
8068 #define M_LNA_RXPWRSTATE    0x3U
8081 #define M_REQ_LNH_RXPWRSTATE    0x3U
8094 #define M_REQ_LNG_RXPWRSTATE    0x3U
8107 #define M_REQ_LNF_RXPWRSTATE    0x3U
8120 #define M_REQ_LNE_RXPWRSTATE    0x3U
8133 #define M_REQ_LND_RXPWRSTATE    0x3U
8146 #define M_REQ_LNC_RXPWRSTATE    0x3U
8159 #define M_REQ_LNB_RXPWRSTATE    0x3U
8171 #define S_REQ_LNA_RXPWRSTATE    0
8172 #define M_REQ_LNA_RXPWRSTATE    0x3U
8176 #define A_PCIE_PHY_CURRXPWR 0x5ba4
8179 #define M_T5_LNH_RXPWRSTATE    0x7U
8184 #define M_T5_LNG_RXPWRSTATE    0x7U
8189 #define M_T5_LNF_RXPWRSTATE    0x7U
8194 #define M_T5_LNE_RXPWRSTATE    0x7U
8199 #define M_T5_LND_RXPWRSTATE    0x7U
8204 #define M_T5_LNC_RXPWRSTATE    0x7U
8209 #define M_T5_LNB_RXPWRSTATE    0x7U
8213 #define S_T5_LNA_RXPWRSTATE    0
8214 #define M_T5_LNA_RXPWRSTATE    0x7U
8219 #define M_CUR_LNH_RXPWRSTATE    0x7U
8224 #define M_CUR_LNG_RXPWRSTATE    0x7U
8229 #define M_CUR_LNF_RXPWRSTATE    0x7U
8234 #define M_CUR_LNE_RXPWRSTATE    0x7U
8239 #define M_CUR_LND_RXPWRSTATE    0x7U
8244 #define M_CUR_LNC_RXPWRSTATE    0x7U
8249 #define M_CUR_LNB_RXPWRSTATE    0x7U
8253 #define S_CUR_LNA_RXPWRSTATE    0
8254 #define M_CUR_LNA_RXPWRSTATE    0x7U
8258 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
8261 #define M_LND_STAT    0x7U
8266 #define M_LND_CMD    0x7U
8271 #define M_LNC_STAT    0x7U
8276 #define M_LNC_CMD    0x7U
8281 #define M_LNB_STAT    0x7U
8286 #define M_LNB_CMD    0x7U
8291 #define M_LNA_STAT    0x7U
8295 #define S_LNA_CMD    0
8296 #define M_LNA_CMD    0x7U
8300 #define A_PCIE_PHY_GEN3_AE1 0x5bac
8303 #define M_LNH_STAT    0x7U
8308 #define M_LNH_CMD    0x7U
8313 #define M_LNG_STAT    0x7U
8318 #define M_LNG_CMD    0x7U
8323 #define M_LNF_STAT    0x7U
8328 #define M_LNF_CMD    0x7U
8333 #define M_LNE_STAT    0x7U
8337 #define S_LNE_CMD    0
8338 #define M_LNE_CMD    0x7U
8342 #define A_PCIE_PHY_FS_LF0 0x5bb0
8345 #define M_LANE1LF    0x3fU
8350 #define M_LANE1FS    0x3fU
8355 #define M_LANE0LF    0x3fU
8359 #define S_LANE0FS    0
8360 #define M_LANE0FS    0x3fU
8364 #define A_PCIE_PHY_FS_LF1 0x5bb4
8367 #define M_LANE3LF    0x3fU
8372 #define M_LANE3FS    0x3fU
8377 #define M_LANE2LF    0x3fU
8381 #define S_LANE2FS    0
8382 #define M_LANE2FS    0x3fU
8386 #define A_PCIE_PHY_FS_LF2 0x5bb8
8389 #define M_LANE5LF    0x3fU
8394 #define M_LANE5FS    0x3fU
8399 #define M_LANE4LF    0x3fU
8403 #define S_LANE4FS    0
8404 #define M_LANE4FS    0x3fU
8408 #define A_PCIE_PHY_FS_LF3 0x5bbc
8411 #define M_LANE7LF    0x3fU
8416 #define M_LANE7FS    0x3fU
8421 #define M_LANE6LF    0x3fU
8425 #define S_LANE6FS    0
8426 #define M_LANE6FS    0x3fU
8430 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
8437 #define M_COEFFLANE    0x7U
8441 #define S_COEFFSTART    0
8446 #define M_T6_COEFFLANE    0xfU
8450 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
8452 #define S_COEFF    0
8453 #define M_COEFF    0x3ffffU
8457 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
8463 #define S_PCIE_PHY_REGADDR    0
8464 #define M_PCIE_PHY_REGADDR    0xffffU
8468 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
8469 #define A_PCIE_STATIC_SPARE1 0x5bf8
8470 #define A_PCIE_STATIC_SPARE2 0x5bfc
8471 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
8474 #define M_KDB_PF_LEN    0x1fU
8478 #define S_KDB_PF_BASEADDR    0
8479 #define M_KDB_PF_BASEADDR    0xfffffU
8483 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
8486 #define M_KDB_VF_LEN    0x1fU
8490 #define S_KDB_VF_BASEADDR    0
8491 #define M_KDB_VF_BASEADDR    0xfffffU
8495 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
8497 #define S_KDB_VF_MODOFST    0
8498 #define M_KDB_VF_MODOFST    0xfffU
8502 #define A_PCIE_PHY_REQRXPWR1 0x5c1c
8513 #define M_REQ_LNP_RXPWRSTATE    0x3U
8526 #define M_REQ_LNO_RXPWRSTATE    0x3U
8539 #define M_REQ_LNN_RXPWRSTATE    0x3U
8552 #define M_REQ_LNM_RXPWRSTATE    0x3U
8565 #define M_REQ_LNL_RXPWRSTATE    0x3U
8578 #define M_REQ_LNK_RXPWRSTATE    0x3U
8591 #define M_REQ_LNJ_RXPWRSTATE    0x3U
8603 #define S_REQ_LNI_RXPWRSTATE    0
8604 #define M_REQ_LNI_RXPWRSTATE    0x3U
8608 #define A_PCIE_PHY_CURRXPWR1 0x5c20
8611 #define M_CUR_LNP_RXPWRSTATE    0x7U
8616 #define M_CUR_LNO_RXPWRSTATE    0x7U
8621 #define M_CUR_LNN_RXPWRSTATE    0x7U
8626 #define M_CUR_LNM_RXPWRSTATE    0x7U
8631 #define M_CUR_LNL_RXPWRSTATE    0x7U
8636 #define M_CUR_LNK_RXPWRSTATE    0x7U
8641 #define M_CUR_LNJ_RXPWRSTATE    0x7U
8645 #define S_CUR_LNI_RXPWRSTATE    0
8646 #define M_CUR_LNI_RXPWRSTATE    0x7U
8650 #define A_PCIE_PHY_GEN3_AE2 0x5c24
8653 #define M_LNL_STAT    0x7U
8658 #define M_LNL_CMD    0x7U
8663 #define M_LNK_STAT    0x7U
8668 #define M_LNK_CMD    0x7U
8673 #define M_LNJ_STAT    0x7U
8678 #define M_LNJ_CMD    0x7U
8683 #define M_LNI_STAT    0x7U
8687 #define S_LNI_CMD    0
8688 #define M_LNI_CMD    0x7U
8692 #define A_PCIE_PHY_GEN3_AE3 0x5c28
8695 #define M_LNP_STAT    0x7U
8700 #define M_LNP_CMD    0x7U
8705 #define M_LNO_STAT    0x7U
8710 #define M_LNO_CMD    0x7U
8715 #define M_LNN_STAT    0x7U
8720 #define M_LNN_CMD    0x7U
8725 #define M_LNM_STAT    0x7U
8729 #define S_LNM_CMD    0
8730 #define M_LNM_CMD    0x7U
8734 #define A_PCIE_PHY_FS_LF4 0x5c2c
8737 #define M_LANE9LF    0x3fU
8742 #define M_LANE9FS    0x3fU
8747 #define M_LANE8LF    0x3fU
8751 #define S_LANE8FS    0
8752 #define M_LANE8FS    0x3fU
8756 #define A_PCIE_PHY_FS_LF5 0x5c30
8759 #define M_LANE11LF    0x3fU
8764 #define M_LANE11FS    0x3fU
8769 #define M_LANE10LF    0x3fU
8773 #define S_LANE10FS    0
8774 #define M_LANE10FS    0x3fU
8778 #define A_PCIE_PHY_FS_LF6 0x5c34
8781 #define M_LANE13LF    0x3fU
8786 #define M_LANE13FS    0x3fU
8791 #define M_LANE12LF    0x3fU
8795 #define S_LANE12FS    0
8796 #define M_LANE12FS    0x3fU
8800 #define A_PCIE_PHY_FS_LF7 0x5c38
8803 #define M_LANE15LF    0x3fU
8808 #define M_LANE15FS    0x3fU
8813 #define M_LANE14LF    0x3fU
8817 #define S_LANE14FS    0
8818 #define M_LANE14FS    0x3fU
8822 #define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
8829 #define M_PHY_REG_SELECT    0x3U
8833 #define S_PHY_REG_REGADDR    0
8834 #define M_PHY_REG_REGADDR    0xffffU
8838 #define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
8840 #define S_PHY_REG_DATA    0
8841 #define M_PHY_REG_DATA    0xffffU
8845 #define A_PCIE_VF_INT_INDIR_REQ 0x5c44
8855 #define S_VFID_PCIE    0
8856 #define M_VFID_PCIE    0x3ffU
8860 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
8861 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
8862 #define A_PCIE_VF_MSI_EN_4 0x5e50
8863 #define A_PCIE_VF_MSI_EN_5 0x5e54
8864 #define A_PCIE_VF_MSI_EN_6 0x5e58
8865 #define A_PCIE_VF_MSI_EN_7 0x5e5c
8866 #define A_PCIE_VF_MSIX_EN_4 0x5e60
8867 #define A_PCIE_VF_MSIX_EN_5 0x5e64
8868 #define A_PCIE_VF_MSIX_EN_6 0x5e68
8869 #define A_PCIE_VF_MSIX_EN_7 0x5e6c
8870 #define A_PCIE_FLR_VF4_STATUS 0x5e70
8871 #define A_PCIE_FLR_VF5_STATUS 0x5e74
8872 #define A_PCIE_FLR_VF6_STATUS 0x5e78
8873 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
8874 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
8875 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
8876 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
8877 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
8878 #define A_PCIE_BUS_MST_STAT_8 0x5e90
8880 #define S_BUSMST_263_256    0
8881 #define M_BUSMST_263_256    0xffU
8885 #define A_PCIE_TGT_SKID_FIFO 0x5e94
8888 #define M_HDRFREECNT    0xfffU
8892 #define S_DATAFREECNT    0
8893 #define M_DATAFREECNT    0xfffU
8897 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
8898 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
8899 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
8900 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
8901 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
8903 #define S_RSPERR_263_256    0
8904 #define M_RSPERR_263_256    0xffU
8908 #define A_PCIE_PHY_STAT1 0x5ec0
8918 #define A_PCIE_PHY_CTRL1 0x5ec4
8929 #define M_TXDEEMPH_GEN1    0xffU
8934 #define M_TXDEEMPH_GEN2_3P5DB    0xffU
8938 #define S_TXDEEMPH_GEN2_6DB    0
8939 #define M_TXDEEMPH_GEN2_6DB    0xffU
8943 #define A_PCIE_PCIE_SPARE0 0x5ec8
8944 #define A_PCIE_RESET_STAT 0x5ecc
8978 #define S_LASTRESETSTATE    0
8979 #define M_LASTRESETSTATE    0x7U
8983 #define A_PCIE_FUNC_DSTATE 0x5ed0
8986 #define M_PF7_DSTATE    0x7U
8991 #define M_PF6_DSTATE    0x7U
8996 #define M_PF5_DSTATE    0x7U
9001 #define M_PF4_DSTATE    0x7U
9006 #define M_PF3_DSTATE    0x7U
9011 #define M_PF2_DSTATE    0x7U
9016 #define M_PF1_DSTATE    0x7U
9020 #define S_PF0_DSTATE    0
9021 #define M_PF0_DSTATE    0x7U
9025 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
9026 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
9027 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
9028 #define A_PCIE_PDEBUG_REG_0X0 0x0
9029 #define A_PCIE_PDEBUG_REG_0X1 0x1
9030 #define A_PCIE_PDEBUG_REG_0X2 0x2
9033 #define M_TAGQ_CH0_TAGS_USED    0xffU
9077 #define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    0
9081 #define A_PCIE_PDEBUG_REG_0X3 0x3
9084 #define M_TAGQ_CH1_TAGS_USED    0xffU
9128 #define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    0
9132 #define A_PCIE_PDEBUG_REG_0X4 0x4
9135 #define M_TAGQ_CH2_TAGS_USED    0xffU
9179 #define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    0
9183 #define A_PCIE_PDEBUG_REG_0X5 0x5
9186 #define M_TAGQ_CH3_TAGS_USED    0xffU
9230 #define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    0
9234 #define A_PCIE_PDEBUG_REG_0X6 0x6
9237 #define M_TAGQ_CH4_TAGS_USED    0xffU
9281 #define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    0
9285 #define A_PCIE_PDEBUG_REG_0X7 0x7
9288 #define M_TAGQ_CH5_TAGS_USED    0xffU
9332 #define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    0
9336 #define A_PCIE_PDEBUG_REG_0X8 0x8
9339 #define M_TAGQ_CH6_TAGS_USED    0xffU
9383 #define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    0
9387 #define A_PCIE_PDEBUG_REG_0X9 0x9
9390 #define M_TAGQ_CH7_TAGS_USED    0xffU
9434 #define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    0
9438 #define A_PCIE_PDEBUG_REG_0XA 0xa
9445 #define M_REQ_CTL_WR_CH0_SEQNUM    0xffU
9450 #define M_REQ_CTL_RD_CH0_SEQNUM    0xffU
9470 #define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    0
9474 #define A_PCIE_PDEBUG_REG_0XB 0xb
9481 #define M_REQ_CTL_WR_CH1_SEQNUM    0xffU
9486 #define M_REQ_CTL_RD_CH1_SEQNUM    0xffU
9506 #define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    0
9510 #define A_PCIE_PDEBUG_REG_0XC 0xc
9517 #define M_REQ_CTL_WR_CH2_SEQNUM    0xffU
9522 #define M_REQ_CTL_RD_CH2_SEQNUM    0xffU
9542 #define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    0
9546 #define A_PCIE_PDEBUG_REG_0XD 0xd
9553 #define M_REQ_CTL_WR_CH3_SEQNUM    0xffU
9558 #define M_REQ_CTL_RD_CH3_SEQNUM    0xffU
9578 #define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    0
9582 #define A_PCIE_PDEBUG_REG_0XE 0xe
9589 #define M_REQ_CTL_WR_CH4_SEQNUM    0xffU
9594 #define M_REQ_CTL_RD_CH4_SEQNUM    0xffU
9614 #define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    0
9618 #define A_PCIE_PDEBUG_REG_0XF 0xf
9619 #define A_PCIE_PDEBUG_REG_0X10 0x10
9626 #define M_PIPE0_TX3_DATA_6_0    0x7fU
9631 #define M_PIPE0_TX2_DATA_7_0    0xffU
9636 #define M_PIPE0_TX1_DATA_7_0    0xffU
9644 #define S_PIPE0_TX0_DATA_6_0    0
9645 #define M_PIPE0_TX0_DATA_6_0    0x7fU
9649 #define A_PCIE_PDEBUG_REG_0X11 0x11
9656 #define M_PIPE0_TX3_DATA_14_8    0x7fU
9661 #define M_PIPE0_TX2_DATA_15_8    0xffU
9666 #define M_PIPE0_TX1_DATA_15_8    0xffU
9674 #define S_PIPE0_TX0_DATA_14_8    0
9675 #define M_PIPE0_TX0_DATA_14_8    0x7fU
9679 #define A_PCIE_PDEBUG_REG_0X12 0x12
9686 #define M_PIPE0_TX7_DATA_6_0    0x7fU
9691 #define M_PIPE0_TX6_DATA_7_0    0xffU
9696 #define M_PIPE0_TX5_DATA_7_0    0xffU
9704 #define S_PIPE0_TX4_DATA_6_0    0
9705 #define M_PIPE0_TX4_DATA_6_0    0x7fU
9709 #define A_PCIE_PDEBUG_REG_0X13 0x13
9716 #define M_PIPE0_TX7_DATA_14_8    0x7fU
9721 #define M_PIPE0_TX6_DATA_15_8    0xffU
9726 #define M_PIPE0_TX5_DATA_15_8    0xffU
9734 #define S_PIPE0_TX4_DATA_14_8    0
9735 #define M_PIPE0_TX4_DATA_14_8    0x7fU
9739 #define A_PCIE_PDEBUG_REG_0X14 0x14
9746 #define M_PIPE0_RX3_VALID2_14    0x7fU
9751 #define M_PIPE0_RX2_VALID_14    0xffU
9756 #define M_PIPE0_RX1_VALID_14    0xffU
9764 #define S_PIPE0_RX0_VALID2_14    0
9765 #define M_PIPE0_RX0_VALID2_14    0x7fU
9769 #define A_PCIE_PDEBUG_REG_0X15 0x15
9776 #define M_PIPE0_RX3_VALID2_15    0x7fU
9781 #define M_PIPE0_RX2_VALID_15    0xffU
9786 #define M_PIPE0_RX1_VALID_15    0xffU
9794 #define S_PIPE0_RX0_VALID2_15    0
9795 #define M_PIPE0_RX0_VALID2_15    0x7fU
9799 #define A_PCIE_PDEBUG_REG_0X16 0x16
9806 #define M_PIPE0_RX7_VALID2_16    0x7fU
9811 #define M_PIPE0_RX6_VALID_16    0xffU
9816 #define M_PIPE0_RX5_VALID_16    0xffU
9824 #define S_PIPE0_RX4_VALID2_16    0
9825 #define M_PIPE0_RX4_VALID2_16    0x7fU
9829 #define A_PCIE_PDEBUG_REG_0X17 0x17
9836 #define M_PIPE0_RX7_VALID2_17    0x7fU
9841 #define M_PIPE0_RX6_VALID_17    0xffU
9846 #define M_PIPE0_RX5_VALID_17    0xffU
9854 #define S_PIPE0_RX4_VALID2_17    0
9855 #define M_PIPE0_RX4_VALID2_17    0x7fU
9859 #define A_PCIE_PDEBUG_REG_0X18 0x18
9866 #define M_PIPE0_RX7_STATUS    0x7U
9875 #define M_PIPE0_RX6_STATUS    0x7U
9884 #define M_PIPE0_RX5_STATUS    0x7U
9893 #define M_PIPE0_RX4_STATUS    0x7U
9902 #define M_PIPE0_RX3_STATUS    0x7U
9911 #define M_PIPE0_RX2_STATUS    0x7U
9920 #define M_PIPE0_RX1_STATUS    0x7U
9928 #define S_PIPE0_RX0_STATUS    0
9929 #define M_PIPE0_RX0_STATUS    0x7U
9933 #define A_PCIE_PDEBUG_REG_0X19 0x19
10059 #define S_PIPE0_RX0_ELECIDLE    0
10063 #define A_PCIE_PDEBUG_REG_0X1A 0x1a
10094 #define M_PIPE0_TX_MARGIN    0x7U
10107 #define M_PIPE0_POWERDOWN    0x3U
10111 #define S_PHY_MAC_PHYSTATUS    0
10112 #define M_PHY_MAC_PHYSTATUS    0xffU
10116 #define A_PCIE_PDEBUG_REG_0X1B 0x1b
10127 #define M_PIPE0_RX7_SYNCHEADER    0x3U
10140 #define M_PIPE0_RX6_SYNCHEADER    0x3U
10153 #define M_PIPE0_RX5_SYNCHEADER    0x3U
10166 #define M_PIPE0_RX4_SYNCHEADER    0x3U
10179 #define M_PIPE0_RX3_SYNCHEADER    0x3U
10192 #define M_PIPE0_RX2_SYNCHEADER    0x3U
10205 #define M_PIPE0_RX1_SYNCHEADER    0x3U
10217 #define S_PIPE0_RX0_SYNCHEADER    0
10218 #define M_PIPE0_RX0_SYNCHEADER    0x3U
10222 #define A_PCIE_PDEBUG_REG_0X1C 0x1c
10225 #define M_SI_REQVFID    0xffU
10230 #define M_SI_REQVEC    0x7ffU
10235 #define M_SI_REQTCVAL    0x7U
10247 #define S_T5_AI    0
10248 #define M_T5_AI    0xffU
10252 #define A_PCIE_PDEBUG_REG_0X1D 0x1d
10263 #define M_SMARB    0x7U
10268 #define M_SMDEFR    0x7U
10273 #define M_SYS_INT    0xffU
10278 #define M_CFG_INTXCLR    0xffU
10282 #define S_PIO_INTXCLR    0
10283 #define M_PIO_INTXCLR    0xffU
10287 #define A_PCIE_PDEBUG_REG_0X1E 0x1e
10298 #define M_TAB_RDENA2    0x7ffU
10303 #define M_PLI_REQADDR    0x1ffU
10308 #define M_PLI_REQVFID    0xffU
10316 #define S_PLI_REQRDVLD    0
10320 #define A_PCIE_PDEBUG_REG_0X1F 0x1f
10321 #define A_PCIE_PDEBUG_REG_0X20 0x20
10322 #define A_PCIE_PDEBUG_REG_0X21 0x21
10325 #define M_PLI_REQPBASTART    0xfffU
10330 #define M_PLI_REQPBAEND    0x7ffU
10335 #define M_T5_PLI_REQVFID    0x7fU
10343 #define A_PCIE_PDEBUG_REG_0X22 0x22
10354 #define M_GNTSI3    0x7U
10359 #define M_GNTSI4    0x7ffU
10364 #define M_GNTSI5    0xffU
10396 #define S_GNTDI    0
10400 #define A_PCIE_PDEBUG_REG_0X23 0x23
10411 #define M_DI_REQWREN    0x7ffU
10428 #define M_DI_REQWREN2    0x3fffU
10436 #define S_DI_REQWREN3    0
10440 #define A_PCIE_PDEBUG_REG_0X24 0x24
10441 #define A_PCIE_PDEBUG_REG_0X25 0x25
10442 #define A_PCIE_PDEBUG_REG_0X26 0x26
10443 #define A_PCIE_PDEBUG_REG_0X27 0x27
10458 #define M_TAB_STIRDENA2    0x7ffU
10463 #define M_T5_PLI_REQTABHIT    0x7ffU
10467 #define S_T5_GNTSI    0
10468 #define M_T5_GNTSI    0x7fU
10472 #define A_PCIE_PDEBUG_REG_0X28 0x28
10499 #define M_AI_REQVLD    0x7U
10512 #define M_VEN_MSI_REQ_28    0x7U
10517 #define M_VEN_MSI_REQ2    0x7fU
10522 #define M_VEN_MSI_REQ3    0x1fU
10527 #define M_VEN_MSI_REQ4    0x7U
10539 #define S_VEN_MSI_REQ6    0
10543 #define A_PCIE_PDEBUG_REG_0X29 0x29
10546 #define M_TRGT1_REQDATAVLD    0xffffU
10551 #define M_TRGT1_REQDATAVLD2    0xfU
10572 #define M_TRGT1_REQDATAVLD7    0xfU
10577 #define M_TRGT1_REQDATAVLD8    0x3U
10585 #define S_TRGT1_REQDATAVLD0    0
10589 #define A_PCIE_PDEBUG_REG_0X2A 0x2a
10590 #define A_PCIE_PDEBUG_REG_0X2B 0x2b
10593 #define M_RADM_TRGT1_ADDR    0xfffU
10598 #define M_RADM_TRGT1_DWEN    0xfU
10603 #define M_RADM_TRGT1_FMT    0x3U
10608 #define M_RADM_TRGT1_TYPE    0x1fU
10613 #define M_RADM_TRGT1_IN_MEMBAR_RANGE    0x7U
10637 #define S_RADM_TRGT1_HV_2B    0
10641 #define A_PCIE_PDEBUG_REG_0X2C 0x2c
10644 #define M_STATEMPIO    0x7U
10649 #define M_STATECPL    0xfU
10654 #define M_STATEALIN    0x7U
10659 #define M_STATEPL    0x7U
10668 #define M_MA_TAGSINUSE    0x7fU
10712 #define S_RADM_TRGT1_ECRC_ERR_2C    0
10716 #define A_PCIE_PDEBUG_REG_0X2D 0x2d
10727 #define M_RADM_TRGT1_HV2    0x7fU
10732 #define M_RADM_TRGT1_HV3    0x7U
10737 #define M_RADM_TRGT1_HV4    0xfU
10742 #define M_RADM_TRGT1_HV5    0xfU
10755 #define M_RADM_TRGT1_HV8    0x7U
10771 #define S_RADM_TRGT1_WRCNT    0
10772 #define M_RADM_TRGT1_WRCNT    0xfU
10776 #define A_PCIE_PDEBUG_REG_0X2E 0x2e
10779 #define M_RADM_TRGT1_HV_2E    0x3U
10784 #define M_RADM_TRGT1_HV_2E_2    0x3ffU
10789 #define M_RADM_TRGT1_HV_WE_3    0xffU
10794 #define M_ALIN_REQDATAVLD4    0xfU
10807 #define M_ALIN_REQDATAVLD7    0x3U
10823 #define S_ALIN_REQDATAVLDA    0
10827 #define A_PCIE_PDEBUG_REG_0X2F 0x2f
10828 #define A_PCIE_PDEBUG_REG_0X30 0x30
10831 #define M_RADM_TRGT1_HV_30    0x7fU
10836 #define M_PIO_WRCNT    0x3ffU
10841 #define M_ALIND_REQWRCNT    0x7U
10846 #define M_FID_LKUPWRCNT    0x7U
10863 #define M_ALIND_REQWRDATAVLD3    0x7U
10875 #define S_ALIND_REQWRDATAVLD5    0
10879 #define A_PCIE_PDEBUG_REG_0X31 0x31
10880 #define A_PCIE_PDEBUG_REG_0X32 0x32
10881 #define A_PCIE_PDEBUG_REG_0X33 0x33
10882 #define A_PCIE_PDEBUG_REG_0X34 0x34
10883 #define A_PCIE_PDEBUG_REG_0X35 0x35
10886 #define M_T5_MPIO_WRVLD    0x1fffU
10950 #define S_MPIO_WRVLD4    0
10951 #define M_MPIO_WRVLD4    0xfU
10955 #define A_PCIE_PDEBUG_REG_0X36 0x36
10956 #define A_PCIE_PDEBUG_REG_0X37 0x37
10957 #define A_PCIE_PDEBUG_REG_0X38 0x38
10958 #define A_PCIE_PDEBUG_REG_0X39 0x39
10959 #define A_PCIE_PDEBUG_REG_0X3A 0x3a
10966 #define M_CLIENT0_TLP_VFUNC_NUM    0x7fU
10971 #define M_CLIENT0_TLP_FUNC_NUM    0x7U
10976 #define M_CLIENT0_TLP_BYTE_EN    0xffU
10980 #define S_CLIENT0_TLP_BYTE_LEN    0
10981 #define M_CLIENT0_TLP_BYTE_LEN    0x1fffU
10985 #define A_PCIE_PDEBUG_REG_0X3B 0x3b
11008 #define M_CLIENT0_CPL_STATUS    0x7U
11017 #define M_CLIENT0_TLP_TYPE    0x1fU
11022 #define M_CLIENT0_TLP_FMT    0x3U
11035 #define M_CLIENT0_TLP_ATTR    0x7U
11040 #define M_CLIENT0_TLP_TC    0x7U
11044 #define S_CLIENT0_TLP_TID    0
11045 #define M_CLIENT0_TLP_TID    0xffU
11049 #define A_PCIE_PDEBUG_REG_0X3C 0x3c
11084 #define M_TGT_TAGQ_RDVLD    0xffU
11089 #define M_CPLTXNDISABLE    0xffU
11097 #define S_CLIENT0_TLP_HV    0
11098 #define M_CLIENT0_TLP_HV    0x7fU
11102 #define A_PCIE_PDEBUG_REG_0X3D 0x3d
11103 #define A_PCIE_PDEBUG_REG_0X3E 0x3e
11104 #define A_PCIE_PDEBUG_REG_0X3F 0x3f
11105 #define A_PCIE_PDEBUG_REG_0X40 0x40
11106 #define A_PCIE_PDEBUG_REG_0X41 0x41
11107 #define A_PCIE_PDEBUG_REG_0X42 0x42
11108 #define A_PCIE_PDEBUG_REG_0X43 0x43
11109 #define A_PCIE_PDEBUG_REG_0X44 0x44
11110 #define A_PCIE_PDEBUG_REG_0X45 0x45
11111 #define A_PCIE_PDEBUG_REG_0X46 0x46
11112 #define A_PCIE_PDEBUG_REG_0X47 0x47
11113 #define A_PCIE_PDEBUG_REG_0X48 0x48
11114 #define A_PCIE_PDEBUG_REG_0X49 0x49
11115 #define A_PCIE_PDEBUG_REG_0X4A 0x4a
11116 #define A_PCIE_PDEBUG_REG_0X4B 0x4b
11117 #define A_PCIE_PDEBUG_REG_0X4C 0x4c
11118 #define A_PCIE_PDEBUG_REG_0X4D 0x4d
11119 #define A_PCIE_PDEBUG_REG_0X4E 0x4e
11120 #define A_PCIE_PDEBUG_REG_0X4F 0x4f
11121 #define A_PCIE_PDEBUG_REG_0X50 0x50
11122 #define A_PCIE_CDEBUG_REG_0X0 0x0
11123 #define A_PCIE_CDEBUG_REG_0X1 0x1
11124 #define A_PCIE_CDEBUG_REG_0X2 0x2
11131 #define M_D_RSPVLD    0x7U
11152 #define M_D_RSPVLD6    0xfU
11157 #define M_D_RSPAFULL    0xfU
11162 #define M_D_RDREQVLD    0xfU
11167 #define M_D_RDREQAFULL    0xfU
11172 #define M_D_WRREQVLD    0xfU
11176 #define S_D_WRREQAFULL    0
11177 #define M_D_WRREQAFULL    0xfU
11181 #define A_PCIE_CDEBUG_REG_0X3 0x3
11184 #define M_C_REQVLD    0x1fffU
11189 #define M_C_RSPVLD2    0x7U
11210 #define M_C_RSPVLD7    0x7U
11215 #define M_C_RSPAFULL    0x7U
11220 #define M_C_REQVLD8    0x7U
11224 #define S_C_REQAFULL    0
11225 #define M_C_REQAFULL    0x7U
11229 #define A_PCIE_CDEBUG_REG_0X4 0x4
11232 #define M_H_REQVLD    0x1ffffffU
11260 #define S_H_REQAFULL    0
11264 #define A_PCIE_CDEBUG_REG_0X5 0x5
11267 #define M_ER_RSPVLD    0xffffU
11272 #define M_ER_REQVLD2    0x7ffU
11277 #define M_ER_REQVLD3    0x7U
11285 #define S_ER_REQVLD5    0
11289 #define A_PCIE_CDEBUG_REG_0X6 0x6
11292 #define M_PL_BAR2_REQVLD    0xfffffffU
11308 #define S_PL_BAR2_REQVLD4    0
11312 #define A_PCIE_CDEBUG_REG_0X7 0x7
11313 #define A_PCIE_CDEBUG_REG_0X8 0x8
11314 #define A_PCIE_CDEBUG_REG_0X9 0x9
11315 #define A_PCIE_CDEBUG_REG_0XA 0xa
11318 #define M_VPD_RSPVLD    0xfffU
11323 #define M_VPD_REQVLD2    0x7ffU
11328 #define M_VPD_REQVLD3    0x7U
11337 #define M_VPD_REQVLD5    0x3U
11349 #define S_VPD_REQVLD6    0
11353 #define A_PCIE_CDEBUG_REG_0XB 0xb
11356 #define M_MA_REQDATAVLD    0xfU
11369 #define M_MA_RSPDATAVLD2    0xfU
11374 #define M_MA_REQADDRVLD3    0x3U
11379 #define M_MA_REQADDRVLD4    0xffffU
11395 #define S_MA_REQADDRVLD7    0
11399 #define A_PCIE_CDEBUG_REG_0XC 0xc
11400 #define A_PCIE_CDEBUG_REG_0XD 0xd
11401 #define A_PCIE_CDEBUG_REG_0XE 0xe
11402 #define A_PCIE_CDEBUG_REG_0XF 0xf
11403 #define A_PCIE_CDEBUG_REG_0X10 0x10
11404 #define A_PCIE_CDEBUG_REG_0X11 0x11
11405 #define A_PCIE_CDEBUG_REG_0X12 0x12
11406 #define A_PCIE_CDEBUG_REG_0X13 0x13
11407 #define A_PCIE_CDEBUG_REG_0X14 0x14
11408 #define A_PCIE_CDEBUG_REG_0X15 0x15
11411 #define M_PLM_REQVLD    0x1fffU
11444 #define M_PLM_REQVLD9    0xffU
11449 #define M_PLM_REQVLDA    0x7U
11453 #define S_PLM_REQVLDB    0
11457 #define A_PCIE_CDEBUG_REG_0X16 0x16
11458 #define A_PCIE_CDEBUG_REG_0X17 0x17
11459 #define A_PCIE_CDEBUG_REG_0X18 0x18
11460 #define A_PCIE_CDEBUG_REG_0X19 0x19
11461 #define A_PCIE_CDEBUG_REG_0X1A 0x1a
11462 #define A_PCIE_CDEBUG_REG_0X1B 0x1b
11463 #define A_PCIE_CDEBUG_REG_0X1C 0x1c
11464 #define A_PCIE_CDEBUG_REG_0X1D 0x1d
11465 #define A_PCIE_CDEBUG_REG_0X1E 0x1e
11466 #define A_PCIE_CDEBUG_REG_0X1F 0x1f
11467 #define A_PCIE_CDEBUG_REG_0X20 0x20
11468 #define A_PCIE_CDEBUG_REG_0X21 0x21
11469 #define A_PCIE_CDEBUG_REG_0X22 0x22
11470 #define A_PCIE_CDEBUG_REG_0X23 0x23
11471 #define A_PCIE_CDEBUG_REG_0X24 0x24
11472 #define A_PCIE_CDEBUG_REG_0X25 0x25
11473 #define A_PCIE_CDEBUG_REG_0X26 0x26
11474 #define A_PCIE_CDEBUG_REG_0X27 0x27
11475 #define A_PCIE_CDEBUG_REG_0X28 0x28
11476 #define A_PCIE_CDEBUG_REG_0X29 0x29
11477 #define A_PCIE_CDEBUG_REG_0X2A 0x2a
11478 #define A_PCIE_CDEBUG_REG_0X2B 0x2b
11479 #define A_PCIE_CDEBUG_REG_0X2C 0x2c
11480 #define A_PCIE_CDEBUG_REG_0X2D 0x2d
11481 #define A_PCIE_CDEBUG_REG_0X2E 0x2e
11482 #define A_PCIE_CDEBUG_REG_0X2F 0x2f
11483 #define A_PCIE_CDEBUG_REG_0X30 0x30
11484 #define A_PCIE_CDEBUG_REG_0X31 0x31
11485 #define A_PCIE_CDEBUG_REG_0X32 0x32
11486 #define A_PCIE_CDEBUG_REG_0X33 0x33
11487 #define A_PCIE_CDEBUG_REG_0X34 0x34
11488 #define A_PCIE_CDEBUG_REG_0X35 0x35
11489 #define A_PCIE_CDEBUG_REG_0X36 0x36
11490 #define A_PCIE_CDEBUG_REG_0X37 0x37
11493 #define DBG_BASE_ADDR 0x6000
11495 #define A_DBG_DBG0_CFG 0x6000
11498 #define M_MODULESELECT    0xffU
11503 #define M_REGSELECT    0xffU
11507 #define S_CLKSELECT    0
11508 #define M_CLKSELECT    0xfU
11512 #define A_DBG_DBG0_EN 0x6004
11530 #define S_DBG_PORTEN    0
11534 #define A_DBG_DBG1_CFG 0x6008
11535 #define A_DBG_DBG1_EN 0x600c
11541 #define A_DBG_GPIO_EN 0x6010
11667 #define S_GPIO0_OUT_VAL    0
11671 #define A_DBG_GPIO_IN 0x6014
11797 #define S_GPIO0_IN    0
11801 #define A_DBG_INT_ENABLE 0x6018
11903 #define S_GPIO0    0
11923 #define A_DBG_INT_CAUSE 0x601c
11941 #define A_DBG_DBG0_RST_VALUE 0x6020
11943 #define S_DEBUGDATA    0
11944 #define M_DEBUGDATA    0xffffU
11948 #define A_DBG_OVERWRSERCFG_EN 0x6024
11950 #define S_OVERWRSERCFG_EN    0
11954 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
11976 #define S_C_OCLK_EN    0
11980 #define A_DBG_PLL_LOCK 0x602c
12002 #define S_PLL_C_LOCK    0
12006 #define A_DBG_GPIO_ACT_LOW 0x6030
12092 #define S_GPIO0_ACT_LOW    0
12112 #define A_DBG_EFUSE_BYTE0_3 0x6034
12113 #define A_DBG_EFUSE_BYTE4_7 0x6038
12114 #define A_DBG_EFUSE_BYTE8_11 0x603c
12115 #define A_DBG_EFUSE_BYTE12_15 0x6040
12116 #define A_DBG_STATIC_U_PLL_CONF 0x6044
12119 #define M_STATIC_U_PLL_MULT    0x1ffU
12124 #define M_STATIC_U_PLL_PREDIV    0x1fU
12129 #define M_STATIC_U_PLL_RANGEA    0xfU
12134 #define M_STATIC_U_PLL_RANGEB    0xfU
12138 #define S_STATIC_U_PLL_TUNE    0
12139 #define M_STATIC_U_PLL_TUNE    0x3ffU
12143 #define A_DBG_STATIC_C_PLL_CONF 0x6048
12146 #define M_STATIC_C_PLL_MULT    0x1ffU
12151 #define M_STATIC_C_PLL_PREDIV    0x1fU
12156 #define M_STATIC_C_PLL_RANGEA    0xfU
12161 #define M_STATIC_C_PLL_RANGEB    0xfU
12165 #define S_STATIC_C_PLL_TUNE    0
12166 #define M_STATIC_C_PLL_TUNE    0x3ffU
12170 #define A_DBG_STATIC_M_PLL_CONF 0x604c
12173 #define M_STATIC_M_PLL_MULT    0x1ffU
12178 #define M_STATIC_M_PLL_PREDIV    0x1fU
12183 #define M_STATIC_M_PLL_RANGEA    0xfU
12188 #define M_STATIC_M_PLL_RANGEB    0xfU
12192 #define S_STATIC_M_PLL_TUNE    0
12193 #define M_STATIC_M_PLL_TUNE    0x3ffU
12197 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
12200 #define M_STATIC_KX_PLL_C    0xffU
12205 #define M_STATIC_KX_PLL_M    0x3fU
12210 #define M_STATIC_KX_PLL_N1    0xfU
12215 #define M_STATIC_KX_PLL_N2    0xfU
12220 #define M_STATIC_KX_PLL_N3    0xfU
12224 #define S_STATIC_KX_PLL_P    0
12225 #define M_STATIC_KX_PLL_P    0x7U
12229 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
12232 #define M_STATIC_KR_PLL_C    0xffU
12237 #define M_STATIC_KR_PLL_M    0x3fU
12242 #define M_STATIC_KR_PLL_N1    0xfU
12247 #define M_STATIC_KR_PLL_N2    0xfU
12252 #define M_STATIC_KR_PLL_N3    0xfU
12256 #define S_STATIC_KR_PLL_P    0
12257 #define M_STATIC_KR_PLL_P    0x7U
12261 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
12288 #define M_STATIC_LVDS_CLKOUT_SEL    0x3U
12297 #define M_STATIC_CCLK_FREQ_SEL    0x3U
12302 #define M_STATIC_UCLK_FREQ_SEL    0x3U
12311 #define M_EXPHYCLK_SEL    0x3U
12332 #define M_STATIC_KX_PLL_V    0xfU
12337 #define M_STATIC_KR_PLL_V    0xfU
12341 #define S_PSRO_SEL    0
12342 #define M_PSRO_SEL    0x7U
12346 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
12353 #define M_C_OCLK_MUXSEL    0x3U
12358 #define M_U_OCLK_MUXSEL    0x3U
12363 #define M_P_OCLK_MUXSEL    0x3U
12368 #define M_KX_OCLK_MUXSEL    0x7U
12372 #define S_KR_OCLK_MUXSEL    0
12373 #define M_KR_OCLK_MUXSEL    0x7U
12378 #define M_T5_P_OCLK_MUXSEL    0xfU
12383 #define M_T6_P_OCLK_MUXSEL    0xfU
12387 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
12388 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
12389 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
12390 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
12391 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
12392 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
12393 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
12394 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
12395 #define A_DBG_TRACE_COUNTER 0x6080
12398 #define M_COUNTER1    0xffffU
12402 #define S_COUNTER0    0
12403 #define M_COUNTER0    0xffffU
12407 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
12409 #define S_STATIC_REFCLK_PERIOD    0
12410 #define M_STATIC_REFCLK_PERIOD    0xffffU
12414 #define A_DBG_TRACE_CONF 0x6088
12436 #define S_DBG_OPERATE0_OR_1    0
12440 #define A_DBG_TRACE_RDEN 0x608c
12443 #define M_RD_ADDR1    0xffU
12448 #define M_RD_ADDR0    0xffU
12456 #define S_RD_EN0    0
12461 #define M_T5_RD_ADDR1    0x1ffU
12466 #define M_T5_RD_ADDR0    0x1ffU
12471 #define M_T6_RD_ADDR1    0x1ffU
12476 #define M_T6_RD_ADDR0    0x1ffU
12480 #define A_DBG_TRACE_WRADDR 0x6090
12483 #define M_WR_POINTER_ADDR1    0xffU
12487 #define S_WR_POINTER_ADDR0    0
12488 #define M_WR_POINTER_ADDR0    0xffU
12493 #define M_T5_WR_POINTER_ADDR1    0x1ffU
12497 #define S_T5_WR_POINTER_ADDR0    0
12498 #define M_T5_WR_POINTER_ADDR0    0x1ffU
12503 #define M_T6_WR_POINTER_ADDR1    0x1ffU
12507 #define S_T6_WR_POINTER_ADDR0    0
12508 #define M_T6_WR_POINTER_ADDR0    0x1ffU
12512 #define A_DBG_TRACE0_DATA_OUT 0x6094
12513 #define A_DBG_TRACE1_DATA_OUT 0x6098
12514 #define A_DBG_FUSE_SENSE_DONE 0x609c
12517 #define M_STATIC_JTAG_VERSIONNR    0xfU
12522 #define M_UNQ0    0xfU
12526 #define S_FUSE_DONE_SENSE    0
12530 #define A_DBG_TVSENSE_EN 0x60a8
12541 #define M_TVSENSE_SNSOUT    0x1ffU
12561 #define S_TVSENSE_RATIO    0
12562 #define M_TVSENSE_RATIO    0xffU
12578 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
12579 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
12580 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
12587 #define M_DBG_FEF    0x3fU
12608 #define M_DBG_FERSEL    0xffffU
12612 #define S_DBG_FETIME    0
12613 #define M_DBG_FETIME    0x7U
12617 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
12620 #define M_T5_STATIC_M_PLL_MULTFRAC    0xffffffU
12624 #define S_T5_STATIC_M_PLL_FFSLEWRATE    0
12625 #define M_T5_STATIC_M_PLL_FFSLEWRATE    0xffU
12629 #define A_DBG_STATIC_M_PLL_CONF1 0x60b8
12632 #define M_STATIC_M_PLL_MULTFRAC    0xffffffU
12636 #define S_STATIC_M_PLL_FFSLEWRATE    0
12637 #define M_STATIC_M_PLL_FFSLEWRATE    0xffU
12641 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
12648 #define M_T5_STATIC_M_PLL_SDORDER    0x3U
12672 #define S_T5_STATIC_M_PLL_LOCKTUNE    0
12673 #define M_T5_STATIC_M_PLL_LOCKTUNE    0xffffU
12677 #define A_DBG_STATIC_M_PLL_CONF2 0x60bc
12680 #define M_T6_STATIC_M_PLL_PREDIV    0x3fU
12689 #define M_STATIC_M_PLL_SDORDER    0x3U
12713 #define S_STATIC_M_PLL_LOCKTUNE    0
12714 #define M_STATIC_M_PLL_LOCKTUNE    0x1fU
12718 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
12721 #define M_T5_STATIC_M_PLL_MULTPRE    0x3U
12726 #define M_T5_STATIC_M_PLL_LOCKSEL    0x3U
12731 #define M_T5_STATIC_M_PLL_FFTUNE    0xffffU
12736 #define M_T5_STATIC_M_PLL_RANGEPRE    0x3U
12741 #define M_T5_STATIC_M_PLL_RANGEB    0x1fU
12745 #define S_T5_STATIC_M_PLL_RANGEA    0
12746 #define M_T5_STATIC_M_PLL_RANGEA    0x1fU
12750 #define A_DBG_STATIC_M_PLL_CONF3 0x60c0
12753 #define M_STATIC_M_PLL_MULTPRE    0x3U
12762 #define M_STATIC_M_PLL_FFTUNE    0xffffU
12767 #define M_STATIC_M_PLL_RANGEPRE    0x3U
12772 #define M_T6_STATIC_M_PLL_RANGEB    0x1fU
12776 #define S_T6_STATIC_M_PLL_RANGEA    0
12777 #define M_T6_STATIC_M_PLL_RANGEA    0x1fU
12781 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
12782 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
12783 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
12786 #define M_T5_STATIC_M_PLL_VCVTUNE    0x7U
12799 #define M_T5_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
12804 #define M_T5_STATIC_M_PLL_PREDIV    0x1fU
12808 #define S_T5_STATIC_M_PLL_MULT    0
12809 #define M_T5_STATIC_M_PLL_MULT    0xffU
12813 #define A_DBG_STATIC_M_PLL_CONF5 0x60c8
12816 #define M_STATIC_M_PLL_VCVTUNE    0x7U
12829 #define M_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
12833 #define S_T6_STATIC_M_PLL_MULT    0
12834 #define M_T6_STATIC_M_PLL_MULT    0xffU
12838 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
12860 #define S_T5_STATIC_SWMC1CFGRST_    0
12864 #define A_DBG_STATIC_M_PLL_CONF6 0x60cc
12883 #define M_STATIC_M_PLL_STARTUP    0x3U
12888 #define M_STATIC_M_PLL_VREGTUNE    0x7ffffU
12912 #define S_STATIC_SWMC1CFGRST_    0
12916 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
12919 #define M_T5_STATIC_C_PLL_MULTFRAC    0xffffffU
12923 #define S_T5_STATIC_C_PLL_FFSLEWRATE    0
12924 #define M_T5_STATIC_C_PLL_FFSLEWRATE    0xffU
12928 #define A_DBG_STATIC_C_PLL_CONF1 0x60d0
12931 #define M_STATIC_C_PLL_MULTFRAC    0xffffffU
12935 #define S_STATIC_C_PLL_FFSLEWRATE    0
12936 #define M_STATIC_C_PLL_FFSLEWRATE    0xffU
12940 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
12947 #define M_T5_STATIC_C_PLL_SDORDER    0x3U
12971 #define S_T5_STATIC_C_PLL_LOCKTUNE    0
12972 #define M_T5_STATIC_C_PLL_LOCKTUNE    0xffffU
12976 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
12979 #define M_T6_STATIC_C_PLL_PREDIV    0x3fU
12984 #define M_STATIC_C_PLL_STARTUP    0x3U
12993 #define M_STATIC_C_PLL_SDORDER    0x3U
13017 #define S_STATIC_C_PLL_LOCKTUNE    0
13018 #define M_STATIC_C_PLL_LOCKTUNE    0x1fU
13022 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
13025 #define M_T5_STATIC_C_PLL_MULTPRE    0x3U
13030 #define M_T5_STATIC_C_PLL_LOCKSEL    0x3U
13035 #define M_T5_STATIC_C_PLL_FFTUNE    0xffffU
13040 #define M_T5_STATIC_C_PLL_RANGEPRE    0x3U
13045 #define M_T5_STATIC_C_PLL_RANGEB    0x1fU
13049 #define S_T5_STATIC_C_PLL_RANGEA    0
13050 #define M_T5_STATIC_C_PLL_RANGEA    0x1fU
13054 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
13057 #define M_STATIC_C_PLL_MULTPRE    0x3U
13066 #define M_STATIC_C_PLL_FFTUNE    0xffffU
13071 #define M_STATIC_C_PLL_RANGEPRE    0x3U
13076 #define M_T6_STATIC_C_PLL_RANGEB    0x1fU
13080 #define S_T6_STATIC_C_PLL_RANGEA    0
13081 #define M_T6_STATIC_C_PLL_RANGEA    0x1fU
13085 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
13086 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
13087 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
13090 #define M_T5_STATIC_C_PLL_VCVTUNE    0x7U
13095 #define M_T5_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
13100 #define M_T5_STATIC_C_PLL_PREDIV    0x1fU
13104 #define S_T5_STATIC_C_PLL_MULT    0
13105 #define M_T5_STATIC_C_PLL_MULT    0xffU
13109 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
13124 #define M_STATIC_C_PLL_VCVTUNE    0x7U
13129 #define M_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
13134 #define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
13138 #define S_T6_STATIC_C_PLL_MULT    0
13139 #define M_T6_STATIC_C_PLL_MULT    0xffU
13143 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
13146 #define M_T5_STATIC_U_PLL_MULTFRAC    0xffffffU
13150 #define S_T5_STATIC_U_PLL_FFSLEWRATE    0
13151 #define M_T5_STATIC_U_PLL_FFSLEWRATE    0xffU
13155 #define A_DBG_STATIC_U_PLL_CONF1 0x60e4
13158 #define M_STATIC_U_PLL_MULTFRAC    0xffffffU
13162 #define S_STATIC_U_PLL_FFSLEWRATE    0
13163 #define M_STATIC_U_PLL_FFSLEWRATE    0xffU
13167 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
13174 #define M_T5_STATIC_U_PLL_SDORDER    0x3U
13198 #define S_T5_STATIC_U_PLL_LOCKTUNE    0
13199 #define M_T5_STATIC_U_PLL_LOCKTUNE    0xffffU
13203 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
13206 #define M_T6_STATIC_U_PLL_PREDIV    0x3fU
13211 #define M_STATIC_U_PLL_STARTUP    0x3U
13220 #define M_STATIC_U_PLL_SDORDER    0x3U
13244 #define S_STATIC_U_PLL_LOCKTUNE    0
13245 #define M_STATIC_U_PLL_LOCKTUNE    0x1fU
13249 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
13252 #define M_T5_STATIC_U_PLL_MULTPRE    0x3U
13257 #define M_T5_STATIC_U_PLL_LOCKSEL    0x3U
13262 #define M_T5_STATIC_U_PLL_FFTUNE    0xffffU
13267 #define M_T5_STATIC_U_PLL_RANGEPRE    0x3U
13272 #define M_T5_STATIC_U_PLL_RANGEB    0x1fU
13276 #define S_T5_STATIC_U_PLL_RANGEA    0
13277 #define M_T5_STATIC_U_PLL_RANGEA    0x1fU
13281 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
13284 #define M_STATIC_U_PLL_MULTPRE    0x3U
13293 #define M_STATIC_U_PLL_FFTUNE    0xffffU
13298 #define M_STATIC_U_PLL_RANGEPRE    0x3U
13303 #define M_T6_STATIC_U_PLL_RANGEB    0x1fU
13307 #define S_T6_STATIC_U_PLL_RANGEA    0
13308 #define M_T6_STATIC_U_PLL_RANGEA    0x1fU
13312 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
13313 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
13314 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
13317 #define M_T5_STATIC_U_PLL_VCVTUNE    0x7U
13322 #define M_T5_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
13327 #define M_T5_STATIC_U_PLL_PREDIV    0x1fU
13331 #define S_T5_STATIC_U_PLL_MULT    0
13332 #define M_T5_STATIC_U_PLL_MULT    0xffU
13336 #define A_DBG_STATIC_U_PLL_CONF5 0x60f4
13351 #define M_STATIC_U_PLL_VCVTUNE    0x7U
13356 #define M_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
13361 #define M_STATIC_U_PLL_PREDIV_CNF5    0x1fU
13365 #define S_T6_STATIC_U_PLL_MULT    0
13366 #define M_T6_STATIC_U_PLL_MULT    0xffU
13370 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
13377 #define M_T5_STATIC_KR_PLL_VBOOSTDIV    0x7U
13382 #define M_T5_STATIC_KR_PLL_CPISEL    0x7U
13407 #define M_T5_STATIC_KR_PLL_CCALBANDSEL    0xfU
13412 #define M_T5_STATIC_KR_PLL_BGOFFSET    0xfU
13417 #define M_T5_STATIC_KR_PLL_P    0x7U
13422 #define M_T5_STATIC_KR_PLL_N2    0xfU
13426 #define S_T5_STATIC_KR_PLL_N1    0
13427 #define M_T5_STATIC_KR_PLL_N1    0xfU
13431 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
13438 #define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
13443 #define M_STATIC_KR_PLL_CPISEL    0x7U
13468 #define M_STATIC_KR_PLL_CCALBANDSEL    0xfU
13473 #define M_STATIC_KR_PLL_BGOFFSET    0xfU
13478 #define M_T6_STATIC_KR_PLL_P    0x7U
13483 #define M_T6_STATIC_KR_PLL_N2    0xfU
13487 #define S_T6_STATIC_KR_PLL_N1    0
13488 #define M_T6_STATIC_KR_PLL_N1    0xfU
13492 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
13495 #define M_T5_STATIC_KR_PLL_M    0x1ffU
13499 #define S_T5_STATIC_KR_PLL_ANALOGTUNE    0
13500 #define M_T5_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
13504 #define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
13507 #define M_T6_STATIC_KR_PLL_M    0x1ffU
13511 #define S_STATIC_KR_PLL_ANALOGTUNE    0
13512 #define M_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
13516 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
13522 #define S_RESET_CALIBRATE    0
13526 #define A_DBG_GPIO_EN_NEW 0x6100
13556 #define S_GPIO19_OUT_VAL    0
13560 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
13574 #define A_DBG_GPIO_IN_NEW 0x6104
13604 #define S_GPIO16_IN    0
13608 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
13611 #define M_LAST_MEASUREMENT_SELECT    0x3U
13616 #define M_LAST_MEASUREMENT_RESULT_BANK_B    0xfU
13620 #define S_LAST_MEASUREMENT_RESULT_BANK_A    0
13621 #define M_LAST_MEASUREMENT_RESULT_BANK_A    0xfU
13625 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
13632 #define M_T5_STATIC_KX_PLL_VBOOSTDIV    0x7U
13637 #define M_T5_STATIC_KX_PLL_CPISEL    0x7U
13662 #define M_T5_STATIC_KX_PLL_CCALBANDSEL    0xfU
13667 #define M_T5_STATIC_KX_PLL_BGOFFSET    0xfU
13672 #define M_T5_STATIC_KX_PLL_P    0x7U
13677 #define M_T5_STATIC_KX_PLL_N2    0xfU
13681 #define S_T5_STATIC_KX_PLL_N1    0
13682 #define M_T5_STATIC_KX_PLL_N1    0xfU
13686 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
13693 #define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
13698 #define M_STATIC_KX_PLL_CPISEL    0x7U
13723 #define M_STATIC_KX_PLL_CCALBANDSEL    0xfU
13728 #define M_STATIC_KX_PLL_BGOFFSET    0xfU
13733 #define M_T6_STATIC_KX_PLL_P    0x7U
13738 #define M_T6_STATIC_KX_PLL_N2    0xfU
13742 #define S_T6_STATIC_KX_PLL_N1    0
13743 #define M_T6_STATIC_KX_PLL_N1    0xfU
13747 #define A_DBG_PVT_REG_DRVN 0x610c
13754 #define M_PVT_REG_DRVN_B    0xfU
13758 #define S_PVT_REG_DRVN_A    0
13759 #define M_PVT_REG_DRVN_A    0xfU
13763 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
13766 #define M_T5_STATIC_KX_PLL_M    0x1ffU
13770 #define S_T5_STATIC_KX_PLL_ANALOGTUNE    0
13771 #define M_T5_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
13775 #define A_DBG_STATIC_KX_PLL_CONF2 0x610c
13778 #define M_T6_STATIC_KX_PLL_M    0x1ffU
13782 #define S_STATIC_KX_PLL_ANALOGTUNE    0
13783 #define M_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
13787 #define A_DBG_PVT_REG_DRVP 0x6110
13794 #define M_PVT_REG_DRVP_B    0xfU
13798 #define S_PVT_REG_DRVP_A    0
13799 #define M_PVT_REG_DRVP_A    0xfU
13803 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
13806 #define M_STATIC_C_DFS_RANGEA    0x1fU
13811 #define M_STATIC_C_DFS_RANGEB    0x1fU
13823 #define S_STATIC_C_DFS_ENABLE    0
13827 #define A_DBG_STATIC_C_DFS_CONF 0x6110
13828 #define A_DBG_PVT_REG_TERMN 0x6114
13835 #define M_PVT_REG_TERMN_B    0xfU
13839 #define S_PVT_REG_TERMN_A    0
13840 #define M_PVT_REG_TERMN_A    0xfU
13844 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
13847 #define M_STATIC_U_DFS_RANGEA    0x1fU
13852 #define M_STATIC_U_DFS_RANGEB    0x1fU
13864 #define S_STATIC_U_DFS_ENABLE    0
13868 #define A_DBG_STATIC_U_DFS_CONF 0x6114
13869 #define A_DBG_PVT_REG_TERMP 0x6118
13876 #define M_PVT_REG_TERMP_B    0xfU
13880 #define S_PVT_REG_TERMP_A    0
13881 #define M_PVT_REG_TERMP_A    0xfU
13885 #define A_DBG_GPIO_PE_EN 0x6118
13963 #define S_GPIO0_PE_EN    0
13967 #define A_DBG_PVT_REG_THRESHOLD 0x611c
14001 #define S_THRESHOLD_DRVN_MIN_SYNC    0
14005 #define A_DBG_GPIO_PS_EN 0x611c
14083 #define S_GPIO0_PS_EN    0
14087 #define A_DBG_PVT_REG_IN_TERMP 0x6120
14090 #define M_REG_IN_TERMP_B    0xfU
14094 #define S_REG_IN_TERMP_A    0
14095 #define M_REG_IN_TERMP_A    0xfU
14099 #define A_DBG_EFUSE_BYTE16_19 0x6120
14100 #define A_DBG_PVT_REG_IN_TERMN 0x6124
14103 #define M_REG_IN_TERMN_B    0xfU
14107 #define S_REG_IN_TERMN_A    0
14108 #define M_REG_IN_TERMN_A    0xfU
14112 #define A_DBG_EFUSE_BYTE20_23 0x6124
14113 #define A_DBG_PVT_REG_IN_DRVP 0x6128
14116 #define M_REG_IN_DRVP_B    0xfU
14120 #define S_REG_IN_DRVP_A    0
14121 #define M_REG_IN_DRVP_A    0xfU
14125 #define A_DBG_EFUSE_BYTE24_27 0x6128
14126 #define A_DBG_PVT_REG_IN_DRVN 0x612c
14129 #define M_REG_IN_DRVN_B    0xfU
14133 #define S_REG_IN_DRVN_A    0
14134 #define M_REG_IN_DRVN_A    0xfU
14138 #define A_DBG_EFUSE_BYTE28_31 0x612c
14139 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
14142 #define M_REG_OUT_TERMP_B    0xfU
14146 #define S_REG_OUT_TERMP_A    0
14147 #define M_REG_OUT_TERMP_A    0xfU
14151 #define A_DBG_EFUSE_BYTE32_35 0x6130
14152 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
14155 #define M_REG_OUT_TERMN_B    0xfU
14159 #define S_REG_OUT_TERMN_A    0
14160 #define M_REG_OUT_TERMN_A    0xfU
14164 #define A_DBG_EFUSE_BYTE36_39 0x6134
14165 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
14168 #define M_REG_OUT_DRVP_B    0xfU
14172 #define S_REG_OUT_DRVP_A    0
14173 #define M_REG_OUT_DRVP_A    0xfU
14177 #define A_DBG_EFUSE_BYTE40_43 0x6138
14178 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
14181 #define M_REG_OUT_DRVN_B    0xfU
14185 #define S_REG_OUT_DRVN_A    0
14186 #define M_REG_OUT_DRVN_A    0xfU
14190 #define A_DBG_EFUSE_BYTE44_47 0x613c
14191 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
14194 #define M_TERMP_B_HISTORY    0xfU
14198 #define S_TERMP_A_HISTORY    0
14199 #define M_TERMP_A_HISTORY    0xfU
14203 #define A_DBG_EFUSE_BYTE48_51 0x6140
14204 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
14207 #define M_TERMN_B_HISTORY    0xfU
14211 #define S_TERMN_A_HISTORY    0
14212 #define M_TERMN_A_HISTORY    0xfU
14216 #define A_DBG_EFUSE_BYTE52_55 0x6144
14217 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
14220 #define M_DRVP_B_HISTORY    0xfU
14224 #define S_DRVP_A_HISTORY    0
14225 #define M_DRVP_A_HISTORY    0xfU
14229 #define A_DBG_EFUSE_BYTE56_59 0x6148
14230 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
14233 #define M_DRVN_B_HISTORY    0xfU
14237 #define S_DRVN_A_HISTORY    0
14238 #define M_DRVN_A_HISTORY    0xfU
14242 #define A_DBG_EFUSE_BYTE60_63 0x614c
14243 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
14245 #define S_SAMPLE_WAIT_CLKS    0
14246 #define M_SAMPLE_WAIT_CLKS    0x1fU
14250 #define A_DBG_STATIC_U_PLL_CONF6 0x6150
14252 #define S_STATIC_U_PLL_VREGTUNE    0
14253 #define M_STATIC_U_PLL_VREGTUNE    0x7ffffU
14257 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
14259 #define S_STATIC_C_PLL_VREGTUNE    0
14260 #define M_STATIC_C_PLL_VREGTUNE    0x7ffffU
14264 #define A_DBG_CUST_EFUSE_PROGRAM 0x6158
14267 #define M_EFUSE_PROG_PERIOD    0xffffU
14272 #define M_EFUSE_OPER_TYP    0x3U
14277 #define M_EFUSE_ADDR    0x3fU
14281 #define S_EFUSE_DIN    0
14282 #define M_EFUSE_DIN    0xffU
14286 #define A_DBG_CUST_EFUSE_OUT 0x615c
14292 #define S_EFUSE_DOUT    0
14293 #define M_EFUSE_DOUT    0xffU
14297 #define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
14298 #define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
14299 #define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
14300 #define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
14301 #define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
14302 #define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
14303 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
14304 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
14305 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
14306 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
14307 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
14308 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
14309 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
14310 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
14311 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
14312 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
14315 #define MC_BASE_ADDR 0x6200
14317 #define A_MC_PCTL_SCFG 0x6200
14335 #define S_HW_LOW_POWER_EN    0
14339 #define A_MC_PCTL_SCTL 0x6204
14341 #define S_STATE_CMD    0
14342 #define M_STATE_CMD    0x7U
14346 #define A_MC_PCTL_STAT 0x6208
14348 #define S_CTL_STAT    0
14349 #define M_CTL_STAT    0x7U
14353 #define A_MC_PCTL_MCMD 0x6240
14360 #define M_CMD_ADD_DEL    0xfU
14365 #define M_RANK_SEL    0xfU
14370 #define M_BANK_ADDR    0x7U
14375 #define M_CMD_ADDR    0x1fffU
14379 #define S_CMD_OPCODE    0
14380 #define M_CMD_OPCODE    0x7U
14384 #define A_MC_PCTL_POWCTL 0x6244
14386 #define S_POWER_UP_START    0
14390 #define A_MC_PCTL_POWSTAT 0x6248
14396 #define S_POWER_UP_DONE    0
14400 #define A_MC_PCTL_MCFG 0x6280
14403 #define M_TFAW_CFG    0x3U
14416 #define M_PD_IDLE    0xffU
14421 #define M_PAGE_POLICY    0x3U
14437 #define S_MEM_BL    0
14441 #define A_MC_PCTL_PPCFG 0x6284
14444 #define M_RPMEM_DIS    0xffU
14448 #define S_PPMEM_EN    0
14452 #define A_MC_PCTL_MSTAT 0x6288
14454 #define S_POWER_DOWN    0
14458 #define A_MC_PCTL_ODTCFG 0x628c
14536 #define S_RANK0_ODT_READ_NSEL    0
14540 #define A_MC_PCTL_DQSECFG 0x6290
14543 #define M_DV_ALAT    0xfU
14548 #define M_DV_ALEN    0x3U
14553 #define M_DSE_ALAT    0xfU
14558 #define M_DSE_ALEN    0x3U
14563 #define M_QSE_ALAT    0xfU
14567 #define S_QSE_ALEN    0
14568 #define M_QSE_ALEN    0x3U
14572 #define A_MC_PCTL_DTUPDES 0x6294
14579 #define M_DTU_EAFFL    0xfU
14615 #define S_DTU_ERR_B0    0
14619 #define A_MC_PCTL_DTUNA 0x6298
14620 #define A_MC_PCTL_DTUNE 0x629c
14621 #define A_MC_PCTL_DTUPRDO 0x62a0
14624 #define M_DTU_ALLBITS_1    0xffffU
14628 #define S_DTU_ALLBITS_0    0
14629 #define M_DTU_ALLBITS_0    0xffffU
14633 #define A_MC_PCTL_DTUPRD1 0x62a4
14636 #define M_DTU_ALLBITS_3    0xffffU
14640 #define S_DTU_ALLBITS_2    0
14641 #define M_DTU_ALLBITS_2    0xffffU
14645 #define A_MC_PCTL_DTUPRD2 0x62a8
14648 #define M_DTU_ALLBITS_5    0xffffU
14652 #define S_DTU_ALLBITS_4    0
14653 #define M_DTU_ALLBITS_4    0xffffU
14657 #define A_MC_PCTL_DTUPRD3 0x62ac
14660 #define M_DTU_ALLBITS_7    0xffffU
14664 #define S_DTU_ALLBITS_6    0
14665 #define M_DTU_ALLBITS_6    0xffffU
14669 #define A_MC_PCTL_DTUAWDT 0x62b0
14672 #define M_NUMBER_RANKS    0x3U
14677 #define M_ROW_ADDR_WIDTH    0x3U
14682 #define M_BANK_ADDR_WIDTH    0x3U
14686 #define S_COLUMN_ADDR_WIDTH    0
14687 #define M_COLUMN_ADDR_WIDTH    0x3U
14691 #define A_MC_PCTL_TOGCNT1U 0x62c0
14693 #define S_TOGGLE_COUNTER_1U    0
14694 #define M_TOGGLE_COUNTER_1U    0x3ffU
14698 #define A_MC_PCTL_TINIT 0x62c4
14700 #define S_T_INIT    0
14701 #define M_T_INIT    0x1ffU
14705 #define A_MC_PCTL_TRSTH 0x62c8
14707 #define S_T_RSTH    0
14708 #define M_T_RSTH    0x3ffU
14712 #define A_MC_PCTL_TOGCNT100N 0x62cc
14714 #define S_TOGGLE_COUNTER_100N    0
14715 #define M_TOGGLE_COUNTER_100N    0x7fU
14719 #define A_MC_PCTL_TREFI 0x62d0
14721 #define S_T_REFI    0
14722 #define M_T_REFI    0xffU
14726 #define A_MC_PCTL_TMRD 0x62d4
14728 #define S_T_MRD    0
14729 #define M_T_MRD    0x7U
14733 #define A_MC_PCTL_TRFC 0x62d8
14735 #define S_T_RFC    0
14736 #define M_T_RFC    0xffU
14740 #define A_MC_PCTL_TRP 0x62dc
14742 #define S_T_RP    0
14743 #define M_T_RP    0xfU
14747 #define A_MC_PCTL_TRTW 0x62e0
14749 #define S_T_RTW    0
14750 #define M_T_RTW    0x7U
14754 #define A_MC_PCTL_TAL 0x62e4
14756 #define S_T_AL    0
14757 #define M_T_AL    0xfU
14761 #define A_MC_PCTL_TCL 0x62e8
14763 #define S_T_CL    0
14764 #define M_T_CL    0xfU
14768 #define A_MC_PCTL_TCWL 0x62ec
14770 #define S_T_CWL    0
14771 #define M_T_CWL    0xfU
14775 #define A_MC_PCTL_TRAS 0x62f0
14777 #define S_T_RAS    0
14778 #define M_T_RAS    0x3fU
14782 #define A_MC_PCTL_TRC 0x62f4
14784 #define S_T_RC    0
14785 #define M_T_RC    0x3fU
14789 #define A_MC_PCTL_TRCD 0x62f8
14791 #define S_T_RCD    0
14792 #define M_T_RCD    0xfU
14796 #define A_MC_PCTL_TRRD 0x62fc
14798 #define S_T_RRD    0
14799 #define M_T_RRD    0xfU
14803 #define A_MC_PCTL_TRTP 0x6300
14805 #define S_T_RTP    0
14806 #define M_T_RTP    0x7U
14810 #define A_MC_PCTL_TWR 0x6304
14812 #define S_T_WR    0
14813 #define M_T_WR    0x7U
14817 #define A_MC_PCTL_TWTR 0x6308
14819 #define S_T_WTR    0
14820 #define M_T_WTR    0x7U
14824 #define A_MC_PCTL_TEXSR 0x630c
14826 #define S_T_EXSR    0
14827 #define M_T_EXSR    0x3ffU
14831 #define A_MC_PCTL_TXP 0x6310
14833 #define S_T_XP    0
14834 #define M_T_XP    0x7U
14838 #define A_MC_PCTL_TXPDLL 0x6314
14840 #define S_T_XPDLL    0
14841 #define M_T_XPDLL    0x3fU
14845 #define A_MC_PCTL_TZQCS 0x6318
14847 #define S_T_ZQCS    0
14848 #define M_T_ZQCS    0x7fU
14852 #define A_MC_PCTL_TZQCSI 0x631c
14854 #define S_T_ZQCSI    0
14855 #define M_T_ZQCSI    0xfffU
14859 #define A_MC_PCTL_TDQS 0x6320
14861 #define S_T_DQS    0
14862 #define M_T_DQS    0x7U
14866 #define A_MC_PCTL_TCKSRE 0x6324
14868 #define S_T_CKSRE    0
14869 #define M_T_CKSRE    0xfU
14873 #define A_MC_PCTL_TCKSRX 0x6328
14875 #define S_T_CKSRX    0
14876 #define M_T_CKSRX    0xfU
14880 #define A_MC_PCTL_TCKE 0x632c
14882 #define S_T_CKE    0
14883 #define M_T_CKE    0x7U
14887 #define A_MC_PCTL_TMOD 0x6330
14889 #define S_T_MOD    0
14890 #define M_T_MOD    0xfU
14894 #define A_MC_PCTL_TRSTL 0x6334
14896 #define S_RSTHOLD    0
14897 #define M_RSTHOLD    0x7fU
14901 #define A_MC_PCTL_TZQCL 0x6338
14903 #define S_T_ZQCL    0
14904 #define M_T_ZQCL    0x3ffU
14908 #define A_MC_PCTL_DWLCFG0 0x6370
14910 #define S_T_ADWL_VEC    0
14911 #define M_T_ADWL_VEC    0x1ffU
14915 #define A_MC_PCTL_DWLCFG1 0x6374
14916 #define A_MC_PCTL_DWLCFG2 0x6378
14917 #define A_MC_PCTL_DWLCFG3 0x637c
14918 #define A_MC_PCTL_ECCCFG 0x6380
14932 #define A_MC_PCTL_ECCTST 0x6384
14934 #define S_ECC_TEST_MASK    0
14935 #define M_ECC_TEST_MASK    0xffU
14939 #define A_MC_PCTL_ECCCLR 0x6388
14945 #define S_CLR_ECC_INTR    0
14949 #define A_MC_PCTL_ECCLOG 0x638c
14950 #define A_MC_PCTL_DTUWACTL 0x6400
14953 #define M_DTU_WR_RANK    0x3U
14958 #define M_DTU_WR_ROW    0x1ffffU
14963 #define M_DTU_WR_BANK    0x7U
14967 #define S_DTU_WR_COL    0
14968 #define M_DTU_WR_COL    0x3ffU
14972 #define A_MC_PCTL_DTURACTL 0x6404
14975 #define M_DTU_RD_RANK    0x3U
14980 #define M_DTU_RD_ROW    0x1ffffU
14985 #define M_DTU_RD_BANK    0x7U
14989 #define S_DTU_RD_COL    0
14990 #define M_DTU_RD_COL    0x3ffU
14994 #define A_MC_PCTL_DTUCFG 0x6408
14997 #define M_DTU_ROW_INCREMENTS    0x7fU
15010 #define M_DTU_TARGET_LANE    0xfU
15027 #define M_DTU_NALEN    0x3fU
15031 #define S_DTU_ENABLE    0
15035 #define A_MC_PCTL_DTUECTL 0x640c
15045 #define S_RUN_DTU    0
15049 #define A_MC_PCTL_DTUWD0 0x6410
15052 #define M_DTU_WR_BYTE3    0xffU
15057 #define M_DTU_WR_BYTE2    0xffU
15062 #define M_DTU_WR_BYTE1    0xffU
15066 #define S_DTU_WR_BYTE0    0
15067 #define M_DTU_WR_BYTE0    0xffU
15071 #define A_MC_PCTL_DTUWD1 0x6414
15074 #define M_DTU_WR_BYTE7    0xffU
15079 #define M_DTU_WR_BYTE6    0xffU
15084 #define M_DTU_WR_BYTE5    0xffU
15088 #define S_DTU_WR_BYTE4    0
15089 #define M_DTU_WR_BYTE4    0xffU
15093 #define A_MC_PCTL_DTUWD2 0x6418
15096 #define M_DTU_WR_BYTE11    0xffU
15101 #define M_DTU_WR_BYTE10    0xffU
15106 #define M_DTU_WR_BYTE9    0xffU
15110 #define S_DTU_WR_BYTE8    0
15111 #define M_DTU_WR_BYTE8    0xffU
15115 #define A_MC_PCTL_DTUWD3 0x641c
15118 #define M_DTU_WR_BYTE15    0xffU
15123 #define M_DTU_WR_BYTE14    0xffU
15128 #define M_DTU_WR_BYTE13    0xffU
15132 #define S_DTU_WR_BYTE12    0
15133 #define M_DTU_WR_BYTE12    0xffU
15137 #define A_MC_PCTL_DTUWDM 0x6420
15139 #define S_DM_WR_BYTE0    0
15140 #define M_DM_WR_BYTE0    0xffffU
15144 #define A_MC_PCTL_DTURD0 0x6424
15147 #define M_DTU_RD_BYTE3    0xffU
15152 #define M_DTU_RD_BYTE2    0xffU
15157 #define M_DTU_RD_BYTE1    0xffU
15161 #define S_DTU_RD_BYTE0    0
15162 #define M_DTU_RD_BYTE0    0xffU
15166 #define A_MC_PCTL_DTURD1 0x6428
15169 #define M_DTU_RD_BYTE7    0xffU
15174 #define M_DTU_RD_BYTE6    0xffU
15179 #define M_DTU_RD_BYTE5    0xffU
15183 #define S_DTU_RD_BYTE4    0
15184 #define M_DTU_RD_BYTE4    0xffU
15188 #define A_MC_PCTL_DTURD2 0x642c
15191 #define M_DTU_RD_BYTE11    0xffU
15196 #define M_DTU_RD_BYTE10    0xffU
15201 #define M_DTU_RD_BYTE9    0xffU
15205 #define S_DTU_RD_BYTE8    0
15206 #define M_DTU_RD_BYTE8    0xffU
15210 #define A_MC_PCTL_DTURD3 0x6430
15213 #define M_DTU_RD_BYTE15    0xffU
15218 #define M_DTU_RD_BYTE14    0xffU
15223 #define M_DTU_RD_BYTE13    0xffU
15227 #define S_DTU_RD_BYTE12    0
15228 #define M_DTU_RD_BYTE12    0xffU
15232 #define A_MC_DTULFSRWD 0x6434
15233 #define A_MC_PCTL_DTULFSRRD 0x6438
15234 #define A_MC_PCTL_DTUEAF 0x643c
15237 #define M_EA_RANK    0x3U
15242 #define M_EA_ROW    0x1ffffU
15247 #define M_EA_BANK    0x7U
15251 #define S_EA_COLUMN    0
15252 #define M_EA_COLUMN    0x3ffU
15256 #define A_MC_PCTL_PHYPVTCFG 0x6500
15275 #define M_PVT_UPD_DONE_TYPE    0x3U
15295 #define S_PHY_UPD_DONE_TYPE    0
15296 #define M_PHY_UPD_DONE_TYPE    0x3U
15300 #define A_MC_PCTL_PHYPVTSTAT 0x6504
15314 #define S_I_PHY_UPD_DONE    0
15318 #define A_MC_PCTL_PHYTUPDON 0x6508
15320 #define S_PHY_T_UPDON    0
15321 #define M_PHY_T_UPDON    0xffU
15325 #define A_MC_PCTL_PHYTUPDDLY 0x650c
15327 #define S_PHY_T_UPDDLY    0
15328 #define M_PHY_T_UPDDLY    0xfU
15332 #define A_MC_PCTL_PVTTUPON 0x6510
15334 #define S_PVT_T_UPDON    0
15335 #define M_PVT_T_UPDON    0xffU
15339 #define A_MC_PCTL_PVTTUPDDLY 0x6514
15341 #define S_PVT_T_UPDDLY    0
15342 #define M_PVT_T_UPDDLY    0xfU
15346 #define A_MC_PCTL_PHYPVTUPDI 0x6518
15348 #define S_PHYPVT_T_UPDI    0
15349 #define M_PHYPVT_T_UPDI    0xffU
15353 #define A_MC_PCTL_PHYIOCRV1 0x651c
15356 #define M_BYTE_OE_CTL    0x3U
15361 #define M_DYN_SOC_ODT_ALAT    0xfU
15366 #define M_DYN_SOC_ODT_ATEN    0x3U
15374 #define S_SOC_ODT_EN    0
15378 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
15380 #define S_PHY_T_UPDWAIT    0
15381 #define M_PHY_T_UPDWAIT    0x3fU
15385 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
15387 #define S_PVT_T_UPDWAIT    0
15388 #define M_PVT_T_UPDWAIT    0x3fU
15392 #define A_MC_DDR3PHYAC_GCR 0x6a00
15395 #define M_WLRANK    0x3U
15400 #define M_FDEPTH    0x3U
15405 #define M_LPFDEPTH    0x3U
15421 #define S_MDLEN    0
15425 #define A_MC_DDR3PHYAC_RCR0 0x6a04
15459 #define S_CKOEN    0
15463 #define A_MC_DDR3PHYAC_ACCR 0x6a14
15497 #define S_CK4OEN    0
15501 #define A_MC_DDR3PHYAC_GSR 0x6a18
15511 #define S_ACCAL    0
15515 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
15521 #define S_WLINC    0
15525 #define A_MC_DDR3PHYAC_OCSR 0x6a20
15526 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
15528 #define S_PRD    0
15529 #define M_PRD    0x3ffU
15533 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
15534 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
15535 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
15536 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
15538 #define S_DFLTDLY    0
15539 #define M_DFLTDLY    0x7fU
15543 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
15544 #define A_MC_DDR3PHYAC_ACR 0x6a60
15551 #define M_ISEL    0x3U
15563 #define S_CKINV    0
15567 #define A_MC_DDR3PHYAC_PSCR 0x6a64
15569 #define S_PSCALE    0
15570 #define M_PSCALE    0x3ffU
15574 #define A_MC_DDR3PHYAC_PRCR 0x6a68
15585 #define M_RSTCLKS    0xfU
15597 #define S_PHYRST    0
15601 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
15604 #define M_RSTCXKS    0x1fU
15612 #define S_TESTA    0
15613 #define M_TESTA    0x7U
15617 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
15624 #define M_BDIV    0x3U
15628 #define S_TESTD    0
15629 #define M_TESTD    0x7U
15633 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
15636 #define M_CKCLKEN    0x3fU
15648 #define S_DDRCLKEN    0
15652 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
15678 #define S_WLSDVT    0
15682 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
15684 #define S_WDSDR_DLY    0
15685 #define M_WDSDR_DLY    0x3ffU
15689 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
15690 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
15692 #define S_WL_DLY    0
15693 #define M_WL_DLY    0x3ffU
15697 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
15699 #define S_DLY    0
15700 #define M_DLY    0x7fU
15704 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
15705 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
15706 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
15707 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
15708 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
15709 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
15710 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
15711 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
15712 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
15714 #define S_MAXDLY    0
15715 #define M_MAXDLY    0x7fU
15719 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
15721 #define S_RDSDR_DLY    0
15722 #define M_RDSDR_DLY    0x3ffU
15726 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
15727 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
15728 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
15729 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
15730 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
15731 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
15732 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
15733 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
15734 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
15735 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
15736 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
15737 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
15738 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
15739 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
15741 #define S_DP_DLY    0
15742 #define M_DP_DLY    0x1ffU
15746 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
15747 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
15761 #define S_RDQSCAL    0
15765 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
15783 #define S_DSINV    0
15787 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
15793 #define S_RANK    0
15794 #define M_RANK    0x3U
15798 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
15801 #define M_DTOSEL    0x3U
15805 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
15806 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
15807 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
15808 #define A_MC_PVT_REG_DRVN 0x740c
15809 #define A_MC_PVT_REG_DRVP 0x7410
15810 #define A_MC_PVT_REG_TERMN 0x7414
15811 #define A_MC_PVT_REG_TERMP 0x7418
15812 #define A_MC_PVT_REG_THRESHOLD 0x741c
15813 #define A_MC_PVT_REG_IN_TERMP 0x7420
15814 #define A_MC_PVT_REG_IN_TERMN 0x7424
15815 #define A_MC_PVT_REG_IN_DRVP 0x7428
15816 #define A_MC_PVT_REG_IN_DRVN 0x742c
15817 #define A_MC_PVT_REG_OUT_TERMP 0x7430
15818 #define A_MC_PVT_REG_OUT_TERMN 0x7434
15819 #define A_MC_PVT_REG_OUT_DRVP 0x7438
15820 #define A_MC_PVT_REG_OUT_DRVN 0x743c
15821 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
15822 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
15823 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
15824 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
15825 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
15826 #define A_MC_DDRPHY_RST_CTRL 0x7500
15832 #define S_PHY_RST_N    0
15836 #define A_MC_PERFORMANCE_CTRL 0x7504
15846 #define S_RMW_PERF_CTRL    0
15850 #define A_MC_ECC_CTRL 0x7508
15856 #define S_ECC_DISABLE    0
15860 #define A_MC_PAR_ENABLE 0x750c
15874 #define S_PERR_BLK_INT_ENABLE    0
15878 #define A_MC_PAR_CAUSE 0x7510
15892 #define S_RDATA_FIFOR_PAR_CAUSE    0
15896 #define A_MC_INT_ENABLE 0x7514
15906 #define S_PERR_INT_ENABLE    0
15910 #define A_MC_INT_CAUSE 0x7518
15920 #define S_PERR_INT_CAUSE    0
15924 #define A_MC_ECC_STATUS 0x751c
15927 #define M_ECC_CECNT    0xffffU
15931 #define S_ECC_UECNT    0
15932 #define M_ECC_UECNT    0xffffU
15936 #define A_MC_PHY_CTRL 0x7520
15938 #define S_CTLPHYRR    0
15942 #define A_MC_STATIC_CFG_STATUS 0x7524
15949 #define M_STATIC_DEN    0x7U
15962 #define M_STATIC_WIDTH    0x7U
15966 #define S_STATIC_SLOW    0
15970 #define A_MC_CORE_PCTL_STAT 0x7528
15972 #define S_PCTL_ACCESS_STAT    0
15973 #define M_PCTL_ACCESS_STAT    0x7U
15977 #define A_MC_DEBUG_CNT 0x752c
15980 #define M_WDATA_OCNT    0x1fU
15984 #define S_RDATA_OCNT    0
15985 #define M_RDATA_OCNT    0x1fU
15989 #define A_MC_BONUS 0x7530
15990 #define A_MC_BIST_CMD 0x7600
15997 #define M_BIST_CMD_GAP    0xffU
16001 #define S_BIST_OPCODE    0
16002 #define M_BIST_OPCODE    0x3U
16006 #define A_MC_BIST_CMD_ADDR 0x7604
16007 #define A_MC_BIST_CMD_LEN 0x7608
16008 #define A_MC_BIST_DATA_PATTERN 0x760c
16010 #define S_BIST_DATA_TYPE    0
16011 #define M_BIST_DATA_TYPE    0xfU
16015 #define A_MC_BIST_USER_WDATA0 0x7614
16016 #define A_MC_BIST_USER_WDATA1 0x7618
16017 #define A_MC_BIST_USER_WDATA2 0x761c
16019 #define S_USER_DATA2    0
16020 #define M_USER_DATA2    0xffU
16024 #define A_MC_BIST_NUM_ERR 0x7680
16025 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
16026 #define A_MC_BIST_STATUS_RDATA 0x7688
16029 #define MA_BASE_ADDR 0x7700
16031 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
16034 #define M_THRESHOLD1    0x7fffU
16043 #define M_THRESHOLD0    0x7fffU
16047 #define S_THRESHOLD0_EN    0
16051 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
16052 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
16053 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
16054 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
16055 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
16056 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
16057 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
16058 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
16059 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
16060 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
16061 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
16062 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
16063 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
16064 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
16065 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
16066 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
16067 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
16068 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
16069 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
16070 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
16071 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
16072 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
16073 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
16074 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
16075 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
16076 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
16079 #define M_DBG_READ_DATA_CNT    0xffU
16084 #define M_DBG_READ_REQ_CNT    0xffU
16089 #define M_DBG_WRITE_DATA_CNT    0xffU
16093 #define S_DBG_WRITE_REQ_CNT    0
16094 #define M_DBG_WRITE_REQ_CNT    0xffU
16098 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
16099 #define A_MA_ULPTX_DEBUG_CNT 0x7770
16100 #define A_MA_ULPRX_DEBUG_CNT 0x7774
16101 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
16102 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
16103 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
16104 #define A_MA_LE_DEBUG_CNT 0x7784
16105 #define A_MA_CIM_DEBUG_CNT 0x7788
16106 #define A_MA_PCIE_DEBUG_CNT 0x778c
16107 #define A_MA_PMTX_DEBUG_CNT 0x7790
16108 #define A_MA_PMRX_DEBUG_CNT 0x7794
16109 #define A_MA_HMA_DEBUG_CNT 0x7798
16110 #define A_MA_EDRAM0_BAR 0x77c0
16113 #define M_EDRAM0_BASE    0xfffU
16117 #define S_EDRAM0_SIZE    0
16118 #define M_EDRAM0_SIZE    0xfffU
16122 #define A_MA_EDRAM1_BAR 0x77c4
16125 #define M_EDRAM1_BASE    0xfffU
16129 #define S_EDRAM1_SIZE    0
16130 #define M_EDRAM1_SIZE    0xfffU
16134 #define A_MA_EXT_MEMORY_BAR 0x77c8
16137 #define M_EXT_MEM_BASE    0xfffU
16141 #define S_EXT_MEM_SIZE    0
16142 #define M_EXT_MEM_SIZE    0xfffU
16146 #define A_MA_EXT_MEMORY0_BAR 0x77c8
16149 #define M_EXT_MEM0_BASE    0xfffU
16153 #define S_EXT_MEM0_SIZE    0
16154 #define M_EXT_MEM0_SIZE    0xfffU
16158 #define A_MA_HOST_MEMORY_BAR 0x77cc
16161 #define M_HMA_BASE    0xfffU
16165 #define S_HMA_SIZE    0
16166 #define M_HMA_SIZE    0xfffU
16170 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
16176 #define S_EXT_MEM_PAGE_SIZE    0
16177 #define M_EXT_MEM_PAGE_SIZE    0x3U
16186 #define M_EXT_MEM_PAGE_SIZE1    0x3U
16198 #define S_T6_EXT_MEM_PAGE_SIZE    0
16199 #define M_T6_EXT_MEM_PAGE_SIZE    0x7U
16203 #define A_MA_ARB_CTRL 0x77d4
16209 #define S_DIS_ADV_ARB    0
16222 #define M_HMA_NUM_PG_128B_FDBK    0x1fU
16247 #define M_NUM_PG_128B_FDBK    0x1fU
16259 #define A_MA_TARGET_MEM_ENABLE 0x77d8
16273 #define S_EDRAM0_ENABLE    0
16293 #define A_MA_INT_ENABLE 0x77dc
16299 #define S_MEM_WRAP_INT_ENABLE    0
16307 #define A_MA_INT_CAUSE 0x77e0
16313 #define S_MEM_WRAP_INT_CAUSE    0
16321 #define A_MA_INT_WRAP_STATUS 0x77e4
16324 #define M_MEM_WRAP_ADDRESS    0xfffffffU
16328 #define S_MEM_WRAP_CLIENT_NUM    0
16329 #define M_MEM_WRAP_CLIENT_NUM    0xfU
16333 #define A_MA_TP_THREAD1_MAPPER 0x77e8
16335 #define S_TP_THREAD1_EN    0
16336 #define M_TP_THREAD1_EN    0xffU
16340 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
16342 #define S_SGE_THREAD1_EN    0
16343 #define M_SGE_THREAD1_EN    0xffU
16347 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
16473 #define S_CL0_PAR_RDQUEUE_ERROR_EN    0
16477 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
16478 #define A_MA_PARITY_ERROR_STATUS 0x77f4
16604 #define S_CL0_PAR_RDQUEUE_ERROR    0
16608 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
16609 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
16612 #define M_BONUS_REG    0x3ffffffU
16617 #define M_COHERANCY_CMD_TYPE    0x3U
16622 #define M_COHERANCY_THREAD_NUM    0x7U
16626 #define S_COHERANCY_ENABLE    0
16630 #define A_MA_ERROR_ENABLE 0x77fc
16632 #define S_UE_ENABLE    0
16637 #define M_FUTURE_EXPANSION    0x7fffffffU
16642 #define M_FUTURE_EXPANSION_EE    0x7fffffffU
16646 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
16652 #define S_ARB4_PAR_RDQUEUE_ERROR_EN    0
16656 #define A_MA_PARITY_ERROR_STATUS2 0x7804
16662 #define S_ARB4_PAR_RDQUEUE_ERROR    0
16666 #define A_MA_EXT_MEMORY1_BAR 0x7808
16669 #define M_EXT_MEM1_BASE    0xfffU
16673 #define S_EXT_MEM1_SIZE    0
16674 #define M_EXT_MEM1_SIZE    0xfffU
16678 #define A_MA_PMTX_THROTTLE 0x780c
16684 #define S_FL_LIMIT    0
16685 #define M_FL_LIMIT    0xffU
16689 #define A_MA_PMRX_THROTTLE 0x7810
16690 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
16691 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
16692 #define A_MA_ULPTX_WRDATA_CNT 0x781c
16693 #define A_MA_ULPRX_WRDATA_CNT 0x7820
16694 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
16695 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
16696 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
16697 #define A_MA_LE_WRDATA_CNT 0x7830
16698 #define A_MA_CIM_WRDATA_CNT 0x7834
16699 #define A_MA_PCIE_WRDATA_CNT 0x7838
16700 #define A_MA_PMTX_WRDATA_CNT 0x783c
16701 #define A_MA_PMRX_WRDATA_CNT 0x7840
16702 #define A_MA_HMA_WRDATA_CNT 0x7844
16703 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
16704 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
16705 #define A_MA_ULPTX_RDDATA_CNT 0x7850
16706 #define A_MA_ULPRX_RDDATA_CNT 0x7854
16707 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
16708 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
16709 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
16710 #define A_MA_LE_RDDATA_CNT 0x7864
16711 #define A_MA_CIM_RDDATA_CNT 0x7868
16712 #define A_MA_PCIE_RDDATA_CNT 0x786c
16713 #define A_MA_PMTX_RDDATA_CNT 0x7870
16714 #define A_MA_PMRX_RDDATA_CNT 0x7874
16715 #define A_MA_HMA_RDDATA_CNT 0x7878
16716 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
16717 #define A_MA_EXIT_ADDR_FAULT 0x787c
16719 #define S_EXIT_ADDR_FAULT    0
16723 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
16724 #define A_MA_DDR_DEVICE_CFG 0x7880
16727 #define M_MEM_WIDTH    0x7U
16731 #define S_DDR_MODE    0
16735 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
16736 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
16737 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
16738 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
16739 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
16740 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
16741 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
16742 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
16743 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
16744 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
16745 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
16746 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
16747 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
16748 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
16749 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
16750 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
16751 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
16752 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
16753 #define A_MA_TIMEOUT_CFG 0x78cc
16776 #define M_CLIENT    0xfU
16780 #define S_DELAY    0
16781 #define M_DELAY    0xffffU
16785 #define A_MA_TIMEOUT_CNT 0x78d0
16787 #define S_CNT_VAL    0
16788 #define M_CNT_VAL    0xffffU
16792 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
16795 #define M_FUTURE_CEXPANSION    0x7U
16852 #define M_FUTURE_DEXPANSION    0x7U
16904 #define S_CL0_WR_DATA_TO_EN    0
16909 #define M_FUTURE_CEXPANSION_WTE    0x7U
16914 #define M_FUTURE_DEXPANSION_WTE    0x7U
16918 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
17020 #define S_CL0_WR_DATA_TO_ERROR    0
17025 #define M_FUTURE_CEXPANSION_WTS    0x7U
17030 #define M_FUTURE_DEXPANSION_WTS    0x7U
17034 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
17136 #define S_CL0_RD_DATA_TO_EN    0
17141 #define M_FUTURE_CEXPANSION_RTE    0x7U
17146 #define M_FUTURE_DEXPANSION_RTE    0x7U
17150 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
17252 #define S_CL0_RD_DATA_TO_ERROR    0
17257 #define M_FUTURE_CEXPANSION_RTS    0x7U
17262 #define M_FUTURE_DEXPANSION_RTS    0x7U
17266 #define A_MA_BKP_CNT_SEL 0x78e4
17269 #define M_BKP_CNT_TYPE    0x3U
17274 #define M_BKP_CLIENT    0xfU
17278 #define A_MA_BKP_CNT 0x78e8
17279 #define A_MA_WRT_ARB 0x78ec
17286 #define M_WR_TIM    0xffU
17291 #define M_RD_WIN    0xffU
17295 #define S_WR_WIN    0
17296 #define M_WR_WIN    0xffU
17300 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
17303 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
17355 #define S_CL0_IF_PAR_EN    0
17360 #define M_FUTURE_DEXPANSION_IPE    0x7ffffU
17364 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
17367 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
17419 #define S_CL0_IF_PAR_ERROR    0
17424 #define M_FUTURE_DEXPANSION_IPS    0x7ffffU
17428 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
17443 #define M_DEBUGPAGE    0x7U
17447 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
17448 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
17463 #define M_CMDLEN0    0xffU
17468 #define M_CMDADDR0    0x1fffU
17488 #define S_RDDATA0    0
17489 #define M_RDDATA0    0xfU
17493 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
17508 #define M_CMDLEN1    0xffU
17513 #define M_CMDADDR1    0x1fffU
17533 #define S_RDDATA1    0
17534 #define M_RDDATA1    0xfU
17538 #define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
17553 #define M_CMDLEN2    0xffU
17558 #define M_CMDADDR2    0x1fffU
17578 #define S_RDDATA2    0
17579 #define M_RDDATA2    0xfU
17583 #define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
17598 #define M_CMDLEN3    0xffU
17603 #define M_CMDADDR3    0x1fffU
17623 #define S_RDDATA3    0
17624 #define M_RDDATA3    0xfU
17628 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
17643 #define M_CMDLEN4    0xffU
17648 #define M_CMDADDR4    0x1fffU
17668 #define S_RDDATA4    0
17669 #define M_RDDATA4    0xfU
17673 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
17688 #define M_CMDLEN5    0xffU
17693 #define M_CMDADDR5    0x1fffU
17713 #define S_RDDATA5    0
17714 #define M_RDDATA5    0xfU
17718 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
17733 #define M_CMDLEN6    0xffU
17738 #define M_CMDADDR6    0x1fffU
17758 #define S_RDDATA6    0
17759 #define M_RDDATA6    0xfU
17763 #define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
17778 #define M_CMDLEN7    0xffU
17783 #define M_CMDADDR7    0x1fffU
17803 #define S_RDDATA7    0
17804 #define M_RDDATA7    0xfU
17808 #define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
17823 #define M_CMDLEN8    0xffU
17828 #define M_CMDADDR8    0x1fffU
17848 #define S_RDDATA8    0
17849 #define M_RDDATA8    0xfU
17853 #define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
17868 #define M_CMDLEN9    0xffU
17873 #define M_CMDADDR9    0x1fffU
17893 #define S_RDDATA9    0
17894 #define M_RDDATA9    0xfU
17898 #define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
17913 #define M_CMDLEN10    0xffU
17918 #define M_CMDADDR10    0x1fffU
17938 #define S_RDDATA10    0
17939 #define M_RDDATA10    0xfU
17943 #define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
17958 #define M_CMDLEN11    0xffU
17963 #define M_CMDADDR11    0x1fffU
17983 #define S_RDDATA11    0
17984 #define M_RDDATA11    0xfU
17988 #define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
18003 #define M_CMDLEN12    0xffU
18008 #define M_CMDADDR12    0x1fffU
18028 #define S_RDDATA12    0
18029 #define M_RDDATA12    0xfU
18033 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
18159 #define S_DM0_CI7_RDATA_VLD    0
18163 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
18289 #define S_DM1_CI7_RDATA_VLD    0
18293 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
18419 #define S_DM2_CI7_RDATA_VLD    0
18423 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
18549 #define S_DM3_CI7_RDATA_VLD    0
18553 #define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
18554 #define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
18555 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
18637 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
18719 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
18801 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
18883 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
18886 #define M_CMD_IN_FIFO_CNT0    0x3U
18891 #define M_CMD_SPLIT_FIFO_CNT0    0x3U
18896 #define M_CMD_THROTTLE_FIFO_CNT0    0x3fU
18901 #define M_RD_CHNL_FIFO_CNT0    0x7fU
18906 #define M_RD_DATA_EXT_FIFO_CNT0    0x3U
18911 #define M_RD_DATA_512B_FIFO_CNT0    0xffU
18916 #define M_RD_REQ_TAG_FIFO_CNT0    0xfU
18920 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
18923 #define M_CMD_IN_FIFO_CNT1    0x3U
18928 #define M_CMD_SPLIT_FIFO_CNT1    0x3U
18933 #define M_CMD_THROTTLE_FIFO_CNT1    0x3fU
18938 #define M_RD_CHNL_FIFO_CNT1    0x7fU
18943 #define M_RD_DATA_EXT_FIFO_CNT1    0x3U
18948 #define M_RD_DATA_512B_FIFO_CNT1    0xffU
18953 #define M_RD_REQ_TAG_FIFO_CNT1    0xfU
18957 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
18960 #define M_CMD_IN_FIFO_CNT2    0x3U
18965 #define M_CMD_SPLIT_FIFO_CNT2    0x3U
18970 #define M_CMD_THROTTLE_FIFO_CNT2    0x3fU
18975 #define M_RD_CHNL_FIFO_CNT2    0x7fU
18980 #define M_RD_DATA_EXT_FIFO_CNT2    0x3U
18985 #define M_RD_DATA_512B_FIFO_CNT2    0xffU
18990 #define M_RD_REQ_TAG_FIFO_CNT2    0xfU
18994 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
18997 #define M_CMD_IN_FIFO_CNT3    0x3U
19002 #define M_CMD_SPLIT_FIFO_CNT3    0x3U
19007 #define M_CMD_THROTTLE_FIFO_CNT3    0x3fU
19012 #define M_RD_CHNL_FIFO_CNT3    0x7fU
19017 #define M_RD_DATA_EXT_FIFO_CNT3    0x3U
19022 #define M_RD_DATA_512B_FIFO_CNT3    0xffU
19027 #define M_RD_REQ_TAG_FIFO_CNT3    0xfU
19031 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
19034 #define M_CMD_IN_FIFO_CNT4    0x3U
19039 #define M_CMD_SPLIT_FIFO_CNT4    0x3U
19044 #define M_CMD_THROTTLE_FIFO_CNT4    0x3fU
19049 #define M_RD_CHNL_FIFO_CNT4    0x7fU
19054 #define M_RD_DATA_EXT_FIFO_CNT4    0x3U
19059 #define M_RD_DATA_512B_FIFO_CNT4    0xffU
19064 #define M_RD_REQ_TAG_FIFO_CNT4    0xfU
19068 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
19071 #define M_CMD_IN_FIFO_CNT5    0x3U
19076 #define M_CMD_SPLIT_FIFO_CNT5    0x3U
19081 #define M_CMD_THROTTLE_FIFO_CNT5    0x3fU
19086 #define M_RD_CHNL_FIFO_CNT5    0x7fU
19091 #define M_RD_DATA_EXT_FIFO_CNT5    0x3U
19096 #define M_RD_DATA_512B_FIFO_CNT5    0xffU
19101 #define M_RD_REQ_TAG_FIFO_CNT5    0xfU
19105 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
19108 #define M_CMD_IN_FIFO_CNT6    0x3U
19113 #define M_CMD_SPLIT_FIFO_CNT6    0x3U
19118 #define M_CMD_THROTTLE_FIFO_CNT6    0x3fU
19123 #define M_RD_CHNL_FIFO_CNT6    0x7fU
19128 #define M_RD_DATA_EXT_FIFO_CNT6    0x3U
19133 #define M_RD_DATA_512B_FIFO_CNT6    0xffU
19138 #define M_RD_REQ_TAG_FIFO_CNT6    0xfU
19142 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
19145 #define M_CMD_IN_FIFO_CNT7    0x3U
19150 #define M_CMD_SPLIT_FIFO_CNT7    0x3U
19155 #define M_CMD_THROTTLE_FIFO_CNT7    0x3fU
19160 #define M_RD_CHNL_FIFO_CNT7    0x7fU
19165 #define M_RD_DATA_EXT_FIFO_CNT7    0x3U
19170 #define M_RD_DATA_512B_FIFO_CNT7    0xffU
19175 #define M_RD_REQ_TAG_FIFO_CNT7    0xfU
19179 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
19182 #define M_CMD_IN_FIFO_CNT8    0x3U
19187 #define M_CMD_SPLIT_FIFO_CNT8    0x3U
19192 #define M_CMD_THROTTLE_FIFO_CNT8    0x3fU
19197 #define M_RD_CHNL_FIFO_CNT8    0x7fU
19202 #define M_RD_DATA_EXT_FIFO_CNT8    0x3U
19207 #define M_RD_DATA_512B_FIFO_CNT8    0xffU
19212 #define M_RD_REQ_TAG_FIFO_CNT8    0xfU
19216 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
19219 #define M_CMD_IN_FIFO_CNT9    0x3U
19224 #define M_CMD_SPLIT_FIFO_CNT9    0x3U
19229 #define M_CMD_THROTTLE_FIFO_CNT9    0x3fU
19234 #define M_RD_CHNL_FIFO_CNT9    0x7fU
19239 #define M_RD_DATA_EXT_FIFO_CNT9    0x3U
19244 #define M_RD_DATA_512B_FIFO_CNT9    0xffU
19249 #define M_RD_REQ_TAG_FIFO_CNT9    0xfU
19253 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
19256 #define M_CMD_IN_FIFO_CNT10    0x3U
19261 #define M_CMD_SPLIT_FIFO_CNT10    0x3U
19266 #define M_CMD_THROTTLE_FIFO_CNT10    0x3fU
19271 #define M_RD_CHNL_FIFO_CNT10    0x7fU
19276 #define M_RD_DATA_EXT_FIFO_CNT10    0x3U
19281 #define M_RD_DATA_512B_FIFO_CNT10    0xffU
19286 #define M_RD_REQ_TAG_FIFO_CNT10    0xfU
19290 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
19293 #define M_CMD_IN_FIFO_CNT11    0x3U
19298 #define M_CMD_SPLIT_FIFO_CNT11    0x3U
19303 #define M_CMD_THROTTLE_FIFO_CNT11    0x3fU
19308 #define M_RD_CHNL_FIFO_CNT11    0x7fU
19313 #define M_RD_DATA_EXT_FIFO_CNT11    0x3U
19318 #define M_RD_DATA_512B_FIFO_CNT11    0xffU
19323 #define M_RD_REQ_TAG_FIFO_CNT11    0xfU
19327 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
19330 #define M_CMD_IN_FIFO_CNT12    0x3U
19335 #define M_CMD_SPLIT_FIFO_CNT12    0x3U
19340 #define M_CMD_THROTTLE_FIFO_CNT12    0x3fU
19345 #define M_RD_CHNL_FIFO_CNT12    0x7fU
19350 #define M_RD_DATA_EXT_FIFO_CNT12    0x3U
19355 #define M_RD_DATA_512B_FIFO_CNT12    0xffU
19360 #define M_RD_REQ_TAG_FIFO_CNT12    0xfU
19364 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
19375 #define M_TGT_CMD_FIFO_CNT0    0x7U
19380 #define M_CLNT_NUM_FIFO_CNT0    0x7U
19385 #define M_WR_CMD_TAG_FIFO_CNT_TGT0    0xffU
19389 #define S_WR_DATA_512B_FIFO_CNT_TGT0    0
19390 #define M_WR_DATA_512B_FIFO_CNT_TGT0    0xffU
19394 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
19405 #define M_TGT_CMD_FIFO_CNT1    0x7U
19410 #define M_CLNT_NUM_FIFO_CNT1    0x7U
19415 #define M_WR_CMD_TAG_FIFO_CNT_TGT1    0xffU
19419 #define S_WR_DATA_512B_FIFO_CNT_TGT1    0
19420 #define M_WR_DATA_512B_FIFO_CNT_TGT1    0xffU
19424 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
19435 #define M_TGT_CMD_FIFO_CNT2    0x7U
19440 #define M_CLNT_NUM_FIFO_CNT2    0x7U
19445 #define M_WR_CMD_TAG_FIFO_CNT_TGT2    0xffU
19449 #define S_WR_DATA_512B_FIFO_CNT_TGT2    0
19450 #define M_WR_DATA_512B_FIFO_CNT_TGT2    0xffU
19454 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
19465 #define M_TGT_CMD_FIFO_CNT3    0x7U
19470 #define M_CLNT_NUM_FIFO_CNT3    0x7U
19475 #define M_WR_CMD_TAG_FIFO_CNT_TGT3    0xffU
19479 #define S_WR_DATA_512B_FIFO_CNT_TGT    0
19480 #define M_WR_DATA_512B_FIFO_CNT_TGT    0xffU
19484 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
19485 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
19486 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
19487 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
19488 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
19489 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
19490 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
19491 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
19492 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
19493 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
19494 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
19495 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
19496 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
19497 #define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
19498 #define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
19499 #define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
19500 #define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
19501 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
19502 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
19503 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
19504 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
19505 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
19506 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
19507 #define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
19508 #define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
19509 #define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
19510 #define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
19511 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
19512 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
19513 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
19514 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
19515 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
19516 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
19517 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
19518 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
19519 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
19520 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
19521 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
19522 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
19523 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
19524 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
19525 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
19526 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
19527 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
19528 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
19529 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
19530 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
19531 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
19532 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
19533 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
19534 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
19535 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
19536 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
19537 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
19538 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
19539 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
19540 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
19541 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
19542 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
19543 #define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
19544 #define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
19545 #define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
19546 #define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
19547 #define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
19548 #define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
19549 #define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
19550 #define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
19551 #define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
19552 #define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
19553 #define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
19554 #define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
19555 #define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
19556 #define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
19557 #define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
19558 #define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
19559 #define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
19560 #define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
19561 #define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
19562 #define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
19563 #define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
19564 #define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
19565 #define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
19566 #define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
19567 #define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
19568 #define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
19569 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
19570 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
19571 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
19572 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
19573 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
19574 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
19575 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
19576 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
19577 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
19578 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
19579 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
19580 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
19581 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
19582 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
19583 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
19584 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
19585 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
19586 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
19587 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
19588 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
19589 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
19590 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
19591 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
19592 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
19593 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
19594 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
19595 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
19598 #define M_WR_DATA_EXT_FIFO_CNT0    0x3U
19603 #define M_WR_CMD_TAG_FIFO_CNT0    0xfU
19608 #define M_WR_DATA_512B_FIFO_CNT0    0xffU
19633 #define M_CMD_SPLIT_FSM0    0x7U
19637 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
19640 #define M_WR_DATA_EXT_FIFO_CNT1    0x3U
19645 #define M_WR_CMD_TAG_FIFO_CNT1    0xfU
19650 #define M_WR_DATA_512B_FIFO_CNT1    0xffU
19675 #define M_CMD_SPLIT_FSM1    0x7U
19679 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
19682 #define M_WR_DATA_EXT_FIFO_CNT2    0x3U
19687 #define M_WR_CMD_TAG_FIFO_CNT2    0xfU
19692 #define M_WR_DATA_512B_FIFO_CNT2    0xffU
19717 #define M_CMD_SPLIT_FSM2    0x7U
19721 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
19724 #define M_WR_DATA_EXT_FIFO_CNT3    0x3U
19729 #define M_WR_CMD_TAG_FIFO_CNT3    0xfU
19734 #define M_WR_DATA_512B_FIFO_CNT3    0xffU
19759 #define M_CMD_SPLIT_FSM3    0x7U
19763 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
19766 #define M_WR_DATA_EXT_FIFO_CNT4    0x3U
19771 #define M_WR_CMD_TAG_FIFO_CNT4    0xfU
19776 #define M_WR_DATA_512B_FIFO_CNT4    0xffU
19801 #define M_CMD_SPLIT_FSM4    0x7U
19805 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
19808 #define M_WR_DATA_EXT_FIFO_CNT5    0x3U
19813 #define M_WR_CMD_TAG_FIFO_CNT5    0xfU
19818 #define M_WR_DATA_512B_FIFO_CNT5    0xffU
19843 #define M_CMD_SPLIT_FSM5    0x7U
19847 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
19850 #define M_WR_DATA_EXT_FIFO_CNT6    0x3U
19855 #define M_WR_CMD_TAG_FIFO_CNT6    0xfU
19860 #define M_WR_DATA_512B_FIFO_CNT6    0xffU
19885 #define M_CMD_SPLIT_FSM6    0x7U
19889 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
19892 #define M_WR_DATA_EXT_FIFO_CNT7    0x3U
19897 #define M_WR_CMD_TAG_FIFO_CNT7    0xfU
19902 #define M_WR_DATA_512B_FIFO_CNT7    0xffU
19927 #define M_CMD_SPLIT_FSM7    0x7U
19931 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
19934 #define M_WR_DATA_EXT_FIFO_CNT8    0x3U
19939 #define M_WR_CMD_TAG_FIFO_CNT8    0xfU
19944 #define M_WR_DATA_512B_FIFO_CNT8    0xffU
19969 #define M_CMD_SPLIT_FSM8    0x7U
19973 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
19976 #define M_WR_DATA_EXT_FIFO_CNT9    0x3U
19981 #define M_WR_CMD_TAG_FIFO_CNT9    0xfU
19986 #define M_WR_DATA_512B_FIFO_CNT9    0xffU
20011 #define M_CMD_SPLIT_FSM9    0x7U
20015 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
20018 #define M_WR_DATA_EXT_FIFO_CNT10    0x3U
20023 #define M_WR_CMD_TAG_FIFO_CNT10    0xfU
20028 #define M_WR_DATA_512B_FIFO_CNT10    0xffU
20053 #define M_CMD_SPLIT_FSM10    0x7U
20057 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
20060 #define M_WR_DATA_EXT_FIFO_CNT11    0x3U
20065 #define M_WR_CMD_TAG_FIFO_CNT11    0xfU
20070 #define M_WR_DATA_512B_FIFO_CNT11    0xffU
20095 #define M_CMD_SPLIT_FSM11    0x7U
20099 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
20102 #define M_WR_DATA_EXT_FIFO_CNT12    0x3U
20107 #define M_WR_CMD_TAG_FIFO_CNT12    0xfU
20112 #define M_WR_DATA_512B_FIFO_CNT12    0xffU
20137 #define M_CMD_SPLIT_FSM12    0x7U
20141 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
20144 #define M_RD_CMD_TAG_FIFO_CNT0    0xffU
20148 #define S_RD_DATA_FIFO_CNT0    0
20149 #define M_RD_DATA_FIFO_CNT0    0xffU
20153 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
20156 #define M_RD_CMD_TAG_FIFO_CNT1    0xffU
20160 #define S_RD_DATA_FIFO_CNT1    0
20161 #define M_RD_DATA_FIFO_CNT1    0xffU
20165 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
20168 #define M_RD_CMD_TAG_FIFO_CNT2    0xffU
20172 #define S_RD_DATA_FIFO_CNT2    0
20173 #define M_RD_DATA_FIFO_CNT2    0xffU
20177 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
20180 #define M_RD_CMD_TAG_FIFO_CNT3    0xffU
20184 #define S_RD_DATA_FIFO_CNT3    0
20185 #define M_RD_DATA_FIFO_CNT3    0xffU
20189 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
20190 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
20191 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
20192 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
20193 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
20194 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
20195 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
20196 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
20197 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
20198 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
20199 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
20200 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
20201 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
20202 #define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
20203 #define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
20204 #define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
20205 #define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
20206 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
20207 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
20208 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
20209 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
20210 #define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
20211 #define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
20212 #define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
20213 #define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
20214 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
20215 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
20216 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
20217 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
20218 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
20219 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
20220 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
20221 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
20222 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
20223 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
20224 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
20225 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
20226 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
20227 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
20228 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
20229 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
20230 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
20231 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
20232 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
20233 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
20234 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
20235 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
20236 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
20237 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
20238 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
20239 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
20240 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
20241 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
20242 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
20243 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
20244 #define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
20250 #define S_PTFLITCNT    0
20251 #define M_PTFLITCNT    0xffU
20255 #define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
20261 #define S_PRFLITCNT    0
20262 #define M_PRFLITCNT    0xffU
20267 #define EDC_0_BASE_ADDR 0x7900
20269 #define A_EDC_REF 0x7900
20283 #define S_REFFREQ    0
20284 #define M_REFFREQ    0xffffU
20288 #define A_EDC_BIST_CMD 0x7904
20289 #define A_EDC_BIST_CMD_ADDR 0x7908
20290 #define A_EDC_BIST_CMD_LEN 0x790c
20291 #define A_EDC_BIST_DATA_PATTERN 0x7910
20292 #define A_EDC_BIST_USER_WDATA0 0x7914
20293 #define A_EDC_BIST_USER_WDATA1 0x7918
20294 #define A_EDC_BIST_USER_WDATA2 0x791c
20295 #define A_EDC_BIST_NUM_ERR 0x7920
20296 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
20297 #define A_EDC_BIST_STATUS_RDATA 0x7928
20298 #define A_EDC_PAR_ENABLE 0x7970
20308 #define A_EDC_INT_ENABLE 0x7974
20309 #define A_EDC_INT_CAUSE 0x7978
20323 #define A_EDC_ECC_STATUS 0x797c
20326 #define EDC_1_BASE_ADDR 0x7980
20329 #define HMA_BASE_ADDR 0x7a00
20332 #define CIM_BASE_ADDR 0x7b00
20334 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
20337 #define M_VFMBGENERIC    0xfU
20341 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
20343 #define S_MBVFREADY    0
20347 #define A_CIM_PF_MAILBOX_DATA 0x240
20348 #define A_CIM_PF_MAILBOX_CTRL 0x280
20351 #define M_MBGENERIC    0xfffffffU
20363 #define S_MBOWNER    0
20364 #define M_MBOWNER    0x3U
20368 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
20374 #define A_CIM_PF_HOST_INT_ENABLE 0x288
20380 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
20386 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
20387 #define A_CIM_BOOT_CFG 0x7b00
20390 #define M_BOOTADDR    0xffffffU
20395 #define M_UPGEN    0x3fU
20403 #define S_UPCRST    0
20407 #define A_CIM_FLASH_BASE_ADDR 0x7b04
20410 #define M_FLASHBASEADDR    0x3ffffU
20414 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
20417 #define M_FLASHADDRSIZE    0xfffffU
20421 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
20424 #define M_EEPROMBASEADDR    0x3ffffU
20428 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
20431 #define M_EEPROMADDRSIZE    0xfffffU
20435 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
20438 #define M_SDRAMBASEADDR    0x3ffffffU
20442 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
20445 #define M_SDRAMADDRSIZE    0xfffffffU
20449 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
20452 #define M_EXTMEM2BASEADDR    0x3ffffffU
20456 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
20459 #define M_EXTMEM2ADDRSIZE    0xfffffffU
20463 #define A_CIM_UP_SPARE_INT 0x7b24
20473 #define S_UPSPAREINT    0
20474 #define M_UPSPAREINT    0x7U
20478 #define A_CIM_HOST_INT_ENABLE 0x7b28
20596 #define A_CIM_HOST_INT_CAUSE 0x7b2c
20618 #define S_UPACCNONZERO    0
20622 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
20744 #define S_RSVDSPACEINTEN    0
20748 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
20870 #define S_RSVDSPACEINT    0
20874 #define A_CIM_UP_INT_ENABLE 0x7b38
20880 #define A_CIM_UP_INT_CAUSE 0x7b3c
20886 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
20887 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
20888 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
20898 #define S_QUENUMSELECT    0
20899 #define M_QUENUMSELECT    0x7U
20903 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
20906 #define M_CIMQSIZE    0x3fU
20911 #define M_CIMQBASE    0x3fU
20919 #define S_QUEFULLTHRSH    0
20920 #define M_QUEFULLTHRSH    0x1ffU
20928 #define A_CIM_HOST_ACC_CTRL 0x7b50
20938 #define S_HOSTADDR    0
20939 #define M_HOSTADDR    0xffffU
20943 #define A_CIM_HOST_ACC_DATA 0x7b54
20944 #define A_CIM_CDEBUGDATA 0x7b58
20947 #define M_CDEBUGDATAH    0xffffU
20951 #define S_CDEBUGDATAL    0
20952 #define M_CDEBUGDATAL    0xffffU
20956 #define A_CIM_IBQ_DBG_CFG 0x7b60
20959 #define M_IBQDBGADDR    0xfffU
20971 #define S_IBQDBGEN    0
20975 #define A_CIM_OBQ_DBG_CFG 0x7b64
20978 #define M_OBQDBGADDR    0xfffU
20990 #define S_OBQDBGEN    0
20994 #define A_CIM_IBQ_DBG_DATA 0x7b68
20995 #define A_CIM_OBQ_DBG_DATA 0x7b6c
20996 #define A_CIM_DEBUGCFG 0x7b70
20999 #define M_POLADBGRDPTR    0x1ffU
21004 #define M_PILADBGRDPTR    0x1ffU
21025 #define M_DEBUGSELH    0x1fU
21029 #define S_DEBUGSELL    0
21030 #define M_DEBUGSELL    0x1fU
21034 #define A_CIM_DEBUGSTS 0x7b74
21041 #define M_POLADBGWRPTR    0x1ffU
21045 #define S_PILADBGWRPTR    0
21046 #define M_PILADBGWRPTR    0x1ffU
21050 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
21051 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
21052 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
21053 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
21054 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
21055 #define A_CIM_MEM_ZONE0_VA 0x7b90
21058 #define M_MEM_ZONE_VA    0xfffffffU
21062 #define A_CIM_MEM_ZONE0_BA 0x7b94
21065 #define M_MEM_ZONE_BA    0x3ffffffU
21073 #define S_ZONE_DST    0
21074 #define M_ZONE_DST    0x3U
21078 #define A_CIM_MEM_ZONE0_LEN 0x7b98
21081 #define M_MEM_ZONE_LEN    0xfffffffU
21085 #define A_CIM_MEM_ZONE1_VA 0x7b9c
21086 #define A_CIM_MEM_ZONE1_BA 0x7ba0
21087 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
21088 #define A_CIM_MEM_ZONE2_VA 0x7ba8
21089 #define A_CIM_MEM_ZONE2_BA 0x7bac
21090 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
21091 #define A_CIM_MEM_ZONE3_VA 0x7bb4
21092 #define A_CIM_MEM_ZONE3_BA 0x7bb8
21093 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
21094 #define A_CIM_MEM_ZONE4_VA 0x7bc0
21095 #define A_CIM_MEM_ZONE4_BA 0x7bc4
21096 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
21097 #define A_CIM_MEM_ZONE5_VA 0x7bcc
21098 #define A_CIM_MEM_ZONE5_BA 0x7bd0
21099 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
21100 #define A_CIM_MEM_ZONE6_VA 0x7bd8
21101 #define A_CIM_MEM_ZONE6_BA 0x7bdc
21102 #define A_CIM_MEM_ZONE6_LEN 0x7be0
21103 #define A_CIM_MEM_ZONE7_VA 0x7be4
21104 #define A_CIM_MEM_ZONE7_BA 0x7be8
21105 #define A_CIM_MEM_ZONE7_LEN 0x7bec
21106 #define A_CIM_BOOT_LEN 0x7bf0
21109 #define M_BOOTLEN    0xfffffffU
21113 #define A_CIM_GLB_TIMER_CTL 0x7bf4
21127 #define A_CIM_GLB_TIMER 0x7bf8
21128 #define A_CIM_GLB_TIMER_TICK 0x7bfc
21130 #define S_GLBLTTICK    0
21131 #define M_GLBLTTICK    0xffffU
21135 #define A_CIM_TIMER0 0x7c00
21136 #define A_CIM_TIMER1 0x7c04
21137 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
21140 #define M_DADDRTIMEOUT    0x3fffffffU
21144 #define S_DADDRTIMEOUTTYPE    0
21145 #define M_DADDRTIMEOUTTYPE    0x3U
21149 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
21152 #define M_DADDRILLEGAL    0x3fffffffU
21156 #define S_DADDRILLEGALTYPE    0
21157 #define M_DADDRILLEGALTYPE    0x3U
21161 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
21163 #define S_DPIFHOSTMASK    0
21164 #define M_DPIFHOSTMASK    0x1fffffU
21168 #define S_T5_DPIFHOSTMASK    0
21169 #define M_T5_DPIFHOSTMASK    0x1fffffffU
21173 #define S_T6_T5_DPIFHOSTMASK    0
21174 #define M_T6_T5_DPIFHOSTMASK    0x3fffffffU
21178 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
21180 #define S_DPIFHUPAMASK    0
21181 #define M_DPIFHUPAMASK    0x7fffffffU
21185 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
21187 #define S_DUPMASK    0
21188 #define M_DUPMASK    0x1fffffU
21192 #define S_T5_DUPMASK    0
21193 #define M_T5_DUPMASK    0x1fffffffU
21197 #define S_T6_T5_DUPMASK    0
21198 #define M_T6_T5_DUPMASK    0x3fffffffU
21202 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
21204 #define S_DUPUACCMASK    0
21205 #define M_DUPUACCMASK    0x7fffffffU
21209 #define A_CIM_PERR_INJECT 0x7c20
21210 #define A_CIM_PERR_ENABLE 0x7c24
21212 #define S_PERREN    0
21213 #define M_PERREN    0x1fffffU
21217 #define S_T5_PERREN    0
21218 #define M_T5_PERREN    0x1fffffffU
21222 #define S_T6_T5_PERREN    0
21223 #define M_T6_T5_PERREN    0x3fffffffU
21227 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
21229 #define S_EEPROMBUSY    0
21233 #define A_CIM_MA_TIMER_EN 0x7c2c
21235 #define S_MA_TIMER_ENABLE    0
21243 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
21245 #define S_UP_PO_SINGLE_OUTSTANDING    0
21249 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
21250 #define A_CIM_UP_OPERATION_FREQ 0x7c38
21251 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
21254 #define M_CIM_ULP_TX_PKT_ERR_CODE    0xffU
21259 #define M_CIM_SGE1_PKT_ERR_CODE    0xffU
21263 #define S_CIM_SGE0_PKT_ERR_CODE    0
21264 #define M_CIM_SGE0_PKT_ERR_CODE    0xffU
21269 #define M_CIM_PCIE_PKT_ERR_CODE    0xffU
21273 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
21274 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
21276 #define S_PIO_UP_MST_CFG_SEL    0
21280 #define A_CIM_CGEN 0x7c48
21282 #define S_TSCH_CGEN    0
21286 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
21304 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL    0
21312 #define A_CIM_CGEN_GLOBAL 0x7c50
21314 #define S_CGEN_GLOBAL    0
21318 #define A_CIM_DPSLP_EN 0x7c54
21320 #define S_PIFDBGLA_DPSLP_EN    0
21325 #define TP_BASE_ADDR 0x7d00
21327 #define A_TP_IN_CONFIG 0x7d00
21429 #define S_CTUNNEL    0
21493 #define S_CFASTDEMUXEN    0
21497 #define A_TP_OUT_CONFIG 0x7d04
21500 #define M_PORTQFCEN    0xfU
21584 #define S_CETHERNET    0
21616 #define A_TP_GLOBAL_CONFIG 0x7d08
21619 #define M_SYNCOOKIEPARAMS    0x3fU
21652 #define M_FIVETUPLELOOKUP    0x3U
21685 #define M_TCAMSERVERUSE    0x3U
21689 #define S_IPTTL    0
21690 #define M_IPTTL    0xffU
21706 #define A_TP_DB_CONFIG 0x7d0c
21709 #define M_DBMAXOPCNT    0xffU
21718 #define M_CXMAXOPCNT    0x7fU
21727 #define M_TXMAXOPCNT    0x7fU
21735 #define S_RXMAXOPCNT    0
21736 #define M_RXMAXOPCNT    0x7fU
21740 #define A_TP_CMM_TCB_BASE 0x7d10
21741 #define A_TP_CMM_MM_BASE 0x7d14
21742 #define A_TP_CMM_TIMER_BASE 0x7d18
21743 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
21746 #define M_RXPOOLSIZE    0xffffU
21750 #define S_TXPOOLSIZE    0
21751 #define M_TXPOOLSIZE    0xffffU
21755 #define A_TP_PMM_TX_BASE 0x7d20
21756 #define A_TP_PMM_DEFRAG_BASE 0x7d24
21757 #define A_TP_PMM_RX_BASE 0x7d28
21758 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
21759 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
21765 #define S_PMRXMAXPAGE    0
21766 #define M_PMRXMAXPAGE    0x1fffffU
21770 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
21771 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
21774 #define M_PMTXNUMCHN    0x3U
21778 #define S_PMTXMAXPAGE    0
21779 #define M_PMTXMAXPAGE    0x1fffffU
21783 #define A_TP_TCP_OPTIONS 0x7d40
21786 #define M_MTUDEFAULT    0xffffU
21803 #define M_SACKMODE    0x3U
21808 #define M_WINDOWSCALEMODE    0x3U
21812 #define S_TIMESTAMPSMODE    0
21813 #define M_TIMESTAMPSMODE    0x3U
21817 #define A_TP_DACK_CONFIG 0x7d44
21820 #define M_AUTOSTATE3    0x3U
21825 #define M_AUTOSTATE2    0x3U
21830 #define M_AUTOSTATE1    0x3U
21835 #define M_BYTETHRESHOLD    0x3ffffU
21840 #define M_MSSTHRESHOLD    0x7U
21852 #define S_MODE    0
21856 #define A_TP_PC_CONFIG 0x7d48
21982 #define S_TXDATAACKPAGEENABLE    0
22002 #define A_TP_PC_CONFIG2 0x7d4c
22128 #define S_ENABLETNLOFDCLOSED    0
22136 #define A_TP_TCP_BACKOFF_REG0 0x7d50
22139 #define M_TIMERBACKOFFINDEX3    0xffU
22144 #define M_TIMERBACKOFFINDEX2    0xffU
22149 #define M_TIMERBACKOFFINDEX1    0xffU
22153 #define S_TIMERBACKOFFINDEX0    0
22154 #define M_TIMERBACKOFFINDEX0    0xffU
22158 #define A_TP_TCP_BACKOFF_REG1 0x7d54
22161 #define M_TIMERBACKOFFINDEX7    0xffU
22166 #define M_TIMERBACKOFFINDEX6    0xffU
22171 #define M_TIMERBACKOFFINDEX5    0xffU
22175 #define S_TIMERBACKOFFINDEX4    0
22176 #define M_TIMERBACKOFFINDEX4    0xffU
22180 #define A_TP_TCP_BACKOFF_REG2 0x7d58
22183 #define M_TIMERBACKOFFINDEX11    0xffU
22188 #define M_TIMERBACKOFFINDEX10    0xffU
22193 #define M_TIMERBACKOFFINDEX9    0xffU
22197 #define S_TIMERBACKOFFINDEX8    0
22198 #define M_TIMERBACKOFFINDEX8    0xffU
22202 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
22205 #define M_TIMERBACKOFFINDEX15    0xffU
22210 #define M_TIMERBACKOFFINDEX14    0xffU
22215 #define M_TIMERBACKOFFINDEX13    0xffU
22219 #define S_TIMERBACKOFFINDEX12    0
22220 #define M_TIMERBACKOFFINDEX12    0xffU
22224 #define A_TP_PARA_REG0 0x7d60
22231 #define M_INITCWND    0x7U
22236 #define M_DUPACKTHRESH    0xfU
22261 #define M_TSMPMODE    0x3U
22266 #define M_BYTECOUNTLIMIT    0x3U
22282 #define S_SWSTIMER    0
22287 #define M_LIMTXTHRESH    0xfU
22308 #define M_ECNTHRESH    0x3U
22324 #define A_TP_PARA_REG1 0x7d64
22327 #define M_INITRWND    0xffffU
22331 #define S_INITIALSSTHRESH    0
22332 #define M_INITIALSSTHRESH    0xffffU
22336 #define A_TP_PARA_REG2 0x7d68
22339 #define M_MAXRXDATA    0xffffU
22343 #define S_RXCOALESCESIZE    0
22344 #define M_RXCOALESCESIZE    0xffffU
22348 #define A_TP_PARA_REG3 0x7d6c
22399 #define M_TXDATAACKIDX    0xfU
22404 #define M_RXFRAGENABLE    0x7U
22441 #define M_CNGCTRLMODE    0x3U
22449 #define S_RXCOALESCEPSHEN    0
22453 #define A_TP_PARA_REG4 0x7d70
22456 #define M_HIGHSPEEDCFG    0xffU
22461 #define M_NEWRENOCFG    0xffU
22466 #define M_TAHOECFG    0xffU
22470 #define S_RENOCFG    0
22471 #define M_RENOCFG    0xffU
22484 #define M_OVERDRIVEHIGHSPEED    0x3U
22501 #define M_OVERDRIVENEWRENO    0x3U
22518 #define M_OVERDRIVETAHOE    0x3U
22535 #define M_OVERDRIVERENO    0x3U
22539 #define S_BYTECOUNTRENO    0
22543 #define A_TP_PARA_REG5 0x7d74
22546 #define M_INDICATESIZE    0xffffU
22551 #define M_MAXPROXYSIZE    0xfU
22587 #define S_PUSHTIMERENABLE    0
22611 #define A_TP_PARA_REG6 0x7d78
22614 #define M_TXPDUSIZEADJ    0xffU
22623 #define M_LIMITEDTRANSMIT    0xfU
22703 #define S_DISABLEPDUXMT    0
22719 #define A_TP_PARA_REG7 0x7d7c
22722 #define M_PMMAXXFERLEN1    0xffffU
22726 #define S_PMMAXXFERLEN0    0
22727 #define M_PMMAXXFERLEN0    0xffffU
22731 #define A_TP_ENG_CONFIG 0x7d80
22734 #define M_TABLELATENCYDONE    0xfU
22739 #define M_TABLELATENCYSTART    0xfU
22744 #define M_ENGINELATENCYDELTA    0xfU
22749 #define M_ENGINELATENCYMMGR    0xfU
22754 #define M_ENGINELATENCYWIREIP6    0xfU
22759 #define M_ENGINELATENCYWIRE    0xfU
22763 #define S_ENGINELATENCYBASE    0
22764 #define M_ENGINELATENCYBASE    0xfU
22768 #define A_TP_PARA_REG8 0x7d84
22778 #define S_ECNSYNECT    0
22782 #define A_TP_ERR_CONFIG 0x7d8c
22884 #define S_DROPERRORANY    0
22912 #define A_TP_TIMER_RESOLUTION 0x7d90
22915 #define M_TIMERRESOLUTION    0xffU
22920 #define M_TIMESTAMPRESOLUTION    0xffU
22924 #define S_DELAYEDACKRESOLUTION    0
22925 #define M_DELAYEDACKRESOLUTION    0xffU
22929 #define A_TP_MSL 0x7d94
22931 #define S_MSL    0
22932 #define M_MSL    0x3fffffffU
22936 #define A_TP_RXT_MIN 0x7d98
22938 #define S_RXTMIN    0
22939 #define M_RXTMIN    0x3fffffffU
22943 #define A_TP_RXT_MAX 0x7d9c
22945 #define S_RXTMAX    0
22946 #define M_RXTMAX    0x3fffffffU
22950 #define A_TP_PERS_MIN 0x7da0
22952 #define S_PERSMIN    0
22953 #define M_PERSMIN    0x3fffffffU
22957 #define A_TP_PERS_MAX 0x7da4
22959 #define S_PERSMAX    0
22960 #define M_PERSMAX    0x3fffffffU
22964 #define A_TP_KEEP_IDLE 0x7da8
22966 #define S_KEEPALIVEIDLE    0
22967 #define M_KEEPALIVEIDLE    0x3fffffffU
22971 #define A_TP_KEEP_INTVL 0x7dac
22973 #define S_KEEPALIVEINTVL    0
22974 #define M_KEEPALIVEINTVL    0x3fffffffU
22978 #define A_TP_INIT_SRTT 0x7db0
22981 #define M_MAXRTT    0xffffU
22985 #define S_INITSRTT    0
22986 #define M_INITSRTT    0xffffU
22990 #define A_TP_DACK_TIMER 0x7db4
22992 #define S_DACKTIME    0
22993 #define M_DACKTIME    0xfffU
22997 #define A_TP_FINWAIT2_TIMER 0x7db8
22999 #define S_FINWAIT2TIME    0
23000 #define M_FINWAIT2TIME    0x3fffffffU
23004 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
23006 #define S_FASTFINWAIT2TIME    0
23007 #define M_FASTFINWAIT2TIME    0x3fffffffU
23011 #define A_TP_SHIFT_CNT 0x7dc0
23014 #define M_SYNSHIFTMAX    0xffU
23019 #define M_RXTSHIFTMAXR1    0xfU
23024 #define M_RXTSHIFTMAXR2    0xfU
23029 #define M_PERSHIFTBACKOFFMAX    0xfU
23034 #define M_PERSHIFTMAX    0xfU
23039 #define M_KEEPALIVEMAXR1    0xfU
23043 #define S_KEEPALIVEMAXR2    0
23044 #define M_KEEPALIVEMAXR2    0xfU
23049 #define M_T6_SYNSHIFTMAX    0xfU
23053 #define A_TP_TM_CONFIG 0x7dc4
23055 #define S_CMTIMERMAXNUM    0
23056 #define M_CMTIMERMAXNUM    0x7U
23060 #define A_TP_TIME_LO 0x7dc8
23061 #define A_TP_TIME_HI 0x7dcc
23062 #define A_TP_PORT_MTU_0 0x7dd0
23065 #define M_PORT1MTUVALUE    0xffffU
23069 #define S_PORT0MTUVALUE    0
23070 #define M_PORT0MTUVALUE    0xffffU
23074 #define A_TP_PORT_MTU_1 0x7dd4
23077 #define M_PORT3MTUVALUE    0xffffU
23081 #define S_PORT2MTUVALUE    0
23082 #define M_PORT2MTUVALUE    0xffffU
23086 #define A_TP_PACE_TABLE 0x7dd8
23087 #define A_TP_CCTRL_TABLE 0x7ddc
23090 #define M_ROWINDEX    0xffffU
23094 #define S_ROWVALUE    0
23095 #define M_ROWVALUE    0xffffU
23099 #define A_TP_MTU_TABLE 0x7de4
23102 #define M_MTUINDEX    0xffU
23107 #define M_MTUWIDTH    0xfU
23111 #define S_MTUVALUE    0
23112 #define M_MTUVALUE    0x3fffU
23116 #define A_TP_ULP_TABLE 0x7de8
23119 #define M_ULPTYPE7FIELD    0xfU
23124 #define M_ULPTYPE6FIELD    0xfU
23129 #define M_ULPTYPE5FIELD    0xfU
23134 #define M_ULPTYPE4FIELD    0xfU
23139 #define M_ULPTYPE3FIELD    0xfU
23144 #define M_ULPTYPE2FIELD    0xfU
23149 #define M_ULPTYPE1FIELD    0xfU
23153 #define S_ULPTYPE0FIELD    0
23154 #define M_ULPTYPE0FIELD    0xfU
23163 #define M_ULPTYPE7OFFSET    0x7U
23172 #define M_ULPTYPE6OFFSET    0x7U
23181 #define M_ULPTYPE5OFFSET    0x7U
23190 #define M_ULPTYPE4OFFSET    0x7U
23199 #define M_ULPTYPE3OFFSET    0x7U
23208 #define M_ULPTYPE2OFFSET    0x7U
23217 #define M_ULPTYPE1OFFSET    0x7U
23225 #define S_ULPTYPE0OFFSET    0
23226 #define M_ULPTYPE0OFFSET    0x7U
23230 #define A_TP_RSS_LKP_TABLE 0x7dec
23237 #define M_LKPTBLROWIDX    0x3ffU
23242 #define M_LKPTBLQUEUE1    0x3ffU
23246 #define S_LKPTBLQUEUE0    0
23247 #define M_LKPTBLQUEUE0    0x3ffU
23252 #define M_T6_LKPTBLROWIDX    0x7ffU
23256 #define A_TP_RSS_CONFIG 0x7df0
23366 #define S_DISABLE    0
23386 #define A_TP_RSS_CONFIG_TNL 0x7df4
23389 #define M_MASKSIZE    0xfU
23394 #define M_MASKFILTER    0x7ffU
23398 #define S_USEWIRECH    0
23410 #define A_TP_RSS_CONFIG_OFD 0x7df8
23417 #define M_RRCPLQUEWIDTH    0xfU
23422 #define M_FRMWRQUEMASK    0xfU
23426 #define A_TP_RSS_CONFIG_SYN 0x7dfc
23427 #define A_TP_RSS_CONFIG_VRT 0x7e00
23454 #define M_HASHDELAY    0xfU
23459 #define M_VFWRADDR    0x7fU
23464 #define M_KEYMODE    0x3U
23476 #define S_KEYWRADDR    0
23477 #define M_KEYWRADDR    0xfU
23490 #define M_KEYWRADDRX    0x3U
23499 #define M_T6_VFWRADDR    0xffU
23503 #define A_TP_RSS_CONFIG_CNG 0x7e04
23593 #define S_QUEUE    0
23594 #define M_QUEUE    0x3ffU
23598 #define A_TP_LA_TABLE_0 0x7e10
23601 #define M_VIRTPORT1TABLE    0xffffU
23605 #define S_VIRTPORT0TABLE    0
23606 #define M_VIRTPORT0TABLE    0xffffU
23610 #define A_TP_LA_TABLE_1 0x7e14
23613 #define M_VIRTPORT3TABLE    0xffffU
23617 #define S_VIRTPORT2TABLE    0
23618 #define M_VIRTPORT2TABLE    0xffffU
23622 #define A_TP_TM_PIO_ADDR 0x7e18
23623 #define A_TP_TM_PIO_DATA 0x7e1c
23624 #define A_TP_MOD_CONFIG 0x7e24
23627 #define M_RXCHANNELWEIGHT1    0xffU
23632 #define M_RXCHANNELWEIGHT0    0xffU
23637 #define M_TIMERMODE    0xffU
23641 #define S_TXCHANNELXOFFEN    0
23642 #define M_TXCHANNELXOFFEN    0xfU
23646 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
23649 #define M_RX_MOD_WEIGHT    0xffU
23654 #define M_TX_MOD_WEIGHT    0xffU
23658 #define S_TX_MOD_QUEUE_REQ_MAP    0
23659 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
23663 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
23666 #define M_TX_MODQ_WEIGHT7    0xffU
23671 #define M_TX_MODQ_WEIGHT6    0xffU
23676 #define M_TX_MODQ_WEIGHT5    0xffU
23680 #define S_TX_MODQ_WEIGHT4    0
23681 #define M_TX_MODQ_WEIGHT4    0xffU
23685 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
23688 #define M_TX_MODQ_WEIGHT3    0xffU
23693 #define M_TX_MODQ_WEIGHT2    0xffU
23698 #define M_TX_MODQ_WEIGHT1    0xffU
23702 #define S_TX_MODQ_WEIGHT0    0
23703 #define M_TX_MODQ_WEIGHT0    0xffU
23707 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
23708 #define A_TP_MOD_RATE_LIMIT 0x7e38
23711 #define M_RX_MOD_RATE_LIMIT_INC    0xffU
23716 #define M_RX_MOD_RATE_LIMIT_TICK    0xffU
23721 #define M_TX_MOD_RATE_LIMIT_INC    0xffU
23725 #define S_TX_MOD_RATE_LIMIT_TICK    0
23726 #define M_TX_MOD_RATE_LIMIT_TICK    0xffU
23730 #define A_TP_PIO_ADDR 0x7e40
23731 #define A_TP_PIO_DATA 0x7e44
23732 #define A_TP_RESET 0x7e4c
23738 #define S_TPRESET    0
23742 #define A_TP_MIB_INDEX 0x7e50
23743 #define A_TP_MIB_DATA 0x7e54
23744 #define A_TP_SYNC_TIME_HI 0x7e58
23745 #define A_TP_SYNC_TIME_LO 0x7e5c
23746 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
23747 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
23748 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
23749 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
23751 #define S_CMMAXPSTRUCT    0
23752 #define M_CMMAXPSTRUCT    0x1fffffU
23756 #define A_TP_INT_ENABLE 0x7e70
23878 #define S_DELINVFIFOPERR    0
23890 #define A_TP_INT_CAUSE 0x7e74
23891 #define A_TP_PER_ENABLE 0x7e78
23892 #define A_TP_FLM_FREE_PS_CNT 0x7e80
23894 #define S_FREEPSTRUCTCOUNT    0
23895 #define M_FREEPSTRUCTCOUNT    0x1fffffU
23899 #define A_TP_FLM_FREE_RX_CNT 0x7e84
23905 #define S_FREERXPAGECOUNT    0
23906 #define M_FREERXPAGECOUNT    0x1fffffU
23910 #define A_TP_FLM_FREE_TX_CNT 0x7e88
23913 #define M_FREETXPAGECHN    0x3U
23917 #define S_FREETXPAGECOUNT    0
23918 #define M_FREETXPAGECOUNT    0x1fffffU
23922 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
23923 #define A_TP_TM_HEAP_POP_CNT 0x7e90
23924 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
23925 #define A_TP_TM_DACK_POP_CNT 0x7e98
23926 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
23927 #define A_TP_MOD_POP_CNT 0x7ea0
23928 #define A_TP_TIMER_SEPARATOR 0x7ea4
23931 #define M_TIMERSEPARATOR    0xffffU
23935 #define S_DISABLETIMEFREEZE    0
23939 #define A_TP_STAMP_TIME 0x7ea8
23940 #define A_TP_DEBUG_FLAGS 0x7eac
24030 #define S_TXRCVADVLTMSS    0
24046 #define A_TP_RX_SCHED 0x7eb0
24065 #define M_ENABLELPBKFULL1    0x3U
24070 #define M_ENABLELPBKFULL0    0x3U
24075 #define M_ENABLEFIFOFULL1    0x3U
24080 #define M_ENABLEPCMDFULL1    0x3U
24085 #define M_ENABLEHDRFULL1    0x3U
24090 #define M_ENABLEFIFOFULL0    0x3U
24095 #define M_ENABLEPCMDFULL0    0x3U
24100 #define M_ENABLEHDRFULL0    0x3U
24105 #define M_COMMITLIMIT1    0x3fU
24109 #define S_COMMITLIMIT0    0
24110 #define M_COMMITLIMIT0    0x3fU
24114 #define A_TP_TX_SCHED 0x7eb4
24149 #define M_COMMITLIMIT3    0x3fU
24154 #define M_COMMITLIMIT2    0x3fU
24158 #define A_TP_FX_SCHED 0x7eb8
24228 #define S_RXMODXOFF0    0
24232 #define A_TP_TX_ORATE 0x7ebc
24235 #define M_OFDRATE3    0xffU
24240 #define M_OFDRATE2    0xffU
24245 #define M_OFDRATE1    0xffU
24249 #define S_OFDRATE0    0
24250 #define M_OFDRATE0    0xffU
24254 #define A_TP_IX_SCHED0 0x7ec0
24255 #define A_TP_IX_SCHED1 0x7ec4
24256 #define A_TP_IX_SCHED2 0x7ec8
24257 #define A_TP_IX_SCHED3 0x7ecc
24258 #define A_TP_TX_TRATE 0x7ed0
24261 #define M_TNLRATE3    0xffU
24266 #define M_TNLRATE2    0xffU
24271 #define M_TNLRATE1    0xffU
24275 #define S_TNLRATE0    0
24276 #define M_TNLRATE0    0xffU
24280 #define A_TP_DBG_LA_CONFIG 0x7ed4
24283 #define M_DBGLAOPCENABLE    0xffU
24292 #define M_DBGLAWPTR    0x7fU
24297 #define M_DBGLAMODE    0x3U
24309 #define S_DBGLARPTR    0
24310 #define M_DBGLARPTR    0x7fU
24314 #define A_TP_DBG_LA_DATAL 0x7ed8
24315 #define A_TP_DBG_LA_DATAH 0x7edc
24316 #define A_TP_PROTOCOL_CNTRL 0x7ee8
24327 #define M_BLOCKSELECT    0x3U
24332 #define M_LINEADDRESS    0x7fU
24336 #define S_REQUESTDONE    0
24340 #define A_TP_PROTOCOL_DATA0 0x7eec
24341 #define A_TP_PROTOCOL_DATA1 0x7ef0
24342 #define A_TP_PROTOCOL_DATA2 0x7ef4
24343 #define A_TP_PROTOCOL_DATA3 0x7ef8
24344 #define A_TP_PROTOCOL_DATA4 0x7efc
24346 #define S_PROTOCOLDATAFIELD    0
24347 #define M_PROTOCOLDATAFIELD    0xfU
24351 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
24354 #define M_TXTIMERSEPQ7    0xffffU
24358 #define S_TXTIMERSEPQ6    0
24359 #define M_TXTIMERSEPQ6    0xffffU
24363 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
24366 #define M_TXTIMERSEPQ5    0xffffU
24370 #define S_TXTIMERSEPQ4    0
24371 #define M_TXTIMERSEPQ4    0xffffU
24375 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
24378 #define M_TXTIMERSEPQ3    0xffffU
24382 #define S_TXTIMERSEPQ2    0
24383 #define M_TXTIMERSEPQ2    0xffffU
24387 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
24390 #define M_TXTIMERSEPQ1    0xffffU
24394 #define S_TXTIMERSEPQ0    0
24395 #define M_TXTIMERSEPQ0    0xffffU
24399 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
24402 #define M_RXTIMERSEPQ1    0xffffU
24406 #define S_RXTIMERSEPQ0    0
24407 #define M_RXTIMERSEPQ0    0xffffU
24411 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
24414 #define M_TXRATEINCQ7    0xffU
24419 #define M_TXRATETCKQ7    0xffU
24424 #define M_TXRATEINCQ6    0xffU
24428 #define S_TXRATETCKQ6    0
24429 #define M_TXRATETCKQ6    0xffU
24433 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
24436 #define M_TXRATEINCQ5    0xffU
24441 #define M_TXRATETCKQ5    0xffU
24446 #define M_TXRATEINCQ4    0xffU
24450 #define S_TXRATETCKQ4    0
24451 #define M_TXRATETCKQ4    0xffU
24455 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
24458 #define M_TXRATEINCQ3    0xffU
24463 #define M_TXRATETCKQ3    0xffU
24468 #define M_TXRATEINCQ2    0xffU
24472 #define S_TXRATETCKQ2    0
24473 #define M_TXRATETCKQ2    0xffU
24477 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
24480 #define M_TXRATEINCQ1    0xffU
24485 #define M_TXRATETCKQ1    0xffU
24490 #define M_TXRATEINCQ0    0xffU
24494 #define S_TXRATETCKQ0    0
24495 #define M_TXRATETCKQ0    0xffU
24499 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
24502 #define M_RXRATEINCQ1    0xffU
24507 #define M_RXRATETCKQ1    0xffU
24512 #define M_RXRATEINCQ0    0xffU
24516 #define S_RXRATETCKQ0    0
24517 #define M_RXRATETCKQ0    0xffU
24521 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
24522 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
24523 #define A_TP_RX_SCHED_MAP 0x20
24526 #define M_RXMAPCHANNEL3    0xffU
24531 #define M_RXMAPCHANNEL2    0xffU
24536 #define M_RXMAPCHANNEL1    0xffU
24540 #define S_RXMAPCHANNEL0    0
24541 #define M_RXMAPCHANNEL0    0xffU
24545 #define A_TP_RX_SCHED_SGE 0x21
24548 #define M_RXSGEMOD1    0xfU
24553 #define M_RXSGEMOD0    0xfU
24569 #define S_RXSGECHANNEL0    0
24573 #define A_TP_TX_SCHED_MAP 0x22
24576 #define M_TXMAPCHANNEL3    0xfU
24581 #define M_TXMAPCHANNEL2    0xfU
24586 #define M_TXMAPCHANNEL1    0xfU
24590 #define S_TXMAPCHANNEL0    0
24591 #define M_TXMAPCHANNEL0    0xfU
24603 #define A_TP_TX_SCHED_HDR 0x23
24606 #define M_TXMAPHDRCHANNEL7    0xfU
24611 #define M_TXMAPHDRCHANNEL6    0xfU
24616 #define M_TXMAPHDRCHANNEL5    0xfU
24621 #define M_TXMAPHDRCHANNEL4    0xfU
24626 #define M_TXMAPHDRCHANNEL3    0xfU
24631 #define M_TXMAPHDRCHANNEL2    0xfU
24636 #define M_TXMAPHDRCHANNEL1    0xfU
24640 #define S_TXMAPHDRCHANNEL0    0
24641 #define M_TXMAPHDRCHANNEL0    0xfU
24645 #define A_TP_TX_SCHED_FIFO 0x24
24648 #define M_TXMAPFIFOCHANNEL7    0xfU
24653 #define M_TXMAPFIFOCHANNEL6    0xfU
24658 #define M_TXMAPFIFOCHANNEL5    0xfU
24663 #define M_TXMAPFIFOCHANNEL4    0xfU
24668 #define M_TXMAPFIFOCHANNEL3    0xfU
24673 #define M_TXMAPFIFOCHANNEL2    0xfU
24678 #define M_TXMAPFIFOCHANNEL1    0xfU
24682 #define S_TXMAPFIFOCHANNEL0    0
24683 #define M_TXMAPFIFOCHANNEL0    0xfU
24687 #define A_TP_TX_SCHED_PCMD 0x25
24690 #define M_TXMAPPCMDCHANNEL7    0xfU
24695 #define M_TXMAPPCMDCHANNEL6    0xfU
24700 #define M_TXMAPPCMDCHANNEL5    0xfU
24705 #define M_TXMAPPCMDCHANNEL4    0xfU
24710 #define M_TXMAPPCMDCHANNEL3    0xfU
24715 #define M_TXMAPPCMDCHANNEL2    0xfU
24720 #define M_TXMAPPCMDCHANNEL1    0xfU
24724 #define S_TXMAPPCMDCHANNEL0    0
24725 #define M_TXMAPPCMDCHANNEL0    0xfU
24729 #define A_TP_TX_SCHED_LPBK 0x26
24732 #define M_TXMAPLPBKCHANNEL7    0xfU
24737 #define M_TXMAPLPBKCHANNEL6    0xfU
24742 #define M_TXMAPLPBKCHANNEL5    0xfU
24747 #define M_TXMAPLPBKCHANNEL4    0xfU
24752 #define M_TXMAPLPBKCHANNEL3    0xfU
24757 #define M_TXMAPLPBKCHANNEL2    0xfU
24762 #define M_TXMAPLPBKCHANNEL1    0xfU
24766 #define S_TXMAPLPBKCHANNEL0    0
24767 #define M_TXMAPLPBKCHANNEL0    0xfU
24771 #define A_TP_CHANNEL_MAP 0x27
24774 #define M_RXMAPCHANNELELN    0xfU
24779 #define M_RXMAPE2LCHANNEL3    0x3U
24784 #define M_RXMAPE2LCHANNEL2    0x3U
24789 #define M_RXMAPE2LCHANNEL1    0x3U
24794 #define M_RXMAPE2LCHANNEL0    0x3U
24826 #define S_RXMAPE2CCHANNEL0    0
24830 #define A_TP_RX_LPBK 0x28
24831 #define A_TP_TX_LPBK 0x29
24832 #define A_TP_TX_SCHED_PPP 0x2a
24835 #define M_TXPPPENPORT3    0xffU
24840 #define M_TXPPPENPORT2    0xffU
24845 #define M_TXPPPENPORT1    0xffU
24849 #define S_TXPPPENPORT0    0
24850 #define M_TXPPPENPORT0    0xffU
24854 #define A_TP_RX_SCHED_FIFO 0x2b
24857 #define M_COMMITLIMIT1H    0xffU
24862 #define M_COMMITLIMIT1L    0xffU
24867 #define M_COMMITLIMIT0H    0xffU
24871 #define S_COMMITLIMIT0L    0
24872 #define M_COMMITLIMIT0L    0xffU
24876 #define A_TP_IPMI_CFG1 0x2e
24894 #define S_IPMI_VLAN    0
24895 #define M_IPMI_VLAN    0xffffU
24899 #define A_TP_IPMI_CFG2 0x2f
24902 #define M_SECUREPORT    0xffffU
24906 #define S_PRIMARYPORT    0
24907 #define M_PRIMARYPORT    0xffffU
24911 #define A_TP_RSS_PF0_CONFIG 0x30
24946 #define M_IVFWIDTH    0xfU
24951 #define M_CH1DEFAULTQUEUE    0x3ffU
24955 #define S_CH0DEFAULTQUEUE    0
24956 #define M_CH0DEFAULTQUEUE    0x3ffU
24968 #define A_TP_RSS_PF1_CONFIG 0x31
24974 #define A_TP_RSS_PF2_CONFIG 0x32
24980 #define A_TP_RSS_PF3_CONFIG 0x33
24986 #define A_TP_RSS_PF4_CONFIG 0x34
24992 #define A_TP_RSS_PF5_CONFIG 0x35
24998 #define A_TP_RSS_PF6_CONFIG 0x36
25004 #define A_TP_RSS_PF7_CONFIG 0x37
25010 #define A_TP_RSS_PF_MAP 0x38
25013 #define M_LKPIDXSIZE    0x3U
25018 #define M_PF7LKPIDX    0x7U
25023 #define M_PF6LKPIDX    0x7U
25028 #define M_PF5LKPIDX    0x7U
25033 #define M_PF4LKPIDX    0x7U
25038 #define M_PF3LKPIDX    0x7U
25043 #define M_PF2LKPIDX    0x7U
25048 #define M_PF1LKPIDX    0x7U
25052 #define S_PF0LKPIDX    0
25053 #define M_PF0LKPIDX    0x7U
25057 #define A_TP_RSS_PF_MSK 0x39
25060 #define M_PF7MSKSIZE    0xfU
25065 #define M_PF6MSKSIZE    0xfU
25070 #define M_PF5MSKSIZE    0xfU
25075 #define M_PF4MSKSIZE    0xfU
25080 #define M_PF3MSKSIZE    0xfU
25085 #define M_PF2MSKSIZE    0xfU
25090 #define M_PF1MSKSIZE    0xfU
25094 #define S_PF0MSKSIZE    0
25095 #define M_PF0MSKSIZE    0xfU
25099 #define A_TP_RSS_VFL_CONFIG 0x3a
25100 #define A_TP_RSS_VFH_CONFIG 0x3b
25123 #define M_DEFAULTQUEUE    0x3ffU
25128 #define M_VFLKPIDX    0xffU
25148 #define S_KEYINDEX    0
25149 #define M_KEYINDEX    0xfU
25153 #define A_TP_RSS_SECRET_KEY0 0x40
25154 #define A_TP_RSS_SECRET_KEY1 0x41
25155 #define A_TP_RSS_SECRET_KEY2 0x42
25156 #define A_TP_RSS_SECRET_KEY3 0x43
25157 #define A_TP_RSS_SECRET_KEY4 0x44
25158 #define A_TP_RSS_SECRET_KEY5 0x45
25159 #define A_TP_RSS_SECRET_KEY6 0x46
25160 #define A_TP_RSS_SECRET_KEY7 0x47
25161 #define A_TP_RSS_SECRET_KEY8 0x48
25162 #define A_TP_RSS_SECRET_KEY9 0x49
25163 #define A_TP_ETHER_TYPE_VL 0x50
25166 #define M_CQFCTYPE    0xffffU
25170 #define S_VLANTYPE    0
25171 #define M_VLANTYPE    0xffffU
25175 #define A_TP_ETHER_TYPE_IP 0x51
25178 #define M_IPV6TYPE    0xffffU
25182 #define S_IPV4TYPE    0
25183 #define M_IPV4TYPE    0xffffU
25187 #define A_TP_ETHER_TYPE_FW 0x52
25190 #define M_ETHTYPE1    0xffffU
25194 #define S_ETHTYPE0    0
25195 #define M_ETHTYPE0    0xffffU
25199 #define A_TP_VXLAN_HEADER 0x53
25201 #define S_VXLANPORT    0
25202 #define M_VXLANPORT    0xffffU
25206 #define A_TP_CORE_POWER 0x54
25244 #define S_SLEEPREQRSS    0
25248 #define A_TP_CORE_RDMA 0x55
25251 #define M_IMMEDIATEOP    0xfU
25256 #define M_IMMEDIATESE    0xfU
25261 #define M_ATOMICREQOP    0xfU
25266 #define M_ATOMICRSPOP    0xfU
25274 #define S_IMMEDIATEEN    0
25286 #define A_TP_FRAG_CONFIG 0x56
25289 #define M_TLSMODE    0x3U
25294 #define M_USERMODE    0x3U
25299 #define M_FCOEMODE    0x3U
25304 #define M_IANDPMODE    0x3U
25309 #define M_RDDPMODE    0x3U
25314 #define M_IWARPMODE    0x3U
25319 #define M_ISCSIMODE    0x3U
25324 #define M_DDPMODE    0x3U
25328 #define S_PASSMODE    0
25329 #define M_PASSMODE    0x3U
25333 #define A_TP_CMM_CONFIG 0x57
25336 #define M_WRCNTIDLE    0xffffU
25341 #define M_RDTHRESHOLD    0x3fU
25357 #define S_WRTHRTHRESH    0
25358 #define M_WRTHRTHRESH    0x1fU
25362 #define A_TP_VXLAN_CONFIG 0x58
25365 #define M_VXLANFLAGS    0xffffU
25369 #define S_VXLANTYPE    0
25370 #define M_VXLANTYPE    0xffffU
25374 #define A_TP_NVGRE_CONFIG 0x59
25377 #define M_GREFLAGS    0xffffU
25381 #define S_GRETYPE    0
25382 #define M_GRETYPE    0xffffU
25386 #define A_TP_DBG_CLEAR 0x60
25387 #define A_TP_DBG_CORE_HDR0 0x61
25453 #define S_E_TCP_OPT_RXVALID    0
25457 #define A_TP_DBG_CORE_HDR1 0x62
25483 #define S_E_TCP_OPT_RXFULL    0
25487 #define A_TP_DBG_CORE_FATAL 0x63
25506 #define M_CPCMDCONG    0xfU
25511 #define M_EPCMDCONG    0x3U
25524 #define M_CPCMDVALID    0xfU
25529 #define M_CPCMDAFULL    0xfU
25534 #define M_EPCMDVALID    0x3U
25539 #define M_EPCMDAFULL    0x3U
25552 #define M_CNONZEROPPOPCNT    0x3U
25556 #define S_CPCMDEOICNT    0
25557 #define M_CPCMDEOICNT    0x3U
25569 #define A_TP_DBG_CORE_OUT 0x64
25655 #define S_EPLDTXZEROPDRDY    0
25699 #define A_TP_DBG_CORE_TID 0x65
25702 #define M_LINENUMBER    0x7fU
25714 #define S_TIDVALUE    0
25715 #define M_TIDVALUE    0xfffffU
25720 #define M_SRC    0x3U
25724 #define A_TP_DBG_ENG_RES0 0x66
25743 #define M_RCFOPSRCOUT    0x3U
25756 #define M_RCFOPCODEOUT    0xfU
25761 #define M_EFFRCFOPCODEOUT    0xfU
25825 #define S_ETXBUSY    0
25830 #define M_EFFOPCODEOUT    0xfU
25842 #define S_T5_EPCMDBUSY    0
25850 #define S_T6_EPCMDBUSY    0
25854 #define A_TP_DBG_ENG_RES1 0x67
25873 #define M_CPLCMDIN    0xffU
25894 #define M_TABLEACCESSLATENCY    0xfU
25915 #define M_ENGINESTATE    0x3U
25939 #define S_RCFDATACMRDY    0
25947 #define A_TP_DBG_ENG_RES2 0x68
25950 #define M_CPLCMDRAW    0xffU
25955 #define M_RXMACPORT    0xfU
25960 #define M_TXECHANNEL    0x3U
25965 #define M_RXECHANNEL    0x3U
26002 #define M_RXPSTRUCTSFULL    0x3U
26007 #define M_RXPAGEPOOLFULL    0x3U
26011 #define S_RCFREASONOUT    0
26012 #define M_RCFREASONOUT    0xfU
26016 #define A_TP_DBG_CORE_PCMD 0x69
26019 #define M_CPCMDEOPCNT    0x3U
26024 #define M_CPCMDLENSAVE    0x3fffU
26029 #define M_EPCMDEOPCNT    0x3U
26033 #define S_EPCMDLENSAVE    0
26034 #define M_EPCMDLENSAVE    0x3fffU
26038 #define A_TP_DBG_SCHED_TX 0x6a
26041 #define M_TXCHNXOFF    0xfU
26046 #define M_TXFIFOCNG    0xfU
26051 #define M_TXPCMDCNG    0xfU
26056 #define M_TXLPBKCNG    0xfU
26061 #define M_TXHDRCNG    0xffU
26065 #define S_TXMODXOFF    0
26066 #define M_TXMODXOFF    0xffU
26070 #define A_TP_DBG_SCHED_RX 0x6b
26073 #define M_RXCHNXOFF    0xfU
26078 #define M_RXSGECNG    0xfU
26083 #define M_RXFIFOCNG    0x3U
26088 #define M_RXPCMDCNG    0x3U
26093 #define M_RXLPBKCNG    0xfU
26098 #define M_RXHDRCNG    0xfU
26102 #define S_RXMODXOFF    0
26103 #define M_RXMODXOFF    0x3U
26108 #define M_T5_RXFIFOCNG    0xfU
26113 #define M_T5_RXPCMDCNG    0x3U
26118 #define M_T6_RXFIFOCNG    0xfU
26123 #define M_T6_RXPCMDCNG    0x3U
26127 #define A_TP_DBG_ERROR_CNT 0x6c
26128 #define A_TP_DBG_CORE_CPL 0x6d
26131 #define M_CPLCMDOUT3    0xffU
26136 #define M_CPLCMDOUT2    0xffU
26141 #define M_CPLCMDOUT1    0xffU
26145 #define S_CPLCMDOUT0    0
26146 #define M_CPLCMDOUT0    0xffU
26150 #define A_TP_MIB_DEBUG 0x6f
26157 #define M_LINENUM3    0x7fU
26166 #define M_LINENUM2    0x7fU
26175 #define M_LINENUM1    0x7fU
26183 #define S_LINENUM0    0
26184 #define M_LINENUM0    0x7fU
26188 #define A_TP_DBG_CACHE_WR_ALL 0x70
26189 #define A_TP_DBG_CACHE_WR_HIT 0x71
26190 #define A_TP_DBG_CACHE_RD_ALL 0x72
26191 #define A_TP_DBG_CACHE_RD_HIT 0x73
26192 #define A_TP_DBG_CACHE_MC_REQ 0x74
26193 #define A_TP_DBG_CACHE_MC_RSP 0x75
26194 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
26195 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
26196 #define A_TP_TX_DROP_CNT_CH2 0x122
26197 #define A_TP_TX_DROP_CNT_CH3 0x123
26198 #define A_TP_TX_DROP_CFG_CH0 0x12b
26209 #define M_TIMERTHRESHOLD    0x3ffffffU
26213 #define S_PACKETDROPS    0
26214 #define M_PACKETDROPS    0xfU
26218 #define A_TP_TX_DROP_CFG_CH1 0x12c
26219 #define A_TP_TX_DROP_CNT_CH0 0x12d
26222 #define M_TXDROPCNTCH0SENT    0xffffU
26226 #define S_TXDROPCNTCH0RCVD    0
26227 #define M_TXDROPCNTCH0RCVD    0xffffU
26231 #define A_TP_TX_DROP_CNT_CH1 0x12e
26234 #define M_TXDROPCNTCH1SENT    0xffffU
26238 #define S_TXDROPCNTCH1RCVD    0
26239 #define M_TXDROPCNTCH1RCVD    0xffffU
26243 #define A_TP_TX_DROP_MODE 0x12f
26257 #define S_TXDROPMODECH0    0
26261 #define A_TP_DBG_ESIDE_PKT0 0x130
26264 #define M_ETXSOPCNT    0xfU
26269 #define M_ETXEOPCNT    0xfU
26274 #define M_ETXPLDSOPCNT    0xfU
26279 #define M_ETXPLDEOPCNT    0xfU
26284 #define M_ERXSOPCNT    0xfU
26289 #define M_ERXEOPCNT    0xfU
26294 #define M_ERXPLDSOPCNT    0xfU
26298 #define S_ERXPLDEOPCNT    0
26299 #define M_ERXPLDEOPCNT    0xfU
26303 #define A_TP_DBG_ESIDE_PKT1 0x131
26304 #define A_TP_DBG_ESIDE_PKT2 0x132
26305 #define A_TP_DBG_ESIDE_PKT3 0x133
26306 #define A_TP_DBG_ESIDE_FIFO0 0x134
26432 #define S_ERXFULL0    0
26436 #define A_TP_DBG_ESIDE_FIFO1 0x135
26562 #define S_ERXFULL2    0
26566 #define A_TP_DBG_ESIDE_DISP0 0x136
26573 #define M_STATE    0x7U
26626 #define M_ESTATIC4    0xfU
26631 #define M_FIFOCPLSOCPCNT    0x3U
26636 #define M_FIFOETHSOCPCNT    0x3U
26641 #define M_FIFOIPSOCPCNT    0x3U
26646 #define M_FIFOTCPSOCPCNT    0x3U
26651 #define M_PLD_RXZEROP_CNT    0x3U
26659 #define S_TXFULL    0
26679 #define S_TXFULL_ESIDE0    0
26683 #define A_TP_DBG_ESIDE_DISP1 0x137
26689 #define S_TXFULL_ESIDE1    0
26693 #define A_TP_MAC_MATCH_MAP0 0x138
26696 #define M_MAPVALUEWR    0xffU
26701 #define M_MAPINDEX    0x1ffU
26709 #define S_MAPWRITE    0
26713 #define A_TP_MAC_MATCH_MAP1 0x139
26715 #define S_MAPVALUERD    0
26716 #define M_MAPVALUERD    0x1ffU
26720 #define A_TP_DBG_ESIDE_DISP2 0x13a
26726 #define S_TXFULL_ESIDE2    0
26730 #define A_TP_DBG_ESIDE_DISP3 0x13b
26736 #define S_TXFULL_ESIDE3    0
26740 #define A_TP_DBG_ESIDE_HDR0 0x13c
26743 #define M_TCPSOPCNT    0xfU
26748 #define M_TCPEOPCNT    0xfU
26753 #define M_IPSOPCNT    0xfU
26758 #define M_IPEOPCNT    0xfU
26763 #define M_ETHSOPCNT    0xfU
26768 #define M_ETHEOPCNT    0xfU
26773 #define M_CPLSOPCNT    0xfU
26777 #define S_CPLEOPCNT    0
26778 #define M_CPLEOPCNT    0xfU
26782 #define A_TP_DBG_ESIDE_HDR1 0x13d
26783 #define A_TP_DBG_ESIDE_HDR2 0x13e
26784 #define A_TP_DBG_ESIDE_HDR3 0x13f
26785 #define A_TP_VLAN_PRI_MAP 0x140
26823 #define S_FCOE    0
26839 #define A_TP_INGRESS_CONFIG 0x141
26842 #define M_OPAQUE_TYPE    0xffffU
26878 #define S_IPV6_EXT_HDR_SKIP    0
26879 #define M_IPV6_EXT_HDR_SKIP    0xffU
26891 #define A_TP_TX_DROP_CFG_CH2 0x142
26892 #define A_TP_TX_DROP_CFG_CH3 0x143
26893 #define A_TP_EGRESS_CONFIG 0x145
26895 #define S_REWRITEFORCETOSIZE    0
26899 #define A_TP_INGRESS_CONFIG2 0x145
26910 #define M_TCP_PLD_FILTER_OFFSET    0x3ffU
26915 #define M_UDP_PLD_FILTER_OFFSET    0x3ffU
26919 #define S_TNL_PLD_FILTER_OFFSET    0
26920 #define M_TNL_PLD_FILTER_OFFSET    0x3ffU
26924 #define A_TP_EHDR_CONFIG_LO 0x146
26927 #define M_CPLLIMIT    0xffU
26932 #define M_ETHLIMIT    0xffU
26937 #define M_IPLIMIT    0xffU
26941 #define S_TCPLIMIT    0
26942 #define M_TCPLIMIT    0xffU
26946 #define A_TP_EHDR_CONFIG_HI 0x147
26947 #define A_TP_DBG_ESIDE_INT 0x148
26950 #define M_ERXSOP2X    0xfU
26955 #define M_ERXEOP2X    0xfU
26960 #define M_ERXVALID2X    0xfU
26965 #define M_ERXAFULL2X    0xfU
26970 #define M_PLD2XTXVALID    0xfU
26975 #define M_PLD2XTXAFULL    0xfU
27007 #define S_TCPOPTTXFULL    0
27019 #define A_TP_DBG_ESIDE_DEMUX 0x149
27022 #define M_EALLDONE    0xfU
27027 #define M_EFIFOPLDDONE    0xfU
27032 #define M_EDBDONE    0xfU
27037 #define M_EISSFIFODONE    0xfU
27042 #define M_EACKERRFIFODONE    0xfU
27047 #define M_EFIFOERRORDONE    0xfU
27052 #define M_ERXPKTATTRFIFOFDONE    0xfU
27056 #define S_ETCPOPDONE    0
27057 #define M_ETCPOPDONE    0xfU
27061 #define A_TP_DBG_ESIDE_IN0 0x14a
27187 #define S_RX_PKT_ATTR_DRDY    0
27207 #define A_TP_DBG_ESIDE_IN1 0x14b
27208 #define A_TP_DBG_ESIDE_IN2 0x14c
27209 #define A_TP_DBG_ESIDE_IN3 0x14d
27210 #define A_TP_DBG_ESIDE_FRM 0x14e
27213 #define M_ERX2XERROR    0xfU
27218 #define M_EPLDTX2XERROR    0xfU
27223 #define M_ETXERROR    0xfU
27228 #define M_EPLDRXERROR    0xfU
27233 #define M_ERXSIZEERROR3    0xfU
27238 #define M_ERXSIZEERROR2    0xfU
27243 #define M_ERXSIZEERROR1    0xfU
27247 #define S_ERXSIZEERROR0    0
27248 #define M_ERXSIZEERROR0    0xfU
27252 #define A_TP_DBG_ESIDE_DRP 0x14f
27255 #define M_RXDROP3    0xffU
27260 #define M_RXDROP2    0xffU
27265 #define M_RXDROP1    0xffU
27269 #define S_RXDROP0    0
27270 #define M_RXDROP0    0xffU
27274 #define A_TP_DBG_ESIDE_TX 0x150
27277 #define M_ETXVALID    0xfU
27281 #define S_ETXFULL    0
27282 #define M_ETXFULL    0xfU
27287 #define M_TXERRORCNT    0xffffffU
27291 #define A_TP_ESIDE_SVID_MASK 0x151
27292 #define A_TP_ESIDE_DVID_MASK 0x152
27293 #define A_TP_ESIDE_ALIGN_MASK 0x153
27300 #define M_LOOP_OFFSET    0xffU
27305 #define M_DVID_ID_OFFSET    0xffU
27309 #define S_SVID_ID_OFFSET    0
27310 #define M_SVID_ID_OFFSET    0xffU
27314 #define A_TP_DBG_ESIDE_OP 0x154
27325 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0    0x3U
27330 #define M_OPT_PARSER_OTK_STATE_CHANNEL0    0x3U
27343 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1    0x3U
27348 #define M_OPT_PARSER_OTK_STATE_CHANNEL1    0x3U
27361 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2    0x3U
27366 #define M_OPT_PARSER_OTK_STATE_CHANNEL2    0x3U
27379 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3    0x3U
27383 #define S_OPT_PARSER_OTK_STATE_CHANNEL3    0
27384 #define M_OPT_PARSER_OTK_STATE_CHANNEL3    0x3U
27388 #define A_TP_DBG_ESIDE_OP_ALT 0x155
27395 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    0x1fU
27404 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    0x1fU
27413 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    0x1fU
27421 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0
27422 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0x1fU
27426 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
27429 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3    0xffU
27434 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2    0xffU
27439 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1    0xffU
27443 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0    0
27444 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0    0xffU
27448 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
27451 #define M_OPT_PARSER_COOKIE_CHANNEL3    0xffU
27456 #define M_OPT_PARSER_COOKIE_CHANNEL2    0xffU
27461 #define M_OPT_PARSER_COOKIE_CHANNEL1    0xffU
27465 #define S_OPT_PARSER_COOKIE_CHANNEL0    0
27466 #define M_OPT_PARSER_COOKIE_CHANNEL0    0xffU
27470 #define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
27471 #define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
27472 #define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
27473 #define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
27474 #define A_TP_ESIDE_CONFIG 0x160
27488 #define S_ROCEV2UDPPORT    0
27489 #define M_ROCEV2UDPPORT    0xffffU
27493 #define A_TP_DBG_CSIDE_RX0 0x230
27496 #define M_CRXSOPCNT    0xfU
27501 #define M_CRXEOPCNT    0xfU
27506 #define M_CRXPLDSOPCNT    0xfU
27511 #define M_CRXPLDEOPCNT    0xfU
27516 #define M_CRXARBSOPCNT    0xfU
27521 #define M_CRXARBEOPCNT    0xfU
27526 #define M_CRXCPLSOPCNT    0xfU
27530 #define S_CRXCPLEOPCNT    0
27531 #define M_CRXCPLEOPCNT    0xfU
27535 #define A_TP_DBG_CSIDE_RX1 0x231
27536 #define A_TP_DBG_CSIDE_RX2 0x232
27537 #define A_TP_DBG_CSIDE_RX3 0x233
27538 #define A_TP_DBG_CSIDE_TX0 0x234
27541 #define M_TXSOPCNT    0xfU
27546 #define M_TXEOPCNT    0xfU
27551 #define M_TXPLDSOPCNT    0xfU
27556 #define M_TXPLDEOPCNT    0xfU
27561 #define M_TXARBSOPCNT    0xfU
27566 #define M_TXARBEOPCNT    0xfU
27571 #define M_TXCPLSOPCNT    0xfU
27575 #define S_TXCPLEOPCNT    0
27576 #define M_TXCPLEOPCNT    0xfU
27580 #define A_TP_DBG_CSIDE_TX1 0x235
27581 #define A_TP_DBG_CSIDE_TX2 0x236
27582 #define A_TP_DBG_CSIDE_TX3 0x237
27583 #define A_TP_DBG_CSIDE_FIFO0 0x238
27709 #define S_CPL5_TXFULL0    0
27713 #define A_TP_DBG_CSIDE_FIFO1 0x239
27839 #define S_CPL5_TXFULL2    0
27843 #define A_TP_DBG_CSIDE_DISP0 0x23a
27878 #define M_DDP_PRE_STATE    0x7U
27887 #define M_DDP_MSG_CODE    0xfU
27892 #define M_CPL5_SOCP_CNT    0x3U
27897 #define M_CSTATIC4    0x3fU
27930 #define M_DDPSTATE    0x1fU
27935 #define M_DDPMSGCODE    0xfU
27940 #define M_CPL5SOCPCNT    0xfU
27945 #define M_PLDRXZEROPCNT    0xfU
27961 #define S_TXFULL2X    0
27981 #define A_TP_DBG_CSIDE_DISP1 0x23b
28015 #define A_TP_DBG_CSIDE_DDP0 0x23c
28018 #define M_DDPMSGLATEST7    0xfU
28023 #define M_DDPMSGLATEST6    0xfU
28028 #define M_DDPMSGLATEST5    0xfU
28033 #define M_DDPMSGLATEST4    0xfU
28038 #define M_DDPMSGLATEST3    0xfU
28043 #define M_DDPMSGLATEST2    0xfU
28048 #define M_DDPMSGLATEST1    0xfU
28052 #define S_DDPMSGLATEST0    0
28053 #define M_DDPMSGLATEST0    0xfU
28057 #define A_TP_DBG_CSIDE_DDP1 0x23d
28058 #define A_TP_DBG_CSIDE_FRM 0x23e
28061 #define M_CRX2XERROR    0xfU
28066 #define M_CPLDTX2XERROR    0xfU
28071 #define M_CTXERROR    0x3U
28076 #define M_CPLDRXERROR    0x3U
28081 #define M_CPLRXERROR    0x3U
28086 #define M_CPLTXERROR    0x3U
28090 #define S_CPRSERROR    0
28091 #define M_CPRSERROR    0xfU
28095 #define A_TP_DBG_CSIDE_INT 0x23f
28098 #define M_CRXVALID2X    0xfU
28103 #define M_CRXAFULL2X    0xfU
28108 #define M_CTXVALID2X    0x3U
28113 #define M_CTXAFULL2X    0x3U
28118 #define M_PLD2X_RXVALID    0x3U
28123 #define M_PLD2X_RXAFULL    0x3U
28128 #define M_CSIDE_DDP_VALID    0x3U
28133 #define M_DDP_AFULL    0x3U
28154 #define M_PLD2X_TXVALID    0xfU
28158 #define S_PLD2X_TXAFULL    0
28159 #define M_PLD2X_TXAFULL    0xfU
28163 #define A_TP_CHDR_CONFIG 0x240
28166 #define M_CH1HIGH    0xffU
28171 #define M_CH1LOW    0xffU
28176 #define M_CH0HIGH    0xffU
28180 #define S_CH0LOW    0
28181 #define M_CH0LOW    0xffU
28185 #define A_TP_UTRN_CONFIG 0x241
28188 #define M_CH2FIFOLIMIT    0xffU
28193 #define M_CH1FIFOLIMIT    0xffU
28197 #define S_CH0FIFOLIMIT    0
28198 #define M_CH0FIFOLIMIT    0xffU
28202 #define A_TP_CDSP_CONFIG 0x242
28208 #define S_WRITEZEROOP    0
28209 #define M_WRITEZEROOP    0xfU
28225 #define A_TP_CSPI_POWER 0x243
28255 #define S_SLEEPREQUTRN    0
28259 #define A_TP_TRC_CONFIG 0x244
28265 #define S_TRCCH    0
28269 #define A_TP_TAG_CONFIG 0x245
28272 #define M_ETAGTYPE    0xffffU
28276 #define A_TP_DBG_CSIDE_PRS 0x246
28279 #define M_CPRSSTATE3    0x7U
28284 #define M_CPRSSTATE2    0x7U
28289 #define M_CPRSSTATE1    0x7U
28293 #define S_CPRSSTATE0    0
28294 #define M_CPRSSTATE0    0x7U
28315 #define M_T5_CPRSSTATE3    0xfU
28336 #define M_T5_CPRSSTATE2    0xfU
28357 #define M_T5_CPRSSTATE1    0xfU
28377 #define S_T5_CPRSSTATE0    0
28378 #define M_T5_CPRSSTATE0    0xfU
28383 #define M_T6_CPRSSTATE3    0xfU
28388 #define M_T6_CPRSSTATE2    0xfU
28393 #define M_T6_CPRSSTATE1    0xfU
28397 #define S_T6_CPRSSTATE0    0
28398 #define M_T6_CPRSSTATE0    0xfU
28402 #define A_TP_DBG_CSIDE_DEMUX 0x247
28405 #define M_CALLDONE    0xfU
28410 #define M_CTCPL5DONE    0xfU
28415 #define M_CTXZEROPDONE    0xfU
28420 #define M_CPLDDONE    0xfU
28425 #define M_CTTCPOPDONE    0xfU
28430 #define M_CDBDONE    0xfU
28435 #define M_CISSFIFODONE    0xfU
28439 #define S_CTXPKTCSUMDONE    0
28440 #define M_CTXPKTCSUMDONE    0xfU
28445 #define M_CARBVALID    0xfU
28450 #define M_CCPL5DONE    0xfU
28455 #define M_CTCPOPDONE    0xfU
28459 #define A_TP_DBG_CSIDE_ARBIT 0x248
28585 #define S_ERRVALID0    0
28589 #define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
28592 #define M_TRCSOPCNT    0xffU
28597 #define M_TRCEOPCNT    0xffU
28602 #define M_TRCFLTHIT    0xfU
28607 #define M_TRCRNTPKT    0xfU
28611 #define S_TRCPKTLEN    0
28612 #define M_TRCPKTLEN    0xffU
28616 #define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
28617 #define A_TP_VLN_CONFIG 0x24c
28620 #define M_ETHTYPEQINQ    0xffffU
28624 #define S_ETHTYPEVLAN    0
28625 #define M_ETHTYPEVLAN    0xffffU
28629 #define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
28630 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
28631 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
28632 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
28633 #define A_TP_FIFO_CONFIG 0x8c0
28636 #define M_CH1_OUTPUT    0x1fU
28641 #define M_CH2_OUTPUT    0x1fU
28650 #define M_CH1_INPUT    0x1fU
28655 #define M_CH2_INPUT    0x1fU
28660 #define M_CH3_INPUT    0x1fU
28664 #define S_STROBE0    0
28668 #define A_TP_MIB_MAC_IN_ERR_0 0x0
28669 #define A_TP_MIB_MAC_IN_ERR_1 0x1
28670 #define A_TP_MIB_MAC_IN_ERR_2 0x2
28671 #define A_TP_MIB_MAC_IN_ERR_3 0x3
28672 #define A_TP_MIB_HDR_IN_ERR_0 0x4
28673 #define A_TP_MIB_HDR_IN_ERR_1 0x5
28674 #define A_TP_MIB_HDR_IN_ERR_2 0x6
28675 #define A_TP_MIB_HDR_IN_ERR_3 0x7
28676 #define A_TP_MIB_TCP_IN_ERR_0 0x8
28677 #define A_TP_MIB_TCP_IN_ERR_1 0x9
28678 #define A_TP_MIB_TCP_IN_ERR_2 0xa
28679 #define A_TP_MIB_TCP_IN_ERR_3 0xb
28680 #define A_TP_MIB_TCP_OUT_RST 0xc
28681 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
28682 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
28683 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
28684 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
28685 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
28686 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
28687 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
28688 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
28689 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
28690 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
28691 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
28692 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
28693 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
28694 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
28695 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
28696 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
28697 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
28698 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
28699 #define A_TP_MIB_TNL_IN_PKT_0 0x24
28700 #define A_TP_MIB_TNL_IN_PKT_1 0x25
28701 #define A_TP_MIB_TNL_IN_PKT_2 0x26
28702 #define A_TP_MIB_TNL_IN_PKT_3 0x27
28703 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
28704 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
28705 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
28706 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
28707 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
28708 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
28709 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
28710 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
28711 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
28712 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
28713 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
28714 #define A_TP_MIB_OFD_ARP_DROP 0x36
28715 #define A_TP_MIB_OFD_DFR_DROP 0x37
28716 #define A_TP_MIB_CPL_IN_REQ_0 0x38
28717 #define A_TP_MIB_CPL_IN_REQ_1 0x39
28718 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
28719 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
28720 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
28721 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
28722 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
28723 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
28724 #define A_TP_MIB_TNL_LPBK_0 0x40
28725 #define A_TP_MIB_TNL_LPBK_1 0x41
28726 #define A_TP_MIB_TNL_LPBK_2 0x42
28727 #define A_TP_MIB_TNL_LPBK_3 0x43
28728 #define A_TP_MIB_TNL_DROP_0 0x44
28729 #define A_TP_MIB_TNL_DROP_1 0x45
28730 #define A_TP_MIB_TNL_DROP_2 0x46
28731 #define A_TP_MIB_TNL_DROP_3 0x47
28732 #define A_TP_MIB_FCOE_DDP_0 0x48
28733 #define A_TP_MIB_FCOE_DDP_1 0x49
28734 #define A_TP_MIB_FCOE_DDP_2 0x4a
28735 #define A_TP_MIB_FCOE_DDP_3 0x4b
28736 #define A_TP_MIB_FCOE_DROP_0 0x4c
28737 #define A_TP_MIB_FCOE_DROP_1 0x4d
28738 #define A_TP_MIB_FCOE_DROP_2 0x4e
28739 #define A_TP_MIB_FCOE_DROP_3 0x4f
28740 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
28741 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
28742 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
28743 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
28744 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
28745 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
28746 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
28747 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
28748 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
28749 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
28750 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
28751 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
28752 #define A_TP_MIB_USM_PKTS 0x5c
28753 #define A_TP_MIB_USM_DROP 0x5d
28754 #define A_TP_MIB_USM_BYTES_HI 0x5e
28755 #define A_TP_MIB_USM_BYTES_LO 0x5f
28756 #define A_TP_MIB_TID_DEL 0x60
28757 #define A_TP_MIB_TID_INV 0x61
28758 #define A_TP_MIB_TID_ACT 0x62
28759 #define A_TP_MIB_TID_PAS 0x63
28760 #define A_TP_MIB_RQE_DFR_PKT 0x64
28761 #define A_TP_MIB_RQE_DFR_MOD 0x65
28762 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
28763 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
28764 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
28765 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
28766 #define A_TP_MIB_ENG_LINE_0 0x6c
28767 #define A_TP_MIB_ENG_LINE_1 0x6d
28768 #define A_TP_MIB_ENG_LINE_2 0x6e
28769 #define A_TP_MIB_ENG_LINE_3 0x6f
28770 #define A_TP_MIB_TNL_ERR_0 0x70
28771 #define A_TP_MIB_TNL_ERR_1 0x71
28772 #define A_TP_MIB_TNL_ERR_2 0x72
28773 #define A_TP_MIB_TNL_ERR_3 0x73
28776 #define ULP_TX_BASE_ADDR 0x8dc0
28778 #define A_ULP_TX_CONFIG 0x8dc0
28788 #define S_EXTRA_TAG_INSERTION_ENABLE    0
28856 #define A_ULP_TX_PERR_INJECT 0x8dc4
28857 #define A_ULP_TX_INT_ENABLE 0x8dc8
28983 #define S_IMM_DATA_PERR_SET_CH0    0
28987 #define A_ULP_TX_INT_CAUSE 0x8dcc
28988 #define A_ULP_TX_PERR_ENABLE 0x8dd0
28989 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
28990 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
28991 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
28992 #define A_ULP_TX_PBL_ULIMIT 0x8de0
28993 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
28994 #define A_ULP_TX_TLS_CTL 0x8de4
29012 #define S_TLSDISABLE    0
29016 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
29017 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
29018 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
29019 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
29020 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
29023 #define M_CH3SIZE1    0xffU
29028 #define M_CH2SIZE1    0xffU
29033 #define M_CH1SIZE1    0xffU
29037 #define S_CH0SIZE1    0
29038 #define M_CH0SIZE1    0xffU
29042 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
29045 #define M_CH3SIZE2    0xffU
29050 #define M_CH2SIZE2    0xffU
29055 #define M_CH1SIZE2    0xffU
29059 #define S_CH0SIZE2    0
29060 #define M_CH0SIZE2    0xffU
29064 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
29065 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
29066 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
29068 #define S_ERR_CNT0    0
29069 #define M_ERR_CNT0    0xfffffU
29073 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
29075 #define S_ERR_CNT1    0
29076 #define M_ERR_CNT1    0xfffffU
29080 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
29082 #define S_ERR_CNT2    0
29083 #define M_ERR_CNT2    0xfffffU
29087 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
29089 #define S_ERR_CNT3    0
29090 #define M_ERR_CNT3    0xfffffU
29094 #define A_ULP_TX_FC_SOF 0x8e20
29097 #define M_SOF_FS3    0xffU
29102 #define M_SOF_FS2    0xffU
29107 #define M_SOF_3    0xffU
29111 #define S_SOF_2    0
29112 #define M_SOF_2    0xffU
29116 #define A_ULP_TX_FC_EOF 0x8e24
29119 #define M_EOF_LS3    0xffU
29124 #define M_EOF_LS2    0xffU
29129 #define M_EOF_3    0xffU
29133 #define S_EOF_2    0
29134 #define M_EOF_2    0xffU
29138 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
29140 #define S_ULP_TX_GLOBAL_CGEN    0
29144 #define A_ULP_TX_CGEN 0x8e2c
29147 #define M_ULP_TX_CGEN_STORAGE    0xfU
29152 #define M_ULP_TX_CGEN_RDMA    0xfU
29156 #define S_ULP_TX_CGEN_CHANNEL    0
29157 #define M_ULP_TX_CGEN_CHANNEL    0xfU
29161 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
29162 #define A_ULP_TX_MEM_CFG 0x8e30
29164 #define S_WRREQ_SZ    0
29165 #define M_WRREQ_SZ    0x7U
29169 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
29170 #define A_ULP_TX_PERR_INJECT_2 0x8e34
29173 #define M_T5_MEMSEL    0x7U
29178 #define M_MEMSEL_ULPTX    0x1fU
29182 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
29183 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
29186 #define M_CHANNEL_SEL    0x3U
29191 #define M_INTF_SEL    0xfU
29196 #define M_NUM_FLITS    0x7U
29200 #define S_CMD_GEN_EN    0
29204 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
29205 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
29206 #define A_ULP_TX_FPGA_CMD_1 0x8e40
29207 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
29208 #define A_ULP_TX_FPGA_CMD_2 0x8e44
29209 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
29210 #define A_ULP_TX_FPGA_CMD_3 0x8e48
29211 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
29212 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
29213 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
29214 #define A_ULP_TX_FPGA_CMD_5 0x8e50
29215 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
29216 #define A_ULP_TX_FPGA_CMD_6 0x8e54
29217 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
29218 #define A_ULP_TX_FPGA_CMD_7 0x8e58
29219 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
29220 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
29221 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
29222 #define A_ULP_TX_FPGA_CMD_9 0x8e60
29223 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
29224 #define A_ULP_TX_FPGA_CMD_10 0x8e64
29225 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
29226 #define A_ULP_TX_FPGA_CMD_11 0x8e68
29227 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
29228 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
29229 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
29230 #define A_ULP_TX_FPGA_CMD_13 0x8e70
29231 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
29232 #define A_ULP_TX_FPGA_CMD_14 0x8e74
29233 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
29234 #define A_ULP_TX_FPGA_CMD_15 0x8e78
29235 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
29236 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
29286 #define S_T10_PI_SRAM_PERR_SET0    0
29386 #define A_ULP_TX_INT_CAUSE_2 0x8e80
29387 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
29388 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
29391 #define M_ERR_CH3    0xfU
29396 #define M_ERR_CH2    0xfU
29401 #define M_ERR_CH1    0xfU
29405 #define S_ERR_CH0    0
29406 #define M_ERR_CH0    0xfU
29410 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
29411 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
29414 #define M_CLR_DROP    0xfU
29419 #define M_CLR_CH3    0xfU
29424 #define M_CLR_CH2    0xfU
29429 #define M_CLR_CH1    0xfU
29433 #define S_CLR_CH0    0
29434 #define M_CLR_CH0    0xfU
29438 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
29439 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
29442 #define M_SOP_CNT_ULP2TP    0xfU
29447 #define M_EOP_CNT_ULP2TP    0xfU
29452 #define M_SOP_CNT_LSO_IN    0xfU
29457 #define M_EOP_CNT_LSO_IN    0xfU
29462 #define M_SOP_CNT_ALG_IN    0xfU
29467 #define M_EOP_CNT_ALG_IN    0xfU
29472 #define M_SOP_CNT_CIM2ULP    0xfU
29476 #define S_EOP_CNT_CIM2ULP    0
29477 #define M_EOP_CNT_CIM2ULP    0xfU
29481 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
29482 #define A_ULP_TX_SE_CNT_CH1 0x8eac
29483 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
29484 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
29485 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
29486 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
29487 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
29488 #define A_ULP_TX_DROP_CNT 0x8eb8
29491 #define M_DROP_CH3    0xfU
29496 #define M_DROP_CH2    0xfU
29501 #define M_DROP_CH1    0xfU
29505 #define S_DROP_CH0    0
29506 #define M_DROP_CH0    0xfU
29510 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
29513 #define M_DROP_INVLD_MC_CH3    0xfU
29518 #define M_DROP_INVLD_MC_CH2    0xfU
29523 #define M_DROP_INVLD_MC_CH1    0xfU
29528 #define M_DROP_INVLD_MC_CH0    0xfU
29532 #define A_ULP_TX_CSU_REVISION 0x8ebc
29533 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
29534 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
29535 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
29536 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
29537 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
29538 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
29539 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
29540 #define A_ULP_TX_LA_RESERVED_1 0x8edc
29541 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
29542 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
29543 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
29544 #define A_ULP_TX_LA_RESERVED_2 0x8eec
29545 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
29546 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
29547 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
29548 #define A_ULP_TX_LA_RESERVED_3 0x8efc
29549 #define A_ULP_TX_LA_RDPTR_4 0x8f00
29550 #define A_ULP_TX_LA_RDDATA_4 0x8f04
29551 #define A_ULP_TX_LA_WRPTR_4 0x8f08
29552 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
29553 #define A_ULP_TX_LA_RDPTR_5 0x8f10
29554 #define A_ULP_TX_LA_RDDATA_5 0x8f14
29555 #define A_ULP_TX_LA_WRPTR_5 0x8f18
29556 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
29557 #define A_ULP_TX_LA_RDPTR_6 0x8f20
29558 #define A_ULP_TX_LA_RDDATA_6 0x8f24
29559 #define A_ULP_TX_LA_WRPTR_6 0x8f28
29560 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
29561 #define A_ULP_TX_LA_RDPTR_7 0x8f30
29562 #define A_ULP_TX_LA_RDDATA_7 0x8f34
29563 #define A_ULP_TX_LA_WRPTR_7 0x8f38
29564 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
29565 #define A_ULP_TX_LA_RDPTR_8 0x8f40
29566 #define A_ULP_TX_LA_RDDATA_8 0x8f44
29567 #define A_ULP_TX_LA_WRPTR_8 0x8f48
29568 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
29569 #define A_ULP_TX_LA_RDPTR_9 0x8f50
29570 #define A_ULP_TX_LA_RDDATA_9 0x8f54
29571 #define A_ULP_TX_LA_WRPTR_9 0x8f58
29572 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
29573 #define A_ULP_TX_LA_RDPTR_10 0x8f60
29574 #define A_ULP_TX_LA_RDDATA_10 0x8f64
29575 #define A_ULP_TX_LA_WRPTR_10 0x8f68
29576 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
29577 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
29579 #define S_LA_WR0    0
29583 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
29584 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
29585 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
29586 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
29587 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
29588 #define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
29670 #define S_SHOVE_LAST    0
29674 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
29676 #define S_TLS_TX_REG_OFF_ADDR    0
29677 #define M_TLS_TX_REG_OFF_ADDR    0x3ffU
29681 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
29684 #define PM_RX_BASE_ADDR 0x8fc0
29686 #define A_PM_RX_CFG 0x8fc0
29687 #define A_PM_RX_MODE 0x8fc4
29698 #define M_STAT_FROM_CH    0x3U
29702 #define S_PREFETCH_ENABLE    0
29706 #define A_PM_RX_STAT_CONFIG 0x8fc8
29707 #define A_PM_RX_STAT_COUNT 0x8fcc
29708 #define A_PM_RX_STAT_LSB 0x8fd0
29709 #define A_PM_RX_DBG_CTRL 0x8fd0
29712 #define M_OSPIWRBUSY_T5    0x3U
29717 #define M_ISPIWRBUSY    0xfU
29721 #define S_PMDBGADDR    0
29722 #define M_PMDBGADDR    0x1ffffU
29726 #define A_PM_RX_STAT_MSB 0x8fd4
29727 #define A_PM_RX_DBG_DATA 0x8fd4
29728 #define A_PM_RX_INT_ENABLE 0x8fd8
29818 #define S_E_PCMD_PAR_ERROR    0
29846 #define A_PM_RX_INT_CAUSE 0x8fdc
29847 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
29848 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
29849 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
29850 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
29851 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
29852 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
29853 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
29854 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
29855 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
29856 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
29857 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
29858 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
29859 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
29860 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
29861 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
29862 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
29863 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
29864 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
29865 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
29866 #define A_PM_RX_DBG_STAT_MSB 0x10013
29867 #define A_PM_RX_DBG_STAT_LSB 0x10014
29868 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
29871 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP    0xfU
29876 #define M_I_TO_O_PATH_RSVD_FLIT    0xfU
29881 #define M_PRFCH_RSVD_FLIT    0xfU
29885 #define S_OSPI_RSVD_FLIT    0
29886 #define M_OSPI_RSVD_FLIT    0xfU
29890 #define A_PM_RX_SDC_EN 0x10016
29892 #define S_SDC_EN    0
29896 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
29910 #define S_CHNL_0_SEL    0
29914 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
29928 #define S_I_FIFO_READ    0
29932 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
29934 #define S_ISPI_STR_FWD_EN    0
29938 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
29940 #define S_PRFTCH_ACROSS_BNDLE_EN    0
29944 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
29946 #define S_PRFTCH_WRR_ENABLE    0
29950 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
29953 #define M_CHNL1_MAX_DEFICIT_CNT    0xffffU
29957 #define S_CHNL0_MAX_DEFICIT_CNT    0
29958 #define M_CHNL0_MAX_DEFICIT_CNT    0xffffU
29962 #define A_PM_RX_FEATURE_EN 0x1001d
29964 #define S_PIO_CH_DEFICIT_CTL_EN_RX    0
29968 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
29970 #define S_CH0_OSPI_DEFICIT_THRSHLD    0
29971 #define M_CH0_OSPI_DEFICIT_THRSHLD    0xfffU
29975 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
29977 #define S_CH1_OSPI_DEFICIT_THRSHLD    0
29978 #define M_CH1_OSPI_DEFICIT_THRSHLD    0xfffU
29982 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
29983 #define A_PM_RX_DBG_STAT0 0x10021
30026 #define M_RX_PCMD_FB    0xfU
30030 #define S_RX_PCMD_LEN    0
30031 #define M_RX_PCMD_LEN    0xffffU
30035 #define A_PM_RX_DBG_STAT1 0x10022
30042 #define M_RX_FREE_OSPI_CNT0    0xfffU
30047 #define M_RX_PCMD0_FLIT_LEN    0xfffU
30052 #define M_RX_PCMD0_CMD    0xfU
30060 #define S_RX_PCMD0_BYPASS    0
30064 #define A_PM_RX_DBG_STAT2 0x10023
30071 #define M_RX_FREE_OSPI_CNT1    0xfffU
30076 #define M_RX_PCMD1_FLIT_LEN    0xfffU
30081 #define M_RX_PCMD1_CMD    0xfU
30089 #define S_RX_PCMD1_BYPASS    0
30093 #define A_PM_RX_DBG_STAT3 0x10024
30096 #define M_RX_SET_PCMD_RES_RDY_RD    0x3U
30101 #define M_RX_ISSUED_PREFETCH_RD_E_CLR    0x3U
30106 #define M_RX_ISSUED_PREFETCH_RD    0x3U
30111 #define M_RX_PCMD_RES_RDY    0x3U
30120 #define M_RX_FIRST_BUNDLE    0x3U
30124 #define S_RX_SDC_DRDY    0
30128 #define A_PM_RX_DBG_STAT4 0x10025
30139 #define M_RX_PCMD_FROM_CH    0x3U
30144 #define M_RX_LINE    0x1fU
30149 #define M_RX_IESPI_TXVALID    0xfU
30154 #define M_RX_IESPI_TXFULL    0xfU
30159 #define M_RX_PCMD_SRDY    0x3U
30164 #define M_RX_PCMD_DRDY    0x3U
30169 #define M_RX_PCMD_CMD    0xfU
30173 #define S_DUPLICATE    0
30174 #define M_DUPLICATE    0x3U
30179 #define M_RX_PCMD_SRDY_STAT4    0x3U
30184 #define M_RX_PCMD_DRDY_STAT4    0x3U
30188 #define A_PM_RX_DBG_STAT5 0x10026
30199 #define M_T5_RX_PCMD_DRDY    0x3U
30204 #define M_T5_RX_PCMD_SRDY    0x3U
30209 #define M_RX_ISPI_TXVALID    0xfU
30214 #define M_RX_ISPI_FULL    0xfU
30219 #define M_RX_OSPI_TXVALID    0x3U
30224 #define M_RX_OSPI_FULL    0x3U
30229 #define M_RX_E_RXVALID    0xfU
30234 #define M_RX_E_RXAFULL    0xfU
30239 #define M_RX_C_TXVALID    0x3U
30243 #define S_RX_C_TXAFULL    0
30244 #define M_RX_C_TXAFULL    0x3U
30249 #define M_T6_RX_PCMD_DRDY    0x3U
30254 #define M_T6_RX_PCMD_SRDY    0x3U
30258 #define A_PM_RX_DBG_STAT6 0x10027
30261 #define M_RX_M_INTRNL_FIFO_CNT    0x3U
30277 #define S_RX_M_REQDATARDY    0
30282 #define M_T6_RX_M_INTRNL_FIFO_CNT    0x3U
30298 #define A_PM_RX_DBG_STAT7 0x10028
30301 #define M_RX_PCMD1_FREE_CNT    0x7fU
30305 #define S_RX_PCMD0_FREE_CNT    0
30306 #define M_RX_PCMD0_FREE_CNT    0x7fU
30310 #define A_PM_RX_DBG_STAT8 0x10029
30313 #define M_RX_IN_EOP_CNT3    0xfU
30318 #define M_RX_IN_EOP_CNT2    0xfU
30323 #define M_RX_IN_EOP_CNT1    0xfU
30328 #define M_RX_IN_EOP_CNT0    0xfU
30333 #define M_RX_IN_SOP_CNT3    0xfU
30338 #define M_RX_IN_SOP_CNT2    0xfU
30343 #define M_RX_IN_SOP_CNT1    0xfU
30347 #define S_RX_IN_SOP_CNT0    0
30348 #define M_RX_IN_SOP_CNT0    0xfU
30352 #define A_PM_RX_DBG_STAT9 0x1002a
30355 #define M_RX_RSVD0    0xfU
30360 #define M_RX_RSVD1    0xfU
30365 #define M_RX_OUT_EOP_CNT1    0xfU
30370 #define M_RX_OUT_EOP_CNT0    0xfU
30375 #define M_RX_RSVD2    0xfU
30380 #define M_RX_RSVD3    0xfU
30385 #define M_RX_OUT_SOP_CNT1    0xfU
30389 #define S_RX_OUT_SOP_CNT0    0
30390 #define M_RX_OUT_SOP_CNT0    0xfU
30394 #define A_PM_RX_DBG_STAT10 0x1002b
30401 #define M_RX_CH1_DEFICIT    0xfffU
30405 #define S_RX_CH0_DEFICIT    0
30406 #define M_RX_CH0_DEFICIT    0xfffU
30410 #define A_PM_RX_DBG_STAT11 0x1002c
30413 #define M_RX_BUNDLE_LEN_SRDY    0x3U
30418 #define M_RX_RSVD11_1    0x3U
30423 #define M_RX_BUNDLE_LEN1    0xfffU
30428 #define M_RX_RSVD11    0xfU
30432 #define S_RX_BUNDLE_LEN0    0
30433 #define M_RX_BUNDLE_LEN0    0xfffU
30438 #define PM_TX_BASE_ADDR 0x8fe0
30440 #define A_PM_TX_CFG 0x8fe0
30443 #define M_CH3_OUTPUT    0x1fU
30447 #define A_PM_TX_MODE 0x8fe4
30450 #define M_CONG_THRESH3    0x7fU
30455 #define M_CONG_THRESH2    0x7fU
30460 #define M_CONG_THRESH1    0x7fU
30465 #define M_CONG_THRESH0    0x7fU
30474 #define M_STAT_CHANNEL    0x3U
30478 #define A_PM_TX_STAT_CONFIG 0x8fe8
30479 #define A_PM_TX_STAT_COUNT 0x8fec
30480 #define A_PM_TX_STAT_LSB 0x8ff0
30481 #define A_PM_TX_DBG_CTRL 0x8ff0
30484 #define M_OSPIWRBUSY    0xfU
30488 #define A_PM_TX_STAT_MSB 0x8ff4
30489 #define A_PM_TX_DBG_DATA 0x8ff4
30490 #define A_PM_TX_INT_ENABLE 0x8ff8
30612 #define S_C_PCMD_PAR_ERROR    0
30616 #define A_PM_TX_INT_CAUSE 0x8ffc
30626 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
30627 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
30628 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
30629 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
30630 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
30631 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
30632 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
30633 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
30634 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
30635 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
30636 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
30637 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
30638 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
30639 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
30640 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
30641 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
30642 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
30643 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
30644 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
30645 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
30646 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
30647 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
30648 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
30649 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
30650 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
30651 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
30652 #define A_PM_TX_DBG_STAT_MSB 0x1001a
30653 #define A_PM_TX_DBG_STAT_LSB 0x1001b
30654 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
30655 #define A_PM_TX_SDC_EN 0x1001d
30656 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
30657 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
30658 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
30659 #define A_PM_TX_FEATURE_EN 0x10021
30669 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
30699 #define S_SDC_ERR_EN    0
30719 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
30720 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
30721 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
30722 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
30723 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
30724 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
30725 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
30727 #define S_CH2_OSPI_DEFICIT_THRSHLD    0
30728 #define M_CH2_OSPI_DEFICIT_THRSHLD    0xfffU
30732 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
30734 #define S_CH3_OSPI_DEFICIT_THRSHLD    0
30735 #define M_CH3_OSPI_DEFICIT_THRSHLD    0xfffU
30739 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
30740 #define A_PM_TX_DBG_STAT0 0x1002c
30783 #define M_PCMD_FB_CMD    0xfU
30787 #define S_CUR_PCMD_LEN    0
30788 #define M_CUR_PCMD_LEN    0xffffU
30820 #define A_PM_TX_DBG_STAT1 0x1002d
30827 #define M_FREE_OESPI_CNT0    0xfffU
30832 #define M_PCMD_FLIT_LEN0    0xfffU
30837 #define M_PCMD_CMD0    0xfU
30849 #define S_BYPASS0    0
30853 #define A_PM_TX_DBG_STAT2 0x1002e
30860 #define M_FREE_OESPI_CNT1    0xfffU
30865 #define M_PCMD_FLIT_LEN1    0xfffU
30870 #define M_PCMD_CMD1    0xfU
30882 #define S_BYPASS1    0
30886 #define A_PM_TX_DBG_STAT3 0x1002f
30893 #define M_FREE_OESPI_CNT2    0xfffU
30898 #define M_PCMD_FLIT_LEN2    0xfffU
30903 #define M_PCMD_CMD2    0xfU
30915 #define S_BYPASS2    0
30919 #define A_PM_TX_DBG_STAT4 0x10030
30926 #define M_FREE_OESPI_CNT3    0xfffU
30931 #define M_PCMD_FLIT_LEN3    0xfffU
30936 #define M_PCMD_CMD3    0xfU
30948 #define S_BYPASS3    0
30952 #define A_PM_TX_DBG_STAT5 0x10031
30955 #define M_SET_PCMD_RES_RDY_RD    0xfU
30960 #define M_ISSUED_PREF_RD_ER_CLR    0xfU
30965 #define M_ISSUED_PREF_RD    0xfU
30970 #define M_PCMD_RES_RDY    0xfU
30987 #define M_FIRST_BUNDLE    0xfU
30992 #define M_GCSUM_MORE_THAN_2_LEFT    0xfU
30996 #define S_SDC_DRDY    0
31000 #define A_PM_TX_DBG_STAT6 0x10032
31007 #define M_PCMD_CH    0x3U
31012 #define M_STATE_MACHINE_LOC    0x1fU
31017 #define M_ICSPI_TXVALID    0xfU
31022 #define M_ICSPI_TXFULL    0xfU
31027 #define M_PCMD_SRDY    0xfU
31032 #define M_PCMD_DRDY    0xfU
31037 #define M_PCMD_CMD    0xfU
31053 #define S_OEFIFO_FULL0    0
31057 #define A_PM_TX_DBG_STAT7 0x10033
31060 #define M_ICSPI_RXVALID    0xfU
31065 #define M_ICSPI_RXFULL    0xfU
31070 #define M_OESPI_VALID    0xfU
31075 #define M_OESPI_FULL    0xfU
31080 #define M_C_RXVALID    0xfU
31085 #define M_C_RXAFULL    0xfU
31117 #define S_E_TXFULL0    0
31121 #define A_PM_TX_DBG_STAT8 0x10034
31124 #define M_MC_RSP_FIFO_CNT    0x3U
31129 #define M_PCMD_FREE_CNT0    0x3ffU
31134 #define M_PCMD_FREE_CNT1    0x3ffU
31150 #define S_M_REQDATARDY    0
31155 #define M_T6_MC_RSP_FIFO_CNT    0x3U
31160 #define M_T6_PCMD_FREE_CNT0    0x3ffU
31165 #define M_T6_PCMD_FREE_CNT1    0x3ffU
31181 #define A_PM_TX_DBG_STAT9 0x10035
31184 #define M_PCMD_FREE_CNT2    0x3ffU
31188 #define S_PCMD_FREE_CNT3    0
31189 #define M_PCMD_FREE_CNT3    0x3ffU
31193 #define A_PM_TX_DBG_STAT10 0x10036
31196 #define M_IN_EOP_CNT3    0xfU
31201 #define M_IN_EOP_CNT2    0xfU
31206 #define M_IN_EOP_CNT1    0xfU
31211 #define M_IN_EOP_CNT0    0xfU
31216 #define M_IN_SOP_CNT3    0xfU
31221 #define M_IN_SOP_CNT2    0xfU
31226 #define M_IN_SOP_CNT1    0xfU
31230 #define S_IN_SOP_CNT0    0
31231 #define M_IN_SOP_CNT0    0xfU
31235 #define A_PM_TX_DBG_STAT11 0x10037
31238 #define M_OUT_EOP_CNT3    0xfU
31243 #define M_OUT_EOP_CNT2    0xfU
31248 #define M_OUT_EOP_CNT1    0xfU
31253 #define M_OUT_EOP_CNT0    0xfU
31258 #define M_OUT_SOP_CNT3    0xfU
31263 #define M_OUT_SOP_CNT2    0xfU
31268 #define M_OUT_SOP_CNT1    0xfU
31272 #define S_OUT_SOP_CNT0    0
31273 #define M_OUT_SOP_CNT0    0xfU
31277 #define A_PM_TX_DBG_STAT12 0x10038
31278 #define A_PM_TX_DBG_STAT13 0x10039
31285 #define M_CH1_DEFICIT    0xfffU
31289 #define S_CH0_DEFICIT    0
31290 #define M_CH0_DEFICIT    0xfffU
31294 #define A_PM_TX_DBG_STAT14 0x1003a
31297 #define M_CH3_DEFICIT    0xfffU
31301 #define S_CH2_DEFICIT    0
31302 #define M_CH2_DEFICIT    0xfffU
31306 #define A_PM_TX_DBG_STAT15 0x1003b
31309 #define M_BUNDLE_LEN_SRDY    0xfU
31314 #define M_BUNDLE_LEN1    0xfffU
31318 #define S_BUNDLE_LEN0    0
31319 #define M_BUNDLE_LEN0    0xfffU
31324 #define M_T6_BUNDLE_LEN_SRDY    0x3U
31329 #define M_T6_BUNDLE_LEN1    0xfffU
31333 #define A_PM_TX_DBG_STAT16 0x1003c
31336 #define M_BUNDLE_LEN3    0xfffU
31340 #define S_BUNDLE_LEN2    0
31341 #define M_BUNDLE_LEN2    0xfffU
31346 #define MPS_BASE_ADDR 0x9000
31348 #define A_MPS_PORT_CTL 0x0
31375 #define M_PRIOPPPENMAP    0xffU
31379 #define A_MPS_VF_CTL 0x0
31380 #define A_MPS_PORT_PAUSE_CTL 0x4
31382 #define S_TIMEUNIT    0
31383 #define M_TIMEUNIT    0xffffU
31387 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
31390 #define M_REGSENDOFF    0xffU
31395 #define M_REGSENDON    0xffU
31400 #define M_SGESENDEN    0xffU
31404 #define S_RXSENDEN    0
31405 #define M_RXSENDEN    0xffU
31409 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
31411 #define S_XOFFDISABLE    0
31415 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
31418 #define M_REGHALTON    0xffU
31422 #define S_RXHALTEN    0
31423 #define M_RXHALTEN    0xffU
31427 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
31430 #define M_REGSENDING    0xffU
31435 #define M_SGESENDING    0xffU
31439 #define S_RXSENDING    0
31440 #define M_RXSENDING    0xffU
31444 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
31447 #define M_REGHALTED    0xffU
31451 #define S_RXHALTED    0
31452 #define M_RXHALTED    0xffU
31456 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
31457 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
31459 #define S_ADDR    0
31460 #define M_ADDR    0xffffU
31464 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
31465 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
31466 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
31469 #define M_PRTY7    0x3U
31474 #define M_PRTY6    0x3U
31479 #define M_PRTY5    0x3U
31484 #define M_PRTY4    0x3U
31489 #define M_PRTY3    0x3U
31494 #define M_PRTY2    0x3U
31499 #define M_PRTY1    0x3U
31503 #define S_PRTY0    0
31504 #define M_PRTY0    0x3U
31508 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
31511 #define M_TXPRTY7    0xfU
31516 #define M_TXPRTY6    0xfU
31521 #define M_TXPRTY5    0xfU
31526 #define M_TXPRTY4    0xfU
31531 #define M_TXPRTY3    0xfU
31536 #define M_TXPRTY2    0xfU
31541 #define M_TXPRTY1    0xfU
31545 #define S_TXPRTY0    0
31546 #define M_TXPRTY0    0xfU
31550 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
31551 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
31552 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
31553 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
31554 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
31555 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
31556 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
31557 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
31558 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
31559 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
31560 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
31561 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
31562 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
31563 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
31564 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
31565 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
31566 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
31567 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
31568 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
31569 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
31570 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
31571 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
31572 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
31573 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
31574 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
31575 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
31576 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
31577 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
31578 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
31579 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
31580 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
31581 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
31582 #define A_MPS_PORT_RX_CTL 0x100
31589 #define M_RPLCT_SEL_L    0x3U
31661 #define S_OVLAN_EN0    0
31685 #define A_MPS_PORT_RX_MTU 0x104
31686 #define A_MPS_PORT_RX_PF_MAP 0x108
31687 #define A_MPS_PORT_RX_VF_MAP0 0x10c
31688 #define A_MPS_PORT_RX_VF_MAP1 0x110
31689 #define A_MPS_PORT_RX_VF_MAP2 0x114
31690 #define A_MPS_PORT_RX_VF_MAP3 0x118
31691 #define A_MPS_PORT_RX_IVLAN 0x11c
31693 #define S_IVLAN_ETYPE    0
31694 #define M_IVLAN_ETYPE    0xffffU
31698 #define A_MPS_PORT_RX_OVLAN0 0x120
31701 #define M_OVLAN_MASK    0xffffU
31705 #define S_OVLAN_ETYPE    0
31706 #define M_OVLAN_ETYPE    0xffffU
31710 #define A_MPS_PORT_RX_OVLAN1 0x124
31711 #define A_MPS_PORT_RX_OVLAN2 0x128
31712 #define A_MPS_PORT_RX_OVLAN3 0x12c
31713 #define A_MPS_PORT_RX_RSS_HASH 0x130
31714 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
31717 #define M_RSS_CTRL    0xffU
31721 #define S_QUE_NUM    0
31722 #define M_QUE_NUM    0xffffU
31726 #define A_MPS_PORT_RX_CTL1 0x138
31741 #define M_FIXED_PF    0x7U
31749 #define S_FIXED_VF    0
31750 #define M_FIXED_VF    0x7fU
31767 #define M_T6_FIXED_PF    0x7U
31775 #define S_T6_FIXED_VF    0
31776 #define M_T6_FIXED_VF    0xffU
31780 #define A_MPS_PORT_RX_SPARE 0x13c
31781 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
31782 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
31783 #define A_MPS_PORT_RX_TS_VLD 0x148
31785 #define S_TS_VLD    0
31786 #define M_TS_VLD    0x3U
31790 #define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
31792 #define S_LKP_SEL    0
31796 #define A_MPS_PORT_RX_VF_MAP4 0x150
31797 #define A_MPS_PORT_RX_VF_MAP5 0x154
31798 #define A_MPS_PORT_RX_VF_MAP6 0x158
31799 #define A_MPS_PORT_RX_VF_MAP7 0x15c
31800 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
31902 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
31916 #define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
31922 #define S_REPL_VECT_SEL    0
31923 #define M_REPL_VECT_SEL    0xfU
31927 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
31929 #define S_CREDIT    0
31930 #define M_CREDIT    0xffffU
31934 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
31935 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
31936 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
31937 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
31938 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
31939 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
31940 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
31941 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
31942 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
31943 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
31946 #define M_FIFOTH    0x1ffU
31954 #define S_MAXPKTCNT    0
31955 #define M_MAXPKTCNT    0xfU
31960 #define M_OUT_TH    0xffU
31965 #define M_IN_TH    0xffU
31969 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
31971 #define S_FPGAPAUSEEN    0
31975 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
31978 #define M_OFF_PENDING    0xffU
31982 #define S_ON_PENDING    0
31983 #define M_ON_PENDING    0xffU
31987 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
31994 #define M_HASHPORTMAP    0xfU
32003 #define M_PRIORITY    0x7U
32012 #define M_PF    0x7U
32020 #define S_VF    0
32021 #define M_VF    0x7fU
32038 #define M_T6_HASHPORTMAP    0xfU
32047 #define M_T6_PRIORITY    0x7U
32056 #define M_T6_PF    0x7U
32064 #define S_T6_VF    0
32065 #define M_T6_VF    0xffU
32069 #define A_MPS_PF_CTL 0x2c0
32075 #define S_RXEN    0
32079 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
32082 #define M_PROTOCOLID    0xffffU
32087 #define M_VLAN_PRIO    0x7U
32095 #define S_TAG    0
32096 #define M_TAG    0xfffU
32100 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
32101 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
32102 #define A_MPS_PORT_CLS_HASH_CTL 0x304
32108 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
32109 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
32120 #define M_T6_PRIORITY    0x7U
32129 #define M_T6_PF    0x7U
32137 #define S_T6_VF    0
32138 #define M_T6_VF    0xffU
32142 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
32143 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
32144 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
32145 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
32159 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
32160 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
32170 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
32171 #define A_MPS_PORT_CLS_CTL 0x318
32173 #define S_PF_VLAN_SEL    0
32190 #define M_LPBK_SMAC_TCAM_SEL    0x3U
32195 #define M_LPBK_DMAC_TCAM_SEL    0x3U
32212 #define M_SMAC_TCAM_SEL    0x3U
32217 #define M_DMAC_TCAM_SEL    0x3U
32221 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
32222 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
32224 #define S_ETHTYPE2    0
32225 #define M_ETHTYPE2    0xffffU
32229 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
32230 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
32236 #define S_EN2    0
32240 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
32241 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
32242 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
32243 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
32244 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
32245 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
32246 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
32247 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
32248 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
32249 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
32250 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
32251 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
32252 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
32253 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
32254 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
32255 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
32256 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
32257 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
32258 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
32259 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
32260 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
32261 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
32262 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
32263 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
32264 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
32265 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
32266 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
32267 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
32268 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
32269 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
32270 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
32271 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
32272 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
32273 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
32274 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
32275 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
32276 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
32277 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
32278 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
32279 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
32280 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
32281 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
32282 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
32283 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
32284 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
32285 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
32286 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
32287 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
32288 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
32289 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
32290 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
32291 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
32292 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
32293 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
32294 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
32295 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
32296 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
32297 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
32298 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
32299 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
32300 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
32301 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
32302 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
32303 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
32304 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
32305 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
32306 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
32307 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
32308 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
32309 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
32310 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
32311 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
32312 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
32313 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
32314 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
32315 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
32316 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
32317 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
32318 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
32319 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
32320 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
32321 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
32322 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
32323 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
32324 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
32325 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
32326 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
32327 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
32328 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
32329 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
32330 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
32331 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
32332 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
32333 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
32334 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
32335 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
32336 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
32337 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
32338 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
32339 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
32340 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
32341 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
32342 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
32343 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
32344 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
32345 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
32346 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
32347 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
32348 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
32349 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
32350 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
32351 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
32352 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
32353 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
32354 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
32355 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
32356 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
32357 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
32358 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
32359 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
32360 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
32361 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
32362 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
32363 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
32364 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
32365 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
32366 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
32367 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
32368 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
32369 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
32370 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
32371 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
32372 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
32373 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
32374 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
32375 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
32376 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
32377 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
32378 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
32379 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
32380 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
32381 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
32382 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
32383 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
32384 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
32385 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
32386 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
32387 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
32388 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
32389 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
32390 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
32391 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
32392 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
32393 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
32394 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
32395 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
32396 #define A_MPS_CMN_CTL 0x9000
32406 #define S_NUMPORTS    0
32407 #define M_NUMPORTS    0x3U
32424 #define M_SPEEDMODE    0x3U
32428 #define A_MPS_INT_ENABLE 0x9004
32450 #define S_PLINTENB    0
32454 #define A_MPS_INT_CAUSE 0x9008
32476 #define S_PLINT    0
32480 #define A_MPS_CGEN_GLOBAL 0x900c
32482 #define S_MPS_GLOBAL_CGEN    0
32486 #define A_MPS_VF_TX_CTL_31_0 0x9010
32487 #define A_MPS_VF_TX_CTL_63_32 0x9014
32488 #define A_MPS_VF_TX_CTL_95_64 0x9018
32489 #define A_MPS_VF_TX_CTL_127_96 0x901c
32490 #define A_MPS_VF_RX_CTL_31_0 0x9020
32491 #define A_MPS_VF_RX_CTL_63_32 0x9024
32492 #define A_MPS_VF_RX_CTL_95_64 0x9028
32493 #define A_MPS_VF_RX_CTL_127_96 0x902c
32494 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
32496 #define S_VALUE    0
32497 #define M_VALUE    0xffffU
32501 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
32502 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
32503 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
32504 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
32505 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
32506 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
32507 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
32508 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
32510 #define S_WEIGHT    0
32511 #define M_WEIGHT    0xfffU
32515 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
32516 #define A_MPS_WOL_CTL_MODE 0x9058
32518 #define S_WOL_MODE    0
32522 #define A_MPS_FPGA_DEBUG 0x9060
32529 #define M_CH_MAP3    0x3U
32534 #define M_CH_MAP2    0x3U
32539 #define M_CH_MAP1    0x3U
32543 #define S_CH_MAP0    0
32544 #define M_CH_MAP0    0x3U
32549 #define M_FPGA_PTP_PORT    0x3U
32553 #define A_MPS_DEBUG_CTL 0x9068
32560 #define M_DBGSEL_H    0x1fU
32568 #define S_DBGSEL_L    0
32569 #define M_DBGSEL_L    0x1fU
32573 #define A_MPS_DEBUG_DATA_REG_L 0x906c
32574 #define A_MPS_DEBUG_DATA_REG_H 0x9070
32575 #define A_MPS_TOP_SPARE 0x9074
32578 #define M_TOPSPARE    0xffffffU
32610 #define S_OVLANSELMAC0    0
32615 #define M_T5_TOPSPARE    0xffffffU
32619 #define A_MPS_T5_BUILD_REVISION 0x9078
32620 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
32621 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
32622 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
32623 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
32624 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
32625 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
32626 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
32627 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
32628 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
32629 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
32630 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
32631 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
32632 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
32633 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
32634 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
32635 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
32636 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
32637 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
32638 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
32639 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
32640 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
32641 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
32642 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
32643 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
32644 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
32645 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
32646 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
32647 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
32648 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
32649 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
32650 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
32651 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
32652 #define A_MPS_BUILD_REVISION 0x90fc
32653 #define A_MPS_VF_TX_CTL_159_128 0x9100
32654 #define A_MPS_VF_TX_CTL_191_160 0x9104
32655 #define A_MPS_VF_TX_CTL_223_192 0x9108
32656 #define A_MPS_VF_TX_CTL_255_224 0x910c
32657 #define A_MPS_VF_RX_CTL_159_128 0x9110
32658 #define A_MPS_VF_RX_CTL_191_160 0x9114
32659 #define A_MPS_VF_RX_CTL_223_192 0x9118
32660 #define A_MPS_VF_RX_CTL_255_224 0x911c
32661 #define A_MPS_FPGA_BIST_CFG_P0 0x9120
32664 #define M_ADDRMASK    0xffffU
32668 #define S_T6_BASEADDR    0
32669 #define M_T6_BASEADDR    0xffffU
32673 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
32675 #define S_T6_BASEADDR    0
32676 #define M_T6_BASEADDR    0xffffU
32680 #define A_MPS_TX_PRTY_SEL 0x9400
32683 #define M_CH4_PRTY    0x7U
32688 #define M_CH3_PRTY    0x7U
32693 #define M_CH2_PRTY    0x7U
32698 #define M_CH1_PRTY    0x7U
32703 #define M_CH0_PRTY    0x7U
32708 #define M_TP_SOURCE    0x3U
32712 #define S_NCSI_SOURCE    0
32713 #define M_NCSI_SOURCE    0x3U
32717 #define A_MPS_TX_INT_ENABLE 0x9404
32736 #define M_TXDESCFIFO    0xfU
32741 #define M_TXDATAFIFO    0xfU
32749 #define S_TPFIFO    0
32750 #define M_TPFIFO    0xfU
32754 #define A_MPS_TX_INT_CAUSE 0x9408
32755 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
32756 #define A_MPS_TX_PERR_ENABLE 0x9410
32757 #define A_MPS_TX_PERR_INJECT 0x9414
32760 #define M_MPSTXMEMSEL    0x1fU
32764 #define A_MPS_TX_SE_CNT_TP01 0x9418
32765 #define A_MPS_TX_SE_CNT_TP23 0x941c
32766 #define A_MPS_TX_SE_CNT_MAC01 0x9420
32767 #define A_MPS_TX_SE_CNT_MAC23 0x9424
32768 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
32771 #define M_BUBBLEERR    0xffU
32776 #define M_SPI    0xffU
32780 #define S_SECNT    0
32781 #define M_SECNT    0xffU
32785 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
32788 #define M_BUBBLECLR    0xffU
32797 #define M_LPBKSECNT    0xfU
32801 #define A_MPS_TX_PORT_ERR 0x9430
32831 #define S_PT0    0
32835 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
32841 #define S_DROPEN    0
32845 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
32846 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
32847 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
32848 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
32859 #define M_SIZECH1    0x7U
32876 #define M_DATACH1    0xffU
32889 #define M_SIZECH0    0x7U
32905 #define S_DATACH0    0
32906 #define M_DATACH0    0xffU
32911 #define M_T5_SIZECH1    0xfU
32928 #define M_T5_DATACH1    0x7fU
32933 #define M_T5_SIZECH0    0xfU
32949 #define S_T5_DATACH0    0
32950 #define M_T5_DATACH0    0x7fU
32954 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
32965 #define M_SIZECH3    0x7U
32982 #define M_DATACH3    0xffU
32995 #define M_SIZECH2    0x7U
33011 #define S_DATACH2    0
33012 #define M_DATACH2    0xffU
33017 #define M_T5_SIZECH3    0xfU
33034 #define M_T5_DATACH3    0x7fU
33039 #define M_T5_SIZECH2    0xfU
33055 #define S_T5_DATACH2    0
33056 #define M_T5_DATACH2    0x7fU
33060 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
33071 #define M_SIZEPT1    0x7U
33088 #define M_DATAPT1    0xffU
33101 #define M_SIZEPT0    0x7U
33117 #define S_DATAPT0    0
33118 #define M_DATAPT0    0xffU
33123 #define M_T5_SIZEPT1    0xfU
33140 #define M_T5_DATAPT1    0x7fU
33145 #define M_T5_SIZEPT0    0xfU
33161 #define S_T5_DATAPT0    0
33162 #define M_T5_DATAPT0    0x7fU
33166 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
33177 #define M_SIZEPT3    0x7U
33194 #define M_DATAPT3    0xffU
33207 #define M_SIZEPT2    0x7U
33223 #define S_DATAPT2    0
33224 #define M_DATAPT2    0xffU
33229 #define M_T5_SIZEPT3    0xfU
33246 #define M_T5_DATAPT3    0x7fU
33251 #define M_T5_SIZEPT2    0xfU
33267 #define S_T5_DATAPT2    0
33268 #define M_T5_DATAPT2    0x7fU
33272 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
33274 #define S_SGEPAUSEIGNR    0
33275 #define M_SGEPAUSEIGNR    0xfU
33279 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
33281 #define S_T5SGEPAUSEIGNR    0
33282 #define M_T5SGEPAUSEIGNR    0xffffU
33286 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
33289 #define M_SUBPRTH    0x1fU
33294 #define M_PORTH    0x7U
33299 #define M_SUBPRTL    0x1fU
33303 #define S_PORTL    0
33304 #define M_PORTL    0x7U
33308 #define A_MPS_TX_PAD_CTL 0x945c
33338 #define S_MACPADENPT0    0
33342 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
33345 #define M_TP2MPS_CH3    0xffU
33350 #define M_TP2MPS_CH2    0xffU
33355 #define M_TP2MPS_CH1    0xffU
33359 #define S_TP2MPS_CH0    0
33360 #define M_TP2MPS_CH0    0xffU
33364 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
33366 #define S_NCSI_CH4    0
33367 #define M_NCSI_CH4    0xffU
33371 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
33393 #define S_TP2MPS_CH0_CLR    0
33397 #define A_MPS_TX_CGEN 0x946c
33483 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
33484 #define A_MPS_STAT_CTL 0x9600
33490 #define S_LPBKERRSTAT    0
33530 #define A_MPS_STAT_INT_ENABLE 0x9608
33532 #define S_PLREADSYNCERR    0
33536 #define A_MPS_STAT_INT_CAUSE 0x960c
33537 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
33544 #define M_RXVF    0x3U
33549 #define M_TXVF    0x3U
33554 #define M_RXPF    0x7U
33559 #define M_TXPF    0x3U
33564 #define M_RXPORT    0xfU
33569 #define M_LBPORT    0x7U
33573 #define S_TXPORT    0
33574 #define M_TXPORT    0xfU
33579 #define M_T5_RXBG    0x3U
33584 #define M_T5_RXPF    0x1fU
33589 #define M_T5_TXPF    0xfU
33594 #define M_T5_RXPORT    0x7fU
33599 #define M_T5_LBPORT    0x1fU
33603 #define S_T5_TXPORT    0
33604 #define M_T5_TXPORT    0x3fU
33608 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
33609 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
33610 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
33613 #define M_TX    0xffU
33618 #define M_TXPAUSEFIFO    0xfU
33622 #define S_DROP    0
33623 #define M_DROP    0xffU
33628 #define M_TXCH    0xfU
33632 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
33633 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
33634 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
33637 #define M_PAUSEFIFO    0xfU
33642 #define M_LPBK    0xfU
33647 #define M_NQ    0xffU
33652 #define M_PV    0xfU
33656 #define S_MAC    0
33657 #define M_MAC    0xfU
33661 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
33662 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
33663 #define A_MPS_STAT_PERR_INJECT 0x9634
33666 #define M_STATMEMSEL    0x7fU
33670 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
33673 #define M_STATSSUBPRTH    0x1fU
33677 #define S_STATSSUBPRTL    0
33678 #define M_STATSSUBPRTL    0x1fU
33683 #define M_STATSUBPRTH    0x1fU
33687 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
33688 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
33689 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
33690 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
33691 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
33692 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
33693 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
33694 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
33695 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
33696 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
33697 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
33698 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
33699 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
33700 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
33701 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
33702 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
33703 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
33704 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
33705 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
33706 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
33707 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
33708 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
33709 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
33710 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
33711 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
33712 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
33713 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
33714 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
33715 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
33716 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
33717 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
33718 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
33719 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
33722 #define M_T5_RXVF    0x7U
33726 #define S_T5_TXVF    0
33727 #define M_T5_TXVF    0x1fU
33731 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
33732 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
33733 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
33735 #define S_BGRX    0
33736 #define M_BGRX    0xfU
33740 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
33743 #define M_PTLPBK    0xfU
33748 #define M_PTTX    0xfU
33752 #define S_PTRX    0
33753 #define M_PTRX    0xfU
33757 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
33760 #define M_PFTX    0xffU
33764 #define S_PFRX    0
33765 #define M_PFRX    0xffU
33769 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
33770 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
33771 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
33772 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
33773 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
33774 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
33775 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
33776 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
33777 #define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
33778 #define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
33779 #define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
33780 #define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
33781 #define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
33782 #define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
33783 #define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
33784 #define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
33785 #define A_MPS_TRC_CFG 0x9800
33803 #define S_TRCMULTIFILTER    0
33811 #define A_MPS_TRC_RSS_HASH 0x9804
33812 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
33813 #define A_MPS_TRC_RSS_CONTROL 0x9808
33816 #define M_RSSCONTROL    0xffU
33820 #define S_QUEUENUMBER    0
33821 #define M_QUEUENUMBER    0xffffU
33825 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
33826 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
33841 #define M_TFPORT    0xfU
33854 #define M_TFLENGTH    0x1fU
33858 #define S_TFOFFSET    0
33859 #define M_TFOFFSET    0x1fU
33884 #define M_T5_TFPORT    0x1fU
33888 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
33891 #define M_TFMINPKTSIZE    0x1ffU
33895 #define S_TFCAPTUREMAX    0
33896 #define M_TFCAPTUREMAX    0x3fffU
33900 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
33902 #define S_TFRUNTSIZE    0
33903 #define M_TFRUNTSIZE    0x3fU
33907 #define A_MPS_TRC_FILTER_DROP 0x9840
33910 #define M_TFDROPINPCOUNT    0xffffU
33914 #define S_TFDROPBUFFERCOUNT    0
33915 #define M_TFDROPBUFFERCOUNT    0xffffU
33919 #define A_MPS_TRC_PERR_INJECT 0x9850
33922 #define M_TRCMEMSEL    0xfU
33926 #define A_MPS_TRC_PERR_ENABLE 0x9854
33933 #define M_PKTFIFO    0xfU
33937 #define S_FILTMEM    0
33938 #define M_FILTMEM    0xfU
33942 #define A_MPS_TRC_INT_ENABLE 0x9858
33948 #define A_MPS_TRC_INT_CAUSE 0x985c
33949 #define A_MPS_TRC_TIMESTAMP_L 0x9860
33950 #define A_MPS_TRC_TIMESTAMP_H 0x9864
33951 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
33952 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
33953 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
33954 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
33955 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
33956 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
33957 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
33958 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
33959 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
33960 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
33961 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
33962 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
33963 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
33964 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
33965 #define A_MPS_T5_TRC_RSS_HASH 0xa008
33966 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
33967 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
33994 #define M_VFFILTMASK    0x7fU
34002 #define S_VFFILTDATA    0
34003 #define M_VFFILTDATA    0x7fU
34032 #define M_T6_VFFILTMASK    0xffU
34040 #define S_T6_VFFILTDATA    0
34041 #define M_T6_VFFILTDATA    0xffU
34045 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
34072 #define M_T6_VFFILTMASK    0xffU
34080 #define S_T6_VFFILTDATA    0
34081 #define M_T6_VFFILTDATA    0xffU
34085 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
34112 #define M_T6_VFFILTMASK    0xffU
34120 #define S_T6_VFFILTDATA    0
34121 #define M_T6_VFFILTDATA    0xffU
34125 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
34152 #define M_T6_VFFILTMASK    0xffU
34160 #define S_T6_VFFILTDATA    0
34161 #define M_T6_VFFILTDATA    0xffU
34165 #define A_MPS_TRC_CGEN 0xa020
34167 #define S_MPSTRCCGEN    0
34168 #define M_MPSTRCCGEN    0xfU
34172 #define A_MPS_CLS_CTL 0xd000
34190 #define S_VLANCLSEN    0
34206 #define A_MPS_CLS_ARB_WEIGHT 0xd004
34209 #define M_PLWEIGHT    0x1fU
34214 #define M_CIMWEIGHT    0x1fU
34218 #define S_LPBKWEIGHT    0
34219 #define M_LPBKWEIGHT    0x1fU
34223 #define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
34224 #define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
34225 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
34226 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
34227 #define A_MPS_CLS_BMC_VLAN 0xd018
34228 #define A_MPS_CLS_PERR_INJECT 0xd01c
34231 #define M_CLS_MEMSEL    0x3U
34235 #define A_MPS_CLS_PERR_ENABLE 0xd020
34245 #define S_MATCHSRAM    0
34249 #define A_MPS_CLS_INT_ENABLE 0xd024
34255 #define A_MPS_CLS_INT_CAUSE 0xd028
34256 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
34257 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
34258 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
34261 #define M_CLS_PRIORITY    0x7U
34270 #define M_CLS_INDEX    0x1ffU
34275 #define M_CLS_VF    0x7fU
34284 #define M_CLS_PF    0x7U
34288 #define S_CLS_MATCH    0
34289 #define M_CLS_MATCH    0x7U
34294 #define M_CLS_SPARE    0xfU
34299 #define M_T6_CLS_PRIORITY    0x7U
34308 #define M_T6_CLS_INDEX    0x1ffU
34313 #define M_T6_CLS_VF    0xffU
34317 #define A_MPS_CLS_PL_TEST_CTL 0xd038
34319 #define S_PLTESTCTL    0
34323 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
34325 #define S_PRTBMCCTL    0
34329 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
34330 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
34331 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
34332 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
34333 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
34334 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
34335 #define A_MPS_CLS_MISS_CNT 0xd118
34336 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
34337 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
34339 #define S_CLSTRCMACDAHI    0
34340 #define M_CLSTRCMACDAHI    0xffffU
34344 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
34345 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
34347 #define S_CLSTRCMACSAHI    0
34348 #define M_CLSTRCMACSAHI    0xffffU
34352 #define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
34359 #define M_CLSTRCVLANID    0xfffU
34363 #define S_CLSTRCREQPORT    0
34364 #define M_CLSTRCREQPORT    0xfU
34368 #define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
34378 #define S_CLSTRCVNI    0
34379 #define M_CLSTRCVNI    0xffffffU
34383 #define A_MPS_CLS_RESULT_TRACE 0xd300
34390 #define M_CLSTRCPRIORITY    0x7U
34403 #define M_CLSTRCPORTMAP    0x3U
34408 #define M_CLSTRCMATCH    0x7U
34413 #define M_CLSTRCINDEX    0x1ffU
34422 #define M_CLSTRCPF    0xffU
34426 #define S_CLSTRCVF    0
34427 #define M_CLSTRCVF    0x7U
34431 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
34434 #define M_VLAN_MASK    0xfffU
34439 #define M_VLANPF    0x7U
34447 #define A_MPS_CLS_SRAM_L 0xe000
34466 #define M_SRAM_PRIO3    0x7U
34471 #define M_SRAM_PRIO2    0x7U
34476 #define M_SRAM_PRIO1    0x7U
34481 #define M_SRAM_PRIO0    0x7U
34489 #define A_MPS_T5_CLS_SRAM_L 0xe000
34516 #define M_T6_SRAM_PRIO3    0x7U
34521 #define M_T6_SRAM_PRIO2    0x7U
34526 #define M_T6_SRAM_PRIO1    0x7U
34531 #define M_T6_SRAM_PRIO0    0x7U
34544 #define M_T6_PF    0x7U
34552 #define S_T6_VF    0
34553 #define M_T6_VF    0xffU
34557 #define A_MPS_CLS_SRAM_H 0xe004
34568 #define M_MACPARITYMASKSIZE    0xfU
34572 #define S_PORTMAP    0
34573 #define M_PORTMAP    0xfU
34577 #define A_MPS_T5_CLS_SRAM_H 0xe004
34583 #define A_MPS_CLS_TCAM_Y_L 0xf000
34584 #define A_MPS_CLS_TCAM_DATA0 0xf000
34585 #define A_MPS_CLS_TCAM_Y_H 0xf004
34587 #define S_TCAMYH    0
34588 #define M_TCAMYH    0xffffU
34592 #define A_MPS_CLS_TCAM_DATA1 0xf004
34595 #define M_VIDL    0xffffU
34599 #define S_DMACH    0
34600 #define M_DMACH    0xffffU
34604 #define A_MPS_CLS_TCAM_X_L 0xf008
34605 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
34620 #define M_CTLTCAMINDEX    0xffU
34629 #define M_DATAPORTNUM    0xfU
34634 #define M_DATALKPTYPE    0x3U
34646 #define S_DATAVIDH1    0
34647 #define M_DATAVIDH1    0x7fU
34651 #define A_MPS_CLS_TCAM_X_H 0xf00c
34653 #define S_TCAMXH    0
34654 #define M_TCAMXH    0xffffU
34658 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
34659 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
34660 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
34661 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
34662 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
34663 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
34664 #define A_MPS_RX_CTL 0x11000
34675 #define M_BLK_SNDR    0xfU
34680 #define M_CMPRS    0xfU
34684 #define S_SNF    0
34685 #define M_SNF    0xffU
34689 #define A_MPS_RX_PORT_MUX_CTL 0x11004
34692 #define M_CTL_P3    0xfU
34697 #define M_CTL_P2    0xfU
34702 #define M_CTL_P1    0xfU
34706 #define S_CTL_P0    0
34707 #define M_CTL_P0    0xfU
34711 #define A_MPS_RX_PG_FL 0x11008
34717 #define S_CNT    0
34718 #define M_CNT    0xffffU
34722 #define A_MPS_RX_FIFO_0_CTL 0x11008
34724 #define S_DEST_SELECT    0
34725 #define M_DEST_SELECT    0xfU
34729 #define A_MPS_RX_PKT_FL 0x1100c
34730 #define A_MPS_RX_FIFO_1_CTL 0x1100c
34731 #define A_MPS_RX_PG_RSV0 0x11010
34742 #define M_USED    0x7ffU
34746 #define S_ALLOC    0
34747 #define M_ALLOC    0x7ffU
34752 #define M_T5_USED    0xfffU
34756 #define S_T5_ALLOC    0
34757 #define M_T5_ALLOC    0xfffU
34761 #define A_MPS_RX_FIFO_2_CTL 0x11010
34762 #define A_MPS_RX_PG_RSV1 0x11014
34763 #define A_MPS_RX_FIFO_3_CTL 0x11014
34764 #define A_MPS_RX_PG_RSV2 0x11018
34765 #define A_MPS_RX_PG_RSV3 0x1101c
34766 #define A_MPS_RX_PG_RSV4 0x11020
34767 #define A_MPS_RX_PG_RSV5 0x11024
34768 #define A_MPS_RX_PG_RSV6 0x11028
34769 #define A_MPS_RX_PG_RSV7 0x1102c
34770 #define A_MPS_RX_PG_SHR_BG0 0x11030
34781 #define M_MAX    0x7ffU
34785 #define S_BORW    0
34786 #define M_BORW    0x7ffU
34791 #define M_T5_MAX    0xfffU
34795 #define S_T5_BORW    0
34796 #define M_T5_BORW    0xfffU
34800 #define A_MPS_RX_PG_SHR_BG1 0x11034
34801 #define A_MPS_RX_PG_SHR_BG2 0x11038
34802 #define A_MPS_RX_PG_SHR_BG3 0x1103c
34803 #define A_MPS_RX_PG_SHR0 0x11040
34806 #define M_QUOTA    0x7ffU
34810 #define S_SHR_USED    0
34811 #define M_SHR_USED    0x7ffU
34816 #define M_T5_QUOTA    0xfffU
34820 #define S_T5_SHR_USED    0
34821 #define M_T5_SHR_USED    0xfffU
34825 #define A_MPS_RX_PG_SHR1 0x11044
34826 #define A_MPS_RX_PG_HYST_BG0 0x11048
34828 #define S_TH    0
34829 #define M_TH    0x7ffU
34833 #define S_T5_TH    0
34834 #define M_T5_TH    0xfffU
34838 #define S_T6_TH    0
34839 #define M_T6_TH    0x7ffU
34843 #define A_MPS_RX_PG_HYST_BG1 0x1104c
34844 #define A_MPS_RX_PG_HYST_BG2 0x11050
34845 #define A_MPS_RX_PG_HYST_BG3 0x11054
34846 #define A_MPS_RX_OCH_CTL 0x11058
34849 #define M_DROP_WT    0x1fU
34854 #define M_TRUNC_WT    0x1fU
34859 #define M_OCH_DRAIN    0x1fU
34864 #define M_OCH_DROP    0x1fU
34868 #define S_STOP    0
34869 #define M_STOP    0x1fU
34873 #define A_MPS_RX_LPBK_BP0 0x1105c
34875 #define S_THRESH    0
34876 #define M_THRESH    0x7ffU
34880 #define A_MPS_RX_LPBK_BP1 0x11060
34881 #define A_MPS_RX_LPBK_BP2 0x11064
34882 #define A_MPS_RX_LPBK_BP3 0x11068
34883 #define A_MPS_RX_PORT_GAP 0x1106c
34885 #define S_GAP    0
34886 #define M_GAP    0xfffffU
34890 #define A_MPS_RX_CHMN_CNT 0x11070
34891 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
34985 #define S_CDM0    0
34993 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
34999 #define A_MPS_RX_PERR_ENABLE 0x1107c
35005 #define A_MPS_RX_PERR_INJECT 0x11080
35006 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
35009 #define M_INT_ERR_INT    0x1fU
35041 #define S_PG_TH_INT0    0
35073 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
35074 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
35077 #define M_TH_HIGH    0xffffU
35081 #define S_TH_LOW    0
35082 #define M_TH_LOW    0xffffU
35086 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
35087 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
35088 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
35089 #define A_MPS_RX_REPL_CTL 0x11098
35091 #define S_INDEX_SEL    0
35095 #define A_MPS_RX_PPP_ATRB 0x1109c
35098 #define M_ETYPE    0xffffU
35102 #define S_OPCODE    0
35103 #define M_OPCODE    0xffffU
35107 #define A_MPS_RX_QFC0_ATRB 0x110a0
35109 #define S_DA    0
35110 #define M_DA    0xffffU
35114 #define A_MPS_RX_QFC1_ATRB 0x110a4
35115 #define A_MPS_RX_PT_ARB0 0x110a8
35118 #define M_LPBK_WT    0x3fffU
35122 #define S_MAC_WT    0
35123 #define M_MAC_WT    0x3fffU
35127 #define A_MPS_RX_PT_ARB1 0x110ac
35128 #define A_MPS_RX_PT_ARB2 0x110b0
35129 #define A_MPS_RX_PT_ARB3 0x110b4
35130 #define A_T6_MPS_PF_OUT_EN 0x110b4
35131 #define A_MPS_RX_PT_ARB4 0x110b8
35132 #define A_T6_MPS_BMC_MTU 0x110b8
35133 #define A_MPS_PF_OUT_EN 0x110bc
35135 #define S_OUTEN    0
35136 #define M_OUTEN    0xffU
35140 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
35141 #define A_MPS_BMC_MTU 0x110c0
35143 #define S_MTU    0
35144 #define M_MTU    0x3fffU
35148 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
35149 #define A_MPS_BMC_PKT_CNT 0x110c4
35150 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
35152 #define S_T6_PFVF    0
35153 #define M_T6_PFVF    0x1ffU
35157 #define A_MPS_BMC_BYTE_CNT 0x110c8
35158 #define A_T6_MPS_PFVF_ATRB 0x110c8
35164 #define A_MPS_PFVF_ATRB_CTL 0x110cc
35170 #define S_PFVF    0
35171 #define M_PFVF    0xffU
35175 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
35176 #define A_MPS_PFVF_ATRB 0x110d0
35179 #define M_ATTR_PF    0x7U
35195 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
35196 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
35202 #define S_VLAN_ID    0
35203 #define M_VLAN_ID    0xfffU
35207 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
35208 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
35209 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
35210 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
35211 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
35212 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
35213 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
35214 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
35215 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
35216 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
35217 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
35218 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
35219 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
35220 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
35221 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
35222 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
35223 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
35224 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
35225 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
35226 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
35227 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
35228 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
35229 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
35230 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
35231 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
35232 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
35233 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
35234 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
35235 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
35236 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
35237 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
35238 #define A_MPS_RPLC_MAP_CTL 0x11114
35240 #define S_RPLC_MAP_ADDR    0
35241 #define M_RPLC_MAP_ADDR    0x3ffU
35245 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
35246 #define A_MPS_PF_RPLCT_MAP 0x11118
35248 #define S_PF_EN    0
35249 #define M_PF_EN    0xffU
35253 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
35254 #define A_MPS_VF_RPLCT_MAP0 0x1111c
35255 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
35256 #define A_MPS_VF_RPLCT_MAP1 0x11120
35257 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
35258 #define A_MPS_VF_RPLCT_MAP2 0x11124
35259 #define A_MPS_VF_RPLCT_MAP3 0x11128
35260 #define A_MPS_MEM_DBG_CTL 0x1112c
35270 #define A_MPS_PKD_MEM_DATA0 0x11130
35271 #define A_MPS_PKD_MEM_DATA1 0x11134
35272 #define A_MPS_PKD_MEM_DATA2 0x11138
35273 #define A_MPS_PGD_MEM_DATA 0x1113c
35274 #define A_MPS_RX_SE_CNT_ERR 0x11140
35276 #define S_RX_SE_ERRMAP    0
35277 #define M_RX_SE_ERRMAP    0xfffffU
35281 #define A_MPS_RX_SE_CNT_CLR 0x11144
35282 #define A_MPS_RX_SE_CNT_IN0 0x11148
35285 #define M_SOP_CNT_PM    0xffU
35290 #define M_EOP_CNT_PM    0xffU
35295 #define M_SOP_CNT_IN    0xffU
35299 #define S_EOP_CNT_IN    0
35300 #define M_EOP_CNT_IN    0xffU
35304 #define A_MPS_RX_SE_CNT_IN1 0x1114c
35305 #define A_MPS_RX_SE_CNT_IN2 0x11150
35306 #define A_MPS_RX_SE_CNT_IN3 0x11154
35307 #define A_MPS_RX_SE_CNT_IN4 0x11158
35308 #define A_MPS_RX_SE_CNT_IN5 0x1115c
35309 #define A_MPS_RX_SE_CNT_IN6 0x11160
35310 #define A_MPS_RX_SE_CNT_IN7 0x11164
35311 #define A_MPS_RX_SE_CNT_OUT01 0x11168
35314 #define M_SOP_CNT_1    0xffU
35319 #define M_EOP_CNT_1    0xffU
35324 #define M_SOP_CNT_0    0xffU
35328 #define S_EOP_CNT_0    0
35329 #define M_EOP_CNT_0    0xffU
35333 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
35336 #define M_SOP_CNT_3    0xffU
35341 #define M_EOP_CNT_3    0xffU
35346 #define M_SOP_CNT_2    0xffU
35350 #define S_EOP_CNT_2    0
35351 #define M_EOP_CNT_2    0xffU
35355 #define A_MPS_RX_SPI_ERR 0x11170
35358 #define M_LENERR    0xfU
35362 #define S_SPIERR    0
35363 #define M_SPIERR    0x1fffffU
35367 #define A_MPS_RX_IN_BUS_STATE 0x11174
35370 #define M_ST3    0xffU
35375 #define M_ST2    0xffU
35380 #define M_ST1    0xffU
35384 #define S_ST0    0
35385 #define M_ST0    0xffU
35389 #define A_MPS_RX_OUT_BUS_STATE 0x11178
35392 #define M_ST_NCSI    0x1ffU
35396 #define S_ST_TP    0
35397 #define M_ST_TP    0x7fffffU
35401 #define A_MPS_RX_DBG_CTL 0x1117c
35404 #define M_OUT_DBG_CHNL    0x7U
35417 #define M_IN_DBG_PORT    0x7U
35421 #define S_IN_DBG_CHNL    0
35422 #define M_IN_DBG_CHNL    0x7U
35426 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
35429 #define M_LPBK_CNT0    0xffffU
35433 #define S_MAC_CNT0    0
35434 #define M_MAC_CNT0    0xffffU
35438 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
35441 #define M_LPBK_CNT1    0xffffU
35445 #define S_MAC_CNT1    0
35446 #define M_MAC_CNT1    0xffffU
35450 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
35453 #define M_LPBK_CNT2    0xffffU
35457 #define S_MAC_CNT2    0
35458 #define M_MAC_CNT2    0xffffU
35462 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
35465 #define M_LPBK_CNT3    0xffffU
35469 #define S_MAC_CNT3    0
35470 #define M_MAC_CNT3    0xffffU
35474 #define A_MPS_RX_SPARE 0x11190
35475 #define A_MPS_RX_PTP_ETYPE 0x11194
35478 #define M_PETYPE2    0xffffU
35482 #define S_PETYPE1    0
35483 #define M_PETYPE1    0xffffU
35487 #define A_MPS_RX_PTP_TCP 0x11198
35490 #define M_PTCPORT2    0xffffU
35494 #define S_PTCPORT1    0
35495 #define M_PTCPORT1    0xffffU
35499 #define A_MPS_RX_PTP_UDP 0x1119c
35502 #define M_PUDPORT2    0xffffU
35506 #define S_PUDPORT1    0
35507 #define M_PUDPORT1    0xffffU
35511 #define A_MPS_RX_PTP_CTL 0x111a0
35514 #define M_MIN_PTP_SPACE    0x7fU
35519 #define M_PUDP2EN    0xfU
35524 #define M_PUDP1EN    0xfU
35529 #define M_PTCP2EN    0xfU
35534 #define M_PTCP1EN    0xfU
35539 #define M_PETYPE2EN    0xfU
35543 #define S_PETYPE1EN    0
35544 #define M_PETYPE1EN    0xfU
35548 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
35549 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
35550 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
35551 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
35552 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
35553 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
35554 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
35555 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
35556 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
35557 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
35558 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
35559 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
35560 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
35561 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
35562 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
35563 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
35564 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
35565 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
35566 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
35567 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
35568 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
35569 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
35570 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
35571 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
35572 #define A_MPS_RX_CGEN 0x11204
35579 #define M_MPS_RX_CGEN_OUT    0xfU
35584 #define M_MPS_RX_CGEN_LPBK_IN    0xfU
35588 #define S_MPS_RX_CGEN_MAC_IN    0
35589 #define M_MPS_RX_CGEN_MAC_IN    0xfU
35593 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
35596 #define M_MAC_USED    0x7ffU
35600 #define S_MAC_ALLOC    0
35601 #define M_MAC_ALLOC    0x7ffU
35605 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
35606 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
35607 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
35608 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
35611 #define M_LPBK_USED    0x7ffU
35615 #define S_LPBK_ALLOC    0
35616 #define M_LPBK_ALLOC    0x7ffU
35620 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
35621 #define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
35627 #define S_CONG_TH    0
35628 #define M_CONG_TH    0xfffffU
35632 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
35633 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
35634 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
35635 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
35645 #define S_GRE    0
35646 #define M_GRE    0xffU
35650 #define A_MPS_RX_VXLAN_TYPE 0x11234
35656 #define S_VXLAN    0
35657 #define M_VXLAN    0xffffU
35661 #define A_MPS_RX_GENEVE_TYPE 0x11238
35667 #define S_GENEVE    0
35668 #define M_GENEVE    0xffffU
35672 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
35678 #define A_MPS_RX_ENCAP_NVGRE 0x11240
35684 #define S_T6_ETYPE    0
35685 #define M_T6_ETYPE    0xffffU
35689 #define A_MPS_RX_ENCAP_GENEVE 0x11244
35691 #define S_T6_ETYPE    0
35692 #define M_T6_ETYPE    0xffffU
35696 #define A_MPS_RX_TCP 0x11248
35702 #define S_PROT_TYPE    0
35703 #define M_PROT_TYPE    0xffU
35707 #define A_MPS_RX_UDP 0x1124c
35708 #define A_MPS_RX_PAUSE 0x11250
35709 #define A_MPS_RX_LENGTH 0x11254
35712 #define M_SAP_VALUE    0xffffU
35716 #define S_LENGTH_ETYPE    0
35717 #define M_LENGTH_ETYPE    0xffffU
35721 #define A_MPS_RX_CTL_ORG 0x11258
35724 #define M_CTL_VALUE    0xffU
35728 #define S_ORG_VALUE    0
35729 #define M_ORG_VALUE    0xffffffU
35733 #define A_MPS_RX_IPV4 0x1125c
35735 #define S_ETYPE_IPV4    0
35736 #define M_ETYPE_IPV4    0xffffU
35740 #define A_MPS_RX_IPV6 0x11260
35742 #define S_ETYPE_IPV6    0
35743 #define M_ETYPE_IPV6    0xffffU
35747 #define A_MPS_RX_TTL 0x11264
35750 #define M_TTL_IPV4    0xffU
35755 #define M_TTL_IPV6    0xffU
35763 #define S_TTL_CHK_EN_IPV6    0
35767 #define A_MPS_RX_DEFAULT_VNI 0x11268
35769 #define S_VNI    0
35770 #define M_VNI    0xffffffU
35774 #define A_MPS_RX_PRS_CTL 0x1126c
35793 #define M_VXLAN_FLAG_MASK    0xffU
35798 #define M_VXLAN_FLAG    0xffU
35807 #define M_GRE_VER    0x7U
35816 #define M_GENEVE_VER    0x3U
35824 #define A_MPS_RX_PRS_CTL_2 0x11270
35842 #define S_T6_IPV6_UDP_CSUM_COMPAT    0
35846 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
35847 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
35849 #define S_T6_LEN    0
35850 #define M_T6_LEN    0x1ffU
35854 #define A_MPS_RX_PAUSE_DA_H 0x1127c
35855 #define A_MPS_RX_PAUSE_DA_L 0x11280
35856 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
35857 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
35858 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
35859 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
35860 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
35861 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
35862 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
35863 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
35864 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
35865 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
35866 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
35867 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
35868 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
35869 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
35870 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
35871 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
35872 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
35873 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
35874 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
35875 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
35876 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
35877 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
35878 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
35879 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
35880 #define A_MPS_VF_RPLCT_MAP4 0x11300
35881 #define A_MPS_VF_RPLCT_MAP5 0x11304
35882 #define A_MPS_VF_RPLCT_MAP6 0x11308
35883 #define A_MPS_VF_RPLCT_MAP7 0x1130c
35884 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
35885 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
35886 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
35887 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
35888 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
35889 #define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
35890 #define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
35891 #define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
35892 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
35893 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
35894 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
35897 #define CPL_SWITCH_BASE_ADDR 0x19040
35899 #define A_CPL_SWITCH_CNTRL 0x19040
35902 #define M_CPL_PKT_TID    0xffffffU
35926 #define S_CIM_ENABLE    0
35934 #define A_CPL_SWITCH_TBL_IDX 0x19044
35936 #define S_SWITCH_TBL_IDX    0
35937 #define M_SWITCH_TBL_IDX    0xfU
35941 #define A_CPL_SWITCH_TBL_DATA 0x19048
35942 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
35945 #define M_ZERO_CMD_CH1    0xffU
35949 #define S_ZERO_CMD_CH0    0
35950 #define M_ZERO_CMD_CH0    0xffU
35954 #define A_CPL_INTR_ENABLE 0x19050
35976 #define S_ZERO_SWITCH_ERROR    0
35988 #define A_CPL_INTR_CAUSE 0x19054
35989 #define A_CPL_MAP_TBL_IDX 0x19058
35991 #define S_MAP_TBL_IDX    0
35992 #define M_MAP_TBL_IDX    0xffU
36000 #define A_CPL_MAP_TBL_DATA 0x1905c
36002 #define S_MAP_TBL_DATA    0
36003 #define M_MAP_TBL_DATA    0xffU
36008 #define SMB_BASE_ADDR 0x19060
36010 #define A_SMB_GLOBAL_TIME_CFG 0x19060
36013 #define M_MACROCNTCFG    0x1fU
36017 #define S_MICROCNTCFG    0
36018 #define M_MICROCNTCFG    0xffU
36022 #define A_SMB_MST_TIMEOUT_CFG 0x19064
36024 #define S_MSTTIMEOUTCFG    0
36025 #define M_MSTTIMEOUTCFG    0xffffffU
36029 #define A_SMB_MST_CTL_CFG 0x19068
36040 #define M_MSTRXBYTECFG    0x3fU
36045 #define M_MSTTXBYTECFG    0x3fU
36053 #define S_MSTCTLEN    0
36057 #define A_SMB_MST_CTL_STS 0x1906c
36060 #define M_MSTRXBYTECNT    0x3fU
36065 #define M_MSTTXBYTECNT    0x3fU
36069 #define S_MSTBUSYSTS    0
36073 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
36074 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
36075 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
36077 #define S_SLVTIMEOUTCFG    0
36078 #define M_SLVTIMEOUTCFG    0xffffffU
36082 #define A_SMB_SLV_CTL_CFG 0x1907c
36105 #define M_SLVCRCPRESET    0xffU
36110 #define M_SLVADDRCFG    0x7fU
36122 #define S_SLVCTLEN    0
36126 #define A_SMB_SLV_CTL_STS 0x19080
36129 #define M_SLVFIFOTXCNT    0x3fU
36134 #define M_SLVFIFOCNT    0x3fU
36142 #define S_SLVBUSYSTS    0
36146 #define A_SMB_SLV_FIFO_RDWR 0x19084
36147 #define A_SMB_INT_ENABLE 0x1908c
36233 #define S_MSTDONEINTEN    0
36237 #define A_SMB_INT_CAUSE 0x19090
36323 #define S_MSTDONEINT    0
36327 #define A_SMB_DEBUG_DATA 0x19094
36330 #define M_DEBUGDATAH    0xffffU
36334 #define S_DEBUGDATAL    0
36335 #define M_DEBUGDATAL    0xffffU
36339 #define A_SMB_PERR_EN 0x19098
36349 #define S_SLVFIFOPERREN    0
36365 #define A_SMB_PERR_INJ 0x1909c
36379 #define S_FIFOINJDATAERREN    0
36383 #define A_SMB_SLV_ARP_CTL 0x190a0
36386 #define M_ARPCOMMANDCODE    0xffU
36394 #define S_ARPADDRVAL    0
36398 #define A_SMB_ARP_UDID0 0x190a4
36399 #define A_SMB_ARP_UDID1 0x190a8
36402 #define M_SUBSYSTEMVENDORID    0xffffU
36406 #define S_SUBSYSTEMDEVICEID    0
36407 #define M_SUBSYSTEMDEVICEID    0xffffU
36411 #define A_SMB_ARP_UDID2 0x190ac
36414 #define M_DEVICEID    0xffffU
36418 #define S_INTERFACE    0
36419 #define M_INTERFACE    0xffffU
36423 #define A_SMB_ARP_UDID3 0x190b0
36426 #define M_DEVICECAP    0xffU
36431 #define M_VERSIONID    0xffU
36435 #define S_VENDORID    0
36436 #define M_VENDORID    0xffffU
36440 #define A_SMB_SLV_AUX_ADDR0 0x190b4
36446 #define S_AUXADDR0    0
36447 #define M_AUXADDR0    0x3fU
36451 #define A_SMB_SLV_AUX_ADDR1 0x190b8
36457 #define S_AUXADDR1    0
36458 #define M_AUXADDR1    0x3fU
36462 #define A_SMB_SLV_AUX_ADDR2 0x190bc
36468 #define S_AUXADDR2    0
36469 #define M_AUXADDR2    0x3fU
36473 #define A_SMB_SLV_AUX_ADDR3 0x190c0
36479 #define S_AUXADDR3    0
36480 #define M_AUXADDR3    0x3fU
36484 #define A_SMB_COMMAND_CODE0 0x190c4
36486 #define S_SMBUSCOMMANDCODE0    0
36487 #define M_SMBUSCOMMANDCODE0    0xffU
36491 #define A_SMB_COMMAND_CODE1 0x190c8
36493 #define S_SMBUSCOMMANDCODE1    0
36494 #define M_SMBUSCOMMANDCODE1    0xffU
36498 #define A_SMB_COMMAND_CODE2 0x190cc
36500 #define S_SMBUSCOMMANDCODE2    0
36501 #define M_SMBUSCOMMANDCODE2    0xffU
36505 #define A_SMB_COMMAND_CODE3 0x190d0
36507 #define S_SMBUSCOMMANDCODE3    0
36508 #define M_SMBUSCOMMANDCODE3    0xffU
36512 #define A_SMB_COMMAND_CODE4 0x190d4
36514 #define S_SMBUSCOMMANDCODE4    0
36515 #define M_SMBUSCOMMANDCODE4    0xffU
36519 #define A_SMB_COMMAND_CODE5 0x190d8
36521 #define S_SMBUSCOMMANDCODE5    0
36522 #define M_SMBUSCOMMANDCODE5    0xffU
36526 #define A_SMB_COMMAND_CODE6 0x190dc
36528 #define S_SMBUSCOMMANDCODE6    0
36529 #define M_SMBUSCOMMANDCODE6    0xffU
36533 #define A_SMB_COMMAND_CODE7 0x190e0
36535 #define S_SMBUSCOMMANDCODE7    0
36536 #define M_SMBUSCOMMANDCODE7    0xffU
36540 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
36543 #define M_MACROCNTCLKCFG    0x1fU
36547 #define S_MICROCNTCLKCFG    0
36548 #define M_MICROCNTCLKCFG    0xffU
36552 #define A_SMB_CTL_STATUS 0x190e8
36562 #define S_BUSBUSY    0
36567 #define I2CM_BASE_ADDR 0x190f0
36569 #define A_I2CM_CFG 0x190f0
36571 #define S_I2C_CLKDIV    0
36572 #define M_I2C_CLKDIV    0xfffU
36576 #define S_I2C_CLKDIV16B    0
36577 #define M_I2C_CLKDIV16B    0xffffU
36581 #define A_I2CM_DATA 0x190f4
36583 #define S_I2C_DATA    0
36584 #define M_I2C_DATA    0xffU
36588 #define A_I2CM_OP 0x190f8
36598 #define S_OP    0
36603 #define MI_BASE_ADDR 0x19100
36605 #define A_MI_CFG 0x19100
36612 #define M_CLKDIV    0xffU
36617 #define M_ST    0x3U
36629 #define S_MDIO_1P2V_SEL    0
36633 #define A_MI_ADDR 0x19104
36636 #define M_PHYADDR    0x1fU
36640 #define S_REGADDR    0
36641 #define M_REGADDR    0x1fU
36645 #define A_MI_DATA 0x19108
36647 #define S_MDIDATA    0
36648 #define M_MDIDATA    0xffffU
36652 #define A_MI_OP 0x1910c
36658 #define S_MDIOP    0
36659 #define M_MDIOP    0x3U
36664 #define UART_BASE_ADDR 0x19110
36666 #define A_UART_CONFIG 0x19110
36669 #define M_STOPBITS    0x3U
36674 #define M_PARITY    0x3U
36679 #define M_DATABITS    0xfU
36683 #define S_UART_CLKDIV    0
36684 #define M_UART_CLKDIV    0xfffU
36689 #define PMU_BASE_ADDR 0x19120
36691 #define A_PMU_PART_CG_PWRMODE 0x19120
36721 #define S_INITPOWERMODE    0
36722 #define M_INITPOWERMODE    0x3U
36770 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
36792 #define S_WAKEUP    0
36801 #define ULP_RX_BASE_ADDR 0x19150
36803 #define A_ULP_RX_CTL 0x19150
36806 #define M_PCMD1THRESHOLD    0xffU
36811 #define M_PCMD0THRESHOLD    0xffU
36820 #define M_RDMA_0B_WR_OPCODE    0xfU
36860 #define S_TDDPTAGTCB    0
36864 #define A_ULP_RX_INT_ENABLE 0x19154
36962 #define S_ENABLE_MPARC_0    0
36974 #define A_ULP_RX_INT_CAUSE 0x19158
37072 #define S_CAUSE_MPARC_0    0
37076 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
37079 #define M_ISCSILLIMIT    0x3ffffffU
37083 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
37086 #define M_ISCSIULIMIT    0x3ffffffU
37090 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
37093 #define M_ISCSITAGMASK    0x3ffffffU
37097 #define A_ULP_RX_ISCSI_PSZ 0x19168
37100 #define M_HPZ3    0xfU
37105 #define M_HPZ2    0xfU
37110 #define M_HPZ1    0xfU
37114 #define S_HPZ0    0
37115 #define M_HPZ0    0xfU
37119 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
37122 #define M_TDDPLLIMIT    0x3ffffffU
37126 #define A_ULP_RX_TDDP_ULIMIT 0x19170
37129 #define M_TDDPULIMIT    0x3ffffffU
37133 #define A_ULP_RX_TDDP_TAGMASK 0x19174
37136 #define M_TDDPTAGMASK    0x3ffffffU
37140 #define A_ULP_RX_TDDP_PSZ 0x19178
37141 #define A_ULP_RX_STAG_LLIMIT 0x1917c
37142 #define A_ULP_RX_STAG_ULIMIT 0x19180
37143 #define A_ULP_RX_RQ_LLIMIT 0x19184
37144 #define A_ULP_RX_RQ_ULIMIT 0x19188
37145 #define A_ULP_RX_PBL_LLIMIT 0x1918c
37146 #define A_ULP_RX_PBL_ULIMIT 0x19190
37147 #define A_ULP_RX_CTX_BASE 0x19194
37148 #define A_ULP_RX_PERR_ENABLE 0x1919c
37238 #define S_PERR_ENABLE_MPARC_0    0
37266 #define A_ULP_RX_PERR_INJECT 0x191a0
37267 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
37268 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
37269 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
37279 #define S_ULPRX_TID    0
37280 #define M_ULPRX_TID    0xfffffU
37284 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
37285 #define A_ULP_RX_SE_CNT_ERR 0x191d0
37286 #define A_ULP_RX_SE_CNT_CLR 0x191d4
37289 #define M_CLRCHAN0    0xfU
37293 #define S_CLRCHAN1    0
37294 #define M_CLRCHAN1    0xfU
37298 #define A_ULP_RX_SE_CNT_CH0 0x191d8
37301 #define M_SOP_CNT_OUT0    0xfU
37306 #define M_EOP_CNT_OUT0    0xfU
37311 #define M_SOP_CNT_AL0    0xfU
37316 #define M_EOP_CNT_AL0    0xfU
37321 #define M_SOP_CNT_MR0    0xfU
37326 #define M_EOP_CNT_MR0    0xfU
37331 #define M_SOP_CNT_IN0    0xfU
37335 #define S_EOP_CNT_IN0    0
37336 #define M_EOP_CNT_IN0    0xfU
37340 #define A_ULP_RX_SE_CNT_CH1 0x191dc
37343 #define M_SOP_CNT_OUT1    0xfU
37348 #define M_EOP_CNT_OUT1    0xfU
37353 #define M_SOP_CNT_AL1    0xfU
37358 #define M_EOP_CNT_AL1    0xfU
37363 #define M_SOP_CNT_MR1    0xfU
37368 #define M_EOP_CNT_MR1    0xfU
37373 #define M_SOP_CNT_IN1    0xfU
37377 #define S_EOP_CNT_IN1    0
37378 #define M_EOP_CNT_IN1    0xfU
37382 #define A_ULP_RX_DBG_CTL 0x191e0
37393 #define M_SEL_H    0xffU
37397 #define S_SEL_L    0
37398 #define M_SEL_L    0xffU
37402 #define A_ULP_RX_DBG_DATAH 0x191e4
37403 #define A_ULP_RX_DBG_DATAL 0x191e8
37404 #define A_ULP_RX_LA_CHNL 0x19238
37406 #define S_CHNL_SEL    0
37410 #define A_ULP_RX_LA_CTL 0x1923c
37412 #define S_TRC_SEL    0
37416 #define A_ULP_RX_LA_RDPTR 0x19240
37418 #define S_RD_PTR    0
37419 #define M_RD_PTR    0x1ffU
37423 #define A_ULP_RX_LA_RDDATA 0x19244
37424 #define A_ULP_RX_LA_WRPTR 0x19248
37426 #define S_WR_PTR    0
37427 #define M_WR_PTR    0x1ffU
37431 #define A_ULP_RX_LA_RESERVED 0x1924c
37432 #define A_ULP_RX_CQE_GEN_EN 0x19250
37438 #define S_TERMINATE_WITH_ERR    0
37442 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
37445 #define M_ATOMIC_REQ_QNO    0x3U
37450 #define M_ATOMIC_RSP_QNO    0x3U
37455 #define M_IMMEDIATE_QNO    0x3U
37460 #define M_IMMEDIATE_WITH_SE_QNO    0x3U
37465 #define M_ATOMIC_WR_OPCODE    0xfU
37470 #define M_ATOMIC_RD_OPCODE    0xfU
37475 #define M_IMMEDIATE_OPCODE    0xfU
37479 #define S_IMMEDIATE_WITH_SE_OPCODE    0
37480 #define M_IMMEDIATE_WITH_SE_OPCODE    0xfU
37484 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
37486 #define S_EN_ORIG_DATA    0
37490 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
37508 #define S_SDC_CRC_PROT_EN    0
37521 #define M_DDP_VERSION_1    0x3U
37526 #define M_DDP_VERSION_0    0x3U
37531 #define M_RDMA_VERSION_1    0x3U
37536 #define M_RDMA_VERSION_0    0x3U
37584 #define A_ULP_RX_CH0_CGEN 0x19260
37614 #define S_RDMA_DATAPATH_CGEN    0
37618 #define A_ULP_RX_CH1_CGEN 0x19264
37619 #define A_ULP_RX_RFE_DISABLE 0x19268
37621 #define S_RQE_LIM_CHECK_RFE_DISABLE    0
37625 #define A_ULP_RX_INT_ENABLE_2 0x1926c
37659 #define S_DDP_HINT_0    0
37663 #define A_ULP_RX_INT_CAUSE_2 0x19270
37664 #define A_ULP_RX_PERR_ENABLE_2 0x19274
37698 #define S_ENABLE_DDP_HINT_0    0
37702 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
37704 #define S_PIO_RQE_PBL_MULTIPLE_CNT    0
37705 #define M_PIO_RQE_PBL_MULTIPLE_CNT    0xfU
37709 #define A_ULP_RX_ATOMIC_LEN 0x1927c
37712 #define M_ATOMIC_RPL_LEN    0xffU
37717 #define M_ATOMIC_REQ_LEN    0xffU
37721 #define S_ATOMIC_IMMEDIATE_LEN    0
37722 #define M_ATOMIC_IMMEDIATE_LEN    0xffU
37726 #define A_ULP_RX_CGEN_GLOBAL 0x19280
37727 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
37741 #define S_SKIP_MA_REQ_EN0    0
37745 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
37746 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
37747 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
37757 #define S_SEND_MSN_CHECK_ENABLE    0
37761 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
37764 #define M_TLSPPLLIMIT    0x3ffffffU
37768 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
37771 #define M_TLSPPULIMIT    0x3ffffffU
37775 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
37778 #define M_TLSKEYLLIMIT    0xffffffU
37782 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
37785 #define M_TLSKEYULIMIT    0xffffffU
37789 #define A_ULP_RX_TLS_CTL 0x192bc
37790 #define A_ULP_RX_TLS_IND_CMD 0x19348
37792 #define S_TLS_RX_REG_OFF_ADDR    0
37793 #define M_TLS_RX_REG_OFF_ADDR    0x3ffU
37797 #define A_ULP_RX_TLS_IND_DATA 0x1934c
37800 #define SF_BASE_ADDR 0x193f8
37802 #define A_SF_DATA 0x193f8
37803 #define A_SF_OP 0x193fc
37814 #define M_BYTECNT    0x3U
37819 #define PL_BASE_ADDR 0x19400
37821 #define A_PL_VF_WHOAMI 0x0
37824 #define M_PORTXMAP    0x7U
37829 #define M_SOURCEBUS    0x3U
37834 #define M_SOURCEPF    0x7U
37842 #define S_VFID    0
37843 #define M_VFID    0x7fU
37848 #define M_T6_SOURCEPF    0x7U
37856 #define S_T6_VFID    0
37857 #define M_T6_VFID    0xffU
37861 #define A_PL_VF_REV 0x4
37864 #define M_CHIPID    0xfU
37868 #define A_PL_VF_REVISION 0x8
37869 #define A_PL_PF_INT_CAUSE 0x3c0
37883 #define S_PFMPS    0
37887 #define A_PL_PF_INT_ENABLE 0x3c4
37888 #define A_PL_PF_CTL 0x3c8
37890 #define S_SWINT    0
37894 #define A_PL_WHOAMI 0x19400
37897 #define M_T6_SOURCEPF    0x7U
37905 #define S_T6_VFID    0
37906 #define M_T6_VFID    0xffU
37910 #define A_PL_PERR_CAUSE 0x19404
38024 #define S_CIM    0
38040 #define A_PL_PERR_ENABLE 0x19408
38041 #define A_PL_INT_CAUSE 0x1940c
38067 #define A_PL_INT_ENABLE 0x19410
38068 #define A_PL_INT_MAP0 0x19414
38071 #define M_MAPNCSI    0x1ffU
38075 #define S_MAPDEFAULT    0
38076 #define M_MAPDEFAULT    0x1ffU
38080 #define A_PL_INT_MAP1 0x19418
38083 #define M_MAPXGMAC1    0x1ffU
38087 #define S_MAPXGMAC0    0
38088 #define M_MAPXGMAC0    0x1ffU
38093 #define M_MAPMAC1    0x1ffU
38097 #define S_MAPMAC0    0
38098 #define M_MAPMAC0    0x1ffU
38102 #define A_PL_INT_MAP2 0x1941c
38105 #define M_MAPXGMAC_KR1    0x1ffU
38109 #define S_MAPXGMAC_KR0    0
38110 #define M_MAPXGMAC_KR0    0x1ffU
38115 #define M_MAPMAC3    0x1ffU
38119 #define S_MAPMAC2    0
38120 #define M_MAPMAC2    0x1ffU
38124 #define A_PL_INT_MAP3 0x19420
38127 #define M_MAPMI    0x1ffU
38131 #define S_MAPSMB    0
38132 #define M_MAPSMB    0x1ffU
38136 #define A_PL_INT_MAP4 0x19424
38139 #define M_MAPDBG    0x1ffU
38143 #define S_MAPI2CM    0
38144 #define M_MAPI2CM    0x1ffU
38148 #define A_PL_RST 0x19428
38162 #define S_PIORSTMODE    0
38170 #define A_PL_PL_PERR_INJECT 0x1942c
38176 #define A_PL_PL_INT_CAUSE 0x19430
38198 #define S_PERRVFID    0
38206 #define A_PL_PL_INT_ENABLE 0x19434
38207 #define A_PL_PL_PERR_ENABLE 0x19438
38208 #define A_PL_REV 0x1943c
38210 #define S_REV    0
38211 #define M_REV    0xfU
38215 #define A_PL_PCIE_LINK 0x19440
38218 #define M_LN0_AESTAT    0x7U
38223 #define M_LN0_AECMD    0x7U
38228 #define M_T5_STATECFGINITF    0x7fU
38233 #define M_T5_STATECFGINIT    0xfU
38238 #define M_PCIE_SPEED    0x3U
38250 #define S_LTSSM    0
38251 #define M_LTSSM    0x3fU
38256 #define M_T6_LN0_AESTAT    0x7U
38261 #define M_T6_LN0_AECMD    0x7U
38266 #define M_T6_STATECFGINITF    0xffU
38271 #define M_T6_STATECFGINIT    0xfU
38280 #define M_SPEED_PL    0x3U
38292 #define A_PL_PCIE_CTL_STAT 0x19444
38295 #define M_PCIE_STATUS    0xffffU
38299 #define S_PCIE_CONTROL    0
38300 #define M_PCIE_CONTROL    0xffffU
38304 #define A_PL_SEMAPHORE_CTL 0x1944c
38307 #define M_LOCKSTATUS    0xffU
38315 #define S_ENABLEPF    0
38316 #define M_ENABLEPF    0xffU
38320 #define A_PL_SEMAPHORE_LOCK 0x19450
38327 #define M_SEMSRCBUS    0x3U
38331 #define S_SEMSRCPF    0
38332 #define M_SEMSRCPF    0x7U
38336 #define A_PL_PF_ENABLE 0x19470
38338 #define S_PF_ENABLE    0
38339 #define M_PF_ENABLE    0xffU
38343 #define A_PL_PORTX_MAP 0x19474
38346 #define M_MAP7    0x7U
38351 #define M_MAP6    0x7U
38356 #define M_MAP5    0x7U
38361 #define M_MAP4    0x7U
38366 #define M_MAP3    0x7U
38371 #define M_MAP2    0x7U
38376 #define M_MAP1    0x7U
38380 #define S_MAP0    0
38381 #define M_MAP0    0x7U
38385 #define A_PL_VF_SLICE_L 0x19490
38388 #define M_LIMITADDR    0x3ffU
38392 #define S_SLICEBASEADDR    0
38393 #define M_SLICEBASEADDR    0x3ffU
38397 #define A_PL_VF_SLICE_H 0x19494
38400 #define M_MODINDX    0x7U
38404 #define S_MODOFFSET    0
38405 #define M_MODOFFSET    0x3ffU
38409 #define A_PL_FLR_VF_STATUS 0x194d0
38410 #define A_PL_FLR_PF_STATUS 0x194e0
38412 #define S_FLR_PF    0
38413 #define M_FLR_PF    0xffU
38417 #define A_PL_TIMEOUT_CTL 0x194f0
38419 #define S_PL_TIMEOUT    0
38420 #define M_PL_TIMEOUT    0xffffU
38428 #define A_PL_TIMEOUT_STATUS0 0x194f4
38431 #define M_PL_TOADDR    0xfffffffU
38435 #define A_PL_TIMEOUT_STATUS1 0x194f8
38446 #define M_PL_TOBUS    0x3U
38455 #define M_PL_TOPF    0x7U
38459 #define S_PL_TORID    0
38460 #define M_PL_TORID    0xffffU
38468 #define S_PL_TOVFID    0
38469 #define M_PL_TOVFID    0xffU
38473 #define S_T6_PL_TOVFID    0
38474 #define M_T6_PL_TOVFID    0x1ffU
38478 #define A_PL_VFID_MAP 0x19800
38485 #define LE_BASE_ADDR 0x19c00
38487 #define A_LE_BUF_CONFIG 0x19c00
38488 #define A_LE_DB_ID 0x19c00
38489 #define A_LE_DB_CONFIG 0x19c04
38516 #define M_SYNMODE    0x3U
38540 #define S_CMDOVERLAPDIS    0
38636 #define S_REGION_EN    0
38637 #define M_REGION_EN    0xfU
38641 #define A_LE_MISC 0x19c08
38643 #define S_CMPUNVAIL    0
38644 #define M_CMPUNVAIL    0xfU
38680 #define A_LE_DB_EXEC_CTRL 0x19c08
38694 #define S_CMDLIMIT    0
38695 #define M_CMDLIMIT    0xffU
38699 #define A_LE_DB_PS_CTRL 0x19c0c
38717 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
38720 #define M_RTINDX    0x3fU
38724 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
38726 #define S_ATINDX    0
38727 #define M_ATINDX    0xfffffU
38731 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
38734 #define M_FTINDX    0x3fU
38738 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
38740 #define S_NFTINDX    0
38741 #define M_NFTINDX    0xfffffU
38745 #define A_LE_DB_SERVER_INDEX 0x19c18
38748 #define M_SRINDX    0x3fU
38752 #define A_LE_DB_SRVR_START_INDEX 0x19c18
38754 #define S_T6_SRINDX    0
38755 #define M_T6_SRINDX    0xfffffU
38759 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
38762 #define M_CLIPTINDX    0x3fU
38766 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
38768 #define S_HFTINDX    0
38769 #define M_HFTINDX    0xfffffU
38773 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
38775 #define S_ACTCNTIPV4    0
38776 #define M_ACTCNTIPV4    0xfffffU
38780 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
38782 #define S_ACTCNTIPV6    0
38783 #define M_ACTCNTIPV6    0xfffffU
38787 #define A_LE_DB_HASH_CONFIG 0x19c28
38790 #define M_HASHTIDSIZE    0x3fU
38794 #define S_HASHSIZE    0
38795 #define M_HASHSIZE    0x3fU
38800 #define M_NUMHASHBKT    0x1fU
38805 #define M_HASHTBLSIZE    0x1ffffU
38809 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
38810 #define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
38812 #define S_MIN_ATCAM_ENTS    0
38813 #define M_MIN_ATCAM_ENTS    0xfffffU
38817 #define A_LE_DB_HASH_TID_BASE 0x19c30
38818 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
38821 #define M_HASHTBLADDR    0xfffffffU
38825 #define A_LE_DB_SIZE 0x19c34
38826 #define A_LE_TCAM_SIZE 0x19c34
38828 #define S_TCAM_SIZE    0
38829 #define M_TCAM_SIZE    0x3U
38833 #define A_LE_DB_INT_ENABLE 0x19c38
38836 #define M_MSGSEL    0x1fU
38900 #define S_SERVERHIT    0
39044 #define S_PIPELINEERR    0
39048 #define A_LE_DB_INT_CAUSE 0x19c3c
39082 #define A_LE_DB_INT_TID 0x19c40
39084 #define S_INTTID    0
39085 #define M_INTTID    0xfffffU
39089 #define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
39092 #define M_CMD_CMP_MASK    0x1fU
39096 #define S_TID_CMP_MASK    0
39097 #define M_TID_CMP_MASK    0xfffffU
39101 #define A_LE_DB_INT_PTID 0x19c44
39103 #define S_INTPTID    0
39104 #define M_INTPTID    0xfffffU
39108 #define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
39111 #define M_CMD_CMP    0x1fU
39115 #define S_TID_CMP    0
39116 #define M_TID_CMP    0xfffffU
39120 #define A_LE_DB_INT_INDEX 0x19c48
39122 #define S_INTINDEX    0
39123 #define M_INTINDEX    0xfffffU
39127 #define A_LE_DB_ERR_CMD_TID 0x19c48
39130 #define M_ERR_CID    0xffU
39135 #define M_ERR_PROT    0x3U
39139 #define S_ERR_TID    0
39140 #define M_ERR_TID    0xfffffU
39144 #define A_LE_DB_INT_CMD 0x19c4c
39146 #define S_INTCMD    0
39147 #define M_INTCMD    0xfU
39151 #define A_LE_DB_MASK_IPV4 0x19c50
39152 #define A_LE_T5_DB_MASK_IPV4 0x19c50
39153 #define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
39154 #define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
39156 #define S_MAX_HASH_ENTS    0
39157 #define M_MAX_HASH_ENTS    0xfffffU
39161 #define A_LE_DB_RSP_CODE_0 0x19c74
39164 #define M_SUCCESS    0x1fU
39169 #define M_TCAM_ACTV_SUCC    0x1fU
39174 #define M_HASH_ACTV_SUCC    0x1fU
39179 #define M_TCAM_SRVR_HIT    0x1fU
39184 #define M_SRAM_SRVR_HIT    0x1fU
39188 #define S_TCAM_ACTV_HIT    0
39189 #define M_TCAM_ACTV_HIT    0x1fU
39193 #define A_LE_DB_RSP_CODE_1 0x19c78
39196 #define M_HASH_ACTV_HIT    0x1fU
39201 #define M_T6_MISS    0x1fU
39206 #define M_NORM_FILT_HIT    0x1fU
39211 #define M_HPRI_FILT_HIT    0x1fU
39216 #define M_ACTV_OPEN_ERR    0x1fU
39220 #define S_ACTV_FULL_ERR    0
39221 #define M_ACTV_FULL_ERR    0x1fU
39225 #define A_LE_DB_RSP_CODE_2 0x19c7c
39228 #define M_SRCH_RGN_HIT    0x1fU
39233 #define M_CLIP_FAIL    0x1fU
39238 #define M_LIP_ZERO_ERR    0x1fU
39243 #define M_UNKNOWN_CMD    0x1fU
39248 #define M_CMD_TID_ERR    0x1fU
39252 #define S_INTERNAL_ERR    0
39253 #define M_INTERNAL_ERR    0x1fU
39257 #define A_LE_DB_RSP_CODE_3 0x19c80
39260 #define M_SRAM_SRVR_HIT_ACTF    0x1fU
39265 #define M_TCAM_SRVR_HIT_ACTF    0x1fU
39270 #define M_INVLDRD    0x1fU
39275 #define M_TUPLZERO    0x1fU
39279 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
39280 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
39281 #define A_LE_ACT_CNT_THRSH 0x19c9c
39283 #define S_ACT_CNT_THRSH    0
39284 #define M_ACT_CNT_THRSH    0x1fffffU
39288 #define A_LE_DB_MASK_IPV6 0x19ca0
39289 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
39290 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
39293 #define M_T4_RSPCNT    0xffffU
39297 #define S_T4_REQCNT    0
39298 #define M_T4_REQCNT    0xffffU
39303 #define M_RSPCNTLE    0xffffU
39307 #define S_REQCNTLE    0
39308 #define M_REQCNTLE    0xffffU
39312 #define A_LE_DB_DBGI_CONFIG 0x19cf0
39319 #define M_DBGICMDRANGE    0x7U
39348 #define M_DBGICMDTYPE    0x7U
39364 #define S_DBGICMDMODE    0
39365 #define M_DBGICMDMODE    0x3U
39377 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
39380 #define M_DBGICMD    0xfU
39384 #define S_DBGITINDEX    0
39385 #define M_DBGITINDEX    0xfffffU
39389 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
39391 #define S_DBGITID    0
39392 #define M_DBGITID    0xfffffU
39396 #define A_LE_PERR_ENABLE 0x19cf8
39402 #define S_TCAM    0
39423 #define M_BKCHKPERIOD    0x3ffU
39439 #define A_LE_SPARE 0x19cfc
39440 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
39441 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
39442 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
39445 #define M_DBGIRSPINDEX    0xfffffU
39450 #define M_DBGIRSPMSG    0xfU
39466 #define S_DBGIRSPVALID    0
39471 #define M_DBGIRSPTID    0xfffffU
39479 #define A_LE_DBG_SEL 0x19d98
39480 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
39481 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
39484 #define M_LASTCMDB    0x7ffU
39488 #define S_LASTCMDA    0
39489 #define M_LASTCMDA    0x7ffU
39493 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
39507 #define S_DROPFILTERFIDX    0
39508 #define M_DROPFILTERFIDX    0x1fffU
39512 #define A_LE_DB_PTID_SVRBASE 0x19df0
39515 #define M_SVRBASE_ADDR    0x3ffffU
39519 #define A_LE_DB_TCAM_TID_BASE 0x19df0
39521 #define S_TCAM_TID_BASE    0
39522 #define M_TCAM_TID_BASE    0xfffffU
39526 #define A_LE_DB_FTID_FLTRBASE 0x19df4
39529 #define M_FLTRBASE_ADDR    0x3ffffU
39533 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
39535 #define S_CLCAM_TID_BASE    0
39536 #define M_CLCAM_TID_BASE    0xfffffU
39540 #define A_LE_DB_TID_HASHBASE 0x19df8
39543 #define M_HASHBASE_ADDR    0xfffffU
39547 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
39549 #define S_HASH_TID_BASE    0
39550 #define M_HASH_TID_BASE    0xfffffU
39554 #define A_LE_PERR_INJECT 0x19dfc
39557 #define M_LEMEMSEL    0x7U
39561 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
39563 #define S_SSRAM_TID_BASE    0
39564 #define M_SSRAM_TID_BASE    0xfffffU
39568 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
39569 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
39570 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
39571 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
39572 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
39573 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
39574 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
39575 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
39576 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
39577 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
39578 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
39579 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
39580 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
39581 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
39582 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
39583 #define A_LE_DEBUG_LA_CONFIG 0x19f20
39584 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
39585 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
39586 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
39587 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
39588 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
39589 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
39590 #define A_LE_SRVR_SRAM_INIT 0x19f34
39593 #define M_SRVRSRAMBASE    0xfffffU
39601 #define S_SRVRINIT    0
39605 #define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
39619 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
39620 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
39627 #define M_VFINDEX    0x7fU
39632 #define M_SRCHHADDR    0x7fU
39636 #define S_SRCHLADDR    0
39637 #define M_SRCHLADDR    0x7fU
39641 #define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
39655 #define S_T6_VFINDEX    0
39656 #define M_T6_VFINDEX    0xffU
39660 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
39661 #define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
39664 #define M_T6_SRCHHADDR    0xfffU
39668 #define S_T6_SRCHLADDR    0
39669 #define M_T6_SRCHLADDR    0xfffU
39673 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
39674 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
39675 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
39676 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
39677 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
39678 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
39679 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
39680 #define A_LE_HASH_COLLISION 0x19fc4
39681 #define A_LE_GLOBAL_COLLISION 0x19fc8
39682 #define A_LE_FULL_CNT_COLLISION 0x19fcc
39683 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
39684 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
39685 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
39686 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
39687 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
39688 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
39691 #define NCSI_BASE_ADDR 0x1a000
39693 #define A_NCSI_PORT_CFGREG 0x1a000
39696 #define M_WIREEN    0xfU
39701 #define M_STRP_CRC    0xfU
39726 #define M_MAX_PKT_SIZE    0x3fffU
39738 #define A_NCSI_RST_CTRL 0x1a004
39748 #define S_MAC_TX_RST    0
39752 #define A_NCSI_CH0_SADDR_LOW 0x1a010
39753 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
39759 #define S_CH0_SADDR_HIGH    0
39760 #define M_CH0_SADDR_HIGH    0xffffU
39764 #define A_NCSI_CH1_SADDR_LOW 0x1a018
39765 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
39771 #define S_CH1_SADDR_HIGH    0
39772 #define M_CH1_SADDR_HIGH    0xffffU
39776 #define A_NCSI_CH2_SADDR_LOW 0x1a020
39777 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
39783 #define S_CH2_SADDR_HIGH    0
39784 #define M_CH2_SADDR_HIGH    0xffffU
39788 #define A_NCSI_CH3_SADDR_LOW 0x1a028
39789 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
39795 #define S_CH3_SADDR_HIGH    0
39796 #define M_CH3_SADDR_HIGH    0xffffU
39800 #define A_NCSI_WORK_REQHDR_0 0x1a030
39801 #define A_NCSI_WORK_REQHDR_1 0x1a034
39802 #define A_NCSI_WORK_REQHDR_2 0x1a038
39803 #define A_NCSI_WORK_REQHDR_3 0x1a03c
39804 #define A_NCSI_MPS_HDR_LO 0x1a040
39805 #define A_NCSI_MPS_HDR_HI 0x1a044
39806 #define A_NCSI_CTL 0x1a048
39820 #define S_FWD_BMC    0
39824 #define A_NCSI_NCSI_ETYPE 0x1a04c
39826 #define S_NCSI_ETHERTYPE    0
39827 #define M_NCSI_ETHERTYPE    0xffffU
39831 #define A_NCSI_RX_FIFO_CNT 0x1a050
39833 #define S_NCSI_RXFIFO_CNT    0
39834 #define M_NCSI_RXFIFO_CNT    0x7ffU
39838 #define A_NCSI_RX_ERR_CNT 0x1a054
39839 #define A_NCSI_RX_OF_CNT 0x1a058
39840 #define A_NCSI_RX_MS_CNT 0x1a05c
39841 #define A_NCSI_RX_IE_CNT 0x1a060
39842 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
39845 #define M_MPS2CIM_CNT    0x1ffU
39849 #define S_MPS2BMC_CNT    0
39850 #define M_MPS2BMC_CNT    0x1ffU
39854 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
39857 #define M_CIM2MPS_CNT    0x1ffU
39861 #define S_CIM2BMC_CNT    0
39862 #define M_CIM2BMC_CNT    0x1ffU
39866 #define A_NCSI_TX_FIFO_CNT 0x1a06c
39868 #define S_TX_FIFO_CNT    0
39869 #define M_TX_FIFO_CNT    0x3ffU
39873 #define A_NCSI_SE_CNT_CTL 0x1a0b0
39875 #define S_SE_CNT_CLR    0
39876 #define M_SE_CNT_CLR    0xfU
39880 #define A_NCSI_SE_CNT_MPS 0x1a0b4
39883 #define M_NC2MPS_SOP_CNT    0xffU
39888 #define M_NC2MPS_EOP_CNT    0x3fU
39893 #define M_MPS2NC_SOP_CNT    0xffU
39897 #define S_MPS2NC_EOP_CNT    0
39898 #define M_MPS2NC_EOP_CNT    0xffU
39902 #define A_NCSI_SE_CNT_CIM 0x1a0b8
39905 #define M_NC2CIM_SOP_CNT    0xffU
39910 #define M_NC2CIM_EOP_CNT    0x3fU
39915 #define M_CIM2NC_SOP_CNT    0xffU
39919 #define S_CIM2NC_EOP_CNT    0
39920 #define M_CIM2NC_EOP_CNT    0xffU
39924 #define A_NCSI_BUS_DEBUG 0x1a0bc
39927 #define M_SOP_CNT_ERR    0xfU
39932 #define M_BUS_STATE_MPS_OUT    0x3U
39937 #define M_BUS_STATE_MPS_IN    0x3U
39942 #define M_BUS_STATE_CIM_OUT    0x3U
39946 #define S_BUS_STATE_CIM_IN    0
39947 #define M_BUS_STATE_CIM_IN    0x3U
39951 #define A_NCSI_LA_RDPTR 0x1a0c0
39952 #define A_NCSI_LA_RDDATA 0x1a0c4
39953 #define A_NCSI_LA_WRPTR 0x1a0c8
39954 #define A_NCSI_LA_RESERVED 0x1a0cc
39955 #define A_NCSI_LA_CTL 0x1a0d0
39956 #define A_NCSI_INT_ENABLE 0x1a0d4
39990 #define S_RXFIFO_PRTY_ERR    0
39994 #define A_NCSI_INT_CAUSE 0x1a0d8
39995 #define A_NCSI_STATUS 0x1a0dc
40001 #define S_ARB_STATUS    0
40005 #define A_NCSI_PAUSE_CTRL 0x1a0e0
40007 #define S_FORCEPAUSE    0
40011 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
40012 #define A_NCSI_PAUSE_WM 0x1a0ec
40015 #define M_PAUSEHWM    0x7ffU
40019 #define S_PAUSELWM    0
40020 #define M_PAUSELWM    0x7ffU
40024 #define A_NCSI_DEBUG 0x1a0f0
40026 #define S_DEBUGSEL    0
40027 #define M_DEBUGSEL    0x3fU
40039 #define S_PKG_ID    0
40040 #define M_PKG_ID    0x7U
40044 #define A_NCSI_PERR_INJECT 0x1a0f4
40050 #define A_NCSI_PERR_ENABLE 0x1a0f8
40051 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
40101 #define S_LOOPPHY    0
40105 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
40136 #define M_RXBUFOFFSET    0x3U
40149 #define M_PCLKDIV    0x3U
40189 #define S_SPEED    0
40193 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
40203 #define S_LINKSTATUS    0
40207 #define A_NCSI_MACB_TX_STATUS 0x1a114
40233 #define S_USEDBITREAD    0
40237 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
40240 #define M_RXBUFQPTR    0x3fffffffU
40244 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
40247 #define M_TXBUFQPTR    0x3fffffffU
40251 #define A_NCSI_MACB_RX_STATUS 0x1a120
40261 #define S_NORXBUF    0
40265 #define A_NCSI_MACB_INT_STATUS 0x1a124
40315 #define S_MGMTFRAMESENT    0
40319 #define A_NCSI_MACB_INT_EN 0x1a128
40320 #define A_NCSI_MACB_INT_DIS 0x1a12c
40321 #define A_NCSI_MACB_INT_MASK 0x1a130
40322 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
40324 #define S_PAUSETIME    0
40325 #define M_PAUSETIME    0xffffU
40329 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
40331 #define S_PAUSEFRRCVD    0
40332 #define M_PAUSEFRRCVD    0xffffU
40336 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
40338 #define S_TXFRAMESOK    0
40339 #define M_TXFRAMESOK    0xffffffU
40343 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
40345 #define S_SINGLECOLTXFRAMES    0
40346 #define M_SINGLECOLTXFRAMES    0xffffU
40350 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
40352 #define S_MULCOLTXFRAMES    0
40353 #define M_MULCOLTXFRAMES    0xffffU
40357 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
40359 #define S_RXFRAMESOK    0
40360 #define M_RXFRAMESOK    0xffffffU
40364 #define A_NCSI_MACB_FCS_ERR 0x1a150
40366 #define S_RXFCSERR    0
40367 #define M_RXFCSERR    0xffU
40371 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
40373 #define S_RXALIGNERR    0
40374 #define M_RXALIGNERR    0xffU
40378 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
40380 #define S_TXDEFERREDFRAMES    0
40381 #define M_TXDEFERREDFRAMES    0xffffU
40385 #define A_NCSI_MACB_LATE_COL 0x1a15c
40387 #define S_LATECOLLISIONS    0
40388 #define M_LATECOLLISIONS    0xffffU
40392 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
40394 #define S_EXCESSIVECOLLISIONS    0
40395 #define M_EXCESSIVECOLLISIONS    0xffU
40399 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
40401 #define S_TXUNDERRUNERR    0
40402 #define M_TXUNDERRUNERR    0xffU
40406 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
40408 #define S_CARRIERSENSEERRS    0
40409 #define M_CARRIERSENSEERRS    0xffU
40413 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
40415 #define S_RXRESOURCEERR    0
40416 #define M_RXRESOURCEERR    0xffffU
40420 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
40422 #define S_RXOVERRUNERRCNT    0
40423 #define M_RXOVERRUNERRCNT    0xffU
40427 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
40429 #define S_RXSYMBOLERR    0
40430 #define M_RXSYMBOLERR    0xffU
40434 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
40436 #define S_RXOVERSIZEERR    0
40437 #define M_RXOVERSIZEERR    0xffU
40441 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
40443 #define S_RXJABBERERR    0
40444 #define M_RXJABBERERR    0xffU
40448 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
40450 #define S_RXUNDERSIZEFR    0
40451 #define M_RXUNDERSIZEFR    0xffU
40455 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
40457 #define S_SQETESTERR    0
40458 #define M_SQETESTERR    0xffU
40462 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
40464 #define S_LENGTHERR    0
40465 #define M_LENGTHERR    0xffU
40469 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
40471 #define S_TXPAUSEFRAMES    0
40472 #define M_TXPAUSEFRAMES    0xffffU
40476 #define A_NCSI_MACB_HASH_LOW 0x1a190
40477 #define A_NCSI_MACB_HASH_HIGH 0x1a194
40478 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
40479 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
40481 #define S_MATCHHIGH    0
40482 #define M_MATCHHIGH    0xffffU
40486 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
40487 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
40488 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
40489 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
40490 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
40491 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
40492 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
40494 #define S_TYPEID    0
40495 #define M_TYPEID    0xffffU
40499 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
40501 #define S_TXPAUSEQUANTUM    0
40502 #define M_TXPAUSEQUANTUM    0xffffU
40506 #define A_NCSI_MACB_USER_IO 0x1a1c0
40509 #define M_USERPROGINPUT    0xffffU
40513 #define S_USERPROGOUTPUT    0
40514 #define M_USERPROGOUTPUT    0xffffU
40518 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
40536 #define S_ARPIPADDR    0
40537 #define M_ARPIPADDR    0xffffU
40541 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
40544 #define M_PARTREF    0xffffU
40548 #define S_DESREV    0
40549 #define M_DESREV    0xffffU
40554 #define XGMAC_BASE_ADDR 0x0
40556 #define A_XGMAC_PORT_CFG 0x1000
40559 #define M_XGMII_CLK_SEL    0x7U
40620 #define M_XGM_RX_SEL    0x3U
40625 #define M_PCS_TX_SEL    0x3U
40637 #define S_PORT_SEL    0
40641 #define A_XGMAC_PORT_RESET_CTRL 0x1004
40683 #define S_HSS_RESET    0
40687 #define A_XGMAC_PORT_LED_CFG 0x1008
40690 #define M_LED1_CFG    0x7U
40699 #define M_LED0_CFG    0x7U
40703 #define S_LED0_POLARITY_INV    0
40707 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
40709 #define S_LED_COUNT_HI    0
40710 #define M_LED_COUNT_HI    0x1ffffffU
40714 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
40716 #define S_LED_COUNT_LO    0
40717 #define M_LED_COUNT_LO    0x1ffffffU
40721 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
40723 #define S_TESTCLK_SEL    0
40724 #define M_TESTCLK_SEL    0xfU
40728 #define A_XGMAC_PORT_CFG2 0x1018
40731 #define M_RX_POLARITY_INV    0xfU
40736 #define M_TX_POLARITY_INV    0xfU
40741 #define M_INSTANCENUM    0x3U
40766 #define M_TX_IPG    0x1fffU
40774 #define S_AEC_PMA_RX_READY    0
40778 #define A_XGMAC_PORT_PKT_COUNT 0x101c
40781 #define M_TX_SOP_COUNT    0xffU
40786 #define M_TX_EOP_COUNT    0xffU
40791 #define M_RX_SOP_COUNT    0xffU
40795 #define S_RX_EOP_COUNT    0
40796 #define M_RX_EOP_COUNT    0xffU
40800 #define A_XGMAC_PORT_PERR_INJECT 0x1020
40806 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
40807 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
40809 #define S_MAC_WOL_DA    0
40810 #define M_MAC_WOL_DA    0xffffU
40814 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
40815 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
40818 #define M_TXSOP    0xffU
40823 #define M_TXEOP    0xffU
40828 #define M_RXSOP    0xffU
40832 #define S_T4_RXEOP    0
40833 #define M_T4_RXEOP    0xffU
40837 #define A_XGMAC_PORT_LINK_STATUS 0x1034
40851 #define S_LINKDN    0
40855 #define A_XGMAC_PORT_CHECKIN 0x1038
40861 #define S_CHECKIN    0
40865 #define A_XGMAC_PORT_FAULT_TEST 0x103c
40871 #define S_FLTCTRL    0
40875 #define A_XGMAC_PORT_SPARE 0x1040
40876 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
40878 #define S_SIGNALDETECT    0
40879 #define M_SIGNALDETECT    0xfU
40883 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
40884 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
40886 #define S_CTRL    0
40887 #define M_CTRL    0xfU
40891 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
40898 #define M_HWM    0x1fffU
40902 #define S_LWM    0
40903 #define M_LWM    0x1fffU
40907 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
40908 #define A_XGMAC_PORT_LA_TX_0 0x1058
40909 #define A_XGMAC_PORT_LA_RX_0 0x105c
40910 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
40932 #define S_LASTOP    0
40936 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
40937 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
40938 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
40939 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
40940 #define A_XGMAC_PORT_EPIO_OP 0x10d0
40946 #define S_ADDRESS    0
40947 #define M_ADDRESS    0xffU
40951 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
40969 #define S_MATCHEDFILTER    0
40970 #define M_MATCHEDFILTER    0x7U
40974 #define A_XGMAC_PORT_INT_EN 0x10d8
41084 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
41085 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
41152 #define M_HSSDIVSEL    0x3U
41177 #define M_HSSRSTCONFIG    0x7U
41181 #define S_HSSPRBSEN    0
41185 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
41263 #define S_TXAPRBSEN    0
41267 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
41361 #define S_RXAPHSUPIN    0
41365 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
41419 #define S_HSSPRTREADY    0
41423 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
41433 #define S_XGM_TXEN    0
41437 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
41440 #define M_CRCCAL    0x3U
41457 #define M_CFGCLKSPEED    0x7U
41465 #define S_TXPAUSEEN    0
41469 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
41471 #define S_TXPAUSEQUANTA    0
41472 #define M_TXPAUSEQUANTA    0xffffU
41476 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
41477 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
41480 #define M_RXCRCCAL    0x3U
41544 #define S_COPYALLFRAMES    0
41548 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
41549 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
41550 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
41551 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
41553 #define S_ADDRESS_HIGH    0
41554 #define M_ADDRESS_HIGH    0xffffU
41558 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
41559 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
41560 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
41561 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
41562 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
41563 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
41564 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
41565 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
41566 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
41567 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
41568 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
41569 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
41570 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
41571 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
41572 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
41578 #define S_TYPE    0
41579 #define M_TYPE    0xffffU
41583 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
41584 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
41585 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
41586 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
41628 #define S_FRAMERCVD    0
41632 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
41633 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
41634 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
41635 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
41637 #define S_CURPAUSETIMER    0
41638 #define M_CURPAUSETIMER    0xffffU
41642 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
41660 #define S_ENTESTMODEWR    0
41664 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
41667 #define M_FRAMETYPE    0x3U
41672 #define M_OPERATION    0x3U
41677 #define M_PORTADDR    0x1fU
41682 #define M_DEVADDR    0x1fU
41687 #define M_RESRV    0x3U
41691 #define S_DATA    0
41692 #define M_DATA    0xffffU
41696 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
41699 #define M_MODULEID    0xffffU
41703 #define S_MODULEREV    0
41704 #define M_MODULEREV    0xffffU
41708 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
41709 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
41711 #define S_TXBYTES_HIGH    0
41712 #define M_TXBYTES_HIGH    0x1fffU
41716 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
41717 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
41719 #define S_TXFRAMES_HIGH    0
41720 #define M_TXFRAMES_HIGH    0xfU
41724 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
41725 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
41726 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
41727 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
41728 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
41729 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
41730 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
41731 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
41732 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
41733 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
41734 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
41735 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
41736 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
41738 #define S_RXBYTES_HIGH    0
41739 #define M_RXBYTES_HIGH    0x1fffU
41743 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
41744 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
41746 #define S_RXFRAMES_HIGH    0
41747 #define M_RXFRAMES_HIGH    0xfU
41751 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
41752 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
41753 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
41755 #define S_RXPAUSEFRAMES    0
41756 #define M_RXPAUSEFRAMES    0xffffU
41760 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
41761 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
41762 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
41763 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
41764 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
41765 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
41766 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
41767 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
41769 #define S_RXSHORTFRAMES    0
41770 #define M_RXSHORTFRAMES    0xffffU
41774 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
41776 #define S_RXOVERSIZEFRAMES    0
41777 #define M_RXOVERSIZEFRAMES    0xffffU
41781 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
41783 #define S_RXJABBERFRAMES    0
41784 #define M_RXJABBERFRAMES    0xffffU
41788 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
41790 #define S_RXCRCERRFRAMES    0
41791 #define M_RXCRCERRFRAMES    0xffffU
41795 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
41797 #define S_RXLENGTHERRFRAMES    0
41798 #define M_RXLENGTHERRFRAMES    0xffffU
41802 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
41804 #define S_RXSYMCODEERRFRAMES    0
41805 #define M_RXSYMCODEERRFRAMES    0xffffU
41809 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
41812 #define M_POLARITY_INV_RX    0xfU
41817 #define M_POLARITY_INV_TX    0xfU
41822 #define M_TEST_SEL    0x3U
41826 #define S_TEST_EN    0
41830 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
41833 #define M_DECODE_ERROR    0xffU
41869 #define S_LANE0_SYNC_STATUS    0
41873 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
41892 #define M_TESTSEL    0x3U
41900 #define S_XGMIILOOPEN    0
41904 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
41922 #define S_TX_TST_EN    0
41926 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
41927 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
41929 #define S_SEEDA_UPPER    0
41930 #define M_SEEDA_UPPER    0x3ffffffU
41934 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
41935 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
41937 #define S_SEEDB_UPPER    0
41938 #define M_SEEDB_UPPER    0x3ffffffU
41942 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
41972 #define S_RX_TST_EN    0
41976 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
41979 #define M_ERR_BLK_CNT    0xffU
41984 #define M_BER_COUNT    0x3fU
41996 #define S_TX_FAULT    0
42000 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
42002 #define S_TPT_ERR_CNT    0
42003 #define M_TPT_ERR_CNT    0xffffU
42007 #define A_XGMAC_PORT_AN_CONTROL 0x1600
42021 #define A_XGMAC_PORT_AN_STATUS 0x1604
42051 #define S_PARTNER_AN_ABILITY    0
42055 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
42078 #define M_TRANSMITTED_NONCE    0x1fU
42103 #define M_ECHOED_NONCE    0x1fU
42107 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
42109 #define S_SELECTOR_FIELD    0
42110 #define M_SELECTOR_FIELD    0x1fU
42114 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
42117 #define M_NP_INFO    0xffffU
42137 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
42139 #define S_NP_INFO_HI    0
42140 #define M_NP_INFO_HI    0xffffU
42144 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
42145 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
42146 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
42172 #define S_BP_AN_ABILITY    0
42176 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
42182 #define S_LFSR_INIT    0
42183 #define M_LFSR_INIT    0x7fffU
42187 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
42201 #define S_PCS_AN_COMPLETE    0
42205 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
42207 #define S_GENERIC_TIMEOUT    0
42208 #define M_GENERIC_TIMEOUT    0x7fffffU
42212 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
42214 #define S_BREAK_LINK_TIMEOUT    0
42215 #define M_BREAK_LINK_TIMEOUT    0xffffffU
42219 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
42222 #define M_MODULE_ID    0xffffU
42226 #define S_MODULE_REVISION    0
42227 #define M_MODULE_REVISION    0xffffU
42231 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
42242 #define M_RXREQ_C0    0x3U
42247 #define M_RXREQ_C1    0x3U
42251 #define S_RXREQ_C2    0
42252 #define M_RXREQ_C2    0x3U
42256 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
42263 #define M_RXSTAT_C0    0x3U
42268 #define M_RXSTAT_C1    0x3U
42272 #define S_RXSTAT_C2    0
42273 #define M_RXSTAT_C2    0x3U
42277 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
42288 #define M_TXREQ_C0    0x3U
42293 #define M_TXREQ_C1    0x3U
42297 #define S_TXREQ_C2    0
42298 #define M_TXREQ_C2    0x3U
42302 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
42309 #define M_TXSTAT_C0    0x3U
42314 #define M_TXSTAT_C1    0x3U
42318 #define S_TXSTAT_C2    0
42319 #define M_TXSTAT_C2    0x3U
42323 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
42326 #define M_MAN_DEC    0x3U
42342 #define S_STICKY_MODE    0
42346 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
42349 #define M_PRBS_CHK_ERRCNT    0xffU
42354 #define M_PRBS_SYNCCNT    0x7U
42374 #define S_PRBS_GEN_OFF    0
42378 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
42385 #define M_FSM_GDMRK    0x7U
42390 #define M_FSM_BADMRK    0x7U
42422 #define S_FSM_TR_EN    0
42426 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
42429 #define M_CC2FSM_STATE    0x7U
42434 #define M_CC1FSM_STATE    0x7U
42439 #define M_CC0FSM_STATE    0x7U
42444 #define M_FLFSM_STATE    0x7U
42448 #define S_TFSM_STATE    0
42449 #define M_TFSM_STATE    0x7U
42453 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
42455 #define S_PMD_TX_DIS    0
42459 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
42465 #define S_RESTART_TRAINING    0
42469 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
42471 #define S_PMD_SIGDET    0
42475 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
42489 #define S_RX_TRAINED    0
42493 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
42496 #define M_BWSEL    0x3U
42500 #define S_RTSEL    0
42501 #define M_RTSEL    0x3U
42505 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
42519 #define S_TPSEL    0
42520 #define M_TPSEL    0x7U
42524 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
42550 #define S_ALOAD    0
42554 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
42561 #define M_SLEW    0x7U
42565 #define S_FFE    0
42566 #define M_FFE    0x3U
42570 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
42596 #define S_IDAC    0
42597 #define M_IDAC    0x3U
42601 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
42603 #define S_STBY    0
42604 #define M_STBY    0xffffU
42608 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
42610 #define S_PON    0
42611 #define M_PON    0xffffU
42615 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
42617 #define S_NXTT0    0
42618 #define M_NXTT0    0xfU
42622 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
42624 #define S_NXTT1    0
42625 #define M_NXTT1    0x3fU
42629 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
42631 #define S_NXTT2    0
42632 #define M_NXTT2    0x1fU
42636 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
42638 #define S_TXPWR    0
42639 #define M_TXPWR    0x7fU
42643 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
42646 #define M_TXPOL    0x7U
42650 #define S_NTXPOL    0
42651 #define M_NTXPOL    0x7U
42655 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
42666 #define M_C2UPDT    0x3U
42671 #define M_C1UPDT    0x3U
42675 #define S_C0UPDT    0
42676 #define M_C0UPDT    0x3U
42680 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
42683 #define M_C2STAT    0x3U
42688 #define M_C1STAT    0x3U
42692 #define S_C0STAT    0
42693 #define M_C0STAT    0x3U
42697 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
42699 #define S_NIDAC0    0
42700 #define M_NIDAC0    0x1fU
42704 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
42706 #define S_NIDAC1    0
42707 #define M_NIDAC1    0x7fU
42711 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
42713 #define S_NIDAC2    0
42714 #define M_NIDAC2    0x3fU
42718 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
42724 #define S_OPVAL    0
42725 #define M_OPVAL    0x1fU
42729 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
42731 #define S_PDAC    0
42732 #define M_PDAC    0x1fU
42736 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
42738 #define S_AIDAC0    0
42739 #define M_AIDAC0    0x1fU
42743 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
42745 #define S_AIDAC1    0
42746 #define M_AIDAC1    0x1fU
42750 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
42752 #define S_TXA_AIDAC2    0
42753 #define M_TXA_AIDAC2    0x1fU
42757 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
42759 #define S_CURSD    0
42760 #define M_CURSD    0x7fU
42764 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
42766 #define S_XDATA    0
42767 #define M_XDATA    0xffffU
42771 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
42774 #define M_EXTADDR    0x1fU
42778 #define S_XWR    0
42782 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
42783 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
42784 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
42785 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
42786 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
42787 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
42788 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
42789 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
42790 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
42791 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
42792 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
42793 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
42794 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
42795 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
42796 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
42797 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
42798 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
42799 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
42800 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
42801 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
42802 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
42803 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
42805 #define S_AIDAC2    0
42806 #define M_AIDAC2    0x3fU
42810 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
42811 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
42812 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
42815 #define M_XADDR    0xfU
42819 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
42830 #define M_DMSEL    0x7U
42834 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
42841 #define M_RRATE    0x3U
42873 #define S_PRBSSEL    0
42874 #define M_PRBSSEL    0x7U
42878 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
42881 #define M_FTHROT    0xfU
42890 #define M_FILTCTL    0xfU
42895 #define M_RSRVO    0x3U
42915 #define S_SSCENABLE    0
42919 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
42934 #define M_TMSCAL    0x3U
42946 #define S_PHOFFS    0
42947 #define M_PHOFFS    0x1fU
42951 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
42954 #define M_ROT0A    0x3fU
42958 #define S_RTSEL_SNAPSHOT    0
42959 #define M_RTSEL_SNAPSHOT    0x3fU
42963 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
42965 #define S_ROT90    0
42966 #define M_ROT90    0x3fU
42970 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
42977 #define M_RAOOFF    0x1fU
42982 #define M_RAEOFF    0x1fU
42986 #define S_RDOFF    0
42987 #define M_RDOFF    0x1fU
42991 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
42994 #define M_SIGNSD    0x3U
42999 #define M_DACSD    0x1fU
43011 #define S_SDLVL    0
43012 #define M_SDLVL    0x1fU
43016 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
43035 #define M_SPIFMT    0x7U
43040 #define M_DFEPWR    0x7U
43064 #define S_DFERST    0
43068 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
43071 #define M_ESAMP    0xffU
43075 #define S_DSAMP    0
43076 #define M_DSAMP    0xffU
43080 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
43083 #define M_SMODE    0xfU
43096 #define M_ASAMPQ    0x7U
43100 #define S_ASAMP    0
43101 #define M_ASAMP    0x7U
43105 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
43108 #define M_POLE    0x3U
43113 #define M_PEAK    0x7U
43118 #define M_VOFFSN    0x3U
43122 #define S_VOFFA    0
43123 #define M_VOFFA    0x3fU
43127 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
43133 #define S_VGAIN    0
43134 #define M_VGAIN    0xfU
43138 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
43156 #define S_AMAXT    0
43157 #define M_AMAXT    0x7fU
43161 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
43164 #define M_D01SN    0x3U
43169 #define M_D01AMP    0x1fU
43174 #define M_D00SN    0x3U
43178 #define S_D00AMP    0
43179 #define M_D00AMP    0x1fU
43183 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
43186 #define M_D11SN    0x3U
43191 #define M_D11AMP    0x1fU
43196 #define M_D10SN    0x3U
43200 #define S_D10AMP    0
43201 #define M_D10AMP    0x1fU
43205 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
43208 #define M_E1SN    0x3U
43213 #define M_E1AMP    0x1fU
43218 #define M_E0SN    0x3U
43222 #define S_E0AMP    0
43223 #define M_E0AMP    0x1fU
43227 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
43230 #define M_AOFFO    0x3fU
43234 #define S_AOFFE    0
43235 #define M_AOFFE    0x3fU
43239 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
43242 #define M_DACAN    0xffU
43246 #define S_DACAP    0
43247 #define M_DACAP    0xffU
43251 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
43254 #define M_DACAZ    0xffU
43258 #define S_DACAM    0
43259 #define M_DACAM    0xffU
43263 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
43266 #define M_ADSN    0x3U
43270 #define S_ADMAG    0
43271 #define M_ADMAG    0x7fU
43275 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
43282 #define M_WIDTH    0x1fU
43287 #define M_MINWIDTH    0x1fU
43291 #define S_MINAMP    0
43292 #define M_MINAMP    0x1fU
43296 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
43307 #define M_EMMD    0x3U
43315 #define S_EMEN    0
43319 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
43322 #define M_H1OSN    0x3U
43327 #define M_H1OMAG    0x3fU
43332 #define M_H1ESN    0x3U
43336 #define S_H1EMAG    0
43337 #define M_H1EMAG    0x3fU
43341 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
43344 #define M_H2OSN    0x3U
43349 #define M_H2OMAG    0x1fU
43354 #define M_H2ESN    0x3U
43358 #define S_H2EMAG    0
43359 #define M_H2EMAG    0x1fU
43363 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
43366 #define M_H3OSN    0x3U
43371 #define M_H3OMAG    0xfU
43376 #define M_H3ESN    0x3U
43380 #define S_H3EMAG    0
43381 #define M_H3EMAG    0xfU
43385 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
43388 #define M_H4OSN    0x3U
43393 #define M_H4OMAG    0xfU
43398 #define M_H4ESN    0x3U
43402 #define S_H4EMAG    0
43403 #define M_H4EMAG    0xfU
43407 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
43410 #define M_H5OSN    0x3U
43415 #define M_H5OMAG    0xfU
43420 #define M_H5ESN    0x3U
43424 #define S_H5EMAG    0
43425 #define M_H5EMAG    0xfU
43429 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
43440 #define M_DPCTGT    0x7U
43453 #define M_H1TGT    0x7U
43457 #define S_OAE    0
43458 #define M_OAE    0xfU
43462 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
43465 #define M_OLS    0x1fU
43470 #define M_OES    0x1fU
43478 #define S_ODEC    0
43479 #define M_ODEC    0x1fU
43483 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
43533 #define S_OCCMP    0
43537 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
43595 #define S_FADAC    0
43599 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
43600 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
43601 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
43602 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
43603 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
43604 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
43605 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
43606 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
43607 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
43608 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
43609 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
43610 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
43611 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
43612 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
43613 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
43614 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
43615 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
43616 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
43617 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
43618 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
43619 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
43620 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
43621 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
43622 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
43623 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
43624 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
43625 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
43626 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
43627 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
43628 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
43629 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
43630 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
43631 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
43632 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
43633 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
43634 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
43635 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
43636 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
43637 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
43638 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
43639 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
43640 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
43641 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
43642 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
43643 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
43644 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
43645 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
43646 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
43647 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
43648 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
43649 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
43650 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
43651 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
43652 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
43653 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
43654 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
43655 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
43656 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
43657 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
43658 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
43659 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
43660 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
43661 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
43662 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
43663 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
43664 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
43665 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
43666 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
43667 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
43668 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
43669 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
43670 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
43671 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
43672 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
43673 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
43674 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
43675 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
43676 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
43677 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
43678 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
43679 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
43680 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
43681 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
43682 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
43683 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
43684 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
43685 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
43686 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
43687 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
43688 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
43689 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
43690 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
43691 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
43692 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
43693 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
43694 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
43695 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
43696 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
43697 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
43698 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
43699 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
43700 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
43701 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
43702 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
43703 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
43704 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
43705 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
43706 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
43707 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
43708 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
43709 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
43710 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
43711 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
43712 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
43713 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
43714 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
43715 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
43716 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
43717 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
43718 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
43719 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
43720 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
43721 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
43722 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
43723 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
43724 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
43725 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
43726 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
43727 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
43728 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
43729 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
43730 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
43731 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
43732 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
43733 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
43734 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
43735 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
43736 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
43737 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
43738 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
43739 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
43740 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
43741 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
43742 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
43743 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
43744 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
43745 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
43747 #define S_BSELO    0
43748 #define M_BSELO    0xfU
43752 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
43766 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
43768 #define S_BSELI    0
43769 #define M_BSELI    0xfU
43773 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
43791 #define S_TCDIS    0
43795 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
43805 #define S_CCLD    0
43809 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
43811 #define S_ATST    0
43812 #define M_ATST    0x1fU
43816 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
43846 #define S_TXAEN    0
43850 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
43880 #define S_TXARST    0
43884 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
43890 #define S_CPISEL    0
43891 #define M_CPISEL    0x3U
43895 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
43897 #define S_BGCTL    0
43898 #define M_BGCTL    0x1fU
43902 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
43916 #define S_LFSEL    0
43920 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
43930 #define S_VBADJ    0
43934 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
43935 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
43936 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
43937 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
43938 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
43939 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
43940 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
43941 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
43942 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
43943 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
43944 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
43945 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
43946 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
43947 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
43948 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
43949 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
43950 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
43951 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
43952 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
43953 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
43954 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
43955 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
43956 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
43957 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
43958 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
43959 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
43960 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
43961 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
43962 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
43963 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
43964 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
43965 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
43966 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
43967 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
43968 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
43969 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
43970 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
43971 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
43972 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
43973 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
43974 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
43975 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
43976 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
43977 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
43978 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
43979 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
43980 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
43981 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
43982 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
43983 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
43984 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
43985 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
43986 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
43987 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
43988 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
43989 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
43990 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
43991 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
43992 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
43995 #define UP_BASE_ADDR 0x0
43997 #define A_UP_IBQ_CONFIG 0x0
44000 #define M_IBQGEN2    0x3fffffffU
44008 #define S_IBQEN    0
44012 #define A_UP_OBQ_CONFIG 0x4
44015 #define M_OBQGEN2    0x3fffffffU
44023 #define S_OBQEN    0
44027 #define A_UP_IBQ_GEN 0x8
44030 #define M_IBQGEN0    0x3ffU
44035 #define M_IBQTSCHCHNLRDY    0xfU
44048 #define M_IBQGEN1    0x3ffU
44052 #define S_IBQEMPTY    0
44053 #define M_IBQEMPTY    0x3fU
44057 #define A_UP_OBQ_GEN 0xc
44060 #define M_OBQGEN    0x3ffffffU
44064 #define S_OBQFULL    0
44065 #define M_OBQFULL    0x3fU
44070 #define M_T5_OBQGEN    0xffffffU
44074 #define S_T5_OBQFULL    0
44075 #define M_T5_OBQFULL    0xffU
44079 #define A_UP_IBQ_0_RDADDR 0x10
44082 #define M_QUEID    0x7ffffU
44086 #define S_IBQRDADDR    0
44087 #define M_IBQRDADDR    0x1fffU
44091 #define A_UP_IBQ_0_WRADDR 0x14
44093 #define S_IBQWRADDR    0
44094 #define M_IBQWRADDR    0x1fffU
44098 #define A_UP_IBQ_0_STATUS 0x18
44104 #define S_QUEREMFLITS    0
44105 #define M_QUEREMFLITS    0x7ffU
44109 #define A_UP_IBQ_0_PKTCNT 0x1c
44112 #define M_QUEEOPCNT    0xfffU
44116 #define S_QUESOPCNT    0
44117 #define M_QUESOPCNT    0xfffU
44121 #define A_UP_IBQ_1_RDADDR 0x20
44122 #define A_UP_IBQ_1_WRADDR 0x24
44123 #define A_UP_IBQ_1_STATUS 0x28
44124 #define A_UP_IBQ_1_PKTCNT 0x2c
44125 #define A_UP_IBQ_2_RDADDR 0x30
44126 #define A_UP_IBQ_2_WRADDR 0x34
44127 #define A_UP_IBQ_2_STATUS 0x38
44128 #define A_UP_IBQ_2_PKTCNT 0x3c
44129 #define A_UP_IBQ_3_RDADDR 0x40
44130 #define A_UP_IBQ_3_WRADDR 0x44
44131 #define A_UP_IBQ_3_STATUS 0x48
44132 #define A_UP_IBQ_3_PKTCNT 0x4c
44133 #define A_UP_IBQ_4_RDADDR 0x50
44134 #define A_UP_IBQ_4_WRADDR 0x54
44135 #define A_UP_IBQ_4_STATUS 0x58
44136 #define A_UP_IBQ_4_PKTCNT 0x5c
44137 #define A_UP_IBQ_5_RDADDR 0x60
44138 #define A_UP_IBQ_5_WRADDR 0x64
44139 #define A_UP_IBQ_5_STATUS 0x68
44140 #define A_UP_IBQ_5_PKTCNT 0x6c
44141 #define A_UP_OBQ_0_RDADDR 0x70
44144 #define M_OBQID    0x1ffffU
44148 #define S_QUERDADDR    0
44149 #define M_QUERDADDR    0x7fffU
44153 #define A_UP_OBQ_0_WRADDR 0x74
44155 #define S_QUEWRADDR    0
44156 #define M_QUEWRADDR    0x7fffU
44160 #define A_UP_OBQ_0_STATUS 0x78
44161 #define A_UP_OBQ_0_PKTCNT 0x7c
44162 #define A_UP_OBQ_1_RDADDR 0x80
44163 #define A_UP_OBQ_1_WRADDR 0x84
44164 #define A_UP_OBQ_1_STATUS 0x88
44165 #define A_UP_OBQ_1_PKTCNT 0x8c
44166 #define A_UP_OBQ_2_RDADDR 0x90
44167 #define A_UP_OBQ_2_WRADDR 0x94
44168 #define A_UP_OBQ_2_STATUS 0x98
44169 #define A_UP_OBQ_2_PKTCNT 0x9c
44170 #define A_UP_OBQ_3_RDADDR 0xa0
44171 #define A_UP_OBQ_3_WRADDR 0xa4
44172 #define A_UP_OBQ_3_STATUS 0xa8
44173 #define A_UP_OBQ_3_PKTCNT 0xac
44174 #define A_UP_OBQ_4_RDADDR 0xb0
44175 #define A_UP_OBQ_4_WRADDR 0xb4
44176 #define A_UP_OBQ_4_STATUS 0xb8
44177 #define A_UP_OBQ_4_PKTCNT 0xbc
44178 #define A_UP_OBQ_5_RDADDR 0xc0
44179 #define A_UP_OBQ_5_WRADDR 0xc4
44180 #define A_UP_OBQ_5_STATUS 0xc8
44181 #define A_UP_OBQ_5_PKTCNT 0xcc
44182 #define A_UP_IBQ_0_CONFIG 0xd0
44185 #define M_QUESIZE    0x3fU
44190 #define M_QUEBASE    0x3fU
44198 #define S_QUEBAREADDR    0
44206 #define A_UP_IBQ_0_REALADDR 0xd4
44217 #define M_QUEMEMADDR    0x7ffU
44221 #define A_UP_IBQ_1_CONFIG 0xd8
44222 #define A_UP_IBQ_1_REALADDR 0xdc
44223 #define A_UP_IBQ_2_CONFIG 0xe0
44224 #define A_UP_IBQ_2_REALADDR 0xe4
44225 #define A_UP_IBQ_3_CONFIG 0xe8
44226 #define A_UP_IBQ_3_REALADDR 0xec
44227 #define A_UP_IBQ_4_CONFIG 0xf0
44228 #define A_UP_IBQ_4_REALADDR 0xf4
44229 #define A_UP_IBQ_5_CONFIG 0xf8
44230 #define A_UP_IBQ_5_REALADDR 0xfc
44231 #define A_UP_OBQ_0_CONFIG 0x100
44232 #define A_UP_OBQ_0_REALADDR 0x104
44233 #define A_UP_OBQ_1_CONFIG 0x108
44234 #define A_UP_OBQ_1_REALADDR 0x10c
44235 #define A_UP_OBQ_2_CONFIG 0x110
44236 #define A_UP_OBQ_2_REALADDR 0x114
44237 #define A_UP_OBQ_3_CONFIG 0x118
44238 #define A_UP_OBQ_3_REALADDR 0x11c
44239 #define A_UP_OBQ_4_CONFIG 0x120
44240 #define A_UP_OBQ_4_REALADDR 0x124
44241 #define A_UP_OBQ_5_CONFIG 0x128
44242 #define A_UP_OBQ_5_REALADDR 0x12c
44243 #define A_UP_MAILBOX_STATUS 0x130
44246 #define M_MBGEN0    0xfffU
44251 #define M_GENTIMERTRIGGER    0xfU
44256 #define M_MBGEN1    0xffU
44260 #define S_MBPFINT    0
44261 #define M_MBPFINT    0xffU
44265 #define A_UP_UP_DBG_LA_CFG 0x140
44284 #define M_UPDBGLAWRPTR    0xfffU
44289 #define M_UPDBGLARDPTR    0xfffU
44297 #define S_UPDBGLAEN    0
44305 #define A_UP_UP_DBG_LA_DATA 0x144
44306 #define A_UP_PIO_MST_CONFIG 0x148
44309 #define M_FLSRC    0x7U
44318 #define M_SESRC    0x7U
44327 #define M_UPPF    0x7U
44331 #define S_UPRID    0
44332 #define M_UPRID    0xffffU
44340 #define S_T5_UPRID    0
44341 #define M_T5_UPRID    0xffU
44345 #define S_T6_UPRID    0
44346 #define M_T6_UPRID    0x1ffU
44350 #define A_UP_UP_SELF_CONTROL 0x14c
44352 #define S_UPSELFRESET    0
44356 #define A_UP_MAILBOX_PF0_CTL 0x180
44357 #define A_UP_MAILBOX_PF1_CTL 0x190
44358 #define A_UP_MAILBOX_PF2_CTL 0x1a0
44359 #define A_UP_MAILBOX_PF3_CTL 0x1b0
44360 #define A_UP_MAILBOX_PF4_CTL 0x1c0
44361 #define A_UP_MAILBOX_PF5_CTL 0x1d0
44362 #define A_UP_MAILBOX_PF6_CTL 0x1e0
44363 #define A_UP_MAILBOX_PF7_CTL 0x1f0
44364 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
44374 #define S_TSCHCHNLCRDY    0
44375 #define M_TSCHCHNLCRDY    0x3fffffffU
44379 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
44382 #define M_TSCHWRRLIMIT    0xffffU
44386 #define S_TSCHCHNLCWRDY    0
44387 #define M_TSCHCHNLCWRDY    0xffffU
44391 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
44394 #define M_TSCHWRRRELOAD    0xffffU
44398 #define S_TSCHCHNLCWATCH    0
44399 #define M_TSCHCHNLCWATCH    0xffffU
44403 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
44406 #define M_TSCHCHNLCNUM    0x1fU
44410 #define S_TSCHCHNLCCNT    0
44411 #define M_TSCHCHNLCCNT    0xffffffU
44427 #define A_UP_UPLADBGPCCHKDATA_0 0x240
44428 #define A_UP_UPLADBGPCCHKMASK_0 0x244
44429 #define A_UP_UPLADBGPCCHKDATA_1 0x250
44430 #define A_UP_UPLADBGPCCHKMASK_1 0x254
44431 #define A_UP_UPLADBGPCCHKDATA_2 0x260
44432 #define A_UP_UPLADBGPCCHKMASK_2 0x264
44433 #define A_UP_UPLADBGPCCHKDATA_3 0x270
44434 #define A_UP_UPLADBGPCCHKMASK_3 0x274
44435 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
44436 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
44437 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
44438 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
44439 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
44440 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
44441 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
44442 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
44443 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
44444 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
44445 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
44446 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
44447 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
44448 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
44449 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
44450 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
44451 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
44452 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
44453 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
44454 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
44455 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
44456 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
44457 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
44458 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
44459 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
44460 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
44461 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
44462 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
44463 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
44464 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
44465 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
44466 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
44467 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
44468 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
44469 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
44470 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
44471 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
44472 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
44473 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
44474 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
44475 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
44476 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
44477 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
44478 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
44479 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
44480 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
44481 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
44482 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
44483 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
44484 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
44485 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
44486 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
44487 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
44488 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
44489 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
44490 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
44491 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
44492 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
44493 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
44494 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
44495 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
44496 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
44497 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
44498 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
44499 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
44500 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
44501 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
44502 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
44503 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
44504 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
44505 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
44506 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
44507 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
44508 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
44509 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
44510 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
44511 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
44512 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
44513 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
44514 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
44515 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
44516 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
44517 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
44518 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
44521 #define CIM_CTL_BASE_ADDR 0x0
44523 #define A_CIM_CTL_CONFIG 0x0
44526 #define M_AUTOPREFLOC    0x1fU
44554 #define S_PREFEN    0
44566 #define A_CIM_CTL_PREFADDR 0x4
44567 #define A_CIM_CTL_ALLOCADDR 0x8
44568 #define A_CIM_CTL_INVLDTADDR 0xc
44569 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
44570 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
44571 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
44572 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
44573 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
44574 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
44575 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
44576 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
44577 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
44578 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
44579 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
44580 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
44581 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
44582 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
44583 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
44584 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
44585 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
44586 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
44587 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
44588 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
44589 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
44590 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
44591 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
44592 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
44593 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
44594 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
44595 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
44596 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
44597 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
44598 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
44599 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
44600 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
44601 #define A_CIM_CTL_FIFO_CNT 0x90
44603 #define S_CTLFIFOCNT    0
44604 #define M_CTLFIFOCNT    0xfU
44608 #define A_CIM_CTL_GLB_TIMER 0x94
44609 #define A_CIM_CTL_TIMER0 0x98
44610 #define A_CIM_CTL_TIMER1 0x9c
44611 #define A_CIM_CTL_GEN0 0xa0
44612 #define A_CIM_CTL_GEN1 0xa4
44613 #define A_CIM_CTL_GEN2 0xa8
44614 #define A_CIM_CTL_GEN3 0xac
44615 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
44616 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
44627 #define M_GENTIMERACT    0x3U
44632 #define M_GENTIMERCFG    0x3U
44640 #define S_GENTIMERSTRT    0
44644 #define A_CIM_CTL_GEN_TIMER0 0xb8
44645 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
44646 #define A_CIM_CTL_GEN_TIMER1 0xc0
44647 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
44648 #define A_CIM_CTL_GEN_TIMER2 0xc8
44649 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
44650 #define A_CIM_CTL_GEN_TIMER3 0xd0
44651 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
44652 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
44653 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
44667 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
44669 #define S_TSCHNLTICK    0
44670 #define M_TSCHNLTICK    0xffffU
44674 #define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
44736 #define S_TSC0RATECTL    0
44740 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
44866 #define S_TSC0RATEEN    0
44870 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
44872 #define S_MIN_MAX_EN    0
44876 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
44882 #define S_TSCHNLRATEL    0
44883 #define M_TSCHNLRATEL    0x7fffffffU
44891 #define S_T6_TSCHNLRATEL    0
44892 #define M_T6_TSCHNLRATEL    0x3fffffffU
44896 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
44899 #define M_TSCHNLRMAX    0xffffU
44903 #define S_TSCHNLRINCR    0
44904 #define M_TSCHNLRINCR    0xffffU
44909 #define M_TSCHNLRTSEL    0x3U
44913 #define S_T6_TSCHNLRINCR    0
44914 #define M_T6_TSCHNLRINCR    0x3fffU
44918 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
44919 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
44921 #define S_TSCHNLWEIGHT    0
44922 #define M_TSCHNLWEIGHT    0x3fffffU
44926 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
44932 #define S_TSCCLRATEL    0
44933 #define M_TSCCLRATEL    0xffffffU
44941 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
44944 #define M_TSCCLRMAX    0xffffU
44948 #define S_TSCCLRINCR    0
44949 #define M_TSCCLRINCR    0xffffU
44954 #define M_TSCCLRTSEL    0x3U
44958 #define S_T6_TSCCLRINCR    0
44959 #define M_T6_TSCCLRINCR    0x3fffU
44963 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
44969 #define S_TSCCLWRR    0
44970 #define M_TSCCLWRR    0x3ffffffU
44978 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
44980 #define S_TSCCLWEIGHT    0
44981 #define M_TSCCLWEIGHT    0xffffU
44986 #define M_PAUSEVECSEL    0x3U
44991 #define M_MPSPAUSEMASK    0xffU
44995 #define A_CIM_CTL_TSCH_TICK0 0xd80
44996 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
44997 #define A_CIM_CTL_TSCH_TICK1 0xd84
44998 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
44999 #define A_CIM_CTL_TSCH_TICK2 0xd88
45000 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
45001 #define A_CIM_CTL_TSCH_TICK3 0xd8c
45002 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
45003 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
45004 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
45005 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
45006 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
45007 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
45008 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
45009 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
45010 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
45011 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
45012 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
45074 #define S_PF0_OWNER_UP    0
45078 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
45079 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
45081 #define S_T5_CTLRID    0
45082 #define M_T5_CTLRID    0xffU
45086 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
45087 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
45088 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
45089 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
45091 #define S_T6_UPRID    0
45092 #define M_T6_UPRID    0x1ffU
45096 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
45097 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
45098 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
45099 #define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
45100 #define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
45106 #define S_CH0_PRIO_EN    0
45110 #define A_CIM_CTL_PIF_TIMEOUT 0xe40
45113 #define M_SLOW_TIMEOUT    0xffffU
45117 #define S_MA_TIMEOUT    0
45118 #define M_MA_TIMEOUT    0xffffU
45123 #define MAC_BASE_ADDR 0x0
45125 #define A_MAC_PORT_CFG 0x800
45128 #define M_MAC_CLK_SEL    0x7U
45141 #define M_PORTSPEED    0x3U
45158 #define M_PORT_MAP    0x7U
45175 #define M_DEBUG_PORT_SEL    0x3U
45191 #define A_MAC_PORT_RESET_CTRL 0x804
45317 #define A_MAC_PORT_LED_CFG 0x808
45320 #define M_LED1_CFG1    0x3U
45325 #define M_LED0_CFG1    0x3U
45345 #define A_MAC_PORT_LED_COUNTHI 0x80c
45346 #define A_MAC_PORT_LED_COUNTLO 0x810
45347 #define A_MAC_PORT_CFG3 0x814
45350 #define M_T5_FPGA_PTP_PORT    0x3U
45375 #define M_AN_ENA    0xfU
45380 #define M_SD_RX_CLK_ENA    0xfU
45385 #define M_SD_TX_CLK_ENA    0xfU
45394 #define M_HSSPLLSEL    0xfU
45398 #define S_HSSC16C20SEL    0
45399 #define M_HSSC16C20SEL    0xfU
45404 #define M_REF_CLK_SEL    0x3U
45417 #define M_MAC_FPGA_PTP_PORT    0x3U
45421 #define A_MAC_PORT_CFG2 0x818
45424 #define M_T5_AEC_PMA_TX_READY    0xfU
45428 #define S_T5_AEC_PMA_RX_READY    0
45429 #define M_T5_AEC_PMA_RX_READY    0xfU
45437 #define A_MAC_PORT_PKT_COUNT 0x81c
45438 #define A_MAC_PORT_CFG4 0x820
45441 #define M_AEC3_RX_WIDTH    0x3U
45446 #define M_AEC2_RX_WIDTH    0x3U
45451 #define M_AEC1_RX_WIDTH    0x3U
45456 #define M_AEC0_RX_WIDTH    0x3U
45461 #define M_AEC3_TX_WIDTH    0x3U
45466 #define M_AEC2_TX_WIDTH    0x3U
45471 #define M_AEC1_TX_WIDTH    0x3U
45475 #define S_AEC0_TX_WIDTH    0
45476 #define M_AEC0_TX_WIDTH    0x3U
45480 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
45481 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
45482 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
45608 #define S_XGMII_CLK_RESET    0
45612 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
45738 #define S_AN_CLK_ENABLE    0
45742 #define A_MAC_PORT_LINK_STATUS 0x834
45764 #define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
45783 #define M_AEC_SYS_LANE_SELECT_3    0x3U
45788 #define M_AEC_SYS_LANE_SELECT_2    0x3U
45793 #define M_AEC_SYS_LANE_SELECT_1    0x3U
45797 #define S_AEC_SYS_LANE_SELECT_O    0
45798 #define M_AEC_SYS_LANE_SELECT_O    0x3U
45802 #define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
45821 #define M_AEC_RX_LANE_ID_3    0x3U
45826 #define M_AEC_RX_LANE_ID_2    0x3U
45831 #define M_AEC_RX_LANE_ID_1    0x3U
45835 #define S_AEC_RX_LANE_ID_O    0
45836 #define M_AEC_RX_LANE_ID_O    0x3U
45840 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
45842 #define S_XGMII_CLK_IN_1MS_LO_40G    0
45843 #define M_XGMII_CLK_IN_1MS_LO_40G    0xffffU
45847 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
45849 #define S_XGMII_CLK_IN_1MS_HI_40G    0
45850 #define M_XGMII_CLK_IN_1MS_HI_40G    0xfU
45854 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
45856 #define S_XGMII_CLK_IN_1MS_LO_100G    0
45857 #define M_XGMII_CLK_IN_1MS_LO_100G    0xffffU
45861 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
45863 #define S_XGMII_CLK_IN_1MS_HI_100G    0
45864 #define M_XGMII_CLK_IN_1MS_HI_100G    0xfU
45868 #define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
45871 #define M_CTL_FSM_CUR_STATE    0x7U
45876 #define M_CIN_FSM_CUR_STATE    0x3U
45881 #define M_CRI_FSM_CUR_STATE    0x7U
45886 #define M_CU_C3_ACK_VALUE    0x3U
45891 #define M_CU_C2_ACK_VALUE    0x3U
45896 #define M_CU_C1_ACK_VALUE    0x3U
45901 #define M_CU_C0_ACK_VALUE    0x3U
45914 #define M_CUF_C3_UPDATE    0x3U
45919 #define M_CUF_C2_UPDATE    0x3U
45924 #define M_CUF_C1_UPDATE    0x3U
45929 #define M_CUF_C0_UPDATE    0x3U
45941 #define S_REG_MAN_DEC_REQ    0
45945 #define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
45952 #define M_CUF_C0_FSM_DEBUG    0x7U
45957 #define M_CUF_C1_FSM_DEBUG    0x7U
45962 #define M_CUF_C2_FSM_DEBUG    0x7U
45966 #define S_LCK_FSM_CUR_STATE    0
45967 #define M_LCK_FSM_CUR_STATE    0x7U
45971 #define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
45972 #define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
45973 #define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
45974 #define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
45975 #define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
45976 #define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
45977 #define A_MAC_PORT_MAC_DEBUG_RO 0x870
45996 #define M_MAC1G10G_IF_MODE_ENA    0x3U
46028 #define S_MAC1G10G_TX_UNDERFLOW    0
46032 #define A_MAC_PORT_MAC_CTRL_RW 0x874
46035 #define M_MAC40G100G_FF_TX_PFC_XOFF    0xffU
46056 #define M_MAC1G10G_IF_MODE_SET    0x3U
46069 #define M_MAC1G10G_XOFF_GEN    0xffU
46073 #define S_MAC1G_LOOP_BCK    0
46077 #define A_MAC_PORT_PCS_DEBUG0_RO 0x878
46080 #define M_FPGA_LOCK    0xfU
46101 #define M_AN_SELECT    0x1fU
46110 #define M_PCS40G_BLOCK_LOCK    0xfU
46154 #define S_SGMII_SG_SPEED    0
46155 #define M_SGMII_SG_SPEED    0x3U
46159 #define A_MAC_PORT_PCS_CTRL_RW 0x87c
46170 #define M_BLK_STB_VAL    0xffU
46175 #define M_DEBUG_SEL    0xfU
46180 #define M_SGMII_LOOP    0x7U
46193 #define M_PCS100G_TX_LANE_THRESH    0xfU
46202 #define M_SGMII_TX_LANE_CKMULT    0x7U
46206 #define S_SGMII_TX_LANE_THRESH    0
46207 #define M_SGMII_TX_LANE_THRESH    0xfU
46211 #define A_MAC_PORT_PCS_DEBUG1_RO 0x880
46221 #define S_PCS100G_BLOCK_LOCK    0
46222 #define M_PCS100G_BLOCK_LOCK    0xfffffU
46226 #define A_MAC_PORT_PERR_INT_EN_100G 0x884
46344 #define S_PERR_RX0_PCS100G    0
46348 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
46349 #define A_MAC_PORT_PERR_ENABLE_100G 0x88c
46350 #define A_MAC_PORT_MAC_STAT_DEBUG 0x890
46351 #define A_MAC_PORT_MAC_25G_50G_AM0 0x894
46352 #define A_MAC_PORT_MAC_25G_50G_AM1 0x898
46353 #define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
46354 #define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
46355 #define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
46356 #define A_MAC_PORT_EPIO_DATA0 0x8c0
46357 #define A_MAC_PORT_EPIO_DATA1 0x8c4
46358 #define A_MAC_PORT_EPIO_DATA2 0x8c8
46359 #define A_MAC_PORT_EPIO_DATA3 0x8cc
46360 #define A_MAC_PORT_EPIO_OP 0x8d0
46361 #define A_MAC_PORT_WOL_STATUS 0x8d4
46362 #define A_MAC_PORT_INT_EN 0x8d8
46384 #define A_MAC_PORT_INT_CAUSE 0x8dc
46385 #define A_MAC_PORT_PERR_INT_EN 0x8e0
46483 #define S_PERR0_TX    0
46611 #define S_PERR_TX_PCS1G    0
46615 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
46629 #define A_MAC_PORT_PERR_ENABLE 0x8e8
46643 #define A_MAC_PORT_PERR_INJECT 0x8ec
46646 #define M_MEMSEL_PERR    0x3fU
46650 #define A_MAC_PORT_HSS_CFG0 0x8f0
46708 #define A_MAC_PORT_HSS_CFG1 0x8f4
46711 #define M_RXACONFIGSEL    0x3U
46724 #define M_RXBCONFIGSEL    0x3U
46737 #define M_RXCCONFIGSEL    0x3U
46750 #define M_RXDCONFIGSEL    0x3U
46763 #define M_TXACONFIGSEL    0x3U
46776 #define M_TXBCONFIGSEL    0x3U
46789 #define M_TXCCONFIGSEL    0x3U
46802 #define M_TXDCONFIGSEL    0x3U
46810 #define S_TXDREFRESH    0
46814 #define A_MAC_PORT_HSS_CFG2 0x8f8
46848 #define A_MAC_PORT_HSS_CFG3 0x8fc
46851 #define M_HSSCALSSTN    0x7U
46856 #define M_HSSCALSSTP    0x7U
46861 #define M_HSSVBOOSTDIVB    0x7U
46866 #define M_HSSVBOOSTDIVA    0x7U
46871 #define M_HSSPLLCONFIGB    0xffU
46875 #define S_HSSPLLCONFIGA    0
46876 #define M_HSSPLLCONFIGA    0xffU
46881 #define M_T6_HSSCALSSTN    0x3fU
46886 #define M_T6_HSSCALSSTP    0x3fU
46890 #define A_MAC_PORT_HSS_CFG4 0x900
46893 #define M_HSSDIVSELA    0x1ffU
46897 #define S_HSSDIVSELB    0
46898 #define M_HSSDIVSELB    0x1ffU
46903 #define M_HSSREFDIVA    0xfU
46908 #define M_HSSREFDIVB    0xfU
46920 #define A_MAC_PORT_HSS_STATUS 0x904
46934 #define S_HSSPRTREADYA    0
46954 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
47016 #define S_TXDREFRESH_STATUS    0
47020 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
47021 #define A_MAC_PORT_HSS_PL_CTL 0x910
47024 #define M_TOV    0xffU
47029 #define M_TSU    0xffU
47033 #define S_IPW    0
47034 #define M_IPW    0xffU
47038 #define A_MAC_PORT_RUNT_FRAME 0x914
47044 #define S_RUNT    0
47045 #define M_RUNT    0xffffU
47049 #define A_MAC_PORT_EEE_STATUS 0x918
47052 #define M_EEE_TX_10G_STATE    0x3U
47057 #define M_EEE_RX_10G_STATE    0x3U
47062 #define M_EEE_TX_1G_STATE    0x3U
47067 #define M_EEE_RX_1G_STATE    0x3U
47083 #define S_PMA_TX_QUIET    0
47087 #define A_MAC_PORT_CGEN 0x91c
47121 #define S_SD0_CGEN    0
47125 #define A_MAC_PORT_CGEN_MTIP 0x920
47171 #define S_PCSSEG0_CGEN    0
47175 #define A_MAC_PORT_TX_TS_ID 0x924
47177 #define S_TS_ID    0
47178 #define M_TS_ID    0x7U
47182 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
47183 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
47184 #define A_MAC_PORT_EEE_CTL 0x930
47187 #define M_EEE_CTRL    0x3fffffffU
47195 #define S_EEE_ENABLE    0
47199 #define A_MAC_PORT_EEE_TX_CTL 0x934
47202 #define M_WAKE_TIMER    0xffffU
47207 #define M_HSS_TIMER    0xfU
47227 #define S_EEE_TX_RESET    0
47231 #define A_MAC_PORT_EEE_RX_CTL 0x938
47237 #define S_EEE_RX_RESET    0
47241 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
47242 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
47243 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
47244 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
47245 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
47246 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
47247 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
47248 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
47249 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
47250 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
47251 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
47252 #define A_MAC_PORT_EEE_WF_COUNT 0x968
47258 #define S_WAKE_CNT    0
47259 #define M_WAKE_CNT    0xffffU
47263 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
47264 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
47265 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
47266 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
47267 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
47268 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
47269 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
47270 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
47271 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
47273 #define S_PTP_OFFSET    0
47274 #define M_PTP_OFFSET    0xffU
47278 #define A_MAC_PORT_PTP_SUM_LO 0x990
47279 #define A_MAC_PORT_PTP_SUM_HI 0x994
47280 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
47283 #define M_Y    0xffffU
47287 #define S_X    0
47288 #define M_X    0xffffU
47292 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
47295 #define M_Y_TICK    0xffffU
47299 #define S_X_TICK    0
47300 #define M_X_TICK    0xffffU
47304 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
47305 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
47308 #define CXGBE_M_B    0xffffU
47312 #define S_A    0
47313 #define M_A    0xffffU
47317 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
47318 #define A_MAC_PORT_PTP_CFG 0x9ac
47333 #define M_CYCLE1    0xffU
47337 #define S_Q    0
47338 #define M_Q    0xffU
47354 #define A_MAC_PORT_PTP_PPS 0x9b0
47355 #define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
47356 #define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
47357 #define A_MAC_PORT_PTP_STATUS 0x9bc
47359 #define S_ALARM_DONE    0
47363 #define A_MAC_PORT_MTIP_REVISION 0xa00
47366 #define M_CUSTREV    0xffffU
47371 #define M_VER    0xffU
47375 #define S_MTIP_REV    0
47376 #define M_MTIP_REV    0xffU
47380 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
47381 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
47467 #define S_TX_ENA    0
47471 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
47472 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
47474 #define S_MACADDRHI    0
47475 #define M_MACADDRHI    0xffffU
47479 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
47481 #define S_LEN    0
47482 #define M_LEN    0xffffU
47486 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
47489 #define M_AVAIL    0xffffU
47493 #define S_EMPTY    0
47494 #define M_EMPTY    0xffffU
47498 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
47499 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
47502 #define M_ALMSTFULL    0xffffU
47506 #define S_ALMSTEMPTY    0
47507 #define M_ALMSTEMPTY    0xffffU
47511 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
47512 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
47518 #define S_HASHTABLE_ADDR    0
47519 #define M_HASHTABLE_ADDR    0x3fU
47523 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
47537 #define S_RX_LOC_FAULT    0
47541 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
47543 #define S_IPG    0
47544 #define M_IPG    0x7fU
47548 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
47550 #define S_RXFIFORST    0
47554 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
47556 #define S_MACCRDRST    0
47557 #define M_MACCRDRST    0xffU
47561 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
47563 #define S_INITCREDIT    0
47564 #define M_INITCREDIT    0xffU
47568 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
47570 #define S_STATUS    0
47571 #define M_STATUS    0xffU
47575 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
47576 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
47577 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
47578 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
47579 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
47580 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
47581 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
47582 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
47583 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
47584 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
47585 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
47586 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
47587 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
47588 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
47589 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
47590 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
47591 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
47592 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
47593 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
47594 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
47595 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
47596 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
47597 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
47598 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
47599 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
47600 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
47601 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
47602 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
47603 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
47604 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
47605 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
47606 #define A_MAC_PORT_IFOUTERRORS 0xaf8
47607 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
47608 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
47609 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
47610 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
47611 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
47612 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
47613 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
47614 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
47615 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
47616 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
47617 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
47618 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
47619 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
47620 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
47621 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
47622 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
47623 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
47624 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
47625 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
47626 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
47627 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
47628 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
47629 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
47630 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
47631 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
47632 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
47633 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
47634 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
47635 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
47636 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
47637 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
47638 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
47639 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
47640 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
47641 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
47642 #define A_MAC_PORT_IFINERRORS 0xb90
47643 #define A_MAC_PORT_IFINERRORSHI 0xb94
47644 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
47645 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
47646 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
47647 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
47648 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
47649 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
47650 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
47651 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
47652 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
47653 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
47654 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
47655 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
47656 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
47657 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
47658 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
47659 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
47660 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
47661 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
47662 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
47663 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
47664 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
47665 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
47666 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
47667 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
47668 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
47669 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
47670 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
47671 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
47672 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
47673 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
47674 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
47675 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
47676 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
47677 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
47678 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
47679 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
47680 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
47722 #define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
47725 #define M_VER_1G10G    0xffU
47729 #define S_REV_1G10G    0
47730 #define M_REV_1G10G    0xffU
47734 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
47776 #define S_EXTDCAPABILITY    0
47780 #define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
47781 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
47782 #define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
47820 #define S_TX_ENAMAC    0
47824 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
47825 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
47826 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
47852 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
47853 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
47864 #define M_CUSPEED    0x3U
47868 #define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
47871 #define M_SET_LEN    0xffffU
47875 #define S_FRM_LEN_SET    0
47876 #define M_FRM_LEN_SET    0xffffU
47880 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
47886 #define S_REALTIMEPGRCVD    0
47890 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
47891 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
47894 #define M_RX1G10G_EMPTY    0xffffU
47898 #define S_RX1G10G_AVAIL    0
47899 #define M_RX1G10G_AVAIL    0xffffU
47903 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
47904 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
47907 #define M_TX1G10G_EMPTY    0xffffU
47911 #define S_TX1G10G_AVAIL    0
47912 #define M_TX1G10G_AVAIL    0xffffU
47916 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
47919 #define M_ALMOSTFULL    0xffffU
47923 #define S_ALMOSTEMPTY    0
47924 #define M_ALMOSTEMPTY    0xffffU
47928 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
47929 #define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
47930 #define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
47933 #define M_CLK_DIVISOR    0x1ffU
47946 #define M_HOLD_TIME_SETTING    0x7U
47954 #define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
47965 #define M_PORT_PHY_ADDR    0x1fU
47969 #define S_DEVICE_REG_ADDR    0
47970 #define M_DEVICE_REG_ADDR    0x1fU
47974 #define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
47976 #define S_MDIO_DATA    0
47977 #define M_MDIO_DATA    0xffffU
47981 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
47982 #define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
47983 #define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
48001 #define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
48002 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
48004 #define S_COUNT_LO    0
48005 #define M_COUNT_LO    0xffffU
48009 #define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
48010 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
48012 #define S_COUNT_HI    0
48013 #define M_COUNT_HI    0x1fU
48017 #define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
48018 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
48029 #define M_SGMII_SPEED    0x3U
48037 #define S_SGMII_ENA    0
48041 #define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
48044 #define M_CL1_PAUSE_QUANTA    0xffffU
48048 #define S_CL0_PAUSE_QUANTA    0
48049 #define M_CL0_PAUSE_QUANTA    0xffffU
48053 #define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
48056 #define M_CL3_PAUSE_QUANTA    0xffffU
48060 #define S_CL2_PAUSE_QUANTA    0
48061 #define M_CL2_PAUSE_QUANTA    0xffffU
48065 #define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
48068 #define M_CL5_PAUSE_QUANTA    0xffffU
48072 #define S_CL4_PAUSE_QUANTA    0
48073 #define M_CL4_PAUSE_QUANTA    0xffffU
48077 #define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
48080 #define M_CL7_PAUSE_QUANTA    0xffffU
48084 #define S_CL6_PAUSE_QUANTA    0
48085 #define M_CL6_PAUSE_QUANTA    0xffffU
48089 #define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
48092 #define M_CL1_QUANTA_THRESH    0xffffU
48096 #define S_CL0_QUANTA_THRESH    0
48097 #define M_CL0_QUANTA_THRESH    0xffffU
48101 #define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
48104 #define M_CL3_QUANTA_THRESH    0xffffU
48108 #define S_CL2_QUANTA_THRESH    0
48109 #define M_CL2_QUANTA_THRESH    0xffffU
48113 #define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
48116 #define M_CL5_QUANTA_THRESH    0xffffU
48120 #define S_CL4_QUANTA_THRESH    0
48121 #define M_CL4_QUANTA_THRESH    0xffffU
48125 #define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
48128 #define M_CL7_QUANTA_THRESH    0xffffU
48132 #define S_CL6_QUANTA_THRESH    0
48133 #define M_CL6_QUANTA_THRESH    0xffffU
48137 #define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
48139 #define S_STATUS_BIT    0
48140 #define M_STATUS_BIT    0xffU
48144 #define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
48145 #define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
48155 #define S_SATURATE    0
48159 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
48160 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
48161 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
48162 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
48163 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
48164 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
48165 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
48166 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
48167 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
48168 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
48169 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
48170 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
48171 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
48172 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
48173 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
48174 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
48175 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
48176 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
48177 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
48178 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
48179 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
48180 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
48181 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
48182 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
48183 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
48184 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
48185 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
48186 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
48187 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
48188 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
48189 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
48190 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
48191 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
48192 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
48193 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
48194 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
48195 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
48196 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
48197 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
48198 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
48199 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
48200 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
48201 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
48202 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
48203 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
48204 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
48205 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
48206 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
48207 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
48208 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
48209 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
48210 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
48211 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
48212 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
48213 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
48214 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
48215 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
48216 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
48217 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
48218 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
48219 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
48220 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
48221 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
48222 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
48223 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
48224 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
48225 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
48226 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
48227 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
48228 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
48229 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
48230 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
48231 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
48232 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
48233 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
48234 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
48235 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
48236 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
48237 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
48238 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
48239 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
48240 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
48241 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
48242 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
48243 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
48244 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
48245 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
48246 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
48247 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
48248 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
48249 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
48250 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
48251 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
48252 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
48253 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
48254 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
48255 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
48256 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
48257 #define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
48263 #define S_IF_MODE    0
48264 #define M_IF_MODE    0x3U
48268 #define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
48270 #define S_IF_STATUS_MODE    0
48271 #define M_IF_STATUS_MODE    0x3U
48275 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
48276 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
48277 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
48278 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
48279 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
48280 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
48281 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
48282 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
48283 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
48284 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
48285 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
48286 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
48287 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
48288 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
48289 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
48290 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
48291 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
48292 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
48293 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
48294 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
48295 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
48296 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
48297 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
48298 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
48299 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
48300 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
48301 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
48302 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
48303 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
48304 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
48305 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
48306 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
48307 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
48309 #define S_ACTIVE    0
48310 #define M_ACTIVE    0x3fU
48314 #define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
48336 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
48338 #define S_MODE_CTL    0
48339 #define M_MODE_CTL    0x3U
48343 #define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
48349 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
48351 #define S_TXCLK_CTL    0
48352 #define M_TXCLK_CTL    0xffffU
48356 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
48357 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
48358 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
48359 #define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
48360 #define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
48361 #define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
48371 #define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
48373 #define S_NP_TX    0
48374 #define M_NP_TX    0xffffU
48378 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
48380 #define S_COL_CNT    0
48381 #define M_COL_CNT    0xffffU
48385 #define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
48387 #define S_LP_NP_RX    0
48388 #define M_LP_NP_RX    0xffffU
48392 #define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
48394 #define S_EXTENDED_STATUS    0
48395 #define M_EXTENDED_STATUS    0xffffU
48399 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
48405 #define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
48407 #define S_SCRATCH    0
48408 #define M_SCRATCH    0xffffU
48412 #define A_MAC_PORT_MTIP_SGMII_REV 0x1244
48415 #define M_SGMII_VER    0xffU
48419 #define S_SGMII_REV    0
48420 #define M_SGMII_REV    0xffU
48424 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
48426 #define S_LINK_TIMER_LO    0
48427 #define M_LINK_TIMER_LO    0xffffU
48431 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
48433 #define S_LINK_TIMER_HI    0
48434 #define M_LINK_TIMER_HI    0xffffU
48438 #define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
48444 #define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
48446 #define S_T6_DECODE_ERROR    0
48447 #define M_T6_DECODE_ERROR    0xffffU
48451 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
48462 #define M_SPEED_SEL2    0xfU
48466 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
48496 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
48497 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
48498 #define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
48500 #define S_10G_CAPABLE    0
48504 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
48530 #define S_CLAUSE_22_REG_PRESENT    0
48534 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
48535 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
48537 #define S_PCS_TYPE_SELECTION    0
48538 #define M_PCS_TYPE_SELECTION    0x3U
48542 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
48545 #define M_DEVICE_PRESENT    0x3U
48565 #define S_10GBASE_R_CAPABLE    0
48569 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
48571 #define S_PCS_PACKAGE_IDENTIFIER_LO    0
48572 #define M_PCS_PACKAGE_IDENTIFIER_LO    0xffffU
48576 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
48578 #define S_PCS_PACKAGE_IDENTIFIER_HI    0
48579 #define M_PCS_PACKAGE_IDENTIFIER_HI    0xffffU
48583 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
48601 #define S_10GBASE_R_PCS_BLOCK_LOCK    0
48605 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
48616 #define M_BERBER_COUNTER    0x3fU
48620 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
48622 #define S_TEST_PATTERN_SEED_A0    0
48623 #define M_TEST_PATTERN_SEED_A0    0xffffU
48627 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
48629 #define S_TEST_PATTERN_SEED_A1    0
48630 #define M_TEST_PATTERN_SEED_A1    0xffffU
48634 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
48636 #define S_TEST_PATTERN_SEED_A2    0
48637 #define M_TEST_PATTERN_SEED_A2    0xffffU
48641 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
48643 #define S_TEST_PATTERN_SEED_A3    0
48644 #define M_TEST_PATTERN_SEED_A3    0x3ffU
48648 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
48650 #define S_TEST_PATTERN_SEED_B0    0
48651 #define M_TEST_PATTERN_SEED_B0    0xffffU
48655 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
48657 #define S_TEST_PATTERN_SEED_B1    0
48658 #define M_TEST_PATTERN_SEED_B1    0xffffU
48662 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
48664 #define S_TEST_PATTERN_SEED_B2    0
48665 #define M_TEST_PATTERN_SEED_B2    0xffffU
48669 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
48671 #define S_TEST_PATTERN_SEED_B3    0
48672 #define M_TEST_PATTERN_SEED_B3    0x3ffU
48676 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
48702 #define S_DATA_PATTERN_SELECT    0
48706 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
48708 #define S_TEST_PATTERN_ERR_CNTR    0
48709 #define M_TEST_PATTERN_ERR_CNTR    0xffffU
48713 #define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
48719 #define S_RECEIVE_FIFO_FAULT    0
48723 #define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
48734 #define M_SPEED_SELECTION2    0xfU
48738 #define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
48744 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
48745 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
48748 #define M_T6_DEVICE_ID1    0xffffU
48752 #define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
48766 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
48768 #define S_CLAUSE_22_REG    0
48772 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
48786 #define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
48788 #define S_PCS_TYPE_SEL    0
48789 #define M_PCS_TYPE_SEL    0x7U
48793 #define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
48807 #define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
48808 #define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
48809 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
48819 #define S_KR4_BLOCK_LOCK    0
48823 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
48834 #define M_BER_CNT    0x3fU
48838 #define S_ERR_BL_CNT    0
48839 #define M_ERR_BL_CNT    0xffU
48843 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
48853 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
48855 #define S_TP_ERR_CNTR    0
48856 #define M_TP_ERR_CNTR    0xffffU
48860 #define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
48862 #define S_BER_HI_ORDER_CNT    0
48863 #define M_BER_HI_ORDER_CNT    0xffffU
48867 #define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
48873 #define S_ERR_BLK_CNTR    0
48874 #define M_ERR_BLK_CNTR    0x3fffU
48878 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
48896 #define S_LANE_0_BLK_LCK    0
48900 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
48901 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
48915 #define S_LANE_0_ALIGN_MRKR_LCK    0
48919 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
48920 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
48923 #define M_CLK_DIV    0x1ffU
48936 #define M_MDIO_HOLD_TIME    0x7U
48944 #define S_MDIO_BUSY    0
48948 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
48959 #define M_PORT_ADDR    0x1fU
48963 #define S_DEV_ADDR    0
48964 #define M_DEV_ADDR    0x1fU
48968 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
48974 #define S_DATA_WORD    0
48975 #define M_DATA_WORD    0xffffU
48979 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
48981 #define S_MDIO_ADDR    0
48982 #define M_MDIO_ADDR    0xffffU
48986 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
48988 #define S_BIP_ERR_CNT_LANE_0    0
48989 #define M_BIP_ERR_CNT_LANE_0    0xffffU
48993 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
48995 #define S_BIP_ERR_CNT_LANE_1    0
48996 #define M_BIP_ERR_CNT_LANE_1    0xffffU
49000 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
49002 #define S_BIP_ERR_CNT_LANE_2    0
49003 #define M_BIP_ERR_CNT_LANE_2    0xffffU
49007 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
49009 #define S_BIP_ERR_CNT_LANE_3    0
49010 #define M_BIP_ERR_CNT_LANE_3    0xffffU
49014 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
49016 #define S_VLANTAG    0
49017 #define CXGBE_M_VLANTAG    0xffffU
49021 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
49022 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
49023 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
49024 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
49025 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
49026 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
49027 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
49028 #define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
49030 #define S_KR4_LANE_0_MAPPING    0
49031 #define M_KR4_LANE_0_MAPPING    0x3U
49035 #define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
49037 #define S_KR4_LANE_1_MAPPING    0
49038 #define M_KR4_LANE_1_MAPPING    0x3U
49042 #define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
49044 #define S_KR4_LANE_2_MAPPING    0
49045 #define M_KR4_LANE_2_MAPPING    0x3U
49049 #define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
49051 #define S_KR4_LANE_3_MAPPING    0
49052 #define M_KR4_LANE_3_MAPPING    0x3U
49056 #define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
49057 #define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
49058 #define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
49060 #define S_SHRT_MRKR_CNFG    0
49064 #define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
49065 #define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
49066 #define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
49072 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
49074 #define S_CR4_DEVICE_ID0    0
49075 #define M_CR4_DEVICE_ID0    0xffffU
49079 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
49081 #define S_CR4_DEVICE_ID1    0
49082 #define M_CR4_DEVICE_ID1    0xffffU
49086 #define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
49096 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
49098 #define S_CLAUSE22REG_PRESENT    0
49102 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
49116 #define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
49118 #define S_CR4_PCS_TYPE_SELECTION    0
49119 #define M_CR4_PCS_TYPE_SELECTION    0x7U
49123 #define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
49124 #define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
49125 #define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
49126 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
49132 #define S_BR_BLOCK_LOCK    0
49136 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
49139 #define M_BER_COUNTER    0x3fU
49143 #define S_ERRORED_BLOCKS_CNTR    0
49144 #define M_ERRORED_BLOCKS_CNTR    0xffU
49148 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
49154 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
49156 #define S_BASE_R_TEST_ERR_CNT    0
49157 #define M_BASE_R_TEST_ERR_CNT    0xffffU
49161 #define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
49163 #define S_BER_HIGH_ORDER_CNT    0
49164 #define M_BER_HIGH_ORDER_CNT    0xffffU
49168 #define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
49174 #define S_ERR_BLKS_CNTR    0
49175 #define M_ERR_BLKS_CNTR    0x3fffU
49179 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
49213 #define S_LANE_0_BLCK_LCK    0
49217 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
49263 #define S_LANE_8_BLCK_LCK    0
49267 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
49297 #define S_LANE0_ALGN_MRKR_LCK    0
49301 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
49347 #define S_LANE8_ALGN_MRKR_LCK    0
49351 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
49370 #define M_PCS_SPEED    0xfU
49374 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
49388 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
49390 #define S_DEVICE_ID0    0
49391 #define M_DEVICE_ID0    0xffffU
49395 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
49397 #define S_DEVICE_ID1    0
49398 #define M_DEVICE_ID1    0xffffU
49402 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
49416 #define S_10G    0
49420 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
49446 #define S_CL22    0
49450 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
49464 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
49466 #define S_PCSTYPE    0
49467 #define M_PCSTYPE    0x7U
49471 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
49505 #define S_10GBASE_R    0
49509 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
49511 #define S_BIP_ERR_CNTLANE_0    0
49512 #define M_BIP_ERR_CNTLANE_0    0xffffU
49516 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
49518 #define S_BIP_ERR_CNTLANE_1    0
49519 #define M_BIP_ERR_CNTLANE_1    0xffffU
49523 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
49525 #define S_BIP_ERR_CNTLANE_2    0
49526 #define M_BIP_ERR_CNTLANE_2    0xffffU
49530 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
49532 #define S_BIP_ERR_CNTLANE_3    0
49533 #define M_BIP_ERR_CNTLANE_3    0xffffU
49537 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
49539 #define S_BIP_ERR_CNTLANE_4    0
49540 #define M_BIP_ERR_CNTLANE_4    0xffffU
49544 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
49546 #define S_BIP_ERR_CNTLANE_5    0
49547 #define M_BIP_ERR_CNTLANE_5    0xffffU
49551 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
49553 #define S_PKG_ID0    0
49554 #define M_PKG_ID0    0xffffU
49558 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
49560 #define S_BIP_ERR_CNTLANE_6    0
49561 #define M_BIP_ERR_CNTLANE_6    0xffffU
49565 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
49567 #define S_PKG_ID1    0
49568 #define M_PKG_ID1    0xffffU
49572 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
49574 #define S_BIP_ERR_CNTLANE_7    0
49575 #define M_BIP_ERR_CNTLANE_7    0xffffU
49579 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
49581 #define S_BIP_ERR_CNTLANE_8    0
49582 #define M_BIP_ERR_CNTLANE_8    0xffffU
49586 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
49588 #define S_BIP_ERR_CNTLANE_9    0
49589 #define M_BIP_ERR_CNTLANE_9    0xffffU
49593 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
49595 #define S_BIP_ERR_CNTLANE_10    0
49596 #define M_BIP_ERR_CNTLANE_10    0xffffU
49600 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
49602 #define S_BIP_ERR_CNTLANE_11    0
49603 #define M_BIP_ERR_CNTLANE_11    0xffffU
49607 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
49609 #define S_BIP_ERR_CNTLANE_12    0
49610 #define M_BIP_ERR_CNTLANE_12    0xffffU
49614 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
49616 #define S_BIP_ERR_CNTLANE_13    0
49617 #define M_BIP_ERR_CNTLANE_13    0xffffU
49621 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
49623 #define S_BIP_ERR_CNTLANE_14    0
49624 #define M_BIP_ERR_CNTLANE_14    0xffffU
49628 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
49630 #define S_BIP_ERR_CNTLANE_15    0
49631 #define M_BIP_ERR_CNTLANE_15    0xffffU
49635 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
49637 #define S_BIP_ERR_CNTLANE_16    0
49638 #define M_BIP_ERR_CNTLANE_16    0xffffU
49642 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
49644 #define S_BIP_ERR_CNTLANE_17    0
49645 #define M_BIP_ERR_CNTLANE_17    0xffffU
49649 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
49651 #define S_BIP_ERR_CNTLANE_18    0
49652 #define M_BIP_ERR_CNTLANE_18    0xffffU
49656 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
49658 #define S_BIP_ERR_CNTLANE_19    0
49659 #define M_BIP_ERR_CNTLANE_19    0xffffU
49663 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
49670 #define M_RESEREVED    0xffU
49686 #define S_BLOCKLOCK    0
49690 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
49701 #define M_HIBERCOUNT    0x3fU
49705 #define S_ERRBLKCNT    0
49706 #define M_ERRBLKCNT    0xffU
49710 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
49712 #define S_SEEDA    0
49713 #define M_SEEDA    0xffffU
49717 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
49719 #define S_SEEDA1    0
49720 #define M_SEEDA1    0xffffU
49724 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
49726 #define S_SEEDA2    0
49727 #define M_SEEDA2    0xffffU
49731 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
49733 #define S_SEEDA3    0
49734 #define M_SEEDA3    0x3ffU
49738 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
49740 #define S_SEEDB    0
49741 #define M_SEEDB    0xffffU
49745 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
49747 #define S_SEEDB1    0
49748 #define M_SEEDB1    0xffffU
49752 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
49754 #define S_SEEDB2    0
49755 #define M_SEEDB2    0xffffU
49759 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
49761 #define S_SEEDB3    0
49762 #define M_SEEDB3    0x3ffU
49766 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
49792 #define S_DATAPATSEL    0
49796 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
49798 #define S_TEST_ERR_CNT    0
49799 #define M_TEST_ERR_CNT    0xffffU
49803 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
49805 #define S_BER_CNT_HI    0
49806 #define M_BER_CNT_HI    0xffffU
49810 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
49816 #define S_BLOCK_CNT_HI    0
49817 #define M_BLOCK_CNT_HI    0x3fffU
49821 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
49855 #define S_LANE0    0
49859 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
49905 #define S_LANE8    0
49909 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
49939 #define S_AMLOCK0    0
49943 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
49989 #define S_AMLOCK8    0
49993 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
49995 #define S_BIPERR_CNT    0
49996 #define M_BIPERR_CNT    0xffffU
50000 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
50001 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
50002 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
50003 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
50004 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
50005 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
50006 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
50007 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
50008 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
50009 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
50010 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
50011 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
50012 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
50013 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
50014 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
50015 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
50016 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
50017 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
50018 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
50019 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
50021 #define S_MAP    0
50022 #define M_MAP    0x1fU
50026 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
50027 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
50028 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
50029 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
50030 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
50031 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
50032 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
50033 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
50034 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
50035 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
50036 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
50037 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
50038 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
50039 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
50040 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
50041 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
50042 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
50043 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
50044 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
50045 #define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
50047 #define S_LANE_0_MAPPING    0
50048 #define M_LANE_0_MAPPING    0x3fU
50052 #define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
50054 #define S_LANE_1_MAPPING    0
50055 #define M_LANE_1_MAPPING    0x3fU
50059 #define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
50061 #define S_LANE_2_MAPPING    0
50062 #define M_LANE_2_MAPPING    0x3fU
50066 #define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
50068 #define S_LANE_3_MAPPING    0
50069 #define M_LANE_3_MAPPING    0x3fU
50073 #define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
50075 #define S_LANE_4_MAPPING    0
50076 #define M_LANE_4_MAPPING    0x3fU
50080 #define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
50082 #define S_LANE_5_MAPPING    0
50083 #define M_LANE_5_MAPPING    0x3fU
50087 #define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
50089 #define S_LANE_6_MAPPING    0
50090 #define M_LANE_6_MAPPING    0x3fU
50094 #define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
50096 #define S_LANE_7_MAPPING    0
50097 #define M_LANE_7_MAPPING    0x3fU
50101 #define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
50103 #define S_LANE_8_MAPPING    0
50104 #define M_LANE_8_MAPPING    0x3fU
50108 #define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
50110 #define S_LANE_9_MAPPING    0
50111 #define M_LANE_9_MAPPING    0x3fU
50115 #define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
50117 #define S_LANE_10_MAPPING    0
50118 #define M_LANE_10_MAPPING    0x3fU
50122 #define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
50124 #define S_LANE_11_MAPPING    0
50125 #define M_LANE_11_MAPPING    0x3fU
50129 #define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
50131 #define S_LANE_12_MAPPING    0
50132 #define M_LANE_12_MAPPING    0x3fU
50136 #define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
50138 #define S_LANE_13_MAPPING    0
50139 #define M_LANE_13_MAPPING    0x3fU
50143 #define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
50145 #define S_LANE_14_MAPPING    0
50146 #define M_LANE_14_MAPPING    0x3fU
50150 #define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
50152 #define S_LANE_15_MAPPING    0
50153 #define M_LANE_15_MAPPING    0x3fU
50157 #define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
50159 #define S_LANE_16_MAPPING    0
50160 #define M_LANE_16_MAPPING    0x3fU
50164 #define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
50166 #define S_LANE_17_MAPPING    0
50167 #define M_LANE_17_MAPPING    0x3fU
50171 #define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
50173 #define S_LANE_18_MAPPING    0
50174 #define M_LANE_18_MAPPING    0x3fU
50178 #define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
50180 #define S_LANE_19_MAPPING    0
50181 #define M_LANE_19_MAPPING    0x3fU
50185 #define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
50186 #define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
50188 #define S_CORE_REVISION    0
50189 #define M_CORE_REVISION    0xffffU
50193 #define A_MAC_PORT_BEAN_CTL 0x2200
50211 #define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
50217 #define S_RS_FEC_BYPASS_CORRECTION    0
50221 #define A_MAC_PORT_BEAN_STATUS 0x2204
50247 #define S_LP_BEAN_ABILITY    0
50251 #define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
50269 #define S_RS_FEC_BYPASS_CORRECTION_ABILITY    0
50273 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
50284 #define M_PAUSE_ABILITY    0x7U
50289 #define M_ECHO_NONCE    0x1fU
50293 #define S_SELECTOR    0
50294 #define M_SELECTOR    0x1fU
50298 #define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
50300 #define S_RS_RS_FEC_CCW_LO    0
50301 #define M_RS_RS_FEC_CCW_LO    0xffffU
50305 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
50308 #define M_TECH_ABILITY_1    0x7ffU
50312 #define S_TX_NONCE    0
50313 #define M_TX_NONCE    0x1fU
50317 #define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
50319 #define S_RS_RS_FEC_CCW_HI    0
50320 #define M_RS_RS_FEC_CCW_HI    0xffffU
50324 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
50327 #define M_T5_FEC_ABILITY    0x3U
50331 #define S_TECH_ABILITY_2    0
50332 #define M_TECH_ABILITY_2    0x3fffU
50336 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
50338 #define S_RS_RS_FEC_NCCW_LO    0
50339 #define M_RS_RS_FEC_NCCW_LO    0xffffU
50343 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
50344 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
50346 #define S_RS_RS_FEC_NCCW_HI    0
50347 #define M_RS_RS_FEC_NCCW_HI    0xffffU
50351 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
50352 #define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
50354 #define S_PMA_MAPPING    0
50355 #define M_PMA_MAPPING    0xffU
50359 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
50360 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
50362 #define S_MS_COUNT    0
50363 #define M_MS_COUNT    0xffffU
50367 #define A_MAC_PORT_BEAN_XNP_0 0x2224
50385 #define S_MU    0
50386 #define M_MU    0x7ffU
50390 #define A_MAC_PORT_BEAN_XNP_1 0x2228
50392 #define S_UNFORMATED    0
50393 #define M_UNFORMATED    0xffffU
50397 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
50399 #define S_RS_FEC_SYMBLERR0_LO    0
50403 #define A_MAC_PORT_BEAN_XNP_2 0x222c
50404 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
50406 #define S_RS_FEC_SYMBLERR0_HI    0
50410 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
50411 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
50413 #define S_RS_FEC_SYMBLERR1_LO    0
50417 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
50418 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
50420 #define S_RS_FEC_SYMBLERR1_HI    0
50424 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
50425 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
50427 #define S_RS_FEC_SYMBLERR2_LO    0
50431 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
50461 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
50463 #define S_RS_FEC_SYMBLERR2_HI    0
50467 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
50468 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
50470 #define S_RS_FEC_SYMBLERR3_LO    0
50474 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
50475 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
50477 #define S_RS_FEC_SYMBLERR3_HI    0
50481 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
50482 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
50483 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
50484 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
50485 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
50486 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
50487 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
50488 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
50489 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
50490 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
50491 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
50492 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
50493 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
50494 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
50495 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
50496 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
50497 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
50498 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
50499 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
50500 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
50501 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
50502 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
50503 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
50504 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
50505 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
50506 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
50507 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
50508 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
50509 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
50510 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
50511 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
50512 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
50513 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
50514 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
50515 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
50516 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
50517 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
50518 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
50519 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
50520 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
50521 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
50522 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
50523 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
50524 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
50525 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
50526 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
50527 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
50537 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
50540 #define M_DESKEW_EMPTY    0xfU
50572 #define S_AMPS_LOCK    0
50573 #define M_AMPS_LOCK    0xfU
50577 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
50578 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
50580 #define S_RS_FEC_VENDOR_REVISION    0
50581 #define M_RS_FEC_VENDOR_REVISION    0xffffU
50585 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
50587 #define S_RS_FEC_VENDOR_TX_TEST_KEY    0
50588 #define M_RS_FEC_VENDOR_TX_TEST_KEY    0xffffU
50592 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
50594 #define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0
50595 #define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0xffffU
50599 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
50601 #define S_RS_FEC_VENDOR_TX_TEST_PATTERN    0
50602 #define M_RS_FEC_VENDOR_TX_TEST_PATTERN    0xffffU
50606 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
50608 #define S_RS_FEC_VENDOR_TX_TEST_TRIGGER    0
50609 #define M_RS_FEC_VENDOR_TX_TEST_TRIGGER    0xffffU
50613 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
50619 #define S_RESTART_TR    0
50623 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
50637 #define S_RX_STATUS    0
50641 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
50652 #define M_CP1_UPD    0x3U
50657 #define M_C0_UPD    0x3U
50661 #define S_CN1_UPD    0
50662 #define M_CN1_UPD    0x3U
50666 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
50673 #define M_CP1_STAT    0x3U
50678 #define M_C0_STAT    0x3U
50682 #define S_CN1_STAT    0
50683 #define M_CN1_STAT    0x3U
50687 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
50688 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
50689 #define A_MAC_PORT_FEC_ABILITY 0x2618
50695 #define S_ABILITY    0
50699 #define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
50705 #define S_BASE_R_FEC_ABILITY    0
50709 #define A_MAC_PORT_FEC_CONTROL 0x261c
50715 #define S_FEC_EN    0
50719 #define A_MAC_PORT_FEC_STATUS 0x2620
50725 #define S_FEC_LOCKED    0
50730 #define M_FEC_LOCKED0    0xfU
50734 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
50736 #define S_FEC_CERR_CNT_0    0
50737 #define M_FEC_CERR_CNT_0    0xffffU
50741 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
50742 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
50744 #define S_FEC_CERR_CNT_1    0
50745 #define M_FEC_CERR_CNT_1    0xffffU
50749 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
50750 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
50752 #define S_FEC_NCERR_CNT_0    0
50753 #define M_FEC_NCERR_CNT_0    0xffffU
50757 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
50759 #define S_FEC0_NCERR_CNT_0    0
50760 #define M_FEC0_NCERR_CNT_0    0xffffU
50764 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
50766 #define S_FEC_NCERR_CNT_1    0
50767 #define M_FEC_NCERR_CNT_1    0xffffU
50771 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
50773 #define S_FEC0_NCERR_CNT_1    0
50774 #define M_FEC0_NCERR_CNT_1    0xffffU
50778 #define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
50779 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
50780 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
50781 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
50782 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
50783 #define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
50784 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
50785 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
50786 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
50787 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
50788 #define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
50789 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
50790 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
50791 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
50792 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
50793 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
50796 #define M_T5_RXREQ_C2    0x3U
50801 #define M_T5_RXREQ_C1    0x3U
50805 #define S_T5_RXREQ_C0    0
50806 #define M_T5_RXREQ_C0    0x3U
50811 #define M_T5_RXREQ_C3    0x3U
50815 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
50822 #define M_T5_AE0_RXSTAT_C2    0x3U
50827 #define M_T5_AE0_RXSTAT_C1    0x3U
50831 #define S_T5_AE0_RXSTAT_C0    0
50832 #define M_T5_AE0_RXSTAT_C0    0x3U
50849 #define M_T5_AE0_RXSTAT_C3    0x3U
50853 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
50856 #define M_T5_TXREQ_C2    0x3U
50861 #define M_T5_TXREQ_C1    0x3U
50865 #define S_T5_TXREQ_C0    0
50866 #define M_T5_TXREQ_C0    0x3U
50875 #define M_T5_TXREQ_C3    0x3U
50879 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
50882 #define M_T5_TXSTAT_C2    0x3U
50887 #define M_T5_TXSTAT_C1    0x3U
50891 #define S_T5_TXSTAT_C0    0
50892 #define M_T5_TXSTAT_C0    0x3U
50897 #define M_T5_TXSTAT_C3    0x3U
50901 #define A_MAC_PORT_AE_REG_MODE 0x2a10
50912 #define M_SET_WAIT_TIMER    0x3U
50936 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
50937 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
50943 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
50944 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
50945 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
50952 #define M_T5_AE1_RXSTAT_C2    0x3U
50957 #define M_T5_AE1_RXSTAT_C1    0x3U
50961 #define S_T5_AE1_RXSTAT_C0    0
50962 #define M_T5_AE1_RXSTAT_C0    0x3U
50979 #define M_T5_AE1_RXSTAT_C3    0x3U
50983 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
50984 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
50985 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
50986 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
50987 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
50988 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
50989 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
50990 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
50997 #define M_T5_AE2_RXSTAT_C2    0x3U
51002 #define M_T5_AE2_RXSTAT_C1    0x3U
51006 #define S_T5_AE2_RXSTAT_C0    0
51007 #define M_T5_AE2_RXSTAT_C0    0x3U
51024 #define M_T5_AE2_RXSTAT_C3    0x3U
51028 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
51029 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
51030 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
51031 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
51032 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
51033 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
51034 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
51035 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
51042 #define M_T5_AE3_RXSTAT_C2    0x3U
51047 #define M_T5_AE3_RXSTAT_C1    0x3U
51051 #define S_T5_AE3_RXSTAT_C0    0
51052 #define M_T5_AE3_RXSTAT_C0    0x3U
51069 #define M_T5_AE3_RXSTAT_C3    0x3U
51073 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
51074 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
51075 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
51076 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
51077 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
51078 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
51079 #define A_MAC_PORT_AE_TX_DIS 0x2a80
51080 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
51081 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
51082 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
51083 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
51084 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
51085 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
51086 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
51087 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
51088 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
51089 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
51090 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
51091 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
51092 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
51093 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
51094 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
51095 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
51102 #define M_INIT_METH    0x3U
51107 #define M_CE_DECS    0xfU
51131 #define S_H1TEQ_GOAL    0
51132 #define M_H1TEQ_GOAL    0x7U
51137 #define M_T6_INIT_METH    0xfU
51142 #define M_INIT_CNT    0xfU
51150 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
51153 #define M_GAIN_TH    0x1fU
51165 #define S_AMIN_TH    0
51166 #define M_AMIN_TH    0xfU
51179 #define M_DPC_METH    0x3U
51187 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
51190 #define M_ACC_LIM    0xfU
51195 #define M_CNV_LIM    0xfU
51199 #define S_TOG_LIM    0
51200 #define M_TOG_LIM    0xfU
51204 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
51207 #define M_BOOT_LUT7    0xfU
51212 #define M_BOOT_LUT6    0xfU
51217 #define M_BOOT_LUT45    0xfU
51222 #define M_BOOT_LUT0123    0x3U
51231 #define M_BOOT_LUT5    0xfU
51235 #define A_MAC_PORT_AET_STATUS_0 0x2b10
51238 #define M_AET_STAT    0xfU
51243 #define M_NEU_STATE    0xfU
51247 #define S_CTRL_STATE    0
51248 #define M_CTRL_STATE    0x1fU
51253 #define M_CTRL_STAT    0x1fU
51258 #define M_T6_NEU_STATE    0xfU
51262 #define S_T6_CTRL_STATE    0
51263 #define M_T6_CTRL_STATE    0xfU
51267 #define A_MAC_PORT_AET_STATUS_20 0x2b14
51269 #define S_FRAME_LOCK_CNT    0
51270 #define M_FRAME_LOCK_CNT    0x7U
51274 #define A_MAC_PORT_AET_LIMITS0 0x2b18
51276 #define S_DPC_TIME_LIM    0
51277 #define M_DPC_TIME_LIM    0x3U
51281 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
51284 #define M_T6_INIT_METH    0xfU
51288 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
51289 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
51290 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
51291 #define A_MAC_PORT_AET_STATUS_1 0x2b30
51294 #define M_T6_NEU_STATE    0xfU
51298 #define S_T6_CTRL_STATE    0
51299 #define M_T6_CTRL_STATE    0xfU
51303 #define A_MAC_PORT_AET_STATUS_21 0x2b34
51304 #define A_MAC_PORT_AET_LIMITS1 0x2b38
51305 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
51308 #define M_T6_INIT_METH    0xfU
51312 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
51313 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
51314 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
51315 #define A_MAC_PORT_AET_STATUS_2 0x2b50
51318 #define M_T6_NEU_STATE    0xfU
51322 #define S_T6_CTRL_STATE    0
51323 #define M_T6_CTRL_STATE    0xfU
51327 #define A_MAC_PORT_AET_STATUS_22 0x2b54
51328 #define A_MAC_PORT_AET_LIMITS2 0x2b58
51329 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
51332 #define M_T6_INIT_METH    0xfU
51336 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
51337 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
51338 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
51339 #define A_MAC_PORT_AET_STATUS_3 0x2b70
51342 #define M_T6_NEU_STATE    0xfU
51346 #define S_T6_CTRL_STATE    0
51347 #define M_T6_CTRL_STATE    0xfU
51351 #define A_MAC_PORT_AET_STATUS_23 0x2b74
51352 #define A_MAC_PORT_AET_LIMITS3 0x2b78
51353 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
51354 #define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
51355 #define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
51361 #define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
51362 #define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
51363 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
51369 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
51370 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
51371 #define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
51372 #define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
51373 #define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
51374 #define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
51375 #define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
51376 #define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
51377 #define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
51378 #define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
51392 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
51407 #define M_T5_TX_CFGPTR    0x3U
51424 #define M_T5_TX_PLLSEL    0x3U
51444 #define S_T5_TX_RTSEL    0
51445 #define M_T5_TX_RTSEL    0x3U
51458 #define M_T6_T5_TX_BWSEL    0x3U
51462 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
51465 #define M_SPSEL    0x7U
51493 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
51515 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
51526 #define M_T5SLEW    0x3U
51530 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
51548 #define S_T5REGAMP    0
51549 #define M_T5REGAMP    0x3U
51553 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
51564 #define M_RPOS    0x3fU
51572 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
51575 #define M_CALSSTN    0x7U
51579 #define S_CALSSTP    0
51580 #define M_CALSSTP    0x7U
51585 #define M_T6_CALSSTN    0x3fU
51589 #define S_T6_CALSSTP    0
51590 #define M_T6_CALSSTP    0x3fU
51594 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
51596 #define S_DRTOL    0
51597 #define M_DRTOL    0x1fU
51602 #define M_T6_DRTOL    0x7U
51606 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
51608 #define S_T5NXTT0    0
51609 #define M_T5NXTT0    0x1fU
51613 #define S_T6_NXTT0    0
51614 #define M_T6_NXTT0    0x3fU
51618 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
51620 #define S_T5NXTT1    0
51621 #define M_T5NXTT1    0x3fU
51625 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
51627 #define S_T5NXTT2    0
51628 #define M_T5NXTT2    0x3fU
51632 #define S_T6_NXTT2    0
51633 #define M_T6_NXTT2    0x3fU
51637 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
51639 #define S_NXTT3    0
51640 #define M_NXTT3    0x3fU
51644 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
51646 #define S_T5TXPWR    0
51647 #define M_T5TXPWR    0x3fU
51651 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
51653 #define S_NXTPOL    0
51654 #define M_NXTPOL    0x7U
51658 #define S_T6_NXTPOL    0
51659 #define M_T6_NXTPOL    0xfU
51663 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
51674 #define M_SASCMD    0x3U
51679 #define M_T6_C0UPDT    0x3U
51684 #define M_C3UPDT    0x3U
51689 #define M_T6_C2UPDT    0x3U
51693 #define S_T6_C1UPDT    0
51694 #define M_T6_C1UPDT    0x3U
51698 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
51701 #define M_T6_C0STAT    0x3U
51706 #define M_C3STAT    0x3U
51711 #define M_T6_C2STAT    0x3U
51715 #define S_T6_C1STAT    0
51716 #define M_T6_C1STAT    0x3U
51720 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51721 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
51723 #define S_AETAP0    0
51724 #define M_AETAP0    0x7fU
51728 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51730 #define S_T5NIDAC1    0
51731 #define M_T5NIDAC1    0x3fU
51735 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
51737 #define S_AETAP1    0
51738 #define M_AETAP1    0x7fU
51742 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51744 #define S_T5NIDAC2    0
51745 #define M_T5NIDAC2    0x3fU
51749 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
51751 #define S_AETAP2    0
51752 #define M_AETAP2    0x7fU
51756 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
51758 #define S_AETAP3    0
51759 #define M_AETAP3    0x7fU
51763 #define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
51766 #define M_ATUNEN    0xffU
51770 #define S_ATUNEP    0
51771 #define M_ATUNEP    0xffU
51775 #define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
51781 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
51782 #define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
51785 #define M_AS4X7    0x3U
51790 #define M_AS4X6    0x3U
51795 #define M_AS4X5    0x3U
51800 #define M_AS4X4    0x3U
51805 #define M_AS4X3    0x3U
51810 #define M_AS4X2    0x3U
51815 #define M_AS4X1    0x3U
51819 #define S_AS4X0    0
51820 #define M_AS4X0    0x3U
51824 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
51826 #define S_T5AIDAC1    0
51827 #define M_T5AIDAC1    0x3fU
51831 #define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
51834 #define M_AS2X3    0x3U
51839 #define M_AS2X2    0x3U
51844 #define M_AS2X1    0x3U
51848 #define S_AS2X0    0
51849 #define M_AS2X0    0x3U
51853 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
51854 #define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
51857 #define M_AS1X7    0x3U
51862 #define M_AS1X6    0x3U
51867 #define M_AS1X5    0x3U
51872 #define M_AS1X4    0x3U
51877 #define M_AS1X3    0x3U
51882 #define M_AS1X2    0x3U
51887 #define M_AS1X1    0x3U
51891 #define S_AS1X0    0
51892 #define M_AS1X0    0x3U
51896 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
51898 #define S_AT4X    0
51899 #define M_AT4X    0xffU
51903 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
51906 #define M_MAINSC    0x3fU
51910 #define S_POSTSC    0
51911 #define M_POSTSC    0x3fU
51915 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
51918 #define M_AT2X    0xfU
51922 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
51924 #define S_PRESC    0
51925 #define M_PRESC    0x1fU
51929 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
51931 #define S_ATSIGN    0
51932 #define M_ATSIGN    0xfU
51936 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
51937 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
51940 #define M_T5XADDR    0x1fU
51944 #define S_T5XWR    0
51949 #define M_T6_XADDR    0x1fU
51953 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
51955 #define S_XDAT10    0
51956 #define M_XDAT10    0xffffU
51960 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
51962 #define S_XDAT32    0
51963 #define M_XDAT32    0xffffU
51967 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
51969 #define S_XDAT4    0
51970 #define M_XDAT4    0xffU
51974 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
51976 #define S_XDAT54    0
51977 #define M_XDAT54    0xffffU
51981 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
51996 #define M_DCCOFFSET    0x1fU
52001 #define M_DCCSTEP    0x3U
52006 #define M_DCCASTEP    0x1fU
52010 #define S_DCCAEN    0
52014 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
52016 #define S_XDAT76    0
52017 #define M_XDAT76    0xffffU
52021 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
52036 #define M_DCCSIGN    0x3U
52041 #define M_DCCAMP    0x7fU
52045 #define S_DCCOEN    0
52049 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
52052 #define M_DCCASIGN    0x3U
52056 #define S_DCCAAMP    0
52057 #define M_DCCAAMP    0x7fU
52061 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
52063 #define S_DCCTIMEOUTVAL    0
52064 #define M_DCCTIMEOUTVAL    0xffffU
52068 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
52075 #define M_LPITERM    0x3U
52079 #define S_LPIPRCD    0
52080 #define M_LPIPRCD    0x3U
52084 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
52087 #define M_T6_DCCTIMEEN    0x3U
52092 #define M_T6_DCCLOCK    0x3U
52097 #define M_T6_DCCOFFSET    0x7U
52102 #define M_TX_LINKA_DCCSTEP_CTL    0x3U
52106 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
52107 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
52108 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
52109 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
52111 #define S_OSIGN    0
52112 #define M_OSIGN    0xfU
52116 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
52119 #define M_OS4X7    0x3U
52124 #define M_OS4X6    0x3U
52129 #define M_OS4X5    0x3U
52134 #define M_OS4X4    0x3U
52139 #define M_OS4X3    0x3U
52144 #define M_OS4X2    0x3U
52149 #define M_OS4X1    0x3U
52153 #define S_OS4X0    0
52154 #define M_OS4X0    0x3U
52158 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
52161 #define M_OS2X3    0x3U
52166 #define M_OS2X2    0x3U
52171 #define M_OS2X1    0x3U
52175 #define S_OS2X0    0
52176 #define M_OS2X0    0x3U
52180 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
52183 #define M_OS1X7    0x3U
52188 #define M_OS1X6    0x3U
52193 #define M_OS1X5    0x3U
52198 #define M_OS1X4    0x3U
52203 #define M_OS1X3    0x3U
52208 #define M_OS1X2    0x3U
52213 #define M_OS1X1    0x3U
52217 #define S_OS1X0    0
52218 #define M_OS1X0    0x3U
52222 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
52224 #define S_OT4X    0
52225 #define M_OT4X    0xffU
52229 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
52231 #define S_OT2X    0
52232 #define M_OT2X    0xfU
52236 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
52238 #define S_OT1X    0
52239 #define M_OT1X    0xffU
52243 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
52258 #define M_TUNEBIT    0x7U
52263 #define M_DATAPOS    0x3U
52268 #define M_SEGSEL    0x1fU
52273 #define M_TAPSEL    0x3U
52277 #define S_DATASIGN    0
52281 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
52287 #define S_SDOVRD    0
52288 #define M_SDOVRD    0xffU
52292 #define S_T6_SDOVRD    0
52293 #define M_T6_SDOVRD    0xffffU
52297 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
52300 #define M_SLEWCODE    0x3U
52304 #define S_ASEGEN    0
52308 #define S_WCNT    0
52309 #define M_WCNT    0x3ffU
52313 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
52320 #define M_AECMD1312    0x3U
52324 #define S_AECMD70    0
52325 #define M_AECMD70    0xffU
52329 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
52332 #define M_C48DIVCTL    0x7U
52337 #define M_RATEDIVCTL    0x7U
52358 #define M_JTAGAMPL    0x3U
52370 #define S_OBS    0
52386 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
52393 #define M_T6_T5_TX_BWSEL    0x3U
52397 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
52403 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
52404 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
52405 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
52406 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
52407 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
52410 #define M_T6_CALSSTN    0x3fU
52414 #define S_T6_CALSSTP    0
52415 #define M_T6_CALSSTP    0x3fU
52419 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
52422 #define M_T6_DRTOL    0x7U
52426 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
52428 #define S_T6_NXTT0    0
52429 #define M_T6_NXTT0    0x3fU
52433 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
52434 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
52436 #define S_T6_NXTT2    0
52437 #define M_T6_NXTT2    0x3fU
52441 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
52442 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
52443 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
52445 #define S_T6_NXTPOL    0
52446 #define M_T6_NXTPOL    0xfU
52450 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
52453 #define M_T6_C0UPDT    0x3U
52458 #define M_T6_C2UPDT    0x3U
52462 #define S_T6_C1UPDT    0
52463 #define M_T6_C1UPDT    0x3U
52467 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
52470 #define M_T6_C0STAT    0x3U
52475 #define M_T6_C2STAT    0x3U
52479 #define S_T6_C1STAT    0
52480 #define M_T6_C1STAT    0x3U
52484 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52485 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
52486 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52487 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
52488 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52489 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
52490 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
52491 #define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
52492 #define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
52493 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
52494 #define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
52495 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
52496 #define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
52497 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
52498 #define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
52499 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
52500 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
52501 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
52502 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
52503 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
52504 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
52505 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
52508 #define M_T6_XADDR    0x1fU
52512 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
52513 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
52514 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
52515 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
52516 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
52517 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
52518 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
52519 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
52520 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
52521 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
52522 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
52525 #define M_T6_DCCTIMEEN    0x3U
52530 #define M_T6_DCCLOCK    0x3U
52535 #define M_T6_DCCOFFSET    0x7U
52540 #define M_TX_LINKB_DCCSTEP_CTL    0x3U
52544 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
52545 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
52546 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
52547 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
52548 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
52549 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
52550 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
52551 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
52552 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
52553 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
52554 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
52555 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
52557 #define S_T6_SDOVRD    0
52558 #define M_T6_SDOVRD    0xffffU
52562 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
52563 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
52564 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
52570 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
52585 #define M_T5_RX_CFGPTR    0x3U
52602 #define M_T5_RX_PLLSEL    0x3U
52607 #define M_T5_RX_DMSEL    0x3U
52612 #define M_T5_RX_BWSEL    0x3U
52616 #define S_T5_RX_RTSEL    0
52617 #define M_T5_RX_RTSEL    0x3U
52625 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
52651 #define S_PATSEL    0
52652 #define M_PATSEL    0x7U
52661 #define M_PPOL    0x3U
52666 #define M_PCLKSEL    0x3U
52670 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
52684 #define S_SSCEN    0
52688 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
52691 #define M_H1ANOFST    0xfU
52696 #define M_T6_TMSCAL    0x3U
52708 #define S_T6_PHOFFS    0
52709 #define M_T6_PHOFFS    0x3fU
52713 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
52715 #define S_ROT00    0
52716 #define M_ROT00    0x3fU
52721 #define M_ROTA    0x3fU
52725 #define S_ROTD    0
52726 #define M_ROTD    0x3fU
52730 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
52733 #define M_FREQFW    0xffU
52741 #define S_ROTE    0
52742 #define M_ROTE    0x3fU
52746 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
52749 #define M_RAOFFF    0xfU
52753 #define S_RAOFF    0
52754 #define M_RAOFF    0x1fU
52758 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
52761 #define M_RBOOFF    0x1fU
52766 #define M_RBEOFF    0x1fU
52770 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
52773 #define M_T6_SPIFMT    0xfU
52777 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
52780 #define M_T5BYTE1    0xffU
52784 #define S_T5BYTE0    0
52785 #define M_T5BYTE0    0xffU
52789 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
52792 #define M_T5_RX_SMODE    0x7U
52805 #define M_T5_RX_ASAMPQ    0x7U
52809 #define S_T5_RX_ASAMP    0
52810 #define M_T5_RX_ASAMP    0x7U
52819 #define M_RASEL    0x7U
52823 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
52834 #define M_T6_PEAK    0x1fU
52838 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
52844 #define S_T5VGAIN    0
52845 #define M_T5VGAIN    0x1fU
52862 #define M_FH1AFLTR    0x3U
52867 #define M_WGAIN    0x3U
52875 #define S_T6_T5VGAIN    0
52876 #define M_T6_T5VGAIN    0x7fU
52880 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
52881 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
52884 #define M_IQSEP    0x1fU
52889 #define M_DUTYQ    0x1fU
52893 #define S_DUTYI    0
52894 #define M_DUTYI    0x1fU
52898 #define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
52901 #define M_PMCFG    0x3U
52905 #define S_PMOFFTIME    0
52906 #define M_PMOFFTIME    0x3fU
52910 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
52917 #define M_SERVREF    0x7U
52921 #define S_IQAMP    0
52922 #define M_IQAMP    0x1fU
52926 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
52929 #define M_DTHR    0x3fU
52933 #define S_SNUL    0
52934 #define M_SNUL    0x1fU
52938 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
52939 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
52965 #define S_DASEL    0
52966 #define M_DASEL    0x7U
52970 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
52971 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
52972 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
52973 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
52984 #define M_ADAC2    0xffU
52988 #define S_ADAC1    0
52989 #define M_ADAC1    0xffU
52993 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
53000 #define M_ACCPLGAIN    0x7U
53005 #define M_ACCPLREF    0x3U
53010 #define M_ACCPLSTEP    0x3U
53015 #define M_ACCPLASTEP    0x1fU
53019 #define S_FACCPL    0
53023 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
53033 #define S_ACCPLBIAS    0
53034 #define M_ACCPLBIAS    0xffU
53038 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
53041 #define M_H1O2    0x3fU
53045 #define S_H1E2    0
53046 #define M_H1E2    0x3fU
53050 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
53052 #define S_H123CH    0
53053 #define M_H123CH    0x3fU
53057 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
53060 #define M_H1O3    0x3fU
53064 #define S_H1E3    0
53065 #define M_H1E3    0x3fU
53069 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
53072 #define M_H1OX    0x3fU
53076 #define S_H1EX    0
53077 #define M_H1EX    0x3fU
53081 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
53084 #define M_H1O4    0x3fU
53088 #define S_H1E4    0
53089 #define M_H1E4    0x3fU
53093 #define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
53100 #define M_UNPKPKA    0x3fU
53104 #define S_UNPKVGA    0
53105 #define M_UNPKVGA    0x3U
53109 #define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
53120 #define M_OVRTAILS    0x3U
53125 #define M_OVRTAILV    0x7U
53145 #define S_CDRANLGSW    0
53146 #define M_CDRANLGSW    0x3U
53150 #define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
53153 #define M_PFLAG    0x3U
53157 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
53183 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
53189 #define S_T6_ODEC    0
53190 #define M_T6_ODEC    0xfU
53194 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
53248 #define S_T5OCCMP    0
53264 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
53270 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
53308 #define S_FDQCC    0
53344 #define S_FQCC    0
53348 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
53355 #define M_LOFE2S_READONLY    0x3U
53360 #define M_LOFE2    0x3fU
53372 #define S_LOFE1    0
53373 #define M_LOFE1    0x3fU
53377 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
53384 #define M_DCDIND    0x7U
53389 #define M_DCCIND    0x3U
53397 #define S_LOFCH    0
53398 #define M_LOFCH    0x1fU
53402 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
53413 #define M_LOFO2    0x3fU
53425 #define S_LOFO1    0
53426 #define M_LOFO1    0x3fU
53430 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
53433 #define M_LOFU    0x7fU
53437 #define S_LOFL    0
53438 #define M_LOFL    0x7fU
53442 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
53453 #define M_LOFE    0x3fU
53465 #define S_LOFE3    0
53466 #define M_LOFE3    0x3fU
53470 #define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
53481 #define M_HBISTSP    0x7U
53501 #define S_HSEL    0
53502 #define M_HSEL    0xfU
53506 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
53517 #define M_LOFO4    0x3fU
53529 #define S_LOFO3    0
53530 #define M_LOFO3    0x3fU
53534 #define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
53549 #define M_ACCIND    0x7U
53553 #define S_ACCRD    0
53554 #define M_ACCRD    0xffU
53558 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
53569 #define M_T5E1AMP    0x3fU
53581 #define S_T5E0AMP    0
53582 #define M_T5E0AMP    0x3fU
53586 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
53597 #define M_T5LFSEL    0x7U
53601 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
53616 #define M_LFTGT    0x1fU
53632 #define S_LCURR    0
53633 #define M_LCURR    0x1fU
53637 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
53648 #define M_OFFAMP    0x1fU
53657 #define M_OFFSN    0x3U
53661 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
53687 #define S_T5_RX_VTERM    0
53688 #define M_T5_RX_VTERM    0x3U
53724 #define S_RX_LINKANLGSW    0
53725 #define M_RX_LINKANLGSW    0x7fU
53729 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
53732 #define M_ISTRIMS    0x3U
53737 #define M_ISTRIM    0x3fU
53749 #define S_INTDAC    0
53750 #define M_INTDAC    0x3fU
53755 #define M_INTDACEGS    0x7U
53760 #define M_INTDACE    0x1fU
53765 #define M_INTDACGS    0x3U
53769 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
53772 #define M_MINWDTH    0x1fU
53776 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
53779 #define M_T5SMQM    0x7U
53784 #define M_T5SMQ    0xffU
53789 #define M_T5EMMD    0x3U
53801 #define S_T5EMEN    0
53806 #define M_SMQM    0x7U
53811 #define M_SMQ    0xffU
53816 #define M_T6_EMMD    0x3U
53828 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
53835 #define M_EMCNT    0xffU
53847 #define S_EMCEN    0
53859 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
53869 #define S_APDF    0
53870 #define M_APDF    0xfffU
53874 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
53876 #define S_SM0LEN    0
53877 #define M_SM0LEN    0x7fffU
53881 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
53943 #define S_FPRBSOFF    0
53947 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
53950 #define M_H_EN    0xfffU
53954 #define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
53956 #define S_RX_LINKA_INDEX_DFE_TC    0
53957 #define M_RX_LINKA_INDEX_DFE_TC    0xfU
53961 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
53962 #define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
53964 #define S_RX_LINKA_INDEX_DFE_TAP    0
53965 #define M_RX_LINKA_INDEX_DFE_TAP    0xfU
53969 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
53987 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
54005 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
54008 #define M_H4OGS    0x3U
54021 #define M_H4EGS    0x3U
54033 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
54036 #define M_H5OGS    0x3U
54049 #define M_H5EGS    0x3U
54061 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
54064 #define M_H7GS    0x3U
54077 #define M_H7MAG    0xfU
54082 #define M_H6GS    0x3U
54094 #define S_H6MAG    0
54095 #define M_H6MAG    0xfU
54099 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
54102 #define M_H9GS    0x3U
54115 #define M_H9MAG    0xfU
54120 #define M_H8GS    0x3U
54132 #define S_H8MAG    0
54133 #define M_H8MAG    0xfU
54137 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
54140 #define M_H11GS    0x3U
54153 #define M_H11MAG    0xfU
54158 #define M_H10GS    0x3U
54170 #define S_H10MAG    0
54171 #define M_H10MAG    0xfU
54175 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
54178 #define M_H12GS    0x3U
54190 #define S_H12MAG    0
54191 #define M_H12MAG    0xfU
54195 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
54225 #define S_QCCCMP    0
54229 #define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
54236 #define M_CSIND    0x3U
54240 #define S_CSVAL    0
54241 #define M_CSVAL    0x7U
54245 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
54260 #define M_DCDSTEP    0x3U
54277 #define M_DCDSIGN    0x3U
54281 #define S_DCDAMP    0
54282 #define M_DCDAMP    0x3fU
54286 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
54289 #define M_PRBSMODE    0x3U
54294 #define M_RX_LINKA_DCCSTEP_RXCTL    0x3U
54306 #define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
54321 #define M_QCCSTEP    0x3U
54334 #define M_QCCSIGN    0x3U
54338 #define S_QCDAMP    0
54339 #define M_QCDAMP    0x3fU
54343 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
54369 #define S_ACJZNT    0
54373 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
54379 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
54421 #define S_MTHOLD    0
54441 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
54442 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
54443 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
54444 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
54447 #define M_T6_TMSCAL    0x3U
54459 #define S_T6_PHOFFS    0
54460 #define M_T6_PHOFFS    0x3fU
54464 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
54465 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
54466 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
54467 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
54468 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
54471 #define M_T6_SPIFMT    0xfU
54475 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
54476 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
54477 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
54484 #define M_T6_PEAK    0x1fU
54488 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
54490 #define S_T6_T5VGAIN    0
54491 #define M_T6_T5VGAIN    0x7fU
54495 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
54496 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
54497 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
54498 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
54499 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
54500 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
54501 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
54502 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
54503 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
54504 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
54505 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
54506 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
54507 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
54508 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
54509 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
54510 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
54511 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
54512 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
54513 #define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
54514 #define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
54515 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
54516 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
54517 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
54519 #define S_T6_ODEC    0
54520 #define M_T6_ODEC    0xfU
54524 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
54530 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
54531 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
54532 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
54533 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
54534 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
54535 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
54536 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
54537 #define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
54538 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
54539 #define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
54545 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
54546 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
54547 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
54548 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
54549 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
54550 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
54551 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
54552 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
54555 #define M_T6_EMMD    0x3U
54567 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
54568 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
54569 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
54570 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
54571 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
54572 #define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
54574 #define S_RX_LINKB_INDEX_DFE_TC    0
54575 #define M_RX_LINKB_INDEX_DFE_TC    0xfU
54579 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
54580 #define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
54582 #define S_RX_LINKB_INDEX_DFE_TAP    0
54583 #define M_RX_LINKB_INDEX_DFE_TAP    0xfU
54587 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
54588 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
54589 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
54590 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
54591 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
54592 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
54593 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
54594 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
54595 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
54596 #define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
54597 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
54598 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
54601 #define M_RX_LINKB_DCCSTEP_RXCTL    0x3U
54609 #define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
54610 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
54611 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
54612 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
54613 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
54620 #define M_T6_T5_TX_BWSEL    0x3U
54624 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
54630 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
54631 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
54632 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
54633 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
54634 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
54637 #define M_T6_CALSSTN    0x3fU
54641 #define S_T6_CALSSTP    0
54642 #define M_T6_CALSSTP    0x3fU
54646 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
54649 #define M_T6_DRTOL    0x7U
54653 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
54655 #define S_T6_NXTT0    0
54656 #define M_T6_NXTT0    0x3fU
54660 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
54661 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
54663 #define S_T6_NXTT2    0
54664 #define M_T6_NXTT2    0x3fU
54668 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
54669 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
54670 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
54672 #define S_T6_NXTPOL    0
54673 #define M_T6_NXTPOL    0xfU
54677 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
54680 #define M_T6_C0UPDT    0x3U
54685 #define M_T6_C2UPDT    0x3U
54689 #define S_T6_C1UPDT    0
54690 #define M_T6_C1UPDT    0x3U
54694 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
54697 #define M_T6_C0STAT    0x3U
54702 #define M_T6_C2STAT    0x3U
54706 #define S_T6_C1STAT    0
54707 #define M_T6_C1STAT    0x3U
54711 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54712 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
54713 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54714 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
54715 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54716 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
54717 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
54718 #define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
54719 #define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
54720 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
54721 #define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
54722 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
54723 #define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
54724 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
54725 #define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
54726 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
54727 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
54728 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
54729 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
54730 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
54731 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
54732 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
54735 #define M_T6_XADDR    0x1fU
54739 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
54740 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
54741 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
54742 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
54743 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
54744 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
54745 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
54746 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
54747 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
54748 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
54749 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
54752 #define M_T6_DCCTIMEEN    0x3U
54757 #define M_T6_DCCLOCK    0x3U
54762 #define M_T6_DCCOFFSET    0x7U
54767 #define M_TX_LINKC_DCCSTEP_CTL    0x3U
54771 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
54772 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
54773 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
54774 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
54775 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
54776 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
54777 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
54778 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
54779 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
54780 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
54781 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
54782 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
54784 #define S_T6_SDOVRD    0
54785 #define M_T6_SDOVRD    0xffffU
54789 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
54790 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
54791 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
54797 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
54804 #define M_T6_T5_TX_BWSEL    0x3U
54808 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
54814 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
54815 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
54816 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
54817 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
54818 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
54821 #define M_T6_CALSSTN    0x3fU
54825 #define S_T6_CALSSTP    0
54826 #define M_T6_CALSSTP    0x3fU
54830 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
54833 #define M_T6_DRTOL    0x7U
54837 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
54839 #define S_T6_NXTT0    0
54840 #define M_T6_NXTT0    0x3fU
54844 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
54845 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
54847 #define S_T6_NXTT2    0
54848 #define M_T6_NXTT2    0x3fU
54852 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
54853 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
54854 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
54856 #define S_T6_NXTPOL    0
54857 #define M_T6_NXTPOL    0xfU
54861 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
54864 #define M_T6_C0UPDT    0x3U
54869 #define M_T6_C2UPDT    0x3U
54873 #define S_T6_C1UPDT    0
54874 #define M_T6_C1UPDT    0x3U
54878 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
54881 #define M_T6_C0STAT    0x3U
54886 #define M_T6_C2STAT    0x3U
54890 #define S_T6_C1STAT    0
54891 #define M_T6_C1STAT    0x3U
54895 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54896 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
54897 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54898 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
54899 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54900 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
54901 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
54902 #define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
54903 #define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
54904 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
54905 #define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
54906 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
54907 #define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
54908 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
54909 #define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
54910 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
54911 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
54912 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
54913 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
54914 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
54915 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
54916 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
54919 #define M_T6_XADDR    0x1fU
54923 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
54924 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
54925 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
54926 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
54927 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
54928 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
54929 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
54930 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
54931 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
54932 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
54933 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
54936 #define M_T6_DCCTIMEEN    0x3U
54941 #define M_T6_DCCLOCK    0x3U
54946 #define M_T6_DCCOFFSET    0x7U
54951 #define M_TX_LINKD_DCCSTEP_CTL    0x3U
54955 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
54956 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
54957 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
54958 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
54959 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
54960 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
54961 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
54962 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
54963 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
54964 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
54965 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
54966 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
54968 #define S_T6_SDOVRD    0
54969 #define M_T6_SDOVRD    0xffffU
54973 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
54974 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
54975 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
54981 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
54982 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
54983 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
54984 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
54987 #define M_T6_TMSCAL    0x3U
54999 #define S_T6_PHOFFS    0
55000 #define M_T6_PHOFFS    0x3fU
55004 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
55005 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
55006 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
55007 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
55008 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
55011 #define M_T6_SPIFMT    0xfU
55015 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
55016 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
55017 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
55024 #define M_T6_PEAK    0x1fU
55028 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
55030 #define S_T6_T5VGAIN    0
55031 #define M_T6_T5VGAIN    0x7fU
55035 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
55036 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
55037 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
55038 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
55039 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
55040 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
55041 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
55042 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
55043 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
55044 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
55045 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
55046 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
55047 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
55048 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
55049 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
55050 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
55051 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
55052 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
55053 #define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
55054 #define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
55055 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
55056 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
55057 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
55059 #define S_T6_ODEC    0
55060 #define M_T6_ODEC    0xfU
55064 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
55070 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
55071 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
55072 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
55073 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
55074 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
55075 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
55076 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
55077 #define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
55078 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
55079 #define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
55085 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
55086 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
55087 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
55088 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
55089 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
55090 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
55091 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
55092 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
55095 #define M_T6_EMMD    0x3U
55107 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
55108 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
55109 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
55110 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
55111 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
55112 #define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
55114 #define S_RX_LINKC_INDEX_DFE_TC    0
55115 #define M_RX_LINKC_INDEX_DFE_TC    0xfU
55119 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
55120 #define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
55122 #define S_RX_LINKC_INDEX_DFE_TAP    0
55123 #define M_RX_LINKC_INDEX_DFE_TAP    0xfU
55127 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
55128 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
55129 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
55130 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
55131 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
55132 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
55133 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
55134 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
55135 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
55136 #define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
55137 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
55138 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
55141 #define M_RX_LINKC_DCCSTEP_RXCTL    0x3U
55149 #define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
55150 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
55151 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
55152 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
55153 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
55154 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
55155 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
55156 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
55159 #define M_T6_TMSCAL    0x3U
55171 #define S_T6_PHOFFS    0
55172 #define M_T6_PHOFFS    0x3fU
55176 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
55177 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
55178 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
55179 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
55180 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
55183 #define M_T6_SPIFMT    0xfU
55187 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
55188 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
55189 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
55196 #define M_T6_PEAK    0x1fU
55200 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
55202 #define S_T6_T5VGAIN    0
55203 #define M_T6_T5VGAIN    0x7fU
55207 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
55208 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
55209 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
55210 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
55211 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
55212 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
55213 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
55214 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
55215 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
55216 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
55217 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
55218 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
55219 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
55220 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
55221 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
55222 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
55223 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
55224 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
55225 #define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
55226 #define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
55227 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
55228 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
55229 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
55231 #define S_T6_ODEC    0
55232 #define M_T6_ODEC    0xfU
55236 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
55242 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
55243 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
55244 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
55245 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
55246 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
55247 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
55248 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
55249 #define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
55250 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
55251 #define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
55257 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
55258 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
55259 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
55260 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
55261 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
55262 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
55263 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
55264 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
55267 #define M_T6_EMMD    0x3U
55279 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
55280 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
55281 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
55282 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
55283 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
55284 #define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
55286 #define S_RX_LINKD_INDEX_DFE_TC    0
55287 #define M_RX_LINKD_INDEX_DFE_TC    0xfU
55291 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
55292 #define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
55294 #define S_RX_LINKD_INDEX_DFE_TAP    0
55295 #define M_RX_LINKD_INDEX_DFE_TAP    0xfU
55299 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
55300 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
55301 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
55302 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
55303 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
55304 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
55305 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
55306 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
55307 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
55308 #define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
55309 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
55310 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
55313 #define M_RX_LINKD_DCCSTEP_RXCTL    0x3U
55321 #define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
55322 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
55323 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
55324 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
55325 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
55326 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
55328 #define S_T5BGCTL    0
55329 #define M_T5BGCTL    0xfU
55333 #define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
55335 #define S_REFSEL    0
55336 #define M_REFSEL    0x7U
55340 #define A_MAC_PORT_REFISINK_CONTROL 0x3858
55342 #define S_REFISINK    0
55343 #define M_REFISINK    0x3fU
55347 #define A_MAC_PORT_REFISRC_CONTROL 0x385c
55349 #define S_REFISRC    0
55350 #define M_REFISRC    0x3fU
55354 #define A_MAC_PORT_REFVREG_CONTROL 0x3860
55356 #define S_REFVREG    0
55357 #define M_REFVREG    0x3fU
55361 #define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
55367 #define S_VBGENDOC    0
55368 #define M_VBGENDOC    0x3U
55372 #define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
55374 #define S_VREFTUNE    0
55375 #define M_VREFTUNE    0xfU
55379 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
55401 #define S_RCRST    0
55405 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
55419 #define S_RCAL_RESET    0
55423 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
55429 #define S_RCCOMP    0
55433 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
55447 #define S_RCALCOMP    0
55451 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
55453 #define S_RESREG2    0
55454 #define M_RESREG2    0xffU
55458 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
55460 #define S_T6_RESREG2    0
55461 #define M_T6_RESREG2    0x3fU
55465 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
55467 #define S_RESREG3    0
55468 #define M_RESREG3    0xffU
55472 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
55474 #define S_T6_RESREG3    0
55475 #define M_T6_RESREG3    0x3fU
55479 #define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
55494 #define M_ISVAL    0x3U
55499 #define M_GTORLT    0x3U
55503 #define S_INEQ    0
55507 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
55509 #define S_LLIM    0
55510 #define M_LLIM    0xffffU
55514 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
55516 #define S_LMSK    0
55517 #define M_LMSK    0xffffU
55521 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
55523 #define S_HLIM    0
55524 #define M_HLIM    0xffffU
55528 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
55530 #define S_HMSK    0
55531 #define M_HMSK    0xffffU
55535 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
55565 #define S_HSSACJAC    0
55569 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
55595 #define S_MACROTEST    0
55599 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
55606 #define M_T6_T5_TX_BWSEL    0x3U
55610 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
55616 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
55617 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
55618 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
55619 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
55620 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
55623 #define M_T6_CALSSTN    0x3fU
55627 #define S_T6_CALSSTP    0
55628 #define M_T6_CALSSTP    0x3fU
55632 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
55635 #define M_T6_DRTOL    0x7U
55639 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
55641 #define S_T6_NXTT0    0
55642 #define M_T6_NXTT0    0x3fU
55646 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
55647 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
55649 #define S_T6_NXTT2    0
55650 #define M_T6_NXTT2    0x3fU
55654 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
55655 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
55656 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
55658 #define S_T6_NXTPOL    0
55659 #define M_T6_NXTPOL    0xfU
55663 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
55666 #define M_T6_C0UPDT    0x3U
55671 #define M_T6_C2UPDT    0x3U
55675 #define S_T6_C1UPDT    0
55676 #define M_T6_C1UPDT    0x3U
55680 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
55683 #define M_T6_C0STAT    0x3U
55688 #define M_T6_C2STAT    0x3U
55692 #define S_T6_C1STAT    0
55693 #define M_T6_C1STAT    0x3U
55697 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55698 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
55699 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55700 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
55701 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55702 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
55703 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
55704 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
55705 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
55706 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
55707 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
55708 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
55709 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
55710 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
55711 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
55712 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
55713 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
55714 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
55715 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
55716 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
55717 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
55718 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
55721 #define M_T6_XADDR    0x1fU
55725 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
55726 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
55727 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
55728 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
55729 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
55730 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
55731 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
55732 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
55733 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
55734 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
55735 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
55738 #define M_T6_DCCTIMEEN    0x3U
55743 #define M_T6_DCCLOCK    0x3U
55748 #define M_T6_DCCOFFSET    0x7U
55753 #define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
55757 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
55758 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
55759 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
55760 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
55761 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
55762 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
55763 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
55764 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
55765 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
55766 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
55767 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
55768 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
55770 #define S_T6_SDOVRD    0
55771 #define M_T6_SDOVRD    0xffffU
55775 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
55776 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
55777 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
55783 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
55784 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
55785 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
55786 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
55789 #define M_T6_TMSCAL    0x3U
55801 #define S_T6_PHOFFS    0
55802 #define M_T6_PHOFFS    0x3fU
55806 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
55807 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
55808 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
55809 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
55810 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
55813 #define M_T6_SPIFMT    0xfU
55817 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
55818 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
55819 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
55826 #define M_T6_PEAK    0x1fU
55830 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
55832 #define S_T6_T5VGAIN    0
55833 #define M_T6_T5VGAIN    0x7fU
55837 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
55838 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
55839 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
55840 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
55841 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
55842 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
55843 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
55844 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
55845 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
55846 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
55847 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
55848 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
55849 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
55850 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
55851 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
55852 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
55853 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
55854 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
55855 #define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
55856 #define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
55857 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
55858 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3…
55859 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
55861 #define S_T6_ODEC    0
55862 #define M_T6_ODEC    0xfU
55866 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
55872 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
55873 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
55874 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
55875 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
55876 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
55877 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
55878 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
55879 #define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
55880 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
55881 #define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
55887 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
55888 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
55889 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
55890 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
55891 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
55892 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
55893 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
55894 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
55897 #define M_T6_EMMD    0x3U
55909 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
55910 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
55911 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
55912 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
55913 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
55914 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
55916 #define S_RX_LINK_BCST_INDEX_DFE_TC    0
55917 #define M_RX_LINK_BCST_INDEX_DFE_TC    0xfU
55921 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
55922 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
55924 #define S_RX_LINK_BCST_INDEX_DFE_TAP    0
55925 #define M_RX_LINK_BCST_INDEX_DFE_TAP    0xfU
55929 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
55930 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
55931 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
55932 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
55933 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
55934 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
55935 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
55936 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
55937 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
55938 #define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
55939 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
55940 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
55943 #define M_RX_LINK_BCST_DCCSTEP_RXCTL    0x3U
55951 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
55952 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
55953 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
55954 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
55955 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
55956 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
55957 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
55958 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
55959 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
55960 #define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
55966 #define S_NPWRENA    0
55970 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
55972 #define S_T5CPISEL    0
55973 #define M_T5CPISEL    0x7U
55977 #define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
55978 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
55981 #define M_SPEDIV    0x1fU
55985 #define S_PCKSEL    0
55986 #define M_PCKSEL    0x7U
55990 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
56000 #define S_EMIS    0
56004 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
56006 #define S_EMIL1    0
56007 #define M_EMIL1    0xffU
56011 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
56013 #define S_EMIL2    0
56014 #define M_EMIL2    0xffU
56018 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
56020 #define S_EMIL3    0
56021 #define M_EMIL3    0xffU
56025 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
56027 #define S_EMIL4    0
56028 #define M_EMIL4    0xffU
56032 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
56035 #define M_VBST    0x7U
56043 #define S_REFDIV    0
56044 #define M_REFDIV    0xfU
56048 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
56074 #define S_DIVSEL8    0
56078 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
56080 #define S_DIVSEL    0
56081 #define M_DIVSEL    0xffU
56085 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
56087 #define S_CONFIG    0
56088 #define M_CONFIG    0xffU
56092 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
56093 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
56094 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
56095 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
56096 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
56097 #define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
56098 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
56099 #define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
56100 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
56101 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
56102 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
56103 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
56104 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
56105 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
56106 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
56107 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
56108 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
56109 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
56110 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56112 #define S_STEP    0
56113 #define M_STEP    0x7U
56117 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56118 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56120 #define S_C0INIT    0
56121 #define M_C0INIT    0x1fU
56126 #define M_C0PRESET    0x7fU
56130 #define S_C0INIT1    0
56131 #define M_C0INIT1    0x7fU
56135 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56138 #define M_C0MAX    0x1fU
56142 #define S_C0MIN    0
56143 #define M_C0MIN    0x1fU
56147 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56150 #define M_T6_C0MAX    0x7fU
56154 #define S_T6_C0MIN    0
56155 #define M_T6_C0MIN    0x7fU
56159 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56161 #define S_C1INIT    0
56162 #define M_C1INIT    0x7fU
56166 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56169 #define M_C1PRESET    0x7fU
56173 #define S_C1INIT1    0
56174 #define M_C1INIT1    0x7fU
56178 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56181 #define M_C1MAX    0x7fU
56185 #define S_C1MIN    0
56186 #define M_C1MIN    0x7fU
56190 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56191 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56193 #define S_C2INIT    0
56194 #define M_C2INIT    0x3fU
56198 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56201 #define M_C2PRESET    0x7fU
56205 #define S_C2INIT1    0
56206 #define M_C2INIT1    0x7fU
56210 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56213 #define M_C2MAX    0x3fU
56217 #define S_C2MIN    0
56218 #define M_C2MIN    0x3fU
56222 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56225 #define M_T6_C2MAX    0x7fU
56229 #define S_T6_C2MIN    0
56230 #define M_T6_C2MIN    0x7fU
56234 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56236 #define S_VMMAX    0
56237 #define M_VMMAX    0x7fU
56241 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56242 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56244 #define S_V2MIN    0
56245 #define M_V2MIN    0x7fU
56249 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56250 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56253 #define M_C3PRESET    0x7fU
56257 #define S_C3INIT1    0
56258 #define M_C3INIT1    0x7fU
56262 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56265 #define M_C3MAX    0x7fU
56269 #define S_C3MIN    0
56270 #define M_C3MIN    0x7fU
56274 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56276 #define S_C0INIT2    0
56277 #define M_C0INIT2    0x7fU
56281 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56283 #define S_C1INIT2    0
56284 #define M_C1INIT2    0x7fU
56288 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56290 #define S_C2INIT2    0
56291 #define M_C2INIT2    0x7fU
56295 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56297 #define S_C3INIT2    0
56298 #define M_C3INIT2    0x7fU
56302 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56303 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56304 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56305 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56306 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56309 #define M_T6_C0MAX    0x7fU
56313 #define S_T6_C0MIN    0
56314 #define M_T6_C0MIN    0x7fU
56318 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56319 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56320 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56321 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56322 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56323 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56324 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56325 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56328 #define M_T6_C2MAX    0x7fU
56332 #define S_T6_C2MIN    0
56333 #define M_T6_C2MIN    0x7fU
56337 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56338 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56339 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56340 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56341 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56342 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56343 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56344 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56345 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56346 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56347 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56348 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56349 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56350 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56351 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56354 #define M_T6_C0MAX    0x7fU
56358 #define S_T6_C0MIN    0
56359 #define M_T6_C0MIN    0x7fU
56363 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56364 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56365 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56366 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56367 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56368 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56369 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56370 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56373 #define M_T6_C2MAX    0x7fU
56377 #define S_T6_C2MIN    0
56378 #define M_T6_C2MIN    0x7fU
56382 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56383 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56384 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56385 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56386 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56387 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56388 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56389 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56390 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56391 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56392 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56393 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56394 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56395 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56396 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56399 #define M_T6_C0MAX    0x7fU
56403 #define S_T6_C0MIN    0
56404 #define M_T6_C0MIN    0x7fU
56408 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56409 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56410 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56411 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56412 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56413 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56414 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56415 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56418 #define M_T6_C2MAX    0x7fU
56422 #define S_T6_C2MIN    0
56423 #define M_T6_C2MIN    0x7fU
56427 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56428 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56429 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56430 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56431 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56432 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56433 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56434 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56435 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56436 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56437 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
56438 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
56439 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
56440 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
56441 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
56444 #define M_T6_C0MAX    0x7fU
56448 #define S_T6_C0MIN    0
56449 #define M_T6_C0MIN    0x7fU
56453 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
56454 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
56455 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
56456 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
56457 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
56458 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
56459 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
56460 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
56463 #define M_T6_C2MAX    0x7fU
56467 #define S_T6_C2MIN    0
56468 #define M_T6_C2MIN    0x7fU
56472 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
56473 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
56474 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
56475 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
56476 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
56477 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
56478 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
56479 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
56480 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
56481 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
56482 #define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
56485 #define M_RX_LINKA_INDEX_DFE_EN    0x7fffU
56489 #define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
56492 #define M_T6_H1OSN    0x7U
56497 #define M_T6_H1OMAG    0x1fU
56501 #define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
56502 #define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
56503 #define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
56506 #define M_H4SN    0x3U
56510 #define S_H4MAG    0
56511 #define M_H4MAG    0xfU
56515 #define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
56518 #define M_H5GS    0x3U
56523 #define M_H5SN    0x3U
56527 #define S_H5MAG    0
56528 #define M_H5MAG    0xfU
56532 #define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
56535 #define M_H7SN    0x3U
56540 #define M_H6SN    0x3U
56544 #define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
56547 #define M_H9SN    0x3U
56552 #define M_H8SN    0x3U
56556 #define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
56559 #define M_H11SN    0x3U
56564 #define M_H10SN    0x3U
56568 #define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
56571 #define M_H13GS    0x7U
56576 #define M_H13SN    0x7U
56581 #define M_H13MAG    0x3U
56586 #define M_H12SN    0x3U
56590 #define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
56593 #define M_H15GS    0x7U
56598 #define M_H15SN    0x7U
56603 #define M_H15MAG    0x3U
56608 #define M_H14GS    0x3U
56613 #define M_H14SN    0x3U
56617 #define S_H14MAG    0
56618 #define M_H14MAG    0xfU
56622 #define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
56625 #define M_H1ODELTA    0x1fU
56629 #define S_H1EDELTA    0
56630 #define M_H1EDELTA    0x3fU
56634 #define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
56637 #define M_RX_LINKB_INDEX_DFE_EN    0x7fffU
56641 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
56644 #define M_T6_H1OSN    0x7U
56649 #define M_T6_H1OMAG    0x1fU
56653 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
56654 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
56655 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
56656 #define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
56657 #define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
56658 #define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
56659 #define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
56660 #define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
56661 #define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
56662 #define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
56663 #define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
56666 #define M_RX_LINKC_INDEX_DFE_EN    0x7fffU
56670 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
56673 #define M_T6_H1OSN    0x7U
56678 #define M_T6_H1OMAG    0x1fU
56682 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
56683 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
56684 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
56685 #define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
56686 #define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
56687 #define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
56688 #define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
56689 #define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
56690 #define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
56691 #define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
56692 #define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
56695 #define M_RX_LINKD_INDEX_DFE_EN    0x7fffU
56699 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
56702 #define M_T6_H1OSN    0x7U
56707 #define M_T6_H1OMAG    0x1fU
56711 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
56712 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
56713 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
56714 #define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
56715 #define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
56716 #define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
56717 #define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
56718 #define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
56719 #define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
56720 #define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
56721 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
56724 #define M_RX_LINK_BCST_INDEX_DFE_EN    0x7fffU
56728 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
56731 #define M_T6_H1OSN    0x7U
56736 #define M_T6_H1OMAG    0x1fU
56740 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
56741 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
56742 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
56743 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
56744 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
56745 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
56746 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
56747 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
56748 #define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
56749 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
56752 #define MC_0_BASE_ADDR 0x40000
56754 #define A_MC_UPCTL_SCFG 0x40000
56757 #define M_BBFLAGS_TIMING    0xfU
56765 #define A_MC_UPCTL_SCTL 0x40004
56766 #define A_MC_UPCTL_STAT 0x40008
56769 #define M_LP_TRIG    0x7U
56773 #define A_MC_UPCTL_INTRSTAT 0x4000c
56779 #define S_ECC_INTR    0
56783 #define A_MC_UPCTL_MCMD 0x40040
56785 #define S_CMD_OPCODE0    0
56786 #define M_CMD_OPCODE0    0xfU
56790 #define A_MC_LMC_MCSTAT 0x40040
56812 #define A_MC_UPCTL_POWCTL 0x40044
56813 #define A_MC_UPCTL_POWSTAT 0x40048
56814 #define A_MC_UPCTL_CMDTSTAT 0x4004c
56816 #define S_CMD_TSTAT    0
56820 #define A_MC_UPCTL_CMDTSTATEN 0x40050
56822 #define S_CMD_TSTAT_EN    0
56826 #define A_MC_UPCTL_MRRCFG0 0x40060
56828 #define S_MRR_BYTE_SEL    0
56829 #define M_MRR_BYTE_SEL    0xfU
56833 #define A_MC_UPCTL_MRRSTAT0 0x40064
56836 #define M_MRRSTAT_BEAT3    0xffU
56841 #define M_MRRSTAT_BEAT2    0xffU
56846 #define M_MRRSTAT_BEAT1    0xffU
56850 #define S_MRRSTAT_BEAT0    0
56851 #define M_MRRSTAT_BEAT0    0xffU
56855 #define A_MC_UPCTL_MRRSTAT1 0x40068
56858 #define M_MRRSTAT_BEAT7    0xffU
56863 #define M_MRRSTAT_BEAT6    0xffU
56868 #define M_MRRSTAT_BEAT5    0xffU
56872 #define S_MRRSTAT_BEAT4    0
56873 #define M_MRRSTAT_BEAT4    0xffU
56877 #define A_MC_UPCTL_MCFG1 0x4007c
56884 #define M_HW_IDLE    0xffU
56888 #define S_SR_IDLE    0
56889 #define M_SR_IDLE    0xffU
56893 #define A_MC_UPCTL_MCFG 0x40080
56896 #define M_MDDR_LPDDR2_CLK_STOP_IDLE    0xffU
56901 #define M_MDDR_LPDDR2_EN    0x3U
56906 #define M_MDDR_LPDDR2_BL    0x3U
56922 #define A_MC_LMC_MCOPT1 0x40080
56945 #define M_PMUM    0x3U
56978 #define M_QDEPTH    0x3U
57007 #define M_ECC_MUX    0x3U
57011 #define S_CE_THRESHOLD    0
57012 #define M_CE_THRESHOLD    0xffU
57016 #define A_MC_UPCTL_PPCFG 0x40084
57017 #define A_MC_LMC_MCOPT2 0x40084
57036 #define M_CLK_DISABLE    0xfU
57041 #define M_RESET_RANK    0xfU
57070 #define M_PM_ENABLE    0xfU
57075 #define M_RD_DEFREF_CNT    0xfU
57079 #define A_MC_UPCTL_MSTAT 0x40088
57089 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
57092 #define M_ZQCL_OP    0xffU
57097 #define M_ZQCL_MA    0xffU
57102 #define M_ZQCS_OP    0xffU
57106 #define S_ZQCS_MA    0
57107 #define M_ZQCS_MA    0xffU
57111 #define A_MC_UPCTL_DTUPDES 0x40094
57117 #define A_MC_UPCTL_DTUNA 0x40098
57118 #define A_MC_UPCTL_DTUNE 0x4009c
57119 #define A_MC_UPCTL_DTUPRD0 0x400a0
57120 #define A_MC_UPCTL_DTUPRD1 0x400a4
57121 #define A_MC_UPCTL_DTUPRD2 0x400a8
57122 #define A_MC_UPCTL_DTUPRD3 0x400ac
57123 #define A_MC_UPCTL_DTUAWDT 0x400b0
57124 #define A_MC_UPCTL_TOGCNT1U 0x400c0
57125 #define A_MC_UPCTL_TINIT 0x400c4
57126 #define A_MC_UPCTL_TRSTH 0x400c8
57127 #define A_MC_UPCTL_TOGCNT100N 0x400cc
57128 #define A_MC_UPCTL_TREFI 0x400d0
57129 #define A_MC_UPCTL_TMRD 0x400d4
57130 #define A_MC_UPCTL_TRFC 0x400d8
57132 #define S_T_RFC0    0
57133 #define M_T_RFC0    0x1ffU
57137 #define A_MC_UPCTL_TRP 0x400dc
57140 #define M_PREA_EXTRA    0x3U
57144 #define A_MC_UPCTL_TRTW 0x400e0
57146 #define S_T_RTW0    0
57147 #define M_T_RTW0    0xfU
57151 #define A_MC_UPCTL_TAL 0x400e4
57152 #define A_MC_UPCTL_TCL 0x400e8
57153 #define A_MC_UPCTL_TCWL 0x400ec
57154 #define A_MC_UPCTL_TRAS 0x400f0
57155 #define A_MC_UPCTL_TRC 0x400f4
57156 #define A_MC_UPCTL_TRCD 0x400f8
57157 #define A_MC_UPCTL_TRRD 0x400fc
57158 #define A_MC_UPCTL_TRTP 0x40100
57160 #define S_T_RTP0    0
57161 #define M_T_RTP0    0xfU
57165 #define A_MC_LMC_CFGR0 0x40100
57168 #define M_ROW_WIDTH    0x7U
57173 #define M_ADDR_MODE    0xfU
57181 #define S_RANK_ENABLE    0
57185 #define A_MC_UPCTL_TWR 0x40104
57187 #define S_U_T_WR    0
57188 #define M_U_T_WR    0x1fU
57192 #define A_MC_UPCTL_TWTR 0x40108
57194 #define S_T_WTR0    0
57195 #define M_T_WTR0    0xfU
57199 #define A_MC_UPCTL_TEXSR 0x4010c
57200 #define A_MC_UPCTL_TXP 0x40110
57201 #define A_MC_UPCTL_TXPDLL 0x40114
57202 #define A_MC_UPCTL_TZQCS 0x40118
57203 #define A_MC_UPCTL_TZQCSI 0x4011c
57204 #define A_MC_UPCTL_TDQS 0x40120
57205 #define A_MC_UPCTL_TCKSRE 0x40124
57207 #define S_T_CKSRE0    0
57208 #define M_T_CKSRE0    0x1fU
57212 #define A_MC_UPCTL_TCKSRX 0x40128
57214 #define S_T_CKSRX0    0
57215 #define M_T_CKSRX0    0x1fU
57219 #define A_MC_UPCTL_TCKE 0x4012c
57220 #define A_MC_UPCTL_TMOD 0x40130
57222 #define S_T_MOD0    0
57223 #define M_T_MOD0    0x1fU
57227 #define A_MC_UPCTL_TRSTL 0x40134
57229 #define S_T_RSTL    0
57230 #define M_T_RSTL    0x7fU
57234 #define A_MC_UPCTL_TZQCL 0x40138
57235 #define A_MC_UPCTL_TMRR 0x4013c
57237 #define S_T_MRR    0
57238 #define M_T_MRR    0xffU
57242 #define A_MC_UPCTL_TCKESR 0x40140
57244 #define S_T_CKESR    0
57245 #define M_T_CKESR    0xfU
57249 #define A_MC_LMC_INITSEQ0 0x40140
57256 #define M_WAIT    0xfffU
57264 #define S_T6_RANK    0
57265 #define M_T6_RANK    0xfU
57269 #define A_MC_UPCTL_TDPD 0x40144
57271 #define S_T_DPD    0
57272 #define M_T_DPD    0x3ffU
57276 #define A_MC_LMC_CMD0 0x40144
57279 #define M_CMD    0x7U
57292 #define M_BANK    0x7U
57296 #define A_MC_LMC_INITSEQ1 0x40148
57298 #define S_T6_RANK    0
57299 #define M_T6_RANK    0xfU
57303 #define A_MC_LMC_CMD1 0x4014c
57304 #define A_MC_LMC_INITSEQ2 0x40150
57306 #define S_T6_RANK    0
57307 #define M_T6_RANK    0xfU
57311 #define A_MC_LMC_CMD2 0x40154
57312 #define A_MC_LMC_INITSEQ3 0x40158
57314 #define S_T6_RANK    0
57315 #define M_T6_RANK    0xfU
57319 #define A_MC_LMC_CMD3 0x4015c
57320 #define A_MC_LMC_INITSEQ4 0x40160
57322 #define S_T6_RANK    0
57323 #define M_T6_RANK    0xfU
57327 #define A_MC_LMC_CMD4 0x40164
57328 #define A_MC_LMC_INITSEQ5 0x40168
57330 #define S_T6_RANK    0
57331 #define M_T6_RANK    0xfU
57335 #define A_MC_LMC_CMD5 0x4016c
57336 #define A_MC_LMC_INITSEQ6 0x40170
57338 #define S_T6_RANK    0
57339 #define M_T6_RANK    0xfU
57343 #define A_MC_LMC_CMD6 0x40174
57344 #define A_MC_LMC_INITSEQ7 0x40178
57346 #define S_T6_RANK    0
57347 #define M_T6_RANK    0xfU
57351 #define A_MC_LMC_CMD7 0x4017c
57352 #define A_MC_UPCTL_ECCCFG 0x40180
57353 #define A_MC_LMC_INITSEQ8 0x40180
57355 #define S_T6_RANK    0
57356 #define M_T6_RANK    0xfU
57360 #define A_MC_UPCTL_ECCTST 0x40184
57362 #define S_ECC_TEST_MASK0    0
57363 #define M_ECC_TEST_MASK0    0x7fU
57367 #define A_MC_LMC_CMD8 0x40184
57368 #define A_MC_UPCTL_ECCCLR 0x40188
57369 #define A_MC_LMC_INITSEQ9 0x40188
57371 #define S_T6_RANK    0
57372 #define M_T6_RANK    0xfU
57376 #define A_MC_UPCTL_ECCLOG 0x4018c
57377 #define A_MC_LMC_CMD9 0x4018c
57378 #define A_MC_LMC_INITSEQ10 0x40190
57380 #define S_T6_RANK    0
57381 #define M_T6_RANK    0xfU
57385 #define A_MC_LMC_CMD10 0x40194
57386 #define A_MC_LMC_INITSEQ11 0x40198
57388 #define S_T6_RANK    0
57389 #define M_T6_RANK    0xfU
57393 #define A_MC_LMC_CMD11 0x4019c
57394 #define A_MC_LMC_INITSEQ12 0x401a0
57396 #define S_T6_RANK    0
57397 #define M_T6_RANK    0xfU
57401 #define A_MC_LMC_CMD12 0x401a4
57402 #define A_MC_LMC_INITSEQ13 0x401a8
57404 #define S_T6_RANK    0
57405 #define M_T6_RANK    0xfU
57409 #define A_MC_LMC_CMD13 0x401ac
57410 #define A_MC_LMC_INITSEQ14 0x401b0
57412 #define S_T6_RANK    0
57413 #define M_T6_RANK    0xfU
57417 #define A_MC_LMC_CMD14 0x401b4
57418 #define A_MC_LMC_INITSEQ15 0x401b8
57420 #define S_T6_RANK    0
57421 #define M_T6_RANK    0xfU
57425 #define A_MC_LMC_CMD15 0x401bc
57426 #define A_MC_UPCTL_DTUWACTL 0x40200
57429 #define M_DTU_WR_ROW0    0xffffU
57433 #define A_MC_LMC_SDTR0 0x40200
57436 #define M_REFI    0xffffU
57440 #define S_T_RFC_XPR    0
57441 #define M_T_RFC_XPR    0xfffU
57445 #define A_MC_UPCTL_DTURACTL 0x40204
57448 #define M_DTU_RD_ROW0    0xffffU
57452 #define A_MC_LMC_SDTR1 0x40204
57467 #define M_T_WTRO    0xfU
57472 #define M_T_RTWO    0xfU
57477 #define M_T_RTW_ADJ    0xfU
57482 #define M_T_WTWO    0xfU
57486 #define S_T_RTRO    0
57487 #define M_T_RTRO    0xfU
57491 #define A_MC_UPCTL_DTUCFG 0x40208
57492 #define A_MC_LMC_SDTR2 0x40208
57495 #define M_T6_T_CWL    0xfU
57500 #define M_T_RCD0    0xfU
57505 #define M_T_PL    0xfU
57510 #define M_T_RP0    0xfU
57523 #define M_T6_T_RC    0x3fU
57527 #define A_MC_UPCTL_DTUECTL 0x4020c
57528 #define A_MC_LMC_SDTR3 0x4020c
57531 #define M_T_WTR_S    0xfU
57536 #define M_T6_T_WTR    0xfU
57541 #define M_FAW_ADJ    0x3U
57546 #define M_T6_T_RTP    0xfU
57551 #define M_T_RRD_L    0xfU
57556 #define M_T6_T_RRD    0xfU
57560 #define S_T_XSDLL    0
57561 #define M_T_XSDLL    0xffU
57565 #define A_MC_UPCTL_DTUWD0 0x40210
57566 #define A_MC_LMC_SDTR4 0x40210
57569 #define M_T_RDDATA_EN    0x7fU
57574 #define M_T_SYS_RDLAT    0x3fU
57579 #define M_T_CCD_L    0xfU
57584 #define M_T_CCD    0x7U
57589 #define M_T_CPDED    0x7U
57593 #define S_T6_T_MOD    0
57594 #define M_T6_T_MOD    0x1fU
57598 #define A_MC_UPCTL_DTUWD1 0x40214
57599 #define A_MC_LMC_SDTR5 0x40214
57602 #define M_T_PHY_WRDATA    0x7U
57607 #define M_T_PHY_WRLAT    0x1fU
57611 #define A_MC_UPCTL_DTUWD2 0x40218
57612 #define A_MC_UPCTL_DTUWD3 0x4021c
57613 #define A_MC_UPCTL_DTUWDM 0x40220
57614 #define A_MC_UPCTL_DTURD0 0x40224
57615 #define A_MC_UPCTL_DTURD1 0x40228
57616 #define A_MC_LMC_DBG0 0x40228
57619 #define M_T_SYS_RDLAT_DBG    0x1fU
57623 #define A_MC_UPCTL_DTURD2 0x4022c
57624 #define A_MC_UPCTL_DTURD3 0x40230
57625 #define A_MC_UPCTL_DTULFSRWD 0x40234
57626 #define A_MC_UPCTL_DTULFSRRD 0x40238
57627 #define A_MC_UPCTL_DTUEAF 0x4023c
57630 #define M_EA_ROW0    0xffffU
57634 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
57636 #define S_TCTRL_DELAY    0
57637 #define M_TCTRL_DELAY    0xfU
57641 #define A_MC_LMC_SMR0 0x40240
57644 #define M_SMR0_RFU0    0x7U
57653 #define M_WR_RTP    0x7U
57666 #define M_CL31    0x7U
57678 #define S_BL    0
57679 #define M_BL    0x3U
57683 #define A_MC_UPCTL_DFIODTCFG 0x40244
57689 #define A_MC_LMC_SMR1 0x40244
57724 #define M_AL    0x3U
57736 #define S_SMR1_DLL    0
57740 #define A_MC_UPCTL_DFIODTCFG1 0x40248
57743 #define M_ODT_LEN_B8_R    0x7U
57748 #define M_ODT_LEN_BL8_W    0x7U
57753 #define M_ODT_LAT_R    0x1fU
57757 #define S_ODT_LAT_W    0
57758 #define M_ODT_LAT_W    0x1fU
57762 #define A_MC_LMC_SMR2 0x40248
57773 #define M_RTT_WR    0x3U
57790 #define M_CWL    0x7U
57794 #define S_PASR    0
57795 #define M_PASR    0x7U
57799 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
57802 #define M_ODT_RANK_MAP3    0xfU
57807 #define M_ODT_RANK_MAP2    0xfU
57812 #define M_ODT_RANK_MAP1    0xfU
57816 #define S_ODT_RANK_MAP0    0
57817 #define M_ODT_RANK_MAP0    0xfU
57821 #define A_MC_LMC_SMR3 0x4024c
57824 #define M_MPR_RD_FMT    0x3U
57829 #define M_SMR3_RFU0    0x3U
57834 #define M_FGR_MODE    0x7U
57854 #define S_MPR_SEL    0
57855 #define M_MPR_SEL    0x3U
57859 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
57861 #define S_TPHY_WRDATA    0
57862 #define M_TPHY_WRDATA    0x1fU
57866 #define A_MC_LMC_SMR4 0x40250
57885 #define M_CS_LAT_MODE    0x7U
57909 #define S_SMR4_RFU    0
57913 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
57915 #define S_TPHY_WRLAT    0
57916 #define M_TPHY_WRLAT    0x1fU
57920 #define A_MC_LMC_SMR5 0x40254
57935 #define M_RTT_PARK    0x7U
57951 #define S_PAR_LAT_MODE    0
57952 #define M_PAR_LAT_MODE    0x7U
57956 #define A_MC_LMC_SMR6 0x40258
57959 #define M_TCCD_L    0x7U
57964 #define M_SRM6_RFU    0x7U
57972 #define S_VREF_DQ_VALUE    0
57973 #define M_VREF_DQ_VALUE    0x3fU
57977 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
57979 #define S_TRDDATA_EN    0
57980 #define M_TRDDATA_EN    0x1fU
57984 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
57986 #define S_TPHY_RDLAT    0
57987 #define M_TPHY_RDLAT    0x3fU
57991 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
57993 #define S_TPHYUPD_TYPE0    0
57994 #define M_TPHYUPD_TYPE0    0xfffU
57998 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
58000 #define S_TPHYUPD_TYPE1    0
58001 #define M_TPHYUPD_TYPE1    0xfffU
58005 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
58007 #define S_TPHYUPD_TYPE2    0
58008 #define M_TPHYUPD_TYPE2    0xfffU
58012 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
58014 #define S_TPHYUPD_TYPE3    0
58015 #define M_TPHYUPD_TYPE3    0xfffU
58019 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
58021 #define S_TCTRLUPD_MIN    0
58022 #define M_TCTRLUPD_MIN    0xffffU
58026 #define A_MC_LMC_ODTR0 0x40280
58036 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
58038 #define S_TCTRLUPD_MAX    0
58039 #define M_TCTRLUPD_MAX    0xffffU
58043 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
58045 #define S_TCTRLUPD_DLY    0
58046 #define M_TCTRLUPD_DLY    0xfU
58050 #define A_MC_UPCTL_DFIUPDCFG 0x40290
58056 #define S_DFI_CTRLUPD_EN    0
58060 #define A_MC_UPCTL_DFITREFMSKI 0x40294
58062 #define S_TREFMSKI    0
58063 #define M_TREFMSKI    0xffU
58067 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
58068 #define A_MC_UPCTL_DFITRCFG0 0x402ac
58071 #define M_DFI_WRLVL_RANK_SEL    0xfU
58076 #define M_DFI_RDLVL_EDGE    0x1ffU
58080 #define S_DFI_RDLVL_RANK_SEL    0
58081 #define M_DFI_RDLVL_RANK_SEL    0xfU
58085 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
58088 #define M_DFI_WRLVL_MODE    0x3U
58093 #define M_DFI_RDLVL_GATE_MODE    0x3U
58097 #define S_DFI_RDLVL_MODE    0
58098 #define M_DFI_RDLVL_MODE    0x3U
58102 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
58104 #define S_DFI_WRLVL_EN    0
58105 #define M_DFI_WRLVL_EN    0x1ffU
58109 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
58111 #define S_DFI_RDLVL_EN    0
58112 #define M_DFI_RDLVL_EN    0x1ffU
58116 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
58118 #define S_DFI_RDLVL_GATE_EN    0
58119 #define M_DFI_RDLVL_GATE_EN    0x1ffU
58123 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
58126 #define M_DFI_DATA_BYTE_DISABLE    0x1ffU
58131 #define M_DFI_FREQ_RATIO    0x3U
58139 #define S_DFI_INIT_COMPLETE    0
58143 #define A_MC_UPCTL_DFISTCFG0 0x402c4
58153 #define S_DFI_INIT_START    0
58157 #define A_MC_UPCTL_DFISTCFG1 0x402c8
58163 #define S_DFI_DRAM_CLK_DISABLE_EN    0
58167 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
58169 #define S_TDRAM_CLK_ENABLE    0
58170 #define M_TDRAM_CLK_ENABLE    0xfU
58174 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
58176 #define S_TDRAM_CLK_DISABLE    0
58177 #define M_TDRAM_CLK_DISABLE    0xfU
58181 #define A_MC_UPCTL_DFISTCFG2 0x402d8
58187 #define S_PARITY_INTR_EN    0
58191 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
58197 #define S_PARITY_INTR_CLR    0
58201 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
58202 #define A_MC_UPCTL_DFILPCFG0 0x402f0
58205 #define M_DFI_LP_WAKEUP_DPD    0xfU
58214 #define M_DFI_TLP_RESP    0xfU
58223 #define M_DFI_LP_WAKEUP_PD    0xfU
58227 #define S_DFI_LP_EN_PD    0
58231 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
58232 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
58233 #define A_MC_LMC_CALSTAT 0x40304
58236 #define M_PHYUPD_ERR    0xfU
58244 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
58246 #define S_DFI_WRLVL_RESP2    0
58247 #define M_DFI_WRLVL_RESP2    0xffU
58251 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
58252 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
58253 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
58255 #define S_DFI_RDLVL_RESP2    0
58256 #define M_DFI_RDLVL_RESP2    0xffU
58260 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
58261 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
58262 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
58264 #define S_DFI_WRLVL_DELAY2    0
58265 #define M_DFI_WRLVL_DELAY2    0xffU
58269 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
58270 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
58271 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
58273 #define S_DFI_RDLVL_DELAY2    0
58274 #define M_DFI_RDLVL_DELAY2    0xffU
58278 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
58279 #define A_MC_LMC_T_PHYUPD0 0x40330
58280 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
58281 #define A_MC_LMC_T_PHYUPD1 0x40334
58282 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
58284 #define S_DFI_RDLVL_GATE_DELAY2    0
58285 #define M_DFI_RDLVL_GATE_DELAY2    0xffU
58289 #define A_MC_LMC_T_PHYUPD2 0x40338
58290 #define A_MC_UPCTL_DFITRCMD 0x4033c
58297 #define M_DFITRCMD_EN    0x1ffU
58301 #define S_DFITRCMD_OPCODE    0
58302 #define M_DFITRCMD_OPCODE    0x3U
58306 #define A_MC_LMC_T_PHYUPD3 0x4033c
58307 #define A_MC_UPCTL_IPVR 0x403f8
58308 #define A_MC_UPCTL_IPTR 0x403fc
58309 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
58312 #define M_PHY_DRAM_WL    0x1fU
58337 #define M_T6_PHY_DRAM_WL    0xfU
58341 #define A_MC_P_PERFORMANCE_CTRL 0x41304
58344 #define M_BUF_USE_TH    0x7U
58349 #define M_MC_IDLE_TH    0xfU
58373 #define A_MC_P_ECC_CTRL 0x41308
58374 #define A_MC_P_PAR_ENABLE 0x4130c
58375 #define A_MC_P_PAR_CAUSE 0x41310
58376 #define A_MC_P_INT_ENABLE 0x41314
58377 #define A_MC_P_INT_CAUSE 0x41318
58378 #define A_MC_P_ECC_STATUS 0x4131c
58379 #define A_MC_P_PHY_CTRL 0x41320
58380 #define A_MC_P_STATIC_CFG_STATUS 0x41324
58387 #define M_STATIC_SWLAT    0x1fU
58400 #define M_STATIC_SLAT    0x1fU
58420 #define A_MC_P_CORE_PCTL_STAT 0x41328
58421 #define A_MC_P_DEBUG_CNT 0x4132c
58422 #define A_MC_CE_ERR_DATA_RDATA 0x41330
58423 #define A_MC_CE_COR_DATA_RDATA 0x41350
58424 #define A_MC_UE_ERR_DATA_RDATA 0x41370
58425 #define A_MC_UE_COR_DATA_RDATA 0x41390
58426 #define A_MC_CE_ADDR 0x413b0
58427 #define A_MC_UE_ADDR 0x413b4
58428 #define A_MC_P_DEEP_SLEEP 0x413b8
58434 #define S_SLEEPREQ    0
58438 #define A_MC_P_FPGA_BONUS 0x413bc
58439 #define A_MC_P_DEBUG_CFG 0x413c0
58440 #define A_MC_P_DEBUG_RPT 0x413c4
58441 #define A_MC_P_PHY_ADR_CK_EN 0x413c8
58443 #define S_ADR_CK_EN    0
58447 #define A_MC_CE_ERR_ECC_DATA0 0x413d0
58448 #define A_MC_CE_ERR_ECC_DATA1 0x413d4
58449 #define A_MC_UE_ERR_ECC_DATA0 0x413d8
58450 #define A_MC_UE_ERR_ECC_DATA1 0x413dc
58451 #define A_MC_P_RMW_PRIO 0x413f0
58454 #define M_WR_HI_TH    0xffU
58459 #define M_WR_MID_TH    0xffU
58464 #define M_RD_HI_TH    0xffU
58468 #define S_RD_MID_TH    0
58469 #define M_RD_MID_TH    0xffU
58473 #define A_MC_P_BIST_CMD 0x41400
58476 #define M_BURST_LEN    0x3U
58480 #define A_MC_P_BIST_CMD_ADDR 0x41404
58481 #define A_MC_P_BIST_CMD_LEN 0x41408
58482 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
58483 #define A_MC_P_BIST_USER_WDATA0 0x41414
58484 #define A_MC_P_BIST_USER_WMASK0 0x41414
58485 #define A_MC_P_BIST_USER_WDATA1 0x41418
58486 #define A_MC_P_BIST_USER_WMASK1 0x41418
58487 #define A_MC_P_BIST_USER_WDATA2 0x4141c
58490 #define M_USER_DATA_MASK    0x1ffU
58494 #define A_MC_P_BIST_USER_WMASK2 0x4141c
58504 #define S_USER_MASK_ECC    0
58505 #define M_USER_MASK_ECC    0xffU
58509 #define A_MC_P_BIST_NUM_ERR 0x41480
58510 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
58511 #define A_MC_P_BIST_STATUS_RDATA 0x41488
58512 #define A_MC_P_BIST_CRC_SEED 0x414d0
58513 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
58515 #define S_DATA_BIT_ENABLE_0_15    0
58516 #define M_DATA_BIT_ENABLE_0_15    0xffffU
58520 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
58523 #define M_DATA_BIT_ENABLE_16_23    0xffU
58551 #define S_MRS_CMD_DATA_N3    0
58563 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
58565 #define S_DATA_BIT_DIR_0_15    0
58566 #define M_DATA_BIT_DIR_0_15    0xffffU
58570 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
58573 #define M_DATA_BIT_DIR_16_23    0xffU
58605 #define S_ATEST_MUX_CTL3    0
58609 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
58667 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
58673 #define S_QUAD3_CLK18_BIT15    0
58677 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
58680 #define M_PEAK_AMP_CTL_SIDE0    0x7U
58685 #define M_PEAK_AMP_CTL_SIDE1    0x7U
58690 #define M_SXMCVREF_0_3    0xfU
58702 #define S_READ_CENTERING_MODE    0
58703 #define M_READ_CENTERING_MODE    0x3U
58707 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
58713 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
58735 #define S_DIGITAL_EYE_VALUE    0
58736 #define M_DIGITAL_EYE_VALUE    0xffU
58740 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
58743 #define M_DQSCLK_SELECT0    0x3U
58748 #define M_RDCLK_SELECT0    0x3U
58753 #define M_DQSCLK_SELECT1    0x3U
58758 #define M_RDCLK_SELECT1    0x3U
58763 #define M_DQSCLK_SELECT2    0x3U
58768 #define M_RDCLK_SELECT2    0x3U
58773 #define M_DQSCLK_SELECT3    0x3U
58777 #define S_RDCLK_SELECT3    0
58778 #define M_RDCLK_SELECT3    0x3U
58782 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
58785 #define M_MIN_RD_EYE_SIZE    0x3fU
58789 #define S_MAX_DQS_DRIFT    0
58790 #define M_MAX_DQS_DRIFT    0x3fU
58794 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
58797 #define M_HS_PROBE_A_SEL    0x1fU
58802 #define M_HS_PROBE_B_SEL    0x1fU
58807 #define M_RD_DEBUG_SEL    0x7U
58811 #define S_WR_DEBUG_SEL    0
58812 #define M_WR_DEBUG_SEL    0x7U
58817 #define M_DP18_HS_PROBE_A_SEL    0x1fU
58822 #define M_DP18_HS_PROBE_B_SEL    0x1fU
58826 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
58829 #define M_OFFSET_BITS1_7    0x7fU
58833 #define S_OFFSET_BITS9_15    0
58834 #define M_OFFSET_BITS9_15    0x7fU
58838 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
58839 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
58841 #define S_LEADING_EDGE_NOT_FOUND_0    0
58842 #define M_LEADING_EDGE_NOT_FOUND_0    0xffffU
58846 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
58849 #define M_LEADING_EDGE_NOT_FOUND_1    0xffU
58853 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
58855 #define S_TRAILING_EDGE_NOT_FOUND    0
58856 #define M_TRAILING_EDGE_NOT_FOUND    0xffffU
58860 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
58863 #define M_TRAILING_EDGE_NOT_FOUND_16_23    0xffU
58867 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
58893 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
58896 #define M_DQS_GATE_DELAY_N0    0x7U
58901 #define M_DQS_GATE_DELAY_N1    0x7U
58906 #define M_DQS_GATE_DELAY_N2    0x7U
58910 #define S_DQS_GATE_DELAY_N3    0
58911 #define M_DQS_GATE_DELAY_N3    0x7U
58915 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
58977 #define S_MIN_EYE    0
58981 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
59043 #define S_MIN_EYE_MASK    0
59047 #define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
59050 #define M_PRBS_WAIT    0x3U
59067 #define M_SS_QUAD    0x3U
59079 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
59082 #define M_CLK_LEVEL    0x3U
59118 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
59121 #define M_BIT_CENTERED    0x1fU
59153 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
59156 #define M_FW_LEFT_SIDE    0x7ffU
59160 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
59163 #define M_FW_RIGHT_SIDE    0x7ffU
59167 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
59213 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
59267 #define S_ADVANCE_PR_VALUE    0
59271 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
59278 #define M_DP18_DFT_SYNC    0x3fU
59282 #define S_ERROR    0
59283 #define M_ERROR    0x3fU
59291 #define S_DP18_DFT_ERROR    0
59292 #define M_DP18_DFT_ERROR    0x3fU
59296 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
59299 #define M_SYSCLK_RDCLK_OFFSET    0x7fU
59303 #define S_SYSCLK_DQSCLK_OFFSET    0
59304 #define M_SYSCLK_DQSCLK_OFFSET    0x7fU
59309 #define M_T6_SYSCLK_DQSCLK_OFFSET    0x7fU
59313 #define S_T6_SYSCLK_RDCLK_OFFSET    0
59314 #define M_T6_SYSCLK_RDCLK_OFFSET    0x7fU
59318 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
59319 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
59322 #define M_DQSCLK_ROT_CLK_N0_N2    0x7fU
59326 #define S_DQSCLK_ROT_CLK_N1_N3    0
59327 #define M_DQSCLK_ROT_CLK_N1_N3    0x7fU
59331 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
59332 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
59335 #define M_MEMINTD00_POS    0x3U
59340 #define M_MEMINTD01_PO    0x3U
59345 #define M_MEMINTD02_POS    0x3U
59350 #define M_MEMINTD03_POS    0x3U
59355 #define M_MEMINTD04_POS    0x3U
59360 #define M_MEMINTD05_POS    0x3U
59365 #define M_MEMINTD06_POS    0x3U
59369 #define S_MEMINTD07_POS    0
59370 #define M_MEMINTD07_POS    0x3U
59374 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
59377 #define M_MEMINTD08_POS    0x3U
59382 #define M_MEMINTD09_POS    0x3U
59387 #define M_MEMINTD10_POS    0x3U
59392 #define M_MEMINTD11_POS    0x3U
59397 #define M_MEMINTD12_POS    0x3U
59402 #define M_MEMINTD13_POS    0x3U
59407 #define M_MEMINTD14_POS    0x3U
59411 #define S_MEMINTD15_POS    0
59412 #define M_MEMINTD15_POS    0x3U
59416 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
59419 #define M_MEMINTD16_POS    0x3U
59424 #define M_MEMINTD17_POS    0x3U
59429 #define M_MEMINTD18_POS    0x3U
59434 #define M_MEMINTD19_POS    0x3U
59439 #define M_MEMINTD20_POS    0x3U
59444 #define M_MEMINTD21_POS    0x3U
59449 #define M_MEMINTD22_POS    0x3U
59453 #define S_MEMINTD23_POS    0
59454 #define M_MEMINTD23_POS    0x3U
59458 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
59461 #define M_DQS_ALIGN_SM    0x1fU
59466 #define M_DQS_ALIGN_CNTR    0xfU
59474 #define S_DQS_ALIGN_ITER_CNTR    0
59475 #define M_DQS_ALIGN_ITER_CNTR    0x3fU
59479 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
59482 #define M_CALIBRATE_BIT    0x7U
59487 #define M_DQS_ALIGN_QUAD    0x3U
59492 #define M_DQS_QUAD_CONFIG    0x7U
59497 #define M_OPERATE_MODE    0xfU
59513 #define S_MAX_DQS_ITER    0
59517 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
59520 #define M_DQS_OFFSET    0x7fU
59524 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
59527 #define M_WR_DELAY    0x3ffU
59531 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
59532 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
59533 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
59534 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
59535 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
59536 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
59537 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
59538 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
59539 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
59540 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
59541 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
59542 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
59543 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
59544 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
59545 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
59546 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
59547 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
59548 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
59549 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
59550 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
59551 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
59552 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
59553 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
59554 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
59557 #define M_RD_DELAY_BITS0_6    0x7fU
59562 #define M_RD_DELAY_BITS8_14    0x7fU
59566 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
59567 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
59568 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
59569 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
59570 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
59571 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
59572 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
59573 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
59574 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
59575 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
59576 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
59577 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
59580 #define M_INITIAL_DQS_ROT_N0_N2    0x7fU
59584 #define S_INITIAL_DQS_ROT_N1_N3    0
59585 #define M_INITIAL_DQS_ROT_N1_N3    0x7fU
59589 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
59590 #define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
59648 #define S_QUAD0_CAVEAT    0
59652 #define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
59655 #define M_FAIL_PASS_VALUE    0x7fU
59659 #define S_PASS_FAIL_VALUE    0
59660 #define M_PASS_FAIL_VALUE    0xffU
59664 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
59667 #define M_RD_EYE_SIZE_BITS2_7    0x3fU
59671 #define S_RD_EYE_SIZE_BITS10_15    0
59672 #define M_RD_EYE_SIZE_BITS10_15    0x3fU
59676 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
59677 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
59678 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
59679 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
59680 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
59681 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
59682 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
59683 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
59684 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
59685 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
59686 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
59687 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
59690 #define M_DESIRED_EDGE_CNTR_TARGET_HIGH    0xffU
59694 #define S_DESIRED_EDGE_CNTR_TARGET_LOW    0
59695 #define M_DESIRED_EDGE_CNTR_TARGET_LOW    0xffU
59699 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
59705 #define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
59708 #define M_QUAD0_PWR_CTL    0xfU
59713 #define M_QUAD1_PWR_CTL    0xfU
59718 #define M_QUAD2_PWR_CTL    0xfU
59722 #define S_QUAD3_PWR_CTL    0
59723 #define M_QUAD3_PWR_CTL    0xfU
59727 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
59730 #define M_REFERENCE_BITS1_7    0x7fU
59734 #define S_REFERENCE_BITS9_15    0
59735 #define M_REFERENCE_BITS9_15    0x7fU
59739 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
59740 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
59743 #define M_REFERENCE    0x7fU
59747 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
59748 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
59749 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
59752 #define M_INTERP_SIG_SLEW    0xfU
59757 #define M_POST_CURSOR    0xfU
59762 #define M_SLEW_CTL    0xfU
59766 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
59767 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
59789 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
59792 #define M_EN_SLICE_N_WR    0xffU
59796 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
59797 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
59800 #define M_EN_TERM_N_WR    0xffU
59805 #define M_EN_TERM_N_WR_FFE    0xfU
59809 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
59812 #define M_EN_TERM_P_WR    0xffU
59817 #define M_EN_TERM_P_WR_FFE    0xfU
59821 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
59823 #define S_DATA_BIT_DISABLE_0_15    0
59824 #define M_DATA_BIT_DISABLE_0_15    0xffffU
59828 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
59831 #define M_DATA_BIT_DISABLE_16_23    0xffU
59835 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
59838 #define M_DQ_WR_OFFSET_N0    0xfU
59843 #define M_DQ_WR_OFFSET_N1    0xfU
59848 #define M_DQ_WR_OFFSET_N2    0xfU
59852 #define S_DQ_WR_OFFSET_N3    0
59853 #define M_DQ_WR_OFFSET_N3    0xfU
59857 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
59868 #define M_DP18_RX_PD    0x3U
59876 #define S_VCC_REG_PD    0
59880 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
59883 #define M_BIT_ENABLE_0_11    0xfffU
59887 #define S_BIT_ENABLE_12_15    0
59888 #define M_BIT_ENABLE_12_15    0xfU
59892 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
59926 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
59929 #define M_ADR_DELAY_BITS1_7    0x7fU
59933 #define S_ADR_DELAY_BITS9_15    0
59934 #define M_ADR_DELAY_BITS9_15    0x7fU
59938 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
59939 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
59940 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
59941 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
59942 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
59943 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
59944 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
59945 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
59948 #define M_ADR_TEST_LANE_PAIR_FAIL    0xffU
59957 #define M_DADR_TEST_MODE    0x3U
59977 #define S_ADR_TEST_CHECK_EN    0
59981 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
59984 #define M_EN_SLICE_N_WR_0    0xffU
59989 #define M_EN_SLICE_N_WR_FFE    0xfU
59993 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
59996 #define M_EN_SLICE_N_WR_1    0xffU
60000 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
60003 #define M_EN_SLICE_N_WR_2    0xffU
60007 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
60010 #define M_EN_SLICE_N_WR_3    0xffU
60014 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
60017 #define M_EN_SLICE_P_WR    0xffU
60022 #define M_EN_SLICE_P_WR_FFE    0xfU
60026 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
60027 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
60028 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
60029 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
60032 #define M_POST_CURSOR0    0xfU
60037 #define M_POST_CURSOR1    0xfU
60042 #define M_POST_CURSOR2    0xfU
60046 #define S_POST_CURSOR3    0
60047 #define M_POST_CURSOR3    0xfU
60051 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
60054 #define M_SLEW_CTL0    0xfU
60059 #define M_SLEW_CTL1    0xfU
60064 #define M_SLEW_CTL2    0xfU
60068 #define S_SLEW_CTL3    0
60069 #define M_SLEW_CTL3    0xfU
60073 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
60076 #define M_SLICE_SEL_REG_BITS0_1    0x3U
60081 #define M_SLICE_SEL_REG_BITS2_3    0x3U
60086 #define M_SLICE_SEL_REG_BITS4_5    0x3U
60091 #define M_SLICE_SEL_REG_BITS6_7    0x3U
60096 #define M_SLICE_SEL_REG_BITS8_9    0x3U
60101 #define M_SLICE_SEL_REG_BITS10_11    0x3U
60106 #define M_SLICE_SEL_REG_BITS12_13    0x3U
60110 #define S_SLICE_SEL_REG_BITS14_15    0
60111 #define M_SLICE_SEL_REG_BITS14_15    0x3U
60115 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
60116 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
60119 #define M_POST_CUR_SEL_BITS0_1    0x3U
60124 #define M_POST_CUR_SEL_BITS2_3    0x3U
60129 #define M_POST_CUR_SEL_BITS4_5    0x3U
60134 #define M_POST_CUR_SEL_BITS6_7    0x3U
60139 #define M_POST_CUR_SEL_BITS8_9    0x3U
60144 #define M_POST_CUR_SEL_BITS10_11    0x3U
60149 #define M_POST_CUR_SEL_BITS12_13    0x3U
60153 #define S_POST_CUR_SEL_BITS14_15    0
60154 #define M_POST_CUR_SEL_BITS14_15    0x3U
60158 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
60159 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
60162 #define M_SLEW_CTL_SEL_BITS0_1    0x3U
60167 #define M_SLEW_CTL_SEL_BITS2_3    0x3U
60172 #define M_SLEW_CTL_SEL_BITS4_5    0x3U
60177 #define M_SLEW_CTL_SEL_BITS6_7    0x3U
60182 #define M_SLEW_CTL_SEL_BITS8_9    0x3U
60187 #define M_SLEW_CTL_SEL_BITS10_11    0x3U
60192 #define M_SLEW_CTL_SEL_BITS12_13    0x3U
60196 #define S_SLEW_CTL_SEL_BITS14_15    0
60197 #define M_SLEW_CTL_SEL_BITS14_15    0x3U
60201 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
60202 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
60205 #define M_ADR_LANE_0_11_PD    0xfffU
60209 #define S_ADR_LANE_12_15_PD    0
60210 #define M_ADR_LANE_12_15_PD    0xfU
60214 #define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
60215 #define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
60216 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
60217 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
60218 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
60219 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
60220 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
60221 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
60222 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
60223 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
60224 #define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
60227 #define M_ADR_TEST_MODE    0x3U
60231 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
60232 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
60233 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
60234 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
60235 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
60236 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
60237 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
60238 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
60239 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
60240 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
60241 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
60242 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
60243 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
60244 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
60245 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
60246 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
60247 #define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
60248 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
60251 #define M_PLL_TUNE_0_2    0x7U
60256 #define M_PLL_TUNECP_0_2    0x7U
60261 #define M_PLL_TUNEF_0_5    0x3fU
60266 #define M_PLL_TUNEVCO_0_1    0x3U
60270 #define S_PLL_PLLXTR_0_1    0
60271 #define M_PLL_PLLXTR_0_1    0x3U
60275 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
60276 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
60279 #define M_PLL_TUNETDIV_0_2    0x7U
60284 #define M_PLL_TUNEMDIV_0_1    0x3U
60293 #define M_VREG_RANGE_0_1    0x3U
60302 #define M_VREG_VCCTUNE_0_1    0x3U
60307 #define M_INTERP_SIG_SLEW_0_3    0xfU
60311 #define S_ANALOG_WRAPON    0
60315 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
60316 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
60323 #define M_SYSCLK_ROT_OVERRIDE    0x7fU
60351 #define S_CE0DLTVCC    0
60352 #define M_CE0DLTVCC    0x3U
60356 #define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
60357 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60360 #define M_TSYS_WRCLK    0x7fU
60364 #define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
60365 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
60372 #define M_SYSCLK_ROT    0x7fU
60385 #define M_SLEW_DONE_STATUS    0x3U
60389 #define S_SLEW_CNTL    0
60390 #define M_SLEW_CNTL    0xfU
60394 #define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
60395 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
60410 #define M_HS_PROBE_A_SEL_    0xfU
60415 #define M_HS_PROBE_B_SEL_    0xfU
60431 #define S_ATEST1CTL3    0
60435 #define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
60442 #define M_AD32S_HS_PROBE_A_SEL    0xfU
60447 #define M_AD32S_HS_PROBE_B_SEL    0xfU
60451 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
60453 #define S_GIANT_MUX_TEST_RESULTS    0
60454 #define M_GIANT_MUX_TEST_RESULTS    0xffffU
60458 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
60460 #define S_OUTPUT_DRIVER_FORCE_VALUE    0
60461 #define M_OUTPUT_DRIVER_FORCE_VALUE    0xffffU
60465 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
60466 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
60467 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
60482 #define M_SYSCLK_CLK_GATE    0x3U
60498 #define S_DVCC_REG_PD    0
60502 #define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
60503 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
60518 #define M_SLEW_CAL_OVERRIDE    0xfU
60522 #define S_SLEW_TARGET_PR_OFFSET    0
60523 #define M_SLEW_TARGET_PR_OFFSET    0x1fU
60527 #define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
60528 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
60531 #define M_DP18_PLL_LOCK    0x7fffU
60535 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
60538 #define M_AD32S_PLL_LOCK    0x3U
60542 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
60545 #define M_RANK_PAIR0_PRI    0x7U
60554 #define M_RANK_PAIR0_SEC    0x7U
60563 #define M_RANK_PAIR1_PRI    0x7U
60572 #define M_RANK_PAIR1_SEC    0x7U
60576 #define S_RANK_PAIR1_SEC_V    0
60580 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
60583 #define M_RANK_PAIR2_PRI    0x7U
60592 #define M_RANK_PAIR2_SEC    0x7U
60601 #define M_RANK_PAIR3_PRI    0x7U
60610 #define M_RANK_PAIR3_SEC    0x7U
60614 #define S_RANK_PAIR3_SEC_V    0
60618 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
60620 #define S_PERIODIC_BASE_CNTR0    0
60621 #define M_PERIODIC_BASE_CNTR0    0xffffU
60625 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
60631 #define S_PERIODIC_RELOAD_VALUE0    0
60632 #define M_PERIODIC_RELOAD_VALUE0    0x7fffU
60636 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
60638 #define S_PERIODIC_BASE_CNTR1    0
60639 #define M_PERIODIC_BASE_CNTR1    0xffffU
60643 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
60645 #define S_PERIODIC_CAL_TIMER    0
60646 #define M_PERIODIC_CAL_TIMER    0xffffU
60650 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
60652 #define S_PERIODIC_TIMER_RELOAD_VALUE    0
60653 #define M_PERIODIC_TIMER_RELOAD_VALUE    0xffffU
60657 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
60659 #define S_PERIODIC_ZCAL_TIMER    0
60660 #define M_PERIODIC_ZCAL_TIMER    0xffffU
60664 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
60665 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
60668 #define M_PER_ENA_RANK_PAIR    0xfU
60693 #define M_PER_NEXT_RANK_PAIR    0x3U
60717 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
60720 #define M_PROTOCOL_DDR    0xfU
60741 #define M_RANK_OVERRIDE_VALUE    0x7U
60758 #define M_DDRPHY_PROTOCOL    0xfU
60770 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
60773 #define M_WRITE_LATENCY_OFFSET    0xfU
60778 #define M_READ_LATENCY_OFFSET    0xfU
60799 #define M_MEMORY_TYPE    0x7U
60807 #define A_MC_DDRPHY_PC_RESETS 0x47038
60817 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
60820 #define M_PER_ZCAL_ENA_RANK    0xffU
60825 #define M_PER_ZCAL_NEXT_RANK    0x7U
60833 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
60868 #define M_RANK_GROUPING    0x3U
60892 #define S_ADDR_MIRROR_BG0_BG1    0
60896 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
60922 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
60948 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
60951 #define M_PVTP    0x1fU
60956 #define M_PVTN    0x1fU
60968 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
60975 #define M_VREFDQ0D    0xfU
60984 #define M_VREFDQ1D    0xfU
60996 #define S_ANALOG_PD_DIV    0
60997 #define M_ANALOG_PD_DIV    0x3U
61001 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
61051 #define S_ENA_RANK_PAIR    0
61052 #define M_ENA_RANK_PAIR    0xfU
61056 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
61059 #define M_REFRESH_COUNT    0xfU
61064 #define M_REFRESH_CONTROL    0x3U
61072 #define S_REFRESH_INTERVAL    0
61073 #define M_REFRESH_INTERVAL    0x7fU
61077 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
61123 #define S_ERROR_RANK_PAIR    0
61124 #define M_ERROR_RANK_PAIR    0xfU
61128 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
61131 #define M_INIT_CAL_COMPLETE    0xfU
61139 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
61185 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
61186 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
61188 #define S_MODEREGISTER0VALUE    0
61189 #define M_MODEREGISTER0VALUE    0xffffU
61193 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
61195 #define S_MODEREGISTER1VALUE    0
61196 #define M_MODEREGISTER1VALUE    0xffffU
61200 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
61202 #define S_MODEREGISTER2VALUE    0
61203 #define M_MODEREGISTER2VALUE    0xffffU
61207 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
61209 #define S_MODEREGISTER3VALUE    0
61210 #define M_MODEREGISTER3VALUE    0xffffU
61214 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
61215 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
61216 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
61217 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
61219 #define S_MODE_REGISTER_3_VALUE    0
61220 #define M_MODE_REGISTER_3_VALUE    0xffffU
61224 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
61226 #define S_DRD_WR_DATA_REG    0
61227 #define M_DRD_WR_DATA_REG    0xffffU
61231 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
61232 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
61243 #define M_MR_MASK_EN    0xfU
61271 #define S_X16_DEVICE    0
61275 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
61276 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
61277 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
61278 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
61279 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
61280 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
61295 #define M_MULTIPLE_REQ_SOURCE    0x7U
61300 #define M_INVALID_REQTYPE    0xfU
61305 #define M_INVALID_REQ_SOURCE    0x7U
61309 #define S_EARLY_REQ_SOURCE    0
61310 #define M_EARLY_REQ_SOURCE    0x7U
61314 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
61328 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
61331 #define M_ODT_WR_VALUES_BITS0_7    0xffU
61335 #define S_ODT_WR_VALUES_BITS8_15    0
61336 #define M_ODT_WR_VALUES_BITS8_15    0xffU
61340 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
61341 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
61342 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
61343 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
61346 #define M_ODT_RD_VALUES_X2    0xffU
61350 #define S_ODT_RD_VALUES_X2PLUS1    0
61351 #define M_ODT_RD_VALUES_X2PLUS1    0xffU
61355 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
61356 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
61357 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
61358 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
61361 #define M_TMOD_CYCLES    0xfU
61366 #define M_TRCD_CYCLES    0xfU
61371 #define M_TRP_CYCLES    0xfU
61375 #define S_TRFC_CYCLES    0
61376 #define M_TRFC_CYCLES    0xfU
61380 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
61383 #define M_TZQINIT_CYCLES    0xfU
61388 #define M_TZQCS_CYCLES    0xfU
61393 #define M_TWLDQSEN_CYCLES    0xfU
61397 #define S_TWRMRD_CYCLES    0
61398 #define M_TWRMRD_CYCLES    0xfU
61402 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
61405 #define M_TODTLON_OFF_CYCLES    0xfU
61410 #define M_TRC_CYCLES    0xfU
61415 #define M_TMRSC_CYCLES    0xfU
61419 #define S_MRS_CMD_SPACE    0
61420 #define M_MRS_CMD_SPACE    0xfU
61424 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
61427 #define M_GLOBAL_PHY_OFFSET    0xfU
61459 #define S_STAGGERED_PATTERN    0
61467 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
61470 #define M_OUTER_LOOP_CNT    0x3fffU
61474 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
61477 #define M_CONSEQ_PASS    0x1fU
61482 #define M_BURST_WINDOW    0x3U
61494 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
61500 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
61506 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
61509 #define M_FINE_CAL_STEP_SIZE    0x7U
61514 #define M_COARSE_CAL_STEP_SIZE    0xfU
61519 #define M_DQ_SEL_QUAD    0x3U
61524 #define M_DQ_SEL_LANE    0x7U
61528 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
61529 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
61532 #define M_TWLO_TWLOE    0xffU
61541 #define M_FW_WR_RD    0x3fU
61545 #define S_CUSTOM_INIT_WRITE    0
61549 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
61552 #define M_BIG_STEP    0xfU
61557 #define M_SMALL_STEP    0x7U
61562 #define M_WR_PRE_DLY    0x3fU
61566 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
61569 #define M_NUM_VALID_SAMPLES    0xfU
61574 #define M_FW_RD_WR    0x3fU
61578 #define S_EN_RESET_WR_DELAY_WL    0
61583 #define M_TWR_MPR    0xfU
61587 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
61593 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
61599 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
61606 #define M_MRS_CMD_DQ_ON    0x3fU
61611 #define M_MRS_CMD_DQ_OFF    0x3fU
61615 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
61625 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
61644 #define M_DEBUG_BUS_SEL_HI    0xfU
61648 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
61658 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
61668 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
61730 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
61764 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
61767 #define M_ATEST_CNTL    0x3fU
61771 #define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
61786 #define M_MT_GLOBAL_PHY_OFFSET    0xfU
61791 #define M_MT_DQ_SEL_QUAD    0x3U
61807 #define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
61814 #define M_MT_PVTP    0x1fU
61819 #define M_MT_PVTN    0x1fU
61823 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
61824 #define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
61830 #define S_MT_DP18_PLL_LOCK_SUM    0
61835 #define MC_1_BASE_ADDR 0x48000
61838 #define EDC_T50_BASE_ADDR 0x50000
61840 #define A_EDC_H_REF 0x50000
61854 #define A_EDC_H_BIST_CMD 0x50004
61855 #define A_EDC_H_BIST_CMD_ADDR 0x50008
61856 #define A_EDC_H_BIST_CMD_LEN 0x5000c
61857 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
61858 #define A_EDC_H_BIST_USER_WDATA0 0x50014
61859 #define A_EDC_H_BIST_USER_WDATA1 0x50018
61860 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
61861 #define A_EDC_H_BIST_NUM_ERR 0x50020
61862 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
61863 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
61864 #define A_EDC_H_PAR_ENABLE 0x50070
61866 #define S_PERR_PAR_ENABLE    0
61870 #define A_EDC_H_INT_ENABLE 0x50074
61871 #define A_EDC_H_INT_CAUSE 0x50078
61885 #define A_EDC_H_ECC_STATUS 0x5007c
61886 #define A_EDC_H_ECC_ERR_SEL 0x50080
61888 #define S_CFG    0
61889 #define M_CFG    0x3U
61893 #define A_EDC_H_ECC_ERR_ADDR 0x50084
61895 #define S_ECC_ADDR    0
61896 #define M_ECC_ADDR    0x7fffffU
61900 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
61901 #define A_EDC_H_BIST_CRC_SEED 0x50400
61904 #define EDC_T51_BASE_ADDR 0x50800
61907 #define HMA_T5_BASE_ADDR 0x51000
61909 #define A_HMA_TABLE_ACCESS 0x51000
61919 #define S_L_SEL    0
61920 #define M_L_SEL    0xfU
61924 #define A_HMA_TABLE_LINE0 0x51004
61926 #define S_CLIENT_EN    0
61927 #define M_CLIENT_EN    0x1fffU
61931 #define A_HMA_TABLE_LINE1 0x51008
61932 #define A_HMA_TABLE_LINE2 0x5100c
61933 #define A_HMA_TABLE_LINE3 0x51010
61934 #define A_HMA_TABLE_LINE4 0x51014
61935 #define A_HMA_TABLE_LINE5 0x51018
61938 #define M_FID    0x7ffU
61950 #define A_HMA_COOKIE 0x5101c
61957 #define M_C_FID    0x7ffU
61962 #define M_C_VAL    0x3ffU
61966 #define S_C_SEL    0
61967 #define M_C_SEL    0xfU
61971 #define A_HMA_PAR_ENABLE 0x51300
61972 #define A_HMA_INT_ENABLE 0x51304
61973 #define A_HMA_INT_CAUSE 0x51308
61976 #define EDC_T60_BASE_ADDR 0x50000
61979 #define M_QDR_CLKPHASE    0x7U
61984 #define M_MAXOPSPERTRC    0x7U
61989 #define M_NUMPIPESTAGES    0x3U
61993 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
61996 #define M_MCMDADDR    0xfffffU
62001 #define M_MCMDLEN    0x7fU
62021 #define S_MCMDVLD    0
62025 #define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
62035 #define S_MWDATA    0
62036 #define M_MWDATA    0x3fffffffU
62040 #define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
62050 #define S_MRSPDATA    0
62051 #define M_MRSPDATA    0x3fffffffU
62055 #define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
62058 #define M_BCMDADDR    0x7fffffU
62063 #define M_BCMDLEN    0x3fU
62075 #define S_BCMDVLD    0
62079 #define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
62089 #define S_BWDATA    0
62090 #define M_BWDATA    0x3fffffffU
62094 #define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
62104 #define S_BRSPDATA    0
62105 #define M_BRSPDATA    0x3fffffffU
62109 #define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
62112 #define M_EDRAMADDR    0xffffU
62117 #define M_EDRAMDWSN    0xffU
62122 #define M_EDRAMCRA    0x7U
62142 #define S_EDRAM0RDENLO    0
62146 #define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
62149 #define M_EDRAMWDATA    0x7fffffU
62153 #define S_EDRAMWBYTEEN    0
62154 #define M_EDRAMWBYTEEN    0x1ffU
62158 #define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
62159 #define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
62160 #define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
62161 #define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
62162 #define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
62163 #define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
62164 #define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
62165 #define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
62166 #define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
62167 #define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
62168 #define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
62169 #define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
62170 #define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
62171 #define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
62172 #define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
62173 #define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
62174 #define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
62175 #define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
62176 #define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
62177 #define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
62178 #define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
62179 #define A_EDC_H_DBG_FIFO_STATUS 0x50374
62218 #define M_RDDQ_RDCNT    0x1fU
62234 #define S_STG_WRDQ_NOTEMPTY    0
62238 #define A_EDC_H_DBG_FSM_STATE 0x50378
62244 #define S_CMDFSM    0
62245 #define M_CMDFSM    0x7U
62249 #define A_EDC_H_DBG_STALL_CYCLES 0x5037c
62327 #define S_DEAD_CYCLE1_POST_REF_RMW    0
62331 #define A_EDC_H_DBG_CMD_QUEUE 0x50380
62346 #define M_ECMDLEN    0x7fU
62350 #define S_ECMDADDR    0
62351 #define M_ECMDADDR    0x3fffffU
62355 #define A_EDC_H_DBG_REFRESH 0x50384
62366 #define M_REFPTR    0x7U
62370 #define S_REFCNT    0
62371 #define M_REFCNT    0xffU
62376 #define EDC_T61_BASE_ADDR 0x50800
62379 #define HMA_T6_BASE_ADDR 0x51000
62382 #define M_TPH    0x3U
62390 #define S_DCA    0
62391 #define M_DCA    0x7ffU
62395 #define A_HMA_CFG 0x51020
62401 #define A_HMA_TLB_ACCESS 0x51028
62411 #define S_E_SEL    0
62412 #define M_E_SEL    0x1fU
62416 #define A_HMA_TLB_BITS 0x5102c
62419 #define M_VA    0xfffffU
62435 #define S_REGION    0
62436 #define M_REGION    0x3U
62440 #define A_HMA_TLB_DESC_0_H 0x51030
62441 #define A_HMA_TLB_DESC_0_L 0x51034
62442 #define A_HMA_TLB_DESC_1_H 0x51038
62443 #define A_HMA_TLB_DESC_1_L 0x5103c
62444 #define A_HMA_TLB_DESC_2_H 0x51040
62445 #define A_HMA_TLB_DESC_2_L 0x51044
62446 #define A_HMA_TLB_DESC_3_H 0x51048
62447 #define A_HMA_TLB_DESC_3_L 0x5104c
62448 #define A_HMA_TLB_DESC_4_H 0x51050
62449 #define A_HMA_TLB_DESC_4_L 0x51054
62450 #define A_HMA_TLB_DESC_5_H 0x51058
62451 #define A_HMA_TLB_DESC_5_L 0x5105c
62452 #define A_HMA_TLB_DESC_6_H 0x51060
62453 #define A_HMA_TLB_DESC_6_L 0x51064
62454 #define A_HMA_TLB_DESC_7_H 0x51068
62455 #define A_HMA_TLB_DESC_7_L 0x5106c
62456 #define A_HMA_REG0_MIN 0x51070
62459 #define M_ADDR0_MIN    0xfffffU
62463 #define A_HMA_REG0_MAX 0x51074
62466 #define M_ADDR0_MAX    0xfffffU
62470 #define A_HMA_REG0_MASK 0x51078
62473 #define M_PAGE_SIZE0    0xfffffU
62477 #define A_HMA_REG0_BASE 0x5107c
62478 #define A_HMA_REG1_MIN 0x51080
62481 #define M_ADDR1_MIN    0xfffffU
62485 #define A_HMA_REG1_MAX 0x51084
62488 #define M_ADDR1_MAX    0xfffffU
62492 #define A_HMA_REG1_MASK 0x51088
62495 #define M_PAGE_SIZE1    0xfffffU
62499 #define A_HMA_REG1_BASE 0x5108c
62500 #define A_HMA_REG2_MIN 0x51090
62503 #define M_ADDR2_MIN    0xfffffU
62507 #define A_HMA_REG2_MAX 0x51094
62510 #define M_ADDR2_MAX    0xfffffU
62514 #define A_HMA_REG2_MASK 0x51098
62517 #define M_PAGE_SIZE2    0xfffffU
62521 #define A_HMA_REG2_BASE 0x5109c
62522 #define A_HMA_REG3_MIN 0x510a0
62525 #define M_ADDR3_MIN    0xfffffU
62529 #define A_HMA_REG3_MAX 0x510a4
62532 #define M_ADDR3_MAX    0xfffffU
62536 #define A_HMA_REG3_MASK 0x510a8
62539 #define M_PAGE_SIZE3    0xfffffU
62543 #define A_HMA_REG3_BASE 0x510ac
62544 #define A_HMA_SW_SYNC 0x510b0
62594 #define A_HMA_MA_MST_ERR 0x5130c
62595 #define A_HMA_RTF_ERR 0x51310
62596 #define A_HMA_OTF_ERR 0x51314
62597 #define A_HMA_IDTF_ERR 0x51318
62598 #define A_HMA_EXIT_TF 0x5131c
62612 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
62613 #define A_HMA_LOCAL_DEBUG_RPT 0x51324
62614 #define A_HMA_DEBUG_FSM_0 0xa000
62617 #define M_EDC_FSM    0x1fU
62622 #define M_RAS_FSM_SLV    0x7U
62627 #define M_FC_FSM    0x1fU
62632 #define M_COOKIE_ARB_FSM    0x3U
62637 #define M_PCIE_CHUNK_FSM    0x3U
62642 #define M_WTRANSFER_FSM    0x3U
62647 #define M_WD_FSM    0x3U
62651 #define S_RD_FSM    0
62652 #define M_RD_FSM    0x3U
62656 #define A_HMA_DEBUG_FSM_1 0xa001
62659 #define M_SYNC_FSM    0x3ffU
62664 #define M_OCHK_FSM    0x3U
62669 #define M_TLB_FSM    0xfU
62673 #define S_PIO_FSM    0
62674 #define M_PIO_FSM    0x1fU
62678 #define A_HMA_DEBUG_PCIE_INTF 0xa002
62729 #define M_PCIE_LEN    0xffU
62765 #define S_PCIE_TRRERR    0
62769 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
62770 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
62771 #define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
62774 #define M_REQDATA2    0xffU
62779 #define M_REQDATA1    0x7U
62783 #define S_REQDATA0    0
62784 #define M_REQDATA0    0x1fffffU
62788 #define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
62791 #define M_RSPDATA3    0xffU
62796 #define M_RSPDATA2    0xffU
62801 #define M_RSPDATA1    0xffU
62805 #define S_RSPDATA0    0
62806 #define M_RSPDATA0    0xffU
62810 #define A_HMA_DEBUG_MA_SLV_CTL 0xa007
62817 #define M_MA_CLNT    0xfU
62826 #define M_MA_LEN    0xffU
62850 #define S_MAS_TLB_ERR    0
62854 #define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
62855 #define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
62856 #define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
62857 #define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
62858 #define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
62865 #define M_LKP_DESC_SEL    0x7U
62869 #define S_LKP_RSP_VLD    0
62873 #define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
62874 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
62875 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
62876 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
62877 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
62878 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
62879 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
62880 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
62881 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
62882 #define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
62883 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
62884 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
62885 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
62886 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
62887 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
62888 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
62889 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
62890 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
62891 #define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
62894 #define M_WR_EOP_CNT    0xffU
62899 #define M_RD_SOP_CNT    0xffU
62903 #define S_RD_EOP_CNT    0
62904 #define M_RD_EOP_CNT    0xffU