Lines Matching +full:0 +full:xcf8

34 /* Directory name: t7_sw_reg.txt, Changeset: 5946:0b60ff298e7d */
36 #define MYPF_BASE 0x1b000
39 #define PF0_BASE 0x1e000
42 #define PF1_BASE 0x1e400
45 #define PF2_BASE 0x1e800
48 #define PF3_BASE 0x1ec00
51 #define PF4_BASE 0x1f000
54 #define PF5_BASE 0x1f400
57 #define PF6_BASE 0x1f800
60 #define PF7_BASE 0x1fc00
63 #define PF_STRIDE 0x400
67 #define VF_SGE_BASE 0x0
70 #define VF_MPS_BASE 0x100
73 #define VF_PL_BASE 0x200
76 #define VF_MBDATA_BASE 0x240
79 #define VF_CIM_BASE 0x300
82 #define MYPORT_BASE 0x1c000
85 #define PORT0_BASE 0x20000
88 #define PORT1_BASE 0x22000
91 #define PORT2_BASE 0x24000
94 #define PORT3_BASE 0x26000
97 #define PORT_STRIDE 0x2000
269 #define T5_MYPORT_BASE 0x2c000
272 #define T5_PORT0_BASE 0x30000
275 #define T5_PORT1_BASE 0x34000
278 #define T5_PORT2_BASE 0x38000
281 #define T5_PORT3_BASE 0x3c000
284 #define T5_PORT_STRIDE 0x4000
498 #define T7_MYPORT_BASE 0x2e000
501 #define T7_PORT0_BASE 0x30000
504 #define T7_PORT1_BASE 0x32000
507 #define T7_PORT2_BASE 0x34000
510 #define T7_PORT3_BASE 0x36000
513 #define T7_PORT_STRIDE 0x2000
668 #define SGE_BASE_ADDR 0x1000
670 #define A_SGE_PF_KDOORBELL 0x0
673 #define M_QID    0x1ffffU
681 #define S_PIDX    0
682 #define M_PIDX    0x3fffU
686 #define A_SGE_VF_KDOORBELL 0x0
692 #define S_PIDX_T5    0
693 #define M_PIDX_T5    0x1fffU
701 #define A_SGE_PF_GTS 0x4
704 #define M_INGRESSQID    0xffffU
709 #define M_TIMERREG    0x7U
717 #define S_CIDXINC    0
718 #define M_CIDXINC    0xfffU
722 #define A_SGE_VF_GTS 0x4
723 #define A_SGE_PF_KTIMESTAMP_LO 0x8
724 #define A_SGE_VF_KTIMESTAMP_LO 0x8
725 #define A_SGE_PF_KTIMESTAMP_HI 0xc
727 #define S_TSTAMPVAL    0
728 #define M_TSTAMPVAL    0xfffffffU
732 #define A_SGE_VF_KTIMESTAMP_HI 0xc
733 #define A_SGE_CONTROL 0x1008
740 #define M_FLSPLITMIN    0x1ffU
745 #define M_FLSPLITMODE    0x3U
774 #define M_PKTSHIFT    0x7U
779 #define M_INGPCIEBOUNDARY    0x7U
784 #define M_INGPADBOUNDARY    0x7U
789 #define M_EGRPCIEBOUNDARY    0x7U
793 #define S_GLOBALENABLE    0
798 #define M_NUMOFFID    0x7U
811 #define M_TF_MODE    0x3U
815 #define A_SGE_HOST_PAGE_SIZE 0x100c
818 #define M_HOSTPAGESIZEPF7    0xfU
823 #define M_HOSTPAGESIZEPF6    0xfU
828 #define M_HOSTPAGESIZEPF5    0xfU
833 #define M_HOSTPAGESIZEPF4    0xfU
838 #define M_HOSTPAGESIZEPF3    0xfU
843 #define M_HOSTPAGESIZEPF2    0xfU
848 #define M_HOSTPAGESIZEPF1    0xfU
852 #define S_HOSTPAGESIZEPF0    0
853 #define M_HOSTPAGESIZEPF0    0xfU
857 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
860 #define M_QUEUESPERPAGEPF7    0xfU
865 #define M_QUEUESPERPAGEPF6    0xfU
870 #define M_QUEUESPERPAGEPF5    0xfU
875 #define M_QUEUESPERPAGEPF4    0xfU
880 #define M_QUEUESPERPAGEPF3    0xfU
885 #define M_QUEUESPERPAGEPF2    0xfU
890 #define M_QUEUESPERPAGEPF1    0xfU
894 #define S_QUEUESPERPAGEPF0    0
895 #define M_QUEUESPERPAGEPF0    0xfU
899 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
902 #define M_QUEUESPERPAGEVFPF7    0xfU
907 #define M_QUEUESPERPAGEVFPF6    0xfU
912 #define M_QUEUESPERPAGEVFPF5    0xfU
917 #define M_QUEUESPERPAGEVFPF4    0xfU
922 #define M_QUEUESPERPAGEVFPF3    0xfU
927 #define M_QUEUESPERPAGEVFPF2    0xfU
932 #define M_QUEUESPERPAGEVFPF1    0xfU
936 #define S_QUEUESPERPAGEVFPF0    0
937 #define M_QUEUESPERPAGEVFPF0    0xfU
941 #define A_SGE_USER_MODE_LIMITS 0x1018
944 #define M_OPCODE_MIN    0xffU
949 #define M_OPCODE_MAX    0xffU
954 #define M_LENGTH_MIN    0xffU
958 #define S_LENGTH_MAX    0
959 #define M_LENGTH_MAX    0xffU
963 #define A_SGE_WR_ERROR 0x101c
965 #define S_WR_ERROR_OPCODE    0
966 #define M_WR_ERROR_OPCODE    0xffU
971 #define M_WR_SENDPATH_ERROR_OPCODE    0xffU
976 #define M_WR_SENDPATH_OPCODE    0xffU
980 #define A_SGE_PERR_INJECT 0x1020
983 #define M_MEMSEL    0x1fU
987 #define S_INJECTDATAERR    0
991 #define A_SGE_INT_CAUSE1 0x1024
1113 #define S_PERR_EGR_CTXT_MIFRSP    0
1145 #define A_SGE_INT_ENABLE1 0x1028
1146 #define A_SGE_PERR_ENABLE1 0x102c
1147 #define A_SGE_INT_CAUSE2 0x1030
1269 #define S_PERR_BASE_SIZE    0
1325 #define A_SGE_INT_ENABLE2 0x1034
1326 #define A_SGE_PERR_ENABLE2 0x1038
1327 #define A_SGE_INT_CAUSE3 0x103c
1453 #define S_ERR_INV_CTXT0    0
1465 #define A_SGE_INT_ENABLE3 0x1040
1466 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1469 #define CXGBE_M_SIZE    0xfffffffU
1474 #define M_T6_SIZE    0xfffffU
1478 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1479 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1480 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1481 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1482 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1483 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1484 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1485 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1486 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1487 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1488 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1489 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1490 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1491 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1492 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1493 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1496 #define M_BASEADDR    0x1fffffffU
1500 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1501 #define A_SGE_FLM_CACHE_BADDR 0x108c
1502 #define A_SGE_FLM_CFG 0x1090
1505 #define M_OPMODE    0x3fU
1514 #define M_CACHEPTRCNT    0x3U
1519 #define M_EDRAMPTRCNT    0x3U
1524 #define M_HDRSTARTFLQ    0x7U
1529 #define M_FETCHTHRESH    0x1fU
1534 #define M_CREDITCNT    0x3U
1538 #define S_NOEDRAM    0
1543 #define M_CREDITCNTPACKING    0x3U
1548 #define M_NULLPTR    0xfU
1560 #define A_SGE_CONM_CTRL 0x1094
1563 #define M_EGRTHRESHOLD    0x3fU
1568 #define M_INGTHRESHOLD    0x3fU
1576 #define S_TP_ENABLE    0
1581 #define M_EGRTHRESHOLDPACKING    0x3fU
1586 #define M_T6_EGRTHRESHOLDPACKING    0xffU
1591 #define M_T6_EGRTHRESHOLD    0xffU
1595 #define A_SGE_TIMESTAMP_LO 0x1098
1596 #define A_SGE_TIMESTAMP_HI 0x109c
1599 #define M_TSOP    0x3U
1603 #define S_TSVAL    0
1604 #define M_TSVAL    0xfffffffU
1608 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1611 #define M_THRESHOLD_0    0x3fU
1616 #define M_THRESHOLD_1    0x3fU
1621 #define M_THRESHOLD_2    0x3fU
1625 #define S_THRESHOLD_3    0
1626 #define M_THRESHOLD_3    0x3fU
1630 #define A_SGE_DBFIFO_STATUS 0x10a4
1633 #define M_HP_INT_THRESH    0xfU
1638 #define M_HP_COUNT    0x7ffU
1643 #define M_LP_INT_THRESH    0xfU
1647 #define S_LP_COUNT    0
1648 #define M_LP_COUNT    0x7ffU
1661 #define M_LP_INT_THRESH_T5    0xfffU
1665 #define S_LP_COUNT_T5    0
1666 #define M_LP_COUNT_T5    0x3ffffU
1671 #define M_VFIFO_CNT    0x1ffffU
1676 #define M_COAL_CTL_FIFO_CNT    0x3fU
1680 #define S_MERGE_FIFO_CNT    0
1681 #define M_MERGE_FIFO_CNT    0x3fU
1685 #define A_SGE_DOORBELL_CONTROL 0x10a8
1688 #define M_HINTDEPTHCTL    0x1fU
1697 #define M_HP_WEIGHT    0x3U
1746 #define M_DROP_TIMEOUT    0xfffU
1750 #define S_DROPPED_DB    0
1755 #define M_T6_DROP_TIMEOUT    0x3fU
1772 #define M_GTS_DBG_TIMER_REG    0x7U
1776 #define S_GTS_DBG_EN    0
1780 #define A_SGE_DROPPED_DOORBELL 0x10ac
1781 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1784 #define M_THROTTLE_COUNT    0xfffU
1788 #define S_THROTTLE_ENABLE    0
1793 #define M_BAR2THROTTLECOUNT    0xffU
1809 #define A_SGE_ITP_CONTROL 0x10b4
1812 #define M_CRITICAL_TIME    0x7fffU
1817 #define M_LL_EMPTY    0x3fU
1821 #define S_LL_READ_WAIT_DISABLE    0
1826 #define M_TSCALE    0xfU
1830 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1833 #define M_TIMERVALUE0    0xffffU
1837 #define S_TIMERVALUE1    0
1838 #define M_TIMERVALUE1    0xffffU
1842 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1845 #define M_TIMERVALUE2    0xffffU
1849 #define S_TIMERVALUE3    0
1850 #define M_TIMERVALUE3    0xffffU
1854 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1857 #define M_TIMERVALUE4    0xffffU
1861 #define S_TIMERVALUE5    0
1862 #define M_TIMERVALUE5    0xffffU
1866 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1873 #define M_MAXTAG0    0x7fU
1878 #define M_MAXRSPCNT0    0xffU
1887 #define M_MAXTAG1    0x7fU
1891 #define S_MAXRSPCNT1    0
1892 #define M_MAXRSPCNT1    0xffU
1896 #define A_SGE_GK_CONTROL 0x10c4
1903 #define M_FL_PROG_THRESH    0x1ffU
1920 #define M_DB_PROG_THRESH    0x1ffU
1924 #define S_100NS_TIMER    0
1925 #define M_100NS_TIMER    0xffU
1929 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1936 #define M_MAXTAG2    0x7fU
1941 #define M_MAXRSPCNT2    0xffU
1950 #define M_MAXTAG3    0x7fU
1954 #define S_MAXRSPCNT3    0
1955 #define M_MAXRSPCNT3    0xffU
1959 #define A_SGE_GK_CONTROL2 0x10c8
1962 #define M_DBQ_TIMER_TICK    0xffffU
1967 #define M_FL_MERGE_CNT_THRESH    0xfU
1971 #define S_MERGE_CNT_THRESH    0
1972 #define M_MERGE_CNT_THRESH    0x3fU
1976 #define A_SGE_DEBUG_INDEX 0x10cc
1977 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1978 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1979 #define A_SGE_REVISION 0x10d8
1980 #define A_SGE_INT_CAUSE4 0x10dc
2014 #define S_ERR_UNEXPECTED_TIMER    0
2126 #define A_SGE_INT_ENABLE4 0x10e0
2127 #define A_SGE_STAT_TOTAL 0x10e4
2128 #define A_SGE_STAT_MATCH 0x10e8
2129 #define A_SGE_STAT_CFG 0x10ec
2136 #define M_EGRCTXTOPMODE    0x3U
2141 #define M_INGCTXTOPMODE    0x3U
2146 #define M_STATMODE    0x3U
2150 #define S_STATSOURCE    0
2151 #define M_STATSOURCE    0x3U
2156 #define M_STATSOURCE_T5    0xfU
2160 #define S_T6_STATMODE    0
2161 #define M_T6_STATMODE    0xfU
2165 #define A_SGE_HINT_CFG 0x10f0
2168 #define M_HINTSALLOWEDNOHDR    0x3fU
2172 #define S_HINTSALLOWEDHDR    0
2173 #define M_HINTSALLOWEDHDR    0x3fU
2178 #define M_UPCUTOFFTHRESHLP    0x7ffU
2182 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
2183 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
2184 #define A_SGE_PD_WRR_CONFIG 0x10fc
2186 #define S_EDMA_WEIGHT    0
2187 #define M_EDMA_WEIGHT    0x3fU
2191 #define A_SGE_ERROR_STATS 0x1100
2201 #define S_ERROR_QID    0
2202 #define M_ERROR_QID    0x1ffffU
2207 #define M_CAUSE_REGISTER    0x7U
2212 #define M_CAUSE_BIT    0x1fU
2216 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
2219 #define M_MINTAG3    0xffU
2224 #define M_MINTAG2    0xffU
2229 #define M_MINTAG1    0xffU
2233 #define S_MINTAG0    0
2234 #define M_MINTAG0    0xffU
2238 #define A_SGE_IDMA0_DROP_CNT 0x1104
2239 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
2241 #define S_TAGPOOLTOTAL    0
2242 #define M_TAGPOOLTOTAL    0xffU
2246 #define A_SGE_IDMA1_DROP_CNT 0x1108
2247 #define A_SGE_INT_CAUSE5 0x110c
2373 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
2401 #define S_PERR_HINT_DELAY_FIFO    0
2405 #define A_SGE_INT_ENABLE5 0x1110
2406 #define A_SGE_PERR_ENABLE5 0x1114
2407 #define A_SGE_DBFIFO_STATUS2 0x1118
2410 #define M_FL_INT_THRESH    0xfU
2415 #define M_FL_COUNT    0x3ffU
2420 #define M_HP_INT_THRESH_T5    0xfU
2424 #define S_HP_COUNT_T5    0
2425 #define M_HP_COUNT_T5    0x3ffU
2429 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
2432 #define M_FETCHBURSTMAX0    0x3ffU
2436 #define S_FETCHBURSTMAX1    0
2437 #define M_FETCHBURSTMAX1    0x3ffU
2441 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
2444 #define M_FETCHBURSTMAX2    0x3ffU
2448 #define S_FETCHBURSTMAX3    0
2449 #define M_FETCHBURSTMAX3    0x3ffU
2453 #define A_SGE_CONTROL2 0x1124
2468 #define M_INGPACKBOUNDARY    0x7U
2501 #define M_HINTDEPTHCTLFL    0x1fU
2517 #define S_TX_COALESCE_PRI    0
2561 #define A_SGE_DEEP_SLEEP 0x1128
2607 #define S_EDMA0_SLEEP_REQ    0
2611 #define A_SGE_INT_CAUSE6 0x1128
2682 #define M_FATAL_DEQ_DRDY    0x3U
2687 #define M_FATAL_OUTP_DRDY    0x3U
2691 #define S_FATAL_DEQ    0
2696 #define M_FATAL_DEQ0_DRDY    0x7U
2701 #define M_FATAL_OUT0_DRDY    0x7U
2722 #define M_FATAL_DEQ1_DRDY    0x3U
2727 #define M_FATAL_OUT1_DRDY    0x3U
2731 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
2734 #define M_THROTTLE_THRESHOLD_FL    0xfU
2739 #define M_THROTTLE_THRESHOLD_HP    0xfU
2743 #define S_THROTTLE_THRESHOLD_LP    0
2744 #define M_THROTTLE_THRESHOLD_LP    0xfffU
2748 #define A_SGE_INT_ENABLE6 0x112c
2749 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2752 #define M_DBP_FETCH_THRESHOLD_FL    0xfU
2757 #define M_DBP_FETCH_THRESHOLD_HP    0xfU
2762 #define M_DBP_FETCH_THRESHOLD_LP    0xfffU
2782 #define S_DBP_FETCH_THRESHOLD_EN0    0
2786 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2789 #define M_DBP_FETCH_THRESHOLD_IQ1    0xffffU
2793 #define S_DBP_FETCH_THRESHOLD_IQ0    0
2794 #define M_DBP_FETCH_THRESHOLD_IQ0    0xffffU
2798 #define A_SGE_DBVFIFO_BADDR 0x1138
2799 #define A_SGE_DBVFIFO_SIZE 0x113c
2802 #define M_DBVFIFO_SIZE    0xfffU
2806 #define S_T6_DBVFIFO_SIZE    0
2807 #define M_T6_DBVFIFO_SIZE    0x1fffU
2811 #define A_SGE_DBFIFO_STATUS3 0x1140
2822 #define M_FL_INT_THRESH_LOW    0xfU
2827 #define M_HP_INT_THRESH_LOW    0xfU
2831 #define S_LP_INT_THRESH_LOW    0
2832 #define M_LP_INT_THRESH_LOW    0xfffU
2836 #define A_SGE_CHANGESET 0x1144
2837 #define A_SGE_PC_RSP_ERROR 0x1148
2838 #define A_SGE_TBUF_CONTROL 0x114c
2841 #define M_DBPTBUFRSV1    0x1ffU
2845 #define S_DBPTBUFRSV0    0
2846 #define M_DBPTBUFRSV0    0x1ffU
2850 #define A_SGE_TBUF_CONTROL0 0x114c
2851 #define A_SGE_TBUF_CONTROL1 0x1150
2854 #define M_DBPTBUFRSV3    0x1ffU
2858 #define S_DBPTBUFRSV2    0
2859 #define M_DBPTBUFRSV2    0x1ffU
2863 #define A_SGE_TBUF_CONTROL2 0x1154
2866 #define M_DBPTBUFRSV5    0x1ffU
2870 #define S_DBPTBUFRSV4    0
2871 #define M_DBPTBUFRSV4    0x1ffU
2875 #define A_SGE_TBUF_CONTROL3 0x1158
2878 #define M_DBPTBUFRSV7    0x1ffU
2882 #define S_DBPTBUFRSV6    0
2883 #define M_DBPTBUFRSV6    0x1ffU
2887 #define A_SGE_TBUF_CONTROL4 0x115c
2890 #define M_DBPTBUFRSV9    0x1ffU
2894 #define S_DBPTBUFRSV8    0
2895 #define M_DBPTBUFRSV8    0x1ffU
2899 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2900 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2901 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2902 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2903 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2904 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2905 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2906 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2907 #define A_SGE_DBQ_TIMER_THRESH0 0x11b8
2910 #define M_TXTIMETH3    0x3fU
2915 #define M_TXTIMETH2    0x3fU
2920 #define M_TXTIMETH1    0x3fU
2924 #define S_TXTIMETH0    0
2925 #define M_TXTIMETH0    0x3fU
2929 #define A_SGE_DBQ_TIMER_THRESH1 0x11bc
2932 #define M_TXTIMETH7    0x3fU
2937 #define M_TXTIMETH6    0x3fU
2942 #define M_TXTIMETH5    0x3fU
2946 #define S_TXTIMETH4    0
2947 #define M_TXTIMETH4    0x3fU
2951 #define A_SGE_DBQ_TIMER_CONFIG 0x11c0
2953 #define S_DBQ_TIMER_OP    0
2954 #define M_DBQ_TIMER_OP    0xffU
2958 #define A_SGE_DBQ_TIMER_DBG 0x11c4
2965 #define M_DBQ_TIMER_INDEX    0x3fU
2969 #define S_DBQ_TIMER_QCNT    0
2970 #define M_DBQ_TIMER_QCNT    0x1ffffU
2974 #define A_SGE_INT_CAUSE8 0x11c8
3008 #define S_T0_RXPERR    0
3012 #define A_SGE_INT_ENABLE8 0x11cc
3013 #define A_SGE_PERR_ENABLE8 0x11d0
3014 #define A_SGE_CTXT_CMD 0x11fc
3021 #define M_CTXTOP    0x3U
3026 #define M_CTXTTYPE    0x3U
3030 #define S_CTXTQID    0
3031 #define M_CTXTQID    0x1ffffU
3035 #define A_SGE_CTXT_DATA0 0x1200
3036 #define A_SGE_CTXT_DATA1 0x1204
3037 #define A_SGE_CTXT_DATA2 0x1208
3038 #define A_SGE_CTXT_DATA3 0x120c
3039 #define A_SGE_CTXT_DATA4 0x1210
3040 #define A_SGE_CTXT_DATA5 0x1214
3041 #define A_SGE_CTXT_DATA6 0x1218
3044 #define M_DATA_UNUSED    0x1ffffffU
3048 #define S_DATA6    0
3049 #define M_DATA6    0x7fU
3053 #define A_SGE_CTXT_DATA7 0x121c
3054 #define A_SGE_CTXT_MASK0 0x1220
3055 #define A_SGE_CTXT_MASK1 0x1224
3056 #define A_SGE_CTXT_MASK2 0x1228
3057 #define A_SGE_CTXT_MASK3 0x122c
3058 #define A_SGE_CTXT_MASK4 0x1230
3059 #define A_SGE_CTXT_MASK5 0x1234
3060 #define A_SGE_CTXT_MASK6 0x1238
3063 #define M_MASK_UNUSED    0x1ffffffU
3067 #define S_MASK    0
3068 #define M_MASK    0x7fU
3072 #define A_SGE_CTXT_MASK7 0x123c
3073 #define A_SGE_QBASE_MAP0 0x1240
3076 #define M_EGRESS0_SIZE    0x1fU
3081 #define M_EGRESS1_SIZE    0x1fU
3086 #define M_INGRESS0_SIZE    0x1fU
3094 #define A_SGE_QBASE_MAP1 0x1244
3096 #define S_EGRESS0_BASE    0
3097 #define M_EGRESS0_BASE    0x1ffffU
3101 #define A_SGE_QBASE_MAP2 0x1248
3103 #define S_EGRESS1_BASE    0
3104 #define M_EGRESS1_BASE    0x1ffffU
3108 #define A_SGE_QBASE_MAP3 0x124c
3111 #define M_INGRESS1_BASE_256VF    0xffffU
3115 #define S_INGRESS0_BASE    0
3116 #define M_INGRESS0_BASE    0xffffU
3120 #define A_SGE_QBASE_INDEX 0x1250
3122 #define S_QIDX    0
3123 #define M_QIDX    0x1ffU
3127 #define A_SGE_CONM_CTRL2 0x1254
3130 #define M_FLMTHRESHPACK    0x7fU
3134 #define S_FLMTHRESH    0
3135 #define M_FLMTHRESH    0x7fU
3143 #define A_SGE_DEBUG_CONM 0x1258
3146 #define M_MPS_CH_CNG    0xffffU
3151 #define M_TP_CH_CNG    0x3U
3156 #define M_ST_CONG    0x3U
3164 #define S_LAST_QID    0
3165 #define M_LAST_QID    0x3ffU
3170 #define M_CH_CNG    0xffffU
3175 #define M_CH_SEL    0x3U
3179 #define A_SGE_DBG_QUEUE_STAT0_CTRL 0x125c
3189 #define S_DB_GTS_QID    0
3190 #define M_DB_GTS_QID    0x1ffffU
3194 #define A_SGE_DBG_QUEUE_STAT1_CTRL 0x1260
3195 #define A_SGE_DBG_QUEUE_STAT0 0x1264
3196 #define A_SGE_DBG_QUEUE_STAT1 0x1268
3197 #define A_SGE_DBG_BAR2_PKT_CNT 0x126c
3198 #define A_SGE_DBG_DB_PKT_CNT 0x1270
3199 #define A_SGE_DBG_GTS_PKT_CNT 0x1274
3200 #define A_SGE_DEBUG_DATA_HIGH_INDEX_16 0x1278
3201 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
3204 #define M_CIM_WM    0x3U
3209 #define M_DEBUG_UP_SOP_CNT    0xfU
3214 #define M_DEBUG_UP_EOP_CNT    0xfU
3219 #define M_DEBUG_CIM_SOP1_CNT    0xfU
3224 #define M_DEBUG_CIM_EOP1_CNT    0xfU
3229 #define M_DEBUG_CIM_SOP0_CNT    0xfU
3233 #define S_DEBUG_CIM_EOP0_CNT    0
3234 #define M_DEBUG_CIM_EOP0_CNT    0xfU
3239 #define M_DEBUG_BAR2_SOP_CNT    0xfU
3244 #define M_DEBUG_BAR2_EOP_CNT    0xfU
3248 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
3251 #define M_DEBUG_T_RX_SOP1_CNT    0xfU
3256 #define M_DEBUG_T_RX_EOP1_CNT    0xfU
3261 #define M_DEBUG_T_RX_SOP0_CNT    0xfU
3266 #define M_DEBUG_T_RX_EOP0_CNT    0xfU
3271 #define M_DEBUG_U_RX_SOP1_CNT    0xfU
3276 #define M_DEBUG_U_RX_EOP1_CNT    0xfU
3281 #define M_DEBUG_U_RX_SOP0_CNT    0xfU
3285 #define S_DEBUG_U_RX_EOP0_CNT    0
3286 #define M_DEBUG_U_RX_EOP0_CNT    0xfU
3290 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
3293 #define M_DEBUG_UD_RX_SOP3_CNT    0xfU
3298 #define M_DEBUG_UD_RX_EOP3_CNT    0xfU
3303 #define M_DEBUG_UD_RX_SOP2_CNT    0xfU
3308 #define M_DEBUG_UD_RX_EOP2_CNT    0xfU
3313 #define M_DEBUG_UD_RX_SOP1_CNT    0xfU
3318 #define M_DEBUG_UD_RX_EOP1_CNT    0xfU
3323 #define M_DEBUG_UD_RX_SOP0_CNT    0xfU
3327 #define S_DEBUG_UD_RX_EOP0_CNT    0
3328 #define M_DEBUG_UD_RX_EOP0_CNT    0xfU
3333 #define M_DBG_TBUF_USED1    0x1ffU
3337 #define S_DBG_TBUF_USED0    0
3338 #define M_DBG_TBUF_USED0    0x1ffU
3342 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
3345 #define M_DEBUG_U_TX_SOP3_CNT    0xfU
3350 #define M_DEBUG_U_TX_EOP3_CNT    0xfU
3355 #define M_DEBUG_U_TX_SOP2_CNT    0xfU
3360 #define M_DEBUG_U_TX_EOP2_CNT    0xfU
3365 #define M_DEBUG_U_TX_SOP1_CNT    0xfU
3370 #define M_DEBUG_U_TX_EOP1_CNT    0xfU
3375 #define M_DEBUG_U_TX_SOP0_CNT    0xfU
3379 #define S_DEBUG_U_TX_EOP0_CNT    0
3380 #define M_DEBUG_U_TX_EOP0_CNT    0xfU
3384 #define A_SGE_DEBUG1_DBP_THREAD 0x128c
3387 #define M_WR_DEQ_CNT    0xfU
3392 #define M_WR_ENQ_CNT    0xfU
3397 #define M_FL_DEQ_CNT    0xfU
3401 #define S_FL_ENQ_CNT    0
3402 #define M_FL_ENQ_CNT    0xfU
3406 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
3409 #define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
3414 #define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
3419 #define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
3424 #define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
3429 #define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
3434 #define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
3439 #define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
3443 #define S_DEBUG_PC_REQ_EOP0_CNT    0
3444 #define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
3448 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
3451 #define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
3456 #define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
3461 #define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
3466 #define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
3471 #define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
3476 #define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
3481 #define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
3485 #define S_DEBUG_PD_RDREQ_EOP0_CNT    0
3486 #define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
3490 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
3493 #define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
3498 #define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
3503 #define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
3508 #define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
3513 #define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
3518 #define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
3523 #define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
3527 #define S_DEBUG_PD_RDRSP_EOP0_CNT    0
3528 #define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
3532 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
3535 #define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
3540 #define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
3545 #define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
3550 #define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
3555 #define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
3560 #define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
3565 #define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
3569 #define S_DEBUG_PD_WRREQ_EOP0_CNT    0
3570 #define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
3575 #define M_DEBUG_PC_RSP_SOP_CNT    0xfU
3580 #define M_DEBUG_PC_RSP_EOP_CNT    0xfU
3585 #define M_DEBUG_PC_REQ_SOP_CNT    0xfU
3590 #define M_DEBUG_PC_REQ_EOP_CNT    0xfU
3594 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
3601 #define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
3606 #define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
3647 #define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
3652 #define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
3657 #define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
3661 #define S_DEBUG_PD_WRREQ_INT0_CNT    0
3662 #define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
3674 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
3677 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
3682 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
3687 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
3692 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
3697 #define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
3702 #define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
3707 #define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
3711 #define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
3712 #define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
3716 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
3719 #define M_DEBUG_T_RXAFULL_D    0x3U
3724 #define M_DEBUG_PD_RDRSPAFULL_D    0xfU
3729 #define M_DEBUG_PD_RDREQAFULL_D    0xfU
3734 #define M_DEBUG_PD_WRREQAFULL_D    0xfU
3739 #define M_DEBUG_PC_RSPAFULL_D    0x7U
3744 #define M_DEBUG_PC_REQAFULL_D    0x7U
3749 #define M_DEBUG_U_TXAFULL_D    0xfU
3754 #define M_DEBUG_UD_RXAFULL_D    0xfU
3759 #define M_DEBUG_U_RXAFULL_D    0x3U
3763 #define S_DEBUG_CIM_AFULL_D    0
3764 #define M_DEBUG_CIM_AFULL_D    0x3U
3769 #define M_DEBUG_IDMA1_S_CPL_FLIT_REMAINING    0xfU
3802 #define M_DEBUG_IDMA0_S_CPL_FLIT_REMAINING    0xfU
3835 #define M_T6_DEBUG_T_RXAFULL_D    0x3U
3840 #define M_T6_DEBUG_PD_WRREQAFULL_D    0x3U
3852 #define S_T6_DEBUG_CIM_AFULL_D    0
3856 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
3875 #define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
3880 #define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
3901 #define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
3905 #define S_DEBUG_ST_FLM_IDMA0_CTXT    0
3906 #define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
3910 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
3913 #define M_DEBUG_CPLSW_SOP1_CNT    0xfU
3918 #define M_DEBUG_CPLSW_EOP1_CNT    0xfU
3923 #define M_DEBUG_CPLSW_SOP0_CNT    0xfU
3928 #define M_DEBUG_CPLSW_EOP0_CNT    0xfU
3933 #define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
3938 #define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
3943 #define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
3947 #define S_DEBUG_PC_REQ_EOP2_CNT    0
3948 #define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
3953 #define M_DEBUG_IDMA1_ISHIFT_TX_SIZE    0x7fU
3957 #define S_DEBUG_IDMA0_ISHIFT_TX_SIZE    0
3958 #define M_DEBUG_IDMA0_ISHIFT_TX_SIZE    0x7fU
3962 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
3963 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
3964 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
3965 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
3968 #define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
3973 #define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
3978 #define M_DEBUG_ST_IMSG_CTXT    0x7U
3983 #define M_DEBUG_ST_IMSG    0x1fU
3988 #define M_DEBUG_ST_IDMA1_IALN    0x3U
3993 #define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
3998 #define M_DEBUG_ST_IDMA0_IALN    0x3U
4002 #define S_DEBUG_ST_IDMA0_IDMA_SM    0
4003 #define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
4015 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
4018 #define M_DEBUG_ITP_EMPTY    0x3fU
4023 #define M_DEBUG_ITP_EXPIRED    0x3fU
4039 #define S_DEBUG_ITP_EVR_STATE    0
4040 #define M_DEBUG_ITP_EVR_STATE    0x7U
4044 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
4047 #define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
4052 #define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
4057 #define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
4062 #define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
4067 #define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
4071 #define S_DEBUG_ST_DBP_THREAD0_MAIN    0
4072 #define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
4077 #define M_T6_DEBUG_ST_DBP_UPCP_MAIN    0x7U
4081 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
4084 #define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
4093 #define M_DEBUG_ST_DBP_CTXT    0x7U
4098 #define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
4102 #define S_DEBUG_ST_DBP_THREAD3_MAIN    0
4103 #define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
4107 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
4110 #define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
4115 #define M_DEBUG_ST_EDMA3_ALIGN    0x3U
4120 #define M_DEBUG_ST_EDMA3_REQ    0x7U
4125 #define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
4130 #define M_DEBUG_ST_EDMA2_ALIGN    0x3U
4135 #define M_DEBUG_ST_EDMA2_REQ    0x7U
4140 #define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
4145 #define M_DEBUG_ST_EDMA1_ALIGN    0x3U
4150 #define M_DEBUG_ST_EDMA1_REQ    0x7U
4155 #define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
4160 #define M_DEBUG_ST_EDMA0_ALIGN    0x3U
4164 #define S_DEBUG_ST_EDMA0_REQ    0
4165 #define M_DEBUG_ST_EDMA0_REQ    0x7U
4169 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
4172 #define M_DEBUG_ST_FLM_DBPTR    0x3U
4177 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
4182 #define M_DEBUG_FLM_CACHE_AGENT    0x7U
4187 #define M_DEBUG_ST_FLM_CACHE    0xfU
4195 #define S_DEBUG_FLM_DBPTR_QID    0
4196 #define M_DEBUG_FLM_DBPTR_QID    0xfffU
4200 #define A_SGE_DEBUG0_DBP_THREAD 0x12d4
4203 #define M_THREAD_ST_MAIN    0x3fU
4208 #define M_THREAD_ST_CIMFL    0xfU
4213 #define M_THREAD_CMDOP    0xfU
4217 #define S_THREAD_QID    0
4218 #define M_THREAD_QID    0x1ffffU
4222 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
4224 #define S_DEBUG_DBP_THREAD0_QID    0
4225 #define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
4229 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
4231 #define S_DEBUG_DBP_THREAD1_QID    0
4232 #define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
4236 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
4238 #define S_DEBUG_DBP_THREAD2_QID    0
4239 #define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
4243 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
4245 #define S_DEBUG_DBP_THREAD3_QID    0
4246 #define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
4250 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
4253 #define M_DEBUG_IMSG_CPL    0xffU
4257 #define S_DEBUG_IMSG_QID    0
4258 #define M_DEBUG_IMSG_QID    0xffffU
4262 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
4265 #define M_DEBUG_IDMA1_QID    0xffffU
4269 #define S_DEBUG_IDMA0_QID    0
4270 #define M_DEBUG_IDMA0_QID    0xffffU
4274 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
4277 #define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
4281 #define S_DEBUG_IDMA0_FLM_REQ_QID    0
4282 #define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
4286 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
4287 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
4288 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
4289 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
4292 #define M_EGRESS_LOG2SIZE    0x1fU
4297 #define M_EGRESS_BASE    0x1ffffU
4302 #define M_INGRESS2_LOG2SIZE    0x1fU
4306 #define S_INGRESS1_LOG2SIZE    0
4307 #define M_INGRESS1_LOG2SIZE    0x1fU
4312 #define M_EGRESS_SIZE    0x1fU
4317 #define M_INGRESS2_SIZE    0x1fU
4321 #define S_INGRESS1_SIZE    0
4322 #define M_INGRESS1_SIZE    0x1fU
4326 #define A_SGE_WC_EGRS_BAR2_OFF_PF 0x1300
4329 #define M_PFIQSPERPAGE    0xfU
4334 #define M_PFEQSPERPAGE    0xfU
4339 #define M_PFWCQSPERPAGE    0xfU
4348 #define M_PFMAXWCSIZE    0x3U
4352 #define S_PFWCOFFSET    0
4353 #define M_PFWCOFFSET    0x1ffffU
4357 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
4360 #define M_INGRESS2_BASE    0xffffU
4364 #define S_INGRESS1_BASE    0
4365 #define M_INGRESS1_BASE    0xffffU
4369 #define A_SGE_WC_EGRS_BAR2_OFF_VF 0x1320
4372 #define M_VFIQSPERPAGE    0xfU
4377 #define M_VFEQSPERPAGE    0xfU
4382 #define M_VFWCQSPERPAGE    0xfU
4391 #define M_VFMAXWCSIZE    0x3U
4395 #define S_VFWCOFFSET    0
4396 #define M_VFWCOFFSET    0x1ffffU
4400 #define A_SGE_DEBUG_DATA_HIGH_INDEX_17 0x1340
4401 #define A_SGE_DEBUG_DATA_HIGH_INDEX_18 0x1344
4402 #define A_SGE_DEBUG_DATA_HIGH_INDEX_19 0x1348
4403 #define A_SGE_DEBUG_DATA_HIGH_INDEX_20 0x134c
4404 #define A_SGE_DEBUG_DATA_HIGH_INDEX_21 0x1350
4405 #define A_SGE_DEBUG_DATA_LOW_INDEX_16 0x1354
4406 #define A_SGE_DEBUG_DATA_LOW_INDEX_17 0x1358
4407 #define A_SGE_DEBUG_DATA_LOW_INDEX_18 0x135c
4408 #define A_SGE_INT_CAUSE7 0x1360
4510 #define S_CERR_FLM_L1CACHE    0
4514 #define A_SGE_INT_ENABLE7 0x1364
4515 #define A_SGE_PERR_ENABLE7 0x1368
4516 #define A_SGE_ING_COMP_COAL_CFG 0x1700
4535 #define M_COMP_COAL_TIMER_CNT    0xffU
4540 #define M_COMP_COAL_CNTR_TH    0xffU
4544 #define S_COMP_COAL_OPCODE    0
4545 #define M_COMP_COAL_OPCODE    0xffU
4549 #define A_SGE_ING_IMSG_DBG 0x1704
4552 #define M_STUCK_CTR_TH    0xffU
4556 #define S_STUCK_INT_EN    0
4560 #define A_SGE_ING_IMSG_RSP0_DBG 0x1708
4563 #define M_IDMA1_QID    0xffffU
4567 #define S_IDMA0_QID    0
4568 #define M_IDMA0_QID    0xffffU
4572 #define A_SGE_ING_IMSG_RSP1_DBG 0x170c
4575 #define M_IDMA3_QID    0xffffU
4579 #define S_IDMA2_QID    0
4580 #define M_IDMA2_QID    0xffffU
4584 #define A_SGE_LB_MODE 0x1710
4586 #define S_LB_MODE    0
4587 #define M_LB_MODE    0x3U
4591 #define A_SGE_IMSG_QUESCENT 0x1714
4593 #define S_IMSG_QUESCENT    0
4597 #define A_SGE_LA_CTRL 0x1718
4631 #define S_DBP_ID_CHK_VLD    0
4635 #define A_SGE_LA_CTRL_EQID_LOW 0x171c
4637 #define S_EQ_ID_CHK_LOW    0
4638 #define M_EQ_ID_CHK_LOW    0x1ffffU
4642 #define A_SGE_LA_CTRL_EQID_HIGH 0x1720
4644 #define S_EQ_ID_CHK_HIGH    0
4645 #define M_EQ_ID_CHK_HIGH    0x1ffffU
4649 #define A_SGE_LA_CTRL_IQID 0x1724
4652 #define M_IQ_ID_CHK_HIGH    0xffffU
4656 #define S_IQ_ID_CHK_LOW    0
4657 #define M_IQ_ID_CHK_LOW    0xffffU
4661 #define A_SGE_LA_CTRL_TID_LOW 0x1728
4663 #define S_TID_CHK_LOW    0
4664 #define M_TID_CHK_LOW    0xffffffU
4668 #define A_SGE_LA_CTRL_TID_HIGH 0x172c
4670 #define S_TID_CHK_HIGH    0
4671 #define M_TID_CHK_HIGH    0xffffffU
4675 #define A_SGE_CFG_TP_ERR 0x173c
4678 #define M_TP_ERR_STATUS_CH3    0x3U
4683 #define M_TP_ERR_STATUS_CH2    0x3U
4688 #define M_TP_ERR_STATUS_CH1    0x3U
4693 #define M_TP_ERR_STATUS_CH0    0x3U
4698 #define M_CPL0_SIZE    0xffU
4703 #define M_CPL1_SIZE    0xffU
4719 #define S_SIZE_CHANGE_42913    0
4723 #define A_SGE_CHNL0_CTX_ERROR_COUNT_PER_TID 0x1740
4724 #define A_SGE_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1744
4725 #define A_SGE_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1748
4726 #define A_SGE_CHNL3_CTX_ERROR_COUNT_PER_TID 0x174c
4727 #define A_SGE_CTX_ACC_CH0 0x1750
4730 #define M_RDMA_INV_HANDLING    0x3U
4742 #define A_SGE_CTX_ACC_CH1 0x1754
4743 #define A_SGE_CTX_ACC_CH2 0x1758
4744 #define A_SGE_CTX_ACC_CH3 0x175c
4745 #define A_SGE_CTX_BASE 0x1760
4746 #define A_SGE_LA_RDPTR_0 0x1800
4747 #define A_SGE_LA_RDDATA_0 0x1804
4748 #define A_SGE_LA_WRPTR_0 0x1808
4749 #define A_SGE_LA_RESERVED_0 0x180c
4750 #define A_SGE_LA_RDPTR_1 0x1810
4751 #define A_SGE_LA_RDDATA_1 0x1814
4752 #define A_SGE_LA_WRPTR_1 0x1818
4753 #define A_SGE_LA_RESERVED_1 0x181c
4754 #define A_SGE_LA_RDPTR_2 0x1820
4755 #define A_SGE_LA_RDDATA_2 0x1824
4756 #define A_SGE_LA_WRPTR_2 0x1828
4757 #define A_SGE_LA_RESERVED_2 0x182c
4758 #define A_SGE_LA_RDPTR_3 0x1830
4759 #define A_SGE_LA_RDDATA_3 0x1834
4760 #define A_SGE_LA_WRPTR_3 0x1838
4761 #define A_SGE_LA_RESERVED_3 0x183c
4762 #define A_SGE_LA_RDPTR_4 0x1840
4763 #define A_SGE_LA_RDDATA_4 0x1844
4764 #define A_SGE_LA_WRPTR_4 0x1848
4765 #define A_SGE_LA_RESERVED_4 0x184c
4766 #define A_SGE_LA_RDPTR_5 0x1850
4767 #define A_SGE_LA_RDDATA_5 0x1854
4768 #define A_SGE_LA_WRPTR_5 0x1858
4769 #define A_SGE_LA_RESERVED_5 0x185c
4770 #define A_SGE_LA_RDPTR_6 0x1860
4771 #define A_SGE_LA_RDDATA_6 0x1864
4772 #define A_SGE_LA_WRPTR_6 0x1868
4773 #define A_SGE_LA_RESERVED_6 0x186c
4774 #define A_SGE_LA_RDPTR_7 0x1870
4775 #define A_SGE_LA_RDDATA_7 0x1874
4776 #define A_SGE_LA_WRPTR_7 0x1878
4777 #define A_SGE_LA_RESERVED_7 0x187c
4778 #define A_SGE_LA_RDPTR_8 0x1880
4779 #define A_SGE_LA_RDDATA_8 0x1884
4780 #define A_SGE_LA_WRPTR_8 0x1888
4781 #define A_SGE_LA_RESERVED_8 0x188c
4782 #define A_SGE_LA_RDPTR_9 0x1890
4783 #define A_SGE_LA_RDDATA_9 0x1894
4784 #define A_SGE_LA_WRPTR_9 0x1898
4785 #define A_SGE_LA_RESERVED_9 0x189c
4786 #define A_SGE_LA_RDPTR_10 0x18a0
4787 #define A_SGE_LA_RDDATA_10 0x18a4
4788 #define A_SGE_LA_WRPTR_10 0x18a8
4789 #define A_SGE_LA_RESERVED_10 0x18ac
4790 #define A_SGE_LA_RDPTR_11 0x18b0
4791 #define A_SGE_LA_RDDATA_11 0x18b4
4792 #define A_SGE_LA_WRPTR_11 0x18b8
4793 #define A_SGE_LA_RESERVED_11 0x18bc
4794 #define A_SGE_LA_RDPTR_12 0x18c0
4795 #define A_SGE_LA_RDDATA_12 0x18c4
4796 #define A_SGE_LA_WRPTR_12 0x18c8
4797 #define A_SGE_LA_RESERVED_12 0x18cc
4798 #define A_SGE_LA_RDPTR_13 0x18d0
4799 #define A_SGE_LA_RDDATA_13 0x18d4
4800 #define A_SGE_LA_WRPTR_13 0x18d8
4801 #define A_SGE_LA_RESERVED_13 0x18dc
4802 #define A_SGE_LA_RDPTR_14 0x18e0
4803 #define A_SGE_LA_RDDATA_14 0x18e4
4804 #define A_SGE_LA_WRPTR_14 0x18e8
4805 #define A_SGE_LA_RESERVED_14 0x18ec
4806 #define A_SGE_LA_RDPTR_15 0x18f0
4807 #define A_SGE_LA_RDDATA_15 0x18f4
4808 #define A_SGE_LA_WRPTR_15 0x18f8
4809 #define A_SGE_LA_RESERVED_15 0x18fc
4812 #define PCIE_BASE_ADDR 0x3000
4814 #define A_PCIE_PF_CFG 0x40
4829 #define M_AIVEC    0x3ffU
4834 #define M_INTXTYPE    0x3U
4842 #define S_CLIDECEN    0
4846 #define A_PCIE_PF_CLI 0x44
4847 #define A_PCIE_PF_GEN_MSG 0x48
4849 #define S_MSGTYPE    0
4850 #define M_MSGTYPE    0xffU
4854 #define A_PCIE_PF_EXPROM_OFST 0x4c
4857 #define M_OFFSET    0x3fffU
4861 #define A_PCIE_INT_ENABLE 0x3000
4983 #define S_MSIADDRLPERR    0
5071 #define S_MSTGRPPERR    0
5075 #define A_PCIE_INT_CAUSE 0x3004
5076 #define A_PCIE_PERR_ENABLE 0x3008
5082 #define A_PCIE_PERR_INJECT 0x300c
5084 #define S_IDE    0
5089 #define M_MEMSEL_PCIE    0x1fU
5093 #define A_PCIE_NONFAT_ERR 0x3010
5131 #define S_CFGSNP    0
5227 #define A_PCIE_CFG 0x3014
5230 #define M_CFGDMAXPYLDSZRX    0x7U
5235 #define M_CFGDMAXPYLDSZTX    0x7U
5240 #define M_CFGDMAXRDREQSZ    0x7U
5289 #define M_AI_TCVAL    0x7U
5313 #define S_LINKDNRSTEN    0
5322 #define M_DIAGCTRLBUS    0x7U
5335 #define M_CFGDMAXPYLDSZ    0x7U
5348 #define M_T5VPDREQPROTECT    0x3U
5368 #define A_PCIE_DMA_CTRL 0x3018
5374 #define A_PCIE_CFG2 0x3018
5377 #define M_VPDTIMER    0xffffU
5382 #define M_BAR2TIMER    0xfffU
5390 #define S_TOTMAXTAG    0
5391 #define M_TOTMAXTAG    0x3U
5395 #define S_T6_TOTMAXTAG    0
5396 #define M_T6_TOTMAXTAG    0x7U
5408 #define A_PCIE_DMA_CFG 0x301c
5411 #define M_MAXPYLDSIZE    0x7U
5416 #define M_MAXRDREQSIZE    0x7U
5421 #define M_DMA_MAXRSPCNT    0x1ffU
5426 #define M_DMA_MAXREQCNT    0xffU
5430 #define S_MAXTAG    0
5431 #define M_MAXTAG    0x7fU
5435 #define A_PCIE_CFG3 0x301c
5442 #define M_FLRPNDCPLMODE    0x3U
5454 #define S_DMADCASTFIRSTONLY    0
5462 #define A_PCIE_DMA_STAT 0x3020
5465 #define M_STATEREQ    0xfU
5470 #define M_DMA_RSPCNT    0xfffU
5475 #define M_STATEAREQ    0x7U
5483 #define S_DMA_REQCNT    0
5484 #define M_DMA_REQCNT    0x7ffU
5488 #define A_PCIE_CFG4 0x3020
5506 #define S_GENPME    0
5507 #define M_GENPME    0xffU
5511 #define A_PCIE_CFG5 0x3024
5521 #define S_HOLDCPLENTERINGL1    0
5525 #define A_PCIE_CFG6 0x3028
5528 #define M_PERSTTIMERCOUNT    0x3fffU
5536 #define S_PERSTTIMER    0
5537 #define M_PERSTTIMER    0xfU
5541 #define A_PCIE_CFG7 0x302c
5542 #define A_PCIE_INT_ENABLE_EXT 0x3030
5652 #define S_MSTGRPCERR    0
5656 #define A_PCIE_INT_ENABLE_X8 0x3034
5690 #define A_PCIE_INT_CAUSE_EXT 0x3038
5691 #define A_PCIE_CMD_CTRL 0x303c
5692 #define A_PCIE_INT_CAUSE_X8 0x303c
5693 #define A_PCIE_CMD_CFG 0x3040
5696 #define M_MAXRSPCNT    0xfU
5701 #define M_MAXREQCNT    0x1fU
5705 #define A_PCIE_PERR_ENABLE_EXT 0x3040
5739 #define A_PCIE_CMD_STAT 0x3044
5742 #define M_RSPCNT    0x7fU
5746 #define S_REQCNT    0
5747 #define M_REQCNT    0xffU
5751 #define A_PCIE_PERR_ENABLE_X8 0x3044
5773 #define S_T7_X8MSTGRPPERR    0
5777 #define A_PCIE_HMA_CTRL 0x3050
5780 #define M_IPLTSSM    0xfU
5785 #define M_IPCONFIGDOWN    0x7U
5789 #define A_PCIE_HMA_CFG 0x3054
5792 #define M_HMA_MAXRSPCNT    0x1fU
5796 #define A_PCIE_HMA_STAT 0x3058
5799 #define M_HMA_RSPCNT    0xffU
5803 #define A_PCIE_PIO_FIFO_CFG 0x305c
5806 #define M_CPLCONFIG    0xffffU
5822 #define S_FORCEPROGRESSCNT    0
5823 #define M_FORCEPROGRESSCNT    0x3ffU
5827 #define A_PCIE_CFG_SPACE_REQ 0x3060
5842 #define M_BUS    0xffU
5847 #define M_DEVICE    0x1fU
5852 #define M_FUNCTION    0x7U
5857 #define M_EXTREGISTER    0xfU
5861 #define S_REGISTER    0
5862 #define M_REGISTER    0xffU
5871 #define M_WRBE    0xfU
5880 #define M_CFG_SPACE_RVF    0x7fU
5885 #define M_CFG_SPACE_PF    0x7U
5902 #define M_T6_WRBE    0xfU
5911 #define M_T6_CFG_SPACE_RVF    0xffU
5915 #define A_PCIE_CFG_SPACE_DATA 0x3064
5916 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
5919 #define M_PCIEOFST    0x3fffffU
5924 #define M_BIR    0x3U
5928 #define S_WINDOW    0
5929 #define M_WINDOW    0xffU
5933 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
5936 #define M_MEMOFST    0x1ffffffU
5940 #define A_T7_PCIE_MAILBOX_BASE_WIN 0x30a4
5941 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
5944 #define M_MBOXPCIEOFST    0x3ffffffU
5949 #define M_MBOXBIR    0x3U
5953 #define S_MBOXWIN    0
5954 #define M_MBOXWIN    0x3U
5958 #define A_PCIE_MAILBOX_OFFSET0 0x30a8
5961 #define M_MEMOFST0    0x1fffffffU
5965 #define A_PCIE_MAILBOX_OFFSET 0x30ac
5966 #define A_PCIE_MAILBOX_OFFSET1 0x30ac
5968 #define S_MEMOFST1    0
5969 #define M_MEMOFST1    0xfU
5973 #define A_PCIE_MA_CTRL 0x30b0
5980 #define M_MA_MAXRSPCNT    0x1fU
5985 #define M_MA_MAXREQCNT    0x1fU
5994 #define M_MA_MAXPYLDSIZE    0x7U
5999 #define M_MA_MAXRDREQSIZE    0x7U
6003 #define S_MA_MAXTAG    0
6004 #define M_MA_MAXTAG    0x1fU
6009 #define M_T5_MA_MAXREQCNT    0x7fU
6014 #define M_MA_MAXREQSIZE    0x7U
6018 #define A_PCIE_MA_SYNC 0x30b4
6019 #define A_PCIE_FW 0x30b8
6020 #define A_PCIE_FW_PF 0x30bc
6021 #define A_PCIE_PIO_PAUSE 0x30dc
6028 #define M_PIOPAUSETIME    0xffffffU
6032 #define S_PIOPAUSE    0
6044 #define A_PCIE_SYS_CFG_READY 0x30e0
6045 #define A_PCIE_MA_STAT 0x30e0
6046 #define A_PCIE_STATIC_CFG1 0x30e4
6057 #define M_IN_RD_CPLSIZE    0x7U
6062 #define M_IN_RD_BUFMODE    0x3U
6067 #define M_GBIF_NPTRANS_TOT    0x3U
6072 #define M_IN_PDAT_TOT    0x7U
6077 #define M_PCIE_NPTRANS_TOT    0x7U
6082 #define M_OUT_PDAT_TOT    0x7U
6087 #define M_GBIF_MAX_WRSIZE    0x7U
6092 #define M_GBIF_MAX_RDSIZE    0x7U
6096 #define S_PCIE_MAX_RDSIZE    0
6097 #define M_PCIE_MAX_RDSIZE    0x7U
6105 #define A_PCIE_STATIC_CFG2 0x30e8
6108 #define M_PL_CONTROL    0xffffU
6112 #define S_STATIC_SPARE3    0
6113 #define M_STATIC_SPARE3    0x3fffU
6117 #define S_T7_STATIC_SPARE3    0
6118 #define M_T7_STATIC_SPARE3    0x7fffU
6122 #define A_PCIE_DBG_INDIR_REQ 0x30ec
6133 #define M_POINTER    0xffffU
6137 #define S_SELECT    0
6138 #define M_SELECT    0xfU
6142 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
6143 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
6144 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
6145 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
6146 #define A_PCIE_FUNC_INT_CFG 0x3100
6149 #define M_PBAOFST    0xfU
6154 #define M_TABOFST    0xfU
6159 #define M_VECNUM    0x3ffU
6163 #define S_VECBASE    0
6164 #define M_VECBASE    0x7ffU
6168 #define A_PCIE_FUNC_CTL_STAT 0x3104
6183 #define M_PNDTXNS    0x3ffU
6191 #define S_PFNUM    0
6192 #define M_PFNUM    0x7U
6196 #define A_PCIE_PF_INT_CFG 0x3140
6199 #define M_T7_VECNUM    0x7ffU
6203 #define S_T7_VECBASE    0
6204 #define M_T7_VECBASE    0xfffU
6208 #define A_PCIE_PF_INT_CFG2 0x3144
6209 #define A_PCIE_VF_INT_CFG 0x3180
6210 #define A_PCIE_VF_INT_CFG2 0x3184
6211 #define A_PCIE_PF_MSI_EN 0x35a8
6213 #define S_PFMSIEN_7_0    0
6214 #define M_PFMSIEN_7_0    0xffU
6218 #define A_PCIE_VF_MSI_EN_0 0x35ac
6219 #define A_PCIE_VF_MSI_EN_1 0x35b0
6220 #define A_PCIE_VF_MSI_EN_2 0x35b4
6221 #define A_PCIE_VF_MSI_EN_3 0x35b8
6222 #define A_PCIE_PF_MSIX_EN 0x35bc
6224 #define S_PFMSIXEN_7_0    0
6225 #define M_PFMSIXEN_7_0    0xffU
6229 #define A_PCIE_VF_MSIX_EN_0 0x35c0
6230 #define A_PCIE_VF_MSIX_EN_1 0x35c4
6231 #define A_PCIE_VF_MSIX_EN_2 0x35c8
6232 #define A_PCIE_VF_MSIX_EN_3 0x35cc
6233 #define A_PCIE_FID_PASID 0x35e0
6234 #define A_PCIE_FID_VFID_CTL 0x35e4
6236 #define S_T7_WRITE    0
6240 #define A_T7_PCIE_FID_VFID_SEL 0x35e8
6243 #define M_T7_ADDR    0x1fffU
6247 #define A_PCIE_FID_VFID_SEL 0x35ec
6249 #define S_FID_VFID_SEL_SELECT    0
6250 #define M_FID_VFID_SEL_SELECT    0x3U
6254 #define A_T7_PCIE_FID_VFID 0x35ec
6261 #define M_FID_VFID_GROUPSEL    0xfU
6265 #define A_PCIE_FID_VFID 0x3600
6268 #define M_FID_VFID_SELECT    0x3U
6277 #define M_FID_VFID_VFID    0xffU
6282 #define M_FID_VFID_TC    0x7U
6291 #define M_FID_VFID_PF    0x7U
6295 #define S_FID_VFID_RVF    0
6296 #define M_FID_VFID_RVF    0x7fU
6301 #define M_T6_FID_VFID_VFID    0x1ffU
6306 #define M_T6_FID_VFID_TC    0x7U
6315 #define M_T6_FID_VFID_PF    0x7U
6319 #define S_T6_FID_VFID_RVF    0
6320 #define M_T6_FID_VFID_RVF    0xffU
6324 #define A_PCIE_JBOF_NVME_HIGH_DW_START_ADDR 0x3600
6325 #define A_PCIE_JBOF_NVME_LOW_DW_START_ADDR 0x3604
6326 #define A_PCIE_JBOF_NVME_LENGTH 0x3608
6332 #define S_NVMELENGTH    0
6333 #define M_NVMELENGTH    0x3fffffffU
6337 #define A_PCIE_JBOF_NVME_GROUP 0x360c
6339 #define S_NVMEGROUPSEL    0
6340 #define M_NVMEGROUPSEL    0xfU
6344 #define A_T7_PCIE_MEM_ACCESS_BASE_WIN 0x3700
6345 #define A_PCIE_MEM_ACCESS_BASE_WIN1 0x3704
6347 #define S_PCIEOFST1    0
6348 #define M_PCIEOFST1    0xffU
6352 #define A_PCIE_MEM_ACCESS_OFFSET0 0x3708
6353 #define A_PCIE_MEM_ACCESS_OFFSET1 0x370c
6354 #define A_PCIE_PTM_EP_EXT_STROBE 0x3804
6360 #define S_PTM_EXT_STROBE    0
6364 #define A_PCIE_PTM_EP_EXT_TIME0 0x3808
6365 #define A_PCIE_PTM_EP_EXT_TIME1 0x380c
6366 #define A_PCIE_PTM_MAN_UPD_PULSE 0x3810
6368 #define S_PTM_MAN_UPD_PULSE    0
6372 #define A_PCIE_SWAP_DATA_B2L_X16 0x3814
6373 #define A_PCIE_PCIE_RC_RST 0x3818
6375 #define S_PERST    0
6379 #define A_PCIE_PCIE_LN_CLKSEL 0x3880
6382 #define M_DS8_SEL    0x3U
6387 #define M_DS7_SEL    0x3U
6392 #define M_DS6_SEL    0x3U
6397 #define M_DS5_SEL    0x3U
6402 #define M_DS4_SEL    0x3U
6407 #define M_DS3_SEL    0x3U
6412 #define M_DS2_SEL    0x3U
6417 #define M_DS1_SEL    0x3U
6422 #define M_LN14_SEL    0x3U
6427 #define M_LN12_SEL    0x3U
6432 #define M_LN10_SEL    0x3U
6437 #define M_LN8_SEL    0x3U
6442 #define M_LN6_SEL    0x3U
6447 #define M_LN4_SEL    0x3U
6452 #define M_LN2_SEL    0x3U
6456 #define S_LN0_SEL    0
6457 #define M_LN0_SEL    0x3U
6461 #define A_PCIE_PCIE_MSIX_EN 0x3884
6463 #define S_MSIX_ENABLE    0
6464 #define M_MSIX_ENABLE    0xffU
6468 #define A_PCIE_LFSR_WRCTRL 0x3888
6471 #define M_WR_LFSR_CMP_DATA    0xffffU
6476 #define M_WR_LFSR_RSVD    0x3fffU
6484 #define S_WR_LFSR_START    0
6488 #define A_PCIE_LFSR_RDCTRL 0x388c
6491 #define M_CMD_LFSR_CMP_DATA    0xffU
6496 #define M_RD_LFSR_CMD_DATA    0xffU
6501 #define M_RD_LFSR_RSVD    0x3fU
6541 #define S_CMD_LFSR_START    0
6545 #define A_PCIE_FID 0x3900
6552 #define M_TC    0x7U
6556 #define S_FUNC    0
6557 #define M_FUNC    0xffU
6561 #define A_PCIE_EMU_ADDR 0x3900
6563 #define S_EMU_ADDR    0
6564 #define M_EMU_ADDR    0x1ffU
6568 #define A_PCIE_EMU_CFG 0x3904
6575 #define M_EMUTYPE    0x3U
6580 #define M_BAR0TARGET    0x3U
6585 #define M_BAR2TARGET    0x3U
6590 #define M_BAR4TARGET    0x3U
6594 #define S_RELEATIVEEMUID    0
6595 #define M_RELEATIVEEMUID    0xffU
6599 #define A_PCIE_EMUADRRMAP_MEM_OFFSET0_BAR0 0x3910
6601 #define S_T7_MEMOFST0    0
6602 #define M_T7_MEMOFST0    0xfffffffU
6606 #define A_PCIE_EMUADRRMAP_MEM_CFG0_BAR0 0x3914
6608 #define S_SIZE0    0
6609 #define M_SIZE0    0x1fU
6613 #define A_PCIE_EMUADRRMAP_MEM_OFFSET1_BAR0 0x3918
6615 #define S_T7_MEMOFST1    0
6616 #define M_T7_MEMOFST1    0xfffffffU
6620 #define A_PCIE_EMUADRRMAP_MEM_CFG1_BAR0 0x391c
6622 #define S_SIZE1    0
6623 #define M_SIZE1    0x1fU
6627 #define A_PCIE_EMUADRRMAP_MEM_OFFSET2_BAR0 0x3920
6629 #define S_MEMOFST2    0
6630 #define M_MEMOFST2    0xfffffffU
6634 #define A_PCIE_EMUADRRMAP_MEM_CFG2_BAR0 0x3924
6636 #define S_SIZE2    0
6637 #define M_SIZE2    0x1fU
6641 #define A_PCIE_EMUADRRMAP_MEM_OFFSET3_BAR0 0x3928
6643 #define S_MEMOFST3    0
6644 #define M_MEMOFST3    0xfffffffU
6648 #define A_PCIE_EMUADRRMAP_MEM_CFG3_BAR0 0x392c
6650 #define S_SIZE3    0
6651 #define M_SIZE3    0x1fU
6655 #define A_PCIE_TCAM_DATA 0x3970
6656 #define A_PCIE_TCAM_CTL 0x3974
6659 #define M_TCAMADDR    0x3ffU
6663 #define S_CAMEN    0
6667 #define A_PCIE_TCAM_DBG 0x3978
6685 #define S_TCAM_DBG_DATA    0
6686 #define M_TCAM_DBG_DATA    0xffffU
6690 #define A_PCIE_TEST_CTRL0 0x3980
6691 #define A_PCIE_TEST_CTRL1 0x3984
6692 #define A_PCIE_TEST_CTRL2 0x3988
6693 #define A_PCIE_TEST_CTRL3 0x398c
6694 #define A_PCIE_TEST_STS0 0x3990
6695 #define A_PCIE_TEST_STS1 0x3994
6696 #define A_PCIE_TEST_STS2 0x3998
6697 #define A_PCIE_TEST_STS3 0x399c
6698 #define A_PCIE_X8_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x4700
6699 #define A_PCIE_X8_CORE_VENDOR_SPECIFIC_DLLP 0x4704
6700 #define A_PCIE_X8_CORE_PORT_FORCE_LINK 0x4708
6701 #define A_PCIE_X8_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x470c
6702 #define A_PCIE_X8_CORE_PORT_LINK_CONTROL 0x4710
6703 #define A_PCIE_X8_CORE_LANE_SKEW 0x4714
6704 #define A_PCIE_X8_CORE_SYMBOL_NUMBER 0x4718
6705 #define A_PCIE_X8_CORE_SYMBOL_TIMER_FILTER_MASK1 0x471c
6706 #define A_PCIE_X8_CORE_FILTER_MASK2 0x4720
6707 #define A_PCIE_X8_CORE_DEBUG_0 0x4728
6708 #define A_PCIE_X8_CORE_DEBUG_1 0x472c
6709 #define A_PCIE_X8_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x4730
6710 #define A_PCIE_X8_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x4734
6711 #define A_PCIE_X8_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x4738
6712 #define A_PCIE_X8_CORE_QUEUE_STATUS 0x473c
6713 #define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_1 0x4740
6714 #define A_PCIE_X8_CORE_VC_TRANSMIT_ARBITRATION_2 0x4744
6715 #define A_PCIE_X8_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x4748
6716 #define A_PCIE_X8_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x474c
6717 #define A_PCIE_X8_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x4750
6718 #define A_PCIE_X8_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x4754
6719 #define A_PCIE_X8_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x4758
6720 #define A_PCIE_X8_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x475c
6721 #define A_PCIE_X8_CORE_LINK_WIDTH_SPEED_CHANGE 0x480c
6722 #define A_PCIE_X8_CORE_PHY_STATUS 0x4810
6723 #define A_PCIE_X8_CORE_PHY_CONTROL 0x4814
6724 #define A_PCIE_X8_CORE_GEN3_CONTROL 0x4890
6725 #define A_PCIE_X8_CORE_GEN3_EQ_FS_LF 0x4894
6726 #define A_PCIE_X8_CORE_GEN3_EQ_PRESET_COEFF 0x4898
6727 #define A_PCIE_X8_CORE_GEN3_EQ_PRESET_INDEX 0x489c
6728 #define A_PCIE_X8_CORE_GEN3_EQ_STATUS 0x48a4
6729 #define A_PCIE_X8_CORE_GEN3_EQ_CONTROL 0x48a8
6730 #define A_PCIE_X8_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x48ac
6731 #define A_PCIE_X8_CORE_PIPE_CONTROL 0x48b8
6732 #define A_PCIE_X8_CORE_DBI_RO_WE 0x48bc
6733 #define A_PCIE_X8_CFG_SPACE_REQ 0x48c0
6734 #define A_PCIE_X8_CFG_SPACE_DATA 0x48c4
6735 #define A_PCIE_X8_CFG_MPS_MRS 0x4900
6738 #define M_MRS    0x7U
6742 #define S_T7_MPS    0
6743 #define M_T7_MPS    0x7U
6747 #define A_PCIE_X8_CFG_ATTRIBUTES 0x4904
6757 #define S_REQCTLDYNSTCLKEN    0
6761 #define A_PCIE_X8_CFG_LTSSM 0x4908
6763 #define S_APP_LTSSM_ENABLE    0
6767 #define A_PCIE_ARM_REQUESTER_ID_X8 0x490c
6770 #define M_A1_RSVD1    0xffU
6775 #define M_A1_PRIMBUSNUMBER    0xffU
6779 #define S_A1_REQUESTERID    0
6780 #define M_A1_REQUESTERID    0xffffU
6784 #define A_PCIE_SWAP_DATA_B2L_X8 0x4910
6790 #define S_CFGWR_SWAP_EN    0
6794 #define A_PCIE_PDEBUG_DATA0_X8 0x4914
6795 #define A_PCIE_PDEBUG_DATA1_X8 0x4918
6796 #define A_PCIE_PDEBUG_DATA2_X8 0x491c
6797 #define A_PCIE_PDEBUG_CTRL_X8 0x4920
6798 #define A_PCIE_PDEBUG_DATA_X8 0x4924
6799 #define A_PCIE_SPARE_REGISTER_SPACES_X8 0x4ffc
6800 #define A_PCIE_PIPE_LANE0_REG0 0x5500
6801 #define A_PCIE_PIPE_LANE0_REG1 0x5504
6802 #define A_PCIE_PIPE_LANE0_REG2 0x5508
6803 #define A_PCIE_PIPE_LANE0_REG3 0x550c
6804 #define A_PCIE_PIPE_LANE1_REG0 0x5510
6805 #define A_PCIE_PIPE_LANE1_REG1 0x5514
6806 #define A_PCIE_PIPE_LANE1_REG2 0x5518
6807 #define A_PCIE_PIPE_LANE1_REG3 0x551c
6808 #define A_PCIE_PIPE_LANE2_REG0 0x5520
6809 #define A_PCIE_PIPE_LANE2_REG1 0x5524
6810 #define A_PCIE_PIPE_LANE2_REG2 0x5528
6811 #define A_PCIE_PIPE_LANE2_REG3 0x552c
6812 #define A_PCIE_PIPE_LANE3_REG0 0x5530
6813 #define A_PCIE_PIPE_LANE3_REG1 0x5534
6814 #define A_PCIE_PIPE_LANE3_REG2 0x5538
6815 #define A_PCIE_PIPE_LANE3_REG3 0x553c
6816 #define A_PCIE_PIPE_LANE4_REG0 0x5540
6817 #define A_PCIE_PIPE_LANE4_REG1 0x5544
6818 #define A_PCIE_PIPE_LANE4_REG2 0x5548
6819 #define A_PCIE_PIPE_LANE4_REG3 0x554c
6820 #define A_PCIE_PIPE_LANE5_REG0 0x5550
6821 #define A_PCIE_PIPE_LANE5_REG1 0x5554
6822 #define A_PCIE_PIPE_LANE5_REG2 0x5558
6823 #define A_PCIE_PIPE_LANE5_REG3 0x555c
6824 #define A_PCIE_PIPE_LANE6_REG0 0x5560
6825 #define A_PCIE_PIPE_LANE6_REG1 0x5564
6826 #define A_PCIE_PIPE_LANE6_REG2 0x5568
6827 #define A_PCIE_PIPE_LANE6_REG3 0x556c
6828 #define A_PCIE_PIPE_LANE7_REG0 0x5570
6829 #define A_PCIE_PIPE_LANE7_REG1 0x5574
6830 #define A_PCIE_PIPE_LANE7_REG2 0x5578
6831 #define A_PCIE_PIPE_LANE7_REG3 0x557c
6832 #define A_PCIE_PIPE_LANE8_REG0 0x5580
6833 #define A_PCIE_PIPE_LANE8_REG1 0x5584
6834 #define A_PCIE_PIPE_LANE8_REG2 0x5588
6835 #define A_PCIE_PIPE_LANE8_REG3 0x558c
6836 #define A_PCIE_PIPE_LANE9_REG0 0x5590
6837 #define A_PCIE_PIPE_LANE9_REG1 0x5594
6838 #define A_PCIE_PIPE_LANE9_REG2 0x5598
6839 #define A_PCIE_PIPE_LANE9_REG3 0x559c
6840 #define A_PCIE_PIPE_LANE10_REG0 0x55a0
6841 #define A_PCIE_PIPE_LANE10_REG1 0x55a4
6842 #define A_PCIE_PIPE_LANE10_REG2 0x55a8
6843 #define A_PCIE_PIPE_LANE10_REG3 0x55ac
6844 #define A_PCIE_PIPE_LANE11_REG0 0x55b0
6845 #define A_PCIE_PIPE_LANE11_REG1 0x55b4
6846 #define A_PCIE_PIPE_LANE11_REG2 0x55b8
6847 #define A_PCIE_PIPE_LANE11_REG3 0x55bc
6848 #define A_PCIE_PIPE_LANE12_REG0 0x55c0
6849 #define A_PCIE_PIPE_LANE12_REG1 0x55c4
6850 #define A_PCIE_PIPE_LANE12_REG2 0x55c8
6851 #define A_PCIE_PIPE_LANE12_REG3 0x55cc
6852 #define A_PCIE_PIPE_LANE13_REG0 0x55d0
6853 #define A_PCIE_PIPE_LANE13_REG1 0x55d4
6854 #define A_PCIE_PIPE_LANE13_REG2 0x55d8
6855 #define A_PCIE_PIPE_LANE13_REG3 0x55dc
6856 #define A_PCIE_PIPE_LANE14_REG0 0x55e0
6857 #define A_PCIE_PIPE_LANE14_REG1 0x55e4
6858 #define A_PCIE_PIPE_LANE14_REG2 0x55e8
6859 #define A_PCIE_PIPE_LANE14_REG3 0x55ec
6860 #define A_PCIE_PIPE_LANE15_REG0 0x55f0
6861 #define A_PCIE_PIPE_LANE15_REG1 0x55f4
6862 #define A_PCIE_PIPE_LANE15_REG2 0x55f8
6863 #define A_PCIE_PIPE_LANE15_REG3 0x55fc
6864 #define A_PCIE_COOKIE_STAT 0x5600
6867 #define M_COOKIEB    0x3ffU
6871 #define S_COOKIEA    0
6872 #define M_COOKIEA    0x3ffU
6876 #define A_PCIE_FLR_PIO 0x5620
6879 #define M_RCVDBAR2COOKIE    0xffU
6884 #define M_RCVDMARSPCOOKIE    0xffU
6889 #define M_RCVDPIORSPCOOKIE    0xffU
6893 #define S_EXPDCOOKIE    0
6894 #define M_EXPDCOOKIE    0xffU
6898 #define A_PCIE_FLR_PIO2 0x5624
6901 #define M_RCVDMAREQCOOKIE    0xffU
6906 #define M_RCVDPIOREQCOOKIE    0xffU
6911 #define M_RCVDVDMRXCOOKIE    0xffU
6916 #define M_RCVDVDMTXCOOKIE    0xffU
6921 #define M_T6_RCVDMAREQCOOKIE    0xffU
6925 #define S_T6_RCVDPIOREQCOOKIE    0
6926 #define M_T6_RCVDPIOREQCOOKIE    0xffU
6930 #define A_T7_PCIE_VC0_CDTS0 0x56c4
6933 #define M_T7_CPLD0    0xffffU
6937 #define S_T7_CPLH0    0
6938 #define M_T7_CPLH0    0xfffU
6942 #define A_T7_PCIE_VC0_CDTS1 0x56c8
6945 #define M_T7_PD0    0xffffU
6949 #define S_T7_PH0    0
6950 #define M_T7_PH0    0xfffU
6954 #define A_PCIE_VC0_CDTS0 0x56cc
6957 #define M_CPLD0    0xfffU
6962 #define M_PH0    0xffU
6966 #define S_PD0    0
6967 #define M_PD0    0xfffU
6971 #define A_PCIE_VC0_CDTS2 0x56cc
6974 #define M_T7_NPD0    0xffffU
6978 #define S_T7_NPH0    0
6979 #define M_T7_NPH0    0xfffU
6983 #define A_PCIE_VC0_CDTS1 0x56d0
6986 #define M_CPLH0    0xffU
6991 #define M_NPH0    0xffU
6995 #define S_NPD0    0
6996 #define M_NPD0    0xfffU
7000 #define A_T7_PCIE_VC1_CDTS0 0x56d0
7001 #define A_PCIE_VC1_CDTS0 0x56d4
7004 #define M_CPLD1    0xfffU
7009 #define M_PH1    0xffU
7013 #define S_PD1    0
7014 #define M_PD1    0xfffU
7018 #define A_T7_PCIE_VC1_CDTS1 0x56d4
7019 #define A_PCIE_VC1_CDTS1 0x56d8
7022 #define M_CPLH1    0xffU
7027 #define M_NPH1    0xffU
7031 #define S_NPD1    0
7032 #define M_NPD1    0xfffU
7036 #define A_PCIE_VC1_CDTS2 0x56d8
7037 #define A_PCIE_FLR_PF_STATUS 0x56dc
7038 #define A_PCIE_FLR_VF0_STATUS 0x56e0
7039 #define A_PCIE_FLR_VF1_STATUS 0x56e4
7040 #define A_PCIE_FLR_VF2_STATUS 0x56e8
7041 #define A_PCIE_FLR_VF3_STATUS 0x56ec
7042 #define A_PCIE_STAT 0x56f4
7045 #define M_PM_STATUS    0xffU
7050 #define M_PM_CURRENTSTATE    0x7U
7059 #define M_STATECFGINITF    0x7fU
7063 #define S_STATECFGINIT    0
7064 #define M_STATECFGINIT    0xfU
7073 #define M_STATECFGINITF_PCIE    0xffU
7077 #define S_STATECFGINIT_PCIE    0
7078 #define M_STATECFGINIT_PCIE    0xfU
7082 #define A_PCIE_CRS 0x56f8
7084 #define S_CRS_ENABLE    0
7088 #define A_PCIE_LTSSM 0x56fc
7090 #define S_LTSSM_ENABLE    0
7098 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
7101 #define M_REPLAY_TIME_LIMIT    0xffffU
7105 #define S_ACK_LATENCY_TIMER_LIMIT    0
7106 #define M_ACK_LATENCY_TIMER_LIMIT    0xffffU
7110 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
7111 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
7114 #define M_LOW_POWER_ENTRANCE_COUNT    0xffU
7119 #define M_LINK_STATE    0x3fU
7127 #define S_LINK_NUMBER    0
7128 #define M_LINK_NUMBER    0xffU
7132 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
7139 #define M_L1_ENTRANCE_LATENCY    0x7U
7144 #define M_L0S_ENTRANCE_LATENCY    0x7U
7149 #define M_COMMON_CLOCK_N_FTS    0xffU
7154 #define M_N_FTS    0xffU
7158 #define S_ACK_FREQUENCY    0
7159 #define M_ACK_FREQUENCY    0xffU
7163 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
7174 #define M_LINK_MODE_ENABLE    0x3fU
7198 #define S_VENDOR_SPECIFIC_DLLP_REQUEST    0
7202 #define A_PCIE_CORE_LANE_SKEW 0x5714
7216 #define S_INSERT_TXSKEW    0
7217 #define M_INSERT_TXSKEW    0xffffffU
7221 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
7224 #define M_FLOW_CONTROL_TIMER_MODIFIER    0x1fU
7229 #define M_ACK_NAK_TIMER_MODIFIER    0x1fU
7234 #define M_REPLAY_TIMER_MODIFIER    0x1fU
7238 #define S_MAXFUNC    0
7239 #define M_MAXFUNC    0x7U
7243 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
7246 #define M_MASK_RADM_FILTER    0xffffU
7254 #define S_SKP_INTERVAL    0
7255 #define M_SKP_INTERVAL    0x7ffU
7259 #define A_PCIE_CORE_FILTER_MASK2 0x5720
7260 #define A_PCIE_CORE_DEBUG_0 0x5728
7261 #define A_PCIE_CORE_DEBUG_1 0x572c
7262 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
7265 #define M_TXPH_FC    0xffU
7269 #define S_TXPD_FC    0
7270 #define M_TXPD_FC    0xfffU
7274 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
7277 #define M_TXNPH_FC    0xffU
7281 #define S_TXNPD_FC    0
7282 #define M_TXNPD_FC    0xfffU
7286 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
7289 #define M_TXCPLH_FC    0xffU
7293 #define S_TXCPLD_FC    0
7294 #define M_TXCPLD_FC    0xfffU
7298 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
7308 #define S_RXTLP_FC_NOT_RETURNED    0
7312 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
7315 #define M_VC3_WRR    0xffU
7320 #define M_VC2_WRR    0xffU
7325 #define M_VC1_WRR    0xffU
7329 #define S_VC0_WRR    0
7330 #define M_VC0_WRR    0xffU
7334 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
7337 #define M_VC7_WRR    0xffU
7342 #define M_VC6_WRR    0xffU
7347 #define M_VC5_WRR    0xffU
7351 #define S_VC4_WRR    0
7352 #define M_VC4_WRR    0xffU
7356 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
7367 #define M_VC0_PTLP_QUEUE_MODE    0x7U
7372 #define M_VC0_PH_CREDITS    0xffU
7376 #define S_VC0_PD_CREDITS    0
7377 #define M_VC0_PD_CREDITS    0xfffU
7381 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
7384 #define M_VC0_NPTLP_QUEUE_MODE    0x7U
7389 #define M_VC0_NPH_CREDITS    0xffU
7393 #define S_VC0_NPD_CREDITS    0
7394 #define M_VC0_NPD_CREDITS    0xfffU
7398 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
7401 #define M_VC0_CPLTLP_QUEUE_MODE    0x7U
7406 #define M_VC0_CPLH_CREDITS    0xffU
7410 #define S_VC0_CPLD_CREDITS    0
7411 #define M_VC0_CPLD_CREDITS    0xfffU
7415 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
7422 #define M_VC1_PTLP_QUEUE_MODE    0x7U
7427 #define M_VC1_PH_CREDITS    0xffU
7431 #define S_VC1_PD_CREDITS    0
7432 #define M_VC1_PD_CREDITS    0xfffU
7436 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
7439 #define M_VC1_NPTLP_QUEUE_MODE    0x7U
7444 #define M_VC1_NPH_CREDITS    0xffU
7448 #define S_VC1_NPD_CREDITS    0
7449 #define M_VC1_NPD_CREDITS    0xfffU
7453 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
7456 #define M_VC1_CPLTLP_QUEUE_MODE    0x7U
7461 #define M_VC1_CPLH_CREDITS    0xffU
7465 #define S_VC1_CPLD_CREDITS    0
7466 #define M_VC1_CPLD_CREDITS    0xfffU
7470 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
7489 #define M_NUM_LANES    0x1ffU
7493 #define S_NFTS_GEN2_3    0
7494 #define M_NFTS_GEN2_3    0xffU
7503 #define M_T6_NUM_LANES    0x1fU
7507 #define A_PCIE_CORE_PHY_STATUS 0x5810
7508 #define A_PCIE_CORE_PHY_CONTROL 0x5814
7509 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
7540 #define M_RATE_SHADOW_SEL    0x3U
7544 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
7547 #define M_FULL_SWING    0x3fU
7551 #define S_LOW_FREQUENCY    0
7552 #define M_LOW_FREQUENCY    0x3fU
7556 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
7559 #define M_POSTCURSOR    0x3fU
7564 #define M_CURSOR    0x3fU
7568 #define S_PRECURSOR    0
7569 #define M_PRECURSOR    0x3fU
7573 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
7575 #define S_INDEX    0
7576 #define M_INDEX    0xfU
7580 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
7582 #define S_LEGALITY_STATUS    0
7586 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
7593 #define M_PRESET_REQUEST_VECTOR    0xffffU
7605 #define S_FEEDBACK_MODE    0
7606 #define M_FEEDBACK_MODE    0xfU
7610 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
7613 #define M_WINAPERTURE_CPLUS1    0xfU
7618 #define M_WINAPERTURE_CMINS1    0xfU
7623 #define M_CONVERGENCE_WINDEPTH    0x1fU
7627 #define S_EQMASTERPHASE_MINTIME    0
7628 #define M_EQMASTERPHASE_MINTIME    0x1fU
7632 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
7634 #define S_PIPE_LOOPBACK_EN    0
7642 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
7644 #define S_READONLY_WRITEEN    0
7648 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
7734 #define S_CRMC    0
7735 #define M_CRMC    0x7U
7739 #define A_PCIE_CORE_UTL_STATUS 0x5904
7773 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
7799 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
7821 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
7843 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
7846 #define M_SBRS    0x7U
7851 #define M_OTWS    0x7U
7855 #define A_PCIE_CORE_REVISION_ID 0x5924
7858 #define M_RVID    0xfffU
7863 #define M_BRVN    0xffU
7867 #define A_PCIE_T5_DMA_CFG 0x5940
7870 #define M_T5_DMA_MAXREQCNT    0xffU
7875 #define M_T5_DMA_MAXRDREQSIZE    0x7U
7880 #define M_T5_DMA_MAXRSPCNT    0x1ffU
7888 #define S_MINTAG    0
7889 #define M_MINTAG    0x7fU
7894 #define M_T6_T5_DMA_MAXREQCNT    0x7fU
7899 #define M_T6_T5_DMA_MAXRSPCNT    0xffU
7907 #define S_T6_MINTAG    0
7908 #define M_T6_MINTAG    0xffU
7912 #define A_PCIE_T5_DMA_STAT 0x5944
7915 #define M_DMA_RESPCNT    0xfffU
7920 #define M_DMA_RDREQCNT    0xffU
7924 #define S_DMA_WRREQCNT    0
7925 #define M_DMA_WRREQCNT    0x7ffU
7930 #define M_T6_DMA_RESPCNT    0x3ffU
7935 #define M_T6_DMA_RDREQCNT    0x3fU
7939 #define S_T6_DMA_WRREQCNT    0
7940 #define M_T6_DMA_WRREQCNT    0x1ffU
7944 #define A_PCIE_T5_DMA_STAT2 0x5948
7947 #define M_COOKIECNT    0xfU
7952 #define M_RDSEQNUMUPDCNT    0xfU
7957 #define M_SIREQCNT    0xfU
7966 #define M_WRSOPCNT    0xfU
7970 #define S_RDSOPCNT    0
7971 #define M_RDSOPCNT    0xffU
7976 #define M_DMA_COOKIECNT    0xfU
7981 #define M_DMA_RDSEQNUMUPDCNT    0xfU
7986 #define M_DMA_SIREQCNT    0xfU
7995 #define M_DMA_WRSOPCNT    0xfU
7999 #define S_DMA_RDSOPCNT    0
8000 #define M_DMA_RDSOPCNT    0xffU
8004 #define A_PCIE_T5_DMA_STAT3 0x594c
8007 #define M_ATMREQSOPCNT    0xffU
8020 #define M_RSPERRCNT    0xffU
8024 #define S_RSPSOPCNT    0
8025 #define M_RSPSOPCNT    0xffU
8030 #define M_DMA_ATMREQSOPCNT    0xffU
8043 #define M_DMA_RSPERRCNT    0xffU
8047 #define S_DMA_RSPSOPCNT    0
8048 #define M_DMA_RSPSOPCNT    0xffU
8052 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
8055 #define M_OP0H    0xfU
8060 #define M_OP1H    0xfU
8065 #define M_OP2H    0xfU
8069 #define S_OP3H    0
8070 #define M_OP3H    0xfU
8074 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
8077 #define M_OP0D    0x7fU
8082 #define M_OP1D    0x7fU
8087 #define M_OP2D    0x7fU
8091 #define S_OP3D    0
8092 #define M_OP3D    0x7fU
8096 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
8099 #define M_IP0H    0x3fU
8104 #define M_IP1H    0x3fU
8109 #define M_IP2H    0x3fU
8113 #define S_IP3H    0
8114 #define M_IP3H    0x3fU
8118 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
8121 #define M_IP0D    0xffU
8126 #define M_IP1D    0xffU
8131 #define M_IP2D    0xffU
8135 #define S_IP3D    0
8136 #define M_IP3D    0xffU
8140 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
8143 #define M_ON0H    0xfU
8148 #define M_ON1H    0xfU
8153 #define M_ON2H    0xfU
8157 #define S_ON3H    0
8158 #define M_ON3H    0xfU
8162 #define A_PCIE_T5_CMD_CFG 0x5980
8165 #define M_T5_CMD_MAXRDREQSIZE    0x7U
8170 #define M_T5_CMD_MAXRSPCNT    0xffU
8179 #define M_T6_T5_CMD_MAXRSPCNT    0x3fU
8187 #define A_PCIE_T5_CMD_STAT 0x5984
8190 #define M_T5_STAT_RSPCNT    0x7ffU
8195 #define M_RDREQCNT    0x1fU
8200 #define M_T6_T5_STAT_RSPCNT    0xffU
8205 #define M_T6_RDREQCNT    0xfU
8209 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
8212 #define M_IN0H    0x3fU
8217 #define M_IN1H    0x3fU
8222 #define M_IN2H    0x3fU
8226 #define S_IN3H    0
8227 #define M_IN3H    0x3fU
8231 #define A_PCIE_T5_CMD_STAT2 0x5988
8232 #define A_PCIE_T5_CMD_STAT3 0x598c
8239 #define M_CMD_RSPERRCNT    0xffU
8243 #define S_CMD_RSPSOPCNT    0
8244 #define M_CMD_RSPSOPCNT    0xffU
8248 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
8251 #define M_OC0T    0xffU
8256 #define M_OC1T    0xffU
8261 #define M_OC2T    0xffU
8265 #define S_OC3T    0
8266 #define M_OC3T    0xffU
8270 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
8273 #define M_IC0T    0x3fU
8278 #define M_IC1T    0x3fU
8283 #define M_IC2T    0x3fU
8287 #define S_IC3T    0
8288 #define M_IC3T    0x3fU
8292 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
8339 #define M_RTOS    0xfU
8343 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
8397 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
8447 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
8485 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
8531 #define A_PCIE_T5_HMA_CFG 0x59b0
8534 #define M_HMA_MAXREQCNT    0x1fU
8539 #define M_T5_HMA_MAXRDREQSIZE    0x7U
8544 #define M_T5_HMA_MAXRSPCNT    0x1fU
8549 #define M_T6_HMA_MAXREQCNT    0x7fU
8554 #define M_T6_T5_HMA_MAXRSPCNT    0xffU
8562 #define S_T5_MINTAG    0
8563 #define M_T5_MINTAG    0xffU
8567 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
8613 #define A_PCIE_T5_HMA_STAT 0x59b4
8616 #define M_HMA_RESPCNT    0x1ffU
8621 #define M_HMA_RDREQCNT    0x3fU
8625 #define S_HMA_WRREQCNT    0
8626 #define M_HMA_WRREQCNT    0x1ffU
8631 #define M_T6_HMA_RESPCNT    0x3ffU
8635 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
8681 #define A_PCIE_T5_HMA_STAT2 0x59b8
8684 #define M_HMA_COOKIECNT    0xfU
8689 #define M_HMA_RDSEQNUMUPDCNT    0xfU
8698 #define M_HMA_WRSOPCNT    0xfU
8702 #define S_HMA_RDSOPCNT    0
8703 #define M_HMA_RDSOPCNT    0xffU
8707 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
8749 #define A_PCIE_T5_HMA_STAT3 0x59bc
8756 #define M_HMA_RSPERRCNT    0xffU
8760 #define S_HMA_RSPSOPCNT    0
8761 #define M_HMA_RSPSOPCNT    0xffU
8765 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
8839 #define A_PCIE_CGEN 0x59c0
8913 #define S_STI_SLEEPREQ    0
8925 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
8967 #define A_PCIE_MA_RSP 0x59c4
8970 #define M_TIMERVALUE    0xffffffU
8978 #define S_MARSPTIMEREN    0
8982 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
9004 #define A_PCIE_HPRD 0x59c8
9007 #define M_NPH_CREDITSAVAILVC0    0x3U
9012 #define M_NPD_CREDITSAVAILVC0    0x3U
9017 #define M_NPH_CREDITSAVAILVC1    0x3U
9022 #define M_NPD_CREDITSAVAILVC1    0x3U
9027 #define M_NPH_CREDITSREQUIRED    0x3U
9032 #define M_NPD_CREDITSREQUIRED    0x3U
9037 #define M_REQBURSTCOUNT    0xfU
9042 #define M_REQBURSTFREQUENCY    0xfU
9046 #define S_ENABLEVC1    0
9050 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
9053 #define M_CPM0    0x3U
9058 #define M_CPM1    0x3U
9063 #define M_CPM2    0x3U
9068 #define M_CPM3    0x3U
9073 #define M_CPM4    0x3U
9078 #define M_CPM5    0x3U
9083 #define M_CPM6    0x3U
9088 #define M_CPM7    0x3U
9093 #define M_OPM0    0x3U
9098 #define M_OPM1    0x3U
9103 #define M_OPM2    0x3U
9108 #define M_OPM3    0x3U
9113 #define M_OPM4    0x3U
9118 #define M_OPM5    0x3U
9123 #define M_OPM6    0x3U
9127 #define S_OPM7    0
9128 #define M_OPM7    0x3U
9132 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
9133 #define A_PCIE_PERR_GROUP 0x59d0
9235 #define S_PIOCPL_PLMRSPPERR    0
9267 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
9268 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
9306 #define S_REQUNDERFLRLOGEN    0
9310 #define A_PCIE_RSP_ERR_LOG1 0x59d8
9313 #define M_REQTAG    0x7fU
9318 #define M_CID    0x7U
9323 #define M_CHNUM    0x7U
9328 #define M_BYTELEN    0x1fffU
9333 #define M_REASON    0x7U
9337 #define S_CPLSTATUS    0
9338 #define M_CPLSTATUS    0x7U
9342 #define A_PCIE_RSP_ERR_LOG2 0x59dc
9349 #define M_ADDR10B    0x3ffU
9353 #define S_REQVFID    0
9354 #define M_REQVFID    0xffU
9359 #define M_T6_ADDR10B    0x3ffU
9363 #define S_T6_REQVFID    0
9364 #define M_T6_REQVFID    0x1ffU
9369 #define M_LOGADDR10B    0x3ffU
9373 #define S_LOGREQVFID    0
9374 #define M_LOGREQVFID    0x1ffU
9378 #define A_PCIE_CHANGESET 0x59fc
9379 #define A_PCIE_REVISION 0x5a00
9380 #define A_PCIE_PDEBUG_INDEX 0x5a04
9383 #define M_PDEBUGSELH    0x3fU
9387 #define S_PDEBUGSELL    0
9388 #define M_PDEBUGSELL    0x3fU
9393 #define M_T6_PDEBUGSELH    0x7fU
9397 #define S_T6_PDEBUGSELL    0
9398 #define M_T6_PDEBUGSELL    0x7fU
9403 #define M_T7_1_PDEBUGSELH    0xffU
9407 #define S_T7_1_PDEBUGSELL    0
9408 #define M_T7_1_PDEBUGSELL    0xffU
9412 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
9413 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
9414 #define A_PCIE_CDEBUG_INDEX 0x5a10
9417 #define M_CDEBUGSELH    0xffU
9421 #define S_CDEBUGSELL    0
9422 #define M_CDEBUGSELL    0xffU
9426 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
9427 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
9428 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
9431 #define M_CH3    0xffU
9436 #define M_CH2    0xffU
9441 #define M_CH1    0xffU
9445 #define S_CH0    0
9446 #define M_CH0    0xffU
9450 #define A_PCIE_DMAW_EOP_CNT 0x5a20
9451 #define A_PCIE_DMAR_REQ_CNT 0x5a24
9452 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
9453 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
9454 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
9455 #define A_PCIE_DMAI_CNT 0x5a34
9456 #define A_PCIE_CMDW_CNT 0x5a38
9459 #define M_CH1_EOP    0xffU
9464 #define M_CH1_SOP    0xffU
9469 #define M_CH0_EOP    0xffU
9473 #define S_CH0_SOP    0
9474 #define M_CH0_SOP    0xffU
9478 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
9479 #define A_PCIE_CMDR_RSP_CNT 0x5a40
9480 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
9481 #define A_PCIE_HMA_REQ_CNT 0x5a48
9484 #define M_CH0_READ    0xffU
9489 #define M_CH0_WEOP    0xffU
9493 #define S_CH0_WSOP    0
9494 #define M_CH0_WSOP    0xffU
9498 #define A_PCIE_HMA_RSP_CNT 0x5a4c
9499 #define A_PCIE_DMA10_RSP_FREE 0x5a50
9502 #define M_CH1_RSP_FREE    0xfffU
9506 #define S_CH0_RSP_FREE    0
9507 #define M_CH0_RSP_FREE    0xfffU
9511 #define A_PCIE_DMA32_RSP_FREE 0x5a54
9514 #define M_CH3_RSP_FREE    0xfffU
9518 #define S_CH2_RSP_FREE    0
9519 #define M_CH2_RSP_FREE    0xfffU
9523 #define A_PCIE_CMD_RSP_FREE 0x5a58
9526 #define M_CMD_CH1_RSP_FREE    0x7fU
9530 #define S_CMD_CH0_RSP_FREE    0
9531 #define M_CMD_CH0_RSP_FREE    0x7fU
9535 #define A_PCIE_HMA_RSP_FREE 0x5a5c
9536 #define A_PCIE_BUS_MST_STAT_0 0x5a60
9537 #define A_PCIE_BUS_MST_STAT_1 0x5a64
9538 #define A_PCIE_BUS_MST_STAT_2 0x5a68
9539 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
9540 #define A_PCIE_BUS_MST_STAT_4 0x5a70
9542 #define S_BUSMST_135_128    0
9543 #define M_BUSMST_135_128    0xffU
9547 #define A_PCIE_BUS_MST_STAT_5 0x5a74
9548 #define A_PCIE_BUS_MST_STAT_6 0x5a78
9549 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
9550 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
9551 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
9552 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
9553 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
9554 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
9556 #define S_RSPERR_135_128    0
9557 #define M_RSPERR_135_128    0xffU
9561 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
9562 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
9564 #define S_DBI_TIMER    0
9565 #define M_DBI_TIMER    0xffffU
9569 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
9570 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
9571 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
9572 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
9575 #define M_SOURCE    0x3U
9580 #define M_DBI_WRITE    0xfU
9589 #define M_DBI_PF    0x7U
9597 #define S_PL_TOVF    0
9598 #define M_PL_TOVF    0x7fU
9603 #define M_T6_SOURCE    0x3U
9608 #define M_T6_DBI_WRITE    0xfU
9617 #define M_T6_DBI_PF    0x7U
9625 #define S_T6_PL_TOVF    0
9626 #define M_T6_PL_TOVF    0xffU
9630 #define A_PCIE_MSI_EN_0 0x5aa0
9631 #define A_PCIE_MSI_EN_1 0x5aa4
9632 #define A_PCIE_MSI_EN_2 0x5aa8
9633 #define A_PCIE_MSI_EN_3 0x5aac
9634 #define A_PCIE_MSI_EN_4 0x5ab0
9635 #define A_PCIE_MSI_EN_5 0x5ab4
9636 #define A_PCIE_MSI_EN_6 0x5ab8
9637 #define A_PCIE_MSI_EN_7 0x5abc
9638 #define A_PCIE_MSIX_EN_0 0x5ac0
9639 #define A_PCIE_MSIX_EN_1 0x5ac4
9640 #define A_PCIE_MSIX_EN_2 0x5ac8
9641 #define A_PCIE_MSIX_EN_3 0x5acc
9642 #define A_PCIE_MSIX_EN_4 0x5ad0
9643 #define A_PCIE_MSIX_EN_5 0x5ad4
9644 #define A_PCIE_MSIX_EN_6 0x5ad8
9645 #define A_PCIE_MSIX_EN_7 0x5adc
9646 #define A_PCIE_DMA_BUF_CTL 0x5ae0
9649 #define M_BUFRDCNT    0x3fffU
9654 #define M_BUFWRCNT    0x1ffU
9658 #define S_MAXBUFWRREQ    0
9659 #define M_MAXBUFWRREQ    0x1ffU
9663 #define A_PCIE_PB_CTL 0x5b94
9666 #define M_PB_SEL    0xffU
9671 #define M_PB_SELREG    0xffU
9675 #define S_PB_FUNC    0
9676 #define M_PB_FUNC    0x7U
9680 #define A_PCIE_PB_DATA 0x5b98
9681 #define A_PCIE_CUR_LINK 0x5b9c
9720 #define M_NEGOTIATEDWIDTH    0x3fU
9724 #define S_ACTIVELANES    0
9725 #define M_ACTIVELANES    0xffU
9729 #define A_PCIE_PHY_REQRXPWR 0x5ba0
9740 #define M_LNH_RXPWRSTATE    0x3U
9753 #define M_LNG_RXPWRSTATE    0x3U
9766 #define M_LNF_RXPWRSTATE    0x3U
9779 #define M_LNE_RXPWRSTATE    0x3U
9792 #define M_LND_RXPWRSTATE    0x3U
9805 #define M_LNC_RXPWRSTATE    0x3U
9818 #define M_LNB_RXPWRSTATE    0x3U
9830 #define S_LNA_RXPWRSTATE    0
9831 #define M_LNA_RXPWRSTATE    0x3U
9844 #define M_REQ_LNH_RXPWRSTATE    0x3U
9857 #define M_REQ_LNG_RXPWRSTATE    0x3U
9870 #define M_REQ_LNF_RXPWRSTATE    0x3U
9883 #define M_REQ_LNE_RXPWRSTATE    0x3U
9896 #define M_REQ_LND_RXPWRSTATE    0x3U
9909 #define M_REQ_LNC_RXPWRSTATE    0x3U
9922 #define M_REQ_LNB_RXPWRSTATE    0x3U
9934 #define S_REQ_LNA_RXPWRSTATE    0
9935 #define M_REQ_LNA_RXPWRSTATE    0x3U
9939 #define A_PCIE_PHY_CURRXPWR 0x5ba4
9942 #define M_T5_LNH_RXPWRSTATE    0x7U
9947 #define M_T5_LNG_RXPWRSTATE    0x7U
9952 #define M_T5_LNF_RXPWRSTATE    0x7U
9957 #define M_T5_LNE_RXPWRSTATE    0x7U
9962 #define M_T5_LND_RXPWRSTATE    0x7U
9967 #define M_T5_LNC_RXPWRSTATE    0x7U
9972 #define M_T5_LNB_RXPWRSTATE    0x7U
9976 #define S_T5_LNA_RXPWRSTATE    0
9977 #define M_T5_LNA_RXPWRSTATE    0x7U
9982 #define M_CUR_LNH_RXPWRSTATE    0x7U
9987 #define M_CUR_LNG_RXPWRSTATE    0x7U
9992 #define M_CUR_LNF_RXPWRSTATE    0x7U
9997 #define M_CUR_LNE_RXPWRSTATE    0x7U
10002 #define M_CUR_LND_RXPWRSTATE    0x7U
10007 #define M_CUR_LNC_RXPWRSTATE    0x7U
10012 #define M_CUR_LNB_RXPWRSTATE    0x7U
10016 #define S_CUR_LNA_RXPWRSTATE    0
10017 #define M_CUR_LNA_RXPWRSTATE    0x7U
10021 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
10024 #define M_LND_STAT    0x7U
10029 #define M_LND_CMD    0x7U
10034 #define M_LNC_STAT    0x7U
10039 #define M_LNC_CMD    0x7U
10044 #define M_LNB_STAT    0x7U
10049 #define M_LNB_CMD    0x7U
10054 #define M_LNA_STAT    0x7U
10058 #define S_LNA_CMD    0
10059 #define M_LNA_CMD    0x7U
10063 #define A_PCIE_PHY_GEN3_AE1 0x5bac
10066 #define M_LNH_STAT    0x7U
10071 #define M_LNH_CMD    0x7U
10076 #define M_LNG_STAT    0x7U
10081 #define M_LNG_CMD    0x7U
10086 #define M_LNF_STAT    0x7U
10091 #define M_LNF_CMD    0x7U
10096 #define M_LNE_STAT    0x7U
10100 #define S_LNE_CMD    0
10101 #define M_LNE_CMD    0x7U
10105 #define A_PCIE_PHY_FS_LF0 0x5bb0
10108 #define M_LANE1LF    0x3fU
10113 #define M_LANE1FS    0x3fU
10118 #define M_LANE0LF    0x3fU
10122 #define S_LANE0FS    0
10123 #define M_LANE0FS    0x3fU
10127 #define A_PCIE_PHY_FS_LF1 0x5bb4
10130 #define M_LANE3LF    0x3fU
10135 #define M_LANE3FS    0x3fU
10140 #define M_LANE2LF    0x3fU
10144 #define S_LANE2FS    0
10145 #define M_LANE2FS    0x3fU
10149 #define A_PCIE_PHY_FS_LF2 0x5bb8
10152 #define M_LANE5LF    0x3fU
10157 #define M_LANE5FS    0x3fU
10162 #define M_LANE4LF    0x3fU
10166 #define S_LANE4FS    0
10167 #define M_LANE4FS    0x3fU
10171 #define A_PCIE_PHY_FS_LF3 0x5bbc
10174 #define M_LANE7LF    0x3fU
10179 #define M_LANE7FS    0x3fU
10184 #define M_LANE6LF    0x3fU
10188 #define S_LANE6FS    0
10189 #define M_LANE6FS    0x3fU
10193 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
10200 #define M_COEFFLANE    0x7U
10204 #define S_COEFFSTART    0
10209 #define M_T6_COEFFLANE    0xfU
10213 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
10215 #define S_COEFF    0
10216 #define M_COEFF    0x3ffffU
10220 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
10226 #define S_PCIE_PHY_REGADDR    0
10227 #define M_PCIE_PHY_REGADDR    0xffffU
10231 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
10232 #define A_PCIE_STATIC_SPARE1 0x5bf8
10233 #define A_PCIE_STATIC_SPARE2 0x5bfc
10240 #define M_SWITCHCFG    0x3U
10244 #define S_STATIC_SPARE2    0
10245 #define M_STATIC_SPARE2    0xfffffffU
10249 #define A_PCIE_KDOORBELL_GTS_PF_BASE_LEN 0x5c10
10252 #define M_KDB_PF_LEN    0x1fU
10256 #define S_KDB_PF_BASEADDR    0
10257 #define M_KDB_PF_BASEADDR    0xfffffU
10261 #define A_PCIE_KDOORBELL_GTS_VF_BASE_LEN 0x5c14
10264 #define M_KDB_VF_LEN    0x1fU
10268 #define S_KDB_VF_BASEADDR    0
10269 #define M_KDB_VF_BASEADDR    0xfffffU
10273 #define A_PCIE_KDOORBELL_GTS_VF_OFFSET 0x5c18
10275 #define S_KDB_VF_MODOFST    0
10276 #define M_KDB_VF_MODOFST    0xfffU
10280 #define A_PCIE_PHY_REQRXPWR1 0x5c1c
10291 #define M_REQ_LNP_RXPWRSTATE    0x3U
10304 #define M_REQ_LNO_RXPWRSTATE    0x3U
10317 #define M_REQ_LNN_RXPWRSTATE    0x3U
10330 #define M_REQ_LNM_RXPWRSTATE    0x3U
10343 #define M_REQ_LNL_RXPWRSTATE    0x3U
10356 #define M_REQ_LNK_RXPWRSTATE    0x3U
10369 #define M_REQ_LNJ_RXPWRSTATE    0x3U
10381 #define S_REQ_LNI_RXPWRSTATE    0
10382 #define M_REQ_LNI_RXPWRSTATE    0x3U
10386 #define A_PCIE_PHY_CURRXPWR1 0x5c20
10389 #define M_CUR_LNP_RXPWRSTATE    0x7U
10394 #define M_CUR_LNO_RXPWRSTATE    0x7U
10399 #define M_CUR_LNN_RXPWRSTATE    0x7U
10404 #define M_CUR_LNM_RXPWRSTATE    0x7U
10409 #define M_CUR_LNL_RXPWRSTATE    0x7U
10414 #define M_CUR_LNK_RXPWRSTATE    0x7U
10419 #define M_CUR_LNJ_RXPWRSTATE    0x7U
10423 #define S_CUR_LNI_RXPWRSTATE    0
10424 #define M_CUR_LNI_RXPWRSTATE    0x7U
10428 #define A_PCIE_PHY_GEN3_AE2 0x5c24
10431 #define M_LNL_STAT    0x7U
10436 #define M_LNL_CMD    0x7U
10441 #define M_LNK_STAT    0x7U
10446 #define M_LNK_CMD    0x7U
10451 #define M_LNJ_STAT    0x7U
10456 #define M_LNJ_CMD    0x7U
10461 #define M_LNI_STAT    0x7U
10465 #define S_LNI_CMD    0
10466 #define M_LNI_CMD    0x7U
10470 #define A_PCIE_PHY_GEN3_AE3 0x5c28
10473 #define M_LNP_STAT    0x7U
10478 #define M_LNP_CMD    0x7U
10483 #define M_LNO_STAT    0x7U
10488 #define M_LNO_CMD    0x7U
10493 #define M_LNN_STAT    0x7U
10498 #define M_LNN_CMD    0x7U
10503 #define M_LNM_STAT    0x7U
10507 #define S_LNM_CMD    0
10508 #define M_LNM_CMD    0x7U
10512 #define A_PCIE_PHY_FS_LF4 0x5c2c
10515 #define M_LANE9LF    0x3fU
10520 #define M_LANE9FS    0x3fU
10525 #define M_LANE8LF    0x3fU
10529 #define S_LANE8FS    0
10530 #define M_LANE8FS    0x3fU
10534 #define A_PCIE_PHY_FS_LF5 0x5c30
10537 #define M_LANE11LF    0x3fU
10542 #define M_LANE11FS    0x3fU
10547 #define M_LANE10LF    0x3fU
10551 #define S_LANE10FS    0
10552 #define M_LANE10FS    0x3fU
10556 #define A_PCIE_PHY_FS_LF6 0x5c34
10559 #define M_LANE13LF    0x3fU
10564 #define M_LANE13FS    0x3fU
10569 #define M_LANE12LF    0x3fU
10573 #define S_LANE12FS    0
10574 #define M_LANE12FS    0x3fU
10578 #define A_PCIE_PHY_FS_LF7 0x5c38
10581 #define M_LANE15LF    0x3fU
10586 #define M_LANE15FS    0x3fU
10591 #define M_LANE14LF    0x3fU
10595 #define S_LANE14FS    0
10596 #define M_LANE14FS    0x3fU
10600 #define A_PCIE_MULTI_PHY_INDIR_REQ 0x5c3c
10607 #define M_PHY_REG_SELECT    0x3U
10611 #define S_PHY_REG_REGADDR    0
10612 #define M_PHY_REG_REGADDR    0xffffU
10616 #define A_PCIE_MULTI_PHY_INDIR_DATA 0x5c40
10618 #define S_PHY_REG_DATA    0
10619 #define M_PHY_REG_DATA    0xffffU
10623 #define A_PCIE_VF_INT_INDIR_REQ 0x5c44
10633 #define S_VFID_PCIE    0
10634 #define M_VFID_PCIE    0x3ffU
10638 #define A_PCIE_VF_INT_INDIR_DATA 0x5c48
10639 #define A_PCIE_VF_256_INT_CFG2 0x5c4c
10640 #define A_PCIE_VF_MSI_EN_4 0x5e50
10641 #define A_PCIE_VF_MSI_EN_5 0x5e54
10642 #define A_PCIE_VF_MSI_EN_6 0x5e58
10643 #define A_PCIE_VF_MSI_EN_7 0x5e5c
10644 #define A_PCIE_VF_MSIX_EN_4 0x5e60
10645 #define A_PCIE_VF_MSIX_EN_5 0x5e64
10646 #define A_PCIE_VF_MSIX_EN_6 0x5e68
10647 #define A_PCIE_VF_MSIX_EN_7 0x5e6c
10648 #define A_PCIE_FLR_VF4_STATUS 0x5e70
10649 #define A_PCIE_FLR_VF5_STATUS 0x5e74
10650 #define A_PCIE_FLR_VF6_STATUS 0x5e78
10651 #define A_PCIE_FLR_VF7_STATUS 0x5e7c
10652 #define A_T6_PCIE_BUS_MST_STAT_4 0x5e80
10653 #define A_T7_PCIE_BUS_MST_STAT_4 0x5e80
10654 #define A_T6_PCIE_BUS_MST_STAT_5 0x5e84
10655 #define A_T7_PCIE_BUS_MST_STAT_5 0x5e84
10656 #define A_T6_PCIE_BUS_MST_STAT_6 0x5e88
10657 #define A_T7_PCIE_BUS_MST_STAT_6 0x5e88
10658 #define A_T6_PCIE_BUS_MST_STAT_7 0x5e8c
10659 #define A_T7_PCIE_BUS_MST_STAT_7 0x5e8c
10660 #define A_PCIE_BUS_MST_STAT_8 0x5e90
10662 #define S_BUSMST_263_256    0
10663 #define M_BUSMST_263_256    0xffU
10667 #define A_PCIE_TGT_SKID_FIFO 0x5e94
10670 #define M_HDRFREECNT    0xfffU
10674 #define S_DATAFREECNT    0
10675 #define M_DATAFREECNT    0xfffU
10679 #define A_T6_PCIE_RSP_ERR_STAT_4 0x5ea0
10680 #define A_T7_PCIE_RSP_ERR_STAT_4 0x5ea0
10681 #define A_T6_PCIE_RSP_ERR_STAT_5 0x5ea4
10682 #define A_T7_PCIE_RSP_ERR_STAT_5 0x5ea4
10683 #define A_T6_PCIE_RSP_ERR_STAT_6 0x5ea8
10684 #define A_T7_PCIE_RSP_ERR_STAT_6 0x5ea8
10685 #define A_T6_PCIE_RSP_ERR_STAT_7 0x5eac
10686 #define A_T7_PCIE_RSP_ERR_STAT_7 0x5eac
10687 #define A_PCIE_RSP_ERR_STAT_8 0x5eb0
10689 #define S_RSPERR_263_256    0
10690 #define M_RSPERR_263_256    0xffU
10694 #define A_PCIE_PHY_STAT1 0x5ec0
10704 #define A_PCIE_PHY_CTRL1 0x5ec4
10715 #define M_TXDEEMPH_GEN1    0xffU
10720 #define M_TXDEEMPH_GEN2_3P5DB    0xffU
10724 #define S_TXDEEMPH_GEN2_6DB    0
10725 #define M_TXDEEMPH_GEN2_6DB    0xffU
10729 #define A_PCIE_PCIE_SPARE0 0x5ec8
10730 #define A_PCIE_RESET_STAT 0x5ecc
10764 #define S_LASTRESETSTATE    0
10765 #define M_LASTRESETSTATE    0x7U
10769 #define A_PCIE_FUNC_DSTATE 0x5ed0
10772 #define M_PF7_DSTATE    0x7U
10777 #define M_PF6_DSTATE    0x7U
10782 #define M_PF5_DSTATE    0x7U
10787 #define M_PF4_DSTATE    0x7U
10792 #define M_PF3_DSTATE    0x7U
10797 #define M_PF2_DSTATE    0x7U
10802 #define M_PF1_DSTATE    0x7U
10806 #define S_PF0_DSTATE    0
10807 #define M_PF0_DSTATE    0x7U
10811 #define A_PCIE_DEBUG_ADDR_RANGE1 0x5ee0
10812 #define A_PCIE_DEBUG_ADDR_RANGE2 0x5ef0
10813 #define A_PCIE_DEBUG_ADDR_RANGE_CNT 0x5f00
10814 #define A_PCIE_PHY_PGM_LOAD_CTRL 0x5f04
10820 #define S_HSS_PMRDWR_ADDR    0
10821 #define M_HSS_PMRDWR_ADDR    0x3ffffU
10825 #define A_PCIE_PHY_PGM_LOAD_DATA 0x5f08
10826 #define A_PCIE_HSS_CFG 0x5f0c
10829 #define M_HSS_PCS_AGGREGATION_MODE    0x3U
10834 #define M_HSS_PCS_FURCATE_MODE    0x3U
10843 #define M_HSS0_PHY_CTRL_REFCLK    0x1fU
10848 #define M_HSS1_PHY_CTRL_REFCLK    0x1fU
10896 #define A_PCIE_HSS_RST 0x5f10
10954 #define S_HSS0_PLL_LOCK    0
10958 #define A_PCIE_T5_ARM_CFG 0x5f20
10961 #define M_T5_ARM_MAXREQCNT    0x7fU
10966 #define M_T5_ARM_MAXRDREQSIZE    0x7U
10971 #define M_T5_ARM_MAXRSPCNT    0xffU
10975 #define A_PCIE_T5_ARM_STAT 0x5f24
10978 #define M_ARM_RESPCNT    0x1ffU
10983 #define M_ARM_RDREQCNT    0x3fU
10987 #define S_ARM_WRREQCNT    0
10988 #define M_ARM_WRREQCNT    0x1ffU
10992 #define A_PCIE_T5_ARM_STAT2 0x5f28
10995 #define M_ARM_COOKIECNT    0xfU
11000 #define M_ARM_RDSEQNUMUPDCNT    0xfU
11005 #define M_ARM_SIREQCNT    0xfU
11014 #define M_ARM_WRSOPCNT    0xfU
11018 #define S_ARM_RDSOPCNT    0
11019 #define M_ARM_RDSOPCNT    0xffU
11023 #define A_PCIE_T5_ARM_STAT3 0x5f2c
11026 #define M_ARM_ATMREQSOPCNT    0xffU
11039 #define M_ARM_RSPERRCNT    0xffU
11043 #define S_ARM_RSPSOPCNT    0
11044 #define M_ARM_RSPSOPCNT    0xffU
11048 #define A_PCIE_ARM_REQUESTER_ID 0x5f30
11051 #define M_A0_RSVD1    0xffU
11056 #define M_A0_PRIMBUSNUMBER    0xffU
11060 #define S_A0_REQUESTERID    0
11061 #define M_A0_REQUESTERID    0xffffU
11065 #define A_PCIE_SWITCH_CFG_SPACE_REQ0 0x5f34
11076 #define M_BYTEENABLE0    0xfU
11080 #define S_REGADDR0    0
11081 #define M_REGADDR0    0x7fffU
11085 #define A_PCIE_SWITCH_CFG_SPACE_DATA0 0x5f38
11086 #define A_PCIE_SWITCH_CFG_SPACE_REQ1 0x5f3c
11093 #define M_RDREQ1TYPE    0xfU
11098 #define M_BYTEENABLE1    0x7ffU
11102 #define S_REGADDR1    0
11103 #define M_REGADDR1    0x7fffU
11107 #define A_PCIE_SWITCH_CFG_SPACE_DATA1 0x5f40
11108 #define A_PCIE_SWITCH_CFG_SPACE_REQ2 0x5f44
11115 #define M_RDREQ2TYPE    0xfU
11120 #define M_BYTEENABLE2    0x7ffU
11124 #define S_REGADDR2    0
11125 #define M_REGADDR2    0x7fffU
11129 #define A_PCIE_SWITCH_CFG_SPACE_DATA2 0x5f48
11130 #define A_PCIE_SWITCH_CFG_SPACE_REQ3 0x5f4c
11137 #define M_RDREQ3TYPE    0xfU
11142 #define M_BYTEENABLE3    0x7ffU
11146 #define S_REGADDR3    0
11147 #define M_REGADDR3    0x7fffU
11151 #define A_PCIE_SWITCH_CFG_SPACE_DATA3 0x5f50
11152 #define A_PCIE_SWITCH_CFG_SPACE_REQ4 0x5f54
11159 #define M_RDREQ4TYPE    0xfU
11164 #define M_BYTEENABLE4    0x7ffU
11168 #define S_REGADDR4    0
11169 #define M_REGADDR4    0x7fffU
11173 #define A_PCIE_SWITCH_CFG_SPACE_DATA4 0x5f58
11174 #define A_PCIE_SWITCH_CFG_SPACE_REQ5 0x5f5c
11181 #define M_RDREQ5TYPE    0xfU
11186 #define M_BYTEENABLE5    0x7ffU
11190 #define S_REGADDR5    0
11191 #define M_REGADDR5    0x7fffU
11195 #define A_PCIE_SWITCH_CFG_SPACE_DATA5 0x5f60
11196 #define A_PCIE_SWITCH_CFG_SPACE_REQ6 0x5f64
11203 #define M_RDREQ6TYPE    0xfU
11208 #define M_BYTEENABLE6    0x7ffU
11212 #define S_REGADDR6    0
11213 #define M_REGADDR6    0x7fffU
11217 #define A_PCIE_SWITCH_CFG_SPACE_DATA6 0x5f68
11218 #define A_PCIE_SWITCH_CFG_SPACE_REQ7 0x5f6c
11225 #define M_RDREQ7TYPE    0xfU
11230 #define M_BYTEENABLE7    0x7ffU
11234 #define S_REGADDR7    0
11235 #define M_REGADDR7    0x7fffU
11239 #define A_PCIE_SWITCH_CFG_SPACE_DATA7 0x5f70
11240 #define A_PCIE_SWITCH_CFG_SPACE_REQ8 0x5f74
11247 #define M_RDREQ8TYPE    0xfU
11252 #define M_BYTEENABLE8    0x7ffU
11256 #define S_REGADDR8    0
11257 #define M_REGADDR8    0x7fffU
11261 #define A_PCIE_SWITCH_CFG_SPACE_DATA8 0x5f78
11262 #define A_PCIE_SNPS_G5_PHY_CR_REQ 0x5f7c
11277 #define M_AUTOINCRVAL    0x3U
11286 #define M_PHYSEL    0xfU
11290 #define S_T7_REGADDR    0
11291 #define M_T7_REGADDR    0xffffU
11295 #define A_PCIE_SNPS_G5_PHY_CR_DATA 0x5f80
11296 #define A_PCIE_SNPS_G5_PHY_SRAM_CFG 0x5f84
11347 #define M_PHY_CR_PARA_SEL    0xfU
11363 #define S_PHY0_SRAM_EXT_LD_DONE    0
11367 #define A_PCIE_SNPS_G5_PHY_SRAM_STS 0x5f88
11381 #define S_PHY0_SRAM_INIT_DONE    0
11385 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_TO_3 0x5f90
11386 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_0_DATA 0x5f94
11387 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_1_DATA 0x5f98
11388 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_2_DATA 0x5f9c
11389 #define A_PCIE_SNPS_G5_PHY_CTRL_PHY_3_DATA 0x5fa0
11390 #define A_PCIE_SNPS_G5_PHY_DEFAULTS 0x5fa4
11391 #define A_PCIE_SNPS_G5_PHY_0_VALUES 0x5fa8
11402 #define M_REFB_RANGE    0xfU
11419 #define M_REFA_RANGE    0xfU
11432 #define M_NOMINAL_VPH_SEL    0x3U
11437 #define M_NOMINAL_VP_SEL    0x3U
11469 #define S_MPLLA_FORCE_EN    0
11473 #define A_PCIE_SNPS_G5_PHY_1_VALUES 0x5fac
11483 #define A_PCIE_SNPS_G5_PHY_2_VALUES 0x5fb0
11484 #define A_PCIE_SNPS_G5_PHY_3_VALUES 0x5fb4
11485 #define A_PCIE_SNPS_G5_PHY_0_RX_LANEPLL_BYPASS_MODE 0x5fb8
11488 #define M_T7_LANE3    0x1fU
11493 #define M_T7_LANE2    0x1fU
11498 #define M_T7_LANE1    0x1fU
11502 #define S_T7_LANE0    0
11503 #define M_T7_LANE0    0x1fU
11507 #define A_PCIE_SNPS_G5_PHY_1_RX_LANEPLL_BYPASS_MODE 0x5fbc
11508 #define A_PCIE_SNPS_G5_PHY_2_RX_LANEPLL_BYPASS_MODE 0x5fc0
11509 #define A_PCIE_SNPS_G5_PHY_3_RX_LANEPLL_BYPASS_MODE 0x5fc4
11510 #define A_PCIE_SNPS_G5_PHY_0_1_RX_LANEPLL_SRC_SEL 0x5fc8
11513 #define M_LANE7_LANEPLL_SRC_SEL    0xfU
11518 #define M_LANE6_LANEPLL_SRC_SEL    0xfU
11523 #define M_LANE5_LANEPLL_SRC_SEL    0xfU
11528 #define M_LANE4_LANEPLL_SRC_SEL    0xfU
11533 #define M_LANE3_LANEPLL_SRC_SEL    0xfU
11538 #define M_LANE2_LANEPLL_SRC_SEL    0xfU
11543 #define M_LANE1_LANEPLL_SRC_SEL    0xfU
11547 #define S_LANE0_LANEPLL_SRC_SEL    0
11548 #define M_LANE0_LANEPLL_SRC_SEL    0xfU
11552 #define A_PCIE_SNPS_G5_PHY_2_3_RX_LANEPLL_SRC_SEL 0x5fcc
11553 #define A_PCIE_SNPS_G5_PHY_RX_DECERR 0x5fd0
11556 #define M_LANE15_REC_OVRD_8B10B_DECERR    0x3U
11561 #define M_LANE14_REC_OVRD_8B10B_DECERR    0x3U
11566 #define M_LANE13_REC_OVRD_8B10B_DECERR    0x3U
11571 #define M_LANE12_REC_OVRD_8B10B_DECERR    0x3U
11576 #define M_LANE11_REC_OVRD_8B10B_DECERR    0x3U
11581 #define M_LANE10_REC_OVRD_8B10B_DECERR    0x3U
11586 #define M_LANE9_REC_OVRD_8B10B_DECERR    0x3U
11591 #define M_LANE8_REC_OVRD_8B10B_DECERR    0x3U
11596 #define M_LANE7_REC_OVRD_8B10B_DECERR    0x3U
11601 #define M_LANE6_REC_OVRD_8B10B_DECERR    0x3U
11606 #define M_LANE5_REC_OVRD_8B10B_DECERR    0x3U
11611 #define M_LANE4_REC_OVRD_8B10B_DECERR    0x3U
11616 #define M_LANE3_REC_OVRD_8B10B_DECERR    0x3U
11621 #define M_LANE2_REC_OVRD_8B10B_DECERR    0x3U
11626 #define M_LANE1_REC_OVRD_8B10B_DECERR    0x3U
11630 #define S_LANE0_REC_OVRD_8B10B_DECERR    0
11631 #define M_LANE0_REC_OVRD_8B10B_DECERR    0x3U
11635 #define A_PCIE_SNPS_G5_PHY_TX2RX_LOOPBK_REC_OVRD_EN 0x5fd4
11761 #define S_LANE0_TX2RX_LOOPBK    0
11765 #define A_PCIE_PHY_TX_DISABLE_UPCS_PIPE_CONFIG 0x5fd8
11768 #define M_UPCS_PIPE_CONFIG    0xffffU
11832 #define S_TX0_DISABLE    0
11836 #define A_PCIE_PDEBUG_REG_0X0 0x0
11837 #define A_PCIE_PDEBUG_REG_0X1 0x1
11838 #define A_PCIE_PDEBUG_REG_0X2 0x2
11841 #define M_TAGQ_CH0_TAGS_USED    0xffU
11885 #define S_REQ_CTL_RD_CH0_WAIT_FOR_FIFO_DATA    0
11889 #define A_PCIE_PDEBUG_REG_0X3 0x3
11892 #define M_TAGQ_CH1_TAGS_USED    0xffU
11936 #define S_REQ_CTL_RD_CH1_WAIT_FOR_FIFO_DATA    0
11940 #define A_PCIE_PDEBUG_REG_0X4 0x4
11943 #define M_TAGQ_CH2_TAGS_USED    0xffU
11987 #define S_REQ_CTL_RD_CH2_WAIT_FOR_FIFO_DATA    0
11991 #define A_PCIE_PDEBUG_REG_0X5 0x5
11994 #define M_TAGQ_CH3_TAGS_USED    0xffU
12038 #define S_REQ_CTL_RD_CH3_WAIT_FOR_FIFO_DATA    0
12042 #define A_PCIE_PDEBUG_REG_0X6 0x6
12045 #define M_TAGQ_CH4_TAGS_USED    0xffU
12089 #define S_REQ_CTL_RD_CH4_WAIT_FOR_FIFO_DATA    0
12093 #define A_PCIE_PDEBUG_REG_0X7 0x7
12096 #define M_TAGQ_CH5_TAGS_USED    0xffU
12140 #define S_REQ_CTL_RD_CH5_WAIT_FOR_FIFO_DATA    0
12144 #define A_PCIE_PDEBUG_REG_0X8 0x8
12147 #define M_TAGQ_CH6_TAGS_USED    0xffU
12191 #define S_REQ_CTL_RD_CH6_WAIT_FOR_FIFO_DATA    0
12195 #define A_PCIE_PDEBUG_REG_0X9 0x9
12198 #define M_TAGQ_CH7_TAGS_USED    0xffU
12242 #define S_REQ_CTL_RD_CH7_WAIT_FOR_FIFO_DATA    0
12246 #define A_PCIE_PDEBUG_REG_0XA 0xa
12253 #define M_REQ_CTL_WR_CH0_SEQNUM    0xffU
12258 #define M_REQ_CTL_RD_CH0_SEQNUM    0xffU
12278 #define S_REQ_CTL_WR_CH0_WAIT_FOR_FIFO_DATA    0
12282 #define A_PCIE_PDEBUG_REG_0XB 0xb
12289 #define M_REQ_CTL_WR_CH1_SEQNUM    0xffU
12294 #define M_REQ_CTL_RD_CH1_SEQNUM    0xffU
12314 #define S_REQ_CTL_WR_CH1_WAIT_FOR_FIFO_DATA    0
12318 #define A_PCIE_PDEBUG_REG_0XC 0xc
12325 #define M_REQ_CTL_WR_CH2_SEQNUM    0xffU
12330 #define M_REQ_CTL_RD_CH2_SEQNUM    0xffU
12350 #define S_REQ_CTL_WR_CH2_WAIT_FOR_FIFO_DATA    0
12354 #define A_PCIE_PDEBUG_REG_0XD 0xd
12361 #define M_REQ_CTL_WR_CH3_SEQNUM    0xffU
12366 #define M_REQ_CTL_RD_CH3_SEQNUM    0xffU
12386 #define S_REQ_CTL_WR_CH3_WAIT_FOR_FIFO_DATA    0
12390 #define A_PCIE_PDEBUG_REG_0XE 0xe
12397 #define M_REQ_CTL_WR_CH4_SEQNUM    0xffU
12402 #define M_REQ_CTL_RD_CH4_SEQNUM    0xffU
12422 #define S_REQ_CTL_WR_CH4_WAIT_FOR_FIFO_DATA    0
12426 #define A_PCIE_PDEBUG_REG_0XF 0xf
12427 #define A_PCIE_PDEBUG_REG_0X10 0x10
12434 #define M_PIPE0_TX3_DATA_6_0    0x7fU
12439 #define M_PIPE0_TX2_DATA_7_0    0xffU
12444 #define M_PIPE0_TX1_DATA_7_0    0xffU
12452 #define S_PIPE0_TX0_DATA_6_0    0
12453 #define M_PIPE0_TX0_DATA_6_0    0x7fU
12457 #define A_PCIE_PDEBUG_REG_0X11 0x11
12464 #define M_PIPE0_TX3_DATA_14_8    0x7fU
12469 #define M_PIPE0_TX2_DATA_15_8    0xffU
12474 #define M_PIPE0_TX1_DATA_15_8    0xffU
12482 #define S_PIPE0_TX0_DATA_14_8    0
12483 #define M_PIPE0_TX0_DATA_14_8    0x7fU
12487 #define A_PCIE_PDEBUG_REG_0X12 0x12
12494 #define M_PIPE0_TX7_DATA_6_0    0x7fU
12499 #define M_PIPE0_TX6_DATA_7_0    0xffU
12504 #define M_PIPE0_TX5_DATA_7_0    0xffU
12512 #define S_PIPE0_TX4_DATA_6_0    0
12513 #define M_PIPE0_TX4_DATA_6_0    0x7fU
12517 #define A_PCIE_PDEBUG_REG_0X13 0x13
12524 #define M_PIPE0_TX7_DATA_14_8    0x7fU
12529 #define M_PIPE0_TX6_DATA_15_8    0xffU
12534 #define M_PIPE0_TX5_DATA_15_8    0xffU
12542 #define S_PIPE0_TX4_DATA_14_8    0
12543 #define M_PIPE0_TX4_DATA_14_8    0x7fU
12547 #define A_PCIE_PDEBUG_REG_0X14 0x14
12554 #define M_PIPE0_RX3_VALID2_14    0x7fU
12559 #define M_PIPE0_RX2_VALID_14    0xffU
12564 #define M_PIPE0_RX1_VALID_14    0xffU
12572 #define S_PIPE0_RX0_VALID2_14    0
12573 #define M_PIPE0_RX0_VALID2_14    0x7fU
12577 #define A_PCIE_PDEBUG_REG_0X15 0x15
12584 #define M_PIPE0_RX3_VALID2_15    0x7fU
12589 #define M_PIPE0_RX2_VALID_15    0xffU
12594 #define M_PIPE0_RX1_VALID_15    0xffU
12602 #define S_PIPE0_RX0_VALID2_15    0
12603 #define M_PIPE0_RX0_VALID2_15    0x7fU
12607 #define A_PCIE_PDEBUG_REG_0X16 0x16
12614 #define M_PIPE0_RX7_VALID2_16    0x7fU
12619 #define M_PIPE0_RX6_VALID_16    0xffU
12624 #define M_PIPE0_RX5_VALID_16    0xffU
12632 #define S_PIPE0_RX4_VALID2_16    0
12633 #define M_PIPE0_RX4_VALID2_16    0x7fU
12637 #define A_PCIE_PDEBUG_REG_0X17 0x17
12644 #define M_PIPE0_RX7_VALID2_17    0x7fU
12649 #define M_PIPE0_RX6_VALID_17    0xffU
12654 #define M_PIPE0_RX5_VALID_17    0xffU
12662 #define S_PIPE0_RX4_VALID2_17    0
12663 #define M_PIPE0_RX4_VALID2_17    0x7fU
12667 #define A_PCIE_PDEBUG_REG_0X18 0x18
12674 #define M_PIPE0_RX7_STATUS    0x7U
12683 #define M_PIPE0_RX6_STATUS    0x7U
12692 #define M_PIPE0_RX5_STATUS    0x7U
12701 #define M_PIPE0_RX4_STATUS    0x7U
12710 #define M_PIPE0_RX3_STATUS    0x7U
12719 #define M_PIPE0_RX2_STATUS    0x7U
12728 #define M_PIPE0_RX1_STATUS    0x7U
12736 #define S_PIPE0_RX0_STATUS    0
12737 #define M_PIPE0_RX0_STATUS    0x7U
12741 #define A_PCIE_PDEBUG_REG_0X19 0x19
12867 #define S_PIPE0_RX0_ELECIDLE    0
12871 #define A_PCIE_PDEBUG_REG_0X1A 0x1a
12902 #define M_PIPE0_TX_MARGIN    0x7U
12915 #define M_PIPE0_POWERDOWN    0x3U
12919 #define S_PHY_MAC_PHYSTATUS    0
12920 #define M_PHY_MAC_PHYSTATUS    0xffU
12924 #define A_PCIE_PDEBUG_REG_0X1B 0x1b
12935 #define M_PIPE0_RX7_SYNCHEADER    0x3U
12948 #define M_PIPE0_RX6_SYNCHEADER    0x3U
12961 #define M_PIPE0_RX5_SYNCHEADER    0x3U
12974 #define M_PIPE0_RX4_SYNCHEADER    0x3U
12987 #define M_PIPE0_RX3_SYNCHEADER    0x3U
13000 #define M_PIPE0_RX2_SYNCHEADER    0x3U
13013 #define M_PIPE0_RX1_SYNCHEADER    0x3U
13025 #define S_PIPE0_RX0_SYNCHEADER    0
13026 #define M_PIPE0_RX0_SYNCHEADER    0x3U
13030 #define A_PCIE_PDEBUG_REG_0X1C 0x1c
13033 #define M_SI_REQVFID    0xffU
13038 #define M_SI_REQVEC    0x7ffU
13043 #define M_SI_REQTCVAL    0x7U
13055 #define S_T5_AI    0
13056 #define M_T5_AI    0xffU
13060 #define A_PCIE_PDEBUG_REG_0X1D 0x1d
13071 #define M_SMARB    0x7U
13076 #define M_SMDEFR    0x7U
13081 #define M_SYS_INT    0xffU
13086 #define M_CFG_INTXCLR    0xffU
13090 #define S_PIO_INTXCLR    0
13091 #define M_PIO_INTXCLR    0xffU
13095 #define A_PCIE_PDEBUG_REG_0X1E 0x1e
13106 #define M_TAB_RDENA2    0x7ffU
13111 #define M_PLI_REQADDR    0x1ffU
13116 #define M_PLI_REQVFID    0xffU
13124 #define S_PLI_REQRDVLD    0
13128 #define A_PCIE_PDEBUG_REG_0X1F 0x1f
13129 #define A_PCIE_PDEBUG_REG_0X20 0x20
13130 #define A_PCIE_PDEBUG_REG_0X21 0x21
13133 #define M_PLI_REQPBASTART    0xfffU
13138 #define M_PLI_REQPBAEND    0x7ffU
13143 #define M_T5_PLI_REQVFID    0x7fU
13151 #define A_PCIE_PDEBUG_REG_0X22 0x22
13162 #define M_GNTSI3    0x7U
13167 #define M_GNTSI4    0x7ffU
13172 #define M_GNTSI5    0xffU
13204 #define S_GNTDI    0
13208 #define A_PCIE_PDEBUG_REG_0X23 0x23
13219 #define M_DI_REQWREN    0x7ffU
13236 #define M_DI_REQWREN2    0x3fffU
13244 #define S_DI_REQWREN3    0
13248 #define A_PCIE_PDEBUG_REG_0X24 0x24
13249 #define A_PCIE_PDEBUG_REG_0X25 0x25
13250 #define A_PCIE_PDEBUG_REG_0X26 0x26
13251 #define A_PCIE_PDEBUG_REG_0X27 0x27
13266 #define M_TAB_STIRDENA2    0x7ffU
13271 #define M_T5_PLI_REQTABHIT    0x7ffU
13275 #define S_T5_GNTSI    0
13276 #define M_T5_GNTSI    0x7fU
13280 #define A_PCIE_PDEBUG_REG_0X28 0x28
13307 #define M_AI_REQVLD    0x7U
13320 #define M_VEN_MSI_REQ_28    0x7U
13325 #define M_VEN_MSI_REQ2    0x7fU
13330 #define M_VEN_MSI_REQ3    0x1fU
13335 #define M_VEN_MSI_REQ4    0x7U
13347 #define S_VEN_MSI_REQ6    0
13351 #define A_PCIE_PDEBUG_REG_0X29 0x29
13354 #define M_TRGT1_REQDATAVLD    0xffffU
13359 #define M_TRGT1_REQDATAVLD2    0xfU
13380 #define M_TRGT1_REQDATAVLD7    0xfU
13385 #define M_TRGT1_REQDATAVLD8    0x3U
13393 #define S_TRGT1_REQDATAVLD0    0
13397 #define A_PCIE_PDEBUG_REG_0X2A 0x2a
13398 #define A_PCIE_PDEBUG_REG_0X2B 0x2b
13401 #define M_RADM_TRGT1_ADDR    0xfffU
13406 #define M_RADM_TRGT1_DWEN    0xfU
13411 #define M_RADM_TRGT1_FMT    0x3U
13416 #define M_RADM_TRGT1_TYPE    0x1fU
13421 #define M_RADM_TRGT1_IN_MEMBAR_RANGE    0x7U
13445 #define S_RADM_TRGT1_HV_2B    0
13449 #define A_PCIE_PDEBUG_REG_0X2C 0x2c
13452 #define M_STATEMPIO    0x7U
13457 #define M_STATECPL    0xfU
13462 #define M_STATEALIN    0x7U
13467 #define M_STATEPL    0x7U
13476 #define M_MA_TAGSINUSE    0x7fU
13520 #define S_RADM_TRGT1_ECRC_ERR_2C    0
13524 #define A_PCIE_PDEBUG_REG_0X2D 0x2d
13535 #define M_RADM_TRGT1_HV2    0x7fU
13540 #define M_RADM_TRGT1_HV3    0x7U
13545 #define M_RADM_TRGT1_HV4    0xfU
13550 #define M_RADM_TRGT1_HV5    0xfU
13563 #define M_RADM_TRGT1_HV8    0x7U
13579 #define S_RADM_TRGT1_WRCNT    0
13580 #define M_RADM_TRGT1_WRCNT    0xfU
13584 #define A_PCIE_PDEBUG_REG_0X2E 0x2e
13587 #define M_RADM_TRGT1_HV_2E    0x3U
13592 #define M_RADM_TRGT1_HV_2E_2    0x3ffU
13597 #define M_RADM_TRGT1_HV_WE_3    0xffU
13602 #define M_ALIN_REQDATAVLD4    0xfU
13615 #define M_ALIN_REQDATAVLD7    0x3U
13631 #define S_ALIN_REQDATAVLDA    0
13635 #define A_PCIE_PDEBUG_REG_0X2F 0x2f
13636 #define A_PCIE_PDEBUG_REG_0X30 0x30
13639 #define M_RADM_TRGT1_HV_30    0x7fU
13644 #define M_PIO_WRCNT    0x3ffU
13649 #define M_ALIND_REQWRCNT    0x7U
13654 #define M_FID_LKUPWRCNT    0x7U
13671 #define M_ALIND_REQWRDATAVLD3    0x7U
13683 #define S_ALIND_REQWRDATAVLD5    0
13687 #define A_PCIE_PDEBUG_REG_0X31 0x31
13688 #define A_PCIE_PDEBUG_REG_0X32 0x32
13689 #define A_PCIE_PDEBUG_REG_0X33 0x33
13690 #define A_PCIE_PDEBUG_REG_0X34 0x34
13691 #define A_PCIE_PDEBUG_REG_0X35 0x35
13694 #define M_T5_MPIO_WRVLD    0x1fffU
13758 #define S_MPIO_WRVLD4    0
13759 #define M_MPIO_WRVLD4    0xfU
13763 #define A_PCIE_PDEBUG_REG_0X36 0x36
13764 #define A_PCIE_PDEBUG_REG_0X37 0x37
13765 #define A_PCIE_PDEBUG_REG_0X38 0x38
13766 #define A_PCIE_PDEBUG_REG_0X39 0x39
13767 #define A_PCIE_PDEBUG_REG_0X3A 0x3a
13774 #define M_CLIENT0_TLP_VFUNC_NUM    0x7fU
13779 #define M_CLIENT0_TLP_FUNC_NUM    0x7U
13784 #define M_CLIENT0_TLP_BYTE_EN    0xffU
13788 #define S_CLIENT0_TLP_BYTE_LEN    0
13789 #define M_CLIENT0_TLP_BYTE_LEN    0x1fffU
13793 #define A_PCIE_PDEBUG_REG_0X3B 0x3b
13816 #define M_CLIENT0_CPL_STATUS    0x7U
13825 #define M_CLIENT0_TLP_TYPE    0x1fU
13830 #define M_CLIENT0_TLP_FMT    0x3U
13843 #define M_CLIENT0_TLP_ATTR    0x7U
13848 #define M_CLIENT0_TLP_TC    0x7U
13852 #define S_CLIENT0_TLP_TID    0
13853 #define M_CLIENT0_TLP_TID    0xffU
13857 #define A_PCIE_PDEBUG_REG_0X3C 0x3c
13892 #define M_TGT_TAGQ_RDVLD    0xffU
13897 #define M_CPLTXNDISABLE    0xffU
13905 #define S_CLIENT0_TLP_HV    0
13906 #define M_CLIENT0_TLP_HV    0x7fU
13910 #define A_PCIE_PDEBUG_REG_0X3D 0x3d
13911 #define A_PCIE_PDEBUG_REG_0X3E 0x3e
13912 #define A_PCIE_PDEBUG_REG_0X3F 0x3f
13913 #define A_PCIE_PDEBUG_REG_0X40 0x40
13914 #define A_PCIE_PDEBUG_REG_0X41 0x41
13915 #define A_PCIE_PDEBUG_REG_0X42 0x42
13916 #define A_PCIE_PDEBUG_REG_0X43 0x43
13917 #define A_PCIE_PDEBUG_REG_0X44 0x44
13918 #define A_PCIE_PDEBUG_REG_0X45 0x45
13919 #define A_PCIE_PDEBUG_REG_0X46 0x46
13920 #define A_PCIE_PDEBUG_REG_0X47 0x47
13921 #define A_PCIE_PDEBUG_REG_0X48 0x48
13922 #define A_PCIE_PDEBUG_REG_0X49 0x49
13923 #define A_PCIE_PDEBUG_REG_0X4A 0x4a
13924 #define A_PCIE_PDEBUG_REG_0X4B 0x4b
13925 #define A_PCIE_PDEBUG_REG_0X4C 0x4c
13926 #define A_PCIE_PDEBUG_REG_0X4D 0x4d
13927 #define A_PCIE_PDEBUG_REG_0X4E 0x4e
13928 #define A_PCIE_PDEBUG_REG_0X4F 0x4f
13929 #define A_PCIE_PDEBUG_REG_0X50 0x50
13930 #define A_PCIE_CDEBUG_REG_0X0 0x0
13931 #define A_PCIE_CDEBUG_REG_0X1 0x1
13932 #define A_PCIE_CDEBUG_REG_0X2 0x2
13939 #define M_D_RSPVLD    0x7U
13960 #define M_D_RSPVLD6    0xfU
13965 #define M_D_RSPAFULL    0xfU
13970 #define M_D_RDREQVLD    0xfU
13975 #define M_D_RDREQAFULL    0xfU
13980 #define M_D_WRREQVLD    0xfU
13984 #define S_D_WRREQAFULL    0
13985 #define M_D_WRREQAFULL    0xfU
13989 #define A_PCIE_CDEBUG_REG_0X3 0x3
13992 #define M_C_REQVLD    0x1fffU
13997 #define M_C_RSPVLD2    0x7U
14018 #define M_C_RSPVLD7    0x7U
14023 #define M_C_RSPAFULL    0x7U
14028 #define M_C_REQVLD8    0x7U
14032 #define S_C_REQAFULL    0
14033 #define M_C_REQAFULL    0x7U
14037 #define A_PCIE_CDEBUG_REG_0X4 0x4
14040 #define M_H_REQVLD    0x1ffffffU
14068 #define S_H_REQAFULL    0
14072 #define A_PCIE_CDEBUG_REG_0X5 0x5
14075 #define M_ER_RSPVLD    0xffffU
14080 #define M_ER_REQVLD2    0x7ffU
14085 #define M_ER_REQVLD3    0x7U
14093 #define S_ER_REQVLD5    0
14097 #define A_PCIE_CDEBUG_REG_0X6 0x6
14100 #define M_PL_BAR2_REQVLD    0xfffffffU
14116 #define S_PL_BAR2_REQVLD4    0
14120 #define A_PCIE_CDEBUG_REG_0X7 0x7
14121 #define A_PCIE_CDEBUG_REG_0X8 0x8
14122 #define A_PCIE_CDEBUG_REG_0X9 0x9
14123 #define A_PCIE_CDEBUG_REG_0XA 0xa
14126 #define M_VPD_RSPVLD    0xfffU
14131 #define M_VPD_REQVLD2    0x7ffU
14136 #define M_VPD_REQVLD3    0x7U
14145 #define M_VPD_REQVLD5    0x3U
14157 #define S_VPD_REQVLD6    0
14161 #define A_PCIE_CDEBUG_REG_0XB 0xb
14164 #define M_MA_REQDATAVLD    0xfU
14177 #define M_MA_RSPDATAVLD2    0xfU
14182 #define M_MA_REQADDRVLD3    0x3U
14187 #define M_MA_REQADDRVLD4    0xffffU
14203 #define S_MA_REQADDRVLD7    0
14207 #define A_PCIE_CDEBUG_REG_0XC 0xc
14208 #define A_PCIE_CDEBUG_REG_0XD 0xd
14209 #define A_PCIE_CDEBUG_REG_0XE 0xe
14210 #define A_PCIE_CDEBUG_REG_0XF 0xf
14211 #define A_PCIE_CDEBUG_REG_0X10 0x10
14212 #define A_PCIE_CDEBUG_REG_0X11 0x11
14213 #define A_PCIE_CDEBUG_REG_0X12 0x12
14214 #define A_PCIE_CDEBUG_REG_0X13 0x13
14215 #define A_PCIE_CDEBUG_REG_0X14 0x14
14216 #define A_PCIE_CDEBUG_REG_0X15 0x15
14219 #define M_PLM_REQVLD    0x1fffU
14252 #define M_PLM_REQVLD9    0xffU
14257 #define M_PLM_REQVLDA    0x7U
14261 #define S_PLM_REQVLDB    0
14265 #define A_PCIE_CDEBUG_REG_0X16 0x16
14266 #define A_PCIE_CDEBUG_REG_0X17 0x17
14267 #define A_PCIE_CDEBUG_REG_0X18 0x18
14268 #define A_PCIE_CDEBUG_REG_0X19 0x19
14269 #define A_PCIE_CDEBUG_REG_0X1A 0x1a
14270 #define A_PCIE_CDEBUG_REG_0X1B 0x1b
14271 #define A_PCIE_CDEBUG_REG_0X1C 0x1c
14272 #define A_PCIE_CDEBUG_REG_0X1D 0x1d
14273 #define A_PCIE_CDEBUG_REG_0X1E 0x1e
14274 #define A_PCIE_CDEBUG_REG_0X1F 0x1f
14275 #define A_PCIE_CDEBUG_REG_0X20 0x20
14276 #define A_PCIE_CDEBUG_REG_0X21 0x21
14277 #define A_PCIE_CDEBUG_REG_0X22 0x22
14278 #define A_PCIE_CDEBUG_REG_0X23 0x23
14279 #define A_PCIE_CDEBUG_REG_0X24 0x24
14280 #define A_PCIE_CDEBUG_REG_0X25 0x25
14281 #define A_PCIE_CDEBUG_REG_0X26 0x26
14282 #define A_PCIE_CDEBUG_REG_0X27 0x27
14283 #define A_PCIE_CDEBUG_REG_0X28 0x28
14284 #define A_PCIE_CDEBUG_REG_0X29 0x29
14285 #define A_PCIE_CDEBUG_REG_0X2A 0x2a
14286 #define A_PCIE_CDEBUG_REG_0X2B 0x2b
14287 #define A_PCIE_CDEBUG_REG_0X2C 0x2c
14288 #define A_PCIE_CDEBUG_REG_0X2D 0x2d
14289 #define A_PCIE_CDEBUG_REG_0X2E 0x2e
14290 #define A_PCIE_CDEBUG_REG_0X2F 0x2f
14291 #define A_PCIE_CDEBUG_REG_0X30 0x30
14292 #define A_PCIE_CDEBUG_REG_0X31 0x31
14293 #define A_PCIE_CDEBUG_REG_0X32 0x32
14294 #define A_PCIE_CDEBUG_REG_0X33 0x33
14295 #define A_PCIE_CDEBUG_REG_0X34 0x34
14296 #define A_PCIE_CDEBUG_REG_0X35 0x35
14297 #define A_PCIE_CDEBUG_REG_0X36 0x36
14298 #define A_PCIE_CDEBUG_REG_0X37 0x37
14301 #define DBG_BASE_ADDR 0x6000
14303 #define A_DBG_DBG0_CFG 0x6000
14306 #define M_MODULESELECT    0xffU
14311 #define M_REGSELECT    0xffU
14315 #define S_CLKSELECT    0
14316 #define M_CLKSELECT    0xfU
14320 #define A_DBG_DBG0_EN 0x6004
14338 #define S_DBG_PORTEN    0
14342 #define A_DBG_DBG1_CFG 0x6008
14343 #define A_DBG_DBG1_EN 0x600c
14349 #define A_DBG_GPIO_EN 0x6010
14475 #define S_GPIO0_OUT_VAL    0
14479 #define A_DBG_GPIO_OUT 0x6010
14513 #define A_DBG_GPIO_IN 0x6014
14639 #define S_GPIO0_IN    0
14675 #define A_DBG_INT_ENABLE 0x6018
14777 #define S_GPIO0    0
14845 #define S_T7_C_LOCK    0
14849 #define A_DBG_INT_CAUSE 0x601c
14875 #define A_DBG_DBG0_RST_VALUE 0x6020
14877 #define S_DEBUGDATA    0
14878 #define M_DEBUGDATA    0xffffU
14882 #define A_DBG_OVERWRSERCFG_EN 0x6024
14884 #define S_OVERWRSERCFG_EN    0
14888 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
14910 #define S_C_OCLK_EN    0
14914 #define S_INIC_MODE_EN    0
14918 #define A_DBG_PLL_LOCK 0x602c
14940 #define S_PLL_C_LOCK    0
14976 #define A_DBG_GPIO_ACT_LOW 0x6030
15062 #define S_GPIO0_ACT_LOW    0
15082 #define A_DBG_PLL_LOCK_ACT_LOW 0x6030
15120 #define S_T7_C_LOCK_ACT_LOW    0
15124 #define A_DBG_EFUSE_BYTE0_3 0x6034
15125 #define A_DBG_EFUSE_BYTE4_7 0x6038
15126 #define A_DBG_EFUSE_BYTE8_11 0x603c
15127 #define A_DBG_EFUSE_BYTE12_15 0x6040
15128 #define A_DBG_STATIC_U_PLL_CONF 0x6044
15131 #define M_STATIC_U_PLL_MULT    0x1ffU
15136 #define M_STATIC_U_PLL_PREDIV    0x1fU
15141 #define M_STATIC_U_PLL_RANGEA    0xfU
15146 #define M_STATIC_U_PLL_RANGEB    0xfU
15150 #define S_STATIC_U_PLL_TUNE    0
15151 #define M_STATIC_U_PLL_TUNE    0x3ffU
15155 #define A_T7_DBG_STATIC_U_PLL_CONF1 0x6044
15158 #define M_STATIC_U_PLL_RANGE    0x7U
15163 #define M_STATIC_U_PLL_DIVQ    0x1fU
15168 #define M_STATIC_U_PLL_DIVFI    0x1ffU
15173 #define M_STATIC_U_PLL_DIVR    0x3fU
15181 #define A_DBG_STATIC_C_PLL_CONF 0x6048
15184 #define M_STATIC_C_PLL_MULT    0x1ffU
15189 #define M_STATIC_C_PLL_PREDIV    0x1fU
15194 #define M_STATIC_C_PLL_RANGEA    0xfU
15199 #define M_STATIC_C_PLL_RANGEB    0xfU
15203 #define S_STATIC_C_PLL_TUNE    0
15204 #define M_STATIC_C_PLL_TUNE    0x3ffU
15208 #define A_T7_DBG_STATIC_U_PLL_CONF2 0x6048
15211 #define M_STATIC_U_PLL_SSMF    0xfU
15216 #define M_STATIC_U_PLL_SSMD    0x7U
15224 #define S_STATIC_U_PLL_SSE    0
15228 #define A_DBG_STATIC_M_PLL_CONF 0x604c
15231 #define M_STATIC_M_PLL_MULT    0x1ffU
15236 #define M_STATIC_M_PLL_PREDIV    0x1fU
15241 #define M_STATIC_M_PLL_RANGEA    0xfU
15246 #define M_STATIC_M_PLL_RANGEB    0xfU
15250 #define S_STATIC_M_PLL_TUNE    0
15251 #define M_STATIC_M_PLL_TUNE    0x3ffU
15255 #define A_T7_DBG_STATIC_C_PLL_CONF1 0x604c
15258 #define M_STATIC_C_PLL_RANGE    0x7U
15263 #define M_STATIC_C_PLL_DIVQ    0x1fU
15268 #define M_STATIC_C_PLL_DIVFI    0x1ffU
15273 #define M_STATIC_C_PLL_DIVR    0x3fU
15281 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
15284 #define M_STATIC_KX_PLL_C    0xffU
15289 #define M_STATIC_KX_PLL_M    0x3fU
15294 #define M_STATIC_KX_PLL_N1    0xfU
15299 #define M_STATIC_KX_PLL_N2    0xfU
15304 #define M_STATIC_KX_PLL_N3    0xfU
15308 #define S_STATIC_KX_PLL_P    0
15309 #define M_STATIC_KX_PLL_P    0x7U
15313 #define A_T7_DBG_STATIC_C_PLL_CONF2 0x6050
15316 #define M_STATIC_C_PLL_SSMF    0xfU
15321 #define M_STATIC_C_PLL_SSMD    0x7U
15329 #define S_STATIC_C_PLL_SSE    0
15333 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
15336 #define M_STATIC_KR_PLL_C    0xffU
15341 #define M_STATIC_KR_PLL_M    0x3fU
15346 #define M_STATIC_KR_PLL_N1    0xfU
15351 #define M_STATIC_KR_PLL_N2    0xfU
15356 #define M_STATIC_KR_PLL_N3    0xfU
15360 #define S_STATIC_KR_PLL_P    0
15361 #define M_STATIC_KR_PLL_P    0x7U
15365 #define A_DBG_STATIC_PLL_DFS_CONF 0x6054
15376 #define M_STATIC_U_DFS_DIVFI    0x1ffU
15389 #define M_STATIC_C_DFS_DIVFI    0x1ffU
15397 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
15424 #define M_STATIC_LVDS_CLKOUT_SEL    0x3U
15433 #define M_STATIC_CCLK_FREQ_SEL    0x3U
15438 #define M_STATIC_UCLK_FREQ_SEL    0x3U
15447 #define M_EXPHYCLK_SEL    0x3U
15468 #define M_STATIC_KX_PLL_V    0xfU
15473 #define M_STATIC_KR_PLL_V    0xfU
15477 #define S_PSRO_SEL    0
15478 #define M_PSRO_SEL    0x7U
15490 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
15497 #define M_C_OCLK_MUXSEL    0x3U
15502 #define M_U_OCLK_MUXSEL    0x3U
15507 #define M_P_OCLK_MUXSEL    0x3U
15512 #define M_KX_OCLK_MUXSEL    0x7U
15516 #define S_KR_OCLK_MUXSEL    0
15517 #define M_KR_OCLK_MUXSEL    0x7U
15522 #define M_T5_P_OCLK_MUXSEL    0xfU
15527 #define M_T6_P_OCLK_MUXSEL    0xfU
15531 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
15532 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
15533 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
15534 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
15535 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
15536 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
15537 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
15538 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
15539 #define A_DBG_TRACE_COUNTER 0x6080
15542 #define M_COUNTER1    0xffffU
15546 #define S_COUNTER0    0
15547 #define M_COUNTER0    0xffffU
15551 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
15553 #define S_STATIC_REFCLK_PERIOD    0
15554 #define M_STATIC_REFCLK_PERIOD    0xffffU
15558 #define A_DBG_TRACE_CONF 0x6088
15580 #define S_DBG_OPERATE0_OR_1    0
15584 #define A_DBG_TRACE_RDEN 0x608c
15587 #define M_RD_ADDR1    0xffU
15592 #define M_RD_ADDR0    0xffU
15600 #define S_RD_EN0    0
15605 #define M_T5_RD_ADDR1    0x1ffU
15610 #define M_T5_RD_ADDR0    0x1ffU
15614 #define A_DBG_TRACE_WRADDR 0x6090
15617 #define M_WR_POINTER_ADDR1    0xffU
15621 #define S_WR_POINTER_ADDR0    0
15622 #define M_WR_POINTER_ADDR0    0xffU
15627 #define M_T5_WR_POINTER_ADDR1    0x1ffU
15631 #define S_T5_WR_POINTER_ADDR0    0
15632 #define M_T5_WR_POINTER_ADDR0    0x1ffU
15636 #define A_DBG_TRACE0_DATA_OUT 0x6094
15637 #define A_DBG_TRACE1_DATA_OUT 0x6098
15638 #define A_DBG_FUSE_SENSE_DONE 0x609c
15641 #define M_STATIC_JTAG_VERSIONNR    0xfU
15646 #define M_UNQ0    0xfU
15650 #define S_FUSE_DONE_SENSE    0
15654 #define A_DBG_TVSENSE_EN 0x60a8
15665 #define M_TVSENSE_SNSOUT    0x1ffU
15685 #define S_TVSENSE_RATIO    0
15686 #define M_TVSENSE_RATIO    0xffU
15702 #define A_DBG_PVT_EN1 0x60a8
15705 #define M_PVT_TRIMO    0x3fU
15710 #define M_PVT_TRIMG    0x1fU
15719 #define M_PVT_PSAMPLE    0x3U
15731 #define S_PVT_DIV    0
15732 #define M_PVT_DIV    0xffU
15736 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
15737 #define A_DBG_PVT_EN2 0x60ac
15740 #define M_PVT_DATA_OUT    0x3ffU
15744 #define S_PVT_DATA_VALID    0
15748 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
15749 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
15756 #define M_DBG_FEF    0x3fU
15777 #define M_DBG_FERSEL    0xffffU
15781 #define S_DBG_FETIME    0
15782 #define M_DBG_FETIME    0x7U
15786 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
15789 #define M_T5_STATIC_M_PLL_MULTFRAC    0xffffffU
15793 #define S_T5_STATIC_M_PLL_FFSLEWRATE    0
15794 #define M_T5_STATIC_M_PLL_FFSLEWRATE    0xffU
15798 #define A_DBG_STATIC_M_PLL_CONF1 0x60b8
15801 #define M_STATIC_M_PLL_MULTFRAC    0xffffffU
15805 #define S_STATIC_M_PLL_FFSLEWRATE    0
15806 #define M_STATIC_M_PLL_FFSLEWRATE    0xffU
15810 #define A_DBG_STATIC_M0_PLL_CONF1 0x60b8
15813 #define M_STATIC_M0_PLL_RANGE    0x7U
15818 #define M_STATIC_M0_PLL_DIVQ    0x1fU
15823 #define M_STATIC_M0_PLL_DIVFI    0x1ffU
15828 #define M_STATIC_M0_PLL_DIVR    0x3fU
15836 #define S_STATIC_M0_PLL_RESET    0
15840 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
15847 #define M_T5_STATIC_M_PLL_SDORDER    0x3U
15871 #define S_T5_STATIC_M_PLL_LOCKTUNE    0
15872 #define M_T5_STATIC_M_PLL_LOCKTUNE    0xffffU
15876 #define A_DBG_STATIC_M_PLL_CONF2 0x60bc
15879 #define M_T6_STATIC_M_PLL_PREDIV    0x3fU
15888 #define M_STATIC_M_PLL_SDORDER    0x3U
15912 #define S_STATIC_M_PLL_LOCKTUNE    0
15913 #define M_STATIC_M_PLL_LOCKTUNE    0x1fU
15917 #define A_DBG_STATIC_M0_PLL_CONF2 0x60bc
15944 #define M_STATIC_M0_PLL_SSMF    0xfU
15949 #define M_STATIC_M0_PLL_SSMD    0x7U
15957 #define S_STATIC_M0_PLL_SSE    0
15961 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
15964 #define M_T5_STATIC_M_PLL_MULTPRE    0x3U
15969 #define M_T5_STATIC_M_PLL_LOCKSEL    0x3U
15974 #define M_T5_STATIC_M_PLL_FFTUNE    0xffffU
15979 #define M_T5_STATIC_M_PLL_RANGEPRE    0x3U
15984 #define M_T5_STATIC_M_PLL_RANGEB    0x1fU
15988 #define S_T5_STATIC_M_PLL_RANGEA    0
15989 #define M_T5_STATIC_M_PLL_RANGEA    0x1fU
15993 #define A_DBG_STATIC_M_PLL_CONF3 0x60c0
15996 #define M_STATIC_M_PLL_MULTPRE    0x3U
16005 #define M_STATIC_M_PLL_FFTUNE    0xffffU
16010 #define M_STATIC_M_PLL_RANGEPRE    0x3U
16015 #define M_T6_STATIC_M_PLL_RANGEB    0x1fU
16019 #define S_T6_STATIC_M_PLL_RANGEA    0
16020 #define M_T6_STATIC_M_PLL_RANGEA    0x1fU
16024 #define A_DBG_STATIC_MAC_PLL_CONF1 0x60c0
16027 #define M_STATIC_MAC_PLL_RANGE    0x7U
16032 #define M_STATIC_MAC_PLL_DIVQ    0x1fU
16037 #define M_STATIC_MAC_PLL_DIVFI    0x1ffU
16042 #define M_STATIC_MAC_PLL_DIVR    0x3fU
16050 #define S_STATIC_MAC_PLL_RESET    0
16054 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
16055 #define A_DBG_STATIC_M_PLL_CONF4 0x60c4
16056 #define A_DBG_STATIC_MAC_PLL_CONF2 0x60c4
16059 #define M_STATIC_MAC_PLL_SSMF    0xfU
16064 #define M_STATIC_MAC_PLL_SSMD    0x7U
16072 #define S_STATIC_MAC_PLL_SSE    0
16076 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
16079 #define M_T5_STATIC_M_PLL_VCVTUNE    0x7U
16092 #define M_T5_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
16097 #define M_T5_STATIC_M_PLL_PREDIV    0x1fU
16101 #define S_T5_STATIC_M_PLL_MULT    0
16102 #define M_T5_STATIC_M_PLL_MULT    0xffU
16106 #define A_DBG_STATIC_M_PLL_CONF5 0x60c8
16109 #define M_STATIC_M_PLL_VCVTUNE    0x7U
16122 #define M_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
16126 #define S_T6_STATIC_M_PLL_MULT    0
16127 #define M_T6_STATIC_M_PLL_MULT    0xffU
16131 #define A_DBG_STATIC_ARM_PLL_CONF1 0x60c8
16134 #define M_STATIC_ARM_PLL_RANGE    0x7U
16139 #define M_STATIC_ARM_PLL_DIVQ    0x1fU
16144 #define M_STATIC_ARM_PLL_DIVFI    0x1ffU
16149 #define M_STATIC_ARM_PLL_DIVR    0x3fU
16157 #define S_STATIC_ARM_PLL_RESET    0
16161 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
16183 #define S_T5_STATIC_SWMC1CFGRST_    0
16187 #define A_DBG_STATIC_M_PLL_CONF6 0x60cc
16206 #define M_STATIC_M_PLL_STARTUP    0x3U
16211 #define M_STATIC_M_PLL_VREGTUNE    0x7ffffU
16235 #define S_STATIC_SWMC1CFGRST_    0
16239 #define A_DBG_STATIC_ARM_PLL_CONF2 0x60cc
16242 #define M_STATIC_ARM_PLL_SSMF    0xfU
16247 #define M_STATIC_ARM_PLL_SSMD    0x7U
16255 #define S_STATIC_ARM_PLL_SSE    0
16259 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
16262 #define M_T5_STATIC_C_PLL_MULTFRAC    0xffffffU
16266 #define S_T5_STATIC_C_PLL_FFSLEWRATE    0
16267 #define M_T5_STATIC_C_PLL_FFSLEWRATE    0xffU
16271 #define A_DBG_STATIC_C_PLL_CONF1 0x60d0
16274 #define M_STATIC_C_PLL_MULTFRAC    0xffffffU
16278 #define S_STATIC_C_PLL_FFSLEWRATE    0
16279 #define M_STATIC_C_PLL_FFSLEWRATE    0xffU
16283 #define A_DBG_STATIC_USB_PLL_CONF1 0x60d0
16286 #define M_STATIC_USB_PLL_RANGE    0x7U
16291 #define M_STATIC_USB_PLL_DIVQ    0x1fU
16296 #define M_STATIC_USB_PLL_DIVFI    0x1ffU
16301 #define M_STATIC_USB_PLL_DIVR    0x3fU
16309 #define S_STATIC_USB_PLL_RESET    0
16313 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
16320 #define M_T5_STATIC_C_PLL_SDORDER    0x3U
16344 #define S_T5_STATIC_C_PLL_LOCKTUNE    0
16345 #define M_T5_STATIC_C_PLL_LOCKTUNE    0xffffU
16349 #define A_DBG_STATIC_C_PLL_CONF2 0x60d4
16352 #define M_T6_STATIC_C_PLL_PREDIV    0x3fU
16357 #define M_STATIC_C_PLL_STARTUP    0x3U
16366 #define M_STATIC_C_PLL_SDORDER    0x3U
16390 #define S_STATIC_C_PLL_LOCKTUNE    0
16391 #define M_STATIC_C_PLL_LOCKTUNE    0x1fU
16395 #define A_DBG_STATIC_USB_PLL_CONF2 0x60d4
16398 #define M_STATIC_USB_PLL_SSMF    0xfU
16403 #define M_STATIC_USB_PLL_SSMD    0x7U
16411 #define S_STATIC_USB_PLL_SSE    0
16415 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
16418 #define M_T5_STATIC_C_PLL_MULTPRE    0x3U
16423 #define M_T5_STATIC_C_PLL_LOCKSEL    0x3U
16428 #define M_T5_STATIC_C_PLL_FFTUNE    0xffffU
16433 #define M_T5_STATIC_C_PLL_RANGEPRE    0x3U
16438 #define M_T5_STATIC_C_PLL_RANGEB    0x1fU
16442 #define S_T5_STATIC_C_PLL_RANGEA    0
16443 #define M_T5_STATIC_C_PLL_RANGEA    0x1fU
16447 #define A_DBG_STATIC_C_PLL_CONF3 0x60d8
16450 #define M_STATIC_C_PLL_MULTPRE    0x3U
16459 #define M_STATIC_C_PLL_FFTUNE    0xffffU
16464 #define M_STATIC_C_PLL_RANGEPRE    0x3U
16469 #define M_T6_STATIC_C_PLL_RANGEB    0x1fU
16473 #define S_T6_STATIC_C_PLL_RANGEA    0
16474 #define M_T6_STATIC_C_PLL_RANGEA    0x1fU
16478 #define A_DBG_STATIC_XGPHY_PLL_CONF1 0x60d8
16481 #define M_STATIC_XGPHY_PLL_RANGE    0x7U
16486 #define M_STATIC_XGPHY_PLL_DIVQ    0x1fU
16491 #define M_STATIC_XGPHY_PLL_DIVFI    0x1ffU
16496 #define M_STATIC_XGPHY_PLL_DIVR    0x3fU
16504 #define S_STATIC_XGPHY_PLL_RESET    0
16508 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
16509 #define A_DBG_STATIC_C_PLL_CONF4 0x60dc
16510 #define A_DBG_STATIC_XGPHY_PLL_CONF2 0x60dc
16513 #define M_STATIC_XGPHY_PLL_SSMF    0xfU
16518 #define M_STATIC_XGPHY_PLL_SSMD    0x7U
16526 #define S_STATIC_XGPHY_PLL_SSE    0
16530 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
16533 #define M_T5_STATIC_C_PLL_VCVTUNE    0x7U
16538 #define M_T5_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
16543 #define M_T5_STATIC_C_PLL_PREDIV    0x1fU
16547 #define S_T5_STATIC_C_PLL_MULT    0
16548 #define M_T5_STATIC_C_PLL_MULT    0xffU
16552 #define A_DBG_STATIC_C_PLL_CONF5 0x60e0
16567 #define M_STATIC_C_PLL_VCVTUNE    0x7U
16572 #define M_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
16577 #define M_STATIC_C_PLL_PREDIV_CNF5    0x1fU
16581 #define S_T6_STATIC_C_PLL_MULT    0
16582 #define M_T6_STATIC_C_PLL_MULT    0xffU
16586 #define A_DBG_STATIC_XGPBUS_PLL_CONF1 0x60e0
16593 #define M_STATIC_XGPBUS_PLL_RANGE    0x7U
16598 #define M_STATIC_XGPBUS_PLL_DIVQ    0x1fU
16603 #define M_STATIC_XGPBUS_PLL_DIVFI    0x1ffU
16608 #define M_STATIC_XGPBUS_PLL_DIVR    0x3fU
16616 #define S_STATIC_XGPBUS_PLL_RESET    0
16620 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
16623 #define M_T5_STATIC_U_PLL_MULTFRAC    0xffffffU
16627 #define S_T5_STATIC_U_PLL_FFSLEWRATE    0
16628 #define M_T5_STATIC_U_PLL_FFSLEWRATE    0xffU
16632 #define A_DBG_STATIC_U_PLL_CONF1 0x60e4
16635 #define M_STATIC_U_PLL_MULTFRAC    0xffffffU
16639 #define S_STATIC_U_PLL_FFSLEWRATE    0
16640 #define M_STATIC_U_PLL_FFSLEWRATE    0xffU
16644 #define A_DBG_STATIC_XGPBUS_PLL_CONF2 0x60e4
16647 #define M_STATIC_XGPBUS_PLL_SSMF    0xfU
16652 #define M_STATIC_XGPBUS_PLL_SSMD    0x7U
16660 #define S_STATIC_XGPBUS_PLL_SSE    0
16664 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
16671 #define M_T5_STATIC_U_PLL_SDORDER    0x3U
16695 #define S_T5_STATIC_U_PLL_LOCKTUNE    0
16696 #define M_T5_STATIC_U_PLL_LOCKTUNE    0xffffU
16700 #define A_DBG_STATIC_U_PLL_CONF2 0x60e8
16703 #define M_T6_STATIC_U_PLL_PREDIV    0x3fU
16708 #define M_STATIC_U_PLL_STARTUP    0x3U
16717 #define M_STATIC_U_PLL_SDORDER    0x3U
16741 #define S_STATIC_U_PLL_LOCKTUNE    0
16742 #define M_STATIC_U_PLL_LOCKTUNE    0x1fU
16746 #define A_DBG_STATIC_M1_PLL_CONF1 0x60e8
16749 #define M_STATIC_M1_PLL_RANGE    0x7U
16754 #define M_STATIC_M1_PLL_DIVQ    0x1fU
16759 #define M_STATIC_M1_PLL_DIVFI    0x1ffU
16764 #define M_STATIC_M1_PLL_DIVR    0x3fU
16772 #define S_STATIC_M1_PLL_RESET    0
16776 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
16779 #define M_T5_STATIC_U_PLL_MULTPRE    0x3U
16784 #define M_T5_STATIC_U_PLL_LOCKSEL    0x3U
16789 #define M_T5_STATIC_U_PLL_FFTUNE    0xffffU
16794 #define M_T5_STATIC_U_PLL_RANGEPRE    0x3U
16799 #define M_T5_STATIC_U_PLL_RANGEB    0x1fU
16803 #define S_T5_STATIC_U_PLL_RANGEA    0
16804 #define M_T5_STATIC_U_PLL_RANGEA    0x1fU
16808 #define A_DBG_STATIC_U_PLL_CONF3 0x60ec
16811 #define M_STATIC_U_PLL_MULTPRE    0x3U
16820 #define M_STATIC_U_PLL_FFTUNE    0xffffU
16825 #define M_STATIC_U_PLL_RANGEPRE    0x3U
16830 #define M_T6_STATIC_U_PLL_RANGEB    0x1fU
16834 #define S_T6_STATIC_U_PLL_RANGEA    0
16835 #define M_T6_STATIC_U_PLL_RANGEA    0x1fU
16839 #define A_DBG_STATIC_M1_PLL_CONF2 0x60ec
16842 #define M_STATIC_M1_PLL_SSMF    0xfU
16847 #define M_STATIC_M1_PLL_SSMD    0x7U
16855 #define S_STATIC_M1_PLL_SSE    0
16859 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
16860 #define A_DBG_STATIC_U_PLL_CONF4 0x60f0
16861 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
16864 #define M_T5_STATIC_U_PLL_VCVTUNE    0x7U
16869 #define M_T5_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
16874 #define M_T5_STATIC_U_PLL_PREDIV    0x1fU
16878 #define S_T5_STATIC_U_PLL_MULT    0
16879 #define M_T5_STATIC_U_PLL_MULT    0xffU
16883 #define A_DBG_STATIC_U_PLL_CONF5 0x60f4
16898 #define M_STATIC_U_PLL_VCVTUNE    0x7U
16903 #define M_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
16908 #define M_STATIC_U_PLL_PREDIV_CNF5    0x1fU
16912 #define S_T6_STATIC_U_PLL_MULT    0
16913 #define M_T6_STATIC_U_PLL_MULT    0xffU
16917 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
16924 #define M_T5_STATIC_KR_PLL_VBOOSTDIV    0x7U
16929 #define M_T5_STATIC_KR_PLL_CPISEL    0x7U
16954 #define M_T5_STATIC_KR_PLL_CCALBANDSEL    0xfU
16959 #define M_T5_STATIC_KR_PLL_BGOFFSET    0xfU
16964 #define M_T5_STATIC_KR_PLL_P    0x7U
16969 #define M_T5_STATIC_KR_PLL_N2    0xfU
16973 #define S_T5_STATIC_KR_PLL_N1    0
16974 #define M_T5_STATIC_KR_PLL_N1    0xfU
16978 #define A_DBG_STATIC_KR_PLL_CONF1 0x60f8
16985 #define M_STATIC_KR_PLL_VBOOSTDIV    0x7U
16990 #define M_STATIC_KR_PLL_CPISEL    0x7U
17015 #define M_STATIC_KR_PLL_CCALBANDSEL    0xfU
17020 #define M_STATIC_KR_PLL_BGOFFSET    0xfU
17025 #define M_T6_STATIC_KR_PLL_P    0x7U
17030 #define M_T6_STATIC_KR_PLL_N2    0xfU
17034 #define S_T6_STATIC_KR_PLL_N1    0
17035 #define M_T6_STATIC_KR_PLL_N1    0xfU
17039 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
17042 #define M_T5_STATIC_KR_PLL_M    0x1ffU
17046 #define S_T5_STATIC_KR_PLL_ANALOGTUNE    0
17047 #define M_T5_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
17051 #define A_DBG_STATIC_KR_PLL_CONF2 0x60fc
17054 #define M_T6_STATIC_KR_PLL_M    0x1ffU
17058 #define S_STATIC_KR_PLL_ANALOGTUNE    0
17059 #define M_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
17063 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
17069 #define S_RESET_CALIBRATE    0
17073 #define A_DBG_GPIO_EN_NEW 0x6100
17103 #define S_GPIO19_OUT_VAL    0
17107 #define A_DBG_GPIO_OEN 0x6100
17201 #define S_T7_GPIO0_OEN    0
17205 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
17219 #define A_DBG_GPIO_IN_NEW 0x6104
17249 #define S_GPIO16_IN    0
17253 #define A_DBG_GPIO_CHG_DET 0x6104
17347 #define S_T7_GPIO0_CHG_DET    0
17351 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
17354 #define M_LAST_MEASUREMENT_SELECT    0x3U
17359 #define M_LAST_MEASUREMENT_RESULT_BANK_B    0xfU
17363 #define S_LAST_MEASUREMENT_RESULT_BANK_A    0
17364 #define M_LAST_MEASUREMENT_RESULT_BANK_A    0xfU
17368 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
17375 #define M_T5_STATIC_KX_PLL_VBOOSTDIV    0x7U
17380 #define M_T5_STATIC_KX_PLL_CPISEL    0x7U
17405 #define M_T5_STATIC_KX_PLL_CCALBANDSEL    0xfU
17410 #define M_T5_STATIC_KX_PLL_BGOFFSET    0xfU
17415 #define M_T5_STATIC_KX_PLL_P    0x7U
17420 #define M_T5_STATIC_KX_PLL_N2    0xfU
17424 #define S_T5_STATIC_KX_PLL_N1    0
17425 #define M_T5_STATIC_KX_PLL_N1    0xfU
17429 #define A_DBG_STATIC_KX_PLL_CONF1 0x6108
17436 #define M_STATIC_KX_PLL_VBOOSTDIV    0x7U
17441 #define M_STATIC_KX_PLL_CPISEL    0x7U
17466 #define M_STATIC_KX_PLL_CCALBANDSEL    0xfU
17471 #define M_STATIC_KX_PLL_BGOFFSET    0xfU
17476 #define M_T6_STATIC_KX_PLL_P    0x7U
17481 #define M_T6_STATIC_KX_PLL_N2    0xfU
17485 #define S_T6_STATIC_KX_PLL_N1    0
17486 #define M_T6_STATIC_KX_PLL_N1    0xfU
17490 #define A_DBG_PVT_REG_DRVN 0x610c
17497 #define M_PVT_REG_DRVN_B    0xfU
17501 #define S_PVT_REG_DRVN_A    0
17502 #define M_PVT_REG_DRVN_A    0xfU
17506 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
17509 #define M_T5_STATIC_KX_PLL_M    0x1ffU
17513 #define S_T5_STATIC_KX_PLL_ANALOGTUNE    0
17514 #define M_T5_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
17518 #define A_DBG_STATIC_KX_PLL_CONF2 0x610c
17521 #define M_T6_STATIC_KX_PLL_M    0x1ffU
17525 #define S_STATIC_KX_PLL_ANALOGTUNE    0
17526 #define M_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
17530 #define A_DBG_PVT_REG_DRVP 0x6110
17537 #define M_PVT_REG_DRVP_B    0xfU
17541 #define S_PVT_REG_DRVP_A    0
17542 #define M_PVT_REG_DRVP_A    0xfU
17546 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
17549 #define M_STATIC_C_DFS_RANGEA    0x1fU
17554 #define M_STATIC_C_DFS_RANGEB    0x1fU
17566 #define S_STATIC_C_DFS_ENABLE    0
17570 #define A_DBG_STATIC_C_DFS_CONF 0x6110
17571 #define A_DBG_PVT_REG_TERMN 0x6114
17578 #define M_PVT_REG_TERMN_B    0xfU
17582 #define S_PVT_REG_TERMN_A    0
17583 #define M_PVT_REG_TERMN_A    0xfU
17587 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
17590 #define M_STATIC_U_DFS_RANGEA    0x1fU
17595 #define M_STATIC_U_DFS_RANGEB    0x1fU
17607 #define S_STATIC_U_DFS_ENABLE    0
17611 #define A_DBG_STATIC_U_DFS_CONF 0x6114
17612 #define A_DBG_PVT_REG_TERMP 0x6118
17619 #define M_PVT_REG_TERMP_B    0xfU
17623 #define S_PVT_REG_TERMP_A    0
17624 #define M_PVT_REG_TERMP_A    0xfU
17628 #define A_DBG_GPIO_PE_EN 0x6118
17706 #define S_GPIO0_PE_EN    0
17726 #define A_DBG_PVT_REG_THRESHOLD 0x611c
17760 #define S_THRESHOLD_DRVN_MIN_SYNC    0
17764 #define A_DBG_GPIO_PS_EN 0x611c
17842 #define S_GPIO0_PS_EN    0
17862 #define A_DBG_PVT_REG_IN_TERMP 0x6120
17865 #define M_REG_IN_TERMP_B    0xfU
17869 #define S_REG_IN_TERMP_A    0
17870 #define M_REG_IN_TERMP_A    0xfU
17874 #define A_DBG_EFUSE_BYTE16_19 0x6120
17875 #define A_DBG_PVT_REG_IN_TERMN 0x6124
17878 #define M_REG_IN_TERMN_B    0xfU
17882 #define S_REG_IN_TERMN_A    0
17883 #define M_REG_IN_TERMN_A    0xfU
17887 #define A_DBG_EFUSE_BYTE20_23 0x6124
17888 #define A_DBG_PVT_REG_IN_DRVP 0x6128
17891 #define M_REG_IN_DRVP_B    0xfU
17895 #define S_REG_IN_DRVP_A    0
17896 #define M_REG_IN_DRVP_A    0xfU
17900 #define A_DBG_EFUSE_BYTE24_27 0x6128
17901 #define A_DBG_PVT_REG_IN_DRVN 0x612c
17904 #define M_REG_IN_DRVN_B    0xfU
17908 #define S_REG_IN_DRVN_A    0
17909 #define M_REG_IN_DRVN_A    0xfU
17913 #define A_DBG_EFUSE_BYTE28_31 0x612c
17914 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
17917 #define M_REG_OUT_TERMP_B    0xfU
17921 #define S_REG_OUT_TERMP_A    0
17922 #define M_REG_OUT_TERMP_A    0xfU
17926 #define A_DBG_EFUSE_BYTE32_35 0x6130
17927 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
17930 #define M_REG_OUT_TERMN_B    0xfU
17934 #define S_REG_OUT_TERMN_A    0
17935 #define M_REG_OUT_TERMN_A    0xfU
17939 #define A_DBG_EFUSE_BYTE36_39 0x6134
17940 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
17943 #define M_REG_OUT_DRVP_B    0xfU
17947 #define S_REG_OUT_DRVP_A    0
17948 #define M_REG_OUT_DRVP_A    0xfU
17952 #define A_DBG_EFUSE_BYTE40_43 0x6138
17953 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
17956 #define M_REG_OUT_DRVN_B    0xfU
17960 #define S_REG_OUT_DRVN_A    0
17961 #define M_REG_OUT_DRVN_A    0xfU
17965 #define A_DBG_EFUSE_BYTE44_47 0x613c
17966 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
17969 #define M_TERMP_B_HISTORY    0xfU
17973 #define S_TERMP_A_HISTORY    0
17974 #define M_TERMP_A_HISTORY    0xfU
17978 #define A_DBG_EFUSE_BYTE48_51 0x6140
17979 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
17982 #define M_TERMN_B_HISTORY    0xfU
17986 #define S_TERMN_A_HISTORY    0
17987 #define M_TERMN_A_HISTORY    0xfU
17991 #define A_DBG_EFUSE_BYTE52_55 0x6144
17992 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
17995 #define M_DRVP_B_HISTORY    0xfU
17999 #define S_DRVP_A_HISTORY    0
18000 #define M_DRVP_A_HISTORY    0xfU
18004 #define A_DBG_EFUSE_BYTE56_59 0x6148
18005 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
18008 #define M_DRVN_B_HISTORY    0xfU
18012 #define S_DRVN_A_HISTORY    0
18013 #define M_DRVN_A_HISTORY    0xfU
18017 #define A_DBG_EFUSE_BYTE60_63 0x614c
18018 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
18020 #define S_SAMPLE_WAIT_CLKS    0
18021 #define M_SAMPLE_WAIT_CLKS    0x1fU
18025 #define A_DBG_STATIC_U_PLL_CONF6 0x6150
18027 #define S_STATIC_U_PLL_VREGTUNE    0
18028 #define M_STATIC_U_PLL_VREGTUNE    0x7ffffU
18032 #define A_DBG_STATIC_PLL_LOCK_WAIT_CONF 0x6150
18038 #define S_STATIC_LOCK_WAIT_TIME    0
18039 #define M_STATIC_LOCK_WAIT_TIME    0xffffffU
18043 #define A_DBG_STATIC_C_PLL_CONF6 0x6154
18045 #define S_STATIC_C_PLL_VREGTUNE    0
18046 #define M_STATIC_C_PLL_VREGTUNE    0x7ffffU
18050 #define A_DBG_CUST_EFUSE_PROGRAM 0x6158
18053 #define M_EFUSE_PROG_PERIOD    0xffffU
18058 #define M_EFUSE_OPER_TYP    0x3U
18063 #define M_EFUSE_ADDR    0x3fU
18067 #define S_EFUSE_DIN    0
18068 #define M_EFUSE_DIN    0xffU
18072 #define A_DBG_CUST_EFUSE_OUT 0x615c
18078 #define S_EFUSE_DOUT    0
18079 #define M_EFUSE_DOUT    0xffU
18083 #define A_DBG_CUST_EFUSE_BYTE0_3 0x6160
18084 #define A_DBG_CUST_EFUSE_BYTE4_7 0x6164
18085 #define A_DBG_CUST_EFUSE_BYTE8_11 0x6168
18086 #define A_DBG_CUST_EFUSE_BYTE12_15 0x616c
18087 #define A_DBG_CUST_EFUSE_BYTE16_19 0x6170
18088 #define A_DBG_CUST_EFUSE_BYTE20_23 0x6174
18089 #define A_DBG_CUST_EFUSE_BYTE24_27 0x6178
18090 #define A_DBG_CUST_EFUSE_BYTE28_31 0x617c
18091 #define A_DBG_CUST_EFUSE_BYTE32_35 0x6180
18092 #define A_DBG_GPIO_INT_ENABLE 0x6180
18126 #define A_DBG_CUST_EFUSE_BYTE36_39 0x6184
18127 #define A_DBG_GPIO_INT_CAUSE 0x6184
18128 #define A_DBG_CUST_EFUSE_BYTE40_43 0x6188
18129 #define A_T7_DBG_GPIO_ACT_LOW 0x6188
18163 #define A_DBG_CUST_EFUSE_BYTE44_47 0x618c
18164 #define A_DBG_DDR_CAL 0x618c
18202 #define S_CAL_RES    0
18206 #define A_DBG_CUST_EFUSE_BYTE48_51 0x6190
18207 #define A_DBG_EFUSE_CTL_0 0x6190
18250 #define M_EFUSE_AT    0x3U
18255 #define M_EFUSE_RD_STATE    0xfU
18264 #define M_EFUSE_WR_RD    0x3U
18268 #define S_EFUSE_A    0
18269 #define M_EFUSE_A    0x7ffU
18273 #define A_DBG_CUST_EFUSE_BYTE52_55 0x6194
18274 #define A_DBG_EFUSE_CTL_1 0x6194
18275 #define A_DBG_CUST_EFUSE_BYTE56_59 0x6198
18276 #define A_DBG_EFUSE_RD_CTL 0x6198
18279 #define M_EFUSE_RD_ID    0x3U
18283 #define S_EFUSE_RD_ADDR    0
18284 #define M_EFUSE_RD_ADDR    0x3fU
18288 #define A_DBG_CUST_EFUSE_BYTE60_63 0x619c
18289 #define A_DBG_EFUSE_RD_DATA 0x619c
18290 #define A_DBG_EFUSE_TIME_0 0x61a0
18293 #define M_EFUSE_TIME_1    0xffffU
18297 #define S_EFUSE_TIME_0    0
18298 #define M_EFUSE_TIME_0    0xffffU
18302 #define A_DBG_EFUSE_TIME_1 0x61a4
18305 #define M_EFUSE_TIME_3    0xffffU
18309 #define S_EFUSE_TIME_2    0
18310 #define M_EFUSE_TIME_2    0xffffU
18314 #define A_DBG_EFUSE_TIME_2 0x61a8
18317 #define M_EFUSE_TIME_5    0xffffU
18321 #define S_EFUSE_TIME_4    0
18322 #define M_EFUSE_TIME_4    0xffffU
18326 #define A_DBG_EFUSE_TIME_3 0x61ac
18329 #define M_EFUSE_TIME_7    0xffffU
18333 #define S_EFUSE_TIME_6    0
18334 #define M_EFUSE_TIME_6    0xffffU
18338 #define A_DBG_VREF_CTL 0x61b0
18345 #define M_VREF_R_1    0x7fU
18353 #define S_VREF_R_0    0
18354 #define M_VREF_R_0    0x7fU
18358 #define A_DBG_FPGA_EFUSE_CTL 0x61b4
18359 #define A_DBG_FPGA_EFUSE_DATA 0x61b8
18362 #define MC_BASE_ADDR 0x6200
18364 #define A_MC_PCTL_SCFG 0x6200
18382 #define S_HW_LOW_POWER_EN    0
18386 #define A_MC_PCTL_SCTL 0x6204
18388 #define S_STATE_CMD    0
18389 #define M_STATE_CMD    0x7U
18393 #define A_MC_PCTL_STAT 0x6208
18395 #define S_CTL_STAT    0
18396 #define M_CTL_STAT    0x7U
18400 #define A_MC_PCTL_MCMD 0x6240
18407 #define M_CMD_ADD_DEL    0xfU
18412 #define M_RANK_SEL    0xfU
18417 #define M_BANK_ADDR    0x7U
18422 #define M_CMD_ADDR    0x1fffU
18426 #define S_CMD_OPCODE    0
18427 #define M_CMD_OPCODE    0x7U
18431 #define A_MC_PCTL_POWCTL 0x6244
18433 #define S_POWER_UP_START    0
18437 #define A_MC_PCTL_POWSTAT 0x6248
18443 #define S_POWER_UP_DONE    0
18447 #define A_MC_PCTL_MCFG 0x6280
18450 #define M_TFAW_CFG    0x3U
18463 #define M_PD_IDLE    0xffU
18468 #define M_PAGE_POLICY    0x3U
18484 #define S_MEM_BL    0
18488 #define A_MC_PCTL_PPCFG 0x6284
18491 #define M_RPMEM_DIS    0xffU
18495 #define S_PPMEM_EN    0
18499 #define A_MC_PCTL_MSTAT 0x6288
18501 #define S_POWER_DOWN    0
18505 #define A_MC_PCTL_ODTCFG 0x628c
18583 #define S_RANK0_ODT_READ_NSEL    0
18587 #define A_MC_PCTL_DQSECFG 0x6290
18590 #define M_DV_ALAT    0xfU
18595 #define M_DV_ALEN    0x3U
18600 #define M_DSE_ALAT    0xfU
18605 #define M_DSE_ALEN    0x3U
18610 #define M_QSE_ALAT    0xfU
18614 #define S_QSE_ALEN    0
18615 #define M_QSE_ALEN    0x3U
18619 #define A_MC_PCTL_DTUPDES 0x6294
18626 #define M_DTU_EAFFL    0xfU
18662 #define S_DTU_ERR_B0    0
18666 #define A_MC_PCTL_DTUNA 0x6298
18667 #define A_MC_PCTL_DTUNE 0x629c
18668 #define A_MC_PCTL_DTUPRDO 0x62a0
18671 #define M_DTU_ALLBITS_1    0xffffU
18675 #define S_DTU_ALLBITS_0    0
18676 #define M_DTU_ALLBITS_0    0xffffU
18680 #define A_MC_PCTL_DTUPRD1 0x62a4
18683 #define M_DTU_ALLBITS_3    0xffffU
18687 #define S_DTU_ALLBITS_2    0
18688 #define M_DTU_ALLBITS_2    0xffffU
18692 #define A_MC_PCTL_DTUPRD2 0x62a8
18695 #define M_DTU_ALLBITS_5    0xffffU
18699 #define S_DTU_ALLBITS_4    0
18700 #define M_DTU_ALLBITS_4    0xffffU
18704 #define A_MC_PCTL_DTUPRD3 0x62ac
18707 #define M_DTU_ALLBITS_7    0xffffU
18711 #define S_DTU_ALLBITS_6    0
18712 #define M_DTU_ALLBITS_6    0xffffU
18716 #define A_MC_PCTL_DTUAWDT 0x62b0
18719 #define M_NUMBER_RANKS    0x3U
18724 #define M_ROW_ADDR_WIDTH    0x3U
18729 #define M_BANK_ADDR_WIDTH    0x3U
18733 #define S_COLUMN_ADDR_WIDTH    0
18734 #define M_COLUMN_ADDR_WIDTH    0x3U
18738 #define A_MC_PCTL_TOGCNT1U 0x62c0
18740 #define S_TOGGLE_COUNTER_1U    0
18741 #define M_TOGGLE_COUNTER_1U    0x3ffU
18745 #define A_MC_PCTL_TINIT 0x62c4
18747 #define S_T_INIT    0
18748 #define M_T_INIT    0x1ffU
18752 #define A_MC_PCTL_TRSTH 0x62c8
18754 #define S_T_RSTH    0
18755 #define M_T_RSTH    0x3ffU
18759 #define A_MC_PCTL_TOGCNT100N 0x62cc
18761 #define S_TOGGLE_COUNTER_100N    0
18762 #define M_TOGGLE_COUNTER_100N    0x7fU
18766 #define A_MC_PCTL_TREFI 0x62d0
18768 #define S_T_REFI    0
18769 #define M_T_REFI    0xffU
18773 #define A_MC_PCTL_TMRD 0x62d4
18775 #define S_T_MRD    0
18776 #define M_T_MRD    0x7U
18780 #define A_MC_PCTL_TRFC 0x62d8
18782 #define S_T_RFC    0
18783 #define M_T_RFC    0xffU
18787 #define A_MC_PCTL_TRP 0x62dc
18789 #define S_T_RP    0
18790 #define M_T_RP    0xfU
18794 #define A_MC_PCTL_TRTW 0x62e0
18796 #define S_T_RTW    0
18797 #define M_T_RTW    0x7U
18801 #define A_MC_PCTL_TAL 0x62e4
18803 #define S_T_AL    0
18804 #define M_T_AL    0xfU
18808 #define A_MC_PCTL_TCL 0x62e8
18810 #define S_T_CL    0
18811 #define M_T_CL    0xfU
18815 #define A_MC_PCTL_TCWL 0x62ec
18817 #define S_T_CWL    0
18818 #define M_T_CWL    0xfU
18822 #define A_MC_PCTL_TRAS 0x62f0
18824 #define S_T_RAS    0
18825 #define M_T_RAS    0x3fU
18829 #define A_MC_PCTL_TRC 0x62f4
18831 #define S_T_RC    0
18832 #define M_T_RC    0x3fU
18836 #define A_MC_PCTL_TRCD 0x62f8
18838 #define S_T_RCD    0
18839 #define M_T_RCD    0xfU
18843 #define A_MC_PCTL_TRRD 0x62fc
18845 #define S_T_RRD    0
18846 #define M_T_RRD    0xfU
18850 #define A_MC_PCTL_TRTP 0x6300
18852 #define S_T_RTP    0
18853 #define M_T_RTP    0x7U
18857 #define A_MC_PCTL_TWR 0x6304
18859 #define S_T_WR    0
18860 #define M_T_WR    0x7U
18864 #define A_MC_PCTL_TWTR 0x6308
18866 #define S_T_WTR    0
18867 #define M_T_WTR    0x7U
18871 #define A_MC_PCTL_TEXSR 0x630c
18873 #define S_T_EXSR    0
18874 #define M_T_EXSR    0x3ffU
18878 #define A_MC_PCTL_TXP 0x6310
18880 #define S_T_XP    0
18881 #define M_T_XP    0x7U
18885 #define A_MC_PCTL_TXPDLL 0x6314
18887 #define S_T_XPDLL    0
18888 #define M_T_XPDLL    0x3fU
18892 #define A_MC_PCTL_TZQCS 0x6318
18894 #define S_T_ZQCS    0
18895 #define M_T_ZQCS    0x7fU
18899 #define A_MC_PCTL_TZQCSI 0x631c
18901 #define S_T_ZQCSI    0
18902 #define M_T_ZQCSI    0xfffU
18906 #define A_MC_PCTL_TDQS 0x6320
18908 #define S_T_DQS    0
18909 #define M_T_DQS    0x7U
18913 #define A_MC_PCTL_TCKSRE 0x6324
18915 #define S_T_CKSRE    0
18916 #define M_T_CKSRE    0xfU
18920 #define A_MC_PCTL_TCKSRX 0x6328
18922 #define S_T_CKSRX    0
18923 #define M_T_CKSRX    0xfU
18927 #define A_MC_PCTL_TCKE 0x632c
18929 #define S_T_CKE    0
18930 #define M_T_CKE    0x7U
18934 #define A_MC_PCTL_TMOD 0x6330
18936 #define S_T_MOD    0
18937 #define M_T_MOD    0xfU
18941 #define A_MC_PCTL_TRSTL 0x6334
18943 #define S_RSTHOLD    0
18944 #define M_RSTHOLD    0x7fU
18948 #define A_MC_PCTL_TZQCL 0x6338
18950 #define S_T_ZQCL    0
18951 #define M_T_ZQCL    0x3ffU
18955 #define A_MC_PCTL_DWLCFG0 0x6370
18957 #define S_T_ADWL_VEC    0
18958 #define M_T_ADWL_VEC    0x1ffU
18962 #define A_MC_PCTL_DWLCFG1 0x6374
18963 #define A_MC_PCTL_DWLCFG2 0x6378
18964 #define A_MC_PCTL_DWLCFG3 0x637c
18965 #define A_MC_PCTL_ECCCFG 0x6380
18979 #define A_MC_PCTL_ECCTST 0x6384
18981 #define S_ECC_TEST_MASK    0
18982 #define M_ECC_TEST_MASK    0xffU
18986 #define A_MC_PCTL_ECCCLR 0x6388
18992 #define S_CLR_ECC_INTR    0
18996 #define A_MC_PCTL_ECCLOG 0x638c
18997 #define A_MC_PCTL_DTUWACTL 0x6400
19000 #define M_DTU_WR_RANK    0x3U
19005 #define M_DTU_WR_ROW    0x1ffffU
19010 #define M_DTU_WR_BANK    0x7U
19014 #define S_DTU_WR_COL    0
19015 #define M_DTU_WR_COL    0x3ffU
19019 #define A_MC_PCTL_DTURACTL 0x6404
19022 #define M_DTU_RD_RANK    0x3U
19027 #define M_DTU_RD_ROW    0x1ffffU
19032 #define M_DTU_RD_BANK    0x7U
19036 #define S_DTU_RD_COL    0
19037 #define M_DTU_RD_COL    0x3ffU
19041 #define A_MC_PCTL_DTUCFG 0x6408
19044 #define M_DTU_ROW_INCREMENTS    0x7fU
19057 #define M_DTU_TARGET_LANE    0xfU
19074 #define M_DTU_NALEN    0x3fU
19078 #define S_DTU_ENABLE    0
19082 #define A_MC_PCTL_DTUECTL 0x640c
19092 #define S_RUN_DTU    0
19096 #define A_MC_PCTL_DTUWD0 0x6410
19099 #define M_DTU_WR_BYTE3    0xffU
19104 #define M_DTU_WR_BYTE2    0xffU
19109 #define M_DTU_WR_BYTE1    0xffU
19113 #define S_DTU_WR_BYTE0    0
19114 #define M_DTU_WR_BYTE0    0xffU
19118 #define A_MC_PCTL_DTUWD1 0x6414
19121 #define M_DTU_WR_BYTE7    0xffU
19126 #define M_DTU_WR_BYTE6    0xffU
19131 #define M_DTU_WR_BYTE5    0xffU
19135 #define S_DTU_WR_BYTE4    0
19136 #define M_DTU_WR_BYTE4    0xffU
19140 #define A_MC_PCTL_DTUWD2 0x6418
19143 #define M_DTU_WR_BYTE11    0xffU
19148 #define M_DTU_WR_BYTE10    0xffU
19153 #define M_DTU_WR_BYTE9    0xffU
19157 #define S_DTU_WR_BYTE8    0
19158 #define M_DTU_WR_BYTE8    0xffU
19162 #define A_MC_PCTL_DTUWD3 0x641c
19165 #define M_DTU_WR_BYTE15    0xffU
19170 #define M_DTU_WR_BYTE14    0xffU
19175 #define M_DTU_WR_BYTE13    0xffU
19179 #define S_DTU_WR_BYTE12    0
19180 #define M_DTU_WR_BYTE12    0xffU
19184 #define A_MC_PCTL_DTUWDM 0x6420
19186 #define S_DM_WR_BYTE0    0
19187 #define M_DM_WR_BYTE0    0xffffU
19191 #define A_MC_PCTL_DTURD0 0x6424
19194 #define M_DTU_RD_BYTE3    0xffU
19199 #define M_DTU_RD_BYTE2    0xffU
19204 #define M_DTU_RD_BYTE1    0xffU
19208 #define S_DTU_RD_BYTE0    0
19209 #define M_DTU_RD_BYTE0    0xffU
19213 #define A_MC_PCTL_DTURD1 0x6428
19216 #define M_DTU_RD_BYTE7    0xffU
19221 #define M_DTU_RD_BYTE6    0xffU
19226 #define M_DTU_RD_BYTE5    0xffU
19230 #define S_DTU_RD_BYTE4    0
19231 #define M_DTU_RD_BYTE4    0xffU
19235 #define A_MC_PCTL_DTURD2 0x642c
19238 #define M_DTU_RD_BYTE11    0xffU
19243 #define M_DTU_RD_BYTE10    0xffU
19248 #define M_DTU_RD_BYTE9    0xffU
19252 #define S_DTU_RD_BYTE8    0
19253 #define M_DTU_RD_BYTE8    0xffU
19257 #define A_MC_PCTL_DTURD3 0x6430
19260 #define M_DTU_RD_BYTE15    0xffU
19265 #define M_DTU_RD_BYTE14    0xffU
19270 #define M_DTU_RD_BYTE13    0xffU
19274 #define S_DTU_RD_BYTE12    0
19275 #define M_DTU_RD_BYTE12    0xffU
19279 #define A_MC_DTULFSRWD 0x6434
19280 #define A_MC_PCTL_DTULFSRRD 0x6438
19281 #define A_MC_PCTL_DTUEAF 0x643c
19284 #define M_EA_RANK    0x3U
19289 #define M_EA_ROW    0x1ffffU
19294 #define M_EA_BANK    0x7U
19298 #define S_EA_COLUMN    0
19299 #define M_EA_COLUMN    0x3ffU
19303 #define A_MC_PCTL_PHYPVTCFG 0x6500
19322 #define M_PVT_UPD_DONE_TYPE    0x3U
19342 #define S_PHY_UPD_DONE_TYPE    0
19343 #define M_PHY_UPD_DONE_TYPE    0x3U
19347 #define A_MC_PCTL_PHYPVTSTAT 0x6504
19361 #define S_I_PHY_UPD_DONE    0
19365 #define A_MC_PCTL_PHYTUPDON 0x6508
19367 #define S_PHY_T_UPDON    0
19368 #define M_PHY_T_UPDON    0xffU
19372 #define A_MC_PCTL_PHYTUPDDLY 0x650c
19374 #define S_PHY_T_UPDDLY    0
19375 #define M_PHY_T_UPDDLY    0xfU
19379 #define A_MC_PCTL_PVTTUPON 0x6510
19381 #define S_PVT_T_UPDON    0
19382 #define M_PVT_T_UPDON    0xffU
19386 #define A_MC_PCTL_PVTTUPDDLY 0x6514
19388 #define S_PVT_T_UPDDLY    0
19389 #define M_PVT_T_UPDDLY    0xfU
19393 #define A_MC_PCTL_PHYPVTUPDI 0x6518
19395 #define S_PHYPVT_T_UPDI    0
19396 #define M_PHYPVT_T_UPDI    0xffU
19400 #define A_MC_PCTL_PHYIOCRV1 0x651c
19403 #define M_BYTE_OE_CTL    0x3U
19408 #define M_DYN_SOC_ODT_ALAT    0xfU
19413 #define M_DYN_SOC_ODT_ATEN    0x3U
19421 #define S_SOC_ODT_EN    0
19425 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
19427 #define S_PHY_T_UPDWAIT    0
19428 #define M_PHY_T_UPDWAIT    0x3fU
19432 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
19434 #define S_PVT_T_UPDWAIT    0
19435 #define M_PVT_T_UPDWAIT    0x3fU
19439 #define A_MC_DDR3PHYAC_GCR 0x6a00
19442 #define M_WLRANK    0x3U
19447 #define M_FDEPTH    0x3U
19452 #define M_LPFDEPTH    0x3U
19468 #define S_MDLEN    0
19472 #define A_MC_DDR3PHYAC_RCR0 0x6a04
19506 #define S_CKOEN    0
19510 #define A_MC_DDR3PHYAC_ACCR 0x6a14
19544 #define S_CK4OEN    0
19548 #define A_MC_DDR3PHYAC_GSR 0x6a18
19558 #define S_ACCAL    0
19562 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
19568 #define S_WLINC    0
19572 #define A_MC_DDR3PHYAC_OCSR 0x6a20
19573 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
19575 #define S_PRD    0
19576 #define M_PRD    0x3ffU
19580 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
19581 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
19582 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
19583 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
19585 #define S_DFLTDLY    0
19586 #define M_DFLTDLY    0x7fU
19590 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
19591 #define A_MC_DDR3PHYAC_ACR 0x6a60
19598 #define M_ISEL    0x3U
19610 #define S_CKINV    0
19614 #define A_MC_DDR3PHYAC_PSCR 0x6a64
19616 #define S_PSCALE    0
19617 #define M_PSCALE    0x3ffU
19621 #define A_MC_DDR3PHYAC_PRCR 0x6a68
19632 #define M_RSTCLKS    0xfU
19644 #define S_PHYRST    0
19648 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
19651 #define M_RSTCXKS    0x1fU
19659 #define S_TESTA    0
19660 #define M_TESTA    0x7U
19664 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
19671 #define M_BDIV    0x3U
19675 #define S_TESTD    0
19676 #define M_TESTD    0x7U
19680 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
19683 #define M_CKCLKEN    0x3fU
19695 #define S_DDRCLKEN    0
19699 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
19725 #define S_WLSDVT    0
19729 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
19731 #define S_WDSDR_DLY    0
19732 #define M_WDSDR_DLY    0x3ffU
19736 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
19737 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
19739 #define S_WL_DLY    0
19740 #define M_WL_DLY    0x3ffU
19744 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
19746 #define S_DLY    0
19747 #define M_DLY    0x7fU
19751 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
19752 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
19753 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
19754 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
19755 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
19756 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
19757 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
19758 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
19759 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
19761 #define S_MAXDLY    0
19762 #define M_MAXDLY    0x7fU
19766 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
19768 #define S_RDSDR_DLY    0
19769 #define M_RDSDR_DLY    0x3ffU
19773 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
19774 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
19775 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
19776 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
19777 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
19778 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
19779 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
19780 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
19781 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
19782 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
19783 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
19784 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
19785 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
19786 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
19788 #define S_DP_DLY    0
19789 #define M_DP_DLY    0x1ffU
19793 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
19794 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
19808 #define S_RDQSCAL    0
19812 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
19830 #define S_DSINV    0
19834 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
19840 #define S_RANK    0
19841 #define M_RANK    0x3U
19845 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
19848 #define M_DTOSEL    0x3U
19852 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
19853 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
19854 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
19855 #define A_MC_PVT_REG_DRVN 0x740c
19856 #define A_MC_PVT_REG_DRVP 0x7410
19857 #define A_MC_PVT_REG_TERMN 0x7414
19858 #define A_MC_PVT_REG_TERMP 0x7418
19859 #define A_MC_PVT_REG_THRESHOLD 0x741c
19860 #define A_MC_PVT_REG_IN_TERMP 0x7420
19861 #define A_MC_PVT_REG_IN_TERMN 0x7424
19862 #define A_MC_PVT_REG_IN_DRVP 0x7428
19863 #define A_MC_PVT_REG_IN_DRVN 0x742c
19864 #define A_MC_PVT_REG_OUT_TERMP 0x7430
19865 #define A_MC_PVT_REG_OUT_TERMN 0x7434
19866 #define A_MC_PVT_REG_OUT_DRVP 0x7438
19867 #define A_MC_PVT_REG_OUT_DRVN 0x743c
19868 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
19869 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
19870 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
19871 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
19872 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
19873 #define A_MC_DDRPHY_RST_CTRL 0x7500
19879 #define S_PHY_RST_N    0
19883 #define A_MC_PERFORMANCE_CTRL 0x7504
19893 #define S_RMW_PERF_CTRL    0
19897 #define A_MC_ECC_CTRL 0x7508
19903 #define S_ECC_DISABLE    0
19907 #define A_MC_PAR_ENABLE 0x750c
19921 #define S_PERR_BLK_INT_ENABLE    0
19925 #define A_MC_PAR_CAUSE 0x7510
19939 #define S_RDATA_FIFOR_PAR_CAUSE    0
19943 #define A_MC_INT_ENABLE 0x7514
19953 #define S_PERR_INT_ENABLE    0
19957 #define A_MC_INT_CAUSE 0x7518
19967 #define S_PERR_INT_CAUSE    0
19971 #define A_MC_ECC_STATUS 0x751c
19974 #define M_ECC_CECNT    0xffffU
19978 #define S_ECC_UECNT    0
19979 #define M_ECC_UECNT    0xffffU
19983 #define A_MC_PHY_CTRL 0x7520
19985 #define S_CTLPHYRR    0
19989 #define A_MC_STATIC_CFG_STATUS 0x7524
19996 #define M_STATIC_DEN    0x7U
20009 #define M_STATIC_WIDTH    0x7U
20013 #define S_STATIC_SLOW    0
20017 #define A_MC_CORE_PCTL_STAT 0x7528
20019 #define S_PCTL_ACCESS_STAT    0
20020 #define M_PCTL_ACCESS_STAT    0x7U
20024 #define A_MC_DEBUG_CNT 0x752c
20027 #define M_WDATA_OCNT    0x1fU
20031 #define S_RDATA_OCNT    0
20032 #define M_RDATA_OCNT    0x1fU
20036 #define A_MC_BONUS 0x7530
20037 #define A_MC_BIST_CMD 0x7600
20044 #define M_BIST_CMD_GAP    0xffU
20048 #define S_BIST_OPCODE    0
20049 #define M_BIST_OPCODE    0x3U
20053 #define A_MC_BIST_CMD_ADDR 0x7604
20054 #define A_MC_BIST_CMD_LEN 0x7608
20055 #define A_MC_BIST_DATA_PATTERN 0x760c
20057 #define S_BIST_DATA_TYPE    0
20058 #define M_BIST_DATA_TYPE    0xfU
20062 #define A_MC_BIST_USER_WDATA0 0x7614
20063 #define A_MC_BIST_USER_WDATA1 0x7618
20064 #define A_MC_BIST_USER_WDATA2 0x761c
20066 #define S_USER_DATA2    0
20067 #define M_USER_DATA2    0xffU
20071 #define A_MC_BIST_NUM_ERR 0x7680
20072 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
20073 #define A_MC_BIST_STATUS_RDATA 0x7688
20076 #define MA_BASE_ADDR 0x7700
20078 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
20081 #define M_THRESHOLD1    0x7fffU
20090 #define M_THRESHOLD0    0x7fffU
20094 #define S_THRESHOLD0_EN    0
20098 #define A_MA_CLIENT0_PR_THRESHOLD 0x7700
20105 #define M_T7_THRESHOLD1    0x7fffU
20113 #define S_T7_THRESHOLD0    0
20114 #define M_T7_THRESHOLD0    0x7fffU
20118 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
20119 #define A_MA_CLIENT0_CR_THRESHOLD 0x7704
20126 #define M_CREDIT_MAX    0xfffU
20130 #define S_CREDIT_VAL    0
20131 #define M_CREDIT_VAL    0xfffU
20135 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
20136 #define A_MA_CLIENT1_PR_THRESHOLD 0x7708
20137 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
20138 #define A_MA_CLIENT1_CR_THRESHOLD 0x770c
20139 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
20140 #define A_MA_CLIENT2_PR_THRESHOLD 0x7710
20141 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
20142 #define A_MA_CLIENT2_CR_THRESHOLD 0x7714
20143 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
20144 #define A_MA_CLIENT3_PR_THRESHOLD 0x7718
20145 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
20146 #define A_MA_CLIENT3_CR_THRESHOLD 0x771c
20147 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
20148 #define A_MA_CLIENT4_PR_THRESHOLD 0x7720
20149 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
20150 #define A_MA_CLIENT4_CR_THRESHOLD 0x7724
20151 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
20152 #define A_MA_CLIENT5_PR_THRESHOLD 0x7728
20153 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
20154 #define A_MA_CLIENT5_CR_THRESHOLD 0x772c
20155 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
20156 #define A_MA_CLIENT6_PR_THRESHOLD 0x7730
20157 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
20158 #define A_MA_CLIENT6_CR_THRESHOLD 0x7734
20159 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
20160 #define A_MA_CLIENT7_PR_THRESHOLD 0x7738
20161 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
20162 #define A_MA_CLIENT7_CR_THRESHOLD 0x773c
20163 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
20164 #define A_MA_CLIENT8_PR_THRESHOLD 0x7740
20165 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
20166 #define A_MA_CLIENT8_CR_THRESHOLD 0x7744
20167 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
20168 #define A_MA_CLIENT9_PR_THRESHOLD 0x7748
20169 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
20170 #define A_MA_CLIENT9_CR_THRESHOLD 0x774c
20171 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
20172 #define A_MA_CLIENT10_PR_THRESHOLD 0x7750
20173 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
20174 #define A_MA_CLIENT10_CR_THRESHOLD 0x7754
20175 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
20176 #define A_MA_CLIENT11_PR_THRESHOLD 0x7758
20177 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
20178 #define A_MA_CLIENT11_CR_THRESHOLD 0x775c
20179 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
20180 #define A_MA_CLIENT12_PR_THRESHOLD 0x7760
20181 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
20182 #define A_MA_CLIENT12_CR_THRESHOLD 0x7764
20183 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
20186 #define M_DBG_READ_DATA_CNT    0xffU
20191 #define M_DBG_READ_REQ_CNT    0xffU
20196 #define M_DBG_WRITE_DATA_CNT    0xffU
20200 #define S_DBG_WRITE_REQ_CNT    0
20201 #define M_DBG_WRITE_REQ_CNT    0xffU
20205 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
20206 #define A_MA_ULPTX_DEBUG_CNT 0x7770
20207 #define A_MA_ULPRX_DEBUG_CNT 0x7774
20208 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
20209 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
20210 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
20211 #define A_MA_LE_DEBUG_CNT 0x7784
20212 #define A_MA_CIM_DEBUG_CNT 0x7788
20213 #define A_MA_CIM_TH0_DEBUG_CNT 0x7788
20214 #define A_MA_PCIE_DEBUG_CNT 0x778c
20215 #define A_MA_PMTX_DEBUG_CNT 0x7790
20216 #define A_MA_PMRX_DEBUG_CNT 0x7794
20217 #define A_MA_HMA_DEBUG_CNT 0x7798
20218 #define A_MA_COR_ERROR_ENABLE1 0x779c
20256 #define S_ARB0_COR_RDQUEUE_ERROR_EN    0
20260 #define A_MA_COR_ERROR_STATUS1 0x77a0
20298 #define S_ARB0_COR_RDQUEUE_ERROR    0
20302 #define A_MA_DBG_CTL 0x77a4
20312 #define S_T7_SEL    0
20313 #define M_T7_SEL    0xffU
20317 #define A_MA_DBG_DATA 0x77a8
20318 #define A_MA_COR_ERROR_ENABLE2 0x77b0
20376 #define S_CL0_COR_WRQUEUE_ERROR_EN    0
20380 #define A_MA_COR_ERROR_STATUS2 0x77b4
20438 #define S_CL0_COR_WRQUEUE_ERROR    0
20442 #define A_MA_COR_ERROR_ENABLE3 0x77b8
20500 #define S_CL0_COR_RDQUEUE_ERROR_EN    0
20504 #define A_MA_COR_ERROR_STATUS3 0x77bc
20562 #define S_CL0_COR_RDQUEUE_ERROR    0
20566 #define A_MA_EDRAM0_BAR 0x77c0
20569 #define M_EDRAM0_BASE    0xfffU
20573 #define S_EDRAM0_SIZE    0
20574 #define M_EDRAM0_SIZE    0xfffU
20579 #define M_T7_EDRAM0_BASE    0xffffU
20583 #define S_T7_EDRAM0_SIZE    0
20584 #define M_T7_EDRAM0_SIZE    0xffffU
20588 #define A_MA_EDRAM1_BAR 0x77c4
20591 #define M_EDRAM1_BASE    0xfffU
20595 #define S_EDRAM1_SIZE    0
20596 #define M_EDRAM1_SIZE    0xfffU
20601 #define M_T7_EDRAM1_BASE    0xffffU
20605 #define S_T7_EDRAM1_SIZE    0
20606 #define M_T7_EDRAM1_SIZE    0xffffU
20610 #define A_MA_EXT_MEMORY_BAR 0x77c8
20613 #define M_EXT_MEM_BASE    0xfffU
20617 #define S_EXT_MEM_SIZE    0
20618 #define M_EXT_MEM_SIZE    0xfffU
20622 #define A_MA_EXT_MEMORY0_BAR 0x77c8
20625 #define M_EXT_MEM0_BASE    0xfffU
20629 #define S_EXT_MEM0_SIZE    0
20630 #define M_EXT_MEM0_SIZE    0xfffU
20635 #define M_T7_EXT_MEM0_BASE    0xffffU
20639 #define S_T7_EXT_MEM0_SIZE    0
20640 #define M_T7_EXT_MEM0_SIZE    0xffffU
20644 #define A_MA_HOST_MEMORY_BAR 0x77cc
20647 #define M_HMA_BASE    0xfffU
20651 #define S_HMA_SIZE    0
20652 #define M_HMA_SIZE    0xfffU
20657 #define M_HMATARGETBASE    0xffffU
20661 #define S_T7_HMA_SIZE    0
20662 #define M_T7_HMA_SIZE    0xffffU
20666 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
20672 #define S_EXT_MEM_PAGE_SIZE    0
20673 #define M_EXT_MEM_PAGE_SIZE    0x3U
20682 #define M_EXT_MEM_PAGE_SIZE1    0x3U
20694 #define S_T6_EXT_MEM_PAGE_SIZE    0
20695 #define M_T6_EXT_MEM_PAGE_SIZE    0x7U
20699 #define A_MA_ARB_CTRL 0x77d4
20705 #define S_DIS_ADV_ARB    0
20718 #define M_HMA_NUM_PG_128B_FDBK    0x1fU
20743 #define M_NUM_PG_128B_FDBK    0x1fU
20755 #define A_MA_TARGET_MEM_ENABLE 0x77d8
20769 #define S_EDRAM0_ENABLE    0
20797 #define A_MA_INT_ENABLE 0x77dc
20803 #define S_MEM_WRAP_INT_ENABLE    0
20811 #define A_MA_INT_CAUSE 0x77e0
20817 #define S_MEM_WRAP_INT_CAUSE    0
20825 #define A_MA_INT_WRAP_STATUS 0x77e4
20828 #define M_MEM_WRAP_ADDRESS    0xfffffffU
20832 #define S_MEM_WRAP_CLIENT_NUM    0
20833 #define M_MEM_WRAP_CLIENT_NUM    0xfU
20837 #define A_MA_TP_THREAD1_MAPPER 0x77e8
20839 #define S_TP_THREAD1_EN    0
20840 #define M_TP_THREAD1_EN    0xffU
20844 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
20846 #define S_SGE_THREAD1_EN    0
20847 #define M_SGE_THREAD1_EN    0xffU
20851 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
20977 #define S_CL0_PAR_RDQUEUE_ERROR_EN    0
20981 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
21027 #define S_T7_LOGIC_FIFO_PAR_ERROR_EN    0
21031 #define A_MA_PARITY_ERROR_STATUS 0x77f4
21157 #define S_CL0_PAR_RDQUEUE_ERROR    0
21161 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
21207 #define S_T7_LOGIC_FIFO_PAR_ERROR    0
21211 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
21214 #define M_BONUS_REG    0x3ffffffU
21219 #define M_COHERANCY_CMD_TYPE    0x3U
21224 #define M_COHERANCY_THREAD_NUM    0x7U
21228 #define S_COHERANCY_ENABLE    0
21232 #define A_MA_ERROR_ENABLE 0x77fc
21234 #define S_UE_ENABLE    0
21239 #define M_FUTURE_EXPANSION    0x7fffffffU
21244 #define M_FUTURE_EXPANSION_EE    0x7fffffffU
21248 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
21254 #define S_ARB4_PAR_RDQUEUE_ERROR_EN    0
21314 #define S_T7_CL0_PAR_WRQUEUE_ERROR_EN    0
21318 #define A_MA_PARITY_ERROR_STATUS2 0x7804
21324 #define S_ARB4_PAR_RDQUEUE_ERROR    0
21384 #define S_T7_CL0_PAR_WRQUEUE_ERROR    0
21388 #define A_MA_EXT_MEMORY1_BAR 0x7808
21391 #define M_EXT_MEM1_BASE    0xfffU
21395 #define S_EXT_MEM1_SIZE    0
21396 #define M_EXT_MEM1_SIZE    0xfffU
21401 #define M_T7_EXT_MEM1_BASE    0xffffU
21405 #define S_T7_EXT_MEM1_SIZE    0
21406 #define M_T7_EXT_MEM1_SIZE    0xffffU
21410 #define A_MA_PMTX_THROTTLE 0x780c
21416 #define S_FL_LIMIT    0
21417 #define M_FL_LIMIT    0xffU
21421 #define A_MA_PMRX_THROTTLE 0x7810
21422 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
21423 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
21424 #define A_MA_ULPTX_WRDATA_CNT 0x781c
21425 #define A_MA_ULPRX_WRDATA_CNT 0x7820
21426 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
21427 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
21428 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
21429 #define A_MA_LE_WRDATA_CNT 0x7830
21430 #define A_MA_CIM_WRDATA_CNT 0x7834
21431 #define A_MA_CIM_TH0_WRDATA_CNT 0x7834
21432 #define A_MA_PCIE_WRDATA_CNT 0x7838
21433 #define A_MA_PMTX_WRDATA_CNT 0x783c
21434 #define A_MA_PMRX_WRDATA_CNT 0x7840
21435 #define A_MA_HMA_WRDATA_CNT 0x7844
21436 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
21437 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
21438 #define A_MA_ULPTX_RDDATA_CNT 0x7850
21439 #define A_MA_ULPRX_RDDATA_CNT 0x7854
21440 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
21441 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
21442 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
21443 #define A_MA_LE_RDDATA_CNT 0x7864
21444 #define A_MA_CIM_RDDATA_CNT 0x7868
21445 #define A_MA_CIM_TH0_RDDATA_CNT 0x7868
21446 #define A_MA_PCIE_RDDATA_CNT 0x786c
21447 #define A_MA_PMTX_RDDATA_CNT 0x7870
21448 #define A_MA_PMRX_RDDATA_CNT 0x7874
21449 #define A_MA_HMA_RDDATA_CNT 0x7878
21450 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
21451 #define A_MA_EXIT_ADDR_FAULT 0x787c
21453 #define S_EXIT_ADDR_FAULT    0
21457 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
21458 #define A_MA_DDR_DEVICE_CFG 0x7880
21461 #define M_MEM_WIDTH    0x7U
21465 #define S_DDR_MODE    0
21469 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
21470 #define A_MA_PARITY_ERROR_ENABLE3 0x7884
21488 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
21489 #define A_MA_PARITY_ERROR_STATUS3 0x7888
21507 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
21508 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
21509 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
21510 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
21511 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
21512 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
21513 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
21514 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
21515 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
21516 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
21517 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
21518 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
21519 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
21520 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
21521 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
21522 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
21523 #define A_MA_TIMEOUT_CFG 0x78cc
21546 #define M_CLIENT    0xfU
21550 #define S_DELAY    0
21551 #define M_DELAY    0xffffU
21555 #define A_MA_TIMEOUT_CNT 0x78d0
21557 #define S_CNT_VAL    0
21558 #define M_CNT_VAL    0xffffU
21562 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
21565 #define M_FUTURE_CEXPANSION    0x7U
21622 #define M_FUTURE_DEXPANSION    0x7U
21674 #define S_CL0_WR_DATA_TO_EN    0
21679 #define M_FUTURE_CEXPANSION_WTE    0x7U
21684 #define M_FUTURE_DEXPANSION_WTE    0x7U
21712 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
21814 #define S_CL0_WR_DATA_TO_ERROR    0
21819 #define M_FUTURE_CEXPANSION_WTS    0x7U
21824 #define M_FUTURE_DEXPANSION_WTS    0x7U
21852 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
21954 #define S_CL0_RD_DATA_TO_EN    0
21959 #define M_FUTURE_CEXPANSION_RTE    0x7U
21964 #define M_FUTURE_DEXPANSION_RTE    0x7U
21992 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
22094 #define S_CL0_RD_DATA_TO_ERROR    0
22099 #define M_FUTURE_CEXPANSION_RTS    0x7U
22104 #define M_FUTURE_DEXPANSION_RTS    0x7U
22121 #define M_T7_FUTURE_DEXPANSION_RTS    0x3U
22129 #define A_MA_BKP_CNT_SEL 0x78e4
22132 #define M_BKP_CNT_TYPE    0x3U
22137 #define M_BKP_CLIENT    0xfU
22141 #define A_MA_BKP_CNT 0x78e8
22142 #define A_MA_WRT_ARB 0x78ec
22149 #define M_WR_TIM    0xffU
22154 #define M_RD_WIN    0xffU
22158 #define S_WR_WIN    0
22159 #define M_WR_WIN    0xffU
22163 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
22166 #define M_T5_FUTURE_DEXPANSION    0x7ffffU
22218 #define S_CL0_IF_PAR_EN    0
22223 #define M_FUTURE_DEXPANSION_IPE    0x7ffffU
22228 #define M_T7_FUTURE_DEXPANSION_IPE    0x3ffffU
22236 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
22286 #define S_CL0_IF_PAR_ERROR    0
22291 #define M_FUTURE_DEXPANSION_IPS    0x7ffffU
22296 #define M_T7_FUTURE_DEXPANSION_IPS    0x3ffffU
22304 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
22319 #define M_DEBUGPAGE    0x7U
22323 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
22324 #define A_MA_CLIENT13_PR_THRESHOLD 0x7900
22325 #define A_MA_CLIENT13_CR_THRESHOLD 0x7904
22326 #define A_MA_CRYPTO_DEBUG_CNT 0x7908
22327 #define A_MA_CRYPTO_WRDATA_CNT 0x790c
22328 #define A_MA_CRYPTO_RDDATA_CNT 0x7910
22329 #define A_MA_LOCAL_DEBUG_PERF_CFG 0x7914
22330 #define A_MA_LOCAL_DEBUG_PERF_RPT 0x7918
22331 #define A_MA_PCIE_THROTTLE 0x791c
22332 #define A_MA_CLIENT14_PR_THRESHOLD 0x7920
22333 #define A_MA_CLIENT14_CR_THRESHOLD 0x7924
22334 #define A_MA_CIM_TH1_DEBUG_CNT 0x7928
22335 #define A_MA_CIM_TH1_WRDATA_CNT 0x792c
22336 #define A_MA_CIM_TH1_RDDATA_CNT 0x7930
22337 #define A_MA_CIM_THREAD1_MAPPER 0x7934
22339 #define S_CIM_THREAD1_EN    0
22340 #define M_CIM_THREAD1_EN    0xffU
22344 #define A_MA_PIO_CI_SGE_TH0_BASE 0x7938
22346 #define S_SGE_TH0_BASE    0
22347 #define M_SGE_TH0_BASE    0xffffU
22351 #define A_MA_PIO_CI_SGE_TH1_BASE 0x793c
22353 #define S_SGE_TH1_BASE    0
22354 #define M_SGE_TH1_BASE    0xffffU
22358 #define A_MA_PIO_CI_ULPTX_BASE 0x7940
22360 #define S_ULPTX_BASE    0
22361 #define M_ULPTX_BASE    0xffffU
22365 #define A_MA_PIO_CI_ULPRX_BASE 0x7944
22367 #define S_ULPRX_BASE    0
22368 #define M_ULPRX_BASE    0xffffU
22372 #define A_MA_PIO_CI_ULPTXRX_BASE 0x7948
22374 #define S_ULPTXRX_BASE    0
22375 #define M_ULPTXRX_BASE    0xffffU
22379 #define A_MA_PIO_CI_TP_TH0_BASE 0x794c
22381 #define S_TP_TH0_BASE    0
22382 #define M_TP_TH0_BASE    0xffffU
22386 #define A_MA_PIO_CI_TP_TH1_BASE 0x7950
22388 #define S_TP_TH1_BASE    0
22389 #define M_TP_TH1_BASE    0xffffU
22393 #define A_MA_PIO_CI_LE_BASE 0x7954
22395 #define S_LE_BASE    0
22396 #define M_LE_BASE    0xffffU
22400 #define A_MA_PIO_CI_CIM_TH0_BASE 0x7958
22402 #define S_CIM_TH0_BASE    0
22403 #define M_CIM_TH0_BASE    0xffffU
22407 #define A_MA_PIO_CI_PCIE_BASE 0x795c
22409 #define S_PCIE_BASE    0
22410 #define M_PCIE_BASE    0xffffU
22414 #define A_MA_PIO_CI_PMTX_BASE 0x7960
22416 #define S_PMTX_BASE    0
22417 #define M_PMTX_BASE    0xffffU
22421 #define A_MA_PIO_CI_PMRX_BASE 0x7964
22423 #define S_PMRX_BASE    0
22424 #define M_PMRX_BASE    0xffffU
22428 #define A_MA_PIO_CI_HMA_BASE 0x7968
22430 #define S_HMACLIENTBASE    0
22431 #define M_HMACLIENTBASE    0xffffU
22435 #define A_MA_PIO_CI_CRYPTO_BASE 0x796c
22437 #define S_CRYPTO_BASE    0
22438 #define M_CRYPTO_BASE    0xffffU
22442 #define A_MA_PIO_CI_CIM_TH1_BASE 0x7970
22444 #define S_CIM_TH1_BASE    0
22445 #define M_CIM_TH1_BASE    0xffffU
22449 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa000
22464 #define M_CMDLEN0    0xffU
22469 #define M_CMDADDR0    0x1fffU
22489 #define S_RDDATA0    0
22490 #define M_RDDATA0    0xfU
22494 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa001
22509 #define M_CMDLEN1    0xffU
22514 #define M_CMDADDR1    0x1fffU
22534 #define S_RDDATA1    0
22535 #define M_RDDATA1    0xfU
22539 #define A_MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL 0xa002
22554 #define M_CMDLEN2    0xffU
22559 #define M_CMDADDR2    0x1fffU
22579 #define S_RDDATA2    0
22580 #define M_RDDATA2    0xfU
22584 #define A_MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL 0xa003
22599 #define M_CMDLEN3    0xffU
22604 #define M_CMDADDR3    0x1fffU
22624 #define S_RDDATA3    0
22625 #define M_RDDATA3    0xfU
22629 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL 0xa004
22644 #define M_CMDLEN4    0xffU
22649 #define M_CMDADDR4    0x1fffU
22669 #define S_RDDATA4    0
22670 #define M_RDDATA4    0xfU
22674 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL 0xa005
22689 #define M_CMDLEN5    0xffU
22694 #define M_CMDADDR5    0x1fffU
22714 #define S_RDDATA5    0
22715 #define M_RDDATA5    0xfU
22719 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL 0xa006
22734 #define M_CMDLEN6    0xffU
22739 #define M_CMDADDR6    0x1fffU
22759 #define S_RDDATA6    0
22760 #define M_RDDATA6    0xfU
22764 #define A_MA_LE_CLIENT_INTERFACE_EXTERNAL 0xa007
22779 #define M_CMDLEN7    0xffU
22784 #define M_CMDADDR7    0x1fffU
22804 #define S_RDDATA7    0
22805 #define M_RDDATA7    0xfU
22809 #define A_MA_CIM_CLIENT_INTERFACE_EXTERNAL 0xa008
22824 #define M_CMDLEN8    0xffU
22829 #define M_CMDADDR8    0x1fffU
22849 #define S_RDDATA8    0
22850 #define M_RDDATA8    0xfU
22854 #define A_MA_PCIE_CLIENT_INTERFACE_EXTERNAL 0xa009
22869 #define M_CMDLEN9    0xffU
22874 #define M_CMDADDR9    0x1fffU
22894 #define S_RDDATA9    0
22895 #define M_RDDATA9    0xfU
22899 #define A_MA_PM_TX_CLIENT_INTERFACE_EXTERNAL 0xa00a
22914 #define M_CMDLEN10    0xffU
22919 #define M_CMDADDR10    0x1fffU
22939 #define S_RDDATA10    0
22940 #define M_RDDATA10    0xfU
22944 #define A_MA_PM_RX_CLIENT_INTERFACE_EXTERNAL 0xa00b
22959 #define M_CMDLEN11    0xffU
22964 #define M_CMDADDR11    0x1fffU
22984 #define S_RDDATA11    0
22985 #define M_RDDATA11    0xfU
22989 #define A_MA_HMA_CLIENT_INTERFACE_EXTERNAL 0xa00c
23004 #define M_CMDLEN12    0xffU
23009 #define M_CMDADDR12    0x1fffU
23029 #define S_RDDATA12    0
23030 #define M_RDDATA12    0xfU
23034 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00d
23160 #define S_DM0_CI7_RDATA_VLD    0
23164 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00e
23290 #define S_DM1_CI7_RDATA_VLD    0
23294 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0 0xa00f
23420 #define S_DM2_CI7_RDATA_VLD    0
23424 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0 0xa010
23550 #define S_DM3_CI7_RDATA_VLD    0
23554 #define A_MA_MA_DEBUG_SIGNATURE_LTL_END 0xa011
23555 #define A_MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE 0xa012
23556 #define A_MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1 0xa013
23638 #define A_MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1 0xa014
23720 #define A_MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1 0xa015
23802 #define A_MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1 0xa016
23884 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa400
23887 #define M_CMD_IN_FIFO_CNT0    0x3U
23892 #define M_CMD_SPLIT_FIFO_CNT0    0x3U
23897 #define M_CMD_THROTTLE_FIFO_CNT0    0x3fU
23902 #define M_RD_CHNL_FIFO_CNT0    0x7fU
23907 #define M_RD_DATA_EXT_FIFO_CNT0    0x3U
23912 #define M_RD_DATA_512B_FIFO_CNT0    0xffU
23917 #define M_RD_REQ_TAG_FIFO_CNT0    0xfU
23921 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa401
23924 #define M_CMD_IN_FIFO_CNT1    0x3U
23929 #define M_CMD_SPLIT_FIFO_CNT1    0x3U
23934 #define M_CMD_THROTTLE_FIFO_CNT1    0x3fU
23939 #define M_RD_CHNL_FIFO_CNT1    0x7fU
23944 #define M_RD_DATA_EXT_FIFO_CNT1    0x3U
23949 #define M_RD_DATA_512B_FIFO_CNT1    0xffU
23954 #define M_RD_REQ_TAG_FIFO_CNT1    0xfU
23958 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa402
23961 #define M_CMD_IN_FIFO_CNT2    0x3U
23966 #define M_CMD_SPLIT_FIFO_CNT2    0x3U
23971 #define M_CMD_THROTTLE_FIFO_CNT2    0x3fU
23976 #define M_RD_CHNL_FIFO_CNT2    0x7fU
23981 #define M_RD_DATA_EXT_FIFO_CNT2    0x3U
23986 #define M_RD_DATA_512B_FIFO_CNT2    0xffU
23991 #define M_RD_REQ_TAG_FIFO_CNT2    0xfU
23995 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa403
23998 #define M_CMD_IN_FIFO_CNT3    0x3U
24003 #define M_CMD_SPLIT_FIFO_CNT3    0x3U
24008 #define M_CMD_THROTTLE_FIFO_CNT3    0x3fU
24013 #define M_RD_CHNL_FIFO_CNT3    0x7fU
24018 #define M_RD_DATA_EXT_FIFO_CNT3    0x3U
24023 #define M_RD_DATA_512B_FIFO_CNT3    0xffU
24028 #define M_RD_REQ_TAG_FIFO_CNT3    0xfU
24032 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa404
24035 #define M_CMD_IN_FIFO_CNT4    0x3U
24040 #define M_CMD_SPLIT_FIFO_CNT4    0x3U
24045 #define M_CMD_THROTTLE_FIFO_CNT4    0x3fU
24050 #define M_RD_CHNL_FIFO_CNT4    0x7fU
24055 #define M_RD_DATA_EXT_FIFO_CNT4    0x3U
24060 #define M_RD_DATA_512B_FIFO_CNT4    0xffU
24065 #define M_RD_REQ_TAG_FIFO_CNT4    0xfU
24069 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0 0xa405
24072 #define M_CMD_IN_FIFO_CNT5    0x3U
24077 #define M_CMD_SPLIT_FIFO_CNT5    0x3U
24082 #define M_CMD_THROTTLE_FIFO_CNT5    0x3fU
24087 #define M_RD_CHNL_FIFO_CNT5    0x7fU
24092 #define M_RD_DATA_EXT_FIFO_CNT5    0x3U
24097 #define M_RD_DATA_512B_FIFO_CNT5    0xffU
24102 #define M_RD_REQ_TAG_FIFO_CNT5    0xfU
24106 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0 0xa406
24109 #define M_CMD_IN_FIFO_CNT6    0x3U
24114 #define M_CMD_SPLIT_FIFO_CNT6    0x3U
24119 #define M_CMD_THROTTLE_FIFO_CNT6    0x3fU
24124 #define M_RD_CHNL_FIFO_CNT6    0x7fU
24129 #define M_RD_DATA_EXT_FIFO_CNT6    0x3U
24134 #define M_RD_DATA_512B_FIFO_CNT6    0xffU
24139 #define M_RD_REQ_TAG_FIFO_CNT6    0xfU
24143 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG0 0xa407
24146 #define M_CMD_IN_FIFO_CNT7    0x3U
24151 #define M_CMD_SPLIT_FIFO_CNT7    0x3U
24156 #define M_CMD_THROTTLE_FIFO_CNT7    0x3fU
24161 #define M_RD_CHNL_FIFO_CNT7    0x7fU
24166 #define M_RD_DATA_EXT_FIFO_CNT7    0x3U
24171 #define M_RD_DATA_512B_FIFO_CNT7    0xffU
24176 #define M_RD_REQ_TAG_FIFO_CNT7    0xfU
24180 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0 0xa408
24183 #define M_CMD_IN_FIFO_CNT8    0x3U
24188 #define M_CMD_SPLIT_FIFO_CNT8    0x3U
24193 #define M_CMD_THROTTLE_FIFO_CNT8    0x3fU
24198 #define M_RD_CHNL_FIFO_CNT8    0x7fU
24203 #define M_RD_DATA_EXT_FIFO_CNT8    0x3U
24208 #define M_RD_DATA_512B_FIFO_CNT8    0xffU
24213 #define M_RD_REQ_TAG_FIFO_CNT8    0xfU
24217 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0 0xa409
24220 #define M_CMD_IN_FIFO_CNT9    0x3U
24225 #define M_CMD_SPLIT_FIFO_CNT9    0x3U
24230 #define M_CMD_THROTTLE_FIFO_CNT9    0x3fU
24235 #define M_RD_CHNL_FIFO_CNT9    0x7fU
24240 #define M_RD_DATA_EXT_FIFO_CNT9    0x3U
24245 #define M_RD_DATA_512B_FIFO_CNT9    0xffU
24250 #define M_RD_REQ_TAG_FIFO_CNT9    0xfU
24254 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40a
24257 #define M_CMD_IN_FIFO_CNT10    0x3U
24262 #define M_CMD_SPLIT_FIFO_CNT10    0x3U
24267 #define M_CMD_THROTTLE_FIFO_CNT10    0x3fU
24272 #define M_RD_CHNL_FIFO_CNT10    0x7fU
24277 #define M_RD_DATA_EXT_FIFO_CNT10    0x3U
24282 #define M_RD_DATA_512B_FIFO_CNT10    0xffU
24287 #define M_RD_REQ_TAG_FIFO_CNT10    0xfU
24291 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0 0xa40b
24294 #define M_CMD_IN_FIFO_CNT11    0x3U
24299 #define M_CMD_SPLIT_FIFO_CNT11    0x3U
24304 #define M_CMD_THROTTLE_FIFO_CNT11    0x3fU
24309 #define M_RD_CHNL_FIFO_CNT11    0x7fU
24314 #define M_RD_DATA_EXT_FIFO_CNT11    0x3U
24319 #define M_RD_DATA_512B_FIFO_CNT11    0xffU
24324 #define M_RD_REQ_TAG_FIFO_CNT11    0xfU
24328 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0 0xa40c
24331 #define M_CMD_IN_FIFO_CNT12    0x3U
24336 #define M_CMD_SPLIT_FIFO_CNT12    0x3U
24341 #define M_CMD_THROTTLE_FIFO_CNT12    0x3fU
24346 #define M_RD_CHNL_FIFO_CNT12    0x7fU
24351 #define M_RD_DATA_EXT_FIFO_CNT12    0x3U
24356 #define M_RD_DATA_512B_FIFO_CNT12    0xffU
24361 #define M_RD_REQ_TAG_FIFO_CNT12    0xfU
24365 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0 0xa40d
24376 #define M_TGT_CMD_FIFO_CNT0    0x7U
24381 #define M_CLNT_NUM_FIFO_CNT0    0x7U
24386 #define M_WR_CMD_TAG_FIFO_CNT_TGT0    0xffU
24390 #define S_WR_DATA_512B_FIFO_CNT_TGT0    0
24391 #define M_WR_DATA_512B_FIFO_CNT_TGT0    0xffU
24395 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0 0xa40e
24406 #define M_TGT_CMD_FIFO_CNT1    0x7U
24411 #define M_CLNT_NUM_FIFO_CNT1    0x7U
24416 #define M_WR_CMD_TAG_FIFO_CNT_TGT1    0xffU
24420 #define S_WR_DATA_512B_FIFO_CNT_TGT1    0
24421 #define M_WR_DATA_512B_FIFO_CNT_TGT1    0xffU
24425 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0 0xa40f
24436 #define M_TGT_CMD_FIFO_CNT2    0x7U
24441 #define M_CLNT_NUM_FIFO_CNT2    0x7U
24446 #define M_WR_CMD_TAG_FIFO_CNT_TGT2    0xffU
24450 #define S_WR_DATA_512B_FIFO_CNT_TGT2    0
24451 #define M_WR_DATA_512B_FIFO_CNT_TGT2    0xffU
24455 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0 0xa410
24466 #define M_TGT_CMD_FIFO_CNT3    0x7U
24471 #define M_CLNT_NUM_FIFO_CNT3    0x7U
24476 #define M_WR_CMD_TAG_FIFO_CNT_TGT3    0xffU
24480 #define S_WR_DATA_512B_FIFO_CNT_TGT    0
24481 #define M_WR_DATA_512B_FIFO_CNT_TGT    0xffU
24485 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa412
24486 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa413
24487 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa414
24488 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa415
24489 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa416
24490 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_LO 0xa417
24491 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_LO 0xa418
24492 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_LO 0xa419
24493 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_LO 0xa41a
24494 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_LO 0xa41b
24495 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_LO 0xa41c
24496 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_LO 0xa41d
24497 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_LO 0xa41e
24498 #define A_T6_MA_EDRAM0_WRDATA_CNT1 0xa800
24499 #define A_T6_MA_EDRAM0_WRDATA_CNT0 0xa801
24500 #define A_T6_MA_EDRAM1_WRDATA_CNT1 0xa802
24501 #define A_T6_MA_EDRAM1_WRDATA_CNT0 0xa803
24502 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT1 0xa804
24503 #define A_T6_MA_EXT_MEMORY0_WRDATA_CNT0 0xa805
24504 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT1 0xa806
24505 #define A_T6_MA_HOST_MEMORY_WRDATA_CNT0 0xa807
24506 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT1 0xa808
24507 #define A_T6_MA_EXT_MEMORY1_WRDATA_CNT0 0xa809
24508 #define A_T6_MA_EDRAM0_RDDATA_CNT1 0xa80a
24509 #define A_T6_MA_EDRAM0_RDDATA_CNT0 0xa80b
24510 #define A_T6_MA_EDRAM1_RDDATA_CNT1 0xa80c
24511 #define A_T6_MA_EDRAM1_RDDATA_CNT0 0xa80d
24512 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT1 0xa80e
24513 #define A_T6_MA_EXT_MEMORY0_RDDATA_CNT0 0xa80f
24514 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT1 0xa810
24515 #define A_T6_MA_HOST_MEMORY_RDDATA_CNT0 0xa811
24516 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT1 0xa812
24517 #define A_T6_MA_EXT_MEMORY1_RDDATA_CNT0 0xa813
24518 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac00
24519 #define A_MA_SGE_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac01
24520 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac02
24521 #define A_MA_SGE_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac03
24522 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac04
24523 #define A_MA_ULP_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac05
24524 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac06
24525 #define A_MA_ULP_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac07
24526 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac08
24527 #define A_MA_ULP_TX_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac09
24528 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_HI 0xac0a
24529 #define A_MA_TP_THREAD_0_CLNT_ACT_WR_CYC_CNT_LO 0xac0b
24530 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_HI 0xac0c
24531 #define A_MA_TP_THREAD_1_CLNT_ACT_WR_CYC_CNT_LO 0xac0d
24532 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_HI 0xac0e
24533 #define A_MA_LE_CLNT_ACT_WR_CYC_CNT_LO 0xac0f
24534 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_HI 0xac10
24535 #define A_MA_CIM_CLNT_ACT_WR_CYC_CNT_LO 0xac11
24536 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_HI 0xac12
24537 #define A_MA_PCIE_CLNT_ACT_WR_CYC_CNT_LO 0xac13
24538 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_HI 0xac14
24539 #define A_MA_PM_TX_CLNT_ACT_WR_CYC_CNT_LO 0xac15
24540 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_HI 0xac16
24541 #define A_MA_PM_RX_CLNT_ACT_WR_CYC_CNT_LO 0xac17
24542 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_HI 0xac18
24543 #define A_MA_HMA_CLNT_ACT_WR_CYC_CNT_LO 0xac19
24544 #define A_MA_SGE_THREAD_0_CLNT_WR_REQ_CNT 0xb000
24545 #define A_MA_SGE_THREAD_1_CLNT_WR_REQ_CNT 0xb001
24546 #define A_MA_ULP_TX_CLNT_WR_REQ_CNT 0xb002
24547 #define A_MA_ULP_RX_CLNT_WR_REQ_CNT 0xb003
24548 #define A_MA_ULP_TX_RX_CLNT_WR_REQ_CNT 0xb004
24549 #define A_MA_TP_THREAD_0_CLNT_WR_REQ_CNT 0xb005
24550 #define A_MA_TP_THREAD_1_CLNT_WR_REQ_CNT 0xb006
24551 #define A_MA_LE_CLNT_WR_REQ_CNT 0xb007
24552 #define A_MA_CIM_CLNT_WR_REQ_CNT 0xb008
24553 #define A_MA_PCIE_CLNT_WR_REQ_CNT 0xb009
24554 #define A_MA_PM_TX_CLNT_WR_REQ_CNT 0xb00a
24555 #define A_MA_PM_RX_CLNT_WR_REQ_CNT 0xb00b
24556 #define A_MA_HMA_CLNT_WR_REQ_CNT 0xb00c
24557 #define A_MA_SGE_THREAD_0_CLNT_RD_REQ_CNT 0xb00d
24558 #define A_MA_SGE_THREAD_1_CLNT_RD_REQ_CNT 0xb00e
24559 #define A_MA_ULP_TX_CLNT_RD_REQ_CNT 0xb00f
24560 #define A_MA_ULP_RX_CLNT_RD_REQ_CNT 0xb010
24561 #define A_MA_ULP_TX_RX_CLNT_RD_REQ_CNT 0xb011
24562 #define A_MA_TP_THREAD_0_CLNT_RD_REQ_CNT 0xb012
24563 #define A_MA_TP_THREAD_1_CLNT_RD_REQ_CNT 0xb013
24564 #define A_MA_LE_CLNT_RD_REQ_CNT 0xb014
24565 #define A_MA_CIM_CLNT_RD_REQ_CNT 0xb015
24566 #define A_MA_PCIE_CLNT_RD_REQ_CNT 0xb016
24567 #define A_MA_PM_TX_CLNT_RD_REQ_CNT 0xb017
24568 #define A_MA_PM_RX_CLNT_RD_REQ_CNT 0xb018
24569 #define A_MA_HMA_CLNT_RD_REQ_CNT 0xb019
24570 #define A_MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb400
24571 #define A_MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb401
24572 #define A_MA_ULP_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb402
24573 #define A_MA_ULP_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb403
24574 #define A_MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb404
24575 #define A_MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT_HI 0xb405
24576 #define A_MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT_HI 0xb406
24577 #define A_MA_LE_CLNT_EXP_RD_CYC_CNT_HI 0xb407
24578 #define A_MA_CIM_CLNT_EXP_RD_CYC_CNT_HI 0xb408
24579 #define A_MA_PCIE_CLNT_EXP_RD_CYC_CNT_HI 0xb409
24580 #define A_MA_PM_TX_CLNT_EXP_RD_CYC_CNT_HI 0xb40a
24581 #define A_MA_PM_RX_CLNT_EXP_RD_CYC_CNT_HI 0xb40b
24582 #define A_MA_HMA_CLNT_EXP_RD_CYC_CNT_HI 0xb40c
24583 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb40d
24584 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb40e
24585 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb40f
24586 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb410
24587 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb411
24588 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_HI 0xb412
24589 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_HI 0xb413
24590 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_HI 0xb414
24591 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_HI 0xb415
24592 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_HI 0xb416
24593 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_HI 0xb417
24594 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_HI 0xb418
24595 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_HI 0xb419
24596 #define A_MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe400
24599 #define M_WR_DATA_EXT_FIFO_CNT0    0x3U
24604 #define M_WR_CMD_TAG_FIFO_CNT0    0xfU
24609 #define M_WR_DATA_512B_FIFO_CNT0    0xffU
24634 #define M_CMD_SPLIT_FSM0    0x7U
24638 #define A_MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe420
24641 #define M_WR_DATA_EXT_FIFO_CNT1    0x3U
24646 #define M_WR_CMD_TAG_FIFO_CNT1    0xfU
24651 #define M_WR_DATA_512B_FIFO_CNT1    0xffU
24676 #define M_CMD_SPLIT_FSM1    0x7U
24680 #define A_MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe440
24683 #define M_WR_DATA_EXT_FIFO_CNT2    0x3U
24688 #define M_WR_CMD_TAG_FIFO_CNT2    0xfU
24693 #define M_WR_DATA_512B_FIFO_CNT2    0xffU
24718 #define M_CMD_SPLIT_FSM2    0x7U
24722 #define A_MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe460
24725 #define M_WR_DATA_EXT_FIFO_CNT3    0x3U
24730 #define M_WR_CMD_TAG_FIFO_CNT3    0xfU
24735 #define M_WR_DATA_512B_FIFO_CNT3    0xffU
24760 #define M_CMD_SPLIT_FSM3    0x7U
24764 #define A_MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe480
24767 #define M_WR_DATA_EXT_FIFO_CNT4    0x3U
24772 #define M_WR_CMD_TAG_FIFO_CNT4    0xfU
24777 #define M_WR_DATA_512B_FIFO_CNT4    0xffU
24802 #define M_CMD_SPLIT_FSM4    0x7U
24806 #define A_MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1 0xe4a0
24809 #define M_WR_DATA_EXT_FIFO_CNT5    0x3U
24814 #define M_WR_CMD_TAG_FIFO_CNT5    0xfU
24819 #define M_WR_DATA_512B_FIFO_CNT5    0xffU
24844 #define M_CMD_SPLIT_FSM5    0x7U
24848 #define A_MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1 0xe4c0
24851 #define M_WR_DATA_EXT_FIFO_CNT6    0x3U
24856 #define M_WR_CMD_TAG_FIFO_CNT6    0xfU
24861 #define M_WR_DATA_512B_FIFO_CNT6    0xffU
24886 #define M_CMD_SPLIT_FSM6    0x7U
24890 #define A_MA_LE_CLIENT_INTERFACE_INTERNAL_REG1 0xe4e0
24893 #define M_WR_DATA_EXT_FIFO_CNT7    0x3U
24898 #define M_WR_CMD_TAG_FIFO_CNT7    0xfU
24903 #define M_WR_DATA_512B_FIFO_CNT7    0xffU
24928 #define M_CMD_SPLIT_FSM7    0x7U
24932 #define A_MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1 0xe500
24935 #define M_WR_DATA_EXT_FIFO_CNT8    0x3U
24940 #define M_WR_CMD_TAG_FIFO_CNT8    0xfU
24945 #define M_WR_DATA_512B_FIFO_CNT8    0xffU
24970 #define M_CMD_SPLIT_FSM8    0x7U
24974 #define A_MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1 0xe520
24977 #define M_WR_DATA_EXT_FIFO_CNT9    0x3U
24982 #define M_WR_CMD_TAG_FIFO_CNT9    0xfU
24987 #define M_WR_DATA_512B_FIFO_CNT9    0xffU
25012 #define M_CMD_SPLIT_FSM9    0x7U
25016 #define A_MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1 0xe540
25019 #define M_WR_DATA_EXT_FIFO_CNT10    0x3U
25024 #define M_WR_CMD_TAG_FIFO_CNT10    0xfU
25029 #define M_WR_DATA_512B_FIFO_CNT10    0xffU
25054 #define M_CMD_SPLIT_FSM10    0x7U
25058 #define A_MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1 0xe560
25061 #define M_WR_DATA_EXT_FIFO_CNT11    0x3U
25066 #define M_WR_CMD_TAG_FIFO_CNT11    0xfU
25071 #define M_WR_DATA_512B_FIFO_CNT11    0xffU
25096 #define M_CMD_SPLIT_FSM11    0x7U
25100 #define A_MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1 0xe580
25103 #define M_WR_DATA_EXT_FIFO_CNT12    0x3U
25108 #define M_WR_CMD_TAG_FIFO_CNT12    0xfU
25113 #define M_WR_DATA_512B_FIFO_CNT12    0xffU
25138 #define M_CMD_SPLIT_FSM12    0x7U
25142 #define A_MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1 0xe5a0
25145 #define M_RD_CMD_TAG_FIFO_CNT0    0xffU
25149 #define S_RD_DATA_FIFO_CNT0    0
25150 #define M_RD_DATA_FIFO_CNT0    0xffU
25154 #define A_MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1 0xe5c0
25157 #define M_RD_CMD_TAG_FIFO_CNT1    0xffU
25161 #define S_RD_DATA_FIFO_CNT1    0
25162 #define M_RD_DATA_FIFO_CNT1    0xffU
25166 #define A_MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1 0xe5e0
25169 #define M_RD_CMD_TAG_FIFO_CNT2    0xffU
25173 #define S_RD_DATA_FIFO_CNT2    0
25174 #define M_RD_DATA_FIFO_CNT2    0xffU
25178 #define A_MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1 0xe600
25181 #define M_RD_CMD_TAG_FIFO_CNT3    0xffU
25185 #define S_RD_DATA_FIFO_CNT3    0
25186 #define M_RD_DATA_FIFO_CNT3    0xffU
25190 #define A_MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe640
25191 #define A_MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe660
25192 #define A_MA_ULP_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe680
25193 #define A_MA_ULP_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6a0
25194 #define A_MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe6c0
25195 #define A_MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT_LO 0xe6e0
25196 #define A_MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT_LO 0xe700
25197 #define A_MA_LE_CLNT_EXP_WR_CYC_CNT_LO 0xe720
25198 #define A_MA_CIM_CLNT_EXP_WR_CYC_CNT_LO 0xe740
25199 #define A_MA_PCIE_CLNT_EXP_WR_CYC_CNT_LO 0xe760
25200 #define A_MA_PM_TX_CLNT_EXP_WR_CYC_CNT_LO 0xe780
25201 #define A_MA_PM_RX_CLNT_EXP_WR_CYC_CNT_LO 0xe7a0
25202 #define A_MA_HMA_CLNT_EXP_WR_CYC_CNT_LO 0xe7c0
25203 #define A_MA_EDRAM0_WR_REQ_CNT_HI 0xe800
25204 #define A_MA_EDRAM0_WR_REQ_CNT_LO 0xe820
25205 #define A_MA_EDRAM1_WR_REQ_CNT_HI 0xe840
25206 #define A_MA_EDRAM1_WR_REQ_CNT_LO 0xe860
25207 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_HI 0xe880
25208 #define A_MA_EXT_MEMORY0_WR_REQ_CNT_LO 0xe8a0
25209 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_HI 0xe8c0
25210 #define A_MA_EXT_MEMORY1_WR_REQ_CNT_LO 0xe8e0
25211 #define A_MA_EDRAM0_RD_REQ_CNT_HI 0xe900
25212 #define A_MA_EDRAM0_RD_REQ_CNT_LO 0xe920
25213 #define A_MA_EDRAM1_RD_REQ_CNT_HI 0xe940
25214 #define A_MA_EDRAM1_RD_REQ_CNT_LO 0xe960
25215 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_HI 0xe980
25216 #define A_MA_EXT_MEMORY0_RD_REQ_CNT_LO 0xe9a0
25217 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_HI 0xe9c0
25218 #define A_MA_EXT_MEMORY1_RD_REQ_CNT_LO 0xe9e0
25219 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xec00
25220 #define A_MA_SGE_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xec20
25221 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xec40
25222 #define A_MA_SGE_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xec60
25223 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_HI 0xec80
25224 #define A_MA_ULP_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeca0
25225 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_HI 0xecc0
25226 #define A_MA_ULP_RX_CLNT_ACT_RD_CYC_CNT_LO 0xece0
25227 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_HI 0xed00
25228 #define A_MA_ULP_TX_RX_CLNT_ACT_RD_CYC_CNT_LO 0xed20
25229 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_HI 0xed40
25230 #define A_MA_TP_THREAD_0_CLNT_ACT_RD_CYC_CNT_LO 0xed60
25231 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_HI 0xed80
25232 #define A_MA_TP_THREAD_1_CLNT_ACT_RD_CYC_CNT_LO 0xeda0
25233 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_HI 0xedc0
25234 #define A_MA_LE_CLNT_ACT_RD_CYC_CNT_LO 0xede0
25235 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_HI 0xee00
25236 #define A_MA_CIM_CLNT_ACT_RD_CYC_CNT_LO 0xee20
25237 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_HI 0xee40
25238 #define A_MA_PCIE_CLNT_ACT_RD_CYC_CNT_LO 0xee60
25239 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_HI 0xee80
25240 #define A_MA_PM_TX_CLNT_ACT_RD_CYC_CNT_LO 0xeea0
25241 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_HI 0xeec0
25242 #define A_MA_PM_RX_CLNT_ACT_RD_CYC_CNT_LO 0xeee0
25243 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_HI 0xef00
25244 #define A_MA_HMA_CLNT_ACT_RD_CYC_CNT_LO 0xef20
25245 #define A_MA_PM_TX_RD_THROTTLE_STATUS 0xf000
25251 #define S_PTFLITCNT    0
25252 #define M_PTFLITCNT    0xffU
25256 #define A_MA_PM_RX_RD_THROTTLE_STATUS 0xf020
25262 #define S_PRFLITCNT    0
25263 #define M_PRFLITCNT    0xffU
25268 #define EDC_0_BASE_ADDR 0x7900
25270 #define A_EDC_REF 0x7900
25284 #define S_REFFREQ    0
25285 #define M_REFFREQ    0xffffU
25289 #define A_EDC_BIST_CMD 0x7904
25290 #define A_EDC_BIST_CMD_ADDR 0x7908
25291 #define A_EDC_BIST_CMD_LEN 0x790c
25292 #define A_EDC_BIST_DATA_PATTERN 0x7910
25293 #define A_EDC_BIST_USER_WDATA0 0x7914
25294 #define A_EDC_BIST_USER_WDATA1 0x7918
25295 #define A_EDC_BIST_USER_WDATA2 0x791c
25296 #define A_EDC_BIST_NUM_ERR 0x7920
25297 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
25298 #define A_EDC_BIST_STATUS_RDATA 0x7928
25299 #define A_EDC_PAR_ENABLE 0x7970
25309 #define A_EDC_INT_ENABLE 0x7974
25310 #define A_EDC_INT_CAUSE 0x7978
25324 #define A_EDC_ECC_STATUS 0x797c
25327 #define EDC_1_BASE_ADDR 0x7980
25330 #define HMA_BASE_ADDR 0x7a00
25333 #define CIM_BASE_ADDR 0x7b00
25335 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
25338 #define M_VFMBGENERIC    0xfU
25342 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
25344 #define S_MBVFREADY    0
25348 #define A_CIM_PF_MAILBOX_DATA 0x240
25349 #define A_CIM_PF_MAILBOX_CTRL 0x280
25352 #define M_MBGENERIC    0xfffffffU
25364 #define S_MBOWNER    0
25365 #define M_MBOWNER    0x3U
25369 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
25375 #define A_CIM_PF_HOST_INT_ENABLE 0x288
25381 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
25387 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
25388 #define A_CIM_BOOT_CFG 0x7b00
25391 #define M_BOOTADDR    0xffffffU
25396 #define M_UPGEN    0x3fU
25404 #define S_UPCRST    0
25408 #define A_CIM_FLASH_BASE_ADDR 0x7b04
25411 #define M_FLASHBASEADDR    0x3ffffU
25415 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
25418 #define M_FLASHADDRSIZE    0xfffffU
25422 #define A_T7_CIM_PERR_ENABLE 0x7b08
25536 #define S_PIFREQPARERR    0
25540 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
25543 #define M_EEPROMBASEADDR    0x3ffffU
25547 #define A_CIM_PERR_CAUSE 0x7b0c
25548 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
25551 #define M_EEPROMADDRSIZE    0xfffffU
25555 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
25558 #define M_SDRAMBASEADDR    0x3ffffffU
25562 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
25565 #define M_SDRAMADDRSIZE    0xfffffffU
25569 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
25572 #define M_EXTMEM2BASEADDR    0x3ffffffU
25576 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
25579 #define M_EXTMEM2ADDRSIZE    0xfffffffU
25583 #define A_CIM_UP_SPARE_INT 0x7b24
25593 #define S_UPSPAREINT    0
25594 #define M_UPSPAREINT    0x7U
25598 #define A_CIM_HOST_INT_ENABLE 0x7b28
25748 #define A_CIM_HOST_INT_CAUSE 0x7b2c
25770 #define S_UPACCNONZERO    0
25774 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
25896 #define S_RSVDSPACEINTEN    0
25904 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
26026 #define S_RSVDSPACEINT    0
26034 #define A_CIM_UP_INT_ENABLE 0x7b38
26056 #define A_CIM_UP_INT_CAUSE 0x7b3c
26062 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
26063 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
26064 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
26074 #define S_QUENUMSELECT    0
26075 #define M_QUENUMSELECT    0x7U
26080 #define M_MAPOFFSET    0x1fU
26089 #define M_CORESELECT    0xfU
26101 #define S_T7_QUENUMSELECT    0
26102 #define M_T7_QUENUMSELECT    0xfU
26106 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
26109 #define M_CIMQSIZE    0x3fU
26114 #define M_CIMQBASE    0x3fU
26122 #define S_QUEFULLTHRSH    0
26123 #define M_QUEFULLTHRSH    0x1ffU
26131 #define A_CIM_HOST_ACC_CTRL 0x7b50
26141 #define S_HOSTADDR    0
26142 #define M_HOSTADDR    0xffffU
26155 #define M_HOSTGRPSEL    0x3U
26160 #define M_HOSTCORESEL    0xfU
26164 #define S_T7_HOSTADDR    0
26165 #define M_T7_HOSTADDR    0xffffffU
26169 #define A_CIM_HOST_ACC_DATA 0x7b54
26170 #define A_CIM_CDEBUGDATA 0x7b58
26173 #define M_CDEBUGDATAH    0xffffU
26177 #define S_CDEBUGDATAL    0
26178 #define M_CDEBUGDATAL    0xffffU
26182 #define A_CIM_DEBUG_CFG 0x7b58
26197 #define M_SELH    0x1ffU
26201 #define S_SELL    0
26202 #define M_SELL    0x1ffU
26206 #define A_CIM_DEBUG_DATA 0x7b5c
26207 #define A_CIM_IBQ_DBG_CFG 0x7b60
26210 #define M_IBQDBGADDR    0xfffU
26222 #define S_IBQDBGEN    0
26227 #define M_IBQDBGCORE    0xfU
26232 #define M_T7_IBQDBGADDR    0x1fffU
26237 #define M_IBQDBGSTATE    0x3U
26245 #define A_CIM_OBQ_DBG_CFG 0x7b64
26248 #define M_OBQDBGADDR    0xfffU
26260 #define S_OBQDBGEN    0
26265 #define M_OBQDBGCORE    0xfU
26270 #define M_T7_OBQDBGADDR    0x1fffU
26275 #define M_OBQDBGSTATE    0x3U
26279 #define A_CIM_IBQ_DBG_DATA 0x7b68
26280 #define A_CIM_OBQ_DBG_DATA 0x7b6c
26281 #define A_CIM_DEBUGCFG 0x7b70
26284 #define M_POLADBGRDPTR    0x1ffU
26289 #define M_PILADBGRDPTR    0x1ffU
26310 #define M_DEBUGSELH    0x1fU
26314 #define S_DEBUGSELL    0
26315 #define M_DEBUGSELL    0x1fU
26319 #define A_CIM_DEBUGSTS 0x7b74
26326 #define M_POLADBGWRPTR    0x1ffU
26330 #define S_PILADBGWRPTR    0
26331 #define M_PILADBGWRPTR    0x1ffU
26335 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
26336 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
26337 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
26338 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
26339 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
26340 #define A_CIM_MEM_ZONE0_VA 0x7b90
26343 #define M_MEM_ZONE_VA    0xfffffffU
26347 #define A_CIM_MEM_ZONE0_BA 0x7b94
26350 #define M_MEM_ZONE_BA    0x3ffffffU
26358 #define S_ZONE_DST    0
26359 #define M_ZONE_DST    0x3U
26364 #define M_THREAD_ID    0x7U
26368 #define A_CIM_MEM_ZONE0_LEN 0x7b98
26371 #define M_MEM_ZONE_LEN    0xfffffffU
26375 #define A_CIM_MEM_ZONE1_VA 0x7b9c
26376 #define A_CIM_MEM_ZONE1_BA 0x7ba0
26377 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
26378 #define A_CIM_MEM_ZONE2_VA 0x7ba8
26379 #define A_CIM_MEM_ZONE2_BA 0x7bac
26380 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
26381 #define A_CIM_MEM_ZONE3_VA 0x7bb4
26382 #define A_CIM_MEM_ZONE3_BA 0x7bb8
26383 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
26384 #define A_CIM_MEM_ZONE4_VA 0x7bc0
26385 #define A_CIM_MEM_ZONE4_BA 0x7bc4
26386 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
26387 #define A_CIM_MEM_ZONE5_VA 0x7bcc
26388 #define A_CIM_MEM_ZONE5_BA 0x7bd0
26389 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
26390 #define A_CIM_MEM_ZONE6_VA 0x7bd8
26391 #define A_CIM_MEM_ZONE6_BA 0x7bdc
26392 #define A_CIM_MEM_ZONE6_LEN 0x7be0
26393 #define A_CIM_MEM_ZONE7_VA 0x7be4
26394 #define A_CIM_MEM_ZONE7_BA 0x7be8
26395 #define A_CIM_MEM_ZONE7_LEN 0x7bec
26396 #define A_CIM_BOOT_LEN 0x7bf0
26399 #define M_BOOTLEN    0xfffffffU
26403 #define A_CIM_GLB_TIMER_CTL 0x7bf4
26417 #define A_CIM_GLB_TIMER 0x7bf8
26418 #define A_CIM_GLB_TIMER_TICK 0x7bfc
26420 #define S_GLBLTTICK    0
26421 #define M_GLBLTTICK    0xffffU
26425 #define A_CIM_TIMER0 0x7c00
26426 #define A_CIM_TIMER1 0x7c04
26427 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
26430 #define M_DADDRTIMEOUT    0x3fffffffU
26434 #define S_DADDRTIMEOUTTYPE    0
26435 #define M_DADDRTIMEOUTTYPE    0x3U
26439 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
26442 #define M_DADDRILLEGAL    0x3fffffffU
26446 #define S_DADDRILLEGALTYPE    0
26447 #define M_DADDRILLEGALTYPE    0x3U
26451 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
26453 #define S_DPIFHOSTMASK    0
26454 #define M_DPIFHOSTMASK    0x1fffffU
26458 #define S_T5_DPIFHOSTMASK    0
26459 #define M_T5_DPIFHOSTMASK    0x1fffffffU
26463 #define S_T6_T5_DPIFHOSTMASK    0
26464 #define M_T6_T5_DPIFHOSTMASK    0x3fffffffU
26468 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
26470 #define S_DPIFHUPAMASK    0
26471 #define M_DPIFHUPAMASK    0x7fffffffU
26475 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
26477 #define S_DUPMASK    0
26478 #define M_DUPMASK    0x1fffffU
26482 #define S_T5_DUPMASK    0
26483 #define M_T5_DUPMASK    0x1fffffffU
26487 #define S_T6_T5_DUPMASK    0
26488 #define M_T6_T5_DUPMASK    0x3fffffffU
26492 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
26494 #define S_DUPUACCMASK    0
26495 #define M_DUPUACCMASK    0x7fffffffU
26499 #define A_CIM_PERR_INJECT 0x7c20
26500 #define A_CIM_FPGA_ROM_EFUSE_CMD 0x7c20
26501 #define A_CIM_PERR_ENABLE 0x7c24
26503 #define S_PERREN    0
26504 #define M_PERREN    0x1fffffU
26508 #define S_T5_PERREN    0
26509 #define M_T5_PERREN    0x1fffffffU
26513 #define S_T6_T5_PERREN    0
26514 #define M_T6_T5_PERREN    0x3fffffffU
26518 #define A_CIM_FPGA_ROM_EFUSE_DATA 0x7c24
26519 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
26521 #define S_EEPROMBUSY    0
26525 #define A_CIM_MA_TIMER_EN 0x7c2c
26527 #define S_MA_TIMER_ENABLE    0
26551 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
26553 #define S_UP_PO_SINGLE_OUTSTANDING    0
26557 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
26558 #define A_CIM_UP_OPERATION_FREQ 0x7c38
26559 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
26562 #define M_CIM_ULP_TX_PKT_ERR_CODE    0xffU
26567 #define M_CIM_SGE1_PKT_ERR_CODE    0xffU
26571 #define S_CIM_SGE0_PKT_ERR_CODE    0
26572 #define M_CIM_SGE0_PKT_ERR_CODE    0xffU
26577 #define M_CIM_PCIE_PKT_ERR_CODE    0xffU
26581 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
26582 #define A_CIM_QUE_PERR_ADDR 0x7c40
26585 #define M_IBQPERRADDR    0xfffU
26589 #define S_OBQPERRADDR    0
26590 #define M_OBQPERRADDR    0xfffU
26594 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
26596 #define S_PIO_UP_MST_CFG_SEL    0
26600 #define A_CIM_CGEN 0x7c48
26602 #define S_TSCH_CGEN    0
26606 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
26624 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL    0
26633 #define M_ULP_OBQ_SIZE    0x3U
26638 #define M_TP_IBQ_SIZE    0x3U
26646 #define A_CIM_CGEN_GLOBAL 0x7c50
26648 #define S_CGEN_GLOBAL    0
26652 #define A_CIM_DPSLP_EN 0x7c54
26654 #define S_PIFDBGLA_DPSLP_EN    0
26658 #define A_CIM_GFT_CMM_CONFIG 0x7c58
26665 #define M_T7_WRCNTIDLE    0x7fffU
26669 #define A_CIM_GFT_CONFIG 0x7c5c
26672 #define M_GFTMABASE    0xffffU
26677 #define M_GFTHASHTBLSIZE    0xfU
26686 #define M_GFTMATHREADID    0x7U
26698 #define S_GFTTBLMODEEN    0
26702 #define A_CIM_TCAM_BIST_CTRL 0x7c60
26708 #define S_CB_START    0
26709 #define M_CB_START    0xfffffffU
26713 #define A_CIM_TCAM_BIST_CB_PASS 0x7c64
26715 #define S_CB_PASS    0
26716 #define M_CB_PASS    0xfffffffU
26720 #define A_CIM_TCAM_BIST_CB_BUSY 0x7c68
26722 #define S_CB_BUSY    0
26723 #define M_CB_BUSY    0xfffffffU
26727 #define A_CIM_GFT_MASK 0x7c70
26730 #define TP_BASE_ADDR 0x7d00
26732 #define A_TP_IN_CONFIG 0x7d00
26834 #define S_CTUNNEL    0
26898 #define S_CFASTDEMUXEN    0
26902 #define A_TP_OUT_CONFIG 0x7d04
26905 #define M_PORTQFCEN    0xfU
26989 #define S_CETHERNET    0
27029 #define A_TP_GLOBAL_CONFIG 0x7d08
27032 #define M_SYNCOOKIEPARAMS    0x3fU
27065 #define M_FIVETUPLELOOKUP    0x3U
27098 #define M_TCAMSERVERUSE    0x3U
27102 #define S_IPTTL    0
27103 #define M_IPTTL    0xffU
27124 #define M_RXSACKFWDMODE    0x3U
27144 #define A_TP_DB_CONFIG 0x7d0c
27147 #define M_DBMAXOPCNT    0xffU
27156 #define M_CXMAXOPCNT    0x7fU
27165 #define M_TXMAXOPCNT    0x7fU
27173 #define S_RXMAXOPCNT    0
27174 #define M_RXMAXOPCNT    0x7fU
27178 #define A_TP_CMM_TCB_BASE 0x7d10
27179 #define A_TP_CMM_MM_BASE 0x7d14
27180 #define A_TP_CMM_TIMER_BASE 0x7d18
27181 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
27184 #define M_RXPOOLSIZE    0xffffU
27188 #define S_TXPOOLSIZE    0
27189 #define M_TXPOOLSIZE    0xffffU
27193 #define A_TP_PMM_TX_BASE 0x7d20
27194 #define A_TP_PMM_DEFRAG_BASE 0x7d24
27195 #define A_TP_PMM_RX_BASE 0x7d28
27196 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
27197 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
27203 #define S_PMRXMAXPAGE    0
27204 #define M_PMRXMAXPAGE    0x1fffffU
27209 #define M_T7_PMRXNUMCHN    0x7U
27213 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
27214 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
27217 #define M_PMTXNUMCHN    0x3U
27221 #define S_PMTXMAXPAGE    0
27222 #define M_PMTXMAXPAGE    0x1fffffU
27227 #define M_T7_PMTXNUMCHN    0x7U
27231 #define A_TP_EXT_CONFIG 0x7d3c
27282 #define M_IPSECROCECRCMODE    0x3U
27298 #define S_IPSECCFG    0
27299 #define M_IPSECCFG    0x7U
27303 #define A_TP_TCP_OPTIONS 0x7d40
27306 #define M_MTUDEFAULT    0xffffU
27323 #define M_SACKMODE    0x3U
27328 #define M_WINDOWSCALEMODE    0x3U
27332 #define S_TIMESTAMPSMODE    0
27333 #define M_TIMESTAMPSMODE    0x3U
27337 #define A_TP_DACK_CONFIG 0x7d44
27340 #define M_AUTOSTATE3    0x3U
27345 #define M_AUTOSTATE2    0x3U
27350 #define M_AUTOSTATE1    0x3U
27355 #define M_BYTETHRESHOLD    0x3ffffU
27360 #define M_MSSTHRESHOLD    0x7U
27372 #define S_MODE    0
27376 #define A_TP_PC_CONFIG 0x7d48
27502 #define S_TXDATAACKPAGEENABLE    0
27522 #define A_TP_PC_CONFIG2 0x7d4c
27648 #define S_ENABLETNLOFDCLOSED    0
27656 #define A_TP_TCP_BACKOFF_REG0 0x7d50
27659 #define M_TIMERBACKOFFINDEX3    0xffU
27664 #define M_TIMERBACKOFFINDEX2    0xffU
27669 #define M_TIMERBACKOFFINDEX1    0xffU
27673 #define S_TIMERBACKOFFINDEX0    0
27674 #define M_TIMERBACKOFFINDEX0    0xffU
27678 #define A_TP_TCP_BACKOFF_REG1 0x7d54
27681 #define M_TIMERBACKOFFINDEX7    0xffU
27686 #define M_TIMERBACKOFFINDEX6    0xffU
27691 #define M_TIMERBACKOFFINDEX5    0xffU
27695 #define S_TIMERBACKOFFINDEX4    0
27696 #define M_TIMERBACKOFFINDEX4    0xffU
27700 #define A_TP_TCP_BACKOFF_REG2 0x7d58
27703 #define M_TIMERBACKOFFINDEX11    0xffU
27708 #define M_TIMERBACKOFFINDEX10    0xffU
27713 #define M_TIMERBACKOFFINDEX9    0xffU
27717 #define S_TIMERBACKOFFINDEX8    0
27718 #define M_TIMERBACKOFFINDEX8    0xffU
27722 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
27725 #define M_TIMERBACKOFFINDEX15    0xffU
27730 #define M_TIMERBACKOFFINDEX14    0xffU
27735 #define M_TIMERBACKOFFINDEX13    0xffU
27739 #define S_TIMERBACKOFFINDEX12    0
27740 #define M_TIMERBACKOFFINDEX12    0xffU
27744 #define A_TP_PARA_REG0 0x7d60
27751 #define M_INITCWND    0x7U
27756 #define M_DUPACKTHRESH    0xfU
27781 #define M_TSMPMODE    0x3U
27786 #define M_BYTECOUNTLIMIT    0x3U
27802 #define S_SWSTIMER    0
27807 #define M_LIMTXTHRESH    0xfU
27828 #define M_ECNTHRESH    0x3U
27844 #define A_TP_PARA_REG1 0x7d64
27847 #define M_INITRWND    0xffffU
27851 #define S_INITIALSSTHRESH    0
27852 #define M_INITIALSSTHRESH    0xffffU
27856 #define A_TP_PARA_REG2 0x7d68
27859 #define M_MAXRXDATA    0xffffU
27863 #define S_RXCOALESCESIZE    0
27864 #define M_RXCOALESCESIZE    0xffffU
27868 #define A_TP_PARA_REG3 0x7d6c
27919 #define M_TXDATAACKIDX    0xfU
27924 #define M_RXFRAGENABLE    0x7U
27961 #define M_CNGCTRLMODE    0x3U
27969 #define S_RXCOALESCEPSHEN    0
27973 #define A_TP_PARA_REG4 0x7d70
27976 #define M_HIGHSPEEDCFG    0xffU
27981 #define M_NEWRENOCFG    0xffU
27986 #define M_TAHOECFG    0xffU
27990 #define S_RENOCFG    0
27991 #define M_RENOCFG    0xffU
28004 #define M_OVERDRIVEHIGHSPEED    0x3U
28021 #define M_OVERDRIVENEWRENO    0x3U
28038 #define M_OVERDRIVETAHOE    0x3U
28055 #define M_OVERDRIVERENO    0x3U
28059 #define S_BYTECOUNTRENO    0
28063 #define A_TP_PARA_REG5 0x7d74
28066 #define M_INDICATESIZE    0xffffU
28071 #define M_MAXPROXYSIZE    0xfU
28107 #define S_PUSHTIMERENABLE    0
28131 #define A_TP_PARA_REG6 0x7d78
28134 #define M_TXPDUSIZEADJ    0xffU
28139 #define M_LIMITEDTRANSMIT    0xfU
28219 #define S_DISABLEPDUXMT    0
28235 #define A_TP_PARA_REG7 0x7d7c
28238 #define M_PMMAXXFERLEN1    0xffffU
28242 #define S_PMMAXXFERLEN0    0
28243 #define M_PMMAXXFERLEN0    0xffffU
28247 #define A_TP_ENG_CONFIG 0x7d80
28250 #define M_TABLELATENCYDONE    0xfU
28255 #define M_TABLELATENCYSTART    0xfU
28260 #define M_ENGINELATENCYDELTA    0xfU
28265 #define M_ENGINELATENCYMMGR    0xfU
28270 #define M_ENGINELATENCYWIREIP6    0xfU
28275 #define M_ENGINELATENCYWIRE    0xfU
28279 #define S_ENGINELATENCYBASE    0
28280 #define M_ENGINELATENCYBASE    0xfU
28284 #define A_TP_PARA_REG8 0x7d84
28294 #define S_ECNSYNECT    0
28298 #define A_TP_PARA_REG9 0x7d88
28301 #define M_PMMAXXFERLEN3    0xffffU
28305 #define S_PMMAXXFERLEN2    0
28306 #define M_PMMAXXFERLEN2    0xffffU
28310 #define A_TP_ERR_CONFIG 0x7d8c
28412 #define S_DROPERRORANY    0
28440 #define A_TP_TIMER_RESOLUTION 0x7d90
28443 #define M_TIMERRESOLUTION    0xffU
28448 #define M_TIMESTAMPRESOLUTION    0xffU
28452 #define S_DELAYEDACKRESOLUTION    0
28453 #define M_DELAYEDACKRESOLUTION    0xffU
28458 #define M_ROCETIMERRESOLUTION    0xffU
28462 #define A_TP_MSL 0x7d94
28464 #define S_MSL    0
28465 #define M_MSL    0x3fffffffU
28469 #define A_TP_RXT_MIN 0x7d98
28471 #define S_RXTMIN    0
28472 #define M_RXTMIN    0x3fffffffU
28476 #define A_TP_RXT_MAX 0x7d9c
28478 #define S_RXTMAX    0
28479 #define M_RXTMAX    0x3fffffffU
28483 #define A_TP_PERS_MIN 0x7da0
28485 #define S_PERSMIN    0
28486 #define M_PERSMIN    0x3fffffffU
28490 #define A_TP_PERS_MAX 0x7da4
28492 #define S_PERSMAX    0
28493 #define M_PERSMAX    0x3fffffffU
28497 #define A_TP_KEEP_IDLE 0x7da8
28499 #define S_KEEPALIVEIDLE    0
28500 #define M_KEEPALIVEIDLE    0x3fffffffU
28504 #define A_TP_KEEP_INTVL 0x7dac
28506 #define S_KEEPALIVEINTVL    0
28507 #define M_KEEPALIVEINTVL    0x3fffffffU
28511 #define A_TP_INIT_SRTT 0x7db0
28514 #define M_MAXRTT    0xffffU
28518 #define S_INITSRTT    0
28519 #define M_INITSRTT    0xffffU
28523 #define A_TP_DACK_TIMER 0x7db4
28525 #define S_DACKTIME    0
28526 #define M_DACKTIME    0xfffU
28530 #define A_TP_FINWAIT2_TIMER 0x7db8
28532 #define S_FINWAIT2TIME    0
28533 #define M_FINWAIT2TIME    0x3fffffffU
28537 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
28539 #define S_FASTFINWAIT2TIME    0
28540 #define M_FASTFINWAIT2TIME    0x3fffffffU
28544 #define A_TP_SHIFT_CNT 0x7dc0
28547 #define M_SYNSHIFTMAX    0xffU
28552 #define M_RXTSHIFTMAXR1    0xfU
28557 #define M_RXTSHIFTMAXR2    0xfU
28562 #define M_PERSHIFTBACKOFFMAX    0xfU
28567 #define M_PERSHIFTMAX    0xfU
28572 #define M_KEEPALIVEMAXR1    0xfU
28576 #define S_KEEPALIVEMAXR2    0
28577 #define M_KEEPALIVEMAXR2    0xfU
28582 #define M_T6_SYNSHIFTMAX    0xfU
28586 #define A_TP_TM_CONFIG 0x7dc4
28588 #define S_CMTIMERMAXNUM    0
28589 #define M_CMTIMERMAXNUM    0x7U
28593 #define A_TP_TIME_LO 0x7dc8
28594 #define A_TP_TIME_HI 0x7dcc
28595 #define A_TP_PORT_MTU_0 0x7dd0
28598 #define M_PORT1MTUVALUE    0xffffU
28602 #define S_PORT0MTUVALUE    0
28603 #define M_PORT0MTUVALUE    0xffffU
28607 #define A_TP_PORT_MTU_1 0x7dd4
28610 #define M_PORT3MTUVALUE    0xffffU
28614 #define S_PORT2MTUVALUE    0
28615 #define M_PORT2MTUVALUE    0xffffU
28619 #define A_TP_PACE_TABLE 0x7dd8
28620 #define A_TP_CCTRL_TABLE 0x7ddc
28623 #define M_ROWINDEX    0xffffU
28627 #define S_ROWVALUE    0
28628 #define M_ROWVALUE    0xffffU
28632 #define A_TP_MTU_TABLE 0x7de4
28635 #define M_MTUINDEX    0xffU
28640 #define M_MTUWIDTH    0xfU
28644 #define S_MTUVALUE    0
28645 #define M_MTUVALUE    0x3fffU
28649 #define A_TP_ULP_TABLE 0x7de8
28652 #define M_ULPTYPE7FIELD    0xfU
28657 #define M_ULPTYPE6FIELD    0xfU
28662 #define M_ULPTYPE5FIELD    0xfU
28667 #define M_ULPTYPE4FIELD    0xfU
28672 #define M_ULPTYPE3FIELD    0xfU
28677 #define M_ULPTYPE2FIELD    0xfU
28682 #define M_ULPTYPE1FIELD    0xfU
28686 #define S_ULPTYPE0FIELD    0
28687 #define M_ULPTYPE0FIELD    0xfU
28696 #define M_ULPTYPE7OFFSET    0x7U
28705 #define M_ULPTYPE6OFFSET    0x7U
28714 #define M_ULPTYPE5OFFSET    0x7U
28723 #define M_ULPTYPE4OFFSET    0x7U
28732 #define M_ULPTYPE3OFFSET    0x7U
28741 #define M_ULPTYPE2OFFSET    0x7U
28750 #define M_ULPTYPE1OFFSET    0x7U
28758 #define S_ULPTYPE0OFFSET    0
28759 #define M_ULPTYPE0OFFSET    0x7U
28763 #define A_TP_RSS_LKP_TABLE 0x7dec
28770 #define M_LKPTBLROWIDX    0x3ffU
28775 #define M_LKPTBLQUEUE1    0x3ffU
28779 #define S_LKPTBLQUEUE0    0
28780 #define M_LKPTBLQUEUE0    0x3ffU
28785 #define M_T6_LKPTBLROWIDX    0x7ffU
28789 #define A_TP_RSS_CONFIG 0x7df0
28899 #define S_DISABLE    0
28919 #define A_TP_RSS_CONFIG_TNL 0x7df4
28922 #define M_MASKSIZE    0xfU
28927 #define M_MASKFILTER    0x7ffU
28931 #define S_USEWIRECH    0
28943 #define A_TP_RSS_CONFIG_OFD 0x7df8
28950 #define M_RRCPLQUEWIDTH    0xfU
28955 #define M_FRMWRQUEMASK    0xfU
28967 #define A_TP_RSS_CONFIG_SYN 0x7dfc
28968 #define A_TP_RSS_CONFIG_VRT 0x7e00
28995 #define M_HASHDELAY    0xfU
29000 #define M_VFWRADDR    0x7fU
29005 #define M_KEYMODE    0x3U
29017 #define S_KEYWRADDR    0
29018 #define M_KEYWRADDR    0xfU
29031 #define M_KEYWRADDRX    0x3U
29040 #define M_T6_VFWRADDR    0xffU
29044 #define A_TP_RSS_CONFIG_CNG 0x7e04
29134 #define S_QUEUE    0
29135 #define M_QUEUE    0x3ffU
29163 #define S_T7_QUEUE    0
29164 #define M_T7_QUEUE    0x3fffU
29168 #define A_TP_RSS_CONFIG_4CH 0x7e08
29174 #define S_200GMODE    0
29178 #define A_TP_RSS_CONFIG_SRAM 0x7e0c
29193 #define M_SRAMSEL    0x3U
29197 #define S_SRAMADDR    0
29198 #define M_SRAMADDR    0x3fffU
29202 #define A_TP_LA_TABLE_0 0x7e10
29205 #define M_VIRTPORT1TABLE    0xffffU
29209 #define S_VIRTPORT0TABLE    0
29210 #define M_VIRTPORT0TABLE    0xffffU
29214 #define A_TP_LA_TABLE_1 0x7e14
29217 #define M_VIRTPORT3TABLE    0xffffU
29221 #define S_VIRTPORT2TABLE    0
29222 #define M_VIRTPORT2TABLE    0xffffU
29226 #define A_TP_TM_PIO_ADDR 0x7e18
29227 #define A_TP_TM_PIO_DATA 0x7e1c
29228 #define A_TP_RX_MOD_CONFIG_CH3_CH2 0x7e20
29231 #define M_RXCHANNELWEIGHT3    0xffU
29235 #define S_RXCHANNELWEIGHT2    0
29236 #define M_RXCHANNELWEIGHT2    0xffU
29240 #define A_TP_MOD_CONFIG 0x7e24
29243 #define M_RXCHANNELWEIGHT1    0xffU
29248 #define M_RXCHANNELWEIGHT0    0xffU
29253 #define M_TIMERMODE    0xffU
29257 #define S_TXCHANNELXOFFEN    0
29258 #define M_TXCHANNELXOFFEN    0xfU
29262 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
29265 #define M_RX_MOD_WEIGHT    0xffU
29270 #define M_TX_MOD_WEIGHT    0xffU
29274 #define S_TX_MOD_QUEUE_REQ_MAP    0
29275 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
29279 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
29282 #define M_TX_MODQ_WEIGHT7    0xffU
29287 #define M_TX_MODQ_WEIGHT6    0xffU
29292 #define M_TX_MODQ_WEIGHT5    0xffU
29296 #define S_TX_MODQ_WEIGHT4    0
29297 #define M_TX_MODQ_WEIGHT4    0xffU
29301 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
29304 #define M_TX_MODQ_WEIGHT3    0xffU
29309 #define M_TX_MODQ_WEIGHT2    0xffU
29314 #define M_TX_MODQ_WEIGHT1    0xffU
29318 #define S_TX_MODQ_WEIGHT0    0
29319 #define M_TX_MODQ_WEIGHT0    0xffU
29323 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
29324 #define A_TP_MOD_RATE_LIMIT 0x7e38
29327 #define M_RX_MOD_RATE_LIMIT_INC    0xffU
29332 #define M_RX_MOD_RATE_LIMIT_TICK    0xffU
29337 #define M_TX_MOD_RATE_LIMIT_INC    0xffU
29341 #define S_TX_MOD_RATE_LIMIT_TICK    0
29342 #define M_TX_MOD_RATE_LIMIT_TICK    0xffU
29346 #define A_TP_PIO_ADDR 0x7e40
29347 #define A_TP_PIO_DATA 0x7e44
29348 #define A_TP_RESET 0x7e4c
29354 #define S_TPRESET    0
29358 #define A_TP_MIB_INDEX 0x7e50
29359 #define A_TP_MIB_DATA 0x7e54
29360 #define A_TP_SYNC_TIME_HI 0x7e58
29361 #define A_TP_SYNC_TIME_LO 0x7e5c
29362 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
29363 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
29364 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
29365 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
29367 #define S_CMMAXPSTRUCT    0
29368 #define M_CMMAXPSTRUCT    0x1fffffU
29372 #define A_TP_INT_ENABLE 0x7e70
29494 #define S_DELINVFIFOPERR    0
29526 #define S_TPCPERR    0
29530 #define A_TP_INT_CAUSE 0x7e74
29531 #define A_TP_PER_ENABLE 0x7e78
29532 #define A_TP_FLM_FREE_PS_CNT 0x7e80
29534 #define S_FREEPSTRUCTCOUNT    0
29535 #define M_FREEPSTRUCTCOUNT    0x1fffffU
29539 #define A_TP_FLM_FREE_RX_CNT 0x7e84
29545 #define S_FREERXPAGECOUNT    0
29546 #define M_FREERXPAGECOUNT    0x1fffffU
29551 #define M_T7_FREERXPAGECHN    0x7U
29555 #define A_TP_FLM_FREE_TX_CNT 0x7e88
29558 #define M_FREETXPAGECHN    0x3U
29562 #define S_FREETXPAGECOUNT    0
29563 #define M_FREETXPAGECOUNT    0x1fffffU
29568 #define M_T7_FREETXPAGECHN    0x7U
29572 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
29573 #define A_TP_TM_HEAP_POP_CNT 0x7e90
29574 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
29575 #define A_TP_TM_DACK_POP_CNT 0x7e98
29576 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
29577 #define A_TP_MOD_POP_CNT 0x7ea0
29578 #define A_TP_TIMER_SEPARATOR 0x7ea4
29581 #define M_TIMERSEPARATOR    0xffffU
29585 #define S_DISABLETIMEFREEZE    0
29589 #define A_TP_STAMP_TIME 0x7ea8
29590 #define A_TP_DEBUG_FLAGS 0x7eac
29680 #define S_TXRCVADVLTMSS    0
29696 #define A_TP_RX_SCHED 0x7eb0
29715 #define M_ENABLELPBKFULL1    0x3U
29720 #define M_ENABLELPBKFULL0    0x3U
29725 #define M_ENABLEFIFOFULL1    0x3U
29730 #define M_ENABLEPCMDFULL1    0x3U
29735 #define M_ENABLEHDRFULL1    0x3U
29740 #define M_ENABLEFIFOFULL0    0x3U
29745 #define M_ENABLEPCMDFULL0    0x3U
29750 #define M_ENABLEHDRFULL0    0x3U
29755 #define M_COMMITLIMIT1    0x3fU
29759 #define S_COMMITLIMIT0    0
29760 #define M_COMMITLIMIT0    0x3fU
29792 #define S_T7_RXFORCECONG0    0
29796 #define A_TP_TX_SCHED 0x7eb4
29831 #define M_COMMITLIMIT3    0x3fU
29836 #define M_COMMITLIMIT2    0x3fU
29840 #define A_TP_FX_SCHED 0x7eb8
29910 #define S_RXMODXOFF0    0
29922 #define A_TP_TX_ORATE 0x7ebc
29925 #define M_OFDRATE3    0xffU
29930 #define M_OFDRATE2    0xffU
29935 #define M_OFDRATE1    0xffU
29939 #define S_OFDRATE0    0
29940 #define M_OFDRATE0    0xffU
29944 #define A_TP_IX_SCHED0 0x7ec0
29945 #define A_TP_IX_SCHED1 0x7ec4
29946 #define A_TP_IX_SCHED2 0x7ec8
29947 #define A_TP_IX_SCHED3 0x7ecc
29948 #define A_TP_TX_TRATE 0x7ed0
29951 #define M_TNLRATE3    0xffU
29956 #define M_TNLRATE2    0xffU
29961 #define M_TNLRATE1    0xffU
29965 #define S_TNLRATE0    0
29966 #define M_TNLRATE0    0xffU
29970 #define A_TP_DBG_LA_CONFIG 0x7ed4
29973 #define M_DBGLAOPCENABLE    0xffU
29982 #define M_DBGLAWPTR    0x7fU
29987 #define M_DBGLAMODE    0x3U
29999 #define S_DBGLARPTR    0
30000 #define M_DBGLARPTR    0x7fU
30004 #define A_TP_DBG_LA_DATAL 0x7ed8
30005 #define A_TP_DBG_LA_DATAH 0x7edc
30006 #define A_TP_DBG_LA_FILTER 0x7ee0
30009 #define M_FILTERTID    0xfffffU
30033 #define S_ENE    0
30037 #define A_TP_PROTOCOL_CNTRL 0x7ee8
30048 #define M_BLOCKSELECT    0x3U
30053 #define M_LINEADDRESS    0x7fU
30057 #define S_REQUESTDONE    0
30061 #define A_TP_PROTOCOL_DATA0 0x7eec
30062 #define A_TP_PROTOCOL_DATA1 0x7ef0
30063 #define A_TP_PROTOCOL_DATA2 0x7ef4
30064 #define A_TP_PROTOCOL_DATA3 0x7ef8
30065 #define A_TP_PROTOCOL_DATA4 0x7efc
30067 #define S_PROTOCOLDATAFIELD    0
30068 #define M_PROTOCOLDATAFIELD    0xfU
30072 #define A_TP_INIC_CTRL0 0x7f00
30073 #define A_TP_INIC_DBG 0x7f04
30074 #define A_TP_INIC_PERR_ENABLE 0x7f08
30077 #define M_INICMAC1_ERR    0x3fU
30081 #define S_INICMAC0_ERR    0
30082 #define M_INICMAC0_ERR    0x3fU
30086 #define A_TP_INIC_PERR_CAUSE 0x7f0c
30087 #define A_TP_PARA_REG10 0x7f20
30094 #define M_IWARPMAXPDULEN    0xfU
30098 #define S_TLSMAXRXDATA    0
30099 #define M_TLSMAXRXDATA    0xffffU
30103 #define A_TP_TCAM_BIST_CTRL 0x7f24
30104 #define A_TP_TCAM_BIST_CB_PASS 0x7f28
30105 #define A_TP_TCAM_BIST_CB_BUSY 0x7f2c
30106 #define A_TP_C_PERR_ENABLE 0x7f30
30212 #define S_LBKDATAFIFO    0
30216 #define A_TP_C_PERR_CAUSE 0x7f34
30217 #define A_TP_E_EG_PERR_ENABLE 0x7f38
30319 #define S_DISPCPL5FIFO0    0
30323 #define A_TP_E_EG_PERR_CAUSE 0x7f3c
30324 #define A_TP_E_IN0_PERR_ENABLE 0x7f40
30430 #define S_MPS2TPINTF0    0
30434 #define A_TP_E_IN0_PERR_CAUSE 0x7f44
30435 #define A_TP_E_IN1_PERR_ENABLE 0x7f48
30513 #define S_MPS2TPINTF2    0
30517 #define A_TP_E_IN1_PERR_CAUSE 0x7f4c
30518 #define A_TP_O_PERR_ENABLE 0x7f50
30596 #define S_ARPIPSECSRAM0    0
30600 #define A_TP_O_PERR_CAUSE 0x7f54
30601 #define A_TP_CERR_ENABLE 0x7f58
30611 #define A_TP_CERR_CAUSE 0x7f5c
30612 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
30615 #define M_TXTIMERSEPQ7    0xffffU
30619 #define S_TXTIMERSEPQ6    0
30620 #define M_TXTIMERSEPQ6    0xffffU
30624 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
30627 #define M_TXTIMERSEPQ5    0xffffU
30631 #define S_TXTIMERSEPQ4    0
30632 #define M_TXTIMERSEPQ4    0xffffU
30636 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
30639 #define M_TXTIMERSEPQ3    0xffffU
30643 #define S_TXTIMERSEPQ2    0
30644 #define M_TXTIMERSEPQ2    0xffffU
30648 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
30651 #define M_TXTIMERSEPQ1    0xffffU
30655 #define S_TXTIMERSEPQ0    0
30656 #define M_TXTIMERSEPQ0    0xffffU
30660 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
30663 #define M_RXTIMERSEPQ1    0xffffU
30667 #define S_RXTIMERSEPQ0    0
30668 #define M_RXTIMERSEPQ0    0xffffU
30672 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
30675 #define M_TXRATEINCQ7    0xffU
30680 #define M_TXRATETCKQ7    0xffU
30685 #define M_TXRATEINCQ6    0xffU
30689 #define S_TXRATETCKQ6    0
30690 #define M_TXRATETCKQ6    0xffU
30694 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
30697 #define M_TXRATEINCQ5    0xffU
30702 #define M_TXRATETCKQ5    0xffU
30707 #define M_TXRATEINCQ4    0xffU
30711 #define S_TXRATETCKQ4    0
30712 #define M_TXRATETCKQ4    0xffU
30716 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
30719 #define M_TXRATEINCQ3    0xffU
30724 #define M_TXRATETCKQ3    0xffU
30729 #define M_TXRATEINCQ2    0xffU
30733 #define S_TXRATETCKQ2    0
30734 #define M_TXRATETCKQ2    0xffU
30738 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
30741 #define M_TXRATEINCQ1    0xffU
30746 #define M_TXRATETCKQ1    0xffU
30751 #define M_TXRATEINCQ0    0xffU
30755 #define S_TXRATETCKQ0    0
30756 #define M_TXRATETCKQ0    0xffU
30760 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
30763 #define M_RXRATEINCQ1    0xffU
30768 #define M_RXRATETCKQ1    0xffU
30773 #define M_RXRATEINCQ0    0xffU
30777 #define S_RXRATETCKQ0    0
30778 #define M_RXRATETCKQ0    0xffU
30782 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
30783 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
30784 #define A_TP_RX_MOD_Q3_Q2_TIMER_SEPARATOR 0xc
30787 #define M_RXTIMERSEPQ3    0xffffU
30791 #define S_RXTIMERSEPQ2    0
30792 #define M_RXTIMERSEPQ2    0xffffU
30796 #define A_TP_RX_MOD_Q3_Q2_RATE_LIMIT 0xd
30799 #define M_RXRATEINCQ3    0xffU
30804 #define M_RXRATETCKQ3    0xffU
30809 #define M_RXRATEINCQ2    0xffU
30813 #define S_RXRATETCKQ2    0
30814 #define M_RXRATETCKQ2    0xffU
30818 #define A_TP_RX_LPBK_CONG 0x1c
30819 #define A_TP_RX_SCHED_MOD 0x1d
30822 #define M_T7_ENABLELPBKFULL1    0xfU
30827 #define M_T7_ENABLEFIFOFULL1    0xfU
30832 #define M_T7_ENABLEPCMDFULL1    0xfU
30837 #define M_T7_ENABLEHDRFULL1    0xfU
30842 #define M_T7_ENABLELPBKFULL0    0xfU
30847 #define M_T7_ENABLEFIFOFULL0    0xfU
30852 #define M_T7_ENABLEPCMDFULL0    0xfU
30856 #define S_T7_ENABLEHDRFULL0    0
30857 #define M_T7_ENABLEHDRFULL0    0xfU
30861 #define A_TP_RX_SCHED_MOD_CH3_CH2 0x1e
30864 #define M_ENABLELPBKFULL3    0xfU
30869 #define M_ENABLEFIFOFULL3    0xfU
30874 #define M_ENABLEPCMDFULL3    0xfU
30879 #define M_ENABLEHDRFULL3    0xfU
30884 #define M_ENABLELPBKFULL2    0xfU
30889 #define M_ENABLEFIFOFULL2    0xfU
30894 #define M_ENABLEPCMDFULL2    0xfU
30898 #define S_ENABLEHDRFULL2    0
30899 #define M_ENABLEHDRFULL2    0xfU
30903 #define A_TP_RX_SCHED_MAP_CH3_CH2 0x1f
30906 #define M_T7_RXMAPCHANNEL3    0xffffU
30910 #define S_T7_RXMAPCHANNEL2    0
30911 #define M_T7_RXMAPCHANNEL2    0xffffU
30915 #define A_TP_RX_SCHED_MAP 0x20
30918 #define M_RXMAPCHANNEL3    0xffU
30923 #define M_RXMAPCHANNEL2    0xffU
30928 #define M_RXMAPCHANNEL1    0xffU
30932 #define S_RXMAPCHANNEL0    0
30933 #define M_RXMAPCHANNEL0    0xffU
30938 #define M_T7_RXMAPCHANNEL1    0xffffU
30942 #define S_T7_RXMAPCHANNEL0    0
30943 #define M_T7_RXMAPCHANNEL0    0xffffU
30947 #define A_TP_RX_SCHED_SGE 0x21
30950 #define M_RXSGEMOD1    0xfU
30955 #define M_RXSGEMOD0    0xfU
30971 #define S_RXSGECHANNEL0    0
30976 #define M_RXSGEMOD3    0xfU
30981 #define M_RXSGEMOD2    0xfU
30985 #define A_TP_TX_SCHED_MAP 0x22
30988 #define M_TXMAPCHANNEL3    0xfU
30993 #define M_TXMAPCHANNEL2    0xfU
30998 #define M_TXMAPCHANNEL1    0xfU
31002 #define S_TXMAPCHANNEL0    0
31003 #define M_TXMAPCHANNEL0    0xfU
31023 #define A_TP_TX_SCHED_HDR 0x23
31026 #define M_TXMAPHDRCHANNEL7    0xfU
31031 #define M_TXMAPHDRCHANNEL6    0xfU
31036 #define M_TXMAPHDRCHANNEL5    0xfU
31041 #define M_TXMAPHDRCHANNEL4    0xfU
31046 #define M_TXMAPHDRCHANNEL3    0xfU
31051 #define M_TXMAPHDRCHANNEL2    0xfU
31056 #define M_TXMAPHDRCHANNEL1    0xfU
31060 #define S_TXMAPHDRCHANNEL0    0
31061 #define M_TXMAPHDRCHANNEL0    0xfU
31065 #define A_TP_TX_SCHED_FIFO 0x24
31068 #define M_TXMAPFIFOCHANNEL7    0xfU
31073 #define M_TXMAPFIFOCHANNEL6    0xfU
31078 #define M_TXMAPFIFOCHANNEL5    0xfU
31083 #define M_TXMAPFIFOCHANNEL4    0xfU
31088 #define M_TXMAPFIFOCHANNEL3    0xfU
31093 #define M_TXMAPFIFOCHANNEL2    0xfU
31098 #define M_TXMAPFIFOCHANNEL1    0xfU
31102 #define S_TXMAPFIFOCHANNEL0    0
31103 #define M_TXMAPFIFOCHANNEL0    0xfU
31107 #define A_TP_TX_SCHED_PCMD 0x25
31110 #define M_TXMAPPCMDCHANNEL7    0xfU
31115 #define M_TXMAPPCMDCHANNEL6    0xfU
31120 #define M_TXMAPPCMDCHANNEL5    0xfU
31125 #define M_TXMAPPCMDCHANNEL4    0xfU
31130 #define M_TXMAPPCMDCHANNEL3    0xfU
31135 #define M_TXMAPPCMDCHANNEL2    0xfU
31140 #define M_TXMAPPCMDCHANNEL1    0xfU
31144 #define S_TXMAPPCMDCHANNEL0    0
31145 #define M_TXMAPPCMDCHANNEL0    0xfU
31149 #define A_TP_TX_SCHED_LPBK 0x26
31152 #define M_TXMAPLPBKCHANNEL7    0xfU
31157 #define M_TXMAPLPBKCHANNEL6    0xfU
31162 #define M_TXMAPLPBKCHANNEL5    0xfU
31167 #define M_TXMAPLPBKCHANNEL4    0xfU
31172 #define M_TXMAPLPBKCHANNEL3    0xfU
31177 #define M_TXMAPLPBKCHANNEL2    0xfU
31182 #define M_TXMAPLPBKCHANNEL1    0xfU
31186 #define S_TXMAPLPBKCHANNEL0    0
31187 #define M_TXMAPLPBKCHANNEL0    0xfU
31191 #define A_TP_CHANNEL_MAP 0x27
31194 #define M_RXMAPCHANNELELN    0xfU
31199 #define M_RXMAPE2LCHANNEL3    0x3U
31204 #define M_RXMAPE2LCHANNEL2    0x3U
31209 #define M_RXMAPE2LCHANNEL1    0x3U
31214 #define M_RXMAPE2LCHANNEL0    0x3U
31246 #define S_RXMAPE2CCHANNEL0    0
31251 #define M_T7_LB_MODE    0x3U
31256 #define M_ING_LB_MODE    0x3U
31261 #define M_RXC_LB_MODE    0x3U
31274 #define M_T7_RXMAPC2CCHANNEL3    0x7U
31279 #define M_T7_RXMAPC2CCHANNEL2    0x7U
31284 #define M_T7_RXMAPC2CCHANNEL1    0x7U
31289 #define M_T7_RXMAPC2CCHANNEL0    0x7U
31294 #define M_T7_RXMAPE2CCHANNEL3    0x7U
31299 #define M_T7_RXMAPE2CCHANNEL2    0x7U
31304 #define M_T7_RXMAPE2CCHANNEL1    0x7U
31308 #define S_T7_RXMAPE2CCHANNEL0    0
31309 #define M_T7_RXMAPE2CCHANNEL0    0x7U
31313 #define A_TP_RX_LPBK 0x28
31314 #define A_TP_TX_LPBK 0x29
31315 #define A_TP_TX_SCHED_PPP 0x2a
31318 #define M_TXPPPENPORT3    0xffU
31323 #define M_TXPPPENPORT2    0xffU
31328 #define M_TXPPPENPORT1    0xffU
31332 #define S_TXPPPENPORT0    0
31333 #define M_TXPPPENPORT0    0xffU
31337 #define A_TP_RX_SCHED_FIFO 0x2b
31340 #define M_COMMITLIMIT1H    0xffU
31345 #define M_COMMITLIMIT1L    0xffU
31350 #define M_COMMITLIMIT0H    0xffU
31354 #define S_COMMITLIMIT0L    0
31355 #define M_COMMITLIMIT0L    0xffU
31359 #define A_TP_RX_SCHED_FIFO_CH3_CH2 0x2c
31362 #define M_COMMITLIMIT3H    0xffU
31367 #define M_COMMITLIMIT3L    0xffU
31372 #define M_COMMITLIMIT2H    0xffU
31376 #define S_COMMITLIMIT2L    0
31377 #define M_COMMITLIMIT2L    0xffU
31381 #define A_TP_CHANNEL_MAP_LPBK 0x2d
31384 #define M_T7_RXMAPCHANNELELN    0xfU
31389 #define M_T7_RXMAPE2LCHANNEL3    0x7U
31394 #define M_T7_RXMAPE2LCHANNEL2    0x7U
31399 #define M_T7_RXMAPE2LCHANNEL1    0x7U
31403 #define S_T7_RXMAPE2LCHANNEL0    0
31404 #define M_T7_RXMAPE2LCHANNEL0    0x7U
31408 #define A_TP_IPMI_CFG1 0x2e
31426 #define S_IPMI_VLAN    0
31427 #define M_IPMI_VLAN    0xffffU
31431 #define A_TP_IPMI_CFG2 0x2f
31434 #define M_SECUREPORT    0xffffU
31438 #define S_PRIMARYPORT    0
31439 #define M_PRIMARYPORT    0xffffU
31443 #define A_TP_RSS_PF0_CONFIG 0x30
31478 #define M_IVFWIDTH    0xfU
31483 #define M_CH1DEFAULTQUEUE    0x3ffU
31487 #define S_CH0DEFAULTQUEUE    0
31488 #define M_CH0DEFAULTQUEUE    0x3ffU
31500 #define A_TP_RSS_PF1_CONFIG 0x31
31501 #define A_TP_RSS_PF2_CONFIG 0x32
31502 #define A_TP_RSS_PF3_CONFIG 0x33
31503 #define A_TP_RSS_PF4_CONFIG 0x34
31504 #define A_TP_RSS_PF5_CONFIG 0x35
31505 #define A_TP_RSS_PF6_CONFIG 0x36
31506 #define A_TP_RSS_PF7_CONFIG 0x37
31507 #define A_TP_RSS_PF_MAP 0x38
31510 #define M_LKPIDXSIZE    0x3U
31515 #define M_PF7LKPIDX    0x7U
31520 #define M_PF6LKPIDX    0x7U
31525 #define M_PF5LKPIDX    0x7U
31530 #define M_PF4LKPIDX    0x7U
31535 #define M_PF3LKPIDX    0x7U
31540 #define M_PF2LKPIDX    0x7U
31545 #define M_PF1LKPIDX    0x7U
31549 #define S_PF0LKPIDX    0
31550 #define M_PF0LKPIDX    0x7U
31554 #define A_TP_RSS_PF_MSK 0x39
31557 #define M_PF7MSKSIZE    0xfU
31562 #define M_PF6MSKSIZE    0xfU
31567 #define M_PF5MSKSIZE    0xfU
31572 #define M_PF4MSKSIZE    0xfU
31577 #define M_PF3MSKSIZE    0xfU
31582 #define M_PF2MSKSIZE    0xfU
31587 #define M_PF1MSKSIZE    0xfU
31591 #define S_PF0MSKSIZE    0
31592 #define M_PF0MSKSIZE    0xfU
31596 #define A_TP_RSS_VFL_CONFIG 0x3a
31599 #define M_BASEQID    0xfffU
31604 #define M_MAXRRQID    0xffU
31608 #define S_RRCOUNTER    0
31609 #define M_RRCOUNTER    0xffU
31613 #define A_TP_RSS_VFH_CONFIG 0x3b
31636 #define M_DEFAULTQUEUE    0x3ffU
31641 #define M_VFLKPIDX    0xffU
31661 #define S_KEYINDEX    0
31662 #define M_KEYINDEX    0xfU
31670 #define A_TP_RSS_SECRET_KEY0 0x40
31671 #define A_TP_RSS_SECRET_KEY1 0x41
31672 #define A_TP_RSS_SECRET_KEY2 0x42
31673 #define A_TP_RSS_SECRET_KEY3 0x43
31674 #define A_TP_RSS_SECRET_KEY4 0x44
31675 #define A_TP_RSS_SECRET_KEY5 0x45
31676 #define A_TP_RSS_SECRET_KEY6 0x46
31677 #define A_TP_RSS_SECRET_KEY7 0x47
31678 #define A_TP_RSS_SECRET_KEY8 0x48
31679 #define A_TP_RSS_SECRET_KEY9 0x49
31680 #define A_TP_ETHER_TYPE_VL 0x50
31683 #define M_CQFCTYPE    0xffffU
31687 #define S_VLANTYPE    0
31688 #define M_VLANTYPE    0xffffU
31692 #define A_TP_ETHER_TYPE_IP 0x51
31695 #define M_IPV6TYPE    0xffffU
31699 #define S_IPV4TYPE    0
31700 #define M_IPV4TYPE    0xffffU
31704 #define A_TP_ETHER_TYPE_FW 0x52
31707 #define M_ETHTYPE1    0xffffU
31711 #define S_ETHTYPE0    0
31712 #define M_ETHTYPE0    0xffffU
31716 #define A_TP_VXLAN_HEADER 0x53
31718 #define S_VXLANPORT    0
31719 #define M_VXLANPORT    0xffffU
31723 #define A_TP_CORE_POWER 0x54
31761 #define S_SLEEPREQRSS    0
31765 #define A_TP_CORE_RDMA 0x55
31768 #define M_IMMEDIATEOP    0xfU
31773 #define M_IMMEDIATESE    0xfU
31778 #define M_ATOMICREQOP    0xfU
31783 #define M_ATOMICRSPOP    0xfU
31791 #define S_IMMEDIATEEN    0
31804 #define M_VERIFYRSPOP    0x1fU
31809 #define M_VERIFYREQOP    0x1fU
31814 #define M_AWRITERSPOP    0x1fU
31819 #define M_AWRITEREQOP    0x1fU
31824 #define M_FLUSHRSPOP    0x1fU
31828 #define S_FLUSHREQOP    0
31829 #define M_FLUSHREQOP    0x1fU
31833 #define A_TP_FRAG_CONFIG 0x56
31836 #define M_TLSMODE    0x3U
31841 #define M_USERMODE    0x3U
31846 #define M_FCOEMODE    0x3U
31851 #define M_IANDPMODE    0x3U
31856 #define M_RDDPMODE    0x3U
31861 #define M_IWARPMODE    0x3U
31866 #define M_ISCSIMODE    0x3U
31871 #define M_DDPMODE    0x3U
31875 #define S_PASSMODE    0
31876 #define M_PASSMODE    0x3U
31881 #define M_NVMTMODE    0x3U
31886 #define M_ROCEMODE    0x3U
31891 #define M_DTLSMODE    0x3U
31895 #define A_TP_CMM_CONFIG 0x57
31898 #define M_WRCNTIDLE    0xffffU
31903 #define M_RDTHRESHOLD    0x3fU
31919 #define S_WRTHRTHRESH    0
31920 #define M_WRTHRTHRESH    0x1fU
31924 #define A_TP_VXLAN_CONFIG 0x58
31927 #define M_VXLANFLAGS    0xffffU
31931 #define S_VXLANTYPE    0
31932 #define M_VXLANTYPE    0xffffU
31936 #define A_TP_NVGRE_CONFIG 0x59
31939 #define M_GREFLAGS    0xffffU
31943 #define S_GRETYPE    0
31944 #define M_GRETYPE    0xffffU
31948 #define A_TP_MMGR_CMM_CONFIG 0x5a
31949 #define A_TP_DBG_CLEAR 0x60
31950 #define A_TP_DBG_CORE_HDR0 0x61
32016 #define S_E_TCP_OPT_RXVALID    0
32020 #define A_TP_DBG_CORE_HDR1 0x62
32046 #define S_E_TCP_OPT_RXFULL    0
32050 #define A_TP_DBG_CORE_FATAL 0x63
32069 #define M_CPCMDCONG    0xfU
32074 #define M_EPCMDCONG    0x3U
32087 #define M_CPCMDVALID    0xfU
32092 #define M_CPCMDAFULL    0xfU
32097 #define M_EPCMDVALID    0x3U
32102 #define M_EPCMDAFULL    0x3U
32115 #define M_CNONZEROPPOPCNT    0x3U
32119 #define S_CPCMDEOICNT    0
32120 #define M_CPCMDEOICNT    0x3U
32132 #define A_TP_DBG_CORE_OUT 0x64
32218 #define S_EPLDTXZEROPDRDY    0
32262 #define A_TP_DBG_CORE_TID 0x65
32265 #define M_LINENUMBER    0x7fU
32277 #define S_TIDVALUE    0
32278 #define M_TIDVALUE    0xfffffU
32283 #define M_SRC    0x3U
32287 #define A_TP_DBG_ENG_RES0 0x66
32306 #define M_RCFOPSRCOUT    0x3U
32319 #define M_RCFOPCODEOUT    0xfU
32324 #define M_EFFRCFOPCODEOUT    0xfU
32388 #define S_ETXBUSY    0
32393 #define M_EFFOPCODEOUT    0xfU
32405 #define S_T5_EPCMDBUSY    0
32409 #define A_TP_DBG_ENG_RES1 0x67
32428 #define M_CPLCMDIN    0xffU
32449 #define M_TABLEACCESSLATENCY    0xfU
32470 #define M_ENGINESTATE    0x3U
32494 #define S_RCFDATACMRDY    0
32502 #define A_TP_DBG_ENG_RES2 0x68
32505 #define M_CPLCMDRAW    0xffU
32510 #define M_RXMACPORT    0xfU
32515 #define M_TXECHANNEL    0x3U
32520 #define M_RXECHANNEL    0x3U
32557 #define M_RXPSTRUCTSFULL    0x3U
32562 #define M_RXPAGEPOOLFULL    0x3U
32566 #define S_RCFREASONOUT    0
32567 #define M_RCFREASONOUT    0xfU
32571 #define A_TP_DBG_CORE_PCMD 0x69
32574 #define M_CPCMDEOPCNT    0x3U
32579 #define M_CPCMDLENSAVE    0x3fffU
32584 #define M_EPCMDEOPCNT    0x3U
32588 #define S_EPCMDLENSAVE    0
32589 #define M_EPCMDLENSAVE    0x3fffU
32593 #define A_TP_DBG_SCHED_TX 0x6a
32596 #define M_TXCHNXOFF    0xfU
32601 #define M_TXFIFOCNG    0xfU
32606 #define M_TXPCMDCNG    0xfU
32611 #define M_TXLPBKCNG    0xfU
32616 #define M_TXHDRCNG    0xffU
32620 #define S_TXMODXOFF    0
32621 #define M_TXMODXOFF    0xffU
32625 #define A_TP_DBG_SCHED_RX 0x6b
32628 #define M_RXCHNXOFF    0xfU
32633 #define M_RXSGECNG    0xfU
32638 #define M_RXFIFOCNG    0x3U
32643 #define M_RXPCMDCNG    0x3U
32648 #define M_RXLPBKCNG    0xfU
32653 #define M_RXHDRCNG    0xfU
32657 #define S_RXMODXOFF    0
32658 #define M_RXMODXOFF    0x3U
32663 #define M_T5_RXFIFOCNG    0xfU
32668 #define M_T5_RXPCMDCNG    0x3U
32672 #define A_TP_DBG_ERROR_CNT 0x6c
32673 #define A_TP_DBG_CORE_CPL 0x6d
32676 #define M_CPLCMDOUT3    0xffU
32681 #define M_CPLCMDOUT2    0xffU
32686 #define M_CPLCMDOUT1    0xffU
32690 #define S_CPLCMDOUT0    0
32691 #define M_CPLCMDOUT0    0xffU
32695 #define A_TP_MIB_DEBUG 0x6f
32702 #define M_LINENUM3    0x7fU
32711 #define M_LINENUM2    0x7fU
32720 #define M_LINENUM1    0x7fU
32728 #define S_LINENUM0    0
32729 #define M_LINENUM0    0x7fU
32733 #define A_TP_DBG_CACHE_WR_ALL 0x70
32734 #define A_TP_DBG_CACHE_WR_HIT 0x71
32735 #define A_TP_DBG_CACHE_RD_ALL 0x72
32736 #define A_TP_DBG_CACHE_RD_HIT 0x73
32737 #define A_TP_DBG_CACHE_MC_REQ 0x74
32738 #define A_TP_DBG_CACHE_MC_RSP 0x75
32739 #define A_TP_RSS_PF0_CONFIG_CH3_CH2 0x80
32754 #define M_CH3DEFAULTQUEUE    0x3ffU
32758 #define S_CH2DEFAULTQUEUE    0
32759 #define M_CH2DEFAULTQUEUE    0x3ffU
32763 #define A_TP_RSS_PF1_CONFIG_CH3_CH2 0x81
32764 #define A_TP_RSS_PF2_CONFIG_CH3_CH2 0x82
32765 #define A_TP_RSS_PF3_CONFIG_CH3_CH2 0x83
32766 #define A_TP_RSS_PF4_CONFIG_CH3_CH2 0x84
32767 #define A_TP_RSS_PF5_CONFIG_CH3_CH2 0x85
32768 #define A_TP_RSS_PF6_CONFIG_CH3_CH2 0x86
32769 #define A_TP_RSS_PF7_CONFIG_CH3_CH2 0x87
32770 #define A_TP_RSS_PF0_EXT_CONFIG 0x88
32771 #define A_TP_RSS_PF1_EXT_CONFIG 0x89
32772 #define A_TP_RSS_PF2_EXT_CONFIG 0x8a
32773 #define A_TP_RSS_PF3_EXT_CONFIG 0x8b
32774 #define A_TP_RSS_PF4_EXT_CONFIG 0x8c
32775 #define A_TP_RSS_PF5_EXT_CONFIG 0x8d
32776 #define A_TP_RSS_PF6_EXT_CONFIG 0x8e
32777 #define A_TP_RSS_PF7_EXT_CONFIG 0x8f
32778 #define A_TP_ROCE_CONFIG 0x90
32793 #define M_ACKINTGENCTRL    0x3U
32841 #define S_DROPERRORTVER    0
32845 #define A_TP_NVMT_CONFIG 0x91
32855 #define S_STRIPHCRC    0
32859 #define A_TP_NVMT_MAXHDR 0x92
32862 #define M_MAXHDR3    0xffU
32867 #define M_MAXHDR2    0xffU
32872 #define M_MAXHDR1    0xffU
32876 #define S_MAXHDR0    0
32877 #define M_MAXHDR0    0xffU
32881 #define A_TP_NVMT_PDORSVD 0x93
32884 #define M_PDORSVD3    0xffU
32889 #define M_PDORSVD2    0xffU
32894 #define M_PDORSVD1    0xffU
32898 #define S_PDORSVD0    0
32899 #define M_PDORSVD0    0xffU
32903 #define A_TP_RDMA_CONFIG 0x94
32910 #define M_SNDIMMSEOP    0x1fU
32915 #define M_SNDIMMOP    0x1fU
32931 #define S_XRCEN    0
32935 #define A_TP_ROCE_RRQ_BASE 0x95
32936 #define A_TP_FILTER_RATE_CFG 0x96
32951 #define M_GRP_CFG_SEL    0xfffU
32955 #define S_US_TIMER_TICK    0
32956 #define M_US_TIMER_TICK    0xffffU
32960 #define A_TP_TLS_CONFIG 0x99
32963 #define M_QUIESCETYPE1    0xffU
32968 #define M_QUIESCETYPE2    0xffU
32973 #define M_QUIESCETYPE3    0xffU
32977 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
32978 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
32979 #define A_TP_TX_DROP_CNT_CH2 0x122
32980 #define A_TP_TX_DROP_CNT_CH3 0x123
32981 #define A_TP_TX_DROP_CFG_CH0 0x12b
32992 #define M_TIMERTHRESHOLD    0x3ffffffU
32996 #define S_PACKETDROPS    0
32997 #define M_PACKETDROPS    0xfU
33001 #define A_TP_TX_DROP_CFG_CH1 0x12c
33002 #define A_TP_TX_DROP_CNT_CH0 0x12d
33005 #define M_TXDROPCNTCH0SENT    0xffffU
33009 #define S_TXDROPCNTCH0RCVD    0
33010 #define M_TXDROPCNTCH0RCVD    0xffffU
33014 #define A_TP_TX_DROP_CNT_CH1 0x12e
33017 #define M_TXDROPCNTCH1SENT    0xffffU
33021 #define S_TXDROPCNTCH1RCVD    0
33022 #define M_TXDROPCNTCH1RCVD    0xffffU
33026 #define A_TP_TX_DROP_MODE 0x12f
33040 #define S_TXDROPMODECH0    0
33044 #define A_TP_DBG_ESIDE_PKT0 0x130
33047 #define M_ETXSOPCNT    0xfU
33052 #define M_ETXEOPCNT    0xfU
33057 #define M_ETXPLDSOPCNT    0xfU
33062 #define M_ETXPLDEOPCNT    0xfU
33067 #define M_ERXSOPCNT    0xfU
33072 #define M_ERXEOPCNT    0xfU
33077 #define M_ERXPLDSOPCNT    0xfU
33081 #define S_ERXPLDEOPCNT    0
33082 #define M_ERXPLDEOPCNT    0xfU
33086 #define A_TP_DBG_ESIDE_PKT1 0x131
33087 #define A_TP_DBG_ESIDE_PKT2 0x132
33088 #define A_TP_DBG_ESIDE_PKT3 0x133
33089 #define A_TP_DBG_ESIDE_FIFO0 0x134
33215 #define S_ERXFULL0    0
33219 #define A_TP_DBG_ESIDE_FIFO1 0x135
33345 #define S_ERXFULL2    0
33349 #define A_TP_DBG_ESIDE_DISP0 0x136
33356 #define M_STATE    0x7U
33409 #define M_ESTATIC4    0xfU
33414 #define M_FIFOCPLSOCPCNT    0x3U
33419 #define M_FIFOETHSOCPCNT    0x3U
33424 #define M_FIFOIPSOCPCNT    0x3U
33429 #define M_FIFOTCPSOCPCNT    0x3U
33434 #define M_PLD_RXZEROP_CNT    0x3U
33442 #define S_TXFULL    0
33462 #define S_TXFULL_ESIDE0    0
33466 #define A_TP_DBG_ESIDE_DISP1 0x137
33468 #define S_TXFULL_ESIDE1    0
33472 #define A_TP_MAC_MATCH_MAP0 0x138
33475 #define M_MAPVALUEWR    0xffU
33480 #define M_MAPINDEX    0x1ffU
33488 #define S_MAPWRITE    0
33492 #define A_TP_MAC_MATCH_MAP1 0x139
33494 #define S_MAPVALUERD    0
33495 #define M_MAPVALUERD    0x1ffU
33499 #define A_TP_DBG_ESIDE_DISP2 0x13a
33501 #define S_TXFULL_ESIDE2    0
33505 #define A_TP_DBG_ESIDE_DISP3 0x13b
33507 #define S_TXFULL_ESIDE3    0
33511 #define A_TP_DBG_ESIDE_HDR0 0x13c
33514 #define M_TCPSOPCNT    0xfU
33519 #define M_TCPEOPCNT    0xfU
33524 #define M_IPSOPCNT    0xfU
33529 #define M_IPEOPCNT    0xfU
33534 #define M_ETHSOPCNT    0xfU
33539 #define M_ETHEOPCNT    0xfU
33544 #define M_CPLSOPCNT    0xfU
33548 #define S_CPLEOPCNT    0
33549 #define M_CPLEOPCNT    0xfU
33553 #define A_TP_DBG_ESIDE_HDR1 0x13d
33554 #define A_TP_DBG_ESIDE_HDR2 0x13e
33555 #define A_TP_DBG_ESIDE_HDR3 0x13f
33556 #define A_TP_VLAN_PRI_MAP 0x140
33594 #define S_FCOE    0
33694 #define S_IPSECIDX    0
33698 #define A_TP_INGRESS_CONFIG 0x141
33701 #define M_OPAQUE_TYPE    0xffffU
33737 #define S_IPV6_EXT_HDR_SKIP    0
33738 #define M_IPV6_EXT_HDR_SKIP    0xffU
33758 #define A_TP_TX_DROP_CFG_CH2 0x142
33759 #define A_TP_TX_DROP_CFG_CH3 0x143
33760 #define A_TP_EGRESS_CONFIG 0x145
33762 #define S_REWRITEFORCETOSIZE    0
33766 #define A_TP_INGRESS_CONFIG2 0x145
33777 #define M_TCP_PLD_FILTER_OFFSET    0x3ffU
33782 #define M_UDP_PLD_FILTER_OFFSET    0x3ffU
33786 #define S_TNL_PLD_FILTER_OFFSET    0
33787 #define M_TNL_PLD_FILTER_OFFSET    0x3ffU
33791 #define A_TP_EHDR_CONFIG_LO 0x146
33794 #define M_CPLLIMIT    0xffU
33799 #define M_ETHLIMIT    0xffU
33804 #define M_IPLIMIT    0xffU
33808 #define S_TCPLIMIT    0
33809 #define M_TCPLIMIT    0xffU
33813 #define A_TP_EHDR_CONFIG_HI 0x147
33814 #define A_TP_DBG_ESIDE_INT 0x148
33817 #define M_ERXSOP2X    0xfU
33822 #define M_ERXEOP2X    0xfU
33827 #define M_ERXVALID2X    0xfU
33832 #define M_ERXAFULL2X    0xfU
33837 #define M_PLD2XTXVALID    0xfU
33842 #define M_PLD2XTXAFULL    0xfU
33874 #define S_TCPOPTTXFULL    0
33886 #define A_TP_DBG_ESIDE_DEMUX 0x149
33889 #define M_EALLDONE    0xfU
33894 #define M_EFIFOPLDDONE    0xfU
33899 #define M_EDBDONE    0xfU
33904 #define M_EISSFIFODONE    0xfU
33909 #define M_EACKERRFIFODONE    0xfU
33914 #define M_EFIFOERRORDONE    0xfU
33919 #define M_ERXPKTATTRFIFOFDONE    0xfU
33923 #define S_ETCPOPDONE    0
33924 #define M_ETCPOPDONE    0xfU
33928 #define A_TP_DBG_ESIDE_IN0 0x14a
34054 #define S_RX_PKT_ATTR_DRDY    0
34074 #define A_TP_DBG_ESIDE_IN1 0x14b
34075 #define A_TP_DBG_ESIDE_IN2 0x14c
34076 #define A_TP_DBG_ESIDE_IN3 0x14d
34077 #define A_TP_DBG_ESIDE_FRM 0x14e
34080 #define M_ERX2XERROR    0xfU
34085 #define M_EPLDTX2XERROR    0xfU
34090 #define M_ETXERROR    0xfU
34095 #define M_EPLDRXERROR    0xfU
34100 #define M_ERXSIZEERROR3    0xfU
34105 #define M_ERXSIZEERROR2    0xfU
34110 #define M_ERXSIZEERROR1    0xfU
34114 #define S_ERXSIZEERROR0    0
34115 #define M_ERXSIZEERROR0    0xfU
34119 #define A_TP_DBG_ESIDE_DRP 0x14f
34122 #define M_RXDROP3    0xffU
34127 #define M_RXDROP2    0xffU
34132 #define M_RXDROP1    0xffU
34136 #define S_RXDROP0    0
34137 #define M_RXDROP0    0xffU
34141 #define A_TP_DBG_ESIDE_TX 0x150
34144 #define M_ETXVALID    0xfU
34148 #define S_ETXFULL    0
34149 #define M_ETXFULL    0xfU
34154 #define M_TXERRORCNT    0xffffffU
34158 #define A_TP_ESIDE_SVID_MASK 0x151
34159 #define A_TP_ESIDE_DVID_MASK 0x152
34160 #define A_TP_ESIDE_ALIGN_MASK 0x153
34167 #define M_LOOP_OFFSET    0xffU
34172 #define M_DVID_ID_OFFSET    0xffU
34176 #define S_SVID_ID_OFFSET    0
34177 #define M_SVID_ID_OFFSET    0xffU
34181 #define A_TP_DBG_ESIDE_OP 0x154
34192 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0    0x3U
34197 #define M_OPT_PARSER_OTK_STATE_CHANNEL0    0x3U
34210 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1    0x3U
34215 #define M_OPT_PARSER_OTK_STATE_CHANNEL1    0x3U
34228 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2    0x3U
34233 #define M_OPT_PARSER_OTK_STATE_CHANNEL2    0x3U
34246 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3    0x3U
34250 #define S_OPT_PARSER_OTK_STATE_CHANNEL3    0
34251 #define M_OPT_PARSER_OTK_STATE_CHANNEL3    0x3U
34255 #define A_TP_DBG_ESIDE_OP_ALT 0x155
34262 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    0x1fU
34271 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    0x1fU
34280 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    0x1fU
34288 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0
34289 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0x1fU
34293 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
34296 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3    0xffU
34301 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2    0xffU
34306 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1    0xffU
34310 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0    0
34311 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0    0xffU
34315 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
34318 #define M_OPT_PARSER_COOKIE_CHANNEL3    0xffU
34323 #define M_OPT_PARSER_COOKIE_CHANNEL2    0xffU
34328 #define M_OPT_PARSER_COOKIE_CHANNEL1    0xffU
34332 #define S_OPT_PARSER_COOKIE_CHANNEL0    0
34333 #define M_OPT_PARSER_COOKIE_CHANNEL0    0xffU
34337 #define A_TP_DBG_ESIDE_DEMUX_WAIT0 0x158
34338 #define A_TP_DBG_ESIDE_DEMUX_WAIT1 0x159
34339 #define A_TP_DBG_ESIDE_DEMUX_CNT0 0x15a
34340 #define A_TP_DBG_ESIDE_DEMUX_CNT1 0x15b
34341 #define A_TP_ESIDE_CONFIG 0x160
34355 #define S_ROCEV2UDPPORT    0
34356 #define M_ROCEV2UDPPORT    0xffffU
34372 #define A_TP_ESIDE_ROCE_PORT12 0x161
34375 #define M_ROCEV2UDPPORT2    0xffffU
34379 #define S_ROCEV2UDPPORT1    0
34380 #define M_ROCEV2UDPPORT1    0xffffU
34384 #define A_TP_ESIDE_ROCE_PORT34 0x162
34387 #define M_ROCEV2UDPPORT4    0xffffU
34391 #define S_ROCEV2UDPPORT3    0
34392 #define M_ROCEV2UDPPORT3    0xffffU
34396 #define A_TP_ESIDE_CONFIG1 0x163
34398 #define S_ROCEV2CRCIGN    0
34399 #define M_ROCEV2CRCIGN    0xfU
34403 #define A_TP_ESIDE_DEBUG_CFG 0x16c
34404 #define A_TP_ESIDE_DEBUG_DATA 0x16d
34405 #define A_TP_DBG_CSIDE_RX0 0x230
34408 #define M_CRXSOPCNT    0xfU
34413 #define M_CRXEOPCNT    0xfU
34418 #define M_CRXPLDSOPCNT    0xfU
34423 #define M_CRXPLDEOPCNT    0xfU
34428 #define M_CRXARBSOPCNT    0xfU
34433 #define M_CRXARBEOPCNT    0xfU
34438 #define M_CRXCPLSOPCNT    0xfU
34442 #define S_CRXCPLEOPCNT    0
34443 #define M_CRXCPLEOPCNT    0xfU
34447 #define A_TP_DBG_CSIDE_RX1 0x231
34448 #define A_TP_DBG_CSIDE_RX2 0x232
34449 #define A_TP_DBG_CSIDE_RX3 0x233
34450 #define A_TP_DBG_CSIDE_TX0 0x234
34453 #define M_TXSOPCNT    0xfU
34458 #define M_TXEOPCNT    0xfU
34463 #define M_TXPLDSOPCNT    0xfU
34468 #define M_TXPLDEOPCNT    0xfU
34473 #define M_TXARBSOPCNT    0xfU
34478 #define M_TXARBEOPCNT    0xfU
34483 #define M_TXCPLSOPCNT    0xfU
34487 #define S_TXCPLEOPCNT    0
34488 #define M_TXCPLEOPCNT    0xfU
34492 #define A_TP_DBG_CSIDE_TX1 0x235
34493 #define A_TP_DBG_CSIDE_TX2 0x236
34494 #define A_TP_DBG_CSIDE_TX3 0x237
34495 #define A_TP_DBG_CSIDE_FIFO0 0x238
34621 #define S_CPL5_TXFULL0    0
34625 #define A_TP_DBG_CSIDE_FIFO1 0x239
34751 #define S_CPL5_TXFULL2    0
34755 #define A_TP_DBG_CSIDE_DISP0 0x23a
34790 #define M_DDP_PRE_STATE    0x7U
34799 #define M_DDP_MSG_CODE    0xfU
34804 #define M_CPL5_SOCP_CNT    0x3U
34809 #define M_CSTATIC4    0x3fU
34842 #define M_DDPSTATE    0x1fU
34847 #define M_DDPMSGCODE    0xfU
34852 #define M_CPL5SOCPCNT    0xfU
34857 #define M_PLDRXZEROPCNT    0xfU
34873 #define S_TXFULL2X    0
34877 #define A_TP_DBG_CSIDE_DISP1 0x23b
34878 #define A_TP_DBG_CSIDE_DDP0 0x23c
34881 #define M_DDPMSGLATEST7    0xfU
34886 #define M_DDPMSGLATEST6    0xfU
34891 #define M_DDPMSGLATEST5    0xfU
34896 #define M_DDPMSGLATEST4    0xfU
34901 #define M_DDPMSGLATEST3    0xfU
34906 #define M_DDPMSGLATEST2    0xfU
34911 #define M_DDPMSGLATEST1    0xfU
34915 #define S_DDPMSGLATEST0    0
34916 #define M_DDPMSGLATEST0    0xfU
34920 #define A_TP_DBG_CSIDE_DDP1 0x23d
34921 #define A_TP_DBG_CSIDE_FRM 0x23e
34924 #define M_CRX2XERROR    0xfU
34929 #define M_CPLDTX2XERROR    0xfU
34934 #define M_CTXERROR    0x3U
34939 #define M_CPLDRXERROR    0x3U
34944 #define M_CPLRXERROR    0x3U
34949 #define M_CPLTXERROR    0x3U
34953 #define S_CPRSERROR    0
34954 #define M_CPRSERROR    0xfU
34958 #define A_TP_DBG_CSIDE_INT 0x23f
34961 #define M_CRXVALID2X    0xfU
34966 #define M_CRXAFULL2X    0xfU
34971 #define M_CTXVALID2X    0x3U
34976 #define M_CTXAFULL2X    0x3U
34981 #define M_PLD2X_RXVALID    0x3U
34986 #define M_PLD2X_RXAFULL    0x3U
34991 #define M_CSIDE_DDP_VALID    0x3U
34996 #define M_DDP_AFULL    0x3U
35017 #define M_PLD2X_TXVALID    0xfU
35021 #define S_PLD2X_TXAFULL    0
35022 #define M_PLD2X_TXAFULL    0xfU
35026 #define A_TP_CHDR_CONFIG 0x240
35029 #define M_CH1HIGH    0xffU
35034 #define M_CH1LOW    0xffU
35039 #define M_CH0HIGH    0xffU
35043 #define S_CH0LOW    0
35044 #define M_CH0LOW    0xffU
35048 #define A_TP_UTRN_CONFIG 0x241
35051 #define M_CH2FIFOLIMIT    0xffU
35056 #define M_CH1FIFOLIMIT    0xffU
35060 #define S_CH0FIFOLIMIT    0
35061 #define M_CH0FIFOLIMIT    0xffU
35065 #define A_TP_CDSP_CONFIG 0x242
35071 #define S_WRITEZEROOP    0
35072 #define M_WRITEZEROOP    0xfU
35109 #define M_T7_WRITEZEROOP    0x1fU
35137 #define S_T7_WRITEZEROEN    0
35141 #define A_TP_CSPI_POWER 0x243
35171 #define S_SLEEPREQUTRN    0
35195 #define A_TP_TRC_CONFIG 0x244
35201 #define S_TRCCH    0
35213 #define S_T7_TRCCH    0
35214 #define M_T7_TRCCH    0x3U
35218 #define A_TP_TAG_CONFIG 0x245
35221 #define M_ETAGTYPE    0xffffU
35225 #define A_TP_DBG_CSIDE_PRS 0x246
35228 #define M_CPRSSTATE3    0x7U
35233 #define M_CPRSSTATE2    0x7U
35238 #define M_CPRSSTATE1    0x7U
35242 #define S_CPRSSTATE0    0
35243 #define M_CPRSSTATE0    0x7U
35264 #define M_T5_CPRSSTATE3    0xfU
35285 #define M_T5_CPRSSTATE2    0xfU
35306 #define M_T5_CPRSSTATE1    0xfU
35326 #define S_T5_CPRSSTATE0    0
35327 #define M_T5_CPRSSTATE0    0xfU
35331 #define A_TP_DBG_CSIDE_DEMUX 0x247
35334 #define M_CALLDONE    0xfU
35339 #define M_CTCPL5DONE    0xfU
35344 #define M_CTXZEROPDONE    0xfU
35349 #define M_CPLDDONE    0xfU
35354 #define M_CTTCPOPDONE    0xfU
35359 #define M_CDBDONE    0xfU
35364 #define M_CISSFIFODONE    0xfU
35368 #define S_CTXPKTCSUMDONE    0
35369 #define M_CTXPKTCSUMDONE    0xfU
35374 #define M_CARBVALID    0xfU
35379 #define M_CCPL5DONE    0xfU
35384 #define M_CTCPOPDONE    0xfU
35388 #define A_TP_DBG_CSIDE_ARBIT 0x248
35514 #define S_ERRVALID0    0
35518 #define A_TP_DBG_CSIDE_TRACE_CNT 0x24a
35521 #define M_TRCSOPCNT    0xffU
35526 #define M_TRCEOPCNT    0xffU
35531 #define M_TRCFLTHIT    0xfU
35536 #define M_TRCRNTPKT    0xfU
35540 #define S_TRCPKTLEN    0
35541 #define M_TRCPKTLEN    0xffU
35545 #define A_TP_DBG_CSIDE_TRACE_RSS 0x24b
35546 #define A_TP_VLN_CONFIG 0x24c
35549 #define M_ETHTYPEQINQ    0xffffU
35553 #define S_ETHTYPEVLAN    0
35554 #define M_ETHTYPEVLAN    0xffffU
35558 #define A_TP_DBG_CSIDE_ARBIT_WAIT0 0x24d
35559 #define A_TP_DBG_CSIDE_ARBIT_WAIT1 0x24e
35560 #define A_TP_DBG_CSIDE_ARBIT_CNT0 0x24f
35561 #define A_TP_DBG_CSIDE_ARBIT_CNT1 0x250
35562 #define A_TP_CHDR_CONFIG1 0x259
35565 #define M_CH3HIGH    0xffU
35570 #define M_CH3LOW    0xffU
35575 #define M_CH2HIGH    0xffU
35579 #define S_CH2LOW    0
35580 #define M_CH2LOW    0xffU
35584 #define A_TP_CDSP_RDMA_CONFIG 0x260
35585 #define A_TP_NVMT_OP_CTRL 0x268
35588 #define M_DEFOPCTRL    0x3U
35592 #define S_NVMTOPCTRL    0
35593 #define M_NVMTOPCTRL    0x3fffffffU
35597 #define A_TP_CSIDE_DEBUG_CFG 0x26c
35608 #define M_T7_SELH    0x3fU
35612 #define S_T7_SELL    0
35613 #define M_T7_SELL    0x3fU
35617 #define A_TP_CSIDE_DEBUG_DATA 0x26d
35618 #define A_TP_FIFO_CONFIG 0x8c0
35621 #define M_CH1_OUTPUT    0x1fU
35626 #define M_CH2_OUTPUT    0x1fU
35635 #define M_CH1_INPUT    0x1fU
35640 #define M_CH2_INPUT    0x1fU
35645 #define M_CH3_INPUT    0x1fU
35649 #define S_STROBE0    0
35653 #define A_TP_MIB_MAC_IN_ERR_0 0x0
35654 #define A_TP_MIB_MAC_IN_ERR_1 0x1
35655 #define A_TP_MIB_MAC_IN_ERR_2 0x2
35656 #define A_TP_MIB_MAC_IN_ERR_3 0x3
35657 #define A_TP_MIB_HDR_IN_ERR_0 0x4
35658 #define A_TP_MIB_HDR_IN_ERR_1 0x5
35659 #define A_TP_MIB_HDR_IN_ERR_2 0x6
35660 #define A_TP_MIB_HDR_IN_ERR_3 0x7
35661 #define A_TP_MIB_TCP_IN_ERR_0 0x8
35662 #define A_TP_MIB_TCP_IN_ERR_1 0x9
35663 #define A_TP_MIB_TCP_IN_ERR_2 0xa
35664 #define A_TP_MIB_TCP_IN_ERR_3 0xb
35665 #define A_TP_MIB_TCP_OUT_RST 0xc
35666 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
35667 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
35668 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
35669 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
35670 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
35671 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
35672 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
35673 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
35674 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
35675 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
35676 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
35677 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
35678 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
35679 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
35680 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
35681 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
35682 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
35683 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
35684 #define A_TP_MIB_TNL_IN_PKT_0 0x24
35685 #define A_TP_MIB_TNL_IN_PKT_1 0x25
35686 #define A_TP_MIB_TNL_IN_PKT_2 0x26
35687 #define A_TP_MIB_TNL_IN_PKT_3 0x27
35688 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
35689 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
35690 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
35691 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
35692 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
35693 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
35694 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
35695 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
35696 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
35697 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
35698 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
35699 #define A_TP_MIB_OFD_ARP_DROP 0x36
35700 #define A_TP_MIB_OFD_DFR_DROP 0x37
35701 #define A_TP_MIB_CPL_IN_REQ_0 0x38
35702 #define A_TP_MIB_CPL_IN_REQ_1 0x39
35703 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
35704 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
35705 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
35706 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
35707 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
35708 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
35709 #define A_TP_MIB_TNL_LPBK_0 0x40
35710 #define A_TP_MIB_TNL_LPBK_1 0x41
35711 #define A_TP_MIB_TNL_LPBK_2 0x42
35712 #define A_TP_MIB_TNL_LPBK_3 0x43
35713 #define A_TP_MIB_TNL_DROP_0 0x44
35714 #define A_TP_MIB_TNL_DROP_1 0x45
35715 #define A_TP_MIB_TNL_DROP_2 0x46
35716 #define A_TP_MIB_TNL_DROP_3 0x47
35717 #define A_TP_MIB_FCOE_DDP_0 0x48
35718 #define A_TP_MIB_FCOE_DDP_1 0x49
35719 #define A_TP_MIB_FCOE_DDP_2 0x4a
35720 #define A_TP_MIB_FCOE_DDP_3 0x4b
35721 #define A_TP_MIB_FCOE_DROP_0 0x4c
35722 #define A_TP_MIB_FCOE_DROP_1 0x4d
35723 #define A_TP_MIB_FCOE_DROP_2 0x4e
35724 #define A_TP_MIB_FCOE_DROP_3 0x4f
35725 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
35726 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
35727 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
35728 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
35729 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
35730 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
35731 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
35732 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
35733 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
35734 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
35735 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
35736 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
35737 #define A_TP_MIB_USM_PKTS 0x5c
35738 #define A_TP_MIB_USM_DROP 0x5d
35739 #define A_TP_MIB_USM_BYTES_HI 0x5e
35740 #define A_TP_MIB_USM_BYTES_LO 0x5f
35741 #define A_TP_MIB_TID_DEL 0x60
35742 #define A_TP_MIB_TID_INV 0x61
35743 #define A_TP_MIB_TID_ACT 0x62
35744 #define A_TP_MIB_TID_PAS 0x63
35745 #define A_TP_MIB_RQE_DFR_PKT 0x64
35746 #define A_TP_MIB_RQE_DFR_MOD 0x65
35747 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
35748 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
35749 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
35750 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
35751 #define A_TP_MIB_ENG_LINE_0 0x6c
35752 #define A_TP_MIB_ENG_LINE_1 0x6d
35753 #define A_TP_MIB_ENG_LINE_2 0x6e
35754 #define A_TP_MIB_ENG_LINE_3 0x6f
35755 #define A_TP_MIB_TNL_ERR_0 0x70
35756 #define A_TP_MIB_TNL_ERR_1 0x71
35757 #define A_TP_MIB_TNL_ERR_2 0x72
35758 #define A_TP_MIB_TNL_ERR_3 0x73
35759 #define A_TP_MIB_RDMA_IN_PKT_0 0x80
35760 #define A_TP_MIB_RDMA_IN_PKT_1 0x81
35761 #define A_TP_MIB_RDMA_IN_PKT_2 0x82
35762 #define A_TP_MIB_RDMA_IN_PKT_3 0x83
35763 #define A_TP_MIB_RDMA_IN_BYTE_HI_0 0x84
35764 #define A_TP_MIB_RDMA_IN_BYTE_LO_0 0x85
35765 #define A_TP_MIB_RDMA_IN_BYTE_HI_1 0x86
35766 #define A_TP_MIB_RDMA_IN_BYTE_LO_1 0x87
35767 #define A_TP_MIB_RDMA_IN_BYTE_HI_2 0x88
35768 #define A_TP_MIB_RDMA_IN_BYTE_LO_2 0x89
35769 #define A_TP_MIB_RDMA_IN_BYTE_HI_3 0x8a
35770 #define A_TP_MIB_RDMA_IN_BYTE_LO_3 0x8b
35771 #define A_TP_MIB_RDMA_OUT_PKT_0 0x90
35772 #define A_TP_MIB_RDMA_OUT_PKT_1 0x91
35773 #define A_TP_MIB_RDMA_OUT_PKT_2 0x92
35774 #define A_TP_MIB_RDMA_OUT_PKT_3 0x93
35775 #define A_TP_MIB_RDMA_OUT_BYTE_HI_0 0x94
35776 #define A_TP_MIB_RDMA_OUT_BYTE_LO_0 0x95
35777 #define A_TP_MIB_RDMA_OUT_BYTE_HI_1 0x96
35778 #define A_TP_MIB_RDMA_OUT_BYTE_LO_1 0x97
35779 #define A_TP_MIB_RDMA_OUT_BYTE_HI_2 0x98
35780 #define A_TP_MIB_RDMA_OUT_BYTE_LO_2 0x99
35781 #define A_TP_MIB_RDMA_OUT_BYTE_HI_3 0x9a
35782 #define A_TP_MIB_RDMA_OUT_BYTE_LO_3 0x9b
35783 #define A_TP_MIB_ISCSI_IN_PKT_0 0xa0
35784 #define A_TP_MIB_ISCSI_IN_PKT_1 0xa1
35785 #define A_TP_MIB_ISCSI_IN_PKT_2 0xa2
35786 #define A_TP_MIB_ISCSI_IN_PKT_3 0xa3
35787 #define A_TP_MIB_ISCSI_IN_BYTE_HI_0 0xa4
35788 #define A_TP_MIB_ISCSI_IN_BYTE_LO_0 0xa5
35789 #define A_TP_MIB_ISCSI_IN_BYTE_HI_1 0xa6
35790 #define A_TP_MIB_ISCSI_IN_BYTE_LO_1 0xa7
35791 #define A_TP_MIB_ISCSI_IN_BYTE_HI_2 0xa8
35792 #define A_TP_MIB_ISCSI_IN_BYTE_LO_2 0xa9
35793 #define A_TP_MIB_ISCSI_IN_BYTE_HI_3 0xaa
35794 #define A_TP_MIB_ISCSI_IN_BYTE_LO_3 0xab
35795 #define A_TP_MIB_ISCSI_OUT_PKT_0 0xb0
35796 #define A_TP_MIB_ISCSI_OUT_PKT_1 0xb1
35797 #define A_TP_MIB_ISCSI_OUT_PKT_2 0xb2
35798 #define A_TP_MIB_ISCSI_OUT_PKT_3 0xb3
35799 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_0 0xb4
35800 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_0 0xb5
35801 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_1 0xb6
35802 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_1 0xb7
35803 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_2 0xb8
35804 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_2 0xb9
35805 #define A_TP_MIB_ISCSI_OUT_BYTE_HI_3 0xba
35806 #define A_TP_MIB_ISCSI_OUT_BYTE_LO_3 0xbb
35807 #define A_TP_MIB_NVMT_IN_PKT_0 0xc0
35808 #define A_TP_MIB_NVMT_IN_PKT_1 0xc1
35809 #define A_TP_MIB_NVMT_IN_PKT_2 0xc2
35810 #define A_TP_MIB_NVMT_IN_PKT_3 0xc3
35811 #define A_TP_MIB_NVMT_IN_BYTE_HI_0 0xc4
35812 #define A_TP_MIB_NVMT_IN_BYTE_LO_0 0xc5
35813 #define A_TP_MIB_NVMT_IN_BYTE_HI_1 0xc6
35814 #define A_TP_MIB_NVMT_IN_BYTE_LO_1 0xc7
35815 #define A_TP_MIB_NVMT_IN_BYTE_HI_2 0xc8
35816 #define A_TP_MIB_NVMT_IN_BYTE_LO_2 0xc9
35817 #define A_TP_MIB_NVMT_IN_BYTE_HI_3 0xca
35818 #define A_TP_MIB_NVMT_IN_BYTE_LO_3 0xcb
35819 #define A_TP_MIB_NVMT_OUT_PKT_0 0xd0
35820 #define A_TP_MIB_NVMT_OUT_PKT_1 0xd1
35821 #define A_TP_MIB_NVMT_OUT_PKT_2 0xd2
35822 #define A_TP_MIB_NVMT_OUT_PKT_3 0xd3
35823 #define A_TP_MIB_NVMT_OUT_BYTE_HI_0 0xd4
35824 #define A_TP_MIB_NVMT_OUT_BYTE_LO_0 0xd5
35825 #define A_TP_MIB_NVMT_OUT_BYTE_HI_1 0xd6
35826 #define A_TP_MIB_NVMT_OUT_BYTE_LO_1 0xd7
35827 #define A_TP_MIB_NVMT_OUT_BYTE_HI_2 0xd8
35828 #define A_TP_MIB_NVMT_OUT_BYTE_LO_2 0xd9
35829 #define A_TP_MIB_NVMT_OUT_BYTE_HI_3 0xda
35830 #define A_TP_MIB_NVMT_OUT_BYTE_LO_3 0xdb
35831 #define A_TP_MIB_TLS_IN_PKT_0 0xe0
35832 #define A_TP_MIB_TLS_IN_PKT_1 0xe1
35833 #define A_TP_MIB_TLS_IN_PKT_2 0xe2
35834 #define A_TP_MIB_TLS_IN_PKT_3 0xe3
35835 #define A_TP_MIB_TLS_IN_BYTE_HI_0 0xe4
35836 #define A_TP_MIB_TLS_IN_BYTE_LO_0 0xe5
35837 #define A_TP_MIB_TLS_IN_BYTE_HI_1 0xe6
35838 #define A_TP_MIB_TLS_IN_BYTE_LO_1 0xe7
35839 #define A_TP_MIB_TLS_IN_BYTE_HI_2 0xe8
35840 #define A_TP_MIB_TLS_IN_BYTE_LO_2 0xe9
35841 #define A_TP_MIB_TLS_IN_BYTE_HI_3 0xea
35842 #define A_TP_MIB_TLS_IN_BYTE_LO_3 0xeb
35843 #define A_TP_MIB_TLS_OUT_PKT_0 0xf0
35844 #define A_TP_MIB_TLS_OUT_PKT_1 0xf1
35845 #define A_TP_MIB_TLS_OUT_PKT_2 0xf2
35846 #define A_TP_MIB_TLS_OUT_PKT_3 0xf3
35847 #define A_TP_MIB_TLS_OUT_BYTE_HI_0 0xf4
35848 #define A_TP_MIB_TLS_OUT_BYTE_LO_0 0xf5
35849 #define A_TP_MIB_TLS_OUT_BYTE_HI_1 0xf6
35850 #define A_TP_MIB_TLS_OUT_BYTE_LO_1 0xf7
35851 #define A_TP_MIB_TLS_OUT_BYTE_HI_2 0xf8
35852 #define A_TP_MIB_TLS_OUT_BYTE_LO_2 0xf9
35853 #define A_TP_MIB_TLS_OUT_BYTE_HI_3 0xfa
35854 #define A_TP_MIB_TLS_OUT_BYTE_LO_3 0xfb
35855 #define A_TP_MIB_ROCE_IN_PKT_0 0x100
35856 #define A_TP_MIB_ROCE_IN_PKT_1 0x101
35857 #define A_TP_MIB_ROCE_IN_PKT_2 0x102
35858 #define A_TP_MIB_ROCE_IN_PKT_3 0x103
35859 #define A_TP_MIB_ROCE_IN_BYTE_HI_0 0x104
35860 #define A_TP_MIB_ROCE_IN_BYTE_LO_0 0x105
35861 #define A_TP_MIB_ROCE_IN_BYTE_HI_1 0x106
35862 #define A_TP_MIB_ROCE_IN_BYTE_LO_1 0x107
35863 #define A_TP_MIB_ROCE_IN_BYTE_HI_2 0x108
35864 #define A_TP_MIB_ROCE_IN_BYTE_LO_2 0x109
35865 #define A_TP_MIB_ROCE_IN_BYTE_HI_3 0x10a
35866 #define A_TP_MIB_ROCE_IN_BYTE_LO_3 0x10b
35867 #define A_TP_MIB_ROCE_OUT_PKT_0 0x110
35868 #define A_TP_MIB_ROCE_OUT_PKT_1 0x111
35869 #define A_TP_MIB_ROCE_OUT_PKT_2 0x112
35870 #define A_TP_MIB_ROCE_OUT_PKT_3 0x113
35871 #define A_TP_MIB_ROCE_OUT_BYTE_HI_0 0x114
35872 #define A_TP_MIB_ROCE_OUT_BYTE_LO_0 0x115
35873 #define A_TP_MIB_ROCE_OUT_BYTE_HI_1 0x116
35874 #define A_TP_MIB_ROCE_OUT_BYTE_LO_1 0x117
35875 #define A_TP_MIB_ROCE_OUT_BYTE_HI_2 0x118
35876 #define A_TP_MIB_ROCE_OUT_BYTE_LO_2 0x119
35877 #define A_TP_MIB_ROCE_OUT_BYTE_HI_3 0x11a
35878 #define A_TP_MIB_ROCE_OUT_BYTE_LO_3 0x11b
35879 #define A_TP_MIB_IPSEC_TNL_IN_PKT_0 0x120
35880 #define A_TP_MIB_IPSEC_TNL_IN_PKT_1 0x121
35881 #define A_TP_MIB_IPSEC_TNL_IN_PKT_2 0x122
35882 #define A_TP_MIB_IPSEC_TNL_IN_PKT_3 0x123
35883 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_0 0x124
35884 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_0 0x125
35885 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_1 0x126
35886 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_1 0x127
35887 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_2 0x128
35888 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_2 0x129
35889 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_HI_3 0x12a
35890 #define A_TP_MIB_IPSEC_TNL_IN_BYTE_LO_3 0x12b
35891 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_0 0x130
35892 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_1 0x131
35893 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_2 0x132
35894 #define A_TP_MIB_IPSEC_TNL_OUT_PKT_3 0x133
35895 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_0 0x134
35896 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_0 0x135
35897 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_1 0x136
35898 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_1 0x137
35899 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_2 0x138
35900 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_2 0x139
35901 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_HI_3 0x13a
35902 #define A_TP_MIB_IPSEC_TNL_OUT_BYTE_LO_3 0x13b
35903 #define A_TP_MIB_IPSEC_OFD_IN_PKT_0 0x140
35904 #define A_TP_MIB_IPSEC_OFD_IN_PKT_1 0x141
35905 #define A_TP_MIB_IPSEC_OFD_IN_PKT_2 0x142
35906 #define A_TP_MIB_IPSEC_OFD_IN_PKT_3 0x143
35907 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_0 0x144
35908 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_0 0x145
35909 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_1 0x146
35910 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_1 0x147
35911 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_2 0x148
35912 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_2 0x149
35913 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_HI_3 0x14a
35914 #define A_TP_MIB_IPSEC_OFD_IN_BYTE_LO_3 0x14b
35915 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_0 0x150
35916 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_1 0x151
35917 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_2 0x152
35918 #define A_TP_MIB_IPSEC_OFD_OUT_PKT_3 0x153
35919 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_0 0x154
35920 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_0 0x155
35921 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_1 0x156
35922 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_1 0x157
35923 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_2 0x158
35924 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_2 0x159
35925 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_HI_3 0x15a
35926 #define A_TP_MIB_IPSEC_OFD_OUT_BYTE_LO_3 0x15b
35929 #define ULP_TX_BASE_ADDR 0x8dc0
35931 #define A_ULP_TX_CONFIG 0x8dc0
35941 #define S_EXTRA_TAG_INSERTION_ENABLE    0
36034 #define M_MEM_ADDR_CTRL    0x3U
36054 #define A_ULP_TX_PERR_INJECT 0x8dc4
36057 #define M_T7_1_MEMSEL    0x7fU
36061 #define A_ULP_TX_INT_ENABLE 0x8dc8
36187 #define S_IMM_DATA_PERR_SET_CH0    0
36191 #define A_ULP_TX_INT_ENABLE_1 0x8dc8
36205 #define S_TLS_DSGL_PARERR0    0
36209 #define A_ULP_TX_INT_CAUSE 0x8dcc
36210 #define A_ULP_TX_INT_CAUSE_1 0x8dcc
36211 #define A_ULP_TX_PERR_ENABLE 0x8dd0
36212 #define A_ULP_TX_PERR_ENABLE_1 0x8dd0
36213 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
36214 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
36215 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
36216 #define A_ULP_TX_PBL_ULIMIT 0x8de0
36217 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
36218 #define A_ULP_TX_TLS_CTL 0x8de4
36236 #define S_TLSDISABLE    0
36240 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
36241 #define A_ULP_TX_FID_1 0x8de8
36243 #define S_FID_1    0
36244 #define M_FID_1    0x7ffU
36248 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
36249 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
36250 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
36251 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
36254 #define M_CH3SIZE1    0xffU
36259 #define M_CH2SIZE1    0xffU
36264 #define M_CH1SIZE1    0xffU
36268 #define S_CH0SIZE1    0
36269 #define M_CH0SIZE1    0xffU
36273 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
36276 #define M_CH3SIZE2    0xffU
36281 #define M_CH2SIZE2    0xffU
36286 #define M_CH1SIZE2    0xffU
36290 #define S_CH0SIZE2    0
36291 #define M_CH0SIZE2    0xffU
36295 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
36296 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
36297 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
36299 #define S_ERR_CNT0    0
36300 #define M_ERR_CNT0    0xfffffU
36304 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
36306 #define S_ERR_CNT1    0
36307 #define M_ERR_CNT1    0xfffffU
36311 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
36313 #define S_ERR_CNT2    0
36314 #define M_ERR_CNT2    0xfffffU
36318 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
36320 #define S_ERR_CNT3    0
36321 #define M_ERR_CNT3    0xfffffU
36325 #define A_ULP_TX_FC_SOF 0x8e20
36328 #define M_SOF_FS3    0xffU
36333 #define M_SOF_FS2    0xffU
36338 #define M_SOF_3    0xffU
36342 #define S_SOF_2    0
36343 #define M_SOF_2    0xffU
36347 #define A_ULP_TX_FC_EOF 0x8e24
36350 #define M_EOF_LS3    0xffU
36355 #define M_EOF_LS2    0xffU
36360 #define M_EOF_3    0xffU
36364 #define S_EOF_2    0
36365 #define M_EOF_2    0xffU
36369 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
36371 #define S_ULP_TX_GLOBAL_CGEN    0
36375 #define A_ULP_TX_CGEN 0x8e2c
36378 #define M_ULP_TX_CGEN_STORAGE    0xfU
36383 #define M_ULP_TX_CGEN_RDMA    0xfU
36387 #define S_ULP_TX_CGEN_CHANNEL    0
36388 #define M_ULP_TX_CGEN_CHANNEL    0xfU
36392 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
36393 #define A_ULP_TX_MEM_CFG 0x8e30
36395 #define S_WRREQ_SZ    0
36396 #define M_WRREQ_SZ    0x7U
36405 #define M_RDREQ_SZ    0x7U
36409 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
36410 #define A_ULP_TX_PERR_INJECT_2 0x8e34
36413 #define M_T5_MEMSEL    0x7U
36418 #define M_MEMSEL_ULPTX    0x1fU
36422 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
36423 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
36426 #define M_CHANNEL_SEL    0x3U
36431 #define M_INTF_SEL    0xfU
36436 #define M_NUM_FLITS    0x7U
36440 #define S_CMD_GEN_EN    0
36444 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
36445 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
36446 #define A_ULP_TX_FPGA_CMD_1 0x8e40
36447 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
36448 #define A_ULP_TX_FPGA_CMD_2 0x8e44
36449 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
36450 #define A_ULP_TX_FPGA_CMD_3 0x8e48
36451 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
36452 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
36453 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
36454 #define A_ULP_TX_FPGA_CMD_5 0x8e50
36455 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
36456 #define A_ULP_TX_FPGA_CMD_6 0x8e54
36457 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
36458 #define A_ULP_TX_FPGA_CMD_7 0x8e58
36459 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
36460 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
36461 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
36462 #define A_ULP_TX_FPGA_CMD_9 0x8e60
36463 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
36464 #define A_ULP_TX_FPGA_CMD_10 0x8e64
36465 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
36466 #define A_ULP_TX_FPGA_CMD_11 0x8e68
36467 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
36468 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
36469 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
36470 #define A_ULP_TX_FPGA_CMD_13 0x8e70
36471 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
36472 #define A_ULP_TX_FPGA_CMD_14 0x8e74
36473 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
36474 #define A_ULP_TX_FPGA_CMD_15 0x8e78
36475 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
36476 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
36526 #define S_T10_PI_SRAM_PERR_SET0    0
36626 #define A_ULP_TX_INT_CAUSE_2 0x8e80
36627 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
36628 #define A_ULP_TX_INT_ENABLE_3 0x8e88
36750 #define S_CIM2ULP_PERR    0
36754 #define A_ULP_TX_INT_CAUSE_3 0x8e8c
36755 #define A_ULP_TX_PERR_ENABLE_3 0x8e90
36756 #define A_ULP_TX_INT_ENABLE_4 0x8e94
36759 #define M_DMA_PAR_ERR3    0xfU
36764 #define M_DMA_PAR_ERR2    0xfU
36769 #define M_DMA_PAR_ERR1    0xfU
36774 #define M_DMA_PAR_ERR0    0xfU
36779 #define M_CORE_CMD_FIFO_LB1    0xfU
36784 #define M_CORE_CMD_FIFO_LB0    0xfU
36816 #define S_TF_MP_PERR    0
36820 #define A_ULP_TX_INT_CAUSE_4 0x8e98
36821 #define A_ULP_TX_PERR_ENABLE_4 0x8e9c
36822 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
36825 #define M_ERR_CH3    0xfU
36830 #define M_ERR_CH2    0xfU
36835 #define M_ERR_CH1    0xfU
36839 #define S_ERR_CH0    0
36840 #define M_ERR_CH0    0xfU
36844 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
36845 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
36848 #define M_CLR_DROP    0xfU
36853 #define M_CLR_CH3    0xfU
36858 #define M_CLR_CH2    0xfU
36863 #define M_CLR_CH1    0xfU
36867 #define S_CLR_CH0    0
36868 #define M_CLR_CH0    0xfU
36872 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
36873 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
36876 #define M_SOP_CNT_ULP2TP    0xfU
36881 #define M_EOP_CNT_ULP2TP    0xfU
36886 #define M_SOP_CNT_LSO_IN    0xfU
36891 #define M_EOP_CNT_LSO_IN    0xfU
36896 #define M_SOP_CNT_ALG_IN    0xfU
36901 #define M_EOP_CNT_ALG_IN    0xfU
36906 #define M_SOP_CNT_CIM2ULP    0xfU
36910 #define S_EOP_CNT_CIM2ULP    0
36911 #define M_EOP_CNT_CIM2ULP    0xfU
36915 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
36916 #define A_ULP_TX_SE_CNT_CH1 0x8eac
36917 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
36918 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
36919 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
36920 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
36921 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
36922 #define A_ULP_TX_DROP_CNT 0x8eb8
36925 #define M_DROP_CH3    0xfU
36930 #define M_DROP_CH2    0xfU
36935 #define M_DROP_CH1    0xfU
36939 #define S_DROP_CH0    0
36940 #define M_DROP_CH0    0xfU
36944 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
36947 #define M_DROP_INVLD_MC_CH3    0xfU
36952 #define M_DROP_INVLD_MC_CH2    0xfU
36957 #define M_DROP_INVLD_MC_CH1    0xfU
36962 #define M_DROP_INVLD_MC_CH0    0xfU
36966 #define A_ULP_TX_CSU_REVISION 0x8ebc
36967 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
36968 #define A_ULP_TX_PL2APB_INFO 0x8ec0
36986 #define S_PL2APB_BRIDGE_HUNG_ADDR    0
36987 #define M_PL2APB_BRIDGE_HUNG_ADDR    0xfffffU
36991 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
36992 #define A_ULP_TX_INT_ENABLE_5 0x8ec4
37054 #define S_ULP_2_XP10_PL_PERR    0
37058 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
37059 #define A_ULP_TX_INT_CAUSE_5 0x8ec8
37060 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
37061 #define A_ULP_TX_PERR_ENABLE_5 0x8ecc
37062 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
37063 #define A_ULP_TX_INT_CAUSE_6 0x8ed0
37113 #define S_RSP_FIFO_PERR_SET    0
37117 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
37118 #define A_ULP_TX_INT_ENABLE_6 0x8ed4
37119 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
37120 #define A_ULP_TX_PERR_ENABLE_6 0x8ed8
37121 #define A_ULP_TX_LA_RESERVED_1 0x8edc
37122 #define A_ULP_TX_INT_CAUSE_7 0x8edc
37216 #define S_PRE_CQE_FIFO_CERR_SET0    0
37220 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
37221 #define A_ULP_TX_INT_ENABLE_7 0x8ee0
37222 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
37223 #define A_ULP_TX_INT_CAUSE_8 0x8ee4
37337 #define S_RSP_FIFO_CERR_SET    0
37341 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
37342 #define A_ULP_TX_INT_ENABLE_8 0x8ee8
37343 #define A_ULP_TX_LA_RESERVED_2 0x8eec
37344 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
37345 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
37346 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
37347 #define A_ULP_TX_LA_RESERVED_3 0x8efc
37348 #define A_ULP_TX_LA_RDPTR_4 0x8f00
37349 #define A_ULP_TX_LA_RDDATA_4 0x8f04
37350 #define A_ULP_TX_LA_WRPTR_4 0x8f08
37351 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
37352 #define A_ULP_TX_LA_RDPTR_5 0x8f10
37353 #define A_ULP_TX_LA_RDDATA_5 0x8f14
37354 #define A_ULP_TX_LA_WRPTR_5 0x8f18
37355 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
37356 #define A_ULP_TX_LA_RDPTR_6 0x8f20
37357 #define A_ULP_TX_LA_RDDATA_6 0x8f24
37358 #define A_ULP_TX_LA_WRPTR_6 0x8f28
37359 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
37360 #define A_ULP_TX_LA_RDPTR_7 0x8f30
37361 #define A_ULP_TX_LA_RDDATA_7 0x8f34
37362 #define A_ULP_TX_LA_WRPTR_7 0x8f38
37363 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
37364 #define A_ULP_TX_LA_RDPTR_8 0x8f40
37365 #define A_ULP_TX_LA_RDDATA_8 0x8f44
37366 #define A_ULP_TX_LA_WRPTR_8 0x8f48
37367 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
37368 #define A_ULP_TX_LA_RDPTR_9 0x8f50
37369 #define A_ULP_TX_LA_RDDATA_9 0x8f54
37370 #define A_ULP_TX_LA_WRPTR_9 0x8f58
37371 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
37372 #define A_ULP_TX_LA_RDPTR_10 0x8f60
37373 #define A_ULP_TX_LA_RDDATA_10 0x8f64
37374 #define A_ULP_TX_LA_WRPTR_10 0x8f68
37375 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
37376 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
37378 #define S_LA_WR0    0
37382 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
37383 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
37384 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
37385 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
37386 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
37387 #define A_ULP_TX_CPL_TX_DATA_FLAGS_MASK 0x8f88
37469 #define S_SHOVE_LAST    0
37473 #define A_ULP_TX_ACCELERATOR_CTL 0x8f90
37476 #define M_FIFO_THRESHOLD    0x1fU
37500 #define S_GFDISABLE    0
37504 #define A_ULP_TX_XP10_IND_ADDR 0x8f94
37510 #define S_XP10_ADDR    0
37511 #define M_XP10_ADDR    0xfffffU
37515 #define A_ULP_TX_XP10_IND_DATA 0x8f98
37516 #define A_ULP_TX_IWARP_PMOF_OPCODES_1 0x8f9c
37519 #define M_RDMA_VERIFY_RESPONSE    0x1fU
37524 #define M_RDMA_VERIFY_REQUEST    0x1fU
37529 #define M_RDMA_FLUSH_RESPONSE    0x1fU
37533 #define S_RDMA_FLUSH_REQUEST    0
37534 #define M_RDMA_FLUSH_REQUEST    0x1fU
37538 #define A_ULP_TX_IWARP_PMOF_OPCODES_2 0x8fa0
37541 #define M_RDMA_SEND_WITH_SE_IMMEDIATE    0x1fU
37546 #define M_RDMA_SEND_WITH_IMMEDIATE    0x1fU
37551 #define M_RDMA_ATOMIC_WRITE_RESPONSE    0x1fU
37555 #define S_RDMA_ATOMIC_WRITE_REQUEST    0
37556 #define M_RDMA_ATOMIC_WRITE_REQUEST    0x1fU
37560 #define A_ULP_TX_NVME_TCP_TPT_LLIMIT 0x8fa4
37561 #define A_ULP_TX_NVME_TCP_TPT_ULIMIT 0x8fa8
37562 #define A_ULP_TX_NVME_TCP_PBL_LLIMIT 0x8fac
37563 #define A_ULP_TX_NVME_TCP_PBL_ULIMIT 0x8fb0
37564 #define A_ULP_TX_TLS_IND_CMD 0x8fb8
37566 #define S_TLS_TX_REG_OFF_ADDR    0
37567 #define M_TLS_TX_REG_OFF_ADDR    0x3ffU
37571 #define A_ULP_TX_DBG_CTL 0x8fb8
37572 #define A_ULP_TX_TLS_IND_DATA 0x8fbc
37573 #define A_ULP_TX_DBG_DATA 0x8fbc
37574 #define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc
37588 #define S_KEX_PERR    0
37592 #define A_ULP_TX_TLS_CH0_PERR_ENABLE 0x10
37593 #define A_ULP_TX_TLS_CH0_HMACCTRL_CFG 0x20
37596 #define M_HMAC_CFG6    0x3fU
37601 #define M_HMAC_CFG5    0x3fU
37605 #define S_HMAC_CFG4    0
37606 #define M_HMAC_CFG4    0x3fU
37610 #define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c
37611 #define A_ULP_TX_TLS_CH1_PERR_ENABLE 0x50
37612 #define A_ULP_TX_TLS_CH1_HMACCTRL_CFG 0x60
37615 #define PM_RX_BASE_ADDR 0x8fc0
37617 #define A_PM_RX_CFG 0x8fc0
37618 #define A_PM_RX_MODE 0x8fc4
37629 #define M_STAT_FROM_CH    0x3U
37633 #define S_PREFETCH_ENABLE    0
37646 #define M_CACHE_DEPTH    0xfU
37662 #define A_PM_RX_STAT_CONFIG 0x8fc8
37663 #define A_PM_RX_STAT_COUNT 0x8fcc
37664 #define A_PM_RX_STAT_LSB 0x8fd0
37665 #define A_PM_RX_DBG_CTRL 0x8fd0
37668 #define M_OSPIWRBUSY_T5    0x3U
37673 #define M_ISPIWRBUSY    0xfU
37677 #define S_PMDBGADDR    0
37678 #define M_PMDBGADDR    0x1ffffU
37683 #define M_T7_OSPIWRBUSY_T5    0xfU
37687 #define A_PM_RX_STAT_MSB 0x8fd4
37688 #define A_PM_RX_DBG_DATA 0x8fd4
37689 #define A_PM_RX_INT_ENABLE 0x8fd8
37779 #define S_E_PCMD_PAR_ERROR    0
37819 #define A_PM_RX_INT_CAUSE 0x8fdc
37833 #define S_CACHE_CTRL_ERROR    0
37837 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
37838 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
37839 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
37840 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
37841 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
37842 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
37843 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
37844 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
37845 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
37846 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
37847 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
37848 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
37849 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
37850 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
37851 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
37852 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
37853 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
37854 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
37855 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
37856 #define A_PM_RX_DBG_STAT_MSB 0x10013
37857 #define A_PM_RX_DBG_STAT_LSB 0x10014
37858 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
37861 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP    0xfU
37866 #define M_I_TO_O_PATH_RSVD_FLIT    0xfU
37871 #define M_PRFCH_RSVD_FLIT    0xfU
37875 #define S_OSPI_RSVD_FLIT    0
37876 #define M_OSPI_RSVD_FLIT    0xfU
37880 #define A_PM_RX_SDC_EN 0x10016
37882 #define S_SDC_EN    0
37886 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
37900 #define S_CHNL_0_SEL    0
37904 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
37918 #define S_I_FIFO_READ    0
37922 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
37924 #define S_ISPI_STR_FWD_EN    0
37928 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
37930 #define S_PRFTCH_ACROSS_BNDLE_EN    0
37934 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
37936 #define S_PRFTCH_WRR_ENABLE    0
37940 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
37943 #define M_CHNL1_MAX_DEFICIT_CNT    0xffffU
37947 #define S_CHNL0_MAX_DEFICIT_CNT    0
37948 #define M_CHNL0_MAX_DEFICIT_CNT    0xffffU
37952 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT0 0x1001c
37953 #define A_PM_RX_FEATURE_EN 0x1001d
37955 #define S_PIO_CH_DEFICIT_CTL_EN_RX    0
37959 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT1 0x1001d
37962 #define M_CHNL3_MAX_DEFICIT_CNT    0xffffU
37966 #define S_CHNL2_MAX_DEFICIT_CNT    0
37967 #define M_CHNL2_MAX_DEFICIT_CNT    0xffffU
37971 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
37973 #define S_CH0_OSPI_DEFICIT_THRSHLD    0
37974 #define M_CH0_OSPI_DEFICIT_THRSHLD    0xfffU
37978 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
37980 #define S_CH1_OSPI_DEFICIT_THRSHLD    0
37981 #define M_CH1_OSPI_DEFICIT_THRSHLD    0xfffU
37985 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
37986 #define A_PM_RX_DBG_STAT0 0x10021
38029 #define M_RX_PCMD_FB    0xfU
38033 #define S_RX_PCMD_LEN    0
38034 #define M_RX_PCMD_LEN    0xffffU
38038 #define A_PM_RX_DBG_STAT1 0x10022
38045 #define M_RX_FREE_OSPI_CNT0    0xfffU
38050 #define M_RX_PCMD0_FLIT_LEN    0xfffU
38055 #define M_RX_PCMD0_CMD    0xfU
38063 #define S_RX_PCMD0_BYPASS    0
38067 #define A_PM_RX_DBG_STAT2 0x10023
38074 #define M_RX_FREE_OSPI_CNT1    0xfffU
38079 #define M_RX_PCMD1_FLIT_LEN    0xfffU
38084 #define M_RX_PCMD1_CMD    0xfU
38092 #define S_RX_PCMD1_BYPASS    0
38096 #define A_PM_RX_DBG_STAT3 0x10024
38099 #define M_RX_SET_PCMD_RES_RDY_RD    0x3U
38104 #define M_RX_ISSUED_PREFETCH_RD_E_CLR    0x3U
38109 #define M_RX_ISSUED_PREFETCH_RD    0x3U
38114 #define M_RX_PCMD_RES_RDY    0x3U
38123 #define M_RX_FIRST_BUNDLE    0x3U
38127 #define S_RX_SDC_DRDY    0
38131 #define A_PM_RX_DBG_STAT4 0x10025
38142 #define M_RX_PCMD_FROM_CH    0x3U
38147 #define M_RX_LINE    0x1fU
38152 #define M_RX_IESPI_TXVALID    0xfU
38157 #define M_RX_IESPI_TXFULL    0xfU
38162 #define M_RX_PCMD_SRDY    0x3U
38167 #define M_RX_PCMD_DRDY    0x3U
38172 #define M_RX_PCMD_CMD    0xfU
38176 #define S_DUPLICATE    0
38177 #define M_DUPLICATE    0x3U
38182 #define M_RX_PCMD_SRDY_STAT4    0x3U
38187 #define M_RX_PCMD_DRDY_STAT4    0x3U
38191 #define A_PM_RX_DBG_STAT5 0x10026
38202 #define M_T5_RX_PCMD_DRDY    0x3U
38207 #define M_T5_RX_PCMD_SRDY    0x3U
38212 #define M_RX_ISPI_TXVALID    0xfU
38217 #define M_RX_ISPI_FULL    0xfU
38222 #define M_RX_OSPI_TXVALID    0x3U
38227 #define M_RX_OSPI_FULL    0x3U
38232 #define M_RX_E_RXVALID    0xfU
38237 #define M_RX_E_RXAFULL    0xfU
38242 #define M_RX_C_TXVALID    0x3U
38246 #define S_RX_C_TXAFULL    0
38247 #define M_RX_C_TXAFULL    0x3U
38251 #define A_PM_RX_DBG_STAT6 0x10027
38254 #define M_RX_M_INTRNL_FIFO_CNT    0x3U
38270 #define S_RX_M_REQDATARDY    0
38275 #define M_T6_RX_M_INTRNL_FIFO_CNT    0x3U
38291 #define A_PM_RX_DBG_STAT7 0x10028
38294 #define M_RX_PCMD1_FREE_CNT    0x7fU
38298 #define S_RX_PCMD0_FREE_CNT    0
38299 #define M_RX_PCMD0_FREE_CNT    0x7fU
38303 #define A_PM_RX_DBG_STAT8 0x10029
38306 #define M_RX_IN_EOP_CNT3    0xfU
38311 #define M_RX_IN_EOP_CNT2    0xfU
38316 #define M_RX_IN_EOP_CNT1    0xfU
38321 #define M_RX_IN_EOP_CNT0    0xfU
38326 #define M_RX_IN_SOP_CNT3    0xfU
38331 #define M_RX_IN_SOP_CNT2    0xfU
38336 #define M_RX_IN_SOP_CNT1    0xfU
38340 #define S_RX_IN_SOP_CNT0    0
38341 #define M_RX_IN_SOP_CNT0    0xfU
38345 #define A_PM_RX_DBG_STAT9 0x1002a
38348 #define M_RX_RSVD0    0xfU
38353 #define M_RX_RSVD1    0xfU
38358 #define M_RX_OUT_EOP_CNT1    0xfU
38363 #define M_RX_OUT_EOP_CNT0    0xfU
38368 #define M_RX_RSVD2    0xfU
38373 #define M_RX_RSVD3    0xfU
38378 #define M_RX_OUT_SOP_CNT1    0xfU
38382 #define S_RX_OUT_SOP_CNT0    0
38383 #define M_RX_OUT_SOP_CNT0    0xfU
38387 #define A_PM_RX_DBG_STAT10 0x1002b
38394 #define M_RX_CH1_DEFICIT    0xfffU
38398 #define S_RX_CH0_DEFICIT    0
38399 #define M_RX_CH0_DEFICIT    0xfffU
38403 #define A_PM_RX_DBG_STAT11 0x1002c
38406 #define M_RX_BUNDLE_LEN_SRDY    0x3U
38411 #define M_RX_RSVD11_1    0x3U
38416 #define M_RX_BUNDLE_LEN1    0xfffU
38421 #define M_RX_RSVD11    0xfU
38425 #define S_RX_BUNDLE_LEN0    0
38426 #define M_RX_BUNDLE_LEN0    0xfffU
38430 #define A_PM_RX_INT_CAUSE_MASK_HALT_2 0x10049
38431 #define A_PM_RX_INT_ENABLE_2 0x10060
38481 #define S_OCSPI3_OFIFO2X_TX_FRAMING_ERROR    0
38485 #define A_PM_RX_INT_CAUSE_2 0x10061
38486 #define A_PM_RX_PERR_ENABLE 0x10062
38568 #define A_PM_RX_PERR_CAUSE 0x10063
38569 #define A_PM_RX_EXT_CFIFO_CONFIG0 0x10070
38572 #define M_CH1_PTR_MAX    0x7fffU
38577 #define M_CH0_PTR_MAX    0x7fffU
38581 #define S_STROBE    0
38585 #define A_PM_RX_EXT_CFIFO_CONFIG1 0x10071
38588 #define M_CH2_PTR_MAX    0x7fffU
38592 #define A_PM_RX_EXT_EFIFO_CONFIG0 0x10072
38593 #define A_PM_RX_EXT_EFIFO_CONFIG1 0x10073
38594 #define A_T7_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x10074
38595 #define A_T7_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x10075
38596 #define A_PM_RX_CH2_OSPI_DEFICIT_THRSHLD 0x10076
38597 #define A_PM_RX_CH3_OSPI_DEFICIT_THRSHLD 0x10077
38598 #define A_T7_PM_RX_FEATURE_EN 0x10078
38599 #define A_PM_RX_TCAM_BIST_CTRL 0x10080
38600 #define A_PM_RX_TCAM_BIST_CB_PASS 0x10081
38601 #define A_PM_RX_TCAM_BIST_CB_BUSY 0x10082
38604 #define PM_TX_BASE_ADDR 0x8fe0
38606 #define A_PM_TX_CFG 0x8fe0
38609 #define M_CH3_OUTPUT    0x1fU
38613 #define A_PM_TX_MODE 0x8fe4
38616 #define M_CONG_THRESH3    0x7fU
38621 #define M_CONG_THRESH2    0x7fU
38626 #define M_CONG_THRESH1    0x7fU
38631 #define M_CONG_THRESH0    0x7fU
38640 #define M_STAT_CHANNEL    0x3U
38644 #define A_PM_TX_STAT_CONFIG 0x8fe8
38645 #define A_PM_TX_STAT_COUNT 0x8fec
38646 #define A_PM_TX_STAT_LSB 0x8ff0
38647 #define A_PM_TX_DBG_CTRL 0x8ff0
38650 #define M_OSPIWRBUSY    0xfU
38654 #define A_PM_TX_STAT_MSB 0x8ff4
38655 #define A_PM_TX_DBG_DATA 0x8ff4
38656 #define A_PM_TX_INT_ENABLE 0x8ff8
38778 #define S_C_PCMD_PAR_ERROR    0
38890 #define S_T7_OESPI3_OFIFO2X_TX_FRAMING_ERROR    0
38894 #define A_PM_TX_INT_CAUSE 0x8ffc
38904 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
38905 #define A_T7_PM_TX_DBG_STAT_MSB 0x10000
38906 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
38907 #define A_T7_PM_TX_DBG_STAT_LSB 0x10001
38908 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
38909 #define A_T7_PM_TX_DBG_RSVD_FLIT_CNT 0x10002
38910 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
38911 #define A_T7_PM_TX_SDC_EN 0x10003
38912 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
38913 #define A_T7_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x10004
38914 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
38915 #define A_T7_PM_TX_INOUT_FIFO_DBG_WR 0x10005
38916 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
38917 #define A_T7_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10006
38918 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
38919 #define A_T7_PM_TX_FEATURE_EN 0x10007
38922 #define M_IN_AFULL_TH    0x3U
38930 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
38931 #define A_T7_PM_TX_T5_PM_TX_INT_ENABLE 0x10008
38932 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
38933 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10009
38934 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
38935 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x1000a
38936 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
38937 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x1000b
38938 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
38939 #define A_T7_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x1000c
38940 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
38941 #define A_T7_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x1000d
38942 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
38943 #define A_T7_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x1000e
38944 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
38945 #define A_T7_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x1000f
38946 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
38947 #define A_T7_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x10010
38948 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
38949 #define A_T7_PM_TX_INT_CAUSE_MASK_HALT 0x10011
38950 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
38951 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
38952 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
38953 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
38954 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
38955 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
38956 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
38957 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
38958 #define A_PM_TX_DBG_STAT_MSB 0x1001a
38959 #define A_PM_TX_DBG_STAT_LSB 0x1001b
38960 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
38961 #define A_PM_TX_SDC_EN 0x1001d
38962 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
38963 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
38964 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
38965 #define A_PM_TX_FEATURE_EN 0x10021
38975 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
39005 #define S_SDC_ERR_EN    0
39025 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
39026 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
39027 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
39028 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
39029 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
39030 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
39031 #define A_PM_TX_PERR_ENABLE 0x10028
39069 #define S_C_PCMD_TOKEN_PAR_ERROR    0
39073 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
39075 #define S_CH2_OSPI_DEFICIT_THRSHLD    0
39076 #define M_CH2_OSPI_DEFICIT_THRSHLD    0xfffU
39080 #define A_PM_TX_PERR_CAUSE 0x10029
39081 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
39083 #define S_CH3_OSPI_DEFICIT_THRSHLD    0
39084 #define M_CH3_OSPI_DEFICIT_THRSHLD    0xfffU
39088 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
39089 #define A_PM_TX_DBG_STAT0 0x1002c
39132 #define M_PCMD_FB_CMD    0xfU
39136 #define S_CUR_PCMD_LEN    0
39137 #define M_CUR_PCMD_LEN    0xffffU
39169 #define A_PM_TX_DBG_STAT1 0x1002d
39176 #define M_FREE_OESPI_CNT0    0xfffU
39181 #define M_PCMD_FLIT_LEN0    0xfffU
39186 #define M_PCMD_CMD0    0xfU
39198 #define S_BYPASS0    0
39202 #define A_PM_TX_DBG_STAT2 0x1002e
39209 #define M_FREE_OESPI_CNT1    0xfffU
39214 #define M_PCMD_FLIT_LEN1    0xfffU
39219 #define M_PCMD_CMD1    0xfU
39231 #define S_BYPASS1    0
39235 #define A_PM_TX_DBG_STAT3 0x1002f
39242 #define M_FREE_OESPI_CNT2    0xfffU
39247 #define M_PCMD_FLIT_LEN2    0xfffU
39252 #define M_PCMD_CMD2    0xfU
39264 #define S_BYPASS2    0
39268 #define A_PM_TX_DBG_STAT4 0x10030
39275 #define M_FREE_OESPI_CNT3    0xfffU
39280 #define M_PCMD_FLIT_LEN3    0xfffU
39285 #define M_PCMD_CMD3    0xfU
39297 #define S_BYPASS3    0
39301 #define A_PM_TX_DBG_STAT5 0x10031
39304 #define M_SET_PCMD_RES_RDY_RD    0xfU
39309 #define M_ISSUED_PREF_RD_ER_CLR    0xfU
39314 #define M_ISSUED_PREF_RD    0xfU
39319 #define M_PCMD_RES_RDY    0xfU
39336 #define M_FIRST_BUNDLE    0xfU
39341 #define M_GCSUM_MORE_THAN_2_LEFT    0xfU
39345 #define S_SDC_DRDY    0
39349 #define A_PM_TX_DBG_STAT6 0x10032
39356 #define M_PCMD_CH    0x3U
39361 #define M_STATE_MACHINE_LOC    0x1fU
39366 #define M_ICSPI_TXVALID    0xfU
39371 #define M_ICSPI_TXFULL    0xfU
39376 #define M_PCMD_SRDY    0xfU
39381 #define M_PCMD_DRDY    0xfU
39386 #define M_PCMD_CMD    0xfU
39402 #define S_OEFIFO_FULL0    0
39406 #define A_PM_TX_DBG_STAT7 0x10033
39409 #define M_ICSPI_RXVALID    0xfU
39414 #define M_ICSPI_RXFULL    0xfU
39419 #define M_OESPI_VALID    0xfU
39424 #define M_OESPI_FULL    0xfU
39429 #define M_C_RXVALID    0xfU
39434 #define M_C_RXAFULL    0xfU
39466 #define S_E_TXFULL0    0
39470 #define A_PM_TX_DBG_STAT8 0x10034
39473 #define M_MC_RSP_FIFO_CNT    0x3U
39478 #define M_PCMD_FREE_CNT0    0x3ffU
39483 #define M_PCMD_FREE_CNT1    0x3ffU
39499 #define S_M_REQDATARDY    0
39504 #define M_T6_MC_RSP_FIFO_CNT    0x3U
39509 #define M_T6_PCMD_FREE_CNT0    0x3ffU
39514 #define M_T6_PCMD_FREE_CNT1    0x3ffU
39530 #define A_PM_TX_DBG_STAT9 0x10035
39533 #define M_PCMD_FREE_CNT2    0x3ffU
39537 #define S_PCMD_FREE_CNT3    0
39538 #define M_PCMD_FREE_CNT3    0x3ffU
39542 #define A_PM_TX_DBG_STAT10 0x10036
39545 #define M_IN_EOP_CNT3    0xfU
39550 #define M_IN_EOP_CNT2    0xfU
39555 #define M_IN_EOP_CNT1    0xfU
39560 #define M_IN_EOP_CNT0    0xfU
39565 #define M_IN_SOP_CNT3    0xfU
39570 #define M_IN_SOP_CNT2    0xfU
39575 #define M_IN_SOP_CNT1    0xfU
39579 #define S_IN_SOP_CNT0    0
39580 #define M_IN_SOP_CNT0    0xfU
39584 #define A_PM_TX_DBG_STAT11 0x10037
39587 #define M_OUT_EOP_CNT3    0xfU
39592 #define M_OUT_EOP_CNT2    0xfU
39597 #define M_OUT_EOP_CNT1    0xfU
39602 #define M_OUT_EOP_CNT0    0xfU
39607 #define M_OUT_SOP_CNT3    0xfU
39612 #define M_OUT_SOP_CNT2    0xfU
39617 #define M_OUT_SOP_CNT1    0xfU
39621 #define S_OUT_SOP_CNT0    0
39622 #define M_OUT_SOP_CNT0    0xfU
39626 #define A_PM_TX_DBG_STAT12 0x10038
39627 #define A_PM_TX_DBG_STAT13 0x10039
39634 #define M_CH1_DEFICIT    0xfffU
39638 #define S_CH0_DEFICIT    0
39639 #define M_CH0_DEFICIT    0xfffU
39643 #define A_PM_TX_DBG_STAT14 0x1003a
39646 #define M_CH3_DEFICIT    0xfffU
39650 #define S_CH2_DEFICIT    0
39651 #define M_CH2_DEFICIT    0xfffU
39655 #define A_PM_TX_DBG_STAT15 0x1003b
39658 #define M_BUNDLE_LEN_SRDY    0xfU
39663 #define M_BUNDLE_LEN1    0xfffU
39667 #define S_BUNDLE_LEN0    0
39668 #define M_BUNDLE_LEN0    0xfffU
39673 #define M_T6_BUNDLE_LEN_SRDY    0x3U
39678 #define M_T6_BUNDLE_LEN1    0xfffU
39682 #define A_PM_TX_DBG_STAT16 0x1003c
39685 #define M_BUNDLE_LEN3    0xfffU
39689 #define S_BUNDLE_LEN2    0
39690 #define M_BUNDLE_LEN2    0xfffU
39695 #define MPS_BASE_ADDR 0x9000
39697 #define A_MPS_PORT_CTL 0x0
39724 #define M_PRIOPPPENMAP    0xffU
39728 #define A_MPS_VF_CTL 0x0
39729 #define A_MPS_PORT_PAUSE_CTL 0x4
39731 #define S_TIMEUNIT    0
39732 #define M_TIMEUNIT    0xffffU
39736 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
39739 #define M_REGSENDOFF    0xffU
39744 #define M_REGSENDON    0xffU
39749 #define M_SGESENDEN    0xffU
39753 #define S_RXSENDEN    0
39754 #define M_RXSENDEN    0xffU
39758 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
39760 #define S_XOFFDISABLE    0
39764 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
39767 #define M_REGHALTON    0xffU
39771 #define S_RXHALTEN    0
39772 #define M_RXHALTEN    0xffU
39776 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
39779 #define M_REGSENDING    0xffU
39784 #define M_SGESENDING    0xffU
39788 #define S_RXSENDING    0
39789 #define M_RXSENDING    0xffU
39793 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
39796 #define M_REGHALTED    0xffU
39800 #define S_RXHALTED    0
39801 #define M_RXHALTED    0xffU
39805 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
39806 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
39808 #define S_ADDR    0
39809 #define M_ADDR    0xffffU
39813 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
39814 #define A_MPS_VF_TX_MAC_DROP_PP 0x24
39815 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
39816 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
39819 #define M_PRTY7    0x3U
39824 #define M_PRTY6    0x3U
39829 #define M_PRTY5    0x3U
39834 #define M_PRTY4    0x3U
39839 #define M_PRTY3    0x3U
39844 #define M_PRTY2    0x3U
39849 #define M_PRTY1    0x3U
39853 #define S_PRTY0    0
39854 #define M_PRTY0    0x3U
39858 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
39861 #define M_TXPRTY7    0xfU
39866 #define M_TXPRTY6    0xfU
39871 #define M_TXPRTY5    0xfU
39876 #define M_TXPRTY4    0xfU
39881 #define M_TXPRTY3    0xfU
39886 #define M_TXPRTY2    0xfU
39891 #define M_TXPRTY1    0xfU
39895 #define S_TXPRTY0    0
39896 #define M_TXPRTY0    0xfU
39900 #define A_MPS_PORT_PRTY_GROUP_MAP 0x34
39901 #define A_MPS_PORT_TRACE_MAX_CAPTURE_SIZE 0x38
39904 #define M_TX2RX    0x7U
39909 #define M_MAC2MPS    0x7U
39913 #define S_MPS2MAC    0
39914 #define M_MPS2MAC    0x7U
39918 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
39919 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
39920 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
39921 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
39922 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
39923 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
39924 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
39925 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
39926 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
39927 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
39928 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
39929 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
39930 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
39931 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
39932 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
39933 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
39934 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
39935 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
39936 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
39937 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
39938 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
39939 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
39940 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
39941 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
39942 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
39943 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
39944 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
39945 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
39946 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
39947 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
39948 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
39949 #define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_L 0xf8
39950 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
39951 #define A_MPS_VF_STAT_RX_VF_ERR_DROP_FRAMES_H 0xfc
39952 #define A_MPS_PORT_RX_CTL 0x100
39959 #define M_RPLCT_SEL_L    0x3U
40031 #define S_OVLAN_EN0    0
40075 #define A_MPS_PORT_RX_MTU 0x104
40076 #define A_MPS_PORT_RX_PF_MAP 0x108
40077 #define A_MPS_PORT_RX_VF_MAP0 0x10c
40078 #define A_MPS_PORT_RX_VF_MAP1 0x110
40079 #define A_MPS_PORT_RX_VF_MAP2 0x114
40080 #define A_MPS_PORT_RX_VF_MAP3 0x118
40081 #define A_MPS_PORT_RX_IVLAN 0x11c
40083 #define S_IVLAN_ETYPE    0
40084 #define M_IVLAN_ETYPE    0xffffU
40088 #define A_MPS_PORT_RX_OVLAN0 0x120
40091 #define M_OVLAN_MASK    0xffffU
40095 #define S_OVLAN_ETYPE    0
40096 #define M_OVLAN_ETYPE    0xffffU
40100 #define A_MPS_PORT_RX_OVLAN1 0x124
40101 #define A_MPS_PORT_RX_OVLAN2 0x128
40102 #define A_MPS_PORT_RX_OVLAN3 0x12c
40103 #define A_MPS_PORT_RX_RSS_HASH 0x130
40104 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
40107 #define M_RSS_CTRL    0xffU
40111 #define S_QUE_NUM    0
40112 #define M_QUE_NUM    0xffffU
40116 #define A_MPS_PORT_RX_CTL1 0x138
40131 #define M_FIXED_PF    0x7U
40139 #define S_FIXED_VF    0
40140 #define M_FIXED_VF    0x7fU
40157 #define M_T6_FIXED_PF    0x7U
40165 #define S_T6_FIXED_VF    0
40166 #define M_T6_FIXED_VF    0xffU
40170 #define A_MPS_PORT_RX_SPARE 0x13c
40171 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
40172 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
40173 #define A_MPS_PORT_RX_TS_VLD 0x148
40175 #define S_TS_VLD    0
40176 #define M_TS_VLD    0x3U
40180 #define A_MPS_PORT_RX_TNL_LKP_INNER_SEL 0x14c
40182 #define S_LKP_SEL    0
40186 #define A_MPS_PORT_RX_VF_MAP4 0x150
40187 #define A_MPS_PORT_RX_VF_MAP5 0x154
40188 #define A_MPS_PORT_RX_VF_MAP6 0x158
40189 #define A_MPS_PORT_RX_VF_MAP7 0x15c
40190 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_MAC 0x160
40292 #define A_MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK 0x164
40306 #define A_MPS_PORT_RX_REPL_VECT_SEL 0x168
40312 #define S_REPL_VECT_SEL    0
40313 #define M_REPL_VECT_SEL    0xfU
40317 #define A_MPS_PORT_MAC_RX_DROP_EN_PP 0x16c
40319 #define S_PRIO    0
40320 #define M_PRIO    0xffU
40324 #define A_MPS_PORT_RX_INT_RSS_HASH 0x170
40325 #define A_MPS_PORT_RX_INT_RSS_CONTROL 0x174
40326 #define A_MPS_PORT_RX_CNT_DBG_CTL 0x178
40328 #define S_DBG_TYPE    0
40329 #define M_DBG_TYPE    0x1fU
40333 #define A_MPS_PORT_RX_CNT_DBG 0x17c
40334 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
40336 #define S_CREDIT    0
40337 #define M_CREDIT    0xffffU
40341 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
40342 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
40343 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
40344 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
40345 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
40346 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
40347 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
40348 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
40349 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
40350 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
40353 #define M_FIFOTH    0x1ffU
40361 #define S_MAXPKTCNT    0
40362 #define M_MAXPKTCNT    0xfU
40367 #define M_OUT_TH    0xffU
40372 #define M_IN_TH    0xffU
40376 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
40378 #define S_FPGAPAUSEEN    0
40382 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
40385 #define M_OFF_PENDING    0xffU
40389 #define S_ON_PENDING    0
40390 #define M_ON_PENDING    0xffU
40394 #define A_MPS_PORT_TX_MAC_DROP_PP 0x1d4
40395 #define A_MPS_PORT_TX_LPBK_DROP_PP 0x1d8
40396 #define A_MPS_PORT_TX_MAC_DROP_CNT 0x1dc
40397 #define A_MPS_PORT_TX_LPBK_DROP_CNT 0x1e0
40398 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
40405 #define M_HASHPORTMAP    0xfU
40414 #define M_PRIORITY    0x7U
40423 #define M_PF    0x7U
40431 #define S_VF    0
40432 #define M_VF    0x7fU
40449 #define M_T6_HASHPORTMAP    0xfU
40458 #define M_T6_PRIORITY    0x7U
40467 #define M_T6_PF    0x7U
40475 #define S_T6_VF    0
40476 #define M_T6_VF    0xffU
40480 #define A_MPS_PF_CTL 0x2c0
40486 #define S_RXEN    0
40490 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
40493 #define M_PROTOCOLID    0xffffU
40498 #define M_VLAN_PRIO    0x7U
40506 #define S_TAG    0
40507 #define M_TAG    0xfffU
40511 #define A_MPS_PF_TX_MAC_DROP_PP 0x2e4
40513 #define S_T7_DROPEN    0
40514 #define M_T7_DROPEN    0xffU
40518 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
40519 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
40520 #define A_MPS_PORT_CLS_HASH_CTL 0x304
40526 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
40527 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
40533 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
40534 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
40535 #define A_MPS_PORT_CLS_BMC_MAC0_ADDR_L 0x30c
40536 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
40537 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
40551 #define A_MPS_PORT_CLS_BMC_MAC0_ADDR_H 0x310
40552 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
40553 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
40563 #define A_MPS_PORT_CLS_BMC_VLAN0 0x314
40564 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
40565 #define A_MPS_PORT_CLS_CTL 0x318
40567 #define S_PF_VLAN_SEL    0
40584 #define M_LPBK_SMAC_TCAM_SEL    0x3U
40589 #define M_LPBK_DMAC_TCAM_SEL    0x3U
40606 #define M_SMAC_TCAM_SEL    0x3U
40611 #define M_DMAC_TCAM_SEL    0x3U
40627 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
40628 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE 0x31c
40630 #define S_ETHTYPE2    0
40631 #define M_ETHTYPE2    0xffffU
40635 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
40636 #define A_MPS_PORT_CLS_NCSI_ETH_TYPE_EN 0x320
40642 #define S_EN2    0
40646 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
40647 #define A_MPS_PORT_CLS_BMC_MAC1_ADDR_L 0x324
40648 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
40649 #define A_MPS_PORT_CLS_BMC_MAC1_ADDR_H 0x328
40650 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
40651 #define A_MPS_PORT_CLS_BMC_MAC2_ADDR_L 0x32c
40652 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
40653 #define A_MPS_PORT_CLS_BMC_MAC2_ADDR_H 0x330
40654 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
40655 #define A_MPS_PORT_CLS_BMC_MAC3_ADDR_L 0x334
40656 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
40657 #define A_MPS_PORT_CLS_BMC_MAC3_ADDR_H 0x338
40658 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
40659 #define A_MPS_PORT_CLS_BMC_VLAN1 0x33c
40660 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
40661 #define A_MPS_PORT_CLS_BMC_VLAN2 0x340
40662 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
40663 #define A_MPS_PORT_CLS_BMC_VLAN3 0x344
40664 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
40665 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
40666 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
40667 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
40668 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
40669 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
40670 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
40671 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
40672 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
40673 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
40674 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
40675 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
40676 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
40677 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
40678 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
40679 #define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_L 0x380
40680 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
40681 #define A_MPS_PF_STAT_RX_PF_ERR_DROP_FRAMES_H 0x384
40682 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
40683 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
40684 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
40685 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
40686 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
40687 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
40688 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
40689 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
40690 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
40691 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
40692 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
40693 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
40694 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
40695 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
40696 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
40697 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
40698 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
40699 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
40700 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
40701 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
40702 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
40703 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
40704 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
40705 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
40706 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
40707 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
40708 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
40709 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
40710 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
40711 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
40712 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
40713 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
40714 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
40715 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
40716 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
40717 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
40718 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
40719 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
40720 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
40721 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
40722 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
40723 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
40724 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
40725 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
40726 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
40727 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
40728 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
40729 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
40730 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
40731 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
40732 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
40733 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
40734 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
40735 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
40736 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
40737 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
40738 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
40739 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
40740 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
40741 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
40742 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
40743 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
40744 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
40745 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
40746 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
40747 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
40748 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
40749 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
40750 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
40751 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
40752 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
40753 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
40754 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
40755 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
40756 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
40757 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
40758 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
40759 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
40760 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
40761 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
40762 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
40763 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
40764 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
40765 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
40766 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
40767 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
40768 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
40769 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
40770 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
40771 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
40772 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
40773 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
40774 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
40775 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
40776 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
40777 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
40778 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
40779 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
40780 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
40781 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
40782 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
40783 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
40784 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
40785 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
40786 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
40787 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
40788 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
40789 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
40790 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
40791 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
40792 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
40793 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
40794 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
40795 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
40796 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
40797 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
40798 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
40799 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
40800 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
40801 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
40802 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
40803 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
40804 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
40805 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
40806 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
40807 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
40808 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
40809 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
40810 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
40811 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
40812 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
40813 #define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_L 0x620
40814 #define A_MPS_PORT_STAT_RX_PRIO_0_DROP_FRAME_H 0x624
40815 #define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_L 0x628
40816 #define A_MPS_PORT_STAT_RX_PRIO_1_DROP_FRAME_H 0x62c
40817 #define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_L 0x630
40818 #define A_MPS_PORT_STAT_RX_PRIO_2_DROP_FRAME_H 0x634
40819 #define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_L 0x638
40820 #define A_MPS_PORT_STAT_RX_PRIO_3_DROP_FRAME_H 0x63c
40821 #define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_L 0x640
40822 #define A_MPS_PORT_STAT_RX_PRIO_4_DROP_FRAME_H 0x644
40823 #define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_L 0x648
40824 #define A_MPS_PORT_STAT_RX_PRIO_5_DROP_FRAME_H 0x64c
40825 #define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_L 0x650
40826 #define A_MPS_PORT_STAT_RX_PRIO_6_DROP_FRAME_H 0x654
40827 #define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_L 0x658
40828 #define A_MPS_PORT_STAT_RX_PRIO_7_DROP_FRAME_H 0x65c
40829 #define A_MPS_CMN_CTL 0x9000
40839 #define S_NUMPORTS    0
40840 #define M_NUMPORTS    0x3U
40857 #define M_SPEEDMODE    0x3U
40878 #define M_PBUS_EN    0x3U
40883 #define M_INIC_EN    0x3U
40888 #define M_SBA_EN    0x3U
40897 #define M_MPS_LB_MODE    0x3U
40901 #define A_MPS_INT_ENABLE 0x9004
40923 #define S_PLINTENB    0
40927 #define A_MPS_INT_CAUSE 0x9008
40949 #define S_PLINT    0
40953 #define A_MPS_CGEN_GLOBAL 0x900c
40955 #define S_MPS_GLOBAL_CGEN    0
40959 #define A_MPS_VF_TX_CTL_31_0 0x9010
40960 #define A_MPS_VF_TX_CTL_63_32 0x9014
40961 #define A_MPS_VF_TX_CTL_95_64 0x9018
40962 #define A_MPS_VF_TX_CTL_127_96 0x901c
40963 #define A_MPS_VF_RX_CTL_31_0 0x9020
40964 #define A_MPS_VF_RX_CTL_63_32 0x9024
40965 #define A_MPS_VF_RX_CTL_95_64 0x9028
40966 #define A_MPS_VF_RX_CTL_127_96 0x902c
40967 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
40969 #define S_VALUE    0
40970 #define M_VALUE    0xffffU
40974 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
40975 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
40976 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
40977 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
40978 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
40979 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
40980 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
40981 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
40983 #define S_WEIGHT    0
40984 #define M_WEIGHT    0xfffU
40988 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
40989 #define A_MPS_WOL_CTL_MODE 0x9058
40991 #define S_WOL_MODE    0
40995 #define A_MPS_FPGA_DEBUG 0x9060
41002 #define M_CH_MAP3    0x3U
41007 #define M_CH_MAP2    0x3U
41012 #define M_CH_MAP1    0x3U
41016 #define S_CH_MAP0    0
41017 #define M_CH_MAP0    0x3U
41022 #define M_FPGA_PTP_PORT    0x3U
41026 #define A_MPS_DEBUG_CTL 0x9068
41033 #define M_DBGSEL_H    0x1fU
41041 #define S_DBGSEL_L    0
41042 #define M_DBGSEL_L    0x1fU
41046 #define A_MPS_DEBUG_DATA_REG_L 0x906c
41047 #define A_MPS_DEBUG_DATA_REG_H 0x9070
41048 #define A_MPS_TOP_SPARE 0x9074
41051 #define M_TOPSPARE    0xffffffU
41083 #define S_OVLANSELMAC0    0
41088 #define M_T5_TOPSPARE    0xffffffU
41092 #define A_MPS_T5_BUILD_REVISION 0x9078
41093 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
41096 #define M_VALUE_1    0xffffU
41100 #define S_VALUE_0    0
41101 #define M_VALUE_0    0xffffU
41105 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
41106 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
41107 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
41108 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
41109 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
41110 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
41111 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
41112 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
41113 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
41114 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
41115 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
41116 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
41117 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
41118 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
41119 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
41120 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
41121 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
41122 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
41123 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
41124 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
41125 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
41126 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
41127 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
41128 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
41129 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
41130 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
41131 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
41132 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
41133 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
41134 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
41135 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
41136 #define A_MPS_BUILD_REVISION 0x90fc
41137 #define A_MPS_VF_TX_CTL_159_128 0x9100
41138 #define A_MPS_VF_TX_CTL_191_160 0x9104
41139 #define A_MPS_VF_TX_CTL_223_192 0x9108
41140 #define A_MPS_VF_TX_CTL_255_224 0x910c
41141 #define A_MPS_VF_RX_CTL_159_128 0x9110
41142 #define A_MPS_VF_RX_CTL_191_160 0x9114
41143 #define A_MPS_VF_RX_CTL_223_192 0x9118
41144 #define A_MPS_VF_RX_CTL_255_224 0x911c
41145 #define A_MPS_FPGA_BIST_CFG_P0 0x9120
41148 #define M_ADDRMASK    0xffffU
41152 #define S_T6_BASEADDR    0
41153 #define M_T6_BASEADDR    0xffffU
41157 #define A_MPS_FPGA_BIST_CFG_P1 0x9124
41158 #define A_MPS_FPGA_BIST_CFG_P2 0x9128
41159 #define A_MPS_FPGA_BIST_CFG_P3 0x912c
41160 #define A_MPS_INIC_CTL 0x9130
41166 #define A_MPS_INIC_DATA 0x9134
41167 #define A_MPS_TP_CSIDE_MUX_CTL_P2 0x9138
41168 #define A_MPS_TP_CSIDE_MUX_CTL_P3 0x913c
41169 #define A_MPS_RED_CTL 0x9140
41172 #define M_LPBK_SHIFT_0    0xfU
41177 #define M_LPBK_SHIFT_1    0xfU
41182 #define M_LPBK_SHIFT_2    0xfU
41187 #define M_LPBK_SHIFT_3    0xfU
41192 #define M_MAC_SHIFT_0    0xfU
41197 #define M_MAC_SHIFT_1    0xfU
41202 #define M_MAC_SHIFT_2    0xfU
41206 #define S_MAC_SHIFT_3    0
41207 #define M_MAC_SHIFT_3    0xfU
41211 #define A_MPS_RED_EN 0x9144
41241 #define S_MAC_EN0    0
41245 #define A_MPS_MAC0_RED_DROP_CNT_H 0x9148
41246 #define A_MPS_MAC0_RED_DROP_CNT_L 0x914c
41247 #define A_MPS_MAC1_RED_DROP_CNT_H 0x9150
41248 #define A_MPS_MAC1_RED_DROP_CNT_L 0x9154
41249 #define A_MPS_MAC2_RED_DROP_CNT_H 0x9158
41250 #define A_MPS_MAC2_RED_DROP_CNT_L 0x915c
41251 #define A_MPS_MAC3_RED_DROP_CNT_H 0x9160
41252 #define A_MPS_MAC3_RED_DROP_CNT_L 0x9164
41253 #define A_MPS_LPBK0_RED_DROP_CNT_H 0x9168
41254 #define A_MPS_LPBK0_RED_DROP_CNT_L 0x916c
41255 #define A_MPS_LPBK1_RED_DROP_CNT_H 0x9170
41256 #define A_MPS_LPBK1_RED_DROP_CNT_L 0x9174
41257 #define A_MPS_LPBK2_RED_DROP_CNT_H 0x9178
41258 #define A_MPS_LPBK2_RED_DROP_CNT_L 0x917c
41259 #define A_MPS_LPBK3_RED_DROP_CNT_H 0x9180
41260 #define A_MPS_LPBK3_RED_DROP_CNT_L 0x9184
41261 #define A_MPS_MAC_RED_PP_DROP_EN 0x9188
41264 #define M_T7_MAC3    0xffU
41269 #define M_T7_MAC2    0xffU
41274 #define M_T7_MAC1    0xffU
41278 #define S_T7_MAC0    0
41279 #define M_T7_MAC0    0xffU
41283 #define A_MPS_TX_PRTY_SEL 0x9400
41286 #define M_CH4_PRTY    0x7U
41291 #define M_CH3_PRTY    0x7U
41296 #define M_CH2_PRTY    0x7U
41301 #define M_CH1_PRTY    0x7U
41306 #define M_CH0_PRTY    0x7U
41311 #define M_TP_SOURCE    0x3U
41315 #define S_NCSI_SOURCE    0
41316 #define M_NCSI_SOURCE    0x3U
41321 #define M_T7_CH4_PRTY    0x7U
41326 #define M_T7_CH3_PRTY    0x7U
41331 #define M_T7_CH2_PRTY    0x7U
41336 #define M_T7_CH1_PRTY    0x7U
41340 #define A_MPS_TX_INT_ENABLE 0x9404
41359 #define M_TXDESCFIFO    0xfU
41364 #define M_TXDATAFIFO    0xfU
41372 #define S_TPFIFO    0
41373 #define M_TPFIFO    0xfU
41394 #define M_TXTOKENFIFO    0x3ffU
41399 #define M_PERR_TP2MPS_TFIFO    0x3U
41403 #define A_MPS_TX_INT_CAUSE 0x9408
41404 #define A_MPS_TX_NCSI2MPS_CNT 0x940c
41405 #define A_MPS_TX_PERR_ENABLE 0x9410
41423 #define A_MPS_TX_PERR_INJECT 0x9414
41426 #define M_MPSTXMEMSEL    0x1fU
41430 #define A_MPS_TX_SE_CNT_TP01 0x9418
41431 #define A_MPS_TX_SE_CNT_TP23 0x941c
41432 #define A_MPS_TX_SE_CNT_MAC01 0x9420
41433 #define A_MPS_TX_SE_CNT_MAC23 0x9424
41434 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
41437 #define M_BUBBLEERR    0xffU
41442 #define M_SPI    0xffU
41446 #define S_SECNT    0
41447 #define M_SECNT    0xffU
41451 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
41454 #define M_BUBBLECLR    0xffU
41463 #define M_LPBKSECNT    0xfU
41467 #define A_MPS_TX_PORT_ERR 0x9430
41497 #define S_PT0    0
41501 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
41507 #define S_DROPEN    0
41511 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
41512 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
41513 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
41514 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
41525 #define M_SIZECH1    0x7U
41542 #define M_DATACH1    0xffU
41555 #define M_SIZECH0    0x7U
41571 #define S_DATACH0    0
41572 #define M_DATACH0    0xffU
41577 #define M_T5_SIZECH1    0xfU
41594 #define M_T5_DATACH1    0x7fU
41599 #define M_T5_SIZECH0    0xfU
41615 #define S_T5_DATACH0    0
41616 #define M_T5_DATACH0    0x7fU
41620 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
41631 #define M_SIZECH3    0x7U
41648 #define M_DATACH3    0xffU
41661 #define M_SIZECH2    0x7U
41677 #define S_DATACH2    0
41678 #define M_DATACH2    0xffU
41683 #define M_T5_SIZECH3    0xfU
41700 #define M_T5_DATACH3    0x7fU
41705 #define M_T5_SIZECH2    0xfU
41721 #define S_T5_DATACH2    0
41722 #define M_T5_DATACH2    0x7fU
41726 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
41737 #define M_SIZEPT1    0x7U
41754 #define M_DATAPT1    0xffU
41767 #define M_SIZEPT0    0x7U
41783 #define S_DATAPT0    0
41784 #define M_DATAPT0    0xffU
41789 #define M_T5_SIZEPT1    0xfU
41806 #define M_T5_DATAPT1    0x7fU
41811 #define M_T5_SIZEPT0    0xfU
41827 #define S_T5_DATAPT0    0
41828 #define M_T5_DATAPT0    0x7fU
41832 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
41843 #define M_SIZEPT3    0x7U
41860 #define M_DATAPT3    0xffU
41873 #define M_SIZEPT2    0x7U
41889 #define S_DATAPT2    0
41890 #define M_DATAPT2    0xffU
41895 #define M_T5_SIZEPT3    0xfU
41912 #define M_T5_DATAPT3    0x7fU
41917 #define M_T5_SIZEPT2    0xfU
41933 #define S_T5_DATAPT2    0
41934 #define M_T5_DATAPT2    0x7fU
41938 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
41940 #define S_SGEPAUSEIGNR    0
41941 #define M_SGEPAUSEIGNR    0xfU
41945 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
41947 #define S_T5SGEPAUSEIGNR    0
41948 #define M_T5SGEPAUSEIGNR    0xffffU
41952 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
41955 #define M_SUBPRTH    0x1fU
41960 #define M_PORTH    0x7U
41965 #define M_SUBPRTL    0x1fU
41969 #define S_PORTL    0
41970 #define M_PORTL    0x7U
41974 #define A_MPS_TX_PAD_CTL 0x945c
42004 #define S_MACPADENPT0    0
42008 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
42011 #define M_TP2MPS_CH3    0xffU
42016 #define M_TP2MPS_CH2    0xffU
42021 #define M_TP2MPS_CH1    0xffU
42025 #define S_TP2MPS_CH0    0
42026 #define M_TP2MPS_CH0    0xffU
42030 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
42032 #define S_NCSI_CH4    0
42033 #define M_NCSI_CH4    0xffU
42037 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
42059 #define S_TP2MPS_CH0_CLR    0
42063 #define A_MPS_TX_CGEN 0x946c
42149 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
42150 #define A_MPS_TX2RX_CH_MAP 0x9474
42164 #define S_ENABLELBK_CH0    0
42168 #define A_MPS_TX_DBG_CNT_CTL 0x9478
42170 #define S_DBG_CNT_CTL    0
42171 #define M_DBG_CNT_CTL    0xffU
42175 #define A_MPS_TX_DBG_CNT 0x947c
42176 #define A_MPS_TX_INT2_ENABLE 0x9498
42177 #define A_MPS_TX_INT2_CAUSE 0x949c
42178 #define A_MPS_TX_PERR2_ENABLE 0x94a0
42179 #define A_MPS_TX_INT3_ENABLE 0x94a4
42180 #define A_MPS_TX_INT3_CAUSE 0x94a8
42181 #define A_MPS_TX_PERR3_ENABLE 0x94ac
42182 #define A_MPS_TX_INT4_ENABLE 0x94b0
42183 #define A_MPS_TX_INT4_CAUSE 0x94b4
42184 #define A_MPS_TX_PERR4_ENABLE 0x94b8
42185 #define A_MPS_STAT_CTL 0x9600
42191 #define S_LPBKERRSTAT    0
42231 #define A_MPS_STAT_INT_ENABLE 0x9608
42233 #define S_PLREADSYNCERR    0
42237 #define A_MPS_STAT_INT_CAUSE 0x960c
42238 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
42245 #define M_RXVF    0x3U
42250 #define M_TXVF    0x3U
42255 #define M_RXPF    0x7U
42260 #define M_TXPF    0x3U
42265 #define M_RXPORT    0xfU
42270 #define M_LBPORT    0x7U
42274 #define S_TXPORT    0
42275 #define M_TXPORT    0xfU
42280 #define M_T5_RXBG    0x3U
42285 #define M_T5_RXPF    0x1fU
42290 #define M_T5_TXPF    0xfU
42295 #define M_T5_RXPORT    0x7fU
42300 #define M_T5_LBPORT    0x1fU
42304 #define S_T5_TXPORT    0
42305 #define M_T5_TXPORT    0x3fU
42309 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
42310 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
42311 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
42314 #define M_TX    0xffU
42319 #define M_TXPAUSEFIFO    0xfU
42323 #define S_DROP    0
42324 #define M_DROP    0xffU
42329 #define M_TXCH    0xfU
42333 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
42334 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
42335 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
42338 #define M_PAUSEFIFO    0xfU
42343 #define M_LPBK    0xfU
42348 #define M_NQ    0xffU
42353 #define M_PV    0xfU
42357 #define S_MAC    0
42358 #define M_MAC    0xfU
42362 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
42363 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
42364 #define A_MPS_STAT_PERR_INJECT 0x9634
42367 #define M_STATMEMSEL    0x7fU
42371 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
42374 #define M_STATSSUBPRTH    0x1fU
42378 #define S_STATSSUBPRTL    0
42379 #define M_STATSSUBPRTL    0x1fU
42384 #define M_STATSUBPRTH    0x1fU
42388 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
42389 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
42390 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
42391 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
42392 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
42393 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
42394 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
42395 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
42396 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
42397 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
42398 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
42399 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
42400 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
42401 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
42402 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
42403 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
42404 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
42405 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
42406 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
42407 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
42408 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
42409 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
42410 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
42411 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
42412 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
42413 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
42414 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
42415 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
42416 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
42417 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
42418 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
42419 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
42420 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
42423 #define M_T5_RXVF    0x7U
42427 #define S_T5_TXVF    0
42428 #define M_T5_TXVF    0x1fU
42432 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
42433 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
42434 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
42436 #define S_BGRX    0
42437 #define M_BGRX    0xfU
42441 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
42444 #define M_PTLPBK    0xfU
42449 #define M_PTTX    0xfU
42453 #define S_PTRX    0
42454 #define M_PTRX    0xfU
42458 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
42461 #define M_PFTX    0xffU
42465 #define S_PFRX    0
42466 #define M_PFRX    0xffU
42470 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
42471 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
42472 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
42473 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
42474 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
42475 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
42476 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
42477 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
42478 #define A_MPS_STAT_STOP_UPD_RX_VF_128_159 0x96f8
42479 #define A_MPS_STAT_STOP_UPD_RX_VF_160_191 0x96fc
42480 #define A_MPS_STAT_STOP_UPD_RX_VF_192_223 0x9700
42481 #define A_MPS_STAT_STOP_UPD_RX_VF_224_255 0x9704
42482 #define A_MPS_STAT_STOP_UPD_TX_VF_128_159 0x9710
42483 #define A_MPS_STAT_STOP_UPD_TX_VF_160_191 0x9714
42484 #define A_MPS_STAT_STOP_UPD_TX_VF_192_223 0x9718
42485 #define A_MPS_STAT_STOP_UPD_TX_VF_224_255 0x971c
42486 #define A_MPS_TRC_CFG 0x9800
42504 #define S_TRCMULTIFILTER    0
42512 #define A_MPS_TRC_RSS_HASH 0x9804
42513 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
42514 #define A_T7_MPS_TRC_PERR_INJECT 0x9804
42515 #define A_MPS_TRC_RSS_CONTROL 0x9808
42518 #define M_RSSCONTROL    0xffU
42522 #define S_QUEUENUMBER    0
42523 #define M_QUEUENUMBER    0xffffU
42527 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
42528 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
42543 #define M_TFPORT    0xfU
42556 #define M_TFLENGTH    0x1fU
42560 #define S_TFOFFSET    0
42561 #define M_TFOFFSET    0x1fU
42586 #define M_T5_TFPORT    0x1fU
42590 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
42593 #define M_TFMINPKTSIZE    0x1ffU
42597 #define S_TFCAPTUREMAX    0
42598 #define M_TFCAPTUREMAX    0x3fffU
42602 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
42604 #define S_TFRUNTSIZE    0
42605 #define M_TFRUNTSIZE    0x3fU
42609 #define A_MPS_TRC_FILTER_DROP 0x9840
42612 #define M_TFDROPINPCOUNT    0xffffU
42616 #define S_TFDROPBUFFERCOUNT    0
42617 #define M_TFDROPBUFFERCOUNT    0xffffU
42621 #define A_MPS_TRC_PERR_INJECT 0x9850
42624 #define M_TRCMEMSEL    0xfU
42628 #define A_MPS_TRC_PERR_ENABLE 0x9854
42635 #define M_PKTFIFO    0xfU
42639 #define S_FILTMEM    0
42640 #define M_FILTMEM    0xfU
42649 #define M_T7_PKTFIFO    0xffU
42653 #define S_T7_FILTMEM    0
42654 #define M_T7_FILTMEM    0xffU
42658 #define A_MPS_TRC_INT_ENABLE 0x9858
42664 #define A_MPS_TRC_INT_CAUSE 0x985c
42665 #define A_MPS_TRC_TIMESTAMP_L 0x9860
42666 #define A_MPS_TRC_TIMESTAMP_H 0x9864
42667 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
42668 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
42669 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
42670 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
42671 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
42672 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
42673 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
42674 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
42675 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
42676 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
42677 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
42678 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
42679 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
42680 #define A_MPS_TRC_FILTER4_MATCH 0xa000
42681 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
42682 #define A_MPS_T5_TRC_RSS_HASH 0xa008
42683 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
42684 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
42711 #define M_VFFILTMASK    0x7fU
42719 #define S_VFFILTDATA    0
42720 #define M_VFFILTDATA    0x7fU
42749 #define M_T6_VFFILTMASK    0xffU
42757 #define S_T6_VFFILTDATA    0
42758 #define M_T6_VFFILTDATA    0xffU
42762 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
42763 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
42764 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
42765 #define A_MPS_TRC_CGEN 0xa020
42767 #define S_MPSTRCCGEN    0
42768 #define M_MPSTRCCGEN    0xfU
42772 #define A_MPS_TRC_FILTER4_DONT_CARE 0xa080
42773 #define A_MPS_TRC_FILTER5_MATCH 0xa100
42774 #define A_MPS_TRC_FILTER5_DONT_CARE 0xa180
42775 #define A_MPS_TRC_FILTER6_MATCH 0xa200
42776 #define A_MPS_TRC_FILTER6_DONT_CARE 0xa280
42777 #define A_MPS_TRC_FILTER7_MATCH 0xa300
42778 #define A_MPS_TRC_FILTER7_DONT_CARE 0xa380
42779 #define A_T7_MPS_TRC_FILTER0_RSS_HASH 0xa3f0
42780 #define A_T7_MPS_TRC_FILTER0_RSS_CONTROL 0xa3f4
42781 #define A_T7_MPS_TRC_FILTER1_RSS_HASH 0xa3f8
42782 #define A_T7_MPS_TRC_FILTER1_RSS_CONTROL 0xa3fc
42783 #define A_T7_MPS_TRC_FILTER2_RSS_HASH 0xa400
42784 #define A_T7_MPS_TRC_FILTER2_RSS_CONTROL 0xa404
42785 #define A_T7_MPS_TRC_FILTER3_RSS_HASH 0xa408
42786 #define A_T7_MPS_TRC_FILTER3_RSS_CONTROL 0xa40c
42787 #define A_MPS_TRC_FILTER4_RSS_HASH 0xa410
42788 #define A_MPS_TRC_FILTER4_RSS_CONTROL 0xa414
42789 #define A_MPS_TRC_FILTER5_RSS_HASH 0xa418
42790 #define A_MPS_TRC_FILTER5_RSS_CONTROL 0xa41c
42791 #define A_MPS_TRC_FILTER6_RSS_HASH 0xa420
42792 #define A_MPS_TRC_FILTER6_RSS_CONTROL 0xa424
42793 #define A_MPS_TRC_FILTER7_RSS_HASH 0xa428
42794 #define A_MPS_TRC_FILTER7_RSS_CONTROL 0xa42c
42795 #define A_T7_MPS_T5_TRC_RSS_HASH 0xa430
42796 #define A_T7_MPS_T5_TRC_RSS_CONTROL 0xa434
42797 #define A_T7_MPS_TRC_VF_OFF_FILTER_0 0xa438
42798 #define A_T7_MPS_TRC_VF_OFF_FILTER_1 0xa43c
42799 #define A_T7_MPS_TRC_VF_OFF_FILTER_2 0xa440
42800 #define A_T7_MPS_TRC_VF_OFF_FILTER_3 0xa444
42801 #define A_MPS_TRC_VF_OFF_FILTER_4 0xa448
42802 #define A_MPS_TRC_VF_OFF_FILTER_5 0xa44c
42803 #define A_MPS_TRC_VF_OFF_FILTER_6 0xa450
42804 #define A_MPS_TRC_VF_OFF_FILTER_7 0xa454
42805 #define A_T7_MPS_TRC_CGEN 0xa458
42807 #define S_T7_MPSTRCCGEN    0
42808 #define M_T7_MPSTRCCGEN    0xffU
42812 #define A_T7_MPS_TRC_FILTER_MATCH_CTL_A 0xa460
42813 #define A_T7_MPS_TRC_FILTER_MATCH_CTL_B 0xa480
42814 #define A_T7_MPS_TRC_FILTER_RUNT_CTL 0xa4a0
42815 #define A_T7_MPS_TRC_FILTER_DROP 0xa4c0
42816 #define A_T7_MPS_TRC_INT_ENABLE 0xa4e0
42822 #define A_T7_MPS_TRC_INT_CAUSE 0xa4e4
42823 #define A_T7_MPS_TRC_TIMESTAMP_L 0xa4e8
42824 #define A_T7_MPS_TRC_TIMESTAMP_H 0xa4ec
42825 #define A_MPS_TRC_PERR_ENABLE2 0xa4f0
42828 #define M_TRC_TF_ECC    0xffU
42833 #define M_MPS2MAC_CONV_TRC_CERR    0x3U
42838 #define M_MPS2MAC_CONV_TRC    0xfU
42882 #define S_PERR_TF_IN_CTL    0
42883 #define M_PERR_TF_IN_CTL    0xffU
42887 #define A_MPS_TRC_INT_ENABLE2 0xa4f4
42888 #define A_MPS_TRC_INT_CAUSE2 0xa4f8
42891 #define M_T7_TRC_TF_ECC    0xffU
42895 #define A_MPS_CLS_CTL 0xd000
42913 #define S_VLANCLSEN    0
42929 #define A_MPS_CLS_ARB_WEIGHT 0xd004
42932 #define M_PLWEIGHT    0x1fU
42937 #define M_CIMWEIGHT    0x1fU
42941 #define S_LPBKWEIGHT    0
42942 #define M_LPBKWEIGHT    0x1fU
42946 #define A_MPS_CLS_NCSI_ETH_TYPE 0xd008
42947 #define A_MPS_CLS_NCSI_ETH_TYPE_EN 0xd00c
42948 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
42949 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
42950 #define A_MPS_CLS_BMC_VLAN 0xd018
42951 #define A_MPS_CLS_PERR_INJECT 0xd01c
42954 #define M_CLS_MEMSEL    0x3U
42958 #define A_MPS_CLS_PERR_ENABLE 0xd020
42968 #define S_MATCHSRAM    0
42980 #define A_MPS_CLS_INT_ENABLE 0xd024
42990 #define A_MPS_CLS_INT_CAUSE 0xd028
42991 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
42992 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
42993 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
42996 #define M_CLS_PRIORITY    0x7U
43005 #define M_CLS_INDEX    0x1ffU
43010 #define M_CLS_VF    0x7fU
43019 #define M_CLS_PF    0x7U
43023 #define S_CLS_MATCH    0
43024 #define M_CLS_MATCH    0x7U
43029 #define M_CLS_SPARE    0xfU
43034 #define M_T6_CLS_PRIORITY    0x7U
43043 #define M_T6_CLS_INDEX    0x1ffU
43048 #define M_T6_CLS_VF    0xffU
43053 #define M_T7_CLS_SPARE    0x3U
43058 #define M_T7_1_CLS_PRIORITY    0x7U
43067 #define M_T7_1_CLS_INDEX    0x7ffU
43071 #define A_MPS_CLS_PL_TEST_CTL 0xd038
43073 #define S_PLTESTCTL    0
43077 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
43079 #define S_PRTBMCCTL    0
43083 #define A_MPS_CLS_MATCH_CNT_TCAM 0xd100
43084 #define A_MPS_CLS0_MATCH_CNT_TCAM 0xd100
43085 #define A_MPS_CLS_MATCH_CNT_HASH 0xd104
43086 #define A_MPS_CLS0_MATCH_CNT_HASH 0xd104
43087 #define A_MPS_CLS_MATCH_CNT_BCAST 0xd108
43088 #define A_MPS_CLS0_MATCH_CNT_BCAST 0xd108
43089 #define A_MPS_CLS_MATCH_CNT_BMC 0xd10c
43090 #define A_MPS_CLS0_MATCH_CNT_BMC 0xd10c
43091 #define A_MPS_CLS_MATCH_CNT_PROM 0xd110
43092 #define A_MPS_CLS0_MATCH_CNT_PROM 0xd110
43093 #define A_MPS_CLS_MATCH_CNT_HPROM 0xd114
43094 #define A_MPS_CLS0_MATCH_CNT_HPROM 0xd114
43095 #define A_MPS_CLS_MISS_CNT 0xd118
43096 #define A_MPS_CLS0_MISS_CNT 0xd118
43097 #define A_MPS_CLS1_MATCH_CNT_TCAM 0xd11c
43098 #define A_MPS_CLS1_MATCH_CNT_HASH 0xd120
43099 #define A_MPS_CLS1_MATCH_CNT_BCAST 0xd124
43100 #define A_MPS_CLS1_MATCH_CNT_BMC 0xd128
43101 #define A_MPS_CLS1_MATCH_CNT_PROM 0xd12c
43102 #define A_MPS_CLS1_MATCH_CNT_HPROM 0xd130
43103 #define A_MPS_CLS1_MISS_CNT 0xd134
43104 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_L 0xd200
43105 #define A_MPS_CLS_REQUEST_TRACE_MAC_DA_H 0xd204
43107 #define S_CLSTRCMACDAHI    0
43108 #define M_CLSTRCMACDAHI    0xffffU
43112 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_L 0xd208
43113 #define A_MPS_CLS_REQUEST_TRACE_MAC_SA_H 0xd20c
43115 #define S_CLSTRCMACSAHI    0
43116 #define M_CLSTRCMACSAHI    0xffffU
43120 #define A_MPS_CLS_REQUEST_TRACE_PORT_VLAN 0xd210
43127 #define M_CLSTRCVLANID    0xfffU
43131 #define S_CLSTRCREQPORT    0
43132 #define M_CLSTRCREQPORT    0xfU
43136 #define A_MPS_CLS_REQUEST_TRACE_ENCAP 0xd214
43146 #define S_CLSTRCVNI    0
43147 #define M_CLSTRCVNI    0xffffffU
43151 #define A_MPS_CLS_RESULT_TRACE 0xd300
43158 #define M_CLSTRCPRIORITY    0x7U
43171 #define M_CLSTRCPORTMAP    0x3U
43176 #define M_CLSTRCMATCH    0x7U
43181 #define M_CLSTRCINDEX    0x1ffU
43190 #define M_CLSTRCPF    0xffU
43194 #define S_CLSTRCVF    0
43195 #define M_CLSTRCVF    0x7U
43204 #define M_T7_CLSTRCINDEX    0x7ffU
43208 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
43211 #define M_VLAN_MASK    0xfffU
43216 #define M_VLANPF    0x7U
43224 #define A_MPS_CLS_SRAM_L 0xe000
43243 #define M_SRAM_PRIO3    0x7U
43248 #define M_SRAM_PRIO2    0x7U
43253 #define M_SRAM_PRIO1    0x7U
43258 #define M_SRAM_PRIO0    0x7U
43266 #define A_MPS_T5_CLS_SRAM_L 0xe000
43293 #define M_T6_SRAM_PRIO3    0x7U
43298 #define M_T6_SRAM_PRIO2    0x7U
43303 #define M_T6_SRAM_PRIO1    0x7U
43308 #define M_T6_SRAM_PRIO0    0x7U
43316 #define A_MPS_CLS_SRAM_H 0xe004
43327 #define M_MACPARITYMASKSIZE    0xfU
43331 #define S_PORTMAP    0
43332 #define M_PORTMAP    0xfU
43336 #define A_MPS_T5_CLS_SRAM_H 0xe004
43347 #define M_SRAMSPARE    0xfU
43352 #define M_SRAMINDEX    0x7ffU
43356 #define A_MPS_CLS_HASH_TCAM_CTL 0xe008
43366 #define S_T7_CTLTCAMINDEX    0
43367 #define M_T7_CTLTCAMINDEX    0x1ffU
43371 #define A_MPS_CLS_HASH_TCAM_DATA 0xe00c
43377 #define A_MPS_CLS_TCAM_Y_L 0xf000
43378 #define A_MPS_CLS_TCAM_DATA0 0xf000
43379 #define A_MPS_CLS_TCAM_Y_H 0xf004
43381 #define S_TCAMYH    0
43382 #define M_TCAMYH    0xffffU
43386 #define A_MPS_CLS_TCAM_DATA1 0xf004
43389 #define M_VIDL    0xffffU
43393 #define S_DMACH    0
43394 #define M_DMACH    0xffffU
43398 #define A_MPS_CLS_TCAM_X_L 0xf008
43399 #define A_MPS_CLS_TCAM_DATA2_CTL 0xf008
43414 #define M_CTLTCAMINDEX    0xffU
43423 #define M_DATAPORTNUM    0xfU
43428 #define M_DATALKPTYPE    0x3U
43440 #define S_DATAVIDH1    0
43441 #define M_DATAVIDH1    0x7fU
43446 #define M_T7_CTLTCAMSEL    0x3U
43451 #define M_T7_1_CTLTCAMINDEX    0x1ffU
43455 #define A_MPS_CLS_TCAM_X_H 0xf00c
43457 #define S_TCAMXH    0
43458 #define M_TCAMXH    0xffffU
43462 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID0 0xf010
43463 #define A_MPS_CLS_TCAM0_RDATA0_REQ_ID0 0xf010
43464 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID0 0xf014
43465 #define A_MPS_CLS_TCAM0_RDATA1_REQ_ID0 0xf014
43466 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID0 0xf018
43467 #define A_MPS_CLS_TCAM0_RDATA2_REQ_ID0 0xf018
43468 #define A_MPS_CLS_TCAM0_RDATA0_REQ_ID1 0xf01c
43469 #define A_MPS_CLS_TCAM_RDATA0_REQ_ID1 0xf020
43470 #define A_MPS_CLS_TCAM0_RDATA1_REQ_ID1 0xf020
43471 #define A_MPS_CLS_TCAM_RDATA1_REQ_ID1 0xf024
43472 #define A_MPS_CLS_TCAM0_RDATA2_REQ_ID1 0xf024
43473 #define A_MPS_CLS_TCAM_RDATA2_REQ_ID1 0xf028
43474 #define A_MPS_CLS_TCAM1_RDATA0_REQ_ID0 0xf028
43475 #define A_MPS_CLS_TCAM1_RDATA1_REQ_ID0 0xf02c
43476 #define A_MPS_CLS_TCAM1_RDATA2_REQ_ID0 0xf030
43477 #define A_MPS_CLS_TCAM1_RDATA0_REQ_ID1 0xf034
43478 #define A_MPS_CLS_TCAM1_RDATA1_REQ_ID1 0xf038
43479 #define A_MPS_CLS_TCAM1_RDATA2_REQ_ID1 0xf03c
43480 #define A_MPS_CLS_TCAM0_MASK_REG0 0xf040
43481 #define A_MPS_CLS_TCAM0_MASK_REG1 0xf044
43482 #define A_MPS_CLS_TCAM0_MASK_REG2 0xf048
43484 #define S_MASK_0_2    0
43485 #define M_MASK_0_2    0xffffU
43489 #define A_MPS_CLS_TCAM1_MASK_REG0 0xf04c
43490 #define A_MPS_CLS_TCAM1_MASK_REG1 0xf050
43491 #define A_MPS_CLS_TCAM1_MASK_REG2 0xf054
43493 #define S_MASK_1_2    0
43494 #define M_MASK_1_2    0xffffU
43498 #define A_MPS_CLS_TCAM_BIST_CTRL 0xf058
43499 #define A_MPS_CLS_TCAM_BIST_CB_PASS 0xf05c
43500 #define A_MPS_CLS_TCAM_BIST_CB_BUSY 0xf060
43501 #define A_MPS_CLS_TCAM2_MASK_REG0 0xf064
43502 #define A_MPS_CLS_TCAM2_MASK_REG1 0xf068
43503 #define A_MPS_CLS_TCAM2_MASK_REG2 0xf06c
43504 #define A_MPS_RX_CTL 0x11000
43515 #define M_BLK_SNDR    0xfU
43520 #define M_CMPRS    0xfU
43524 #define S_SNF    0
43525 #define M_SNF    0xffU
43537 #define A_MPS_RX_PORT_MUX_CTL 0x11004
43540 #define M_CTL_P3    0xfU
43545 #define M_CTL_P2    0xfU
43550 #define M_CTL_P1    0xfU
43554 #define S_CTL_P0    0
43555 #define M_CTL_P0    0xfU
43559 #define A_MPS_RX_PG_FL 0x11008
43565 #define S_CNT    0
43566 #define M_CNT    0xffffU
43570 #define A_MPS_RX_FIFO_0_CTL 0x11008
43572 #define S_DEST_SELECT    0
43573 #define M_DEST_SELECT    0xfU
43577 #define A_MPS_RX_PKT_FL 0x1100c
43578 #define A_MPS_RX_FIFO_1_CTL 0x1100c
43579 #define A_MPS_RX_PG_RSV0 0x11010
43590 #define M_USED    0x7ffU
43594 #define S_ALLOC    0
43595 #define M_ALLOC    0x7ffU
43600 #define M_T5_USED    0xfffU
43604 #define S_T5_ALLOC    0
43605 #define M_T5_ALLOC    0xfffU
43609 #define A_MPS_RX_FIFO_2_CTL 0x11010
43610 #define A_MPS_RX_PG_RSV1 0x11014
43611 #define A_MPS_RX_FIFO_3_CTL 0x11014
43612 #define A_MPS_RX_PG_RSV2 0x11018
43613 #define A_MPS_RX_PG_RSV3 0x1101c
43614 #define A_MPS_RX_PG_RSV4 0x11020
43615 #define A_MPS_RX_PG_RSV5 0x11024
43616 #define A_MPS_RX_PG_RSV6 0x11028
43617 #define A_MPS_RX_PG_RSV7 0x1102c
43618 #define A_MPS_RX_PG_SHR_BG0 0x11030
43629 #define M_MAX    0x7ffU
43633 #define S_BORW    0
43634 #define M_BORW    0x7ffU
43639 #define M_T5_MAX    0xfffU
43643 #define S_T5_BORW    0
43644 #define M_T5_BORW    0xfffU
43648 #define A_MPS_RX_PG_SHR_BG1 0x11034
43649 #define A_MPS_RX_PG_SHR_BG2 0x11038
43650 #define A_MPS_RX_PG_SHR_BG3 0x1103c
43651 #define A_MPS_RX_PG_SHR0 0x11040
43654 #define M_QUOTA    0x7ffU
43658 #define S_SHR_USED    0
43659 #define M_SHR_USED    0x7ffU
43664 #define M_T5_QUOTA    0xfffU
43668 #define S_T5_SHR_USED    0
43669 #define M_T5_SHR_USED    0xfffU
43673 #define A_MPS_RX_PG_SHR1 0x11044
43674 #define A_MPS_RX_PG_HYST_BG0 0x11048
43676 #define S_TH    0
43677 #define M_TH    0x7ffU
43681 #define S_T5_TH    0
43682 #define M_T5_TH    0xfffU
43686 #define S_T6_TH    0
43687 #define M_T6_TH    0x7ffU
43691 #define A_MPS_RX_PG_HYST_BG1 0x1104c
43692 #define A_MPS_RX_PG_HYST_BG2 0x11050
43693 #define A_MPS_RX_PG_HYST_BG3 0x11054
43694 #define A_MPS_RX_OCH_CTL 0x11058
43697 #define M_DROP_WT    0x1fU
43702 #define M_TRUNC_WT    0x1fU
43707 #define M_OCH_DRAIN    0x1fU
43712 #define M_OCH_DROP    0x1fU
43716 #define S_STOP    0
43717 #define M_STOP    0x1fU
43721 #define A_MPS_RX_LPBK_BP0 0x1105c
43723 #define S_THRESH    0
43724 #define M_THRESH    0x7ffU
43728 #define S_T7_THRESH    0
43729 #define M_T7_THRESH    0xfffU
43733 #define A_MPS_RX_LPBK_BP1 0x11060
43734 #define A_MPS_RX_LPBK_BP2 0x11064
43735 #define A_MPS_RX_LPBK_BP3 0x11068
43736 #define A_MPS_RX_PORT_GAP 0x1106c
43738 #define S_GAP    0
43739 #define M_GAP    0xfffffU
43743 #define A_MPS_RX_CHMN_CNT 0x11070
43744 #define A_MPS_CTL_STAT 0x11070
43746 #define S_T7_CTL    0
43750 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
43844 #define S_CDM0    0
43865 #define M_RPLC_MAP    0x1fU
43874 #define M_T7_PPM3    0x7U
43879 #define M_T7_PPM2    0x7U
43884 #define M_T7_PPM1    0x7U
43888 #define S_T7_PPM0    0
43889 #define M_T7_PPM0    0x7U
43893 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
43899 #define A_MPS_RX_PERR_ENABLE 0x1107c
43900 #define A_MPS_RX_PERR_INJECT 0x11080
43901 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
43904 #define M_INT_ERR_INT    0x1fU
43936 #define S_PG_TH_INT0    0
43968 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
43969 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
43972 #define M_TH_HIGH    0xffffU
43976 #define S_TH_LOW    0
43977 #define M_TH_LOW    0xffffU
43981 #define A_MPS_RX_PERR_INT_CAUSE2 0x1108c
43984 #define M_CRYPT2MPS_RX_INTF_FIFO    0xfU
44005 #define M_MPS2CRYPTO_RX_INTF_FIFO    0xfU
44061 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
44062 #define A_MPS_RX_PERR_INT_ENABLE2 0x11090
44063 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
44064 #define A_MPS_RX_PERR_ENABLE2 0x11094
44065 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
44066 #define A_MPS_RX_REPL_CTL 0x11098
44068 #define S_INDEX_SEL    0
44072 #define A_MPS_RX_PPP_ATRB 0x1109c
44075 #define M_ETYPE    0xffffU
44079 #define S_OPCODE    0
44080 #define M_OPCODE    0xffffU
44084 #define A_MPS_RX_QFC0_ATRB 0x110a0
44086 #define S_DA    0
44087 #define M_DA    0xffffU
44091 #define A_MPS_RX_QFC1_ATRB 0x110a4
44092 #define A_MPS_RX_PT_ARB0 0x110a8
44095 #define M_LPBK_WT    0x3fffU
44099 #define S_MAC_WT    0
44100 #define M_MAC_WT    0x3fffU
44104 #define A_MPS_RX_PT_ARB1 0x110ac
44105 #define A_MPS_RX_PT_ARB2 0x110b0
44106 #define A_T7_MPS_RX_PT_ARB4 0x110b0
44107 #define A_MPS_RX_PT_ARB3 0x110b4
44108 #define A_T6_MPS_PF_OUT_EN 0x110b4
44109 #define A_T7_MPS_PF_OUT_EN 0x110b4
44110 #define A_MPS_RX_PT_ARB4 0x110b8
44111 #define A_T6_MPS_BMC_MTU 0x110b8
44112 #define A_T7_MPS_BMC_MTU 0x110b8
44113 #define A_MPS_PF_OUT_EN 0x110bc
44115 #define S_OUTEN    0
44116 #define M_OUTEN    0xffU
44120 #define A_T6_MPS_BMC_PKT_CNT 0x110bc
44121 #define A_T7_MPS_BMC_PKT_CNT 0x110bc
44122 #define A_MPS_BMC_MTU 0x110c0
44124 #define S_MTU    0
44125 #define M_MTU    0x3fffU
44129 #define A_T6_MPS_BMC_BYTE_CNT 0x110c0
44130 #define A_T7_MPS_BMC_BYTE_CNT 0x110c0
44131 #define A_MPS_BMC_PKT_CNT 0x110c4
44132 #define A_T6_MPS_PFVF_ATRB_CTL 0x110c4
44134 #define S_T6_PFVF    0
44135 #define M_T6_PFVF    0x1ffU
44139 #define A_T7_MPS_PFVF_ATRB_CTL 0x110c4
44140 #define A_MPS_BMC_BYTE_CNT 0x110c8
44141 #define A_T6_MPS_PFVF_ATRB 0x110c8
44147 #define A_T7_MPS_PFVF_ATRB 0x110c8
44153 #define A_MPS_PFVF_ATRB_CTL 0x110cc
44159 #define S_PFVF    0
44160 #define M_PFVF    0xffU
44164 #define A_T6_MPS_PFVF_ATRB_FLTR0 0x110cc
44165 #define A_T7_MPS_PFVF_ATRB_FLTR0 0x110cc
44166 #define A_MPS_PFVF_ATRB 0x110d0
44169 #define M_ATTR_PF    0x7U
44185 #define A_T6_MPS_PFVF_ATRB_FLTR1 0x110d0
44186 #define A_T7_MPS_PFVF_ATRB_FLTR1 0x110d0
44187 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
44193 #define S_VLAN_ID    0
44194 #define M_VLAN_ID    0xfffU
44198 #define A_T6_MPS_PFVF_ATRB_FLTR2 0x110d4
44199 #define A_T7_MPS_PFVF_ATRB_FLTR2 0x110d4
44200 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
44201 #define A_T6_MPS_PFVF_ATRB_FLTR3 0x110d8
44202 #define A_T7_MPS_PFVF_ATRB_FLTR3 0x110d8
44203 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
44204 #define A_T6_MPS_PFVF_ATRB_FLTR4 0x110dc
44205 #define A_T7_MPS_PFVF_ATRB_FLTR4 0x110dc
44206 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
44207 #define A_T6_MPS_PFVF_ATRB_FLTR5 0x110e0
44208 #define A_T7_MPS_PFVF_ATRB_FLTR5 0x110e0
44209 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
44210 #define A_T6_MPS_PFVF_ATRB_FLTR6 0x110e4
44211 #define A_T7_MPS_PFVF_ATRB_FLTR6 0x110e4
44212 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
44213 #define A_T6_MPS_PFVF_ATRB_FLTR7 0x110e8
44214 #define A_T7_MPS_PFVF_ATRB_FLTR7 0x110e8
44215 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
44216 #define A_T6_MPS_PFVF_ATRB_FLTR8 0x110ec
44217 #define A_T7_MPS_PFVF_ATRB_FLTR8 0x110ec
44218 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
44219 #define A_T6_MPS_PFVF_ATRB_FLTR9 0x110f0
44220 #define A_T7_MPS_PFVF_ATRB_FLTR9 0x110f0
44221 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
44222 #define A_T6_MPS_PFVF_ATRB_FLTR10 0x110f4
44223 #define A_T7_MPS_PFVF_ATRB_FLTR10 0x110f4
44224 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
44225 #define A_T6_MPS_PFVF_ATRB_FLTR11 0x110f8
44226 #define A_T7_MPS_PFVF_ATRB_FLTR11 0x110f8
44227 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
44228 #define A_T6_MPS_PFVF_ATRB_FLTR12 0x110fc
44229 #define A_T7_MPS_PFVF_ATRB_FLTR12 0x110fc
44230 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
44231 #define A_T6_MPS_PFVF_ATRB_FLTR13 0x11100
44232 #define A_T7_MPS_PFVF_ATRB_FLTR13 0x11100
44233 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
44234 #define A_T6_MPS_PFVF_ATRB_FLTR14 0x11104
44235 #define A_T7_MPS_PFVF_ATRB_FLTR14 0x11104
44236 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
44237 #define A_T6_MPS_PFVF_ATRB_FLTR15 0x11108
44238 #define A_T7_MPS_PFVF_ATRB_FLTR15 0x11108
44239 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
44240 #define A_T6_MPS_RPLC_MAP_CTL 0x1110c
44241 #define A_T7_MPS_RPLC_MAP_CTL 0x1110c
44243 #define S_T7_RPLC_MAP_ADDR    0
44244 #define M_T7_RPLC_MAP_ADDR    0xfffU
44248 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
44249 #define A_T6_MPS_PF_RPLCT_MAP 0x11110
44250 #define A_T7_MPS_PF_RPLCT_MAP 0x11110
44251 #define A_MPS_RPLC_MAP_CTL 0x11114
44253 #define S_RPLC_MAP_ADDR    0
44254 #define M_RPLC_MAP_ADDR    0x3ffU
44258 #define A_T6_MPS_VF_RPLCT_MAP0 0x11114
44259 #define A_T7_MPS_VF_RPLCT_MAP0 0x11114
44260 #define A_MPS_PF_RPLCT_MAP 0x11118
44262 #define S_PF_EN    0
44263 #define M_PF_EN    0xffU
44267 #define A_T6_MPS_VF_RPLCT_MAP1 0x11118
44268 #define A_T7_MPS_VF_RPLCT_MAP1 0x11118
44269 #define A_MPS_VF_RPLCT_MAP0 0x1111c
44270 #define A_T6_MPS_VF_RPLCT_MAP2 0x1111c
44271 #define A_T7_MPS_VF_RPLCT_MAP2 0x1111c
44272 #define A_MPS_VF_RPLCT_MAP1 0x11120
44273 #define A_T6_MPS_VF_RPLCT_MAP3 0x11120
44274 #define A_T7_MPS_VF_RPLCT_MAP3 0x11120
44275 #define A_MPS_VF_RPLCT_MAP2 0x11124
44276 #define A_MPS_VF_RPLCT_MAP3 0x11128
44277 #define A_MPS_MEM_DBG_CTL 0x1112c
44287 #define A_MPS_PKD_MEM_DATA0 0x11130
44288 #define A_MPS_PKD_MEM_DATA1 0x11134
44289 #define A_MPS_PKD_MEM_DATA2 0x11138
44290 #define A_MPS_PGD_MEM_DATA 0x1113c
44291 #define A_MPS_RX_SE_CNT_ERR 0x11140
44293 #define S_RX_SE_ERRMAP    0
44294 #define M_RX_SE_ERRMAP    0xfffffU
44298 #define A_MPS_RX_SE_CNT_CLR 0x11144
44299 #define A_MPS_RX_SE_CNT_IN0 0x11148
44302 #define M_SOP_CNT_PM    0xffU
44307 #define M_EOP_CNT_PM    0xffU
44312 #define M_SOP_CNT_IN    0xffU
44316 #define S_EOP_CNT_IN    0
44317 #define M_EOP_CNT_IN    0xffU
44321 #define A_MPS_RX_SE_CNT_IN1 0x1114c
44322 #define A_MPS_RX_SE_CNT_IN2 0x11150
44323 #define A_MPS_RX_SE_CNT_IN3 0x11154
44324 #define A_MPS_RX_SE_CNT_IN4 0x11158
44325 #define A_MPS_RX_SE_CNT_IN5 0x1115c
44326 #define A_MPS_RX_SE_CNT_IN6 0x11160
44327 #define A_MPS_RX_SE_CNT_IN7 0x11164
44328 #define A_MPS_RX_SE_CNT_OUT01 0x11168
44331 #define M_SOP_CNT_1    0xffU
44336 #define M_EOP_CNT_1    0xffU
44341 #define M_SOP_CNT_0    0xffU
44345 #define S_EOP_CNT_0    0
44346 #define M_EOP_CNT_0    0xffU
44350 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
44353 #define M_SOP_CNT_3    0xffU
44358 #define M_EOP_CNT_3    0xffU
44363 #define M_SOP_CNT_2    0xffU
44367 #define S_EOP_CNT_2    0
44368 #define M_EOP_CNT_2    0xffU
44372 #define A_MPS_RX_SPI_ERR 0x11170
44375 #define M_LENERR    0xfU
44379 #define S_SPIERR    0
44380 #define M_SPIERR    0x1fffffU
44384 #define A_MPS_RX_IN_BUS_STATE 0x11174
44387 #define M_ST3    0xffU
44392 #define M_ST2    0xffU
44397 #define M_ST1    0xffU
44401 #define S_ST0    0
44402 #define M_ST0    0xffU
44406 #define A_MPS_RX_OUT_BUS_STATE 0x11178
44409 #define M_ST_NCSI    0x1ffU
44413 #define S_ST_TP    0
44414 #define M_ST_TP    0x7fffffU
44418 #define A_MPS_RX_DBG_CTL 0x1117c
44421 #define M_OUT_DBG_CHNL    0x7U
44434 #define M_IN_DBG_PORT    0x7U
44438 #define S_IN_DBG_CHNL    0
44439 #define M_IN_DBG_CHNL    0x7U
44443 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
44446 #define M_LPBK_CNT0    0xffffU
44450 #define S_MAC_CNT0    0
44451 #define M_MAC_CNT0    0xffffU
44455 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
44458 #define M_LPBK_CNT1    0xffffU
44462 #define S_MAC_CNT1    0
44463 #define M_MAC_CNT1    0xffffU
44467 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
44470 #define M_LPBK_CNT2    0xffffU
44474 #define S_MAC_CNT2    0
44475 #define M_MAC_CNT2    0xffffU
44479 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
44482 #define M_LPBK_CNT3    0xffffU
44486 #define S_MAC_CNT3    0
44487 #define M_MAC_CNT3    0xffffU
44491 #define A_MPS_RX_SPARE 0x11190
44492 #define A_MPS_RX_PTP_ETYPE 0x11194
44495 #define M_PETYPE2    0xffffU
44499 #define S_PETYPE1    0
44500 #define M_PETYPE1    0xffffU
44504 #define A_MPS_RX_PTP_TCP 0x11198
44507 #define M_PTCPORT2    0xffffU
44511 #define S_PTCPORT1    0
44512 #define M_PTCPORT1    0xffffU
44516 #define A_MPS_RX_PTP_UDP 0x1119c
44519 #define M_PUDPORT2    0xffffU
44523 #define S_PUDPORT1    0
44524 #define M_PUDPORT1    0xffffU
44528 #define A_MPS_RX_PTP_CTL 0x111a0
44531 #define M_MIN_PTP_SPACE    0x7fU
44536 #define M_PUDP2EN    0xfU
44541 #define M_PUDP1EN    0xfU
44546 #define M_PTCP2EN    0xfU
44551 #define M_PTCP1EN    0xfU
44556 #define M_PETYPE2EN    0xfU
44560 #define S_PETYPE1EN    0
44561 #define M_PETYPE1EN    0xfU
44565 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
44566 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
44567 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
44568 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
44569 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
44570 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
44571 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
44572 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
44573 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
44574 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
44575 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
44576 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
44577 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
44578 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
44579 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
44580 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
44581 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
44582 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
44583 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
44584 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
44585 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
44586 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
44587 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
44588 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
44589 #define A_MPS_RX_CGEN 0x11204
44596 #define M_MPS_RX_CGEN_OUT    0xfU
44601 #define M_MPS_RX_CGEN_LPBK_IN    0xfU
44605 #define S_MPS_RX_CGEN_MAC_IN    0
44606 #define M_MPS_RX_CGEN_MAC_IN    0xfU
44610 #define A_MPS_RX_MAC_BG_PG_CNT0 0x11208
44613 #define M_MAC_USED    0x7ffU
44617 #define S_MAC_ALLOC    0
44618 #define M_MAC_ALLOC    0x7ffU
44622 #define A_MPS_RX_MAC_BG_PG_CNT1 0x1120c
44623 #define A_MPS_RX_MAC_BG_PG_CNT2 0x11210
44624 #define A_MPS_RX_MAC_BG_PG_CNT3 0x11214
44625 #define A_MPS_RX_LPBK_BG_PG_CNT0 0x11218
44628 #define M_LPBK_USED    0x7ffU
44632 #define S_LPBK_ALLOC    0
44633 #define M_LPBK_ALLOC    0x7ffU
44637 #define A_MPS_RX_LPBK_BG_PG_CNT1 0x1121c
44638 #define A_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11220
44644 #define S_CONG_TH    0
44645 #define M_CONG_TH    0xfffffU
44649 #define A_MPS_RX_LPBK_BG_PG_CNT2 0x11220
44650 #define A_MPS_RX_CONGESTION_THRESHOLD_BG1 0x11224
44651 #define A_MPS_RX_LPBK_BG_PG_CNT3 0x11224
44652 #define A_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11228
44653 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG0 0x11228
44654 #define A_MPS_RX_CONGESTION_THRESHOLD_BG3 0x1122c
44655 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG1 0x1122c
44656 #define A_MPS_RX_GRE_PROT_TYPE 0x11230
44666 #define S_GRE    0
44667 #define M_GRE    0xffU
44671 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG2 0x11230
44672 #define A_MPS_RX_VXLAN_TYPE 0x11234
44678 #define S_VXLAN    0
44679 #define M_VXLAN    0xffffU
44683 #define A_T7_MPS_RX_CONGESTION_THRESHOLD_BG3 0x11234
44684 #define A_MPS_RX_GENEVE_TYPE 0x11238
44690 #define S_GENEVE    0
44691 #define M_GENEVE    0xffffU
44695 #define A_T7_MPS_RX_GRE_PROT_TYPE 0x11238
44696 #define A_MPS_RX_INNER_HDR_IVLAN 0x1123c
44702 #define A_T7_MPS_RX_VXLAN_TYPE 0x1123c
44703 #define A_MPS_RX_ENCAP_NVGRE 0x11240
44709 #define S_T6_ETYPE    0
44710 #define M_T6_ETYPE    0xffffU
44714 #define A_T7_MPS_RX_GENEVE_TYPE 0x11240
44715 #define A_MPS_RX_ENCAP_GENEVE 0x11244
44716 #define A_T7_MPS_RX_INNER_HDR_IVLAN 0x11244
44717 #define A_MPS_RX_TCP 0x11248
44723 #define S_PROT_TYPE    0
44724 #define M_PROT_TYPE    0xffU
44728 #define A_T7_MPS_RX_ENCAP_NVGRE 0x11248
44729 #define A_MPS_RX_UDP 0x1124c
44730 #define A_T7_MPS_RX_ENCAP_GENEVE 0x1124c
44731 #define A_MPS_RX_PAUSE 0x11250
44732 #define A_T7_MPS_RX_TCP 0x11250
44733 #define A_MPS_RX_LENGTH 0x11254
44736 #define M_SAP_VALUE    0xffffU
44740 #define S_LENGTH_ETYPE    0
44741 #define M_LENGTH_ETYPE    0xffffU
44745 #define A_T7_MPS_RX_UDP 0x11254
44746 #define A_MPS_RX_CTL_ORG 0x11258
44749 #define M_CTL_VALUE    0xffU
44753 #define S_ORG_VALUE    0
44754 #define M_ORG_VALUE    0xffffffU
44758 #define A_T7_MPS_RX_PAUSE 0x11258
44759 #define A_MPS_RX_IPV4 0x1125c
44761 #define S_ETYPE_IPV4    0
44762 #define M_ETYPE_IPV4    0xffffU
44766 #define A_T7_MPS_RX_LENGTH 0x1125c
44767 #define A_MPS_RX_IPV6 0x11260
44769 #define S_ETYPE_IPV6    0
44770 #define M_ETYPE_IPV6    0xffffU
44774 #define A_T7_MPS_RX_CTL_ORG 0x11260
44775 #define A_MPS_RX_TTL 0x11264
44778 #define M_TTL_IPV4    0xffU
44783 #define M_TTL_IPV6    0xffU
44791 #define S_TTL_CHK_EN_IPV6    0
44795 #define A_T7_MPS_RX_IPV4 0x11264
44796 #define A_MPS_RX_DEFAULT_VNI 0x11268
44798 #define S_VNI    0
44799 #define M_VNI    0xffffffU
44803 #define A_T7_MPS_RX_IPV6 0x11268
44804 #define A_MPS_RX_PRS_CTL 0x1126c
44823 #define M_VXLAN_FLAG_MASK    0xffU
44828 #define M_VXLAN_FLAG    0xffU
44837 #define M_GRE_VER    0x7U
44846 #define M_GENEVE_VER    0x3U
44854 #define A_T7_MPS_RX_TTL 0x1126c
44855 #define A_MPS_RX_PRS_CTL_2 0x11270
44873 #define S_T6_IPV6_UDP_CSUM_COMPAT    0
44877 #define A_T7_MPS_RX_DEFAULT_VNI 0x11270
44878 #define A_MPS_RX_MPS2NCSI_CNT 0x11274
44879 #define A_T7_MPS_RX_PRS_CTL 0x11274
44880 #define A_MPS_RX_MAX_TNL_HDR_LEN 0x11278
44882 #define S_T6_LEN    0
44883 #define M_T6_LEN    0x1ffU
44887 #define A_T7_MPS_RX_PRS_CTL_2 0x11278
44893 #define A_MPS_RX_PAUSE_DA_H 0x1127c
44894 #define A_T7_MPS_RX_MPS2NCSI_CNT 0x1127c
44895 #define A_MPS_RX_PAUSE_DA_L 0x11280
44896 #define A_T7_MPS_RX_MAX_TNL_HDR_LEN 0x11280
44902 #define S_MPS_MAX_TNL_HDR_LEN    0
44903 #define M_MPS_MAX_TNL_HDR_LEN    0x1ffU
44907 #define A_MPS_RX_CNT_NVGRE_PKT_MAC0 0x11284
44908 #define A_T7_MPS_RX_PAUSE_DA_H 0x11284
44909 #define A_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11288
44910 #define A_T7_MPS_RX_PAUSE_DA_L 0x11288
44911 #define A_MPS_RX_CNT_GENEVE_PKT_MAC0 0x1128c
44912 #define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC0 0x1128c
44913 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11290
44914 #define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC0 0x11290
44915 #define A_MPS_RX_CNT_NVGRE_PKT_MAC1 0x11294
44916 #define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC0 0x11294
44917 #define A_MPS_RX_CNT_VXLAN_PKT_MAC1 0x11298
44918 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC0 0x11298
44919 #define A_MPS_RX_CNT_GENEVE_PKT_MAC1 0x1129c
44920 #define A_T7_MPS_RX_CNT_NVGRE_PKT_MAC1 0x1129c
44921 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a0
44922 #define A_T7_MPS_RX_CNT_VXLAN_PKT_MAC1 0x112a0
44923 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112a4
44924 #define A_T7_MPS_RX_CNT_GENEVE_PKT_MAC1 0x112a4
44925 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112a8
44926 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_MAC1 0x112a8
44927 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112ac
44928 #define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK0 0x112ac
44929 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b0
44930 #define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK0 0x112b0
44931 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112b4
44932 #define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK0 0x112b4
44933 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112b8
44934 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK0 0x112b8
44935 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112bc
44936 #define A_T7_MPS_RX_CNT_NVGRE_PKT_LPBK1 0x112bc
44937 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c0
44938 #define A_T7_MPS_RX_CNT_VXLAN_PKT_LPBK1 0x112c0
44939 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112c4
44940 #define A_T7_MPS_RX_CNT_GENEVE_PKT_LPBK1 0x112c4
44941 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112c8
44942 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_LPBK1 0x112c8
44943 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112cc
44944 #define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP0 0x112cc
44945 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d0
44946 #define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP0 0x112d0
44947 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112d4
44948 #define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP0 0x112d4
44949 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112d8
44950 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP0 0x112d8
44951 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112dc
44952 #define A_T7_MPS_RX_CNT_NVGRE_PKT_TO_TP1 0x112dc
44953 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e0
44954 #define A_T7_MPS_RX_CNT_VXLAN_PKT_TO_TP1 0x112e0
44955 #define A_T7_MPS_RX_CNT_GENEVE_PKT_TO_TP1 0x112e4
44956 #define A_T7_MPS_RX_CNT_TNL_ERR_PKT_TO_TP1 0x112e8
44957 #define A_MPS_RX_ESP 0x112ec
44958 #define A_MPS_EN_LPBK_BLK_SNDR 0x112f0
44972 #define S_EN_CH0    0
44976 #define A_MPS_VF_RPLCT_MAP4 0x11300
44977 #define A_MPS_VF_RPLCT_MAP5 0x11304
44978 #define A_MPS_VF_RPLCT_MAP6 0x11308
44979 #define A_MPS_VF_RPLCT_MAP7 0x1130c
44980 #define A_MPS_RX_PERR_INT_CAUSE3 0x11310
44981 #define A_MPS_RX_PERR_INT_ENABLE3 0x11314
44982 #define A_MPS_RX_PERR_ENABLE3 0x11318
44983 #define A_MPS_RX_PERR_INT_CAUSE4 0x1131c
44986 #define M_CLS    0x3fU
44991 #define M_RX_PRE_PROC    0xfU
44996 #define M_PPROC3    0xfU
45001 #define M_PPROC2    0xfU
45006 #define M_PPROC1    0xfU
45010 #define S_PPROC0    0
45011 #define M_PPROC0    0xfU
45015 #define A_MPS_RX_PERR_INT_ENABLE4 0x11320
45016 #define A_MPS_RX_PERR_ENABLE4 0x11324
45017 #define A_MPS_RX_PERR_INT_CAUSE5 0x11328
45020 #define M_MPS2CRYP_RX_FIFO    0xfU
45025 #define M_RX_OUT    0x3fU
45029 #define S_MEM_WRAP    0
45030 #define M_MEM_WRAP    0xfffffU
45034 #define A_MPS_RX_PERR_INT_ENABLE5 0x1132c
45035 #define A_MPS_RX_PERR_ENABLE5 0x11330
45036 #define A_MPS_RX_PERR_INT_CAUSE6 0x11334
45038 #define S_MPS_RX_MEM_WRAP    0
45039 #define M_MPS_RX_MEM_WRAP    0x1ffffffU
45043 #define A_MPS_RX_PERR_INT_ENABLE6 0x11338
45044 #define A_MPS_RX_PERR_ENABLE6 0x1133c
45045 #define A_MPS_RX_CNT_NVGRE_PKT_MAC2 0x11408
45046 #define A_MPS_RX_CNT_VXLAN_PKT_MAC2 0x1140c
45047 #define A_MPS_RX_CNT_GENEVE_PKT_MAC2 0x11410
45048 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC2 0x11414
45049 #define A_MPS_RX_CNT_NVGRE_PKT_MAC3 0x11418
45050 #define A_MPS_RX_CNT_VXLAN_PKT_MAC3 0x1141c
45051 #define A_MPS_RX_CNT_GENEVE_PKT_MAC3 0x11420
45052 #define A_MPS_RX_CNT_TNL_ERR_PKT_MAC3 0x11424
45053 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK2 0x11428
45054 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK2 0x1142c
45055 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK2 0x11430
45056 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK2 0x11434
45057 #define A_MPS_RX_CNT_NVGRE_PKT_LPBK3 0x11438
45058 #define A_MPS_RX_CNT_VXLAN_PKT_LPBK3 0x1143c
45059 #define A_MPS_RX_CNT_GENEVE_PKT_LPBK3 0x11440
45060 #define A_MPS_RX_CNT_TNL_ERR_PKT_LPBK3 0x11444
45061 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP2 0x11448
45062 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP2 0x1144c
45063 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP2 0x11450
45064 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP2 0x11454
45065 #define A_MPS_RX_CNT_NVGRE_PKT_TO_TP3 0x11458
45066 #define A_MPS_RX_CNT_VXLAN_PKT_TO_TP3 0x1145c
45067 #define A_MPS_RX_CNT_GENEVE_PKT_TO_TP3 0x11460
45068 #define A_MPS_RX_CNT_TNL_ERR_PKT_TO_TP3 0x11464
45069 #define A_T7_MPS_RX_PT_ARB2 0x11468
45070 #define A_T7_MPS_RX_PT_ARB3 0x1146c
45071 #define A_MPS_CLS_DIPIPV4_ID_TABLE 0x12000
45072 #define A_MPS_CLS_DIP_ID_TABLE_CTL 0x12000
45087 #define M_DIP_SEG    0x3U
45092 #define M_DIP_TBL_RSVD1    0x7U
45096 #define S_DIP_TBL_ADDR    0
45097 #define M_DIP_TBL_ADDR    0x1fU
45101 #define A_MPS_CLS_DIPIPV4_MASK_TABLE 0x12004
45102 #define A_MPS_CLS_DIP_ID_TABLE_DATA 0x12004
45103 #define A_MPS_CLS_DIPIPV6ID_0_TABLE 0x12020
45104 #define A_MPS_CLS_DIPIPV6ID_1_TABLE 0x12024
45105 #define A_MPS_CLS_DIPIPV6ID_2_TABLE 0x12028
45106 #define A_MPS_CLS_DIPIPV6ID_3_TABLE 0x1202c
45107 #define A_MPS_CLS_DIPIPV6MASK_0_TABLE 0x12030
45108 #define A_MPS_CLS_DIPIPV6MASK_1_TABLE 0x12034
45109 #define A_MPS_CLS_DIPIPV6MASK_2_TABLE 0x12038
45110 #define A_MPS_CLS_DIPIPV6MASK_3_TABLE 0x1203c
45111 #define A_MPS_RX_HASH_LKP_TABLE 0x12060
45112 #define A_MPS_CLS_DROP_DMAC0_L 0x12070
45113 #define A_MPS_CLS_DROP_DMAC0_H 0x12074
45115 #define S_DMAC    0
45116 #define M_DMAC    0xffffU
45120 #define A_MPS_CLS_DROP_DMAC1_L 0x12078
45121 #define A_MPS_CLS_DROP_DMAC1_H 0x1207c
45122 #define A_MPS_CLS_DROP_DMAC2_L 0x12080
45123 #define A_MPS_CLS_DROP_DMAC2_H 0x12084
45124 #define A_MPS_CLS_DROP_DMAC3_L 0x12088
45125 #define A_MPS_CLS_DROP_DMAC3_H 0x1208c
45126 #define A_MPS_CLS_DROP_DMAC4_L 0x12090
45127 #define A_MPS_CLS_DROP_DMAC4_H 0x12094
45128 #define A_MPS_CLS_DROP_DMAC5_L 0x12098
45129 #define A_MPS_CLS_DROP_DMAC5_H 0x1209c
45130 #define A_MPS_CLS_DROP_DMAC6_L 0x120a0
45131 #define A_MPS_CLS_DROP_DMAC6_H 0x120a4
45132 #define A_MPS_CLS_DROP_DMAC7_L 0x120a8
45133 #define A_MPS_CLS_DROP_DMAC7_H 0x120ac
45134 #define A_MPS_CLS_DROP_DMAC8_L 0x120b0
45135 #define A_MPS_CLS_DROP_DMAC8_H 0x120b4
45136 #define A_MPS_CLS_DROP_DMAC9_L 0x120b8
45137 #define A_MPS_CLS_DROP_DMAC9_H 0x120bc
45138 #define A_MPS_CLS_DROP_DMAC10_L 0x120c0
45139 #define A_MPS_CLS_DROP_DMAC10_H 0x120c4
45140 #define A_MPS_CLS_DROP_DMAC11_L 0x120c8
45141 #define A_MPS_CLS_DROP_DMAC11_H 0x120cc
45142 #define A_MPS_CLS_DROP_DMAC12_L 0x120d0
45143 #define A_MPS_CLS_DROP_DMAC12_H 0x120d4
45144 #define A_MPS_CLS_DROP_DMAC13_L 0x120d8
45145 #define A_MPS_CLS_DROP_DMAC13_H 0x120dc
45146 #define A_MPS_CLS_DROP_DMAC14_L 0x120e0
45147 #define A_MPS_CLS_DROP_DMAC14_H 0x120e4
45148 #define A_MPS_CLS_DROP_DMAC15_L 0x120e8
45149 #define A_MPS_CLS_DROP_DMAC15_H 0x120ec
45150 #define A_MPS_RX_ENCAP_VXLAN 0x120f0
45151 #define A_MPS_RX_INT_VXLAN 0x120f4
45157 #define S_INT_TYPE    0
45158 #define M_INT_TYPE    0xffffU
45162 #define A_MPS_RX_INT_GENEVE 0x120f8
45163 #define A_MPS_PFVF_ATRB2 0x120fc
45169 #define A_MPS_RX_TRANS_ENCAP_FLTR_CTL 0x12100
45175 #define S_FLTR_TIMOUT_VAL    0
45176 #define M_FLTR_TIMOUT_VAL    0xffU
45180 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_0 0x12104
45181 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_1 0x12108
45182 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_2 0x1210c
45183 #define A_T7_MPS_RX_PAUSE_GEN_TH_0_3 0x12110
45184 #define A_MPS_RX_PAUSE_GEN_TH_0_4 0x12114
45185 #define A_MPS_RX_PAUSE_GEN_TH_0_5 0x12118
45186 #define A_MPS_RX_PAUSE_GEN_TH_0_6 0x1211c
45187 #define A_MPS_RX_PAUSE_GEN_TH_0_7 0x12120
45188 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_0 0x12124
45189 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_1 0x12128
45190 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_2 0x1212c
45191 #define A_T7_MPS_RX_PAUSE_GEN_TH_1_3 0x12130
45192 #define A_MPS_RX_PAUSE_GEN_TH_1_4 0x12134
45193 #define A_MPS_RX_PAUSE_GEN_TH_1_5 0x12138
45194 #define A_MPS_RX_PAUSE_GEN_TH_1_6 0x1213c
45195 #define A_MPS_RX_PAUSE_GEN_TH_1_7 0x12140
45196 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_0 0x12144
45197 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_1 0x12148
45198 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_2 0x1214c
45199 #define A_T7_MPS_RX_PAUSE_GEN_TH_2_3 0x12150
45200 #define A_MPS_RX_PAUSE_GEN_TH_2_4 0x12154
45201 #define A_MPS_RX_PAUSE_GEN_TH_2_5 0x12158
45202 #define A_MPS_RX_PAUSE_GEN_TH_2_6 0x1215c
45203 #define A_MPS_RX_PAUSE_GEN_TH_2_7 0x12160
45204 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_0 0x12164
45205 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_1 0x12168
45206 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_2 0x1216c
45207 #define A_T7_MPS_RX_PAUSE_GEN_TH_3_3 0x12170
45208 #define A_MPS_RX_PAUSE_GEN_TH_3_4 0x12174
45209 #define A_MPS_RX_PAUSE_GEN_TH_3_5 0x12178
45210 #define A_MPS_RX_PAUSE_GEN_TH_3_6 0x1217c
45211 #define A_MPS_RX_PAUSE_GEN_TH_3_7 0x12180
45212 #define A_MPS_RX_DROP_0_0 0x12184
45214 #define S_DROP_TH    0
45215 #define M_DROP_TH    0xffffU
45219 #define A_MPS_RX_DROP_0_1 0x12188
45220 #define A_MPS_RX_DROP_0_2 0x1218c
45221 #define A_MPS_RX_DROP_0_3 0x12190
45222 #define A_MPS_RX_DROP_0_4 0x12194
45223 #define A_MPS_RX_DROP_0_5 0x12198
45224 #define A_MPS_RX_DROP_0_6 0x1219c
45225 #define A_MPS_RX_DROP_0_7 0x121a0
45226 #define A_MPS_RX_DROP_1_0 0x121a4
45227 #define A_MPS_RX_DROP_1_1 0x121a8
45228 #define A_MPS_RX_DROP_1_2 0x121ac
45229 #define A_MPS_RX_DROP_1_3 0x121b0
45230 #define A_MPS_RX_DROP_1_4 0x121b4
45231 #define A_MPS_RX_DROP_1_5 0x121b8
45232 #define A_MPS_RX_DROP_1_6 0x121bc
45233 #define A_MPS_RX_DROP_1_7 0x121c0
45234 #define A_MPS_RX_DROP_2_0 0x121c4
45235 #define A_MPS_RX_DROP_2_1 0x121c8
45236 #define A_MPS_RX_DROP_2_2 0x121cc
45237 #define A_MPS_RX_DROP_2_3 0x121d0
45238 #define A_MPS_RX_DROP_2_4 0x121d4
45239 #define A_MPS_RX_DROP_2_5 0x121d8
45240 #define A_MPS_RX_DROP_2_6 0x121dc
45241 #define A_MPS_RX_DROP_2_7 0x121e0
45242 #define A_MPS_RX_DROP_3_0 0x121e4
45243 #define A_MPS_RX_DROP_3_1 0x121e8
45244 #define A_MPS_RX_DROP_3_2 0x121ec
45245 #define A_MPS_RX_DROP_3_3 0x121f0
45246 #define A_MPS_RX_DROP_3_4 0x121f4
45247 #define A_MPS_RX_DROP_3_5 0x121f8
45248 #define A_MPS_RX_DROP_3_6 0x121fc
45249 #define A_MPS_RX_DROP_3_7 0x12200
45250 #define A_MPS_RX_MAC_BG_PG_CNT0_0 0x12204
45251 #define A_MPS_RX_MAC_BG_PG_CNT0_1 0x12208
45252 #define A_MPS_RX_MAC_BG_PG_CNT0_2 0x1220c
45253 #define A_MPS_RX_MAC_BG_PG_CNT0_3 0x12210
45254 #define A_MPS_RX_MAC_BG_PG_CNT0_4 0x12214
45255 #define A_MPS_RX_MAC_BG_PG_CNT0_5 0x12218
45256 #define A_MPS_RX_MAC_BG_PG_CNT0_6 0x1221c
45257 #define A_MPS_RX_MAC_BG_PG_CNT0_7 0x12220
45258 #define A_MPS_RX_MAC_BG_PG_CNT1_0 0x12224
45259 #define A_MPS_RX_MAC_BG_PG_CNT1_1 0x12228
45260 #define A_MPS_RX_MAC_BG_PG_CNT1_2 0x1222c
45261 #define A_MPS_RX_MAC_BG_PG_CNT1_3 0x12230
45262 #define A_MPS_RX_MAC_BG_PG_CNT1_4 0x12234
45263 #define A_MPS_RX_MAC_BG_PG_CNT1_5 0x12238
45264 #define A_MPS_RX_MAC_BG_PG_CNT1_6 0x1223c
45265 #define A_MPS_RX_MAC_BG_PG_CNT1_7 0x12240
45266 #define A_MPS_RX_MAC_BG_PG_CNT2_0 0x12244
45267 #define A_MPS_RX_MAC_BG_PG_CNT2_1 0x12248
45268 #define A_MPS_RX_MAC_BG_PG_CNT2_2 0x1224c
45269 #define A_MPS_RX_MAC_BG_PG_CNT2_3 0x12250
45270 #define A_MPS_RX_MAC_BG_PG_CNT2_4 0x12254
45271 #define A_MPS_RX_MAC_BG_PG_CNT2_5 0x12258
45272 #define A_MPS_RX_MAC_BG_PG_CNT2_6 0x1225c
45273 #define A_MPS_RX_MAC_BG_PG_CNT2_7 0x12260
45274 #define A_MPS_RX_MAC_BG_PG_CNT3_0 0x12264
45275 #define A_MPS_RX_MAC_BG_PG_CNT3_1 0x12268
45276 #define A_MPS_RX_MAC_BG_PG_CNT3_2 0x1226c
45277 #define A_MPS_RX_MAC_BG_PG_CNT3_3 0x12270
45278 #define A_MPS_RX_MAC_BG_PG_CNT3_4 0x12274
45279 #define A_MPS_RX_MAC_BG_PG_CNT3_5 0x12278
45280 #define A_MPS_RX_MAC_BG_PG_CNT3_6 0x1227c
45281 #define A_MPS_RX_MAC_BG_PG_CNT3_7 0x12280
45282 #define A_T7_MPS_RX_PAUSE_GEN_TH_0 0x12284
45283 #define A_T7_MPS_RX_PAUSE_GEN_TH_1 0x12288
45284 #define A_T7_MPS_RX_PAUSE_GEN_TH_2 0x1228c
45285 #define A_T7_MPS_RX_PAUSE_GEN_TH_3 0x12290
45286 #define A_MPS_RX_BG0_IPSEC_CNT 0x12294
45287 #define A_MPS_RX_BG1_IPSEC_CNT 0x12298
45288 #define A_MPS_RX_BG2_IPSEC_CNT 0x1229c
45289 #define A_MPS_RX_BG3_IPSEC_CNT 0x122a0
45290 #define A_MPS_RX_MEM_FIFO_CONFIG0 0x122a4
45293 #define M_FIFO_CONFIG2    0xffffU
45297 #define S_FIFO_CONFIG1    0
45298 #define M_FIFO_CONFIG1    0xffffU
45302 #define A_MPS_RX_MEM_FIFO_CONFIG1 0x122a8
45304 #define S_FIFO_CONFIG3    0
45305 #define M_FIFO_CONFIG3    0xffffU
45309 #define A_MPS_LPBK_MEM_FIFO_CONFIG0 0x122ac
45310 #define A_MPS_LPBK_MEM_FIFO_CONFIG1 0x122b0
45311 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG0 0x122b4
45312 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG1 0x122b8
45313 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG2 0x122bc
45314 #define A_MPS_RX_LPBK_CONGESTION_THRESHOLD_BG3 0x122c0
45315 #define A_MPS_BG_PAUSE_CTL 0x122c4
45329 #define S_BG3_PAUSE_EN    0
45334 #define CPL_SWITCH_BASE_ADDR 0x19040
45336 #define A_CPL_SWITCH_CNTRL 0x19040
45339 #define M_CPL_PKT_TID    0xffffffU
45363 #define S_CIM_ENABLE    0
45371 #define A_CNTRL 0x19040
45372 #define A_CPL_SWITCH_TBL_IDX 0x19044
45374 #define S_SWITCH_TBL_IDX    0
45375 #define M_SWITCH_TBL_IDX    0xfU
45379 #define A_TBL_IDX 0x19044
45380 #define A_CPL_SWITCH_TBL_DATA 0x19048
45381 #define A_TBL_DATA 0x19048
45382 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
45385 #define M_ZERO_CMD_CH1    0xffU
45389 #define S_ZERO_CMD_CH0    0
45390 #define M_ZERO_CMD_CH0    0xffU
45394 #define A_ZERO_ERROR 0x1904c
45397 #define M_ZERO_CMD_CH3    0xffU
45402 #define M_ZERO_CMD_CH2    0xffU
45406 #define A_CPL_INTR_ENABLE 0x19050
45428 #define S_ZERO_SWITCH_ERROR    0
45440 #define A_INTR_ENABLE 0x19050
45450 #define A_CPL_INTR_CAUSE 0x19054
45451 #define A_INTR_CAUSE 0x19054
45452 #define A_CPL_MAP_TBL_IDX 0x19058
45454 #define S_MAP_TBL_IDX    0
45455 #define M_MAP_TBL_IDX    0xffU
45463 #define A_MAP_TBL_IDX 0x19058
45466 #define M_CPL_MAP_TBL_SEL    0x3U
45470 #define A_CPL_MAP_TBL_DATA 0x1905c
45472 #define S_MAP_TBL_DATA    0
45473 #define M_MAP_TBL_DATA    0xffU
45477 #define A_MAP_TBL_DATA 0x1905c
45480 #define SMB_BASE_ADDR 0x19060
45482 #define A_SMB_GLOBAL_TIME_CFG 0x19060
45485 #define M_MACROCNTCFG    0x1fU
45489 #define S_MICROCNTCFG    0
45490 #define M_MICROCNTCFG    0xffU
45495 #define M_T7_MACROCNTCFG    0x1fU
45499 #define S_T7_MICROCNTCFG    0
45500 #define M_T7_MICROCNTCFG    0xfffU
45504 #define A_SMB_MST_TIMEOUT_CFG 0x19064
45506 #define S_MSTTIMEOUTCFG    0
45507 #define M_MSTTIMEOUTCFG    0xffffffU
45511 #define A_SMB_MST_CTL_CFG 0x19068
45522 #define M_MSTRXBYTECFG    0x3fU
45527 #define M_MSTTXBYTECFG    0x3fU
45535 #define S_MSTCTLEN    0
45539 #define A_SMB_MST_CTL_STS 0x1906c
45542 #define M_MSTRXBYTECNT    0x3fU
45547 #define M_MSTTXBYTECNT    0x3fU
45551 #define S_MSTBUSYSTS    0
45555 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
45556 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
45557 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
45559 #define S_SLVTIMEOUTCFG    0
45560 #define M_SLVTIMEOUTCFG    0xffffffU
45564 #define A_SMB_SLV_CTL_CFG 0x1907c
45587 #define M_SLVCRCPRESET    0xffU
45592 #define M_SLVADDRCFG    0x7fU
45604 #define S_SLVCTLEN    0
45608 #define A_SMB_SLV_CTL_STS 0x19080
45611 #define M_SLVFIFOTXCNT    0x3fU
45616 #define M_SLVFIFOCNT    0x3fU
45624 #define S_SLVBUSYSTS    0
45628 #define A_SMB_SLV_FIFO_RDWR 0x19084
45629 #define A_SMB_INT_ENABLE 0x1908c
45715 #define S_MSTDONEINTEN    0
45719 #define A_SMB_INT_CAUSE 0x19090
45805 #define S_MSTDONEINT    0
45809 #define A_SMB_DEBUG_DATA 0x19094
45812 #define M_DEBUGDATAH    0xffffU
45816 #define S_DEBUGDATAL    0
45817 #define M_DEBUGDATAL    0xffffU
45821 #define A_SMB_PERR_EN 0x19098
45831 #define S_SLVFIFOPERREN    0
45847 #define A_SMB_PERR_INJ 0x1909c
45861 #define S_FIFOINJDATAERREN    0
45865 #define A_SMB_SLV_ARP_CTL 0x190a0
45868 #define M_ARPCOMMANDCODE    0xffU
45876 #define S_ARPADDRVAL    0
45880 #define A_SMB_ARP_UDID0 0x190a4
45881 #define A_SMB_ARP_UDID1 0x190a8
45884 #define M_SUBSYSTEMVENDORID    0xffffU
45888 #define S_SUBSYSTEMDEVICEID    0
45889 #define M_SUBSYSTEMDEVICEID    0xffffU
45893 #define A_SMB_ARP_UDID2 0x190ac
45896 #define M_DEVICEID    0xffffU
45900 #define S_INTERFACE    0
45901 #define M_INTERFACE    0xffffU
45905 #define A_SMB_ARP_UDID3 0x190b0
45908 #define M_DEVICECAP    0xffU
45913 #define M_VERSIONID    0xffU
45917 #define S_VENDORID    0
45918 #define M_VENDORID    0xffffU
45922 #define A_SMB_SLV_AUX_ADDR0 0x190b4
45928 #define S_AUXADDR0    0
45929 #define M_AUXADDR0    0x3fU
45933 #define A_SMB_SLV_AUX_ADDR1 0x190b8
45939 #define S_AUXADDR1    0
45940 #define M_AUXADDR1    0x3fU
45944 #define A_SMB_SLV_AUX_ADDR2 0x190bc
45950 #define S_AUXADDR2    0
45951 #define M_AUXADDR2    0x3fU
45955 #define A_SMB_SLV_AUX_ADDR3 0x190c0
45961 #define S_AUXADDR3    0
45962 #define M_AUXADDR3    0x3fU
45966 #define A_SMB_COMMAND_CODE0 0x190c4
45968 #define S_SMBUSCOMMANDCODE0    0
45969 #define M_SMBUSCOMMANDCODE0    0xffU
45973 #define A_SMB_COMMAND_CODE1 0x190c8
45975 #define S_SMBUSCOMMANDCODE1    0
45976 #define M_SMBUSCOMMANDCODE1    0xffU
45980 #define A_SMB_COMMAND_CODE2 0x190cc
45982 #define S_SMBUSCOMMANDCODE2    0
45983 #define M_SMBUSCOMMANDCODE2    0xffU
45987 #define A_SMB_COMMAND_CODE3 0x190d0
45989 #define S_SMBUSCOMMANDCODE3    0
45990 #define M_SMBUSCOMMANDCODE3    0xffU
45994 #define A_SMB_COMMAND_CODE4 0x190d4
45996 #define S_SMBUSCOMMANDCODE4    0
45997 #define M_SMBUSCOMMANDCODE4    0xffU
46001 #define A_SMB_COMMAND_CODE5 0x190d8
46003 #define S_SMBUSCOMMANDCODE5    0
46004 #define M_SMBUSCOMMANDCODE5    0xffU
46008 #define A_SMB_COMMAND_CODE6 0x190dc
46010 #define S_SMBUSCOMMANDCODE6    0
46011 #define M_SMBUSCOMMANDCODE6    0xffU
46015 #define A_SMB_COMMAND_CODE7 0x190e0
46017 #define S_SMBUSCOMMANDCODE7    0
46018 #define M_SMBUSCOMMANDCODE7    0xffU
46022 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
46025 #define M_MACROCNTCLKCFG    0x1fU
46029 #define S_MICROCNTCLKCFG    0
46030 #define M_MICROCNTCLKCFG    0xffU
46034 #define A_SMB_CTL_STATUS 0x190e8
46044 #define S_BUSBUSY    0
46049 #define I2CM_BASE_ADDR 0x190f0
46051 #define A_I2CM_CFG 0x190f0
46053 #define S_I2C_CLKDIV    0
46054 #define M_I2C_CLKDIV    0xfffU
46058 #define S_I2C_CLKDIV16B    0
46059 #define M_I2C_CLKDIV16B    0xffffU
46063 #define A_I2CM_DATA 0x190f4
46065 #define S_I2C_DATA    0
46066 #define M_I2C_DATA    0xffU
46070 #define A_I2CM_OP 0x190f8
46080 #define S_OP    0
46085 #define MI_BASE_ADDR 0x19100
46087 #define A_MI_CFG 0x19100
46094 #define M_CLKDIV    0xffU
46099 #define M_ST    0x3U
46111 #define S_MDIO_1P2V_SEL    0
46115 #define A_MI_ADDR 0x19104
46118 #define M_PHYADDR    0x1fU
46122 #define S_REGADDR    0
46123 #define M_REGADDR    0x1fU
46127 #define A_MI_DATA 0x19108
46129 #define S_MDIDATA    0
46130 #define M_MDIDATA    0xffffU
46134 #define A_MI_OP 0x1910c
46140 #define S_MDIOP    0
46141 #define M_MDIOP    0x3U
46146 #define UART_BASE_ADDR 0x19110
46148 #define A_UART_CONFIG 0x19110
46151 #define M_STOPBITS    0x3U
46156 #define M_PARITY    0x3U
46161 #define M_DATABITS    0xfU
46165 #define S_UART_CLKDIV    0
46166 #define M_UART_CLKDIV    0xfffU
46171 #define M_T7_STOPBITS    0x3U
46176 #define M_T7_PARITY    0x3U
46181 #define M_T7_DATABITS    0xfU
46185 #define S_T7_UART_CLKDIV    0
46186 #define M_T7_UART_CLKDIV    0x3ffffU
46191 #define PMU_BASE_ADDR 0x19120
46193 #define A_PMU_PART_CG_PWRMODE 0x19120
46223 #define S_INITPOWERMODE    0
46224 #define M_INITPOWERMODE    0x3U
46292 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
46314 #define S_WAKEUP    0
46323 #define ULP_RX_BASE_ADDR 0x19150
46325 #define A_ULP_RX_CTL 0x19150
46328 #define M_PCMD1THRESHOLD    0xffU
46333 #define M_PCMD0THRESHOLD    0xffU
46342 #define M_RDMA_0B_WR_OPCODE    0xfU
46382 #define S_TDDPTAGTCB    0
46435 #define M_NVME_TCP_OFFSET_SUBMODE    0x3U
46448 #define M_RDMA_0B_WR_OPCODE_LO    0xfU
46452 #define A_ULP_RX_INT_ENABLE 0x19154
46550 #define S_ENABLE_MPARC_0    0
46638 #define S_T7_ENABLE_ALN_SDC_ERR_0    0
46642 #define A_ULP_RX_INT_CAUSE 0x19158
46740 #define S_CAUSE_MPARC_0    0
46744 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
46747 #define M_ISCSILLIMIT    0x3ffffffU
46751 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
46754 #define M_ISCSIULIMIT    0x3ffffffU
46758 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
46761 #define M_ISCSITAGMASK    0x3ffffffU
46765 #define A_ULP_RX_ISCSI_PSZ 0x19168
46768 #define M_HPZ3    0xfU
46773 #define M_HPZ2    0xfU
46778 #define M_HPZ1    0xfU
46782 #define S_HPZ0    0
46783 #define M_HPZ0    0xfU
46787 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
46790 #define M_TDDPLLIMIT    0x3ffffffU
46794 #define A_ULP_RX_TDDP_ULIMIT 0x19170
46797 #define M_TDDPULIMIT    0x3ffffffU
46801 #define A_ULP_RX_TDDP_TAGMASK 0x19174
46804 #define M_TDDPTAGMASK    0x3ffffffU
46808 #define A_ULP_RX_TDDP_PSZ 0x19178
46809 #define A_ULP_RX_STAG_LLIMIT 0x1917c
46810 #define A_ULP_RX_STAG_ULIMIT 0x19180
46811 #define A_ULP_RX_RQ_LLIMIT 0x19184
46812 #define A_ULP_RX_RQ_ULIMIT 0x19188
46813 #define A_ULP_RX_PBL_LLIMIT 0x1918c
46814 #define A_ULP_RX_PBL_ULIMIT 0x19190
46815 #define A_ULP_RX_CTX_BASE 0x19194
46816 #define A_ULP_RX_PERR_ENABLE 0x1919c
46906 #define S_PERR_ENABLE_MPARC_0    0
46934 #define A_ULP_RX_PERR_INJECT 0x191a0
46935 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
46936 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
46937 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
46947 #define S_ULPRX_TID    0
46948 #define M_ULPRX_TID    0xfffffU
46952 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
46953 #define A_ULP_RX_CTX_ACC_CH2 0x191b4
46954 #define A_ULP_RX_CTX_ACC_CH3 0x191b8
46955 #define A_ULP_RX_CTL2 0x191bc
46958 #define M_PCMD3THRESHOLD    0xffU
46963 #define M_PCMD2THRESHOLD    0xffU
46968 #define M_T7_PCMD1THRESHOLD    0xffU
46972 #define S_T7_PCMD0THRESHOLD    0
46973 #define M_T7_PCMD0THRESHOLD    0xffU
46977 #define A_ULP_RX_INT_ENABLE_INTERFACE 0x191c0
47067 #define S_ENABLE_TP2ULP_PCMD_0    0
47071 #define A_ULP_RX_INT_CAUSE_INTERFACE 0x191c4
47161 #define S_CAUSE_TP2ULP_PCMD_0    0
47165 #define A_ULP_RX_PERR_ENABLE_INTERFACE 0x191c8
47255 #define S_PERR_TP2ULP_PCMD_0    0
47259 #define A_ULP_RX_SE_CNT_ERR 0x191d0
47260 #define A_ULP_RX_SE_CNT_CLR 0x191d4
47263 #define M_CLRCHAN0    0xfU
47267 #define S_CLRCHAN1    0
47268 #define M_CLRCHAN1    0xfU
47273 #define M_CLRCHAN3    0xfU
47278 #define M_CLRCHAN2    0xfU
47283 #define M_T7_CLRCHAN1    0xfU
47287 #define S_T7_CLRCHAN0    0
47288 #define M_T7_CLRCHAN0    0xfU
47292 #define A_ULP_RX_SE_CNT_CH0 0x191d8
47295 #define M_SOP_CNT_OUT0    0xfU
47300 #define M_EOP_CNT_OUT0    0xfU
47305 #define M_SOP_CNT_AL0    0xfU
47310 #define M_EOP_CNT_AL0    0xfU
47315 #define M_SOP_CNT_MR0    0xfU
47320 #define M_EOP_CNT_MR0    0xfU
47325 #define M_SOP_CNT_IN0    0xfU
47329 #define S_EOP_CNT_IN0    0
47330 #define M_EOP_CNT_IN0    0xfU
47334 #define A_ULP_RX_SE_CNT_CH1 0x191dc
47337 #define M_SOP_CNT_OUT1    0xfU
47342 #define M_EOP_CNT_OUT1    0xfU
47347 #define M_SOP_CNT_AL1    0xfU
47352 #define M_EOP_CNT_AL1    0xfU
47357 #define M_SOP_CNT_MR1    0xfU
47362 #define M_EOP_CNT_MR1    0xfU
47367 #define M_SOP_CNT_IN1    0xfU
47371 #define S_EOP_CNT_IN1    0
47372 #define M_EOP_CNT_IN1    0xfU
47376 #define A_ULP_RX_DBG_CTL 0x191e0
47387 #define M_SEL_H    0xffU
47391 #define S_SEL_L    0
47392 #define M_SEL_L    0xffU
47396 #define A_ULP_RX_DBG_DATAH 0x191e4
47397 #define A_ULP_RX_DBG_DATA 0x191e4
47398 #define A_ULP_RX_DBG_DATAL 0x191e8
47399 #define A_ULP_RX_LA_CHNL 0x19238
47401 #define S_CHNL_SEL    0
47405 #define A_ULP_RX_LA_CTL 0x1923c
47407 #define S_TRC_SEL    0
47411 #define A_ULP_RX_LA_RDPTR 0x19240
47413 #define S_RD_PTR    0
47414 #define M_RD_PTR    0x1ffU
47418 #define A_ULP_RX_LA_RDDATA 0x19244
47419 #define A_ULP_RX_LA_WRPTR 0x19248
47421 #define S_WR_PTR    0
47422 #define M_WR_PTR    0x1ffU
47426 #define A_ULP_RX_LA_RESERVED 0x1924c
47427 #define A_ULP_RX_CQE_GEN_EN 0x19250
47433 #define S_TERMINATE_WITH_ERR    0
47437 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
47440 #define M_ATOMIC_REQ_QNO    0x3U
47445 #define M_ATOMIC_RSP_QNO    0x3U
47450 #define M_IMMEDIATE_QNO    0x3U
47455 #define M_IMMEDIATE_WITH_SE_QNO    0x3U
47460 #define M_ATOMIC_WR_OPCODE    0xfU
47465 #define M_ATOMIC_RD_OPCODE    0xfU
47470 #define M_IMMEDIATE_OPCODE    0xfU
47474 #define S_IMMEDIATE_WITH_SE_OPCODE    0
47475 #define M_IMMEDIATE_WITH_SE_OPCODE    0xfU
47479 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
47481 #define S_EN_ORIG_DATA    0
47485 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
47503 #define S_SDC_CRC_PROT_EN    0
47516 #define M_DDP_VERSION_1    0x3U
47521 #define M_DDP_VERSION_0    0x3U
47526 #define M_RDMA_VERSION_1    0x3U
47531 #define M_RDMA_VERSION_0    0x3U
47580 #define M_TLS_KEYSIZECONF    0x3U
47584 #define A_ULP_RX_CH0_CGEN 0x19260
47614 #define S_RDMA_DATAPATH_CGEN    0
47618 #define A_ULP_RX_CH_CGEN 0x19260
47621 #define M_T7_BYPASS_CGEN    0xfU
47626 #define M_T7_TDDP_CGEN    0xfU
47631 #define M_T7_ISCSI_CGEN    0xfU
47636 #define M_T7_RDMA_CGEN    0xfU
47641 #define M_T7_CHANNEL_CGEN    0xfU
47646 #define M_T7_ALL_DATAPATH_CGEN    0xfU
47651 #define M_T7_T10DIFF_DATAPATH_CGEN    0xfU
47655 #define S_T7_RDMA_DATAPATH_CGEN    0
47656 #define M_T7_RDMA_DATAPATH_CGEN    0xfU
47660 #define A_ULP_RX_CH1_CGEN 0x19264
47661 #define A_ULP_RX_CH_CGEN_1 0x19264
47664 #define M_NVME_TCP_CGEN    0xfU
47668 #define S_ROCE_CGEN    0
47669 #define M_ROCE_CGEN    0xfU
47673 #define A_ULP_RX_RFE_DISABLE 0x19268
47675 #define S_RQE_LIM_CHECK_RFE_DISABLE    0
47679 #define A_ULP_RX_INT_ENABLE_2 0x1926c
47713 #define S_DDP_HINT_0    0
47717 #define A_ULP_RX_INT_CAUSE_2 0x19270
47718 #define A_ULP_RX_PERR_ENABLE_2 0x19274
47752 #define S_ENABLE_DDP_HINT_0    0
47756 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
47758 #define S_PIO_RQE_PBL_MULTIPLE_CNT    0
47759 #define M_PIO_RQE_PBL_MULTIPLE_CNT    0xfU
47763 #define A_ULP_RX_ATOMIC_LEN 0x1927c
47766 #define M_ATOMIC_RPL_LEN    0xffU
47771 #define M_ATOMIC_REQ_LEN    0xffU
47775 #define S_ATOMIC_IMMEDIATE_LEN    0
47776 #define M_ATOMIC_IMMEDIATE_LEN    0xffU
47780 #define A_ULP_RX_CGEN_GLOBAL 0x19280
47781 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
47795 #define S_SKIP_MA_REQ_EN0    0
47823 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
47824 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
47825 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
47835 #define S_SEND_MSN_CHECK_ENABLE    0
47839 #define A_ULP_RX_SE_CNT_CH2 0x19294
47842 #define M_SOP_CNT_OUT2    0xfU
47847 #define M_EOP_CNT_OUT2    0xfU
47852 #define M_SOP_CNT_AL2    0xfU
47857 #define M_EOP_CNT_AL2    0xfU
47862 #define M_SOP_CNT_MR2    0xfU
47867 #define M_EOP_CNT_MR2    0xfU
47872 #define M_SOP_CNT_IN2    0xfU
47876 #define S_EOP_CNT_IN2    0
47877 #define M_EOP_CNT_IN2    0xfU
47881 #define A_ULP_RX_SE_CNT_CH3 0x19298
47884 #define M_SOP_CNT_OUT3    0xfU
47889 #define M_EOP_CNT_OUT3    0xfU
47894 #define M_SOP_CNT_AL3    0xfU
47899 #define M_EOP_CNT_AL3    0xfU
47904 #define M_SOP_CNT_MR3    0xfU
47909 #define M_EOP_CNT_MR3    0xfU
47914 #define M_SOP_CNT_IN3    0xfU
47918 #define S_EOP_CNT_IN3    0
47919 #define M_EOP_CNT_IN3    0xfU
47923 #define A_ULP_RX_CHNL2_CTX_ERROR_COUNT_PER_TID 0x1929c
47924 #define A_ULP_RX_CHNL3_CTX_ERROR_COUNT_PER_TID 0x192a0
47925 #define A_ULP_RX_TLS_PP_LLIMIT 0x192a4
47928 #define M_TLSPPLLIMIT    0x3ffffffU
47932 #define A_ULP_RX_TLS_PP_ULIMIT 0x192a8
47935 #define M_TLSPPULIMIT    0x3ffffffU
47939 #define A_ULP_RX_TLS_KEY_LLIMIT 0x192ac
47942 #define M_TLSKEYLLIMIT    0xffffffU
47946 #define A_ULP_RX_TLS_KEY_ULIMIT 0x192b0
47949 #define M_TLSKEYULIMIT    0xffffffU
47953 #define A_ULP_RX_TLS_CTL 0x192bc
47954 #define A_ULP_RX_RRQ_LLIMIT 0x192c0
47955 #define A_ULP_RX_RRQ_ULIMIT 0x192c4
47956 #define A_ULP_RX_NVME_TCP_STAG_LLIMIT 0x192c8
47957 #define A_ULP_RX_NVME_TCP_STAG_ULIMIT 0x192cc
47958 #define A_ULP_RX_NVME_TCP_RQ_LLIMIT 0x192d0
47959 #define A_ULP_RX_NVME_TCP_RQ_ULIMIT 0x192d4
47960 #define A_ULP_RX_NVME_TCP_PBL_LLIMIT 0x192d8
47961 #define A_ULP_RX_NVME_TCP_PBL_ULIMIT 0x192dc
47962 #define A_ULP_RX_NVME_TCP_MAX_LENGTH 0x192e0
47965 #define M_NVME_TCP_MAX_PLEN01    0xffU
47970 #define M_NVME_TCP_MAX_PLEN23    0xffU
47974 #define S_NVME_TCP_MAX_CMD_PDU_LENGTH    0
47975 #define M_NVME_TCP_MAX_CMD_PDU_LENGTH    0xffffU
47979 #define A_ULP_RX_NVME_TCP_IQE_SIZE 0x192e4
47980 #define A_ULP_RX_NVME_TCP_NEW_PDU_TYPES 0x192e8
47981 #define A_ULP_RX_IWARP_PMOF_OPCODES_1 0x192ec
47982 #define A_ULP_RX_IWARP_PMOF_OPCODES_2 0x192f0
47983 #define A_ULP_RX_INT_ENABLE_PCMD 0x19300
48093 #define S_ENABLE_PCMD_MPAC_0    0
48097 #define A_ULP_RX_INT_CAUSE_PCMD 0x19304
48207 #define S_CAUSE_PCMD_MPAC_0    0
48211 #define A_ULP_RX_PERR_ENABLE_PCMD 0x19308
48321 #define S_PERR_ENABLE_PCMD_MPAC_0    0
48325 #define A_ULP_RX_INT_ENABLE_DATA 0x19310
48419 #define S_ENABLE_DATA_PARSER_0    0
48423 #define A_ULP_RX_INT_CAUSE_DATA 0x19314
48517 #define S_CAUSE_DATA_PARSER_0    0
48521 #define A_ULP_RX_PERR_ENABLE_DATA 0x19318
48615 #define S_PERR_ENABLE_DATA_PARSER_0    0
48619 #define A_ULP_RX_INT_ENABLE_ARB 0x19320
48681 #define S_ENABLE_ARB_F_0    0
48685 #define A_ULP_RX_INT_CAUSE_ARB 0x19324
48747 #define S_CAUSE_ARB_F_0    0
48751 #define A_ULP_RX_PERR_ENABLE_ARB 0x19328
48813 #define S_PERR_ENABLE_ARB_F_0    0
48817 #define A_ULP_RX_CTL1 0x19330
48832 #define M_NVME_TCP_DATA_ALIGNMENT    0x1ffU
48837 #define M_NVME_TCP_INVLD_MSG_DIS    0x3U
48850 #define M_NVME_TCP_COLOUR_ENB    0x3U
48859 #define M_RDMA_INVLD_MSG_DIS    0x3U
48864 #define M_ROCE_INVLD_MSG_DIS    0x3U
48869 #define M_T7_MEM_ADDR_CTRL    0x3U
48877 #define S_C2H_SUCCESS_WO_LAST_PDU_CHK_DIS    0
48881 #define A_ULP_RX_TLS_IND_CMD 0x19348
48883 #define S_TLS_RX_REG_OFF_ADDR    0
48884 #define M_TLS_RX_REG_OFF_ADDR    0x3ffU
48888 #define A_ULP_RX_TLS_IND_DATA 0x1934c
48889 #define A_ULP_RX_TLS_CH0_HMACCTRL_CFG 0x20
48890 #define A_ULP_RX_TLS_CH1_HMACCTRL_CFG 0x60
48893 #define SF_BASE_ADDR 0x193f8
48895 #define A_SF_DATA 0x193f8
48896 #define A_SF_OP 0x193fc
48907 #define M_BYTECNT    0x3U
48916 #define M_NUM_OF_BYTES    0x3U
48945 #define PL_BASE_ADDR 0x19400
48947 #define A_PL_VF_WHOAMI 0x0
48950 #define M_PORTXMAP    0x7U
48955 #define M_SOURCEBUS    0x3U
48960 #define M_SOURCEPF    0x7U
48968 #define S_VFID    0
48969 #define M_VFID    0x7fU
48974 #define M_T6_SOURCEPF    0x7U
48982 #define S_T6_VFID    0
48983 #define M_T6_VFID    0xffU
48987 #define A_PL_VF_REV 0x4
48990 #define M_CHIPID    0xfU
48994 #define A_PL_VF_REVISION 0x8
48995 #define A_PL_PF_INT_CAUSE 0x3c0
49009 #define S_PFMPS    0
49013 #define A_PL_PF_INT_ENABLE 0x3c4
49014 #define A_PL_PF_CTL 0x3c8
49016 #define S_SWINT    0
49020 #define A_PL_WHOAMI 0x19400
49021 #define A_PL_PERR_CAUSE 0x19404
49135 #define S_CIM    0
49275 #define S_T7_PL_PERR_CIM    0
49279 #define A_PL_PERR_ENABLE 0x19408
49280 #define A_PL_INT_CAUSE 0x1940c
49378 #define A_PL_INT_ENABLE 0x19410
49379 #define A_PL_INT_MAP0 0x19414
49382 #define M_MAPNCSI    0x1ffU
49386 #define S_MAPDEFAULT    0
49387 #define M_MAPDEFAULT    0x1ffU
49391 #define A_PL_INT_MAP1 0x19418
49394 #define M_MAPXGMAC1    0x1ffU
49398 #define S_MAPXGMAC0    0
49399 #define M_MAPXGMAC0    0x1ffU
49404 #define M_MAPMAC1    0x1ffU
49408 #define S_MAPMAC0    0
49409 #define M_MAPMAC0    0x1ffU
49413 #define A_PL_INT_MAP2 0x1941c
49416 #define M_MAPXGMAC_KR1    0x1ffU
49420 #define S_MAPXGMAC_KR0    0
49421 #define M_MAPXGMAC_KR0    0x1ffU
49426 #define M_MAPMAC3    0x1ffU
49430 #define S_MAPMAC2    0
49431 #define M_MAPMAC2    0x1ffU
49435 #define A_PL_INT_MAP3 0x19420
49438 #define M_MAPMI    0x1ffU
49442 #define S_MAPSMB    0
49443 #define M_MAPSMB    0x1ffU
49447 #define A_PL_INT_MAP4 0x19424
49450 #define M_MAPDBG    0x1ffU
49454 #define S_MAPI2CM    0
49455 #define M_MAPI2CM    0x1ffU
49459 #define A_PL_RST 0x19428
49473 #define S_PIORSTMODE    0
49481 #define A_PL_PL_PERR_INJECT 0x1942c
49487 #define A_PL_PL_INT_CAUSE 0x19430
49509 #define S_PERRVFID    0
49517 #define A_PL_PL_INT_ENABLE 0x19434
49518 #define A_PL_PL_PERR_ENABLE 0x19438
49519 #define A_PL_REV 0x1943c
49521 #define S_REV    0
49522 #define M_REV    0xfU
49526 #define A_PL_PCIE_LINK 0x19440
49529 #define M_LN0_AESTAT    0x7U
49534 #define M_LN0_AECMD    0x7U
49539 #define M_T5_STATECFGINITF    0x7fU
49544 #define M_T5_STATECFGINIT    0xfU
49549 #define M_PCIE_SPEED    0x3U
49561 #define S_LTSSM    0
49562 #define M_LTSSM    0x3fU
49567 #define M_T6_LN0_AESTAT    0x7U
49572 #define M_T6_LN0_AECMD    0x7U
49577 #define M_T6_1_STATECFGINITF    0xffU
49586 #define M_SPEED_PL    0x3U
49598 #define A_PL_PCIE_CTL_STAT 0x19444
49601 #define M_PCIE_STATUS    0xffffU
49605 #define S_PCIE_CONTROL    0
49606 #define M_PCIE_CONTROL    0xffffU
49610 #define A_PL_SEMAPHORE_CTL 0x1944c
49613 #define M_LOCKSTATUS    0xffU
49621 #define S_ENABLEPF    0
49622 #define M_ENABLEPF    0xffU
49626 #define A_PL_SEMAPHORE_LOCK 0x19450
49633 #define M_SEMSRCBUS    0x3U
49637 #define S_SEMSRCPF    0
49638 #define M_SEMSRCPF    0x7U
49642 #define A_PL_PF_ENABLE 0x19470
49644 #define S_PF_ENABLE    0
49645 #define M_PF_ENABLE    0xffU
49649 #define A_PL_PORTX_MAP 0x19474
49652 #define M_MAP7    0x7U
49657 #define M_MAP6    0x7U
49662 #define M_MAP5    0x7U
49667 #define M_MAP4    0x7U
49672 #define M_MAP3    0x7U
49677 #define M_MAP2    0x7U
49682 #define M_MAP1    0x7U
49686 #define S_MAP0    0
49687 #define M_MAP0    0x7U
49691 #define A_PL_INT_CAUSE2 0x19478
49709 #define S_ARM    0
49713 #define A_PL_INT_ENABLE2 0x1947c
49714 #define A_PL_ER_CMD 0x19488
49717 #define M_ER_ADDR    0x3fffffffU
49721 #define A_PL_ER_DATA 0x1948c
49722 #define A_PL_VF_SLICE_L 0x19490
49725 #define M_LIMITADDR    0x3ffU
49729 #define S_SLICEBASEADDR    0
49730 #define M_SLICEBASEADDR    0x3ffU
49734 #define A_PL_VF_SLICE_H 0x19494
49737 #define M_MODINDX    0x7U
49741 #define S_MODOFFSET    0
49742 #define M_MODOFFSET    0x3ffU
49746 #define A_PL_FLR_VF_STATUS 0x194d0
49747 #define A_PL_FLR_PF_STATUS 0x194e0
49749 #define S_FLR_PF    0
49750 #define M_FLR_PF    0xffU
49754 #define A_PL_TIMEOUT_CTL 0x194f0
49756 #define S_PL_TIMEOUT    0
49757 #define M_PL_TIMEOUT    0xffffU
49765 #define A_PL_TIMEOUT_STATUS0 0x194f4
49768 #define M_PL_TOADDR    0xfffffffU
49772 #define A_PL_TIMEOUT_STATUS1 0x194f8
49783 #define M_PL_TOBUS    0x3U
49792 #define M_PL_TOPF    0x7U
49796 #define S_PL_TORID    0
49797 #define M_PL_TORID    0xffffU
49805 #define S_PL_TOVFID    0
49806 #define M_PL_TOVFID    0xffU
49810 #define S_T6_PL_TOVFID    0
49811 #define M_T6_PL_TOVFID    0x1ffU
49815 #define A_PL_VFID_MAP 0x19800
49822 #define LE_BASE_ADDR 0x19c00
49824 #define A_LE_BUF_CONFIG 0x19c00
49825 #define A_LE_DB_ID 0x19c00
49826 #define A_LE_DB_CONFIG 0x19c04
49853 #define M_SYNMODE    0x3U
49877 #define S_CMDOVERLAPDIS    0
49973 #define S_REGION_EN    0
49974 #define M_REGION_EN    0xfU
49982 #define A_LE_MISC 0x19c08
49984 #define S_CMPUNVAIL    0
49985 #define M_CMPUNVAIL    0xfU
50021 #define A_LE_DB_EXEC_CTRL 0x19c08
50035 #define S_CMDLIMIT    0
50036 #define M_CMDLIMIT    0xffU
50040 #define A_LE_DB_PS_CTRL 0x19c0c
50058 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
50061 #define M_RTINDX    0x3fU
50065 #define A_LE_DB_ACTIVE_TABLE_START_INDEX 0x19c10
50067 #define S_ATINDX    0
50068 #define M_ATINDX    0xfffffU
50072 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
50075 #define M_FTINDX    0x3fU
50079 #define A_LE_DB_NORM_FILT_TABLE_START_INDEX 0x19c14
50081 #define S_NFTINDX    0
50082 #define M_NFTINDX    0xfffffU
50086 #define A_LE_DB_SERVER_INDEX 0x19c18
50089 #define M_SRINDX    0x3fU
50093 #define A_LE_DB_SRVR_START_INDEX 0x19c18
50095 #define S_T6_SRINDX    0
50096 #define M_T6_SRINDX    0xfffffU
50100 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
50103 #define M_CLIPTINDX    0x3fU
50107 #define A_LE_DB_HPRI_FILT_TABLE_START_INDEX 0x19c1c
50109 #define S_HFTINDX    0
50110 #define M_HFTINDX    0xfffffU
50114 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
50116 #define S_ACTCNTIPV4    0
50117 #define M_ACTCNTIPV4    0xfffffU
50121 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
50123 #define S_ACTCNTIPV6    0
50124 #define M_ACTCNTIPV6    0xfffffU
50128 #define A_LE_DB_HASH_CONFIG 0x19c28
50131 #define M_HASHTIDSIZE    0x3fU
50135 #define S_HASHSIZE    0
50136 #define M_HASHSIZE    0x3fU
50141 #define M_NUMHASHBKT    0x1fU
50146 #define M_HASHTBLSIZE    0x1ffffU
50150 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
50151 #define A_LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES 0x19c2c
50153 #define S_MIN_ATCAM_ENTS    0
50154 #define M_MIN_ATCAM_ENTS    0xfffffU
50158 #define A_LE_DB_HASH_TID_BASE 0x19c30
50159 #define A_LE_DB_HASH_TBL_BASE_ADDR 0x19c30
50162 #define M_HASHTBLADDR    0xfffffffU
50166 #define A_LE_DB_SIZE 0x19c34
50167 #define A_LE_TCAM_SIZE 0x19c34
50169 #define S_TCAM_SIZE    0
50170 #define M_TCAM_SIZE    0x3U
50178 #define A_LE_DB_INT_ENABLE 0x19c38
50181 #define M_MSGSEL    0x1fU
50245 #define S_SERVERHIT    0
50389 #define S_PIPELINEERR    0
50401 #define A_LE_DB_INT_CAUSE 0x19c3c
50402 #define A_LE_DB_INT_TID 0x19c40
50404 #define S_INTTID    0
50405 #define M_INTTID    0xfffffU
50409 #define A_LE_DB_DBG_MATCH_CMD_IDX_MASK 0x19c40
50412 #define M_CMD_CMP_MASK    0x1fU
50416 #define S_TID_CMP_MASK    0
50417 #define M_TID_CMP_MASK    0xfffffU
50421 #define A_LE_DB_INT_PTID 0x19c44
50423 #define S_INTPTID    0
50424 #define M_INTPTID    0xfffffU
50428 #define A_LE_DB_DBG_MATCH_CMD_IDX_DATA 0x19c44
50431 #define M_CMD_CMP    0x1fU
50435 #define S_TID_CMP    0
50436 #define M_TID_CMP    0xfffffU
50440 #define A_LE_DB_INT_INDEX 0x19c48
50442 #define S_INTINDEX    0
50443 #define M_INTINDEX    0xfffffU
50447 #define A_LE_DB_ERR_CMD_TID 0x19c48
50450 #define M_ERR_CID    0xffU
50455 #define M_ERR_PROT    0x3U
50459 #define S_ERR_TID    0
50460 #define M_ERR_TID    0xfffffU
50464 #define A_LE_DB_INT_CMD 0x19c4c
50466 #define S_INTCMD    0
50467 #define M_INTCMD    0xfU
50471 #define A_LE_DB_MASK_IPV4 0x19c50
50472 #define A_LE_T5_DB_MASK_IPV4 0x19c50
50473 #define A_LE_DB_DBG_MATCH_DATA_MASK 0x19c50
50474 #define A_LE_DB_MAX_NUM_HASH_ENTRIES 0x19c70
50476 #define S_MAX_HASH_ENTS    0
50477 #define M_MAX_HASH_ENTS    0xfffffU
50481 #define A_LE_DB_RSP_CODE_0 0x19c74
50484 #define M_SUCCESS    0x1fU
50489 #define M_TCAM_ACTV_SUCC    0x1fU
50494 #define M_HASH_ACTV_SUCC    0x1fU
50499 #define M_TCAM_SRVR_HIT    0x1fU
50504 #define M_SRAM_SRVR_HIT    0x1fU
50508 #define S_TCAM_ACTV_HIT    0
50509 #define M_TCAM_ACTV_HIT    0x1fU
50513 #define A_LE_DB_RSP_CODE_1 0x19c78
50516 #define M_HASH_ACTV_HIT    0x1fU
50521 #define M_T6_MISS    0x1fU
50526 #define M_NORM_FILT_HIT    0x1fU
50531 #define M_HPRI_FILT_HIT    0x1fU
50536 #define M_ACTV_OPEN_ERR    0x1fU
50540 #define S_ACTV_FULL_ERR    0
50541 #define M_ACTV_FULL_ERR    0x1fU
50545 #define A_LE_DB_RSP_CODE_2 0x19c7c
50548 #define M_SRCH_RGN_HIT    0x1fU
50553 #define M_CLIP_FAIL    0x1fU
50558 #define M_LIP_ZERO_ERR    0x1fU
50563 #define M_UNKNOWN_CMD    0x1fU
50568 #define M_CMD_TID_ERR    0x1fU
50572 #define S_INTERNAL_ERR    0
50573 #define M_INTERNAL_ERR    0x1fU
50577 #define A_LE_DB_RSP_CODE_3 0x19c80
50580 #define M_SRAM_SRVR_HIT_ACTF    0x1fU
50585 #define M_TCAM_SRVR_HIT_ACTF    0x1fU
50590 #define M_INVLDRD    0x1fU
50595 #define M_TUPLZERO    0x1fU
50599 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
50600 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
50601 #define A_LE_ACT_CNT_THRSH 0x19c9c
50603 #define S_ACT_CNT_THRSH    0
50604 #define M_ACT_CNT_THRSH    0x1fffffU
50608 #define A_LE_DB_MASK_IPV6 0x19ca0
50609 #define A_LE_DB_DBG_MATCH_DATA 0x19ca0
50610 #define A_LE_CMM_CONFIG 0x19cc0
50611 #define A_LE_CACHE_DBG 0x19cc4
50612 #define A_LE_CACHE_WR_ALL_CNT 0x19cc8
50613 #define A_LE_CACHE_WR_HIT_CNT 0x19ccc
50614 #define A_LE_CACHE_RD_ALL_CNT 0x19cd0
50615 #define A_LE_CACHE_RD_HIT_CNT 0x19cd4
50616 #define A_LE_CACHE_MC_WR_CNT 0x19cd8
50617 #define A_LE_CACHE_MC_RD_CNT 0x19cdc
50618 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
50621 #define M_T4_RSPCNT    0xffffU
50625 #define S_T4_REQCNT    0
50626 #define M_T4_REQCNT    0xffffU
50631 #define M_RSPCNTLE    0xffffU
50635 #define S_REQCNTLE    0
50636 #define M_REQCNTLE    0xffffU
50640 #define A_LE_IND_ADDR 0x19ce8
50642 #define S_T7_1_ADDR    0
50643 #define M_T7_1_ADDR    0xffU
50647 #define A_LE_IND_DATA 0x19cec
50648 #define A_LE_DB_DBGI_CONFIG 0x19cf0
50655 #define M_DBGICMDRANGE    0x7U
50684 #define M_DBGICMDTYPE    0x7U
50700 #define S_DBGICMDMODE    0
50701 #define M_DBGICMDMODE    0x3U
50713 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
50716 #define M_DBGICMD    0xfU
50720 #define S_DBGITINDEX    0
50721 #define M_DBGITINDEX    0xfffffU
50725 #define A_LE_DB_DBGI_REQ_CMD 0x19cf4
50727 #define S_DBGITID    0
50728 #define M_DBGITID    0xfffffU
50732 #define A_LE_PERR_ENABLE 0x19cf8
50738 #define S_TCAM    0
50759 #define M_BKCHKPERIOD    0x3ffU
50776 #define M_T7_BKCHKPERIOD    0xffU
50780 #define A_LE_SPARE 0x19cfc
50781 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
50782 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
50783 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
50786 #define M_DBGIRSPINDEX    0xfffffU
50791 #define M_DBGIRSPMSG    0xfU
50807 #define S_DBGIRSPVALID    0
50812 #define M_DBGIRSPTID    0xfffffU
50820 #define A_LE_DBG_SEL 0x19d98
50821 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
50822 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
50825 #define M_LASTCMDB    0x7ffU
50829 #define S_LASTCMDA    0
50830 #define M_LASTCMDA    0x7ffU
50834 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
50848 #define S_DROPFILTERFIDX    0
50849 #define M_DROPFILTERFIDX    0x1fffU
50853 #define A_LE_DB_PTID_SVRBASE 0x19df0
50856 #define M_SVRBASE_ADDR    0x3ffffU
50860 #define A_LE_DB_TCAM_TID_BASE 0x19df0
50862 #define S_TCAM_TID_BASE    0
50863 #define M_TCAM_TID_BASE    0xfffffU
50867 #define A_LE_DB_FTID_FLTRBASE 0x19df4
50870 #define M_FLTRBASE_ADDR    0x3ffffU
50874 #define A_LE_DB_CLCAM_TID_BASE 0x19df4
50876 #define S_CLCAM_TID_BASE    0
50877 #define M_CLCAM_TID_BASE    0xfffffU
50881 #define A_LE_DB_TID_HASHBASE 0x19df8
50884 #define M_HASHBASE_ADDR    0xfffffU
50888 #define A_T6_LE_DB_HASH_TID_BASE 0x19df8
50890 #define S_HASH_TID_BASE    0
50891 #define M_HASH_TID_BASE    0xfffffU
50895 #define A_T7_LE_DB_HASH_TID_BASE 0x19df8
50896 #define A_LE_PERR_INJECT 0x19dfc
50899 #define M_LEMEMSEL    0x7U
50903 #define A_LE_DB_SSRAM_TID_BASE 0x19dfc
50905 #define S_SSRAM_TID_BASE    0
50906 #define M_SSRAM_TID_BASE    0xfffffU
50910 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
50911 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
50912 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
50913 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
50914 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
50915 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
50916 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
50917 #define A_T6_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
50918 #define A_T7_LE_HASH_MASK_GEN_IPV6T5 0x19ec4
50919 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
50920 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
50921 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV4 0x19ee4
50922 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
50923 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV4 0x19ef0
50924 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
50925 #define A_LE_DB_PSV_FILTER_MASK_TUP_IPV6 0x19f04
50926 #define A_LE_DEBUG_LA_CONFIG 0x19f20
50927 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
50928 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
50929 #define A_LE_DB_PSV_FILTER_MASK_FLT_IPV6 0x19f28
50930 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
50931 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
50932 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
50933 #define A_LE_SRVR_SRAM_INIT 0x19f34
50936 #define M_SRVRSRAMBASE    0xfffffU
50944 #define S_SRVRINIT    0
50948 #define A_LE_DB_SRVR_SRAM_CONFIG 0x19f34
50962 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
50963 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
50970 #define M_VFINDEX    0x7fU
50975 #define M_SRCHHADDR    0x7fU
50979 #define S_SRCHLADDR    0
50980 #define M_SRCHLADDR    0x7fU
50984 #define A_LE_DB_SRVR_VF_SRCH_TABLE_CTRL 0x19f38
50998 #define S_T6_VFINDEX    0
50999 #define M_T6_VFINDEX    0xffU
51003 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
51004 #define A_LE_DB_SRVR_VF_SRCH_TABLE_DATA 0x19f3c
51007 #define M_T6_SRCHHADDR    0xfffU
51011 #define S_T6_SRCHLADDR    0
51012 #define M_T6_SRCHLADDR    0xfffU
51016 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
51017 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
51018 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
51019 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
51020 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
51021 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
51022 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
51023 #define A_LE_TCAM_BIST_CTRL 0x19fb0
51024 #define A_LE_TCAM_BIST_CB_PASS 0x19fb4
51025 #define A_LE_TCAM_BIST_CB_BUSY 0x19fbc
51026 #define A_LE_HASH_COLLISION 0x19fc4
51027 #define A_LE_GLOBAL_COLLISION 0x19fc8
51028 #define A_LE_FULL_CNT_COLLISION 0x19fcc
51029 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
51030 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
51031 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
51032 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
51033 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
51034 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
51035 #define A_LE_TCAM_NEG_CTRL0 0x0
51036 #define A_LE_TCAM_NEG_CTRL1 0x1
51037 #define A_LE_TCAM_NEG_CTRL2 0x2
51038 #define A_LE_TCAM_NEG_CTRL3 0x3
51039 #define A_LE_TCAM_NEG_CTRL4 0x4
51040 #define A_LE_TCAM_NEG_CTRL5 0x5
51041 #define A_LE_TCAM_NEG_CTRL6 0x6
51042 #define A_LE_TCAM_NEG_CTRL7 0x7
51043 #define A_LE_TCAM_NEG_CTRL8 0x8
51044 #define A_LE_TCAM_NEG_CTRL9 0x9
51045 #define A_LE_TCAM_NEG_CTRL10 0xa
51046 #define A_LE_TCAM_NEG_CTRL11 0xb
51047 #define A_LE_TCAM_NEG_CTRL12 0xc
51048 #define A_LE_TCAM_NEG_CTRL13 0xd
51049 #define A_LE_TCAM_NEG_CTRL14 0xe
51050 #define A_LE_TCAM_NEG_CTRL15 0xf
51051 #define A_LE_TCAM_NEG_CTRL16 0x10
51052 #define A_LE_TCAM_NEG_CTRL17 0x11
51053 #define A_LE_TCAM_NEG_CTRL18 0x12
51054 #define A_LE_TCAM_NEG_CTRL19 0x13
51055 #define A_LE_TCAM_NEG_CTRL20 0x14
51056 #define A_LE_TCAM_NEG_CTRL21 0x15
51057 #define A_LE_TCAM_NEG_CTRL22 0x16
51058 #define A_LE_TCAM_NEG_CTRL23 0x17
51059 #define A_LE_TCAM_NEG_CTRL24 0x18
51060 #define A_LE_TCAM_NEG_CTRL25 0x19
51061 #define A_LE_TCAM_NEG_CTRL26 0x1a
51062 #define A_LE_TCAM_NEG_CTRL27 0x1b
51063 #define A_LE_TCAM_NEG_CTRL28 0x1c
51064 #define A_LE_TCAM_NEG_CTRL29 0x1d
51065 #define A_LE_TCAM_NEG_CTRL30 0x1e
51066 #define A_LE_TCAM_NEG_CTRL31 0x1f
51069 #define NCSI_BASE_ADDR 0x1a000
51071 #define A_NCSI_PORT_CFGREG 0x1a000
51074 #define M_WIREEN    0xfU
51079 #define M_STRP_CRC    0xfU
51104 #define M_MAX_PKT_SIZE    0x3fffU
51116 #define S_XGMAC0_EN    0
51120 #define A_NCSI_RST_CTRL 0x1a004
51130 #define S_MAC_TX_RST    0
51134 #define A_NCSI_CH0_SADDR_LOW 0x1a010
51135 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
51141 #define S_CH0_SADDR_HIGH    0
51142 #define M_CH0_SADDR_HIGH    0xffffU
51146 #define A_NCSI_CH1_SADDR_LOW 0x1a018
51147 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
51153 #define S_CH1_SADDR_HIGH    0
51154 #define M_CH1_SADDR_HIGH    0xffffU
51158 #define A_NCSI_CH2_SADDR_LOW 0x1a020
51159 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
51165 #define S_CH2_SADDR_HIGH    0
51166 #define M_CH2_SADDR_HIGH    0xffffU
51170 #define A_NCSI_CH3_SADDR_LOW 0x1a028
51171 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
51177 #define S_CH3_SADDR_HIGH    0
51178 #define M_CH3_SADDR_HIGH    0xffffU
51182 #define A_NCSI_WORK_REQHDR_0 0x1a030
51183 #define A_NCSI_WORK_REQHDR_1 0x1a034
51184 #define A_NCSI_WORK_REQHDR_2 0x1a038
51185 #define A_NCSI_WORK_REQHDR_3 0x1a03c
51186 #define A_NCSI_MPS_HDR_LO 0x1a040
51187 #define A_NCSI_MPS_HDR_HI 0x1a044
51188 #define A_NCSI_CTL 0x1a048
51202 #define S_FWD_BMC    0
51206 #define A_NCSI_NCSI_ETYPE 0x1a04c
51208 #define S_NCSI_ETHERTYPE    0
51209 #define M_NCSI_ETHERTYPE    0xffffU
51213 #define A_NCSI_RX_FIFO_CNT 0x1a050
51215 #define S_NCSI_RXFIFO_CNT    0
51216 #define M_NCSI_RXFIFO_CNT    0x7ffU
51220 #define A_NCSI_RX_ERR_CNT 0x1a054
51221 #define A_NCSI_RX_OF_CNT 0x1a058
51222 #define A_NCSI_RX_MS_CNT 0x1a05c
51223 #define A_NCSI_RX_IE_CNT 0x1a060
51224 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
51227 #define M_MPS2CIM_CNT    0x1ffU
51231 #define S_MPS2BMC_CNT    0
51232 #define M_MPS2BMC_CNT    0x1ffU
51236 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
51239 #define M_CIM2MPS_CNT    0x1ffU
51243 #define S_CIM2BMC_CNT    0
51244 #define M_CIM2BMC_CNT    0x1ffU
51248 #define A_NCSI_TX_FIFO_CNT 0x1a06c
51250 #define S_TX_FIFO_CNT    0
51251 #define M_TX_FIFO_CNT    0x3ffU
51255 #define A_NCSI_SE_CNT_CTL 0x1a0b0
51257 #define S_SE_CNT_CLR    0
51258 #define M_SE_CNT_CLR    0xfU
51262 #define A_NCSI_SE_CNT_MPS 0x1a0b4
51265 #define M_NC2MPS_SOP_CNT    0xffU
51270 #define M_NC2MPS_EOP_CNT    0x3fU
51275 #define M_MPS2NC_SOP_CNT    0xffU
51279 #define S_MPS2NC_EOP_CNT    0
51280 #define M_MPS2NC_EOP_CNT    0xffU
51284 #define A_NCSI_SE_CNT_CIM 0x1a0b8
51287 #define M_NC2CIM_SOP_CNT    0xffU
51292 #define M_NC2CIM_EOP_CNT    0x3fU
51297 #define M_CIM2NC_SOP_CNT    0xffU
51301 #define S_CIM2NC_EOP_CNT    0
51302 #define M_CIM2NC_EOP_CNT    0xffU
51306 #define A_NCSI_BUS_DEBUG 0x1a0bc
51309 #define M_SOP_CNT_ERR    0xfU
51314 #define M_BUS_STATE_MPS_OUT    0x3U
51319 #define M_BUS_STATE_MPS_IN    0x3U
51324 #define M_BUS_STATE_CIM_OUT    0x3U
51328 #define S_BUS_STATE_CIM_IN    0
51329 #define M_BUS_STATE_CIM_IN    0x3U
51333 #define A_NCSI_LA_RDPTR 0x1a0c0
51334 #define A_NCSI_LA_RDDATA 0x1a0c4
51335 #define A_NCSI_LA_WRPTR 0x1a0c8
51336 #define A_NCSI_LA_RESERVED 0x1a0cc
51337 #define A_NCSI_LA_CTL 0x1a0d0
51338 #define A_NCSI_INT_ENABLE 0x1a0d4
51372 #define S_RXFIFO_PRTY_ERR    0
51380 #define A_NCSI_INT_CAUSE 0x1a0d8
51381 #define A_NCSI_STATUS 0x1a0dc
51387 #define S_ARB_STATUS    0
51391 #define A_NCSI_PAUSE_CTRL 0x1a0e0
51393 #define S_FORCEPAUSE    0
51397 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
51398 #define A_NCSI_PAUSE_WM 0x1a0ec
51401 #define M_PAUSEHWM    0x7ffU
51405 #define S_PAUSELWM    0
51406 #define M_PAUSELWM    0x7ffU
51410 #define A_NCSI_DEBUG 0x1a0f0
51412 #define S_DEBUGSEL    0
51413 #define M_DEBUGSEL    0x3fU
51425 #define S_PKG_ID    0
51426 #define M_PKG_ID    0x7U
51430 #define A_NCSI_PERR_INJECT 0x1a0f4
51436 #define A_NCSI_PERR_ENABLE 0x1a0f8
51437 #define A_NCSI_MODE_SEL 0x1a0fc
51439 #define S_XGMAC_MODE    0
51443 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
51493 #define S_LOOPPHY    0
51497 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
51528 #define M_RXBUFOFFSET    0x3U
51541 #define M_PCLKDIV    0x3U
51581 #define S_SPEED    0
51585 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
51595 #define S_LINKSTATUS    0
51599 #define A_NCSI_MACB_TX_STATUS 0x1a114
51625 #define S_USEDBITREAD    0
51629 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
51632 #define M_RXBUFQPTR    0x3fffffffU
51636 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
51639 #define M_TXBUFQPTR    0x3fffffffU
51643 #define A_NCSI_MACB_RX_STATUS 0x1a120
51653 #define S_NORXBUF    0
51657 #define A_NCSI_MACB_INT_STATUS 0x1a124
51707 #define S_MGMTFRAMESENT    0
51711 #define A_NCSI_MACB_INT_EN 0x1a128
51712 #define A_NCSI_MACB_INT_DIS 0x1a12c
51713 #define A_NCSI_MACB_INT_MASK 0x1a130
51714 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
51716 #define S_PAUSETIME    0
51717 #define M_PAUSETIME    0xffffU
51721 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
51723 #define S_PAUSEFRRCVD    0
51724 #define M_PAUSEFRRCVD    0xffffU
51728 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
51730 #define S_TXFRAMESOK    0
51731 #define M_TXFRAMESOK    0xffffffU
51735 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
51737 #define S_SINGLECOLTXFRAMES    0
51738 #define M_SINGLECOLTXFRAMES    0xffffU
51742 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
51744 #define S_MULCOLTXFRAMES    0
51745 #define M_MULCOLTXFRAMES    0xffffU
51749 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
51751 #define S_RXFRAMESOK    0
51752 #define M_RXFRAMESOK    0xffffffU
51756 #define A_NCSI_MACB_FCS_ERR 0x1a150
51758 #define S_RXFCSERR    0
51759 #define M_RXFCSERR    0xffU
51763 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
51765 #define S_RXALIGNERR    0
51766 #define M_RXALIGNERR    0xffU
51770 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
51772 #define S_TXDEFERREDFRAMES    0
51773 #define M_TXDEFERREDFRAMES    0xffffU
51777 #define A_NCSI_MACB_LATE_COL 0x1a15c
51779 #define S_LATECOLLISIONS    0
51780 #define M_LATECOLLISIONS    0xffffU
51784 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
51786 #define S_EXCESSIVECOLLISIONS    0
51787 #define M_EXCESSIVECOLLISIONS    0xffU
51791 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
51793 #define S_TXUNDERRUNERR    0
51794 #define M_TXUNDERRUNERR    0xffU
51798 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
51800 #define S_CARRIERSENSEERRS    0
51801 #define M_CARRIERSENSEERRS    0xffU
51805 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
51807 #define S_RXRESOURCEERR    0
51808 #define M_RXRESOURCEERR    0xffffU
51812 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
51814 #define S_RXOVERRUNERRCNT    0
51815 #define M_RXOVERRUNERRCNT    0xffU
51819 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
51821 #define S_RXSYMBOLERR    0
51822 #define M_RXSYMBOLERR    0xffU
51826 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
51828 #define S_RXOVERSIZEERR    0
51829 #define M_RXOVERSIZEERR    0xffU
51833 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
51835 #define S_RXJABBERERR    0
51836 #define M_RXJABBERERR    0xffU
51840 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
51842 #define S_RXUNDERSIZEFR    0
51843 #define M_RXUNDERSIZEFR    0xffU
51847 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
51849 #define S_SQETESTERR    0
51850 #define M_SQETESTERR    0xffU
51854 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
51856 #define S_LENGTHERR    0
51857 #define M_LENGTHERR    0xffU
51861 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
51863 #define S_TXPAUSEFRAMES    0
51864 #define M_TXPAUSEFRAMES    0xffffU
51868 #define A_NCSI_MACB_HASH_LOW 0x1a190
51869 #define A_NCSI_MACB_HASH_HIGH 0x1a194
51870 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
51871 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
51873 #define S_MATCHHIGH    0
51874 #define M_MATCHHIGH    0xffffU
51878 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
51879 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
51880 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
51881 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
51882 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
51883 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
51884 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
51886 #define S_TYPEID    0
51887 #define M_TYPEID    0xffffU
51891 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
51893 #define S_TXPAUSEQUANTUM    0
51894 #define M_TXPAUSEQUANTUM    0xffffU
51898 #define A_NCSI_MACB_USER_IO 0x1a1c0
51901 #define M_USERPROGINPUT    0xffffU
51905 #define S_USERPROGOUTPUT    0
51906 #define M_USERPROGOUTPUT    0xffffU
51910 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
51928 #define S_ARPIPADDR    0
51929 #define M_ARPIPADDR    0xffffU
51933 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
51936 #define M_PARTREF    0xffffU
51940 #define S_DESREV    0
51941 #define M_DESREV    0xffffU
51945 #define A_NCSI_TX_CTRL 0x1a200
51947 #define S_T7_TXEN    0
51951 #define A_NCSI_TX_CFG 0x1a204
51952 #define A_NCSI_TX_PAUSE_QUANTA 0x1a208
51953 #define A_NCSI_RX_CTRL 0x1a20c
51954 #define A_NCSI_RX_CFG 0x1a210
51955 #define A_NCSI_RX_HASH_LOW 0x1a214
51956 #define A_NCSI_RX_HASH_HIGH 0x1a218
51957 #define A_NCSI_RX_EXACT_MATCH_LOW_1 0x1a21c
51958 #define A_NCSI_RX_EXACT_MATCH_HIGH_1 0x1a220
51959 #define A_NCSI_RX_EXACT_MATCH_LOW_2 0x1a224
51960 #define A_NCSI_RX_EXACT_MATCH_HIGH_2 0x1a228
51961 #define A_NCSI_RX_EXACT_MATCH_LOW_3 0x1a22c
51962 #define A_NCSI_RX_EXACT_MATCH_HIGH_3 0x1a230
51963 #define A_NCSI_RX_EXACT_MATCH_LOW_4 0x1a234
51964 #define A_NCSI_RX_EXACT_MATCH_HIGH_4 0x1a238
51965 #define A_NCSI_RX_EXACT_MATCH_LOW_5 0x1a23c
51966 #define A_NCSI_RX_EXACT_MATCH_HIGH_5 0x1a240
51967 #define A_NCSI_RX_EXACT_MATCH_LOW_6 0x1a244
51968 #define A_NCSI_RX_EXACT_MATCH_HIGH_6 0x1a248
51969 #define A_NCSI_RX_EXACT_MATCH_LOW_7 0x1a24c
51970 #define A_NCSI_RX_EXACT_MATCH_HIGH_7 0x1a250
51971 #define A_NCSI_RX_EXACT_MATCH_LOW_8 0x1a254
51972 #define A_NCSI_RX_EXACT_MATCH_HIGH_8 0x1a258
51973 #define A_NCSI_RX_TYPE_MATCH_1 0x1a25c
51974 #define A_NCSI_RX_TYPE_MATCH_2 0x1a260
51975 #define A_NCSI_RX_TYPE_MATCH_3 0x1a264
51976 #define A_NCSI_RX_TYPE_MATCH_4 0x1a268
51977 #define A_NCSI_INT_STATUS 0x1a26c
51978 #define A_NCSI_XGM_INT_MASK 0x1a270
51979 #define A_NCSI_XGM_INT_ENABLE 0x1a274
51980 #define A_NCSI_XGM_INT_DISABLE 0x1a278
51981 #define A_NCSI_TX_PAUSE_TIMER 0x1a27c
51982 #define A_NCSI_STAT_CTRL 0x1a280
51983 #define A_NCSI_RXFIFO_CFG 0x1a284
51994 #define M_RXFIFOPAUSEHWM    0xfffU
51999 #define M_RXFIFOPAUSELWM    0xfffU
52019 #define S_DISERRFRAMES    0
52023 #define A_NCSI_TXFIFO_CFG 0x1a288
52042 #define M_TXIPG    0xffU
52047 #define M_TXFIFOTHRESH    0x1ffU
52063 #define S_DISPREAMBLE    0
52067 #define A_NCSI_SLOW_TIMER 0x1a28c
52073 #define S_PAUSESLOWTIMER    0
52074 #define M_PAUSESLOWTIMER    0xfffffU
52078 #define A_NCSI_PAUSE_TIMER 0x1a290
52080 #define S_PAUSETIMER    0
52081 #define M_PAUSETIMER    0xfffffU
52085 #define A_NCSI_XAUI_PCS_TEST 0x1a294
52088 #define M_TESTPATTERN    0x3U
52092 #define S_ENTEST    0
52096 #define A_NCSI_RGMII_CTRL 0x1a298
52099 #define M_PHALIGNFIFOTHRESH    0x3U
52103 #define S_TXCLK90SHIFT    0
52107 #define A_NCSI_RGMII_IMP 0x1a29c
52122 #define M_RGMIIIMPPD    0x7U
52126 #define S_RGMIIIMPPU    0
52127 #define M_RGMIIIMPPU    0x7U
52131 #define A_NCSI_RX_MAX_PKT_SIZE 0x1a2a8
52134 #define M_RXMAXFRAMERSIZE    0x3fffU
52150 #define S_RXMAXPKTSIZE    0
52151 #define M_RXMAXPKTSIZE    0x3fffU
52155 #define A_NCSI_RESET_CTRL 0x1a2ac
52173 #define S_MAC_RESET_    0
52177 #define A_NCSI_XAUI1G_CTRL 0x1a2b0
52179 #define S_XAUI1GLINKID    0
52180 #define M_XAUI1GLINKID    0x3U
52184 #define A_NCSI_SERDES_LANE_CTRL 0x1a2b4
52191 #define M_TXPOLARITY    0xfU
52195 #define S_RXPOLARITY    0
52196 #define M_RXPOLARITY    0xfU
52200 #define A_NCSI_PORT_CFG 0x1a2b8
52211 #define M_NCSI_PORTSPEED    0x3U
52215 #define S_NCSI_ENRGMII    0
52219 #define A_NCSI_EPIO_DATA0 0x1a2c0
52220 #define A_NCSI_EPIO_DATA1 0x1a2c4
52221 #define A_NCSI_EPIO_DATA2 0x1a2c8
52222 #define A_NCSI_EPIO_DATA3 0x1a2cc
52223 #define A_NCSI_EPIO_OP 0x1a2d0
52233 #define S_PIO_ADDRESS    0
52234 #define M_PIO_ADDRESS    0xffU
52238 #define A_NCSI_XGMAC0_INT_ENABLE 0x1a2d4
52261 #define M_T7_TXFIFO_PRTY_ERR    0x7U
52266 #define M_T7_RXFIFO_PRTY_ERR    0x7U
52279 #define M_SERDESBISTERR    0xfU
52284 #define M_SERDESLOWSIGCHANGE    0xfU
52300 #define S_T7_XGM_INT    0
52304 #define A_NCSI_XGMAC0_INT_CAUSE 0x1a2d8
52305 #define A_NCSI_XAUI_ACT_CTRL 0x1a2dc
52306 #define A_NCSI_SERDES_CTRL0 0x1a2e0
52365 #define M_PW23    0x3U
52370 #define M_PW01    0x3U
52375 #define M_DEQ    0xfU
52380 #define M_DTX    0xfU
52388 #define S_HIDRV    0
52392 #define A_NCSI_SERDES_CTRL1 0x1a2e4
52395 #define M_FMOFFSET3    0x1fU
52404 #define M_FMOFFSET2    0x1fU
52413 #define M_FMOFFSET1    0x1fU
52422 #define M_FMOFFSET0    0x1fU
52426 #define S_FMOFFSETEN0    0
52430 #define A_NCSI_SERDES_CTRL2 0x1a2e8
52476 #define S_RXSLAVE0    0
52480 #define A_NCSI_SERDES_CTRL3 0x1a2ec
52495 #define M_EXTBISTPAT3    0x7U
52520 #define M_EXTBISTPAT2    0x7U
52545 #define M_EXTBISTPAT1    0x7U
52570 #define M_EXTBISTPAT0    0x7U
52578 #define S_EXTPARLPBK0    0
52582 #define A_NCSI_SERDES_STAT0 0x1a2f0
52585 #define M_EXTBISTCHKERRCNT0    0xffffffU
52601 #define S_LOWSIG0    0
52605 #define A_NCSI_SERDES_STAT1 0x1a2f4
52608 #define M_EXTBISTCHKERRCNT1    0xffffffU
52624 #define S_LOWSIG1    0
52628 #define A_NCSI_SERDES_STAT2 0x1a2f8
52631 #define M_EXTBISTCHKERRCNT2    0xffffffU
52647 #define S_LOWSIG2    0
52651 #define A_NCSI_SERDES_STAT3 0x1a2fc
52654 #define M_EXTBISTCHKERRCNT3    0xffffffU
52670 #define S_LOWSIG3    0
52674 #define A_NCSI_STAT_TX_BYTE_LOW 0x1a300
52675 #define A_NCSI_STAT_TX_BYTE_HIGH 0x1a304
52676 #define A_NCSI_STAT_TX_FRAME_LOW 0x1a308
52677 #define A_NCSI_STAT_TX_FRAME_HIGH 0x1a30c
52678 #define A_NCSI_STAT_TX_BCAST 0x1a310
52679 #define A_NCSI_STAT_TX_MCAST 0x1a314
52680 #define A_NCSI_STAT_TX_PAUSE 0x1a318
52681 #define A_NCSI_STAT_TX_64B_FRAMES 0x1a31c
52682 #define A_NCSI_STAT_TX_65_127B_FRAMES 0x1a320
52683 #define A_NCSI_STAT_TX_128_255B_FRAMES 0x1a324
52684 #define A_NCSI_STAT_TX_256_511B_FRAMES 0x1a328
52685 #define A_NCSI_STAT_TX_512_1023B_FRAMES 0x1a32c
52686 #define A_NCSI_STAT_TX_1024_1518B_FRAMES 0x1a330
52687 #define A_NCSI_STAT_TX_1519_MAXB_FRAMES 0x1a334
52688 #define A_NCSI_STAT_TX_ERR_FRAMES 0x1a338
52689 #define A_NCSI_STAT_RX_BYTES_LOW 0x1a33c
52690 #define A_NCSI_STAT_RX_BYTES_HIGH 0x1a340
52691 #define A_NCSI_STAT_RX_FRAMES_LOW 0x1a344
52692 #define A_NCSI_STAT_RX_FRAMES_HIGH 0x1a348
52693 #define A_NCSI_STAT_RX_BCAST_FRAMES 0x1a34c
52694 #define A_NCSI_STAT_RX_MCAST_FRAMES 0x1a350
52695 #define A_NCSI_STAT_RX_PAUSE_FRAMES 0x1a354
52696 #define A_NCSI_STAT_RX_64B_FRAMES 0x1a358
52697 #define A_NCSI_STAT_RX_65_127B_FRAMES 0x1a35c
52698 #define A_NCSI_STAT_RX_128_255B_FRAMES 0x1a360
52699 #define A_NCSI_STAT_RX_256_511B_FRAMES 0x1a364
52700 #define A_NCSI_STAT_RX_512_1023B_FRAMES 0x1a368
52701 #define A_NCSI_STAT_RX_1024_1518B_FRAMES 0x1a36c
52702 #define A_NCSI_STAT_RX_1519_MAXB_FRAMES 0x1a370
52703 #define A_NCSI_STAT_RX_SHORT_FRAMES 0x1a374
52704 #define A_NCSI_STAT_RX_OVERSIZE_FRAMES 0x1a378
52705 #define A_NCSI_STAT_RX_JABBER_FRAMES 0x1a37c
52706 #define A_NCSI_STAT_RX_CRC_ERR_FRAMES 0x1a380
52707 #define A_NCSI_STAT_RX_LENGTH_ERR_FRAMES 0x1a384
52708 #define A_NCSI_STAT_RX_SYM_CODE_ERR_FRAMES 0x1a388
52709 #define A_NCSI_XAUI_PCS_ERR 0x1a398
52712 #define M_PCS_SYNCSTATUS    0xfU
52717 #define M_PCS_CTCFIFOERR    0xfU
52721 #define S_PCS_NOTALIGNED    0
52725 #define A_NCSI_RGMII_STATUS 0x1a39c
52732 #define M_GMIISPEED    0x3U
52736 #define S_GMIILINKSTATUS    0
52740 #define A_NCSI_WOL_STATUS 0x1a3a0
52746 #define A_NCSI_RX_MAX_PKT_SIZE_ERR_CNT 0x1a3a4
52747 #define A_NCSI_TX_SPI4_SOP_EOP_CNT 0x1a3a8
52750 #define M_TXSPI4SOPCNT    0xffffU
52754 #define S_TXSPI4EOPCNT    0
52755 #define M_TXSPI4EOPCNT    0xffffU
52759 #define A_NCSI_RX_SPI4_SOP_EOP_CNT 0x1a3ac
52762 #define M_RXSPI4SOPCNT    0xffffU
52766 #define S_RXSPI4EOPCNT    0
52767 #define M_RXSPI4EOPCNT    0xffffU
52772 #define XGMAC_BASE_ADDR 0x0
52774 #define A_XGMAC_PORT_CFG 0x1000
52777 #define M_XGMII_CLK_SEL    0x7U
52838 #define M_XGM_RX_SEL    0x3U
52843 #define M_PCS_TX_SEL    0x3U
52855 #define S_PORT_SEL    0
52859 #define A_XGMAC_PORT_RESET_CTRL 0x1004
52901 #define S_HSS_RESET    0
52905 #define A_XGMAC_PORT_LED_CFG 0x1008
52908 #define M_LED1_CFG    0x7U
52917 #define M_LED0_CFG    0x7U
52921 #define S_LED0_POLARITY_INV    0
52925 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
52927 #define S_LED_COUNT_HI    0
52928 #define M_LED_COUNT_HI    0x1ffffffU
52932 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
52934 #define S_LED_COUNT_LO    0
52935 #define M_LED_COUNT_LO    0x1ffffffU
52939 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
52941 #define S_TESTCLK_SEL    0
52942 #define M_TESTCLK_SEL    0xfU
52946 #define A_XGMAC_PORT_CFG2 0x1018
52949 #define M_RX_POLARITY_INV    0xfU
52954 #define M_TX_POLARITY_INV    0xfU
52959 #define M_INSTANCENUM    0x3U
52984 #define M_TX_IPG    0x1fffU
52992 #define S_AEC_PMA_RX_READY    0
52996 #define A_XGMAC_PORT_PKT_COUNT 0x101c
52999 #define M_TX_SOP_COUNT    0xffU
53004 #define M_TX_EOP_COUNT    0xffU
53009 #define M_RX_SOP_COUNT    0xffU
53013 #define S_RX_EOP_COUNT    0
53014 #define M_RX_EOP_COUNT    0xffU
53018 #define A_XGMAC_PORT_PERR_INJECT 0x1020
53024 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
53025 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
53027 #define S_MAC_WOL_DA    0
53028 #define M_MAC_WOL_DA    0xffffU
53032 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
53033 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
53036 #define M_TXSOP    0xffU
53041 #define M_TXEOP    0xffU
53046 #define M_RXSOP    0xffU
53050 #define S_T4_RXEOP    0
53051 #define M_T4_RXEOP    0xffU
53055 #define A_XGMAC_PORT_LINK_STATUS 0x1034
53069 #define S_LINKDN    0
53073 #define A_XGMAC_PORT_CHECKIN 0x1038
53079 #define S_CHECKIN    0
53083 #define A_XGMAC_PORT_FAULT_TEST 0x103c
53089 #define S_FLTCTRL    0
53093 #define A_XGMAC_PORT_SPARE 0x1040
53094 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
53096 #define S_SIGNALDETECT    0
53097 #define M_SIGNALDETECT    0xfU
53101 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
53102 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
53104 #define S_CTRL    0
53105 #define M_CTRL    0xfU
53109 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
53116 #define M_HWM    0x1fffU
53120 #define S_LWM    0
53121 #define M_LWM    0x1fffU
53125 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
53126 #define A_XGMAC_PORT_LA_TX_0 0x1058
53127 #define A_XGMAC_PORT_LA_RX_0 0x105c
53128 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
53150 #define S_LASTOP    0
53154 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
53155 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
53156 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
53157 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
53158 #define A_XGMAC_PORT_EPIO_OP 0x10d0
53164 #define S_ADDRESS    0
53165 #define M_ADDRESS    0xffU
53169 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
53187 #define S_MATCHEDFILTER    0
53188 #define M_MATCHEDFILTER    0x7U
53192 #define A_XGMAC_PORT_INT_EN 0x10d8
53302 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
53303 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
53370 #define M_HSSDIVSEL    0x3U
53395 #define M_HSSRSTCONFIG    0x7U
53399 #define S_HSSPRBSEN    0
53403 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
53481 #define S_TXAPRBSEN    0
53485 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
53579 #define S_RXAPHSUPIN    0
53583 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
53637 #define S_HSSPRTREADY    0
53641 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
53651 #define S_XGM_TXEN    0
53655 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
53658 #define M_CRCCAL    0x3U
53675 #define M_CFGCLKSPEED    0x7U
53683 #define S_TXPAUSEEN    0
53687 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
53689 #define S_TXPAUSEQUANTA    0
53690 #define M_TXPAUSEQUANTA    0xffffU
53694 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
53695 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
53698 #define M_RXCRCCAL    0x3U
53762 #define S_COPYALLFRAMES    0
53766 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
53767 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
53768 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
53769 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
53771 #define S_ADDRESS_HIGH    0
53772 #define M_ADDRESS_HIGH    0xffffU
53776 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
53777 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
53778 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
53779 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
53780 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
53781 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
53782 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
53783 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
53784 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
53785 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
53786 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
53787 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
53788 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
53789 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
53790 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
53796 #define S_TYPE    0
53797 #define M_TYPE    0xffffU
53801 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
53802 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
53803 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
53804 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
53846 #define S_FRAMERCVD    0
53850 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
53851 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
53852 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
53853 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
53855 #define S_CURPAUSETIMER    0
53856 #define M_CURPAUSETIMER    0xffffU
53860 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
53878 #define S_ENTESTMODEWR    0
53882 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
53885 #define M_FRAMETYPE    0x3U
53890 #define M_OPERATION    0x3U
53895 #define M_PORTADDR    0x1fU
53900 #define M_DEVADDR    0x1fU
53905 #define M_RESRV    0x3U
53909 #define S_DATA    0
53910 #define M_DATA    0xffffU
53914 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
53917 #define M_MODULEID    0xffffU
53921 #define S_MODULEREV    0
53922 #define M_MODULEREV    0xffffU
53926 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
53927 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
53929 #define S_TXBYTES_HIGH    0
53930 #define M_TXBYTES_HIGH    0x1fffU
53934 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
53935 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
53937 #define S_TXFRAMES_HIGH    0
53938 #define M_TXFRAMES_HIGH    0xfU
53942 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
53943 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
53944 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
53945 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
53946 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
53947 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
53948 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
53949 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
53950 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
53951 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
53952 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
53953 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
53954 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
53956 #define S_RXBYTES_HIGH    0
53957 #define M_RXBYTES_HIGH    0x1fffU
53961 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
53962 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
53964 #define S_RXFRAMES_HIGH    0
53965 #define M_RXFRAMES_HIGH    0xfU
53969 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
53970 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
53971 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
53973 #define S_RXPAUSEFRAMES    0
53974 #define M_RXPAUSEFRAMES    0xffffU
53978 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
53979 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
53980 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
53981 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
53982 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
53983 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
53984 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
53985 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
53987 #define S_RXSHORTFRAMES    0
53988 #define M_RXSHORTFRAMES    0xffffU
53992 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
53994 #define S_RXOVERSIZEFRAMES    0
53995 #define M_RXOVERSIZEFRAMES    0xffffU
53999 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
54001 #define S_RXJABBERFRAMES    0
54002 #define M_RXJABBERFRAMES    0xffffU
54006 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
54008 #define S_RXCRCERRFRAMES    0
54009 #define M_RXCRCERRFRAMES    0xffffU
54013 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
54015 #define S_RXLENGTHERRFRAMES    0
54016 #define M_RXLENGTHERRFRAMES    0xffffU
54020 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
54022 #define S_RXSYMCODEERRFRAMES    0
54023 #define M_RXSYMCODEERRFRAMES    0xffffU
54027 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
54030 #define M_POLARITY_INV_RX    0xfU
54035 #define M_POLARITY_INV_TX    0xfU
54040 #define M_TEST_SEL    0x3U
54044 #define S_TEST_EN    0
54048 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
54051 #define M_DECODE_ERROR    0xffU
54087 #define S_LANE0_SYNC_STATUS    0
54091 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
54110 #define M_TESTSEL    0x3U
54118 #define S_XGMIILOOPEN    0
54122 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
54140 #define S_TX_TST_EN    0
54144 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
54145 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
54147 #define S_SEEDA_UPPER    0
54148 #define M_SEEDA_UPPER    0x3ffffffU
54152 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
54153 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
54155 #define S_SEEDB_UPPER    0
54156 #define M_SEEDB_UPPER    0x3ffffffU
54160 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
54190 #define S_RX_TST_EN    0
54194 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
54197 #define M_ERR_BLK_CNT    0xffU
54202 #define M_BER_COUNT    0x3fU
54214 #define S_TX_FAULT    0
54218 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
54220 #define S_TPT_ERR_CNT    0
54221 #define M_TPT_ERR_CNT    0xffffU
54225 #define A_XGMAC_PORT_AN_CONTROL 0x1600
54239 #define A_XGMAC_PORT_AN_STATUS 0x1604
54269 #define S_PARTNER_AN_ABILITY    0
54273 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
54296 #define M_TRANSMITTED_NONCE    0x1fU
54321 #define M_ECHOED_NONCE    0x1fU
54325 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
54327 #define S_SELECTOR_FIELD    0
54328 #define M_SELECTOR_FIELD    0x1fU
54332 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
54335 #define M_NP_INFO    0xffffU
54355 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
54357 #define S_NP_INFO_HI    0
54358 #define M_NP_INFO_HI    0xffffU
54362 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
54363 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
54364 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
54390 #define S_BP_AN_ABILITY    0
54394 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
54400 #define S_LFSR_INIT    0
54401 #define M_LFSR_INIT    0x7fffU
54405 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
54419 #define S_PCS_AN_COMPLETE    0
54423 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
54425 #define S_GENERIC_TIMEOUT    0
54426 #define M_GENERIC_TIMEOUT    0x7fffffU
54430 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
54432 #define S_BREAK_LINK_TIMEOUT    0
54433 #define M_BREAK_LINK_TIMEOUT    0xffffffU
54437 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
54440 #define M_MODULE_ID    0xffffU
54444 #define S_MODULE_REVISION    0
54445 #define M_MODULE_REVISION    0xffffU
54449 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
54460 #define M_RXREQ_C0    0x3U
54465 #define M_RXREQ_C1    0x3U
54469 #define S_RXREQ_C2    0
54470 #define M_RXREQ_C2    0x3U
54474 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
54481 #define M_RXSTAT_C0    0x3U
54486 #define M_RXSTAT_C1    0x3U
54490 #define S_RXSTAT_C2    0
54491 #define M_RXSTAT_C2    0x3U
54495 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
54506 #define M_TXREQ_C0    0x3U
54511 #define M_TXREQ_C1    0x3U
54515 #define S_TXREQ_C2    0
54516 #define M_TXREQ_C2    0x3U
54520 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
54527 #define M_TXSTAT_C0    0x3U
54532 #define M_TXSTAT_C1    0x3U
54536 #define S_TXSTAT_C2    0
54537 #define M_TXSTAT_C2    0x3U
54541 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
54544 #define M_MAN_DEC    0x3U
54560 #define S_STICKY_MODE    0
54564 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
54567 #define M_PRBS_CHK_ERRCNT    0xffU
54572 #define M_PRBS_SYNCCNT    0x7U
54592 #define S_PRBS_GEN_OFF    0
54596 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
54603 #define M_FSM_GDMRK    0x7U
54608 #define M_FSM_BADMRK    0x7U
54640 #define S_FSM_TR_EN    0
54644 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
54647 #define M_CC2FSM_STATE    0x7U
54652 #define M_CC1FSM_STATE    0x7U
54657 #define M_CC0FSM_STATE    0x7U
54662 #define M_FLFSM_STATE    0x7U
54666 #define S_TFSM_STATE    0
54667 #define M_TFSM_STATE    0x7U
54671 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
54673 #define S_PMD_TX_DIS    0
54677 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
54683 #define S_RESTART_TRAINING    0
54687 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
54689 #define S_PMD_SIGDET    0
54693 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
54707 #define S_RX_TRAINED    0
54711 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
54714 #define M_BWSEL    0x3U
54718 #define S_RTSEL    0
54719 #define M_RTSEL    0x3U
54723 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
54737 #define S_TPSEL    0
54738 #define M_TPSEL    0x7U
54742 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
54768 #define S_ALOAD    0
54772 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
54779 #define M_SLEW    0x7U
54783 #define S_FFE    0
54784 #define M_FFE    0x3U
54788 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
54814 #define S_IDAC    0
54815 #define M_IDAC    0x3U
54819 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
54821 #define S_STBY    0
54822 #define M_STBY    0xffffU
54826 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
54828 #define S_PON    0
54829 #define M_PON    0xffffU
54833 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
54835 #define S_NXTT0    0
54836 #define M_NXTT0    0xfU
54840 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
54842 #define S_NXTT1    0
54843 #define M_NXTT1    0x3fU
54847 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
54849 #define S_NXTT2    0
54850 #define M_NXTT2    0x1fU
54854 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
54856 #define S_TXPWR    0
54857 #define M_TXPWR    0x7fU
54861 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
54864 #define M_TXPOL    0x7U
54868 #define S_NTXPOL    0
54869 #define M_NTXPOL    0x7U
54873 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
54884 #define M_C2UPDT    0x3U
54889 #define M_C1UPDT    0x3U
54893 #define S_C0UPDT    0
54894 #define M_C0UPDT    0x3U
54898 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
54901 #define M_C2STAT    0x3U
54906 #define M_C1STAT    0x3U
54910 #define S_C0STAT    0
54911 #define M_C0STAT    0x3U
54915 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
54917 #define S_NIDAC0    0
54918 #define M_NIDAC0    0x1fU
54922 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
54924 #define S_NIDAC1    0
54925 #define M_NIDAC1    0x7fU
54929 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
54931 #define S_NIDAC2    0
54932 #define M_NIDAC2    0x3fU
54936 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
54942 #define S_OPVAL    0
54943 #define M_OPVAL    0x1fU
54947 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
54949 #define S_PDAC    0
54950 #define M_PDAC    0x1fU
54954 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
54956 #define S_AIDAC0    0
54957 #define M_AIDAC0    0x1fU
54961 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
54963 #define S_AIDAC1    0
54964 #define M_AIDAC1    0x1fU
54968 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
54970 #define S_TXA_AIDAC2    0
54971 #define M_TXA_AIDAC2    0x1fU
54975 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
54977 #define S_CURSD    0
54978 #define M_CURSD    0x7fU
54982 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
54984 #define S_XDATA    0
54985 #define M_XDATA    0xffffU
54989 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
54992 #define M_EXTADDR    0x1fU
54996 #define S_XWR    0
55000 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
55001 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
55002 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
55003 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
55004 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
55005 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
55006 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
55007 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
55008 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
55009 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
55010 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
55011 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
55012 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
55013 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
55014 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
55015 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
55016 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
55017 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
55018 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
55019 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
55020 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
55021 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
55023 #define S_AIDAC2    0
55024 #define M_AIDAC2    0x3fU
55028 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
55029 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
55030 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
55033 #define M_XADDR    0xfU
55037 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
55048 #define M_DMSEL    0x7U
55052 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
55059 #define M_RRATE    0x3U
55091 #define S_PRBSSEL    0
55092 #define M_PRBSSEL    0x7U
55096 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
55099 #define M_FTHROT    0xfU
55108 #define M_FILTCTL    0xfU
55113 #define M_RSRVO    0x3U
55133 #define S_SSCENABLE    0
55137 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
55152 #define M_TMSCAL    0x3U
55164 #define S_PHOFFS    0
55165 #define M_PHOFFS    0x1fU
55169 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
55172 #define M_ROT0A    0x3fU
55176 #define S_RTSEL_SNAPSHOT    0
55177 #define M_RTSEL_SNAPSHOT    0x3fU
55181 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
55183 #define S_ROT90    0
55184 #define M_ROT90    0x3fU
55188 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
55195 #define M_RAOOFF    0x1fU
55200 #define M_RAEOFF    0x1fU
55204 #define S_RDOFF    0
55205 #define M_RDOFF    0x1fU
55209 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
55212 #define M_SIGNSD    0x3U
55217 #define M_DACSD    0x1fU
55229 #define S_SDLVL    0
55230 #define M_SDLVL    0x1fU
55234 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
55253 #define M_SPIFMT    0x7U
55258 #define M_DFEPWR    0x7U
55282 #define S_DFERST    0
55286 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
55289 #define M_ESAMP    0xffU
55293 #define S_DSAMP    0
55294 #define M_DSAMP    0xffU
55298 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
55301 #define M_SMODE    0xfU
55314 #define M_ASAMPQ    0x7U
55318 #define S_ASAMP    0
55319 #define M_ASAMP    0x7U
55323 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
55326 #define M_POLE    0x3U
55331 #define M_PEAK    0x7U
55336 #define M_VOFFSN    0x3U
55340 #define S_VOFFA    0
55341 #define M_VOFFA    0x3fU
55345 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
55351 #define S_VGAIN    0
55352 #define M_VGAIN    0xfU
55356 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
55374 #define S_AMAXT    0
55375 #define M_AMAXT    0x7fU
55379 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
55382 #define M_D01SN    0x3U
55387 #define M_D01AMP    0x1fU
55392 #define M_D00SN    0x3U
55396 #define S_D00AMP    0
55397 #define M_D00AMP    0x1fU
55401 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
55404 #define M_D11SN    0x3U
55409 #define M_D11AMP    0x1fU
55414 #define M_D10SN    0x3U
55418 #define S_D10AMP    0
55419 #define M_D10AMP    0x1fU
55423 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
55426 #define M_E1SN    0x3U
55431 #define M_E1AMP    0x1fU
55436 #define M_E0SN    0x3U
55440 #define S_E0AMP    0
55441 #define M_E0AMP    0x1fU
55445 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
55448 #define M_AOFFO    0x3fU
55452 #define S_AOFFE    0
55453 #define M_AOFFE    0x3fU
55457 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
55460 #define M_DACAN    0xffU
55464 #define S_DACAP    0
55465 #define M_DACAP    0xffU
55469 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
55472 #define M_DACAZ    0xffU
55476 #define S_DACAM    0
55477 #define M_DACAM    0xffU
55481 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
55484 #define M_ADSN    0x3U
55488 #define S_ADMAG    0
55489 #define M_ADMAG    0x7fU
55493 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
55500 #define M_WIDTH    0x1fU
55505 #define M_MINWIDTH    0x1fU
55509 #define S_MINAMP    0
55510 #define M_MINAMP    0x1fU
55514 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
55525 #define M_EMMD    0x3U
55533 #define S_EMEN    0
55537 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
55540 #define M_H1OSN    0x3U
55545 #define M_H1OMAG    0x3fU
55550 #define M_H1ESN    0x3U
55554 #define S_H1EMAG    0
55555 #define M_H1EMAG    0x3fU
55559 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
55562 #define M_H2OSN    0x3U
55567 #define M_H2OMAG    0x1fU
55572 #define M_H2ESN    0x3U
55576 #define S_H2EMAG    0
55577 #define M_H2EMAG    0x1fU
55581 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
55584 #define M_H3OSN    0x3U
55589 #define M_H3OMAG    0xfU
55594 #define M_H3ESN    0x3U
55598 #define S_H3EMAG    0
55599 #define M_H3EMAG    0xfU
55603 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
55606 #define M_H4OSN    0x3U
55611 #define M_H4OMAG    0xfU
55616 #define M_H4ESN    0x3U
55620 #define S_H4EMAG    0
55621 #define M_H4EMAG    0xfU
55625 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
55628 #define M_H5OSN    0x3U
55633 #define M_H5OMAG    0xfU
55638 #define M_H5ESN    0x3U
55642 #define S_H5EMAG    0
55643 #define M_H5EMAG    0xfU
55647 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
55658 #define M_DPCTGT    0x7U
55671 #define M_H1TGT    0x7U
55675 #define S_OAE    0
55676 #define M_OAE    0xfU
55680 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
55683 #define M_OLS    0x1fU
55688 #define M_OES    0x1fU
55696 #define S_ODEC    0
55697 #define M_ODEC    0x1fU
55701 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
55751 #define S_OCCMP    0
55755 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
55813 #define S_FADAC    0
55817 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
55818 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
55819 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
55820 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
55821 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
55822 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
55823 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
55824 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
55825 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
55826 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
55827 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
55828 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
55829 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
55830 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
55831 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
55832 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
55833 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
55834 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
55835 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
55836 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
55837 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
55838 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
55839 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
55840 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
55841 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
55842 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
55843 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
55844 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
55845 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
55846 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
55847 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
55848 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
55849 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
55850 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
55851 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
55852 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
55853 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
55854 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
55855 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
55856 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
55857 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
55858 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
55859 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
55860 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
55861 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
55862 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
55863 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
55864 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
55865 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
55866 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
55867 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
55868 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
55869 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
55870 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
55871 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
55872 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
55873 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
55874 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
55875 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
55876 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
55877 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
55878 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
55879 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
55880 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
55881 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
55882 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
55883 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
55884 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
55885 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
55886 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
55887 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
55888 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
55889 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
55890 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
55891 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
55892 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
55893 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
55894 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
55895 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
55896 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
55897 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
55898 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
55899 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
55900 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
55901 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
55902 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
55903 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
55904 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
55905 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
55906 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
55907 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
55908 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
55909 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
55910 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
55911 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
55912 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
55913 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
55914 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
55915 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
55916 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
55917 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
55918 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
55919 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
55920 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
55921 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
55922 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
55923 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
55924 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
55925 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
55926 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
55927 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
55928 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
55929 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
55930 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
55931 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
55932 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
55933 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
55934 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
55935 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
55936 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
55937 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
55938 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
55939 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
55940 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
55941 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
55942 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
55943 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
55944 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
55945 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
55946 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
55947 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
55948 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
55949 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
55950 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
55951 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
55952 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
55953 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
55954 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
55955 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
55956 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
55957 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
55958 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
55959 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
55960 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
55961 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
55962 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
55963 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
55965 #define S_BSELO    0
55966 #define M_BSELO    0xfU
55970 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
55984 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
55986 #define S_BSELI    0
55987 #define M_BSELI    0xfU
55991 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
56009 #define S_TCDIS    0
56013 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
56023 #define S_CCLD    0
56027 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
56029 #define S_ATST    0
56030 #define M_ATST    0x1fU
56034 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
56064 #define S_TXAEN    0
56068 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
56098 #define S_TXARST    0
56102 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
56108 #define S_CPISEL    0
56109 #define M_CPISEL    0x3U
56113 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
56115 #define S_BGCTL    0
56116 #define M_BGCTL    0x1fU
56120 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
56134 #define S_LFSEL    0
56138 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
56148 #define S_VBADJ    0
56152 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
56153 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
56154 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
56155 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
56156 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
56157 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
56158 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
56159 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
56160 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
56161 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
56162 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
56163 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
56164 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
56165 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
56166 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
56167 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
56168 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
56169 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
56170 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
56171 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
56172 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
56173 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
56174 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
56175 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
56176 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
56177 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
56178 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
56179 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
56180 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
56181 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
56182 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
56183 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
56184 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
56185 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
56186 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
56187 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
56188 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
56189 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
56190 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
56191 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
56192 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
56193 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
56194 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
56195 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
56196 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
56197 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
56198 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
56199 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
56200 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
56201 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
56202 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
56203 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
56204 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
56205 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
56206 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
56207 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
56208 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
56209 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
56210 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
56213 #define UP_BASE_ADDR 0x0
56215 #define A_UP_IBQ_CONFIG 0x0
56218 #define M_IBQGEN2    0x3fffffffU
56226 #define S_IBQEN    0
56230 #define A_UP_OBQ_CONFIG 0x4
56233 #define M_OBQGEN2    0x3fffffffU
56241 #define S_OBQEN    0
56245 #define A_UP_IBQ_GEN 0x8
56248 #define M_IBQGEN0    0x3ffU
56253 #define M_IBQTSCHCHNLRDY    0xfU
56266 #define M_IBQGEN1    0x3ffU
56270 #define S_IBQEMPTY    0
56271 #define M_IBQEMPTY    0x3fU
56276 #define M_T7_IBQGEN1    0x3fU
56280 #define S_T7_IBQEMPTY    0
56281 #define M_T7_IBQEMPTY    0x3ffU
56285 #define A_UP_OBQ_GEN 0xc
56288 #define M_OBQGEN    0x3ffffffU
56292 #define S_OBQFULL    0
56293 #define M_OBQFULL    0x3fU
56298 #define M_T5_OBQGEN    0xffffffU
56302 #define S_T5_OBQFULL    0
56303 #define M_T5_OBQFULL    0xffU
56308 #define M_T7_T5_OBQGEN    0xffffU
56312 #define S_T7_T5_OBQFULL    0
56313 #define M_T7_T5_OBQFULL    0xffffU
56317 #define A_UP_IBQ_0_RDADDR 0x10
56320 #define M_QUEID    0x7ffffU
56324 #define S_IBQRDADDR    0
56325 #define M_IBQRDADDR    0x1fffU
56329 #define A_UP_IBQ_GEN_IPC 0x10
56331 #define S_IPCEMPTY    0
56332 #define M_IPCEMPTY    0x7fU
56336 #define A_UP_IBQ_0_WRADDR 0x14
56338 #define S_IBQWRADDR    0
56339 #define M_IBQWRADDR    0x1fffU
56343 #define A_UP_IBQ_0_STATUS 0x18
56349 #define S_QUEREMFLITS    0
56350 #define M_QUEREMFLITS    0x7ffU
56354 #define A_UP_IBQ_0_PKTCNT 0x1c
56357 #define M_QUEEOPCNT    0xfffU
56361 #define S_QUESOPCNT    0
56362 #define M_QUESOPCNT    0xfffU
56366 #define A_UP_IBQ_1_RDADDR 0x20
56367 #define A_UP_IBQ_1_WRADDR 0x24
56368 #define A_UP_IBQ_1_STATUS 0x28
56369 #define A_UP_IBQ_1_PKTCNT 0x2c
56370 #define A_UP_IBQ_2_RDADDR 0x30
56371 #define A_UP_IBQ_2_WRADDR 0x34
56372 #define A_UP_IBQ_2_STATUS 0x38
56373 #define A_UP_IBQ_2_PKTCNT 0x3c
56374 #define A_UP_IBQ_3_RDADDR 0x40
56375 #define A_UP_IBQ_3_WRADDR 0x44
56376 #define A_UP_IBQ_3_STATUS 0x48
56377 #define A_UP_IBQ_3_PKTCNT 0x4c
56378 #define A_UP_IBQ_4_RDADDR 0x50
56379 #define A_UP_IBQ_4_WRADDR 0x54
56380 #define A_UP_IBQ_4_STATUS 0x58
56381 #define A_UP_IBQ_4_PKTCNT 0x5c
56382 #define A_UP_IBQ_5_RDADDR 0x60
56383 #define A_UP_IBQ_5_WRADDR 0x64
56384 #define A_UP_IBQ_5_STATUS 0x68
56385 #define A_UP_IBQ_5_PKTCNT 0x6c
56386 #define A_UP_OBQ_0_RDADDR 0x70
56389 #define M_OBQID    0x1ffffU
56393 #define S_QUERDADDR    0
56394 #define M_QUERDADDR    0x7fffU
56398 #define A_UP_OBQ_0_WRADDR 0x74
56400 #define S_QUEWRADDR    0
56401 #define M_QUEWRADDR    0x7fffU
56405 #define A_UP_OBQ_0_STATUS 0x78
56406 #define A_UP_OBQ_0_PKTCNT 0x7c
56407 #define A_UP_OBQ_1_RDADDR 0x80
56408 #define A_UP_NXT_FLOWADDR0 0x80
56409 #define A_UP_OBQ_1_WRADDR 0x84
56410 #define A_UP_NXT_FLOWADDR1 0x84
56411 #define A_UP_OBQ_1_STATUS 0x88
56412 #define A_UP_NXT_FLOWADDR2 0x88
56413 #define A_UP_OBQ_1_PKTCNT 0x8c
56414 #define A_UP_NXT_FLOWADDR3 0x8c
56415 #define A_UP_OBQ_2_RDADDR 0x90
56416 #define A_UP_DFT_FLOWADDR 0x90
56417 #define A_UP_OBQ_2_WRADDR 0x94
56418 #define A_UP_OBQ_2_STATUS 0x98
56419 #define A_UP_OBQ_2_PKTCNT 0x9c
56420 #define A_UP_OBQ_3_RDADDR 0xa0
56421 #define A_UP_OBQ_3_WRADDR 0xa4
56422 #define A_UP_OBQ_3_STATUS 0xa8
56423 #define A_UP_OBQ_3_PKTCNT 0xac
56424 #define A_UP_OBQ_4_RDADDR 0xb0
56425 #define A_UP_OBQ_4_WRADDR 0xb4
56426 #define A_UP_OBQ_4_STATUS 0xb8
56427 #define A_UP_OBQ_4_PKTCNT 0xbc
56428 #define A_UP_OBQ_5_RDADDR 0xc0
56429 #define A_UP_MAX_SEQ_NUM 0xc0
56430 #define A_UP_OBQ_5_WRADDR 0xc4
56431 #define A_UP_UNACK_SEQ_NUM 0xc4
56432 #define A_UP_OBQ_5_STATUS 0xc8
56433 #define A_UP_SEARCH_SEQ_NUM 0xc8
56434 #define A_UP_OBQ_5_PKTCNT 0xcc
56435 #define A_UP_SEQ_SEARCH_CTRL 0xcc
56438 #define M_FIFO_SIZE    0x7U
56447 #define M_SEQ_WR_PTR    0xfffU
56451 #define S_SEQ_RD_PTR    0
56452 #define M_SEQ_RD_PTR    0xfffU
56456 #define A_UP_IBQ_0_CONFIG 0xd0
56459 #define M_QUESIZE    0x3fU
56464 #define M_QUEBASE    0x3fU
56472 #define S_QUEBAREADDR    0
56480 #define A_UP_SEQ_SEARCH_RES0 0xd0
56494 #define S_MATCH_INDEX    0
56495 #define M_MATCH_INDEX    0xffffU
56499 #define A_UP_IBQ_0_REALADDR 0xd4
56510 #define M_QUEMEMADDR    0x7ffU
56514 #define A_UP_SEQ_SEARCH_RES1 0xd4
56515 #define A_UP_IBQ_1_CONFIG 0xd8
56516 #define A_UP_IBQ_1_REALADDR 0xdc
56517 #define A_UP_IBQ_2_CONFIG 0xe0
56518 #define A_UP_IBQ_2_REALADDR 0xe4
56519 #define A_UP_IBQ_3_CONFIG 0xe8
56520 #define A_UP_IBQ_3_REALADDR 0xec
56521 #define A_UP_IBQ_4_CONFIG 0xf0
56522 #define A_UP_IBQ_4_REALADDR 0xf4
56523 #define A_UP_IBQ_5_CONFIG 0xf8
56524 #define A_UP_IBQ_5_REALADDR 0xfc
56525 #define A_UP_OBQ_0_CONFIG 0x100
56526 #define A_UP_PEER_HALT_STAT0 0x100
56529 #define M_HALTINFO    0x7fffffffU
56533 #define A_UP_OBQ_0_REALADDR 0x104
56534 #define A_UP_PEER_HALT_STAT1 0x104
56535 #define A_UP_OBQ_1_CONFIG 0x108
56536 #define A_UP_PEER_HALT_STAT2 0x108
56537 #define A_UP_OBQ_1_REALADDR 0x10c
56538 #define A_UP_PEER_HALT_STAT3 0x10c
56539 #define A_UP_OBQ_2_CONFIG 0x110
56540 #define A_UP_PEER_HALT_STAT4 0x110
56541 #define A_UP_OBQ_2_REALADDR 0x114
56542 #define A_UP_PEER_HALT_STAT5 0x114
56543 #define A_UP_OBQ_3_CONFIG 0x118
56544 #define A_UP_PEER_HALT_STAT6 0x118
56545 #define A_UP_OBQ_3_REALADDR 0x11c
56546 #define A_UP_PEER_HALT_STAT7 0x11c
56547 #define A_UP_OBQ_4_CONFIG 0x120
56548 #define A_UP_PEER_HALT_CTL 0x120
56550 #define S_HALTREQ    0
56554 #define A_UP_OBQ_4_REALADDR 0x124
56555 #define A_UP_OBQ_5_CONFIG 0x128
56556 #define A_UP_OBQ_5_REALADDR 0x12c
56557 #define A_UP_MAILBOX_STATUS 0x130
56560 #define M_MBGEN0    0xfffU
56565 #define M_GENTIMERTRIGGER    0xfU
56570 #define M_MBGEN1    0xffU
56574 #define S_MBPFINT    0
56575 #define M_MBPFINT    0xffU
56579 #define A_UP_UP_DBG_LA_CFG 0x140
56598 #define M_UPDBGLAWRPTR    0xfffU
56603 #define M_UPDBGLARDPTR    0xfffU
56611 #define S_UPDBGLAEN    0
56619 #define A_UP_UP_DBG_LA_DATA 0x144
56620 #define A_UP_PIO_MST_CONFIG 0x148
56623 #define M_FLSRC    0x7U
56632 #define M_SESRC    0x7U
56641 #define M_UPPF    0x7U
56645 #define S_UPRID    0
56646 #define M_UPRID    0xffffU
56654 #define S_T5_UPRID    0
56655 #define M_T5_UPRID    0xffU
56659 #define S_T6_UPRID    0
56660 #define M_T6_UPRID    0x1ffU
56664 #define A_UP_UP_SELF_CONTROL 0x14c
56666 #define S_UPSELFRESET    0
56670 #define A_UP_MAILBOX_PF0_CTL 0x180
56671 #define A_UP_MAILBOX_PF1_CTL 0x190
56672 #define A_UP_MAILBOX_PF2_CTL 0x1a0
56673 #define A_UP_MAILBOX_PF3_CTL 0x1b0
56674 #define A_UP_MAILBOX_PF4_CTL 0x1c0
56675 #define A_UP_MAILBOX_PF5_CTL 0x1d0
56676 #define A_UP_MAILBOX_PF6_CTL 0x1e0
56677 #define A_UP_MAILBOX_PF7_CTL 0x1f0
56678 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
56688 #define S_TSCHCHNLCRDY    0
56689 #define M_TSCHCHNLCRDY    0x3fffffffU
56693 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
56696 #define M_TSCHWRRLIMIT    0xffffU
56700 #define S_TSCHCHNLCWRDY    0
56701 #define M_TSCHCHNLCWRDY    0xffffU
56705 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
56708 #define M_TSCHWRRRELOAD    0xffffU
56712 #define S_TSCHCHNLCWATCH    0
56713 #define M_TSCHCHNLCWATCH    0xffffU
56717 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
56720 #define M_TSCHCHNLCNUM    0x1fU
56724 #define S_TSCHCHNLCCNT    0
56725 #define M_TSCHCHNLCCNT    0xffffffU
56741 #define A_UP_UPLADBGPCCHKDATA_0 0x240
56742 #define A_UP_UPLADBGPCCHKMASK_0 0x244
56743 #define A_UP_UPLADBGPCCHKDATA_1 0x250
56744 #define A_UP_UPLADBGPCCHKMASK_1 0x254
56745 #define A_UP_UPLADBGPCCHKDATA_2 0x260
56746 #define A_UP_UPLADBGPCCHKMASK_2 0x264
56747 #define A_UP_UPLADBGPCCHKDATA_3 0x270
56748 #define A_UP_UPLADBGPCCHKMASK_3 0x274
56749 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
56750 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
56751 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
56752 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
56753 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
56754 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
56755 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
56756 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
56757 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
56758 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
56759 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
56760 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
56761 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
56762 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
56763 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
56764 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
56765 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
56766 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
56767 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
56768 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
56769 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
56770 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
56771 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
56772 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
56773 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
56774 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
56775 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
56776 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
56777 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
56778 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
56779 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
56780 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
56781 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
56782 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
56783 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
56784 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
56785 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
56786 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
56787 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
56788 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
56789 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
56790 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
56791 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
56792 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
56793 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
56794 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
56795 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
56796 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
56797 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
56798 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
56799 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
56800 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
56801 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
56802 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
56803 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
56804 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
56805 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
56806 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
56807 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
56808 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
56809 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
56810 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
56811 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
56812 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
56813 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
56814 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
56815 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
56816 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
56817 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
56818 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
56819 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
56820 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
56821 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
56822 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
56823 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
56824 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
56825 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
56826 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
56827 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
56828 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
56829 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
56830 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
56831 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
56832 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
56833 #define A_T7_UP_IBQ_0_SHADOW_RDADDR 0x400
56834 #define A_T7_UP_IBQ_0_SHADOW_WRADDR 0x404
56835 #define A_T7_UP_IBQ_0_SHADOW_STATUS 0x408
56837 #define S_T7_QUEREMFLITS    0
56838 #define M_T7_QUEREMFLITS    0xfffU
56842 #define A_T7_UP_IBQ_0_SHADOW_PKTCNT 0x40c
56843 #define A_T7_UP_IBQ_1_SHADOW_RDADDR 0x410
56844 #define A_T7_UP_IBQ_1_SHADOW_WRADDR 0x414
56845 #define A_T7_UP_IBQ_1_SHADOW_STATUS 0x418
56846 #define A_T7_UP_IBQ_1_SHADOW_PKTCNT 0x41c
56847 #define A_T7_UP_IBQ_2_SHADOW_RDADDR 0x420
56848 #define A_T7_UP_IBQ_2_SHADOW_WRADDR 0x424
56849 #define A_T7_UP_IBQ_2_SHADOW_STATUS 0x428
56850 #define A_T7_UP_IBQ_2_SHADOW_PKTCNT 0x42c
56851 #define A_T7_UP_IBQ_3_SHADOW_RDADDR 0x430
56852 #define A_T7_UP_IBQ_3_SHADOW_WRADDR 0x434
56853 #define A_T7_UP_IBQ_3_SHADOW_STATUS 0x438
56854 #define A_T7_UP_IBQ_3_SHADOW_PKTCNT 0x43c
56855 #define A_T7_UP_IBQ_4_SHADOW_RDADDR 0x440
56856 #define A_T7_UP_IBQ_4_SHADOW_WRADDR 0x444
56857 #define A_T7_UP_IBQ_4_SHADOW_STATUS 0x448
56858 #define A_T7_UP_IBQ_4_SHADOW_PKTCNT 0x44c
56859 #define A_T7_UP_IBQ_5_SHADOW_RDADDR 0x450
56860 #define A_T7_UP_IBQ_5_SHADOW_WRADDR 0x454
56861 #define A_T7_UP_IBQ_5_SHADOW_STATUS 0x458
56862 #define A_T7_UP_IBQ_5_SHADOW_PKTCNT 0x45c
56863 #define A_UP_IBQ_6_SHADOW_RDADDR 0x460
56864 #define A_UP_IBQ_6_SHADOW_WRADDR 0x464
56865 #define A_UP_IBQ_6_SHADOW_STATUS 0x468
56866 #define A_UP_IBQ_6_SHADOW_PKTCNT 0x46c
56867 #define A_UP_IBQ_7_SHADOW_RDADDR 0x470
56868 #define A_UP_IBQ_7_SHADOW_WRADDR 0x474
56869 #define A_UP_IBQ_7_SHADOW_STATUS 0x478
56870 #define A_UP_IBQ_7_SHADOW_PKTCNT 0x47c
56871 #define A_UP_IBQ_8_SHADOW_RDADDR 0x480
56872 #define A_UP_IBQ_8_SHADOW_WRADDR 0x484
56873 #define A_UP_IBQ_8_SHADOW_STATUS 0x488
56874 #define A_UP_IBQ_8_SHADOW_PKTCNT 0x48c
56875 #define A_UP_IBQ_9_SHADOW_RDADDR 0x490
56876 #define A_UP_IBQ_9_SHADOW_WRADDR 0x494
56877 #define A_UP_IBQ_9_SHADOW_STATUS 0x498
56878 #define A_UP_IBQ_9_SHADOW_PKTCNT 0x49c
56879 #define A_UP_IBQ_10_SHADOW_RDADDR 0x4a0
56880 #define A_UP_IBQ_10_SHADOW_WRADDR 0x4a4
56881 #define A_UP_IBQ_10_SHADOW_STATUS 0x4a8
56882 #define A_UP_IBQ_10_SHADOW_PKTCNT 0x4ac
56883 #define A_UP_IBQ_11_SHADOW_RDADDR 0x4b0
56884 #define A_UP_IBQ_11_SHADOW_WRADDR 0x4b4
56885 #define A_UP_IBQ_11_SHADOW_STATUS 0x4b8
56886 #define A_UP_IBQ_11_SHADOW_PKTCNT 0x4bc
56887 #define A_UP_IBQ_12_SHADOW_RDADDR 0x4c0
56888 #define A_UP_IBQ_12_SHADOW_WRADDR 0x4c4
56889 #define A_UP_IBQ_12_SHADOW_STATUS 0x4c8
56890 #define A_UP_IBQ_12_SHADOW_PKTCNT 0x4cc
56891 #define A_UP_IBQ_13_SHADOW_RDADDR 0x4d0
56892 #define A_UP_IBQ_13_SHADOW_WRADDR 0x4d4
56893 #define A_UP_IBQ_13_SHADOW_STATUS 0x4d8
56894 #define A_UP_IBQ_13_SHADOW_PKTCNT 0x4dc
56895 #define A_UP_IBQ_14_SHADOW_RDADDR 0x4e0
56896 #define A_UP_IBQ_14_SHADOW_WRADDR 0x4e4
56897 #define A_UP_IBQ_14_SHADOW_STATUS 0x4e8
56898 #define A_UP_IBQ_14_SHADOW_PKTCNT 0x4ec
56899 #define A_UP_IBQ_15_SHADOW_RDADDR 0x4f0
56900 #define A_UP_IBQ_15_SHADOW_WRADDR 0x4f4
56901 #define A_UP_IBQ_15_SHADOW_STATUS 0x4f8
56902 #define A_UP_IBQ_15_SHADOW_PKTCNT 0x4fc
56903 #define A_T7_UP_IBQ_0_SHADOW_CONFIG 0x500
56904 #define A_T7_UP_IBQ_0_SHADOW_REALADDR 0x504
56905 #define A_T7_UP_IBQ_1_SHADOW_CONFIG 0x510
56906 #define A_T7_UP_IBQ_1_SHADOW_REALADDR 0x514
56907 #define A_T7_UP_IBQ_2_SHADOW_CONFIG 0x520
56908 #define A_T7_UP_IBQ_2_SHADOW_REALADDR 0x524
56909 #define A_T7_UP_IBQ_3_SHADOW_CONFIG 0x530
56910 #define A_T7_UP_IBQ_3_SHADOW_REALADDR 0x534
56911 #define A_T7_UP_IBQ_4_SHADOW_CONFIG 0x540
56912 #define A_T7_UP_IBQ_4_SHADOW_REALADDR 0x544
56913 #define A_T7_UP_IBQ_5_SHADOW_CONFIG 0x550
56914 #define A_T7_UP_IBQ_5_SHADOW_REALADDR 0x554
56915 #define A_UP_IBQ_6_SHADOW_CONFIG 0x560
56916 #define A_UP_IBQ_6_SHADOW_REALADDR 0x564
56917 #define A_UP_IBQ_7_SHADOW_CONFIG 0x570
56918 #define A_UP_IBQ_7_SHADOW_REALADDR 0x574
56919 #define A_UP_IBQ_8_SHADOW_CONFIG 0x580
56920 #define A_UP_IBQ_8_SHADOW_REALADDR 0x584
56921 #define A_UP_IBQ_9_SHADOW_CONFIG 0x590
56922 #define A_UP_IBQ_9_SHADOW_REALADDR 0x594
56923 #define A_UP_IBQ_10_SHADOW_CONFIG 0x5a0
56924 #define A_UP_IBQ_10_SHADOW_REALADDR 0x5a4
56925 #define A_UP_IBQ_11_SHADOW_CONFIG 0x5b0
56926 #define A_UP_IBQ_11_SHADOW_REALADDR 0x5b4
56927 #define A_UP_IBQ_12_SHADOW_CONFIG 0x5c0
56928 #define A_UP_IBQ_12_SHADOW_REALADDR 0x5c4
56929 #define A_UP_IBQ_13_SHADOW_CONFIG 0x5d0
56930 #define A_UP_IBQ_13_SHADOW_REALADDR 0x5d4
56931 #define A_UP_IBQ_14_SHADOW_CONFIG 0x5e0
56932 #define A_UP_IBQ_14_SHADOW_REALADDR 0x5e4
56933 #define A_UP_IBQ_15_SHADOW_CONFIG 0x5f0
56934 #define A_UP_IBQ_15_SHADOW_REALADDR 0x5f4
56935 #define A_T7_UP_OBQ_0_SHADOW_RDADDR 0x600
56936 #define A_T7_UP_OBQ_0_SHADOW_WRADDR 0x604
56937 #define A_T7_UP_OBQ_0_SHADOW_STATUS 0x608
56938 #define A_T7_UP_OBQ_0_SHADOW_PKTCNT 0x60c
56939 #define A_T7_UP_OBQ_1_SHADOW_RDADDR 0x610
56940 #define A_T7_UP_OBQ_1_SHADOW_WRADDR 0x614
56941 #define A_T7_UP_OBQ_1_SHADOW_STATUS 0x618
56942 #define A_T7_UP_OBQ_1_SHADOW_PKTCNT 0x61c
56943 #define A_T7_UP_OBQ_2_SHADOW_RDADDR 0x620
56944 #define A_T7_UP_OBQ_2_SHADOW_WRADDR 0x624
56945 #define A_T7_UP_OBQ_2_SHADOW_STATUS 0x628
56946 #define A_T7_UP_OBQ_2_SHADOW_PKTCNT 0x62c
56947 #define A_T7_UP_OBQ_3_SHADOW_RDADDR 0x630
56948 #define A_T7_UP_OBQ_3_SHADOW_WRADDR 0x634
56949 #define A_T7_UP_OBQ_3_SHADOW_STATUS 0x638
56950 #define A_T7_UP_OBQ_3_SHADOW_PKTCNT 0x63c
56951 #define A_T7_UP_OBQ_4_SHADOW_RDADDR 0x640
56952 #define A_T7_UP_OBQ_4_SHADOW_WRADDR 0x644
56953 #define A_T7_UP_OBQ_4_SHADOW_STATUS 0x648
56954 #define A_T7_UP_OBQ_4_SHADOW_PKTCNT 0x64c
56955 #define A_T7_UP_OBQ_5_SHADOW_RDADDR 0x650
56956 #define A_T7_UP_OBQ_5_SHADOW_WRADDR 0x654
56957 #define A_T7_UP_OBQ_5_SHADOW_STATUS 0x658
56958 #define A_T7_UP_OBQ_5_SHADOW_PKTCNT 0x65c
56959 #define A_T7_UP_OBQ_6_SHADOW_RDADDR 0x660
56960 #define A_T7_UP_OBQ_6_SHADOW_WRADDR 0x664
56961 #define A_T7_UP_OBQ_6_SHADOW_STATUS 0x668
56962 #define A_T7_UP_OBQ_6_SHADOW_PKTCNT 0x66c
56963 #define A_T7_UP_OBQ_7_SHADOW_RDADDR 0x670
56964 #define A_T7_UP_OBQ_7_SHADOW_WRADDR 0x674
56965 #define A_T7_UP_OBQ_7_SHADOW_STATUS 0x678
56966 #define A_T7_UP_OBQ_7_SHADOW_PKTCNT 0x67c
56967 #define A_UP_OBQ_8_SHADOW_RDADDR 0x680
56968 #define A_UP_OBQ_8_SHADOW_WRADDR 0x684
56969 #define A_UP_OBQ_8_SHADOW_STATUS 0x688
56970 #define A_UP_OBQ_8_SHADOW_PKTCNT 0x68c
56971 #define A_UP_OBQ_9_SHADOW_RDADDR 0x690
56972 #define A_UP_OBQ_9_SHADOW_WRADDR 0x694
56973 #define A_UP_OBQ_9_SHADOW_STATUS 0x698
56974 #define A_UP_OBQ_9_SHADOW_PKTCNT 0x69c
56975 #define A_UP_OBQ_10_SHADOW_RDADDR 0x6a0
56976 #define A_UP_OBQ_10_SHADOW_WRADDR 0x6a4
56977 #define A_UP_OBQ_10_SHADOW_STATUS 0x6a8
56978 #define A_UP_OBQ_10_SHADOW_PKTCNT 0x6ac
56979 #define A_UP_OBQ_11_SHADOW_RDADDR 0x6b0
56980 #define A_UP_OBQ_11_SHADOW_WRADDR 0x6b4
56981 #define A_UP_OBQ_11_SHADOW_STATUS 0x6b8
56982 #define A_UP_OBQ_11_SHADOW_PKTCNT 0x6bc
56983 #define A_UP_OBQ_12_SHADOW_RDADDR 0x6c0
56984 #define A_UP_OBQ_12_SHADOW_WRADDR 0x6c4
56985 #define A_UP_OBQ_12_SHADOW_STATUS 0x6c8
56986 #define A_UP_OBQ_12_SHADOW_PKTCNT 0x6cc
56987 #define A_UP_OBQ_13_SHADOW_RDADDR 0x6d0
56988 #define A_UP_OBQ_13_SHADOW_WRADDR 0x6d4
56989 #define A_UP_OBQ_13_SHADOW_STATUS 0x6d8
56990 #define A_UP_OBQ_13_SHADOW_PKTCNT 0x6dc
56991 #define A_UP_OBQ_14_SHADOW_RDADDR 0x6e0
56992 #define A_UP_OBQ_14_SHADOW_WRADDR 0x6e4
56993 #define A_UP_OBQ_14_SHADOW_STATUS 0x6e8
56994 #define A_UP_OBQ_14_SHADOW_PKTCNT 0x6ec
56995 #define A_UP_OBQ_15_SHADOW_RDADDR 0x6f0
56996 #define A_UP_OBQ_15_SHADOW_WRADDR 0x6f4
56997 #define A_UP_OBQ_15_SHADOW_STATUS 0x6f8
56998 #define A_UP_OBQ_15_SHADOW_PKTCNT 0x6fc
56999 #define A_T7_UP_OBQ_0_SHADOW_CONFIG 0x700
57000 #define A_T7_UP_OBQ_0_SHADOW_REALADDR 0x704
57001 #define A_T7_UP_OBQ_1_SHADOW_CONFIG 0x710
57002 #define A_T7_UP_OBQ_1_SHADOW_REALADDR 0x714
57003 #define A_T7_UP_OBQ_2_SHADOW_CONFIG 0x720
57004 #define A_T7_UP_OBQ_2_SHADOW_REALADDR 0x724
57005 #define A_T7_UP_OBQ_3_SHADOW_CONFIG 0x730
57006 #define A_T7_UP_OBQ_3_SHADOW_REALADDR 0x734
57007 #define A_T7_UP_OBQ_4_SHADOW_CONFIG 0x740
57008 #define A_T7_UP_OBQ_4_SHADOW_REALADDR 0x744
57009 #define A_T7_UP_OBQ_5_SHADOW_CONFIG 0x750
57010 #define A_T7_UP_OBQ_5_SHADOW_REALADDR 0x754
57011 #define A_T7_UP_OBQ_6_SHADOW_CONFIG 0x760
57012 #define A_T7_UP_OBQ_6_SHADOW_REALADDR 0x764
57013 #define A_T7_UP_OBQ_7_SHADOW_CONFIG 0x770
57014 #define A_T7_UP_OBQ_7_SHADOW_REALADDR 0x774
57015 #define A_UP_OBQ_8_SHADOW_CONFIG 0x780
57016 #define A_UP_OBQ_8_SHADOW_REALADDR 0x784
57017 #define A_UP_OBQ_9_SHADOW_CONFIG 0x790
57018 #define A_UP_OBQ_9_SHADOW_REALADDR 0x794
57019 #define A_UP_OBQ_10_SHADOW_CONFIG 0x7a0
57020 #define A_UP_OBQ_10_SHADOW_REALADDR 0x7a4
57021 #define A_UP_OBQ_11_SHADOW_CONFIG 0x7b0
57022 #define A_UP_OBQ_11_SHADOW_REALADDR 0x7b4
57023 #define A_UP_OBQ_12_SHADOW_CONFIG 0x7c0
57024 #define A_UP_OBQ_12_SHADOW_REALADDR 0x7c4
57025 #define A_UP_OBQ_13_SHADOW_CONFIG 0x7d0
57026 #define A_UP_OBQ_13_SHADOW_REALADDR 0x7d4
57027 #define A_UP_OBQ_14_SHADOW_CONFIG 0x7e0
57028 #define A_UP_OBQ_14_SHADOW_REALADDR 0x7e4
57029 #define A_UP_OBQ_15_SHADOW_CONFIG 0x7f0
57030 #define A_UP_OBQ_15_SHADOW_REALADDR 0x7f4
57033 #define CIM_CTL_BASE_ADDR 0x0
57035 #define A_CIM_CTL_CONFIG 0x0
57038 #define M_AUTOPREFLOC    0x1fU
57066 #define S_PREFEN    0
57078 #define A_CIM_CTL_PREFADDR 0x4
57079 #define A_CIM_CTL_ALLOCADDR 0x8
57080 #define A_CIM_CTL_INVLDTADDR 0xc
57081 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
57082 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
57083 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
57084 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
57085 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
57086 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
57087 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
57088 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
57089 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
57090 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
57091 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
57092 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
57093 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
57094 #define A_CIM_CTL_SEM_CFG 0x40
57100 #define S_NUMSEM    0
57101 #define M_NUMSEM    0x3ffffU
57105 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
57106 #define A_CIM_CTL_SEM_MA_CFG 0x44
57109 #define M_SEMMABASE    0xfffffffU
57113 #define S_SEMMATHREADID    0
57114 #define M_SEMMATHREADID    0x7U
57118 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
57119 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
57120 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
57121 #define A_CIM_CTL_LOCK_CFG 0x50
57123 #define S_NUMLOCK    0
57124 #define M_NUMLOCK    0x3ffffU
57128 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
57129 #define A_CIM_CTL_LOCK_MA_CFG 0x54
57132 #define M_LOCKMABASE    0xfffffffU
57136 #define S_LOCKMATHREADID    0
57137 #define M_LOCKMATHREADID    0x7U
57141 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
57142 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
57143 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
57144 #define A_CIM_CTL_RSA_INT 0x60
57145 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
57146 #define A_CIM_CTL_RSA_BUSY 0x64
57147 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
57148 #define A_CIM_CTL_RSA_CPERR 0x68
57149 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
57150 #define A_CIM_CTL_RSA_DPERR 0x6c
57151 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
57152 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
57153 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
57154 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
57155 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
57156 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
57157 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
57158 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
57159 #define A_CIM_CTL_FIFO_CNT 0x90
57161 #define S_CTLFIFOCNT    0
57162 #define M_CTLFIFOCNT    0xfU
57166 #define A_CIM_CTL_GLB_TIMER 0x94
57167 #define A_CIM_CTL_TIMER0 0x98
57168 #define A_CIM_CTL_TIMER1 0x9c
57169 #define A_CIM_CTL_GEN0 0xa0
57170 #define A_CIM_CTL_GEN1 0xa4
57171 #define A_CIM_CTL_GEN2 0xa8
57172 #define A_CIM_CTL_GEN3 0xac
57173 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
57174 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
57185 #define M_GENTIMERACT    0x3U
57190 #define M_GENTIMERCFG    0x3U
57198 #define S_GENTIMERSTRT    0
57202 #define A_CIM_CTL_GEN_TIMER0 0xb8
57203 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
57204 #define A_CIM_CTL_GEN_TIMER1 0xc0
57205 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
57206 #define A_CIM_CTL_GEN_TIMER2 0xc8
57207 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
57208 #define A_CIM_CTL_GEN_TIMER3 0xd0
57209 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
57210 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
57211 #define A_CIM_CTL_TID_MAP_EN 0x500
57212 #define A_CIM_CTL_TID_MAP_CORE 0x520
57213 #define A_CIM_CTL_TID_MAP_CONFIG 0x540
57216 #define M_TIDDEFCORE    0xfU
57220 #define S_TIDVECBASE    0
57221 #define M_TIDVECBASE    0x7U
57225 #define A_CIM_CTL_CRYPTO_KEY_DATA 0x600
57226 #define A_CIM_CTL_SECURE_CONFIG 0x6f8
57227 #define A_CIM_CTL_CRYPTO_KEY_CTRL 0x6fc
57230 #define M_CRYPTOKEYDATAREGNUM    0xffU
57234 #define S_CRYPTOKEYSTARTBUSY    0
57238 #define A_CIM_CTL_FLOWID_OP_VALID 0x700
57239 #define A_CIM_CTL_FLOWID_CTL 0x720
57242 #define M_FLOWBASEADDR    0xffffffU
57247 #define M_SEQSRCHALIGNCFG    0x3U
57252 #define M_FLOWADDRSIZE    0x3U
57256 #define S_FLOWIDEN    0
57260 #define A_CIM_CTL_FLOWID_MAX 0x724
57262 #define S_MAXFLOWID    0
57263 #define M_MAXFLOWID    0xffffffU
57267 #define A_CIM_CTL_FLOWID_HINT0 0x728
57268 #define A_CIM_CTL_EFUSE_CTRL 0x780
57269 #define A_CIM_CTL_EFUSE_QOUT 0x784
57270 #define A_CIM_CTL_EFUSE_RFOUT 0x788
57271 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
57285 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
57287 #define S_TSCHNLTICK    0
57288 #define M_TSCHNLTICK    0xffffU
57292 #define A_CIM_CTL_TSCH_CHNLN_CLASS_RATECTL 0x904
57354 #define S_TSC0RATECTL    0
57358 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
57484 #define S_TSC0RATEEN    0
57488 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
57490 #define S_MIN_MAX_EN    0
57494 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
57500 #define S_TSCHNLRATEL    0
57501 #define M_TSCHNLRATEL    0x7fffffffU
57509 #define S_T6_TSCHNLRATEL    0
57510 #define M_T6_TSCHNLRATEL    0x3fffffffU
57514 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
57517 #define M_TSCHNLRMAX    0xffffU
57521 #define S_TSCHNLRINCR    0
57522 #define M_TSCHNLRINCR    0xffffU
57527 #define M_TSCHNLRTSEL    0x3U
57531 #define S_T6_TSCHNLRINCR    0
57532 #define M_T6_TSCHNLRINCR    0x3fffU
57536 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
57537 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
57539 #define S_TSCHNLWEIGHT    0
57540 #define M_TSCHNLWEIGHT    0x3fffffU
57544 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
57550 #define S_TSCCLRATEL    0
57551 #define M_TSCCLRATEL    0xffffffU
57559 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
57562 #define M_TSCCLRMAX    0xffffU
57566 #define S_TSCCLRINCR    0
57567 #define M_TSCCLRINCR    0xffffU
57572 #define M_TSCCLRTSEL    0x3U
57576 #define S_T6_TSCCLRINCR    0
57577 #define M_T6_TSCCLRINCR    0x3fffU
57581 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
57587 #define S_TSCCLWRR    0
57588 #define M_TSCCLWRR    0x3ffffffU
57596 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
57598 #define S_TSCCLWEIGHT    0
57599 #define M_TSCCLWEIGHT    0xffffU
57604 #define M_PAUSEVECSEL    0x3U
57609 #define M_MPSPAUSEMASK    0xffU
57613 #define A_CIM_CTL_TSCH_TICK0 0xd80
57614 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
57615 #define A_CIM_CTL_TSCH_TICK1 0xd84
57616 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
57617 #define A_CIM_CTL_TSCH_TICK2 0xd88
57618 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
57619 #define A_CIM_CTL_TSCH_TICK3 0xd8c
57620 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
57621 #define A_T6_CIM_CTL_MAILBOX_PF0_CTL 0xd90
57622 #define A_T7_CIM_CTL_MAILBOX_PF0_CTL 0xd90
57623 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
57624 #define A_T6_CIM_CTL_MAILBOX_PF1_CTL 0xd94
57625 #define A_T7_CIM_CTL_MAILBOX_PF1_CTL 0xd94
57626 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
57627 #define A_T6_CIM_CTL_MAILBOX_PF2_CTL 0xd98
57628 #define A_T7_CIM_CTL_MAILBOX_PF2_CTL 0xd98
57629 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
57630 #define A_T6_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
57631 #define A_T7_CIM_CTL_MAILBOX_PF3_CTL 0xd9c
57632 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
57633 #define A_T6_CIM_CTL_MAILBOX_PF4_CTL 0xda0
57634 #define A_T7_CIM_CTL_MAILBOX_PF4_CTL 0xda0
57635 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
57697 #define S_PF0_OWNER_UP    0
57701 #define A_T6_CIM_CTL_MAILBOX_PF5_CTL 0xda4
57702 #define A_T7_CIM_CTL_MAILBOX_PF5_CTL 0xda4
57703 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
57705 #define S_T5_CTLRID    0
57706 #define M_T5_CTLRID    0xffU
57710 #define A_T6_CIM_CTL_MAILBOX_PF6_CTL 0xda8
57711 #define A_T7_CIM_CTL_MAILBOX_PF6_CTL 0xda8
57712 #define A_T6_CIM_CTL_MAILBOX_PF7_CTL 0xdac
57713 #define A_T7_CIM_CTL_MAILBOX_PF7_CTL 0xdac
57714 #define A_T6_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
57715 #define A_T7_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xdb0
57716 #define A_T6_CIM_CTL_PIO_MST_CONFIG 0xdb4
57717 #define A_T7_CIM_CTL_PIO_MST_CONFIG 0xdb4
57718 #define A_CIM_CTL_ULP_OBQ0_PAUSE_MASK 0xe00
57719 #define A_CIM_CTL_ULP_OBQ1_PAUSE_MASK 0xe04
57720 #define A_CIM_CTL_ULP_OBQ2_PAUSE_MASK 0xe08
57721 #define A_CIM_CTL_ULP_OBQ3_PAUSE_MASK 0xe0c
57722 #define A_CIM_CTL_ULP_OBQ_CONFIG 0xe10
57728 #define S_CH0_PRIO_EN    0
57732 #define A_CIM_CTL_PIF_TIMEOUT 0xe40
57735 #define M_SLOW_TIMEOUT    0xffffU
57739 #define S_MA_TIMEOUT    0
57740 #define M_MA_TIMEOUT    0xffffU
57744 #define A_CIM_CTL_BREAK 0xf00
57747 #define M_XOCDMODE    0xffU
57751 #define S_BREAKIN_CONTROL    0
57752 #define M_BREAKIN_CONTROL    0xffU
57756 #define A_CIM_CTL_SLV_BOOT_CFG 0x4000
57759 #define M_T7_UPGEN    0x1fU
57767 #define A_CIM_CTL_SLV_BOOT_LEN 0x4004
57768 #define A_CIM_CTL_SLV_ACC_INT_ENABLE 0x4008
57769 #define A_CIM_CTL_SLV_ACC_INT_CAUSE 0x400c
57770 #define A_CIM_CTL_SLV_INT_ENABLE 0x4010
57771 #define A_CIM_CTL_SLV_INT_CAUSE 0x4014
57772 #define A_CIM_CTL_SLV_PERR_ENABLE 0x4018
57773 #define A_CIM_CTL_SLV_PERR_CAUSE 0x401c
57774 #define A_CIM_CTL_SLV_ADDR_TIMEOUT 0x4028
57775 #define A_CIM_CTL_SLV_ADDR_ILLEGAL 0x402c
57776 #define A_CIM_CTL_SLV_PIO_MST_CONFIG 0x4030
57777 #define A_CIM_CTL_SLV_MEM_ZONE0_VA 0x4040
57778 #define A_CIM_CTL_SLV_MEM_ZONE0_BA 0x4044
57779 #define A_CIM_CTL_SLV_MEM_ZONE0_LEN 0x4048
57780 #define A_CIM_CTL_SLV_MEM_ZONE1_VA 0x404c
57781 #define A_CIM_CTL_SLV_MEM_ZONE1_BA 0x4050
57782 #define A_CIM_CTL_SLV_MEM_ZONE1_LEN 0x4054
57783 #define A_CIM_CTL_SLV_MEM_ZONE2_VA 0x4058
57784 #define A_CIM_CTL_SLV_MEM_ZONE2_BA 0x405c
57785 #define A_CIM_CTL_SLV_MEM_ZONE2_LEN 0x4060
57786 #define A_CIM_CTL_SLV_MEM_ZONE3_VA 0x4064
57787 #define A_CIM_CTL_SLV_MEM_ZONE3_BA 0x4068
57788 #define A_CIM_CTL_SLV_MEM_ZONE3_LEN 0x406c
57789 #define A_CIM_CTL_SLV_MEM_ZONE4_VA 0x4070
57790 #define A_CIM_CTL_SLV_MEM_ZONE4_BA 0x4074
57791 #define A_CIM_CTL_SLV_MEM_ZONE4_LEN 0x4078
57792 #define A_CIM_CTL_SLV_MEM_ZONE5_VA 0x407c
57793 #define A_CIM_CTL_SLV_MEM_ZONE5_BA 0x4080
57794 #define A_CIM_CTL_SLV_MEM_ZONE5_LEN 0x4084
57795 #define A_CIM_CTL_SLV_MEM_ZONE6_VA 0x4088
57796 #define A_CIM_CTL_SLV_MEM_ZONE6_BA 0x408c
57797 #define A_CIM_CTL_SLV_MEM_ZONE6_LEN 0x4090
57798 #define A_CIM_CTL_SLV_MEM_ZONE7_VA 0x4094
57799 #define A_CIM_CTL_SLV_MEM_ZONE7_BA 0x4098
57800 #define A_CIM_CTL_SLV_MEM_ZONE7_LEN 0x409c
57803 #define MAC_BASE_ADDR 0x0
57805 #define A_MAC_PORT_CFG 0x800
57808 #define M_MAC_CLK_SEL    0x7U
57821 #define M_PORTSPEED    0x3U
57838 #define M_PORT_MAP    0x7U
57855 #define M_DEBUG_PORT_SEL    0x3U
57871 #define A_MAC_PORT_RESET_CTRL 0x804
57997 #define A_MAC_PORT_LED_CFG 0x808
58000 #define M_LED1_CFG1    0x3U
58005 #define M_LED0_CFG1    0x3U
58025 #define A_MAC_PORT_LED_COUNTHI 0x80c
58026 #define A_MAC_PORT_LED_COUNTLO 0x810
58027 #define A_MAC_PORT_CFG3 0x814
58030 #define M_T5_FPGA_PTP_PORT    0x3U
58055 #define M_AN_ENA    0xfU
58060 #define M_SD_RX_CLK_ENA    0xfU
58065 #define M_SD_TX_CLK_ENA    0xfU
58074 #define M_HSSPLLSEL    0xfU
58078 #define S_HSSC16C20SEL    0
58079 #define M_HSSC16C20SEL    0xfU
58084 #define M_REF_CLK_SEL    0x3U
58097 #define M_MAC_FPGA_PTP_PORT    0x3U
58101 #define A_MAC_PORT_CFG2 0x818
58104 #define M_T5_AEC_PMA_TX_READY    0xfU
58108 #define S_T5_AEC_PMA_RX_READY    0
58109 #define M_T5_AEC_PMA_RX_READY    0xfU
58117 #define A_MAC_PORT_PKT_COUNT 0x81c
58118 #define A_MAC_PORT_CFG4 0x820
58121 #define M_AEC3_RX_WIDTH    0x3U
58126 #define M_AEC2_RX_WIDTH    0x3U
58131 #define M_AEC1_RX_WIDTH    0x3U
58136 #define M_AEC0_RX_WIDTH    0x3U
58141 #define M_AEC3_TX_WIDTH    0x3U
58146 #define M_AEC2_TX_WIDTH    0x3U
58151 #define M_AEC1_TX_WIDTH    0x3U
58155 #define S_AEC0_TX_WIDTH    0
58156 #define M_AEC0_TX_WIDTH    0x3U
58160 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
58161 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
58162 #define A_MAC_PORT_MTIP_RESET_CTRL 0x82c
58288 #define S_XGMII_CLK_RESET    0
58292 #define A_MAC_PORT_MTIP_GATE_CTRL 0x830
58418 #define S_AN_CLK_ENABLE    0
58422 #define A_MAC_PORT_LINK_STATUS 0x834
58444 #define A_MAC_PORT_AEC_ADD_CTL_STAT_0 0x838
58463 #define M_AEC_SYS_LANE_SELECT_3    0x3U
58468 #define M_AEC_SYS_LANE_SELECT_2    0x3U
58473 #define M_AEC_SYS_LANE_SELECT_1    0x3U
58477 #define S_AEC_SYS_LANE_SELECT_O    0
58478 #define M_AEC_SYS_LANE_SELECT_O    0x3U
58482 #define A_MAC_PORT_AEC_ADD_CTL_STAT_1 0x83c
58501 #define M_AEC_RX_LANE_ID_3    0x3U
58506 #define M_AEC_RX_LANE_ID_2    0x3U
58511 #define M_AEC_RX_LANE_ID_1    0x3U
58515 #define S_AEC_RX_LANE_ID_O    0
58516 #define M_AEC_RX_LANE_ID_O    0x3U
58520 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_40G 0x840
58522 #define S_XGMII_CLK_IN_1MS_LO_40G    0
58523 #define M_XGMII_CLK_IN_1MS_LO_40G    0xffffU
58527 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_40G 0x844
58529 #define S_XGMII_CLK_IN_1MS_HI_40G    0
58530 #define M_XGMII_CLK_IN_1MS_HI_40G    0xfU
58534 #define A_MAC_PORT_AEC_XGMII_TIMER_LO_100G 0x848
58536 #define S_XGMII_CLK_IN_1MS_LO_100G    0
58537 #define M_XGMII_CLK_IN_1MS_LO_100G    0xffffU
58541 #define A_MAC_PORT_AEC_XGMII_TIMER_HI_100G 0x84c
58543 #define S_XGMII_CLK_IN_1MS_HI_100G    0
58544 #define M_XGMII_CLK_IN_1MS_HI_100G    0xfU
58548 #define A_MAC_PORT_AEC_DEBUG_LO_0 0x850
58551 #define M_CTL_FSM_CUR_STATE    0x7U
58556 #define M_CIN_FSM_CUR_STATE    0x3U
58561 #define M_CRI_FSM_CUR_STATE    0x7U
58566 #define M_CU_C3_ACK_VALUE    0x3U
58571 #define M_CU_C2_ACK_VALUE    0x3U
58576 #define M_CU_C1_ACK_VALUE    0x3U
58581 #define M_CU_C0_ACK_VALUE    0x3U
58594 #define M_CUF_C3_UPDATE    0x3U
58599 #define M_CUF_C2_UPDATE    0x3U
58604 #define M_CUF_C1_UPDATE    0x3U
58609 #define M_CUF_C0_UPDATE    0x3U
58621 #define S_REG_MAN_DEC_REQ    0
58625 #define A_MAC_PORT_AEC_DEBUG_HI_0 0x854
58632 #define M_CUF_C0_FSM_DEBUG    0x7U
58637 #define M_CUF_C1_FSM_DEBUG    0x7U
58642 #define M_CUF_C2_FSM_DEBUG    0x7U
58646 #define S_LCK_FSM_CUR_STATE    0
58647 #define M_LCK_FSM_CUR_STATE    0x7U
58651 #define A_MAC_PORT_AEC_DEBUG_LO_1 0x858
58652 #define A_MAC_PORT_AEC_DEBUG_HI_1 0x85c
58653 #define A_MAC_PORT_AEC_DEBUG_LO_2 0x860
58654 #define A_MAC_PORT_AEC_DEBUG_HI_2 0x864
58655 #define A_MAC_PORT_AEC_DEBUG_LO_3 0x868
58656 #define A_MAC_PORT_AEC_DEBUG_HI_3 0x86c
58657 #define A_MAC_PORT_MAC_DEBUG_RO 0x870
58676 #define M_MAC1G10G_IF_MODE_ENA    0x3U
58708 #define S_MAC1G10G_TX_UNDERFLOW    0
58712 #define A_MAC_PORT_MAC_CTRL_RW 0x874
58715 #define M_MAC40G100G_FF_TX_PFC_XOFF    0xffU
58736 #define M_MAC1G10G_IF_MODE_SET    0x3U
58749 #define M_MAC1G10G_XOFF_GEN    0xffU
58753 #define S_MAC1G_LOOP_BCK    0
58757 #define A_MAC_PORT_PCS_DEBUG0_RO 0x878
58760 #define M_FPGA_LOCK    0xfU
58781 #define M_AN_SELECT    0x1fU
58790 #define M_PCS40G_BLOCK_LOCK    0xfU
58834 #define S_SGMII_SG_SPEED    0
58835 #define M_SGMII_SG_SPEED    0x3U
58839 #define A_MAC_PORT_PCS_CTRL_RW 0x87c
58850 #define M_BLK_STB_VAL    0xffU
58855 #define M_DEBUG_SEL    0xfU
58860 #define M_SGMII_LOOP    0x7U
58873 #define M_PCS100G_TX_LANE_THRESH    0xfU
58882 #define M_SGMII_TX_LANE_CKMULT    0x7U
58886 #define S_SGMII_TX_LANE_THRESH    0
58887 #define M_SGMII_TX_LANE_THRESH    0xfU
58891 #define A_MAC_PORT_PCS_DEBUG1_RO 0x880
58901 #define S_PCS100G_BLOCK_LOCK    0
58902 #define M_PCS100G_BLOCK_LOCK    0xfffffU
58906 #define A_MAC_PORT_PERR_INT_EN_100G 0x884
59024 #define S_PERR_RX0_PCS100G    0
59028 #define A_MAC_PORT_PERR_INT_CAUSE_100G 0x888
59029 #define A_MAC_PORT_PERR_ENABLE_100G 0x88c
59030 #define A_MAC_PORT_MAC_STAT_DEBUG 0x890
59031 #define A_MAC_PORT_MAC_25G_50G_AM0 0x894
59032 #define A_MAC_PORT_MAC_25G_50G_AM1 0x898
59033 #define A_MAC_PORT_MAC_25G_50G_AM2 0x89c
59034 #define A_MAC_PORT_MAC_25G_50G_AM3 0x8a0
59035 #define A_MAC_PORT_MAC_AN_STATE_STATUS 0x8a4
59036 #define A_MAC_PORT_EPIO_DATA0 0x8c0
59037 #define A_MAC_PORT_EPIO_DATA1 0x8c4
59038 #define A_MAC_PORT_EPIO_DATA2 0x8c8
59039 #define A_MAC_PORT_EPIO_DATA3 0x8cc
59040 #define A_MAC_PORT_EPIO_OP 0x8d0
59041 #define A_MAC_PORT_WOL_STATUS 0x8d4
59042 #define A_MAC_PORT_INT_EN 0x8d8
59064 #define A_MAC_PORT_INT_CAUSE 0x8dc
59065 #define A_MAC_PORT_PERR_INT_EN 0x8e0
59163 #define S_PERR0_TX    0
59291 #define S_PERR_TX_PCS1G    0
59295 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
59296 #define A_MAC_PORT_PERR_ENABLE 0x8e8
59297 #define A_MAC_PORT_PERR_INJECT 0x8ec
59300 #define M_MEMSEL_PERR    0x3fU
59304 #define A_MAC_PORT_HSS_CFG0 0x8f0
59362 #define A_MAC_PORT_HSS_CFG1 0x8f4
59365 #define M_RXACONFIGSEL    0x3U
59378 #define M_RXBCONFIGSEL    0x3U
59391 #define M_RXCCONFIGSEL    0x3U
59404 #define M_RXDCONFIGSEL    0x3U
59417 #define M_TXACONFIGSEL    0x3U
59430 #define M_TXBCONFIGSEL    0x3U
59443 #define M_TXCCONFIGSEL    0x3U
59456 #define M_TXDCONFIGSEL    0x3U
59464 #define S_TXDREFRESH    0
59468 #define A_MAC_PORT_HSS_CFG2 0x8f8
59502 #define A_MAC_PORT_HSS_CFG3 0x8fc
59505 #define M_HSSCALSSTN    0x7U
59510 #define M_HSSCALSSTP    0x7U
59515 #define M_HSSVBOOSTDIVB    0x7U
59520 #define M_HSSVBOOSTDIVA    0x7U
59525 #define M_HSSPLLCONFIGB    0xffU
59529 #define S_HSSPLLCONFIGA    0
59530 #define M_HSSPLLCONFIGA    0xffU
59535 #define M_T6_HSSCALSSTN    0x3fU
59540 #define M_T6_HSSCALSSTP    0x3fU
59544 #define A_MAC_PORT_HSS_CFG4 0x900
59547 #define M_HSSDIVSELA    0x1ffU
59551 #define S_HSSDIVSELB    0
59552 #define M_HSSDIVSELB    0x1ffU
59557 #define M_HSSREFDIVA    0xfU
59562 #define M_HSSREFDIVB    0xfU
59574 #define A_MAC_PORT_HSS_STATUS 0x904
59588 #define S_HSSPRTREADYA    0
59608 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
59670 #define S_TXDREFRESH_STATUS    0
59674 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
59675 #define A_MAC_PORT_HSS_PL_CTL 0x910
59678 #define M_TOV    0xffU
59683 #define M_TSU    0xffU
59687 #define S_IPW    0
59688 #define M_IPW    0xffU
59692 #define A_MAC_PORT_RUNT_FRAME 0x914
59698 #define S_RUNT    0
59699 #define M_RUNT    0xffffU
59703 #define A_MAC_PORT_EEE_STATUS 0x918
59706 #define M_EEE_TX_10G_STATE    0x3U
59711 #define M_EEE_RX_10G_STATE    0x3U
59716 #define M_EEE_TX_1G_STATE    0x3U
59721 #define M_EEE_RX_1G_STATE    0x3U
59737 #define S_PMA_TX_QUIET    0
59741 #define A_MAC_PORT_CGEN 0x91c
59775 #define S_SD0_CGEN    0
59779 #define A_MAC_PORT_CGEN_MTIP 0x920
59825 #define S_PCSSEG0_CGEN    0
59829 #define A_MAC_PORT_TX_TS_ID 0x924
59831 #define S_TS_ID    0
59832 #define M_TS_ID    0x7U
59836 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
59837 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
59838 #define A_MAC_PORT_EEE_CTL 0x930
59841 #define M_EEE_CTRL    0x3fffffffU
59849 #define S_EEE_ENABLE    0
59853 #define A_MAC_PORT_EEE_TX_CTL 0x934
59856 #define M_WAKE_TIMER    0xffffU
59861 #define M_HSS_TIMER    0xfU
59881 #define S_EEE_TX_RESET    0
59885 #define A_MAC_PORT_EEE_RX_CTL 0x938
59891 #define S_EEE_RX_RESET    0
59895 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
59896 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
59897 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
59898 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
59899 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
59900 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
59901 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
59902 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
59903 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
59904 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
59905 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
59906 #define A_MAC_PORT_EEE_WF_COUNT 0x968
59912 #define S_WAKE_CNT    0
59913 #define M_WAKE_CNT    0xffffU
59917 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
59918 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
59919 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
59920 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
59921 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
59922 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
59923 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
59924 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
59925 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
59927 #define S_PTP_OFFSET    0
59928 #define M_PTP_OFFSET    0xffU
59932 #define A_MAC_PORT_PTP_SUM_LO 0x990
59933 #define A_MAC_PORT_PTP_SUM_HI 0x994
59934 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
59937 #define M_Y    0xffffU
59941 #define S_X    0
59942 #define M_X    0xffffU
59946 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
59949 #define M_Y_TICK    0xffffU
59953 #define S_X_TICK    0
59954 #define M_X_TICK    0xffffU
59958 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
59959 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
59961 #if 0
59963 #define M_B    0xffffU
59968 #define S_A    0
59969 #define M_A    0xffffU
59973 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
59974 #define A_MAC_PORT_PTP_CFG 0x9ac
59989 #define M_CYCLE1    0xffU
59993 #define S_Q    0
59994 #define M_Q    0xffU
60010 #define A_MAC_PORT_PTP_PPS 0x9b0
60011 #define A_MAC_PORT_PTP_SINGLE_ALARM 0x9b4
60012 #define A_MAC_PORT_PTP_PERIODIC_ALARM 0x9b8
60013 #define A_MAC_PORT_PTP_STATUS 0x9bc
60015 #define S_ALARM_DONE    0
60019 #define A_MAC_PORT_MTIP_REVISION 0xa00
60022 #define M_CUSTREV    0xffffU
60027 #define M_VER    0xffU
60031 #define S_MTIP_REV    0
60032 #define M_MTIP_REV    0xffU
60036 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
60037 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
60123 #define S_TX_ENA    0
60127 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
60128 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
60130 #define S_MACADDRHI    0
60131 #define M_MACADDRHI    0xffffU
60135 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
60137 #define S_LEN    0
60138 #define M_LEN    0xffffU
60142 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
60145 #define M_AVAIL    0xffffU
60149 #define S_EMPTY    0
60150 #define M_EMPTY    0xffffU
60154 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
60155 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
60158 #define M_ALMSTFULL    0xffffU
60162 #define S_ALMSTEMPTY    0
60163 #define M_ALMSTEMPTY    0xffffU
60167 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
60168 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
60174 #define S_HASHTABLE_ADDR    0
60175 #define M_HASHTABLE_ADDR    0x3fU
60179 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
60193 #define S_RX_LOC_FAULT    0
60197 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
60199 #define S_IPG    0
60200 #define M_IPG    0x7fU
60204 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
60206 #define S_RXFIFORST    0
60210 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
60212 #define S_MACCRDRST    0
60213 #define M_MACCRDRST    0xffU
60217 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
60219 #define S_INITCREDIT    0
60220 #define M_INITCREDIT    0xffU
60224 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
60226 #define S_STATUS    0
60227 #define M_STATUS    0xffU
60231 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
60232 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
60233 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
60234 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
60235 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
60236 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
60237 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
60238 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
60239 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
60240 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
60241 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
60242 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
60243 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
60244 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
60245 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
60246 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
60247 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
60248 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
60249 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
60250 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
60251 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
60252 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
60253 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
60254 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
60255 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
60256 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
60257 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
60258 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
60259 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
60260 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
60261 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
60262 #define A_MAC_PORT_IFOUTERRORS 0xaf8
60263 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
60264 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
60265 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
60266 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
60267 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
60268 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
60269 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
60270 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
60271 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
60272 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
60273 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
60274 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
60275 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
60276 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
60277 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
60278 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
60279 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
60280 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
60281 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
60282 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
60283 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
60284 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
60285 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
60286 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
60287 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
60288 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
60289 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
60290 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
60291 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
60292 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
60293 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
60294 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
60295 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
60296 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
60297 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
60298 #define A_MAC_PORT_IFINERRORS 0xb90
60299 #define A_MAC_PORT_IFINERRORSHI 0xb94
60300 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
60301 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
60302 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
60303 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
60304 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
60305 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
60306 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
60307 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
60308 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
60309 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
60310 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
60311 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
60312 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
60313 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
60314 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
60315 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
60316 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
60317 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
60318 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
60319 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
60320 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
60321 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
60322 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
60323 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
60324 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
60325 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
60326 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
60327 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
60328 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
60329 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
60330 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
60331 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
60332 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
60333 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
60334 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
60335 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
60336 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
60378 #define A_MAC_PORT_MTIP_1G10G_REVISION 0xd00
60381 #define M_VER_1G10G    0xffU
60385 #define S_REV_1G10G    0
60386 #define M_REV_1G10G    0xffU
60390 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
60432 #define S_EXTDCAPABILITY    0
60436 #define A_MAC_PORT_MTIP_1G10G_SCRATCH 0xd04
60437 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
60438 #define A_MAC_PORT_MTIP_1G10G_COMMAND_CONFIG 0xd08
60476 #define S_TX_ENAMAC    0
60480 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
60481 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_0 0xd0c
60482 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
60508 #define A_MAC_PORT_MTIP_1G10G_MAC_ADDR_1 0xd10
60509 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
60520 #define M_CUSPEED    0x3U
60524 #define A_MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU 0xd14
60527 #define M_SET_LEN    0xffffU
60531 #define S_FRM_LEN_SET    0
60532 #define M_FRM_LEN_SET    0xffffU
60536 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
60542 #define S_REALTIMEPGRCVD    0
60546 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
60547 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS 0xd1c
60550 #define M_RX1G10G_EMPTY    0xffffU
60554 #define S_RX1G10G_AVAIL    0
60555 #define M_RX1G10G_AVAIL    0xffffU
60559 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
60560 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS 0xd20
60563 #define M_TX1G10G_EMPTY    0xffffU
60567 #define S_TX1G10G_AVAIL    0
60568 #define M_TX1G10G_AVAIL    0xffffU
60572 #define A_MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E 0xd24
60575 #define M_ALMOSTFULL    0xffffU
60579 #define S_ALMOSTEMPTY    0
60580 #define M_ALMOSTEMPTY    0xffffU
60584 #define A_MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E 0xd28
60585 #define A_MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD 0xd2c
60586 #define A_MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS 0xd30
60589 #define M_CLK_DIVISOR    0x1ffU
60602 #define M_HOLD_TIME_SETTING    0x7U
60610 #define A_MAC_PORT_MTIP_1G10G_MDIO_COMMAND 0xd34
60621 #define M_PORT_PHY_ADDR    0x1fU
60625 #define S_DEVICE_REG_ADDR    0
60626 #define M_DEVICE_REG_ADDR    0x1fU
60630 #define A_MAC_PORT_MTIP_1G10G_MDIO_DATA 0xd38
60632 #define S_MDIO_DATA    0
60633 #define M_MDIO_DATA    0xffffU
60637 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
60638 #define A_MAC_PORT_MTIP_1G10G_MDIO_REGADDR 0xd3c
60639 #define A_MAC_PORT_MTIP_1G10G_STATUS 0xd40
60657 #define A_MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH 0xd44
60658 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
60660 #define S_COUNT_LO    0
60661 #define M_COUNT_LO    0xffffU
60665 #define A_MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER 0xd48
60666 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
60668 #define S_COUNT_HI    0
60669 #define M_COUNT_HI    0x1fU
60673 #define A_MAC_PORT_MTIP_1G10G_INIT_CREDIT 0xd4c
60674 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
60685 #define M_SGMII_SPEED    0x3U
60693 #define S_SGMII_ENA    0
60697 #define A_MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA 0xd54
60700 #define M_CL1_PAUSE_QUANTA    0xffffU
60704 #define S_CL0_PAUSE_QUANTA    0
60705 #define M_CL0_PAUSE_QUANTA    0xffffU
60709 #define A_MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA 0xd58
60712 #define M_CL3_PAUSE_QUANTA    0xffffU
60716 #define S_CL2_PAUSE_QUANTA    0
60717 #define M_CL2_PAUSE_QUANTA    0xffffU
60721 #define A_MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA 0xd5c
60724 #define M_CL5_PAUSE_QUANTA    0xffffU
60728 #define S_CL4_PAUSE_QUANTA    0
60729 #define M_CL4_PAUSE_QUANTA    0xffffU
60733 #define A_MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA 0xd60
60736 #define M_CL7_PAUSE_QUANTA    0xffffU
60740 #define S_CL6_PAUSE_QUANTA    0
60741 #define M_CL6_PAUSE_QUANTA    0xffffU
60745 #define A_MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH 0xd64
60748 #define M_CL1_QUANTA_THRESH    0xffffU
60752 #define S_CL0_QUANTA_THRESH    0
60753 #define M_CL0_QUANTA_THRESH    0xffffU
60757 #define A_MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH 0xd68
60760 #define M_CL3_QUANTA_THRESH    0xffffU
60764 #define S_CL2_QUANTA_THRESH    0
60765 #define M_CL2_QUANTA_THRESH    0xffffU
60769 #define A_MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH 0xd6c
60772 #define M_CL5_QUANTA_THRESH    0xffffU
60776 #define S_CL4_QUANTA_THRESH    0
60777 #define M_CL4_QUANTA_THRESH    0xffffU
60781 #define A_MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH 0xd70
60784 #define M_CL7_QUANTA_THRESH    0xffffU
60788 #define S_CL6_QUANTA_THRESH    0
60789 #define M_CL6_QUANTA_THRESH    0xffffU
60793 #define A_MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS 0xd74
60795 #define S_STATUS_BIT    0
60796 #define M_STATUS_BIT    0xffU
60800 #define A_MAC_PORT_MTIP_1G10G_TS_TIMESTAMP 0xd7c
60801 #define A_MAC_PORT_MTIP_1G10G_STATN_CONFIG 0xde0
60811 #define S_SATURATE    0
60815 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS 0xe00
60816 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI 0xe04
60817 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOK 0xe08
60818 #define A_MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI 0xe0c
60819 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS 0xe10
60820 #define A_MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI 0xe14
60821 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES 0xe18
60822 #define A_MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI 0xe1c
60823 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOK 0xe20
60824 #define A_MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI 0xe24
60825 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORS 0xe28
60826 #define A_MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI 0xe2c
60827 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOK 0xe30
60828 #define A_MAC_PORT_MTIP_1G10G_RX_VLANOKHI 0xe34
60829 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORS 0xe38
60830 #define A_MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI 0xe3c
60831 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS 0xe40
60832 #define A_MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI 0xe44
60833 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS 0xe48
60834 #define A_MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI 0xe4c
60835 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS 0xe50
60836 #define A_MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI 0xe54
60837 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS 0xe58
60838 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI 0xe5c
60839 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS 0xe60
60840 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI 0xe64
60841 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS 0xe68
60842 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI 0xe6c
60843 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS 0xe70
60844 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI 0xe74
60845 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS 0xe78
60846 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI 0xe7c
60847 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS 0xe80
60848 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI 0xe84
60849 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS 0xe88
60850 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI 0xe8c
60851 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS 0xe90
60852 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI 0xe94
60853 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS 0xe98
60854 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xe9c
60855 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX 0xea0
60856 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI 0xea4
60857 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS 0xea8
60858 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI 0xeac
60859 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS 0xeb0
60860 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI 0xeb4
60861 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS 0xeb8
60862 #define A_MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI 0xebc
60863 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED 0xec0
60864 #define A_MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI 0xec4
60865 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG 0xec8
60866 #define A_MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI 0xecc
60867 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS 0xed0
60868 #define A_MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI 0xed4
60869 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS 0xf00
60870 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI 0xf04
60871 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOK 0xf08
60872 #define A_MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI 0xf0c
60873 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS 0xf10
60874 #define A_MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI 0xf14
60875 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES 0xf18
60876 #define A_MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI 0xf1c
60877 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOK 0xf20
60878 #define A_MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI 0xf24
60879 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORS 0xf28
60880 #define A_MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI 0xf2c
60881 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOK 0xf30
60882 #define A_MAC_PORT_MTIP_1G10G_TX_VLANOKHI 0xf34
60883 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS 0xf38
60884 #define A_MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI 0xf3c
60885 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS 0xf40
60886 #define A_MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI 0xf44
60887 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS 0xf48
60888 #define A_MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI 0xf4c
60889 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS 0xf50
60890 #define A_MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI 0xf54
60891 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS 0xf58
60892 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI 0xf5c
60893 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS 0xf60
60894 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI 0xf64
60895 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS 0xf68
60896 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI 0xf6c
60897 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS 0xf70
60898 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI 0xf74
60899 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS 0xf78
60900 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI 0xf7c
60901 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS 0xf80
60902 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI 0xf84
60903 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS 0xf88
60904 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI 0xf8c
60905 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS 0xf90
60906 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI 0xf94
60907 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS 0xf98
60908 #define A_MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI 0xf9c
60909 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU 0xfa0
60910 #define A_MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI 0xfa4
60911 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES 0xfc0
60912 #define A_MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI 0xfc4
60913 #define A_MAC_PORT_MTIP_1G10G_IF_MODE 0x1000
60919 #define S_IF_MODE    0
60920 #define M_IF_MODE    0x3U
60924 #define A_MAC_PORT_MTIP_1G10G_IF_STATUS 0x1004
60926 #define S_IF_STATUS_MODE    0
60927 #define M_IF_STATUS_MODE    0x3U
60931 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0 0x1080
60932 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI 0x1084
60933 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1 0x1088
60934 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI 0x108c
60935 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2 0x1090
60936 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI 0x1094
60937 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3 0x1098
60938 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI 0x109c
60939 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4 0x10a0
60940 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI 0x10a4
60941 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5 0x10a8
60942 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI 0x10ac
60943 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6 0x10b0
60944 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI 0x10b4
60945 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7 0x10b8
60946 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI 0x10bc
60947 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0 0x10c0
60948 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI 0x10c4
60949 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1 0x10c8
60950 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI 0x10cc
60951 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2 0x10d0
60952 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI 0x10d4
60953 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3 0x10d8
60954 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI 0x10dc
60955 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4 0x10e0
60956 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI 0x10e4
60957 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5 0x10e8
60958 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI 0x10ec
60959 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6 0x10f0
60960 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI 0x10f4
60961 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7 0x10f8
60962 #define A_MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI 0x10fc
60963 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
60965 #define S_ACTIVE    0
60966 #define M_ACTIVE    0x3fU
60970 #define A_T6_MAC_PORT_MTIP_SGMII_CONTROL 0x1200
60992 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
60994 #define S_MODE_CTL    0
60995 #define M_MODE_CTL    0x3U
60999 #define A_T6_MAC_PORT_MTIP_SGMII_STATUS 0x1204
61005 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
61007 #define S_TXCLK_CTL    0
61008 #define M_TXCLK_CTL    0xffffU
61012 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0x1208
61013 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
61014 #define A_T6_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0x120c
61015 #define A_T6_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0x1210
61016 #define A_T6_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0x1214
61017 #define A_T6_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0x1218
61027 #define A_MAC_PORT_MTIP_SGMII_NP_TX 0x121c
61029 #define S_NP_TX    0
61030 #define M_NP_TX    0xffffU
61034 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
61036 #define S_COL_CNT    0
61037 #define M_COL_CNT    0xffffU
61041 #define A_MAC_PORT_MTIP_SGMII_LP_NP_RX 0x1220
61043 #define S_LP_NP_RX    0
61044 #define M_LP_NP_RX    0xffffU
61048 #define A_T6_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0x123c
61050 #define S_EXTENDED_STATUS    0
61051 #define M_EXTENDED_STATUS    0xffffU
61055 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
61061 #define A_MAC_PORT_MTIP_SGMII_SCRATCH 0x1240
61063 #define S_SCRATCH    0
61064 #define M_SCRATCH    0xffffU
61068 #define A_MAC_PORT_MTIP_SGMII_REV 0x1244
61071 #define M_SGMII_VER    0xffU
61075 #define S_SGMII_REV    0
61076 #define M_SGMII_REV    0xffU
61080 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0x1248
61082 #define S_LINK_TIMER_LO    0
61083 #define M_LINK_TIMER_LO    0xffffU
61087 #define A_T6_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0x124c
61089 #define S_LINK_TIMER_HI    0
61090 #define M_LINK_TIMER_HI    0xffffU
61094 #define A_T6_MAC_PORT_MTIP_SGMII_IF_MODE 0x1250
61100 #define A_MAC_PORT_MTIP_SGMII_DECODE_ERROR 0x1254
61102 #define S_T6_DECODE_ERROR    0
61103 #define M_T6_DECODE_ERROR    0xffffU
61107 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_1 0x1300
61114 #define M_SPEED_SEL2    0xfU
61118 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_1 0x1304
61148 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1 0x1308
61149 #define A_MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2 0x130c
61150 #define A_MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY 0x1310
61152 #define S_10G_CAPABLE    0
61156 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO 0x1314
61182 #define S_CLAUSE_22_REG_PRESENT    0
61186 #define A_MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI 0x1318
61187 #define A_MAC_PORT_MTIP_KR_PCS_CONTROL_2 0x131c
61189 #define S_PCS_TYPE_SELECTION    0
61190 #define M_PCS_TYPE_SELECTION    0x3U
61194 #define A_MAC_PORT_MTIP_KR_PCS_STATUS_2 0x1320
61197 #define M_DEVICE_PRESENT    0x3U
61217 #define S_10GBASE_R_CAPABLE    0
61221 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO 0x1338
61223 #define S_PCS_PACKAGE_IDENTIFIER_LO    0
61224 #define M_PCS_PACKAGE_IDENTIFIER_LO    0xffffU
61228 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI 0x133c
61230 #define S_PCS_PACKAGE_IDENTIFIER_HI    0
61231 #define M_PCS_PACKAGE_IDENTIFIER_HI    0xffffU
61235 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1 0x1380
61253 #define S_10GBASE_R_PCS_BLOCK_LOCK    0
61257 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2 0x1384
61268 #define M_BERBER_COUNTER    0x3fU
61272 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0 0x1388
61274 #define S_TEST_PATTERN_SEED_A0    0
61275 #define M_TEST_PATTERN_SEED_A0    0xffffU
61279 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1 0x138c
61281 #define S_TEST_PATTERN_SEED_A1    0
61282 #define M_TEST_PATTERN_SEED_A1    0xffffU
61286 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2 0x1390
61288 #define S_TEST_PATTERN_SEED_A2    0
61289 #define M_TEST_PATTERN_SEED_A2    0xffffU
61293 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3 0x1394
61295 #define S_TEST_PATTERN_SEED_A3    0
61296 #define M_TEST_PATTERN_SEED_A3    0x3ffU
61300 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0 0x1398
61302 #define S_TEST_PATTERN_SEED_B0    0
61303 #define M_TEST_PATTERN_SEED_B0    0xffffU
61307 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1 0x139c
61309 #define S_TEST_PATTERN_SEED_B1    0
61310 #define M_TEST_PATTERN_SEED_B1    0xffffU
61314 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2 0x13a0
61316 #define S_TEST_PATTERN_SEED_B2    0
61317 #define M_TEST_PATTERN_SEED_B2    0xffffU
61321 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3 0x13a4
61323 #define S_TEST_PATTERN_SEED_B3    0
61324 #define M_TEST_PATTERN_SEED_B3    0x3ffU
61328 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL 0x13a8
61354 #define S_DATA_PATTERN_SELECT    0
61358 #define A_MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER 0x13ac
61360 #define S_TEST_PATTERN_ERR_CNTR    0
61361 #define M_TEST_PATTERN_ERR_CNTR    0xffffU
61365 #define A_MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS 0x13b4
61371 #define S_RECEIVE_FIFO_FAULT    0
61375 #define A_MAC_PORT_MTIP_KR4_CONTROL_1 0x1400
61386 #define M_SPEED_SELECTION2    0xfU
61390 #define A_MAC_PORT_MTIP_KR4_STATUS_1 0x1404
61396 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID0 0x1408
61397 #define A_MAC_PORT_MTIP_KR4_DEVICE_ID1 0x140c
61400 #define M_T6_DEVICE_ID1    0xffffU
61404 #define A_MAC_PORT_MTIP_KR4_SPEED_ABILITY 0x1410
61418 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1 0x1414
61420 #define S_CLAUSE_22_REG    0
61424 #define A_MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2 0x1418
61438 #define A_MAC_PORT_MTIP_KR4_CONTROL_2 0x141c
61440 #define S_PCS_TYPE_SEL    0
61441 #define M_PCS_TYPE_SEL    0x7U
61445 #define A_MAC_PORT_MTIP_KR4_STATUS_2 0x1420
61459 #define A_MAC_PORT_MTIP_KR4_PKG_ID0 0x1438
61460 #define A_MAC_PORT_MTIP_KR4_PKG_ID1 0x143c
61461 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_1 0x1480
61471 #define S_KR4_BLOCK_LOCK    0
61475 #define A_MAC_PORT_MTIP_KR4_BASE_R_STATUS_2 0x1484
61486 #define M_BER_CNT    0x3fU
61490 #define S_ERR_BL_CNT    0
61491 #define M_ERR_BL_CNT    0xffU
61495 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL 0x14a8
61505 #define A_MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT 0x14ac
61507 #define S_TP_ERR_CNTR    0
61508 #define M_TP_ERR_CNTR    0xffffU
61512 #define A_MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT 0x14b0
61514 #define S_BER_HI_ORDER_CNT    0
61515 #define M_BER_HI_ORDER_CNT    0xffffU
61519 #define A_MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT 0x14b4
61525 #define S_ERR_BLK_CNTR    0
61526 #define M_ERR_BLK_CNTR    0x3fffU
61530 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1 0x14c8
61548 #define S_LANE_0_BLK_LCK    0
61552 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2 0x14cc
61553 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3 0x14d0
61567 #define S_LANE_0_ALIGN_MRKR_LCK    0
61571 #define A_MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4 0x14d4
61572 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
61575 #define M_CLK_DIV    0x1ffU
61588 #define M_MDIO_HOLD_TIME    0x7U
61596 #define S_MDIO_BUSY    0
61600 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
61611 #define M_PORT_ADDR    0x1fU
61615 #define S_DEV_ADDR    0
61616 #define M_DEV_ADDR    0x1fU
61620 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
61626 #define S_DATA_WORD    0
61627 #define M_DATA_WORD    0xffffU
61631 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
61633 #define S_MDIO_ADDR    0
61634 #define M_MDIO_ADDR    0xffffU
61638 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0 0x1720
61640 #define S_BIP_ERR_CNT_LANE_0    0
61641 #define M_BIP_ERR_CNT_LANE_0    0xffffU
61645 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1 0x1724
61647 #define S_BIP_ERR_CNT_LANE_1    0
61648 #define M_BIP_ERR_CNT_LANE_1    0xffffU
61652 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2 0x1728
61654 #define S_BIP_ERR_CNT_LANE_2    0
61655 #define M_BIP_ERR_CNT_LANE_2    0xffffU
61659 #define A_MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3 0x172c
61661 #define S_BIP_ERR_CNT_LANE_3    0
61662 #define M_BIP_ERR_CNT_LANE_3    0xffffU
61666 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
61668 #define S_VLANTAG    0
61669 #define CXGBE_M_VLANTAG    0xffffU
61673 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
61674 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
61675 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
61676 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
61677 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
61678 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
61679 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
61680 #define A_MAC_PORT_MTIP_KR4_LANE_0_MAPPING 0x1a40
61682 #define S_KR4_LANE_0_MAPPING    0
61683 #define M_KR4_LANE_0_MAPPING    0x3U
61687 #define A_MAC_PORT_MTIP_KR4_LANE_1_MAPPING 0x1a44
61689 #define S_KR4_LANE_1_MAPPING    0
61690 #define M_KR4_LANE_1_MAPPING    0x3U
61694 #define A_MAC_PORT_MTIP_KR4_LANE_2_MAPPING 0x1a48
61696 #define S_KR4_LANE_2_MAPPING    0
61697 #define M_KR4_LANE_2_MAPPING    0x3U
61701 #define A_MAC_PORT_MTIP_KR4_LANE_3_MAPPING 0x1a4c
61703 #define S_KR4_LANE_3_MAPPING    0
61704 #define M_KR4_LANE_3_MAPPING    0x3U
61708 #define A_MAC_PORT_MTIP_KR4_SCRATCH 0x1af0
61709 #define A_MAC_PORT_MTIP_KR4_CORE_REVISION 0x1af4
61710 #define A_MAC_PORT_MTIP_KR4_VL_INTVL 0x1af8
61712 #define S_SHRT_MRKR_CNFG    0
61716 #define A_MAC_PORT_MTIP_KR4_TX_LANE_THRESH 0x1afc
61717 #define A_MAC_PORT_MTIP_CR4_CONTROL_1 0x1b00
61718 #define A_MAC_PORT_MTIP_CR4_STATUS_1 0x1b04
61724 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID0 0x1b08
61726 #define S_CR4_DEVICE_ID0    0
61727 #define M_CR4_DEVICE_ID0    0xffffU
61731 #define A_MAC_PORT_MTIP_CR4_DEVICE_ID1 0x1b0c
61733 #define S_CR4_DEVICE_ID1    0
61734 #define M_CR4_DEVICE_ID1    0xffffU
61738 #define A_MAC_PORT_MTIP_CR4_SPEED_ABILITY 0x1b10
61748 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1 0x1b14
61750 #define S_CLAUSE22REG_PRESENT    0
61754 #define A_MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2 0x1b18
61768 #define A_MAC_PORT_MTIP_CR4_CONTROL_2 0x1b1c
61770 #define S_CR4_PCS_TYPE_SELECTION    0
61771 #define M_CR4_PCS_TYPE_SELECTION    0x7U
61775 #define A_MAC_PORT_MTIP_CR4_STATUS_2 0x1b20
61776 #define A_MAC_PORT_MTIP_CR4_PKG_ID0 0x1b38
61777 #define A_MAC_PORT_MTIP_CR4_PKG_ID1 0x1b3c
61778 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_1 0x1b80
61784 #define S_BR_BLOCK_LOCK    0
61788 #define A_MAC_PORT_MTIP_CR4_BASE_R_STATUS_2 0x1b84
61791 #define M_BER_COUNTER    0x3fU
61795 #define S_ERRORED_BLOCKS_CNTR    0
61796 #define M_ERRORED_BLOCKS_CNTR    0xffU
61800 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL 0x1ba8
61806 #define A_MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT 0x1bac
61808 #define S_BASE_R_TEST_ERR_CNT    0
61809 #define M_BASE_R_TEST_ERR_CNT    0xffffU
61813 #define A_MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT 0x1bb0
61815 #define S_BER_HIGH_ORDER_CNT    0
61816 #define M_BER_HIGH_ORDER_CNT    0xffffU
61820 #define A_MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT 0x1bb4
61826 #define S_ERR_BLKS_CNTR    0
61827 #define M_ERR_BLKS_CNTR    0x3fffU
61831 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1 0x1bc8
61865 #define S_LANE_0_BLCK_LCK    0
61869 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2 0x1bcc
61915 #define S_LANE_8_BLCK_LCK    0
61919 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3 0x1bd0
61949 #define S_LANE0_ALGN_MRKR_LCK    0
61953 #define A_MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4 0x1bd4
61999 #define S_LANE8_ALGN_MRKR_LCK    0
62003 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
62022 #define M_PCS_SPEED    0xfU
62026 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
62040 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
62042 #define S_DEVICE_ID0    0
62043 #define M_DEVICE_ID0    0xffffU
62047 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
62049 #define S_DEVICE_ID1    0
62050 #define M_DEVICE_ID1    0xffffU
62054 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
62068 #define S_10G    0
62072 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
62098 #define S_CL22    0
62102 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
62116 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
62118 #define S_PCSTYPE    0
62119 #define M_PCSTYPE    0x7U
62123 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
62157 #define S_10GBASE_R    0
62161 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0 0x1e20
62163 #define S_BIP_ERR_CNTLANE_0    0
62164 #define M_BIP_ERR_CNTLANE_0    0xffffU
62168 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1 0x1e24
62170 #define S_BIP_ERR_CNTLANE_1    0
62171 #define M_BIP_ERR_CNTLANE_1    0xffffU
62175 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2 0x1e28
62177 #define S_BIP_ERR_CNTLANE_2    0
62178 #define M_BIP_ERR_CNTLANE_2    0xffffU
62182 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3 0x1e2c
62184 #define S_BIP_ERR_CNTLANE_3    0
62185 #define M_BIP_ERR_CNTLANE_3    0xffffU
62189 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4 0x1e30
62191 #define S_BIP_ERR_CNTLANE_4    0
62192 #define M_BIP_ERR_CNTLANE_4    0xffffU
62196 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5 0x1e34
62198 #define S_BIP_ERR_CNTLANE_5    0
62199 #define M_BIP_ERR_CNTLANE_5    0xffffU
62203 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
62205 #define S_PKG_ID0    0
62206 #define M_PKG_ID0    0xffffU
62210 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6 0x1e38
62212 #define S_BIP_ERR_CNTLANE_6    0
62213 #define M_BIP_ERR_CNTLANE_6    0xffffU
62217 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
62219 #define S_PKG_ID1    0
62220 #define M_PKG_ID1    0xffffU
62224 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7 0x1e3c
62226 #define S_BIP_ERR_CNTLANE_7    0
62227 #define M_BIP_ERR_CNTLANE_7    0xffffU
62231 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8 0x1e40
62233 #define S_BIP_ERR_CNTLANE_8    0
62234 #define M_BIP_ERR_CNTLANE_8    0xffffU
62238 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9 0x1e44
62240 #define S_BIP_ERR_CNTLANE_9    0
62241 #define M_BIP_ERR_CNTLANE_9    0xffffU
62245 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10 0x1e48
62247 #define S_BIP_ERR_CNTLANE_10    0
62248 #define M_BIP_ERR_CNTLANE_10    0xffffU
62252 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11 0x1e4c
62254 #define S_BIP_ERR_CNTLANE_11    0
62255 #define M_BIP_ERR_CNTLANE_11    0xffffU
62259 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12 0x1e50
62261 #define S_BIP_ERR_CNTLANE_12    0
62262 #define M_BIP_ERR_CNTLANE_12    0xffffU
62266 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13 0x1e54
62268 #define S_BIP_ERR_CNTLANE_13    0
62269 #define M_BIP_ERR_CNTLANE_13    0xffffU
62273 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14 0x1e58
62275 #define S_BIP_ERR_CNTLANE_14    0
62276 #define M_BIP_ERR_CNTLANE_14    0xffffU
62280 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15 0x1e5c
62282 #define S_BIP_ERR_CNTLANE_15    0
62283 #define M_BIP_ERR_CNTLANE_15    0xffffU
62287 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16 0x1e60
62289 #define S_BIP_ERR_CNTLANE_16    0
62290 #define M_BIP_ERR_CNTLANE_16    0xffffU
62294 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17 0x1e64
62296 #define S_BIP_ERR_CNTLANE_17    0
62297 #define M_BIP_ERR_CNTLANE_17    0xffffU
62301 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18 0x1e68
62303 #define S_BIP_ERR_CNTLANE_18    0
62304 #define M_BIP_ERR_CNTLANE_18    0xffffU
62308 #define A_MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19 0x1e6c
62310 #define S_BIP_ERR_CNTLANE_19    0
62311 #define M_BIP_ERR_CNTLANE_19    0xffffU
62315 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
62322 #define M_RESEREVED    0xffU
62338 #define S_BLOCKLOCK    0
62342 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
62353 #define M_HIBERCOUNT    0x3fU
62357 #define S_ERRBLKCNT    0
62358 #define M_ERRBLKCNT    0xffU
62362 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
62364 #define S_SEEDA    0
62365 #define M_SEEDA    0xffffU
62369 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
62371 #define S_SEEDA1    0
62372 #define M_SEEDA1    0xffffU
62376 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
62378 #define S_SEEDA2    0
62379 #define M_SEEDA2    0xffffU
62383 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
62385 #define S_SEEDA3    0
62386 #define M_SEEDA3    0x3ffU
62390 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
62392 #define S_SEEDB    0
62393 #define M_SEEDB    0xffffU
62397 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
62399 #define S_SEEDB1    0
62400 #define M_SEEDB1    0xffffU
62404 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
62406 #define S_SEEDB2    0
62407 #define M_SEEDB2    0xffffU
62411 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
62413 #define S_SEEDB3    0
62414 #define M_SEEDB3    0x3ffU
62418 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
62444 #define S_DATAPATSEL    0
62448 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
62450 #define S_TEST_ERR_CNT    0
62451 #define M_TEST_ERR_CNT    0xffffU
62455 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
62457 #define S_BER_CNT_HI    0
62458 #define M_BER_CNT_HI    0xffffU
62462 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
62468 #define S_BLOCK_CNT_HI    0
62469 #define M_BLOCK_CNT_HI    0x3fffU
62473 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
62507 #define S_LANE0    0
62511 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
62557 #define S_LANE8    0
62561 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
62591 #define S_AMLOCK0    0
62595 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
62641 #define S_AMLOCK8    0
62645 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
62647 #define S_BIPERR_CNT    0
62648 #define M_BIPERR_CNT    0xffffU
62652 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
62653 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
62654 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
62655 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
62656 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
62657 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
62658 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
62659 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
62660 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
62661 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
62662 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
62663 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
62664 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
62665 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
62666 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
62667 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
62668 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
62669 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
62670 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
62671 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
62673 #define S_MAP    0
62674 #define M_MAP    0x1fU
62678 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
62679 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
62680 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
62681 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
62682 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
62683 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
62684 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
62685 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
62686 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
62687 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
62688 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
62689 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
62690 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
62691 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
62692 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
62693 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
62694 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
62695 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
62696 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
62697 #define A_MAC_PORT_MTIP_CR4_LANE_0_MAPPING 0x2140
62699 #define S_LANE_0_MAPPING    0
62700 #define M_LANE_0_MAPPING    0x3fU
62704 #define A_MAC_PORT_MTIP_CR4_LANE_1_MAPPING 0x2144
62706 #define S_LANE_1_MAPPING    0
62707 #define M_LANE_1_MAPPING    0x3fU
62711 #define A_MAC_PORT_MTIP_CR4_LANE_2_MAPPING 0x2148
62713 #define S_LANE_2_MAPPING    0
62714 #define M_LANE_2_MAPPING    0x3fU
62718 #define A_MAC_PORT_MTIP_CR4_LANE_3_MAPPING 0x214c
62720 #define S_LANE_3_MAPPING    0
62721 #define M_LANE_3_MAPPING    0x3fU
62725 #define A_MAC_PORT_MTIP_CR4_LANE_4_MAPPING 0x2150
62727 #define S_LANE_4_MAPPING    0
62728 #define M_LANE_4_MAPPING    0x3fU
62732 #define A_MAC_PORT_MTIP_CR4_LANE_5_MAPPING 0x2154
62734 #define S_LANE_5_MAPPING    0
62735 #define M_LANE_5_MAPPING    0x3fU
62739 #define A_MAC_PORT_MTIP_CR4_LANE_6_MAPPING 0x2158
62741 #define S_LANE_6_MAPPING    0
62742 #define M_LANE_6_MAPPING    0x3fU
62746 #define A_MAC_PORT_MTIP_CR4_LANE_7_MAPPING 0x215c
62748 #define S_LANE_7_MAPPING    0
62749 #define M_LANE_7_MAPPING    0x3fU
62753 #define A_MAC_PORT_MTIP_CR4_LANE_8_MAPPING 0x2160
62755 #define S_LANE_8_MAPPING    0
62756 #define M_LANE_8_MAPPING    0x3fU
62760 #define A_MAC_PORT_MTIP_CR4_LANE_9_MAPPING 0x2164
62762 #define S_LANE_9_MAPPING    0
62763 #define M_LANE_9_MAPPING    0x3fU
62767 #define A_MAC_PORT_MTIP_CR4_LANE_10_MAPPING 0x2168
62769 #define S_LANE_10_MAPPING    0
62770 #define M_LANE_10_MAPPING    0x3fU
62774 #define A_MAC_PORT_MTIP_CR4_LANE_11_MAPPING 0x216c
62776 #define S_LANE_11_MAPPING    0
62777 #define M_LANE_11_MAPPING    0x3fU
62781 #define A_MAC_PORT_MTIP_CR4_LANE_12_MAPPING 0x2170
62783 #define S_LANE_12_MAPPING    0
62784 #define M_LANE_12_MAPPING    0x3fU
62788 #define A_MAC_PORT_MTIP_CR4_LANE_13_MAPPING 0x2174
62790 #define S_LANE_13_MAPPING    0
62791 #define M_LANE_13_MAPPING    0x3fU
62795 #define A_MAC_PORT_MTIP_CR4_LANE_14_MAPPING 0x2178
62797 #define S_LANE_14_MAPPING    0
62798 #define M_LANE_14_MAPPING    0x3fU
62802 #define A_MAC_PORT_MTIP_CR4_LANE_15_MAPPING 0x217c
62804 #define S_LANE_15_MAPPING    0
62805 #define M_LANE_15_MAPPING    0x3fU
62809 #define A_MAC_PORT_MTIP_CR4_LANE_16_MAPPING 0x2180
62811 #define S_LANE_16_MAPPING    0
62812 #define M_LANE_16_MAPPING    0x3fU
62816 #define A_MAC_PORT_MTIP_CR4_LANE_17_MAPPING 0x2184
62818 #define S_LANE_17_MAPPING    0
62819 #define M_LANE_17_MAPPING    0x3fU
62823 #define A_MAC_PORT_MTIP_CR4_LANE_18_MAPPING 0x2188
62825 #define S_LANE_18_MAPPING    0
62826 #define M_LANE_18_MAPPING    0x3fU
62830 #define A_MAC_PORT_MTIP_CR4_LANE_19_MAPPING 0x218c
62832 #define S_LANE_19_MAPPING    0
62833 #define M_LANE_19_MAPPING    0x3fU
62837 #define A_MAC_PORT_MTIP_CR4_SCRATCH 0x21f0
62838 #define A_MAC_PORT_MTIP_CR4_CORE_REVISION 0x21f4
62840 #define S_CORE_REVISION    0
62841 #define M_CORE_REVISION    0xffffU
62845 #define A_MAC_PORT_BEAN_CTL 0x2200
62863 #define A_MAC_PORT_MTIP_RS_FEC_CONTROL 0x2200
62869 #define S_RS_FEC_BYPASS_CORRECTION    0
62873 #define A_MAC_PORT_BEAN_STATUS 0x2204
62899 #define S_LP_BEAN_ABILITY    0
62903 #define A_MAC_PORT_MTIP_RS_FEC_STATUS 0x2204
62921 #define S_RS_FEC_BYPASS_CORRECTION_ABILITY    0
62925 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
62936 #define M_PAUSE_ABILITY    0x7U
62941 #define M_ECHO_NONCE    0x1fU
62945 #define S_SELECTOR    0
62946 #define M_SELECTOR    0x1fU
62950 #define A_MAC_PORT_MTIP_RS_FEC_CCW_LO 0x2208
62952 #define S_RS_RS_FEC_CCW_LO    0
62953 #define M_RS_RS_FEC_CCW_LO    0xffffU
62957 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
62960 #define M_TECH_ABILITY_1    0x7ffU
62964 #define S_TX_NONCE    0
62965 #define M_TX_NONCE    0x1fU
62969 #define A_MAC_PORT_MTIP_RS_FEC_CCW_HI 0x220c
62971 #define S_RS_RS_FEC_CCW_HI    0
62972 #define M_RS_RS_FEC_CCW_HI    0xffffU
62976 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
62979 #define M_T5_FEC_ABILITY    0x3U
62983 #define S_TECH_ABILITY_2    0
62984 #define M_TECH_ABILITY_2    0x3fffU
62988 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_LO 0x2210
62990 #define S_RS_RS_FEC_NCCW_LO    0
62991 #define M_RS_RS_FEC_NCCW_LO    0xffffU
62995 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
62996 #define A_MAC_PORT_MTIP_RS_FEC_NCCW_HI 0x2214
62998 #define S_RS_RS_FEC_NCCW_HI    0
62999 #define M_RS_RS_FEC_NCCW_HI    0xffffU
63003 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
63004 #define A_MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI 0x2218
63006 #define S_PMA_MAPPING    0
63007 #define M_PMA_MAPPING    0xffU
63011 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
63012 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
63014 #define S_MS_COUNT    0
63015 #define M_MS_COUNT    0xffffU
63019 #define A_MAC_PORT_BEAN_XNP_0 0x2224
63037 #define S_MU    0
63038 #define M_MU    0x7ffU
63042 #define A_MAC_PORT_BEAN_XNP_1 0x2228
63044 #define S_UNFORMATED    0
63045 #define M_UNFORMATED    0xffffU
63049 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO 0x2228
63051 #define S_RS_FEC_SYMBLERR0_LO    0
63055 #define A_MAC_PORT_BEAN_XNP_2 0x222c
63056 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI 0x222c
63058 #define S_RS_FEC_SYMBLERR0_HI    0
63062 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
63063 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO 0x2230
63065 #define S_RS_FEC_SYMBLERR1_LO    0
63069 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
63070 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI 0x2234
63072 #define S_RS_FEC_SYMBLERR1_HI    0
63076 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
63077 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO 0x2238
63079 #define S_RS_FEC_SYMBLERR2_LO    0
63083 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
63113 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI 0x223c
63115 #define S_RS_FEC_SYMBLERR2_HI    0
63119 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
63120 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO 0x2240
63122 #define S_RS_FEC_SYMBLERR3_LO    0
63126 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
63127 #define A_MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI 0x2244
63129 #define S_RS_FEC_SYMBLERR3_HI    0
63133 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
63134 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
63135 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
63136 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
63137 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
63138 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
63139 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
63140 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
63141 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
63142 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
63143 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
63144 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
63145 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
63146 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
63147 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
63148 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
63149 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
63150 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
63151 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
63152 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
63153 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
63154 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
63155 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
63156 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
63157 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
63158 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
63159 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
63160 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
63161 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
63162 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
63163 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
63164 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
63165 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
63166 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
63167 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
63168 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
63169 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
63170 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
63171 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
63172 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
63173 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
63174 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
63175 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
63176 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
63177 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
63178 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
63179 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL 0x2400
63189 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1 0x2404
63192 #define M_DESKEW_EMPTY    0xfU
63224 #define S_AMPS_LOCK    0
63225 #define M_AMPS_LOCK    0xfU
63229 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2 0x2408
63230 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION 0x240c
63232 #define S_RS_FEC_VENDOR_REVISION    0
63233 #define M_RS_FEC_VENDOR_REVISION    0xffffU
63237 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY 0x2410
63239 #define S_RS_FEC_VENDOR_TX_TEST_KEY    0
63240 #define M_RS_FEC_VENDOR_TX_TEST_KEY    0xffffU
63244 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS 0x2414
63246 #define S_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0
63247 #define M_RS_FEC_VENDOR_TX_TEST_SYMBOLS    0xffffU
63251 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN 0x2418
63253 #define S_RS_FEC_VENDOR_TX_TEST_PATTERN    0
63254 #define M_RS_FEC_VENDOR_TX_TEST_PATTERN    0xffffU
63258 #define A_MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER 0x241c
63260 #define S_RS_FEC_VENDOR_TX_TEST_TRIGGER    0
63261 #define M_RS_FEC_VENDOR_TX_TEST_TRIGGER    0xffffU
63265 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
63271 #define S_RESTART_TR    0
63275 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
63289 #define S_RX_STATUS    0
63293 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
63304 #define M_CP1_UPD    0x3U
63309 #define M_C0_UPD    0x3U
63313 #define S_CN1_UPD    0
63314 #define M_CN1_UPD    0x3U
63318 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
63325 #define M_CP1_STAT    0x3U
63330 #define M_C0_STAT    0x3U
63334 #define S_CN1_STAT    0
63335 #define M_CN1_STAT    0x3U
63339 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
63340 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
63341 #define A_MAC_PORT_FEC_ABILITY 0x2618
63347 #define S_ABILITY    0
63351 #define A_MAC_PORT_MTIP_FEC_ABILITY 0x2618
63357 #define S_BASE_R_FEC_ABILITY    0
63361 #define A_MAC_PORT_FEC_CONTROL 0x261c
63367 #define S_FEC_EN    0
63371 #define A_MAC_PORT_FEC_STATUS 0x2620
63377 #define S_FEC_LOCKED    0
63382 #define M_FEC_LOCKED0    0xfU
63386 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
63388 #define S_FEC_CERR_CNT_0    0
63389 #define M_FEC_CERR_CNT_0    0xffffU
63393 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_0 0x2624
63394 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
63396 #define S_FEC_CERR_CNT_1    0
63397 #define M_FEC_CERR_CNT_1    0xffffU
63401 #define A_MAC_PORT_MTIP_FEC0_CERR_CNT_1 0x2628
63402 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
63404 #define S_FEC_NCERR_CNT_0    0
63405 #define M_FEC_NCERR_CNT_0    0xffffU
63409 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_0 0x262c
63411 #define S_FEC0_NCERR_CNT_0    0
63412 #define M_FEC0_NCERR_CNT_0    0xffffU
63416 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
63418 #define S_FEC_NCERR_CNT_1    0
63419 #define M_FEC_NCERR_CNT_1    0xffffU
63423 #define A_MAC_PORT_MTIP_FEC0_NCERR_CNT_1 0x2630
63425 #define S_FEC0_NCERR_CNT_1    0
63426 #define M_FEC0_NCERR_CNT_1    0xffffU
63430 #define A_MAC_PORT_MTIP_FEC_STATUS1 0x2664
63431 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_0 0x2668
63432 #define A_MAC_PORT_MTIP_FEC1_CERR_CNT_1 0x266c
63433 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_0 0x2670
63434 #define A_MAC_PORT_MTIP_FEC1_NCERR_CNT_1 0x2674
63435 #define A_MAC_PORT_MTIP_FEC_STATUS2 0x26a8
63436 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_0 0x26ac
63437 #define A_MAC_PORT_MTIP_FEC2_CERR_CNT_1 0x26b0
63438 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_0 0x26b4
63439 #define A_MAC_PORT_MTIP_FEC2_NCERR_CNT_1 0x26b8
63440 #define A_MAC_PORT_MTIP_FEC_STATUS3 0x26ec
63441 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_0 0x26f0
63442 #define A_MAC_PORT_MTIP_FEC3_CERR_CNT_1 0x26f4
63443 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_0 0x26f8
63444 #define A_MAC_PORT_MTIP_FEC3_NCERR_CNT_1 0x26fc
63445 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
63448 #define M_T5_RXREQ_C2    0x3U
63453 #define M_T5_RXREQ_C1    0x3U
63457 #define S_T5_RXREQ_C0    0
63458 #define M_T5_RXREQ_C0    0x3U
63463 #define M_T5_RXREQ_C3    0x3U
63467 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
63474 #define M_T5_AE0_RXSTAT_C2    0x3U
63479 #define M_T5_AE0_RXSTAT_C1    0x3U
63483 #define S_T5_AE0_RXSTAT_C0    0
63484 #define M_T5_AE0_RXSTAT_C0    0x3U
63501 #define M_T5_AE0_RXSTAT_C3    0x3U
63505 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
63508 #define M_T5_TXREQ_C2    0x3U
63513 #define M_T5_TXREQ_C1    0x3U
63517 #define S_T5_TXREQ_C0    0
63518 #define M_T5_TXREQ_C0    0x3U
63527 #define M_T5_TXREQ_C3    0x3U
63531 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
63534 #define M_T5_TXSTAT_C2    0x3U
63539 #define M_T5_TXSTAT_C1    0x3U
63543 #define S_T5_TXSTAT_C0    0
63544 #define M_T5_TXSTAT_C0    0x3U
63549 #define M_T5_TXSTAT_C3    0x3U
63553 #define A_MAC_PORT_AE_REG_MODE 0x2a10
63564 #define M_SET_WAIT_TIMER    0x3U
63588 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
63589 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
63595 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
63596 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
63597 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
63604 #define M_T5_AE1_RXSTAT_C2    0x3U
63609 #define M_T5_AE1_RXSTAT_C1    0x3U
63613 #define S_T5_AE1_RXSTAT_C0    0
63614 #define M_T5_AE1_RXSTAT_C0    0x3U
63631 #define M_T5_AE1_RXSTAT_C3    0x3U
63635 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
63636 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
63637 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
63638 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
63639 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
63640 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
63641 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
63642 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
63649 #define M_T5_AE2_RXSTAT_C2    0x3U
63654 #define M_T5_AE2_RXSTAT_C1    0x3U
63658 #define S_T5_AE2_RXSTAT_C0    0
63659 #define M_T5_AE2_RXSTAT_C0    0x3U
63676 #define M_T5_AE2_RXSTAT_C3    0x3U
63680 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
63681 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
63682 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
63683 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
63684 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
63685 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
63686 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
63687 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
63694 #define M_T5_AE3_RXSTAT_C2    0x3U
63699 #define M_T5_AE3_RXSTAT_C1    0x3U
63703 #define S_T5_AE3_RXSTAT_C0    0
63704 #define M_T5_AE3_RXSTAT_C0    0x3U
63721 #define M_T5_AE3_RXSTAT_C3    0x3U
63725 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
63726 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
63727 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
63728 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
63729 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
63730 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
63731 #define A_MAC_PORT_AE_TX_DIS 0x2a80
63732 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
63733 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
63734 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
63735 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
63736 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
63737 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
63738 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
63739 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
63740 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
63741 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
63742 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
63743 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
63744 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
63745 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
63746 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
63747 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
63754 #define M_INIT_METH    0x3U
63759 #define M_CE_DECS    0xfU
63783 #define S_H1TEQ_GOAL    0
63784 #define M_H1TEQ_GOAL    0x7U
63789 #define M_T6_INIT_METH    0xfU
63794 #define M_INIT_CNT    0xfU
63802 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
63805 #define M_GAIN_TH    0x1fU
63817 #define S_AMIN_TH    0
63818 #define M_AMIN_TH    0xfU
63831 #define M_DPC_METH    0x3U
63839 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
63842 #define M_ACC_LIM    0xfU
63847 #define M_CNV_LIM    0xfU
63851 #define S_TOG_LIM    0
63852 #define M_TOG_LIM    0xfU
63856 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
63859 #define M_BOOT_LUT7    0xfU
63864 #define M_BOOT_LUT6    0xfU
63869 #define M_BOOT_LUT45    0xfU
63874 #define M_BOOT_LUT0123    0x3U
63883 #define M_BOOT_LUT5    0xfU
63887 #define A_MAC_PORT_AET_STATUS_0 0x2b10
63890 #define M_AET_STAT    0xfU
63895 #define M_NEU_STATE    0xfU
63899 #define S_CTRL_STATE    0
63900 #define M_CTRL_STATE    0x1fU
63905 #define M_CTRL_STAT    0x1fU
63910 #define M_T6_NEU_STATE    0xfU
63914 #define S_T6_CTRL_STATE    0
63915 #define M_T6_CTRL_STATE    0xfU
63919 #define A_MAC_PORT_AET_STATUS_20 0x2b14
63921 #define S_FRAME_LOCK_CNT    0
63922 #define M_FRAME_LOCK_CNT    0x7U
63926 #define A_MAC_PORT_AET_LIMITS0 0x2b18
63928 #define S_DPC_TIME_LIM    0
63929 #define M_DPC_TIME_LIM    0x3U
63933 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
63934 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
63935 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
63936 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
63937 #define A_MAC_PORT_AET_STATUS_1 0x2b30
63938 #define A_MAC_PORT_AET_STATUS_21 0x2b34
63939 #define A_MAC_PORT_AET_LIMITS1 0x2b38
63940 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
63941 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
63942 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
63943 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
63944 #define A_MAC_PORT_AET_STATUS_2 0x2b50
63945 #define A_MAC_PORT_AET_STATUS_22 0x2b54
63946 #define A_MAC_PORT_AET_LIMITS2 0x2b58
63947 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
63948 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
63949 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
63950 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
63951 #define A_MAC_PORT_AET_STATUS_3 0x2b70
63952 #define A_MAC_PORT_AET_STATUS_23 0x2b74
63953 #define A_MAC_PORT_AET_LIMITS3 0x2b78
63954 #define A_T6_MAC_PORT_BEAN_CTL 0x2c00
63955 #define A_T6_MAC_PORT_BEAN_STATUS 0x2c04
63956 #define A_T6_MAC_PORT_BEAN_ABILITY_0 0x2c08
63962 #define A_T6_MAC_PORT_BEAN_ABILITY_1 0x2c0c
63963 #define A_T6_MAC_PORT_BEAN_ABILITY_2 0x2c10
63964 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_0 0x2c14
63970 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_1 0x2c18
63971 #define A_T6_MAC_PORT_BEAN_REM_ABILITY_2 0x2c1c
63972 #define A_T6_MAC_PORT_BEAN_MS_COUNT 0x2c20
63973 #define A_T6_MAC_PORT_BEAN_XNP_0 0x2c24
63974 #define A_T6_MAC_PORT_BEAN_XNP_1 0x2c28
63975 #define A_T6_MAC_PORT_BEAN_XNP_2 0x2c2c
63976 #define A_T6_MAC_PORT_LP_BEAN_XNP_0 0x2c30
63977 #define A_T6_MAC_PORT_LP_BEAN_XNP_1 0x2c34
63978 #define A_T6_MAC_PORT_LP_BEAN_XNP_2 0x2c38
63979 #define A_T6_MAC_PORT_BEAN_ETH_STATUS 0x2c3c
63993 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
64008 #define M_T5_TX_CFGPTR    0x3U
64025 #define M_T5_TX_PLLSEL    0x3U
64045 #define S_T5_TX_RTSEL    0
64046 #define M_T5_TX_RTSEL    0x3U
64059 #define M_T6_T5_TX_BWSEL    0x3U
64063 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
64066 #define M_SPSEL    0x7U
64094 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
64116 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
64127 #define M_T5SLEW    0x3U
64131 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
64149 #define S_T5REGAMP    0
64150 #define M_T5REGAMP    0x3U
64154 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
64165 #define M_RPOS    0x3fU
64173 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
64176 #define M_CALSSTN    0x7U
64180 #define S_CALSSTP    0
64181 #define M_CALSSTP    0x7U
64186 #define M_T6_CALSSTN    0x3fU
64190 #define S_T6_CALSSTP    0
64191 #define M_T6_CALSSTP    0x3fU
64195 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
64197 #define S_DRTOL    0
64198 #define M_DRTOL    0x1fU
64203 #define M_T6_DRTOL    0x7U
64207 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
64209 #define S_T5NXTT0    0
64210 #define M_T5NXTT0    0x1fU
64214 #define S_T6_NXTT0    0
64215 #define M_T6_NXTT0    0x3fU
64219 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
64221 #define S_T5NXTT1    0
64222 #define M_T5NXTT1    0x3fU
64226 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
64228 #define S_T5NXTT2    0
64229 #define M_T5NXTT2    0x3fU
64233 #define S_T6_NXTT2    0
64234 #define M_T6_NXTT2    0x3fU
64238 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT 0x302c
64240 #define S_NXTT3    0
64241 #define M_NXTT3    0x3fU
64245 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
64247 #define S_T5TXPWR    0
64248 #define M_T5TXPWR    0x3fU
64252 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
64254 #define S_NXTPOL    0
64255 #define M_NXTPOL    0x7U
64259 #define S_T6_NXTPOL    0
64260 #define M_T6_NXTPOL    0xfU
64264 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
64275 #define M_SASCMD    0x3U
64280 #define M_T6_C0UPDT    0x3U
64285 #define M_C3UPDT    0x3U
64290 #define M_T6_C2UPDT    0x3U
64294 #define S_T6_C1UPDT    0
64295 #define M_T6_C1UPDT    0x3U
64299 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
64302 #define M_T6_C0STAT    0x3U
64307 #define M_C3STAT    0x3U
64312 #define M_T6_C2STAT    0x3U
64316 #define S_T6_C1STAT    0
64317 #define M_T6_C1STAT    0x3U
64321 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
64322 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3040
64324 #define S_AETAP0    0
64325 #define M_AETAP0    0x7fU
64329 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
64331 #define S_T5NIDAC1    0
64332 #define M_T5NIDAC1    0x3fU
64336 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3044
64338 #define S_AETAP1    0
64339 #define M_AETAP1    0x7fU
64343 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
64345 #define S_T5NIDAC2    0
64346 #define M_T5NIDAC2    0x3fU
64350 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3048
64352 #define S_AETAP2    0
64353 #define M_AETAP2    0x7fU
64357 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x304c
64359 #define S_AETAP3    0
64360 #define M_AETAP3    0x7fU
64364 #define A_MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER 0x3050
64367 #define M_ATUNEN    0xffU
64371 #define S_ATUNEP    0
64372 #define M_ATUNEP    0xffU
64376 #define A_MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3058
64382 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
64383 #define A_MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED 0x3060
64386 #define M_AS4X7    0x3U
64391 #define M_AS4X6    0x3U
64396 #define M_AS4X5    0x3U
64401 #define M_AS4X4    0x3U
64406 #define M_AS4X3    0x3U
64411 #define M_AS4X2    0x3U
64416 #define M_AS4X1    0x3U
64420 #define S_AS4X0    0
64421 #define M_AS4X0    0x3U
64425 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
64427 #define S_T5AIDAC1    0
64428 #define M_T5AIDAC1    0x3fU
64432 #define A_MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED 0x3064
64435 #define M_AS2X3    0x3U
64440 #define M_AS2X2    0x3U
64445 #define M_AS2X1    0x3U
64449 #define S_AS2X0    0
64450 #define M_AS2X0    0x3U
64454 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
64455 #define A_MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED 0x3068
64458 #define M_AS1X7    0x3U
64463 #define M_AS1X6    0x3U
64468 #define M_AS1X5    0x3U
64473 #define M_AS1X4    0x3U
64478 #define M_AS1X3    0x3U
64483 #define M_AS1X2    0x3U
64488 #define M_AS1X1    0x3U
64492 #define S_AS1X0    0
64493 #define M_AS1X0    0x3U
64497 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x306c
64499 #define S_AT4X    0
64500 #define M_AT4X    0xffU
64504 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
64507 #define M_MAINSC    0x3fU
64511 #define S_POSTSC    0
64512 #define M_POSTSC    0x3fU
64516 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3070
64519 #define M_AT2X    0xfU
64523 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
64525 #define S_PRESC    0
64526 #define M_PRESC    0x1fU
64530 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3074
64532 #define S_ATSIGN    0
64533 #define M_ATSIGN    0xfU
64537 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
64538 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
64541 #define M_T5XADDR    0x1fU
64545 #define S_T5XWR    0
64550 #define M_T6_XADDR    0x1fU
64554 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
64556 #define S_XDAT10    0
64557 #define M_XDAT10    0xffffU
64561 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
64563 #define S_XDAT32    0
64564 #define M_XDAT32    0xffffU
64568 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
64570 #define S_XDAT4    0
64571 #define M_XDAT4    0xffU
64575 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3088
64577 #define S_XDAT54    0
64578 #define M_XDAT54    0xffffU
64582 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
64597 #define M_DCCOFFSET    0x1fU
64602 #define M_DCCSTEP    0x3U
64607 #define M_DCCASTEP    0x1fU
64611 #define S_DCCAEN    0
64615 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x308c
64617 #define S_XDAT76    0
64618 #define M_XDAT76    0xffffU
64622 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
64637 #define M_DCCSIGN    0x3U
64642 #define M_DCCAMP    0x7fU
64646 #define S_DCCOEN    0
64650 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
64653 #define M_DCCASIGN    0x3U
64657 #define S_DCCAAMP    0
64658 #define M_DCCAAMP    0x7fU
64662 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
64664 #define S_DCCTIMEOUTVAL    0
64665 #define M_DCCTIMEOUTVAL    0xffffU
64669 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
64676 #define M_LPITERM    0x3U
64680 #define S_LPIPRCD    0
64681 #define M_LPIPRCD    0x3U
64685 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x30a0
64688 #define M_T6_DCCTIMEEN    0x3U
64693 #define M_T6_DCCLOCK    0x3U
64698 #define M_T6_DCCOFFSET    0x7U
64703 #define M_TX_LINKA_DCCSTEP_CTL    0x3U
64707 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x30a4
64708 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x30a8
64709 #define A_T6_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x30ac
64710 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE 0x30c0
64712 #define S_OSIGN    0
64713 #define M_OSIGN    0xfU
64717 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE 0x30c8
64720 #define M_OS4X7    0x3U
64725 #define M_OS4X6    0x3U
64730 #define M_OS4X5    0x3U
64735 #define M_OS4X4    0x3U
64740 #define M_OS4X3    0x3U
64745 #define M_OS4X2    0x3U
64750 #define M_OS4X1    0x3U
64754 #define S_OS4X0    0
64755 #define M_OS4X0    0x3U
64759 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE 0x30cc
64762 #define M_OS2X3    0x3U
64767 #define M_OS2X2    0x3U
64772 #define M_OS2X1    0x3U
64776 #define S_OS2X0    0
64777 #define M_OS2X0    0x3U
64781 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE 0x30d0
64784 #define M_OS1X7    0x3U
64789 #define M_OS1X6    0x3U
64794 #define M_OS1X5    0x3U
64799 #define M_OS1X4    0x3U
64804 #define M_OS1X3    0x3U
64809 #define M_OS1X2    0x3U
64814 #define M_OS1X1    0x3U
64818 #define S_OS1X0    0
64819 #define M_OS1X0    0x3U
64823 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x30d8
64825 #define S_OT4X    0
64826 #define M_OT4X    0xffU
64830 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x30dc
64832 #define S_OT2X    0
64833 #define M_OT2X    0xfU
64837 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x30e0
64839 #define S_OT1X    0
64840 #define M_OT1X    0xffU
64844 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5 0x30ec
64859 #define M_TUNEBIT    0x7U
64864 #define M_DATAPOS    0x3U
64869 #define M_SEGSEL    0x1fU
64874 #define M_TAPSEL    0x3U
64878 #define S_DATASIGN    0
64882 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
64888 #define S_SDOVRD    0
64889 #define M_SDOVRD    0xffU
64893 #define S_T6_SDOVRD    0
64894 #define M_T6_SDOVRD    0xffffU
64898 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
64901 #define M_SLEWCODE    0x3U
64905 #define S_ASEGEN    0
64909 #define S_WCNT    0
64910 #define M_WCNT    0x3ffU
64914 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
64921 #define M_AECMD1312    0x3U
64925 #define S_AECMD70    0
64926 #define M_AECMD70    0xffU
64930 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
64933 #define M_C48DIVCTL    0x7U
64938 #define M_RATEDIVCTL    0x7U
64959 #define M_JTAGAMPL    0x3U
64971 #define S_OBS    0
64987 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
64988 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
64989 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
64990 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
64991 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
64992 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
64993 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
64994 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
64995 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
64996 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
64997 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
64998 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT 0x312c
64999 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
65000 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
65001 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
65002 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
65003 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
65004 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3140
65005 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
65006 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3144
65007 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
65008 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3148
65009 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x314c
65010 #define A_MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER 0x3150
65011 #define A_MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3158
65012 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
65013 #define A_MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED 0x3160
65014 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
65015 #define A_MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED 0x3164
65016 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
65017 #define A_MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED 0x3168
65018 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x316c
65019 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
65020 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3170
65021 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
65022 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3174
65023 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
65024 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
65025 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
65026 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
65027 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
65028 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3188
65029 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
65030 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x318c
65031 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
65032 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
65033 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
65034 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
65035 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x31a0
65038 #define M_TX_LINKB_DCCSTEP_CTL    0x3U
65042 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x31a4
65043 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x31a8
65044 #define A_T6_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x31ac
65045 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE 0x31c0
65046 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE 0x31c8
65047 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE 0x31cc
65048 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE 0x31d0
65049 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x31d8
65050 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x31dc
65051 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x31e0
65052 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5 0x31ec
65053 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
65054 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
65055 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
65056 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
65057 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
65072 #define M_T5_RX_CFGPTR    0x3U
65089 #define M_T5_RX_PLLSEL    0x3U
65094 #define M_T5_RX_DMSEL    0x3U
65099 #define M_T5_RX_BWSEL    0x3U
65103 #define S_T5_RX_RTSEL    0
65104 #define M_T5_RX_RTSEL    0x3U
65112 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
65138 #define S_PATSEL    0
65139 #define M_PATSEL    0x7U
65148 #define M_PPOL    0x3U
65153 #define M_PCLKSEL    0x3U
65157 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
65171 #define S_SSCEN    0
65175 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
65178 #define M_H1ANOFST    0xfU
65183 #define M_T6_TMSCAL    0x3U
65195 #define S_T6_PHOFFS    0
65196 #define M_T6_PHOFFS    0x3fU
65200 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
65202 #define S_ROT00    0
65203 #define M_ROT00    0x3fU
65208 #define M_ROTA    0x3fU
65212 #define S_ROTD    0
65213 #define M_ROTD    0x3fU
65217 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
65220 #define M_FREQFW    0xffU
65228 #define S_ROTE    0
65229 #define M_ROTE    0x3fU
65233 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
65236 #define M_RAOFFF    0xfU
65240 #define S_RAOFF    0
65241 #define M_RAOFF    0x1fU
65245 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
65248 #define M_RBOOFF    0x1fU
65253 #define M_RBEOFF    0x1fU
65257 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
65260 #define M_T6_SPIFMT    0xfU
65264 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
65267 #define M_T5BYTE1    0xffU
65271 #define S_T5BYTE0    0
65272 #define M_T5BYTE0    0xffU
65276 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
65279 #define M_T5_RX_SMODE    0x7U
65292 #define M_T5_RX_ASAMPQ    0x7U
65296 #define S_T5_RX_ASAMP    0
65297 #define M_T5_RX_ASAMP    0x7U
65306 #define M_RASEL    0x7U
65310 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
65321 #define M_T6_PEAK    0x1fU
65325 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
65331 #define S_T5VGAIN    0
65332 #define M_T5VGAIN    0x1fU
65349 #define M_FH1AFLTR    0x3U
65354 #define M_WGAIN    0x3U
65362 #define S_T6_T5VGAIN    0
65363 #define M_T6_T5VGAIN    0x7fU
65367 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
65368 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
65371 #define M_IQSEP    0x1fU
65376 #define M_DUTYQ    0x1fU
65380 #define S_DUTYI    0
65381 #define M_DUTYI    0x1fU
65385 #define A_MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3238
65388 #define M_PMCFG    0x3U
65392 #define S_PMOFFTIME    0
65393 #define M_PMOFFTIME    0x3fU
65397 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1 0x323c
65404 #define M_SERVREF    0x7U
65408 #define S_IQAMP    0
65409 #define M_IQAMP    0x1fU
65413 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
65416 #define M_DTHR    0x3fU
65420 #define S_SNUL    0
65421 #define M_SNUL    0x1fU
65425 #define A_MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2 0x3240
65426 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3244
65452 #define S_DASEL    0
65453 #define M_DASEL    0x7U
65457 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
65458 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
65459 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN 0x324c
65460 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
65471 #define M_ADAC2    0xffU
65475 #define S_ADAC1    0
65476 #define M_ADAC1    0xffU
65480 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL 0x3254
65487 #define M_ACCPLGAIN    0x7U
65492 #define M_ACCPLREF    0x3U
65497 #define M_ACCPLSTEP    0x3U
65502 #define M_ACCPLASTEP    0x1fU
65506 #define S_FACCPL    0
65510 #define A_MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE 0x3258
65520 #define S_ACCPLBIAS    0
65521 #define M_ACCPLBIAS    0xffU
65525 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
65528 #define M_H1O2    0x3fU
65532 #define S_H1E2    0
65533 #define M_H1E2    0x3fU
65537 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET 0x325c
65539 #define S_H123CH    0
65540 #define M_H123CH    0x3fU
65544 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
65547 #define M_H1O3    0x3fU
65551 #define S_H1E3    0
65552 #define M_H1E3    0x3fU
65556 #define A_MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3260
65559 #define M_H1OX    0x3fU
65563 #define S_H1EX    0
65564 #define M_H1EX    0x3fU
65568 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
65571 #define M_H1O4    0x3fU
65575 #define S_H1E4    0
65576 #define M_H1E4    0x3fU
65580 #define A_MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR 0x3264
65587 #define M_UNPKPKA    0x3fU
65591 #define S_UNPKVGA    0
65592 #define M_UNPKVGA    0x3U
65596 #define A_MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH 0x3268
65607 #define M_OVRTAILS    0x3U
65612 #define M_OVRTAILV    0x7U
65632 #define S_CDRANLGSW    0
65633 #define M_CDRANLGSW    0x3U
65637 #define A_MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x326c
65640 #define M_PFLAG    0x3U
65644 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
65670 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
65676 #define S_T6_ODEC    0
65677 #define M_T6_ODEC    0xfU
65681 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
65735 #define S_T5OCCMP    0
65751 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
65757 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
65795 #define S_FDQCC    0
65831 #define S_FQCC    0
65835 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
65842 #define M_LOFE2S_READONLY    0x3U
65847 #define M_LOFE2    0x3fU
65859 #define S_LOFE1    0
65860 #define M_LOFE1    0x3fU
65864 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL 0x3284
65871 #define M_DCDIND    0x7U
65876 #define M_DCCIND    0x3U
65884 #define S_LOFCH    0
65885 #define M_LOFCH    0x1fU
65889 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
65900 #define M_LOFO2    0x3fU
65912 #define S_LOFO1    0
65913 #define M_LOFO1    0x3fU
65917 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE 0x3288
65920 #define M_LOFU    0x7fU
65924 #define S_LOFL    0
65925 #define M_LOFL    0x7fU
65929 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
65940 #define M_LOFE    0x3fU
65952 #define S_LOFE3    0
65953 #define M_LOFE3    0x3fU
65957 #define A_MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST 0x328c
65968 #define M_HBISTSP    0x7U
65988 #define S_HSEL    0
65989 #define M_HSEL    0xfU
65993 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
66004 #define M_LOFO4    0x3fU
66016 #define S_LOFO3    0
66017 #define M_LOFO3    0x3fU
66021 #define A_MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST 0x3290
66036 #define M_ACCIND    0x7U
66040 #define S_ACCRD    0
66041 #define M_ACCRD    0xffU
66045 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
66056 #define M_T5E1AMP    0x3fU
66068 #define S_T5E0AMP    0
66069 #define M_T5E0AMP    0x3fU
66073 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
66084 #define M_T5LFSEL    0x7U
66088 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER 0x3298
66103 #define M_LFTGT    0x1fU
66119 #define S_LCURR    0
66120 #define M_LCURR    0x1fU
66124 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
66135 #define M_OFFAMP    0x1fU
66144 #define M_OFFSN    0x3U
66148 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
66174 #define S_T5_RX_VTERM    0
66175 #define M_T5_RX_VTERM    0x3U
66211 #define S_RX_LINKANLGSW    0
66212 #define M_RX_LINKANLGSW    0x7fU
66216 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
66219 #define M_ISTRIMS    0x3U
66224 #define M_ISTRIM    0x3fU
66236 #define S_INTDAC    0
66237 #define M_INTDAC    0x3fU
66242 #define M_INTDACEGS    0x7U
66247 #define M_INTDACE    0x1fU
66252 #define M_INTDACGS    0x3U
66256 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
66259 #define M_MINWDTH    0x1fU
66263 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
66266 #define M_T5SMQM    0x7U
66271 #define M_T5SMQ    0xffU
66276 #define M_T5EMMD    0x3U
66288 #define S_T5EMEN    0
66293 #define M_SMQM    0x7U
66298 #define M_SMQ    0xffU
66303 #define M_T6_EMMD    0x3U
66315 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
66322 #define M_EMCNT    0xffU
66334 #define S_EMCEN    0
66346 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
66356 #define S_APDF    0
66357 #define M_APDF    0xfffU
66361 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
66363 #define S_SM0LEN    0
66364 #define M_SM0LEN    0x7fffU
66368 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3 0x32bc
66430 #define S_FPRBSOFF    0
66434 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
66437 #define M_H_EN    0xfffU
66441 #define A_MAC_PORT_RX_LINKA_DFE_TAP_CONTROL 0x32c0
66443 #define S_RX_LINKA_INDEX_DFE_TC    0
66444 #define M_RX_LINKA_INDEX_DFE_TC    0xfU
66448 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
66449 #define A_MAC_PORT_RX_LINKA_DFE_TAP 0x32c4
66451 #define S_RX_LINKA_INDEX_DFE_TAP    0
66452 #define M_RX_LINKA_INDEX_DFE_TAP    0xfU
66456 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
66474 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
66492 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
66495 #define M_H4OGS    0x3U
66508 #define M_H4EGS    0x3U
66520 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
66523 #define M_H5OGS    0x3U
66536 #define M_H5EGS    0x3U
66548 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
66551 #define M_H7GS    0x3U
66564 #define M_H7MAG    0xfU
66569 #define M_H6GS    0x3U
66581 #define S_H6MAG    0
66582 #define M_H6MAG    0xfU
66586 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
66589 #define M_H9GS    0x3U
66602 #define M_H9MAG    0xfU
66607 #define M_H8GS    0x3U
66619 #define S_H8MAG    0
66620 #define M_H8MAG    0xfU
66624 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
66627 #define M_H11GS    0x3U
66640 #define M_H11MAG    0xfU
66645 #define M_H10GS    0x3U
66657 #define S_H10MAG    0
66658 #define M_H10MAG    0xfU
66662 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
66665 #define M_H12GS    0x3U
66677 #define S_H12MAG    0
66678 #define M_H12MAG    0xfU
66682 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2 0x32e4
66712 #define S_QCCCMP    0
66716 #define A_MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x32e8
66723 #define M_CSIND    0x3U
66727 #define S_CSVAL    0
66728 #define M_CSVAL    0x7U
66732 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL 0x32ec
66747 #define M_DCDSTEP    0x3U
66764 #define M_DCDSIGN    0x3U
66768 #define S_DCDAMP    0
66769 #define M_DCDAMP    0x3fU
66773 #define A_MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL 0x32f0
66776 #define M_PRBSMODE    0x3U
66781 #define M_RX_LINKA_DCCSTEP_RXCTL    0x3U
66793 #define A_MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL 0x32f4
66808 #define M_QCCSTEP    0x3U
66821 #define M_QCCSIGN    0x3U
66825 #define S_QCDAMP    0
66826 #define M_QCDAMP    0x3fU
66830 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
66856 #define S_ACJZNT    0
66860 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x32f8
66866 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
66908 #define S_MTHOLD    0
66928 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
66929 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
66930 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
66931 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
66932 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
66933 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
66934 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
66935 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
66936 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
66937 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
66938 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
66939 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
66940 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
66941 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
66942 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
66943 #define A_MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3338
66944 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1 0x333c
66945 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
66946 #define A_MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2 0x3340
66947 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3344
66948 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
66949 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
66950 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN 0x334c
66951 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
66952 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL 0x3354
66953 #define A_MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE 0x3358
66954 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
66955 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET 0x335c
66956 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
66957 #define A_MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3360
66958 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
66959 #define A_MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR 0x3364
66960 #define A_MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH 0x3368
66961 #define A_MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x336c
66962 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
66963 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
66964 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
66970 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
66971 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
66972 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
66973 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL 0x3384
66974 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
66975 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE 0x3388
66976 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
66977 #define A_MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST 0x338c
66978 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
66979 #define A_MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST 0x3390
66985 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
66986 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
66987 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER 0x3398
66988 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
66989 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
66990 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
66991 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
66992 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
66993 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
66994 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
66995 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
66996 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3 0x33bc
66997 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
66998 #define A_MAC_PORT_RX_LINKB_DFE_TAP_CONTROL 0x33c0
67000 #define S_RX_LINKB_INDEX_DFE_TC    0
67001 #define M_RX_LINKB_INDEX_DFE_TC    0xfU
67005 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
67006 #define A_MAC_PORT_RX_LINKB_DFE_TAP 0x33c4
67008 #define S_RX_LINKB_INDEX_DFE_TAP    0
67009 #define M_RX_LINKB_INDEX_DFE_TAP    0xfU
67013 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
67014 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
67015 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
67016 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
67017 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
67018 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
67019 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
67020 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
67021 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2 0x33e4
67022 #define A_MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x33e8
67023 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL 0x33ec
67024 #define A_MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL 0x33f0
67027 #define M_RX_LINKB_DCCSTEP_RXCTL    0x3U
67035 #define A_MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL 0x33f4
67036 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
67037 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x33f8
67038 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
67039 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
67040 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
67041 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
67042 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
67043 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
67044 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
67045 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
67046 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
67047 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
67048 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
67049 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
67050 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT 0x342c
67051 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
67052 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
67053 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
67054 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
67055 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
67056 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3440
67057 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
67058 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3444
67059 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
67060 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3448
67061 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x344c
67062 #define A_MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER 0x3450
67063 #define A_MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3458
67064 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
67065 #define A_MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED 0x3460
67066 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
67067 #define A_MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED 0x3464
67068 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
67069 #define A_MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED 0x3468
67070 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x346c
67071 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
67072 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3470
67073 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
67074 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3474
67075 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
67076 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
67077 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
67078 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
67079 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
67080 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3488
67081 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
67082 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x348c
67083 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
67084 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
67085 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
67086 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
67087 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x34a0
67090 #define M_TX_LINKC_DCCSTEP_CTL    0x3U
67094 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x34a4
67095 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x34a8
67096 #define A_T6_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x34ac
67097 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE 0x34c0
67098 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE 0x34c8
67099 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE 0x34cc
67100 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE 0x34d0
67101 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x34d8
67102 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x34dc
67103 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x34e0
67104 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5 0x34ec
67105 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
67106 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
67107 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
67108 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
67109 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
67110 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
67111 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
67112 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
67113 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
67114 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
67115 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
67116 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
67117 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
67118 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
67119 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
67120 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT 0x352c
67121 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
67122 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
67123 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
67124 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
67125 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
67126 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3540
67127 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
67128 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3544
67129 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
67130 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3548
67131 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x354c
67132 #define A_MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER 0x3550
67133 #define A_MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3558
67134 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
67135 #define A_MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED 0x3560
67136 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
67137 #define A_MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED 0x3564
67138 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
67139 #define A_MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED 0x3568
67140 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x356c
67141 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
67142 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3570
67143 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
67144 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3574
67145 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
67146 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
67147 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
67148 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
67149 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
67150 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3588
67151 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
67152 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x358c
67153 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
67154 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
67155 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
67156 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
67157 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x35a0
67160 #define M_TX_LINKD_DCCSTEP_CTL    0x3U
67164 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x35a4
67165 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x35a8
67166 #define A_T6_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x35ac
67167 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE 0x35c0
67168 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE 0x35c8
67169 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE 0x35cc
67170 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE 0x35d0
67171 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x35d8
67172 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x35dc
67173 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x35e0
67174 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5 0x35ec
67175 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
67176 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
67177 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
67178 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
67179 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
67180 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
67181 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
67182 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
67183 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
67184 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
67185 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
67186 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
67187 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
67188 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
67189 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
67190 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
67191 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
67192 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
67193 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
67194 #define A_MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3638
67195 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1 0x363c
67196 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
67197 #define A_MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2 0x3640
67198 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3644
67199 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
67200 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
67201 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN 0x364c
67202 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
67203 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL 0x3654
67204 #define A_MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE 0x3658
67205 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
67206 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET 0x365c
67207 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
67208 #define A_MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3660
67209 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
67210 #define A_MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR 0x3664
67211 #define A_MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH 0x3668
67212 #define A_MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x366c
67213 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
67214 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
67215 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
67221 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
67222 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
67223 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
67224 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL 0x3684
67225 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
67226 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE 0x3688
67227 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
67228 #define A_MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST 0x368c
67229 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
67230 #define A_MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST 0x3690
67236 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
67237 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
67238 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER 0x3698
67239 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
67240 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
67241 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
67242 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
67243 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
67244 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
67245 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
67246 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
67247 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3 0x36bc
67248 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
67249 #define A_MAC_PORT_RX_LINKC_DFE_TAP_CONTROL 0x36c0
67251 #define S_RX_LINKC_INDEX_DFE_TC    0
67252 #define M_RX_LINKC_INDEX_DFE_TC    0xfU
67256 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
67257 #define A_MAC_PORT_RX_LINKC_DFE_TAP 0x36c4
67259 #define S_RX_LINKC_INDEX_DFE_TAP    0
67260 #define M_RX_LINKC_INDEX_DFE_TAP    0xfU
67264 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
67265 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
67266 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
67267 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
67268 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
67269 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
67270 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
67271 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
67272 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2 0x36e4
67273 #define A_MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x36e8
67274 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL 0x36ec
67275 #define A_MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL 0x36f0
67278 #define M_RX_LINKC_DCCSTEP_RXCTL    0x3U
67286 #define A_MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL 0x36f4
67287 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
67288 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x36f8
67289 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
67290 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
67291 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
67292 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
67293 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
67294 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
67295 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
67296 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
67297 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
67298 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
67299 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
67300 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
67301 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
67302 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
67303 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
67304 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
67305 #define A_MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3738
67306 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1 0x373c
67307 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
67308 #define A_MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2 0x3740
67309 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3744
67310 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
67311 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
67312 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN 0x374c
67313 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
67314 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL 0x3754
67315 #define A_MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE 0x3758
67316 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
67317 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET 0x375c
67318 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
67319 #define A_MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3760
67320 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
67321 #define A_MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR 0x3764
67322 #define A_MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH 0x3768
67323 #define A_MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x376c
67324 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
67325 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
67326 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
67332 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
67333 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
67334 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
67335 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL 0x3784
67336 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
67337 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE 0x3788
67338 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
67339 #define A_MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST 0x378c
67340 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
67341 #define A_MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST 0x3790
67347 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
67348 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
67349 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER 0x3798
67350 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
67351 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
67352 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
67353 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
67354 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
67355 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
67356 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
67357 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
67358 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3 0x37bc
67359 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
67360 #define A_MAC_PORT_RX_LINKD_DFE_TAP_CONTROL 0x37c0
67362 #define S_RX_LINKD_INDEX_DFE_TC    0
67363 #define M_RX_LINKD_INDEX_DFE_TC    0xfU
67367 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
67368 #define A_MAC_PORT_RX_LINKD_DFE_TAP 0x37c4
67370 #define S_RX_LINKD_INDEX_DFE_TAP    0
67371 #define M_RX_LINKD_INDEX_DFE_TAP    0xfU
67375 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
67376 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
67377 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
67378 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
67379 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
67380 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
67381 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
67382 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
67383 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2 0x37e4
67384 #define A_MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x37e8
67385 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL 0x37ec
67386 #define A_MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL 0x37f0
67389 #define M_RX_LINKD_DCCSTEP_RXCTL    0x3U
67397 #define A_MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL 0x37f4
67398 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
67399 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x37f8
67400 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
67401 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
67402 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
67404 #define S_T5BGCTL    0
67405 #define M_T5BGCTL    0xfU
67409 #define A_MAC_PORT_PLLREFSEL_CONTROL 0x3854
67411 #define S_REFSEL    0
67412 #define M_REFSEL    0x7U
67416 #define A_MAC_PORT_REFISINK_CONTROL 0x3858
67418 #define S_REFISINK    0
67419 #define M_REFISINK    0x3fU
67423 #define A_MAC_PORT_REFISRC_CONTROL 0x385c
67425 #define S_REFISRC    0
67426 #define M_REFISRC    0x3fU
67430 #define A_MAC_PORT_REFVREG_CONTROL 0x3860
67432 #define S_REFVREG    0
67433 #define M_REFVREG    0x3fU
67437 #define A_MAC_PORT_VBGENDOC_CONTROL 0x3864
67443 #define S_VBGENDOC    0
67444 #define M_VBGENDOC    0x3U
67448 #define A_MAC_PORT_VREFTUNE_CONTROL 0x3868
67450 #define S_VREFTUNE    0
67451 #define M_VREFTUNE    0xfU
67455 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
67477 #define S_RCRST    0
67481 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL 0x3880
67495 #define S_RCAL_RESET    0
67499 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
67505 #define S_RCCOMP    0
67509 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1 0x3884
67523 #define S_RCALCOMP    0
67527 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
67529 #define S_RESREG2    0
67530 #define M_RESREG2    0xffU
67534 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2 0x3888
67536 #define S_T6_RESREG2    0
67537 #define M_T6_RESREG2    0x3fU
67541 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
67543 #define S_RESREG3    0
67544 #define M_RESREG3    0xffU
67548 #define A_MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3 0x388c
67550 #define S_T6_RESREG3    0
67551 #define M_T6_RESREG3    0x3fU
67555 #define A_MAC_PORT_INEQUALITY_CONTROL_AND_RESULT 0x38c0
67570 #define M_ISVAL    0x3U
67575 #define M_GTORLT    0x3U
67579 #define S_INEQ    0
67583 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT 0x38c4
67585 #define S_LLIM    0
67586 #define M_LLIM    0xffffU
67590 #define A_MAC_PORT_INEQUALITY_LOW_LIMIT_MASK 0x38c8
67592 #define S_LMSK    0
67593 #define M_LMSK    0xffffU
67597 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT 0x38cc
67599 #define S_HLIM    0
67600 #define M_HLIM    0xffffU
67604 #define A_MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK 0x38d0
67606 #define S_HMSK    0
67607 #define M_HMSK    0xffffU
67611 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
67641 #define S_HSSACJAC    0
67645 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
67671 #define S_MACROTEST    0
67675 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
67676 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
67677 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
67678 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
67679 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
67680 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
67681 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
67682 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
67683 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
67684 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
67685 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
67686 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT 0x392c
67687 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
67688 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
67689 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
67690 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
67691 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
67692 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE 0x3940
67693 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
67694 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE 0x3944
67695 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
67696 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE 0x3948
67697 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE 0x394c
67698 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER 0x3950
67699 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER 0x3958
67700 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
67701 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED 0x3960
67702 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
67703 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED 0x3964
67704 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
67705 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED 0x3968
67706 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED 0x396c
67707 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
67708 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED 0x3970
67709 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
67710 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER 0x3974
67711 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
67712 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
67713 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
67714 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
67715 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
67716 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4 0x3988
67717 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
67718 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6 0x398c
67719 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
67720 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
67721 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
67722 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
67723 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x39a0
67726 #define M_TX_LINK_BCST_DCCSTEP_CTL    0x3U
67730 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x39a4
67731 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x39a8
67732 #define A_T6_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x39ac
67733 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE 0x39c0
67734 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE 0x39c8
67735 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE 0x39cc
67736 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE 0x39d0
67737 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE 0x39d8
67738 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE 0x39dc
67739 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE 0x39e0
67740 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5 0x39ec
67741 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
67742 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
67743 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
67744 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
67745 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
67746 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
67747 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
67748 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
67749 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
67750 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
67751 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
67752 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
67753 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
67754 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
67755 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
67756 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
67757 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
67758 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
67759 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
67760 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL 0x3a38
67761 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1 0x3a3c
67762 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
67763 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2 0x3a40
67764 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION 0x3a44
67765 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
67766 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
67767 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN 0x3a4c
67768 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
67769 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL 0x3a54
67770 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE 0x3a58
67771 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
67772 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET 0x3a5c
67773 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
67774 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE 0x3a60
67775 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
67776 #define A_MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR 0x3a64
67777 #define A_MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH 0x3a68
67778 #define A_MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL 0x3a6c
67779 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3…
67780 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
67781 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
67787 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
67788 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
67789 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
67790 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL 0x3a84
67791 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
67792 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE 0x3a88
67793 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
67794 #define A_MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST 0x3a8c
67795 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
67796 #define A_MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST 0x3a90
67802 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
67803 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
67804 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER 0x3a98
67805 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
67806 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
67807 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
67808 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
67809 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
67810 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
67811 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
67812 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
67813 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3 0x3abc
67814 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
67815 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL 0x3ac0
67817 #define S_RX_LINK_BCST_INDEX_DFE_TC    0
67818 #define M_RX_LINK_BCST_INDEX_DFE_TC    0xfU
67822 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
67823 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP 0x3ac4
67825 #define S_RX_LINK_BCST_INDEX_DFE_TAP    0
67826 #define M_RX_LINK_BCST_INDEX_DFE_TAP    0xfU
67830 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
67831 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
67832 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
67833 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
67834 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
67835 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
67836 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
67837 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
67838 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2 0x3ae4
67839 #define A_MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST 0x3ae8
67840 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL 0x3aec
67841 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL 0x3af0
67844 #define M_RX_LINK_BCST_DCCSTEP_RXCTL    0x3U
67852 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL 0x3af4
67853 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
67854 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2 0x3af8
67855 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
67856 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
67857 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
67858 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
67859 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
67860 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
67861 #define A_MAC_PORT_PLLA_POWER_CONTROL 0x3b24
67867 #define S_NPWRENA    0
67871 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
67873 #define S_T5CPISEL    0
67874 #define M_T5CPISEL    0x7U
67878 #define A_MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL 0x3b38
67879 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
67882 #define M_SPEDIV    0x1fU
67886 #define S_PCKSEL    0
67887 #define M_PCKSEL    0x7U
67891 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
67901 #define S_EMIS    0
67905 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
67907 #define S_EMIL1    0
67908 #define M_EMIL1    0xffU
67912 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
67914 #define S_EMIL2    0
67915 #define M_EMIL2    0xffU
67919 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
67921 #define S_EMIL3    0
67922 #define M_EMIL3    0xffU
67926 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
67928 #define S_EMIL4    0
67929 #define M_EMIL4    0xffU
67933 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
67936 #define M_VBST    0x7U
67944 #define S_REFDIV    0
67945 #define M_REFDIV    0xfU
67949 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
67975 #define S_DIVSEL8    0
67979 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
67981 #define S_DIVSEL    0
67982 #define M_DIVSEL    0xffU
67986 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
67988 #define S_CONFIG    0
67989 #define M_CONFIG    0xffU
67993 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
67994 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
67995 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
67996 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
67997 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
67998 #define A_MAC_PORT_PLLB_POWER_CONTROL 0x3c24
67999 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
68000 #define A_MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL 0x3c38
68001 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
68002 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
68003 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
68004 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
68005 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
68006 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
68007 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
68008 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
68009 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
68010 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
68011 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68013 #define S_STEP    0
68014 #define M_STEP    0x7U
68018 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68019 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68021 #define S_C0INIT    0
68022 #define M_C0INIT    0x1fU
68027 #define M_C0PRESET    0x7fU
68031 #define S_C0INIT1    0
68032 #define M_C0INIT1    0x7fU
68036 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68039 #define M_C0MAX    0x1fU
68043 #define S_C0MIN    0
68044 #define M_C0MIN    0x1fU
68048 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68051 #define M_T6_C0MAX    0x7fU
68055 #define S_T6_C0MIN    0
68056 #define M_T6_C0MIN    0x7fU
68060 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68062 #define S_C1INIT    0
68063 #define M_C1INIT    0x7fU
68067 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68070 #define M_C1PRESET    0x7fU
68074 #define S_C1INIT1    0
68075 #define M_C1INIT1    0x7fU
68079 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68082 #define M_C1MAX    0x7fU
68086 #define S_C1MIN    0
68087 #define M_C1MIN    0x7fU
68091 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68092 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68094 #define S_C2INIT    0
68095 #define M_C2INIT    0x3fU
68099 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68102 #define M_C2PRESET    0x7fU
68106 #define S_C2INIT1    0
68107 #define M_C2INIT1    0x7fU
68111 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68114 #define M_C2MAX    0x3fU
68118 #define S_C2MIN    0
68119 #define M_C2MIN    0x3fU
68123 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68126 #define M_T6_C2MAX    0x7fU
68130 #define S_T6_C2MIN    0
68131 #define M_T6_C2MIN    0x7fU
68135 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68137 #define S_VMMAX    0
68138 #define M_VMMAX    0x7fU
68142 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68143 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68145 #define S_V2MIN    0
68146 #define M_V2MIN    0x7fU
68150 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68151 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68154 #define M_C3PRESET    0x7fU
68158 #define S_C3INIT1    0
68159 #define M_C3INIT1    0x7fU
68163 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68166 #define M_C3MAX    0x7fU
68170 #define S_C3MIN    0
68171 #define M_C3MIN    0x7fU
68175 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68177 #define S_C0INIT2    0
68178 #define M_C0INIT2    0x7fU
68182 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68184 #define S_C1INIT2    0
68185 #define M_C1INIT2    0x7fU
68189 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68191 #define S_C2INIT2    0
68192 #define M_C2INIT2    0x7fU
68196 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68198 #define S_C3INIT2    0
68199 #define M_C3INIT2    0x7fU
68203 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68204 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68205 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68206 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68207 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68208 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68209 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68210 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68211 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68212 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68213 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68214 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68215 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68216 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68217 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68218 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68219 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68220 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68221 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68222 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68223 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68224 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68225 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68226 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68227 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68228 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68229 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68230 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68231 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68232 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68233 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68234 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68235 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68236 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68237 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68238 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68239 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68240 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68241 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68242 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68243 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68244 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68245 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68246 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68247 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68248 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68249 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68250 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68251 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68252 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68253 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68254 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68255 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68256 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68257 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68258 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68259 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68260 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68261 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68262 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68263 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68264 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68265 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68266 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68267 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68268 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68269 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68270 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68271 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68272 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
68273 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_STEP_SIZE_EXTENDED 0x0
68274 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
68275 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
68276 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_LIMIT_EXTENDED 0x10
68277 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
68278 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT_EXTENDED 0x18
68279 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
68280 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_LIMIT_EXTENDED 0x20
68281 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
68282 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT_EXTENDED 0x28
68283 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
68284 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_LIMIT_EXTENDED 0x30
68285 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
68286 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_VM_LIMIT_EXTENDED 0x38
68287 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
68288 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_V2_LIMIT_EXTENDED 0x40
68289 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT_EXTENDED 0x48
68290 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_LIMIT_EXTENDED 0x50
68291 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C0_INIT2_EXTENDED 0x5c
68292 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C1_INIT2_EXTENDED 0x60
68293 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C2_INIT2_EXTENDED 0x68
68294 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_C3_INIT2_EXTENDED 0x70
68295 #define A_T6_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x2a00
68298 #define M_RX_LINKA_INDEX_DFE_EN    0x7fffU
68302 #define A_T6_MAC_PORT_RX_LINKA_DFE_H1 0x2a04
68305 #define M_T6_H1OSN    0x7U
68310 #define M_T6_H1OMAG    0x1fU
68314 #define A_T6_MAC_PORT_RX_LINKA_DFE_H2 0x2a08
68315 #define A_T6_MAC_PORT_RX_LINKA_DFE_H3 0x2a0c
68316 #define A_T6_MAC_PORT_RX_LINKA_DFE_H4 0x2a10
68319 #define M_H4SN    0x3U
68323 #define S_H4MAG    0
68324 #define M_H4MAG    0xfU
68328 #define A_T6_MAC_PORT_RX_LINKA_DFE_H5 0x2a14
68331 #define M_H5GS    0x3U
68336 #define M_H5SN    0x3U
68340 #define S_H5MAG    0
68341 #define M_H5MAG    0xfU
68345 #define A_T6_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x2a18
68348 #define M_H7SN    0x3U
68353 #define M_H6SN    0x3U
68357 #define A_T6_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x2a1c
68360 #define M_H9SN    0x3U
68365 #define M_H8SN    0x3U
68369 #define A_T6_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x2a20
68372 #define M_H11SN    0x3U
68377 #define M_H10SN    0x3U
68381 #define A_MAC_PORT_RX_LINKA_DFE_H12_13 0x2a24
68384 #define M_H13GS    0x7U
68389 #define M_H13SN    0x7U
68394 #define M_H13MAG    0x3U
68399 #define M_H12SN    0x3U
68403 #define A_MAC_PORT_RX_LINKA_DFE_H14_15 0x2a28
68406 #define M_H15GS    0x7U
68411 #define M_H15SN    0x7U
68416 #define M_H15MAG    0x3U
68421 #define M_H14GS    0x3U
68426 #define M_H14SN    0x3U
68430 #define S_H14MAG    0
68431 #define M_H14MAG    0xfU
68435 #define A_MAC_PORT_RX_LINKA_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2a2c
68438 #define M_H1ODELTA    0x1fU
68442 #define S_H1EDELTA    0
68443 #define M_H1EDELTA    0x3fU
68447 #define A_T6_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x2b00
68450 #define M_RX_LINKB_INDEX_DFE_EN    0x7fffU
68454 #define A_T6_MAC_PORT_RX_LINKB_DFE_H1 0x2b04
68455 #define A_T6_MAC_PORT_RX_LINKB_DFE_H2 0x2b08
68456 #define A_T6_MAC_PORT_RX_LINKB_DFE_H3 0x2b0c
68457 #define A_T6_MAC_PORT_RX_LINKB_DFE_H4 0x2b10
68458 #define A_T6_MAC_PORT_RX_LINKB_DFE_H5 0x2b14
68459 #define A_T6_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x2b18
68460 #define A_T6_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x2b1c
68461 #define A_T6_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x2b20
68462 #define A_MAC_PORT_RX_LINKB_DFE_H12_13 0x2b24
68463 #define A_MAC_PORT_RX_LINKB_DFE_H14_15 0x2b28
68464 #define A_MAC_PORT_RX_LINKB_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2b2c
68465 #define A_T6_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x2e00
68468 #define M_RX_LINKC_INDEX_DFE_EN    0x7fffU
68472 #define A_T6_MAC_PORT_RX_LINKC_DFE_H1 0x2e04
68473 #define A_T6_MAC_PORT_RX_LINKC_DFE_H2 0x2e08
68474 #define A_T6_MAC_PORT_RX_LINKC_DFE_H3 0x2e0c
68475 #define A_T6_MAC_PORT_RX_LINKC_DFE_H4 0x2e10
68476 #define A_T6_MAC_PORT_RX_LINKC_DFE_H5 0x2e14
68477 #define A_T6_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x2e18
68478 #define A_T6_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x2e1c
68479 #define A_T6_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x2e20
68480 #define A_MAC_PORT_RX_LINKC_DFE_H12_13 0x2e24
68481 #define A_MAC_PORT_RX_LINKC_DFE_H14_15 0x2e28
68482 #define A_MAC_PORT_RX_LINKC_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2e2c
68483 #define A_T6_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x2f00
68486 #define M_RX_LINKD_INDEX_DFE_EN    0x7fffU
68490 #define A_T6_MAC_PORT_RX_LINKD_DFE_H1 0x2f04
68491 #define A_T6_MAC_PORT_RX_LINKD_DFE_H2 0x2f08
68492 #define A_T6_MAC_PORT_RX_LINKD_DFE_H3 0x2f0c
68493 #define A_T6_MAC_PORT_RX_LINKD_DFE_H4 0x2f10
68494 #define A_T6_MAC_PORT_RX_LINKD_DFE_H5 0x2f14
68495 #define A_T6_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x2f18
68496 #define A_T6_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x2f1c
68497 #define A_T6_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x2f20
68498 #define A_MAC_PORT_RX_LINKD_DFE_H12_13 0x2f24
68499 #define A_MAC_PORT_RX_LINKD_DFE_H14_15 0x2f28
68500 #define A_MAC_PORT_RX_LINKD_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x2f2c
68501 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3200
68504 #define M_RX_LINK_BCST_INDEX_DFE_EN    0x7fffU
68508 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3204
68509 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3208
68510 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H3 0x320c
68511 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3210
68512 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3214
68513 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3218
68514 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x321c
68515 #define A_T6_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3220
68516 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12_13 0x3224
68517 #define A_MAC_PORT_RX_LINK_BCST_DFE_H14_15 0x3228
68518 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1ODD_DELTA_AND_H1EVEN_DELTA 0x322c
68521 #define MC_0_BASE_ADDR 0x40000
68523 #define A_MC_UPCTL_SCFG 0x40000
68526 #define M_BBFLAGS_TIMING    0xfU
68534 #define A_MC_UPCTL_SCTL 0x40004
68535 #define A_MC_UPCTL_STAT 0x40008
68538 #define M_LP_TRIG    0x7U
68542 #define A_MC_UPCTL_INTRSTAT 0x4000c
68548 #define S_ECC_INTR    0
68552 #define A_MC_UPCTL_MCMD 0x40040
68554 #define S_CMD_OPCODE0    0
68555 #define M_CMD_OPCODE0    0xfU
68559 #define A_MC_LMC_MCSTAT 0x40040
68581 #define A_MC_UPCTL_POWCTL 0x40044
68582 #define A_MC_UPCTL_POWSTAT 0x40048
68583 #define A_MC_UPCTL_CMDTSTAT 0x4004c
68585 #define S_CMD_TSTAT    0
68589 #define A_MC_UPCTL_CMDTSTATEN 0x40050
68591 #define S_CMD_TSTAT_EN    0
68595 #define A_MC_UPCTL_MRRCFG0 0x40060
68597 #define S_MRR_BYTE_SEL    0
68598 #define M_MRR_BYTE_SEL    0xfU
68602 #define A_MC_UPCTL_MRRSTAT0 0x40064
68605 #define M_MRRSTAT_BEAT3    0xffU
68610 #define M_MRRSTAT_BEAT2    0xffU
68615 #define M_MRRSTAT_BEAT1    0xffU
68619 #define S_MRRSTAT_BEAT0    0
68620 #define M_MRRSTAT_BEAT0    0xffU
68624 #define A_MC_UPCTL_MRRSTAT1 0x40068
68627 #define M_MRRSTAT_BEAT7    0xffU
68632 #define M_MRRSTAT_BEAT6    0xffU
68637 #define M_MRRSTAT_BEAT5    0xffU
68641 #define S_MRRSTAT_BEAT4    0
68642 #define M_MRRSTAT_BEAT4    0xffU
68646 #define A_MC_UPCTL_MCFG1 0x4007c
68653 #define M_HW_IDLE    0xffU
68657 #define S_SR_IDLE    0
68658 #define M_SR_IDLE    0xffU
68662 #define A_MC_UPCTL_MCFG 0x40080
68665 #define M_MDDR_LPDDR2_CLK_STOP_IDLE    0xffU
68670 #define M_MDDR_LPDDR2_EN    0x3U
68675 #define M_MDDR_LPDDR2_BL    0x3U
68691 #define A_MC_LMC_MCOPT1 0x40080
68714 #define M_PMUM    0x3U
68747 #define M_QDEPTH    0x3U
68776 #define M_ECC_MUX    0x3U
68780 #define S_CE_THRESHOLD    0
68781 #define M_CE_THRESHOLD    0xffU
68785 #define A_MC_UPCTL_PPCFG 0x40084
68786 #define A_MC_LMC_MCOPT2 0x40084
68805 #define M_CLK_DISABLE    0xfU
68810 #define M_RESET_RANK    0xfU
68839 #define M_PM_ENABLE    0xfU
68844 #define M_RD_DEFREF_CNT    0xfU
68848 #define A_MC_UPCTL_MSTAT 0x40088
68858 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
68861 #define M_ZQCL_OP    0xffU
68866 #define M_ZQCL_MA    0xffU
68871 #define M_ZQCS_OP    0xffU
68875 #define S_ZQCS_MA    0
68876 #define M_ZQCS_MA    0xffU
68880 #define A_MC_UPCTL_DTUPDES 0x40094
68886 #define A_MC_UPCTL_DTUNA 0x40098
68887 #define A_MC_UPCTL_DTUNE 0x4009c
68888 #define A_MC_UPCTL_DTUPRD0 0x400a0
68889 #define A_MC_UPCTL_DTUPRD1 0x400a4
68890 #define A_MC_UPCTL_DTUPRD2 0x400a8
68891 #define A_MC_UPCTL_DTUPRD3 0x400ac
68892 #define A_MC_UPCTL_DTUAWDT 0x400b0
68893 #define A_MC_UPCTL_TOGCNT1U 0x400c0
68894 #define A_MC_UPCTL_TINIT 0x400c4
68895 #define A_MC_UPCTL_TRSTH 0x400c8
68896 #define A_MC_UPCTL_TOGCNT100N 0x400cc
68897 #define A_MC_UPCTL_TREFI 0x400d0
68898 #define A_MC_UPCTL_TMRD 0x400d4
68899 #define A_MC_UPCTL_TRFC 0x400d8
68901 #define S_T_RFC0    0
68902 #define M_T_RFC0    0x1ffU
68906 #define A_MC_UPCTL_TRP 0x400dc
68909 #define M_PREA_EXTRA    0x3U
68913 #define A_MC_UPCTL_TRTW 0x400e0
68915 #define S_T_RTW0    0
68916 #define M_T_RTW0    0xfU
68920 #define A_MC_UPCTL_TAL 0x400e4
68921 #define A_MC_UPCTL_TCL 0x400e8
68922 #define A_MC_UPCTL_TCWL 0x400ec
68923 #define A_MC_UPCTL_TRAS 0x400f0
68924 #define A_MC_UPCTL_TRC 0x400f4
68925 #define A_MC_UPCTL_TRCD 0x400f8
68926 #define A_MC_UPCTL_TRRD 0x400fc
68927 #define A_MC_UPCTL_TRTP 0x40100
68929 #define S_T_RTP0    0
68930 #define M_T_RTP0    0xfU
68934 #define A_MC_LMC_CFGR0 0x40100
68937 #define M_ROW_WIDTH    0x7U
68942 #define M_ADDR_MODE    0xfU
68950 #define S_RANK_ENABLE    0
68954 #define A_MC_UPCTL_TWR 0x40104
68956 #define S_U_T_WR    0
68957 #define M_U_T_WR    0x1fU
68961 #define A_MC_UPCTL_TWTR 0x40108
68963 #define S_T_WTR0    0
68964 #define M_T_WTR0    0xfU
68968 #define A_MC_UPCTL_TEXSR 0x4010c
68969 #define A_MC_UPCTL_TXP 0x40110
68970 #define A_MC_UPCTL_TXPDLL 0x40114
68971 #define A_MC_UPCTL_TZQCS 0x40118
68972 #define A_MC_UPCTL_TZQCSI 0x4011c
68973 #define A_MC_UPCTL_TDQS 0x40120
68974 #define A_MC_UPCTL_TCKSRE 0x40124
68976 #define S_T_CKSRE0    0
68977 #define M_T_CKSRE0    0x1fU
68981 #define A_MC_UPCTL_TCKSRX 0x40128
68983 #define S_T_CKSRX0    0
68984 #define M_T_CKSRX0    0x1fU
68988 #define A_MC_UPCTL_TCKE 0x4012c
68989 #define A_MC_UPCTL_TMOD 0x40130
68991 #define S_T_MOD0    0
68992 #define M_T_MOD0    0x1fU
68996 #define A_MC_UPCTL_TRSTL 0x40134
68998 #define S_T_RSTL    0
68999 #define M_T_RSTL    0x7fU
69003 #define A_MC_UPCTL_TZQCL 0x40138
69004 #define A_MC_UPCTL_TMRR 0x4013c
69006 #define S_T_MRR    0
69007 #define M_T_MRR    0xffU
69011 #define A_MC_UPCTL_TCKESR 0x40140
69013 #define S_T_CKESR    0
69014 #define M_T_CKESR    0xfU
69018 #define A_MC_LMC_INITSEQ0 0x40140
69025 #define M_WAIT    0xfffU
69033 #define S_T6_RANK    0
69034 #define M_T6_RANK    0xfU
69038 #define A_MC_UPCTL_TDPD 0x40144
69040 #define S_T_DPD    0
69041 #define M_T_DPD    0x3ffU
69045 #define A_MC_LMC_CMD0 0x40144
69048 #define M_CMD    0x7U
69061 #define M_BANK    0x7U
69065 #define A_MC_LMC_INITSEQ1 0x40148
69066 #define A_MC_LMC_CMD1 0x4014c
69067 #define A_MC_LMC_INITSEQ2 0x40150
69068 #define A_MC_LMC_CMD2 0x40154
69069 #define A_MC_LMC_INITSEQ3 0x40158
69070 #define A_MC_LMC_CMD3 0x4015c
69071 #define A_MC_LMC_INITSEQ4 0x40160
69072 #define A_MC_LMC_CMD4 0x40164
69073 #define A_MC_LMC_INITSEQ5 0x40168
69074 #define A_MC_LMC_CMD5 0x4016c
69075 #define A_MC_LMC_INITSEQ6 0x40170
69076 #define A_MC_LMC_CMD6 0x40174
69077 #define A_MC_LMC_INITSEQ7 0x40178
69078 #define A_MC_LMC_CMD7 0x4017c
69079 #define A_MC_UPCTL_ECCCFG 0x40180
69080 #define A_MC_LMC_INITSEQ8 0x40180
69081 #define A_MC_UPCTL_ECCTST 0x40184
69083 #define S_ECC_TEST_MASK0    0
69084 #define M_ECC_TEST_MASK0    0x7fU
69088 #define A_MC_LMC_CMD8 0x40184
69089 #define A_MC_UPCTL_ECCCLR 0x40188
69090 #define A_MC_LMC_INITSEQ9 0x40188
69091 #define A_MC_UPCTL_ECCLOG 0x4018c
69092 #define A_MC_LMC_CMD9 0x4018c
69093 #define A_MC_LMC_INITSEQ10 0x40190
69094 #define A_MC_LMC_CMD10 0x40194
69095 #define A_MC_LMC_INITSEQ11 0x40198
69096 #define A_MC_LMC_CMD11 0x4019c
69097 #define A_MC_LMC_INITSEQ12 0x401a0
69098 #define A_MC_LMC_CMD12 0x401a4
69099 #define A_MC_LMC_INITSEQ13 0x401a8
69100 #define A_MC_LMC_CMD13 0x401ac
69101 #define A_MC_LMC_INITSEQ14 0x401b0
69102 #define A_MC_LMC_CMD14 0x401b4
69103 #define A_MC_LMC_INITSEQ15 0x401b8
69104 #define A_MC_LMC_CMD15 0x401bc
69105 #define A_MC_UPCTL_DTUWACTL 0x40200
69108 #define M_DTU_WR_ROW0    0xffffU
69112 #define A_MC_LMC_SDTR0 0x40200
69115 #define M_REFI    0xffffU
69119 #define S_T_RFC_XPR    0
69120 #define M_T_RFC_XPR    0xfffU
69124 #define A_MC_UPCTL_DTURACTL 0x40204
69127 #define M_DTU_RD_ROW0    0xffffU
69131 #define A_MC_LMC_SDTR1 0x40204
69146 #define M_T_WTRO    0xfU
69151 #define M_T_RTWO    0xfU
69156 #define M_T_RTW_ADJ    0xfU
69161 #define M_T_WTWO    0xfU
69165 #define S_T_RTRO    0
69166 #define M_T_RTRO    0xfU
69170 #define A_MC_UPCTL_DTUCFG 0x40208
69171 #define A_MC_LMC_SDTR2 0x40208
69174 #define M_T6_T_CWL    0xfU
69179 #define M_T_RCD0    0xfU
69184 #define M_T_PL    0xfU
69189 #define M_T_RP0    0xfU
69202 #define M_T6_T_RC    0x3fU
69206 #define A_MC_UPCTL_DTUECTL 0x4020c
69207 #define A_MC_LMC_SDTR3 0x4020c
69210 #define M_T_WTR_S    0xfU
69215 #define M_T6_T_WTR    0xfU
69220 #define M_FAW_ADJ    0x3U
69225 #define M_T6_T_RTP    0xfU
69230 #define M_T_RRD_L    0xfU
69235 #define M_T6_T_RRD    0xfU
69239 #define S_T_XSDLL    0
69240 #define M_T_XSDLL    0xffU
69244 #define A_MC_UPCTL_DTUWD0 0x40210
69245 #define A_MC_LMC_SDTR4 0x40210
69248 #define M_T_RDDATA_EN    0x7fU
69253 #define M_T_SYS_RDLAT    0x3fU
69258 #define M_T_CCD_L    0xfU
69263 #define M_T_CCD    0x7U
69268 #define M_T_CPDED    0x7U
69272 #define S_T6_T_MOD    0
69273 #define M_T6_T_MOD    0x1fU
69277 #define A_MC_UPCTL_DTUWD1 0x40214
69278 #define A_MC_LMC_SDTR5 0x40214
69281 #define M_T_PHY_WRDATA    0x7U
69286 #define M_T_PHY_WRLAT    0x1fU
69290 #define A_MC_UPCTL_DTUWD2 0x40218
69291 #define A_MC_UPCTL_DTUWD3 0x4021c
69292 #define A_MC_UPCTL_DTUWDM 0x40220
69293 #define A_MC_UPCTL_DTURD0 0x40224
69294 #define A_MC_UPCTL_DTURD1 0x40228
69295 #define A_MC_LMC_DBG0 0x40228
69298 #define M_T_SYS_RDLAT_DBG    0x1fU
69302 #define A_MC_UPCTL_DTURD2 0x4022c
69303 #define A_MC_UPCTL_DTURD3 0x40230
69304 #define A_MC_UPCTL_DTULFSRWD 0x40234
69305 #define A_MC_UPCTL_DTULFSRRD 0x40238
69306 #define A_MC_UPCTL_DTUEAF 0x4023c
69309 #define M_EA_ROW0    0xffffU
69313 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
69315 #define S_TCTRL_DELAY    0
69316 #define M_TCTRL_DELAY    0xfU
69320 #define A_MC_LMC_SMR0 0x40240
69323 #define M_SMR0_RFU0    0x7U
69332 #define M_WR_RTP    0x7U
69345 #define M_CL31    0x7U
69357 #define S_BL    0
69358 #define M_BL    0x3U
69362 #define A_MC_UPCTL_DFIODTCFG 0x40244
69368 #define A_MC_LMC_SMR1 0x40244
69403 #define M_AL    0x3U
69415 #define S_SMR1_DLL    0
69419 #define A_MC_UPCTL_DFIODTCFG1 0x40248
69422 #define M_ODT_LEN_B8_R    0x7U
69427 #define M_ODT_LEN_BL8_W    0x7U
69432 #define M_ODT_LAT_R    0x1fU
69436 #define S_ODT_LAT_W    0
69437 #define M_ODT_LAT_W    0x1fU
69441 #define A_MC_LMC_SMR2 0x40248
69452 #define M_RTT_WR    0x3U
69469 #define M_CWL    0x7U
69473 #define S_PASR    0
69474 #define M_PASR    0x7U
69478 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
69481 #define M_ODT_RANK_MAP3    0xfU
69486 #define M_ODT_RANK_MAP2    0xfU
69491 #define M_ODT_RANK_MAP1    0xfU
69495 #define S_ODT_RANK_MAP0    0
69496 #define M_ODT_RANK_MAP0    0xfU
69500 #define A_MC_LMC_SMR3 0x4024c
69503 #define M_MPR_RD_FMT    0x3U
69508 #define M_SMR3_RFU0    0x3U
69513 #define M_FGR_MODE    0x7U
69533 #define S_MPR_SEL    0
69534 #define M_MPR_SEL    0x3U
69538 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
69540 #define S_TPHY_WRDATA    0
69541 #define M_TPHY_WRDATA    0x1fU
69545 #define A_MC_LMC_SMR4 0x40250
69564 #define M_CS_LAT_MODE    0x7U
69588 #define S_SMR4_RFU    0
69592 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
69594 #define S_TPHY_WRLAT    0
69595 #define M_TPHY_WRLAT    0x1fU
69599 #define A_MC_LMC_SMR5 0x40254
69614 #define M_RTT_PARK    0x7U
69630 #define S_PAR_LAT_MODE    0
69631 #define M_PAR_LAT_MODE    0x7U
69635 #define A_MC_LMC_SMR6 0x40258
69638 #define M_TCCD_L    0x7U
69643 #define M_SRM6_RFU    0x7U
69651 #define S_VREF_DQ_VALUE    0
69652 #define M_VREF_DQ_VALUE    0x3fU
69656 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
69658 #define S_TRDDATA_EN    0
69659 #define M_TRDDATA_EN    0x1fU
69663 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
69665 #define S_TPHY_RDLAT    0
69666 #define M_TPHY_RDLAT    0x3fU
69670 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
69672 #define S_TPHYUPD_TYPE0    0
69673 #define M_TPHYUPD_TYPE0    0xfffU
69677 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
69679 #define S_TPHYUPD_TYPE1    0
69680 #define M_TPHYUPD_TYPE1    0xfffU
69684 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
69686 #define S_TPHYUPD_TYPE2    0
69687 #define M_TPHYUPD_TYPE2    0xfffU
69691 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
69693 #define S_TPHYUPD_TYPE3    0
69694 #define M_TPHYUPD_TYPE3    0xfffU
69698 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
69700 #define S_TCTRLUPD_MIN    0
69701 #define M_TCTRLUPD_MIN    0xffffU
69705 #define A_MC_LMC_ODTR0 0x40280
69715 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
69717 #define S_TCTRLUPD_MAX    0
69718 #define M_TCTRLUPD_MAX    0xffffU
69722 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
69724 #define S_TCTRLUPD_DLY    0
69725 #define M_TCTRLUPD_DLY    0xfU
69729 #define A_MC_UPCTL_DFIUPDCFG 0x40290
69735 #define S_DFI_CTRLUPD_EN    0
69739 #define A_MC_UPCTL_DFITREFMSKI 0x40294
69741 #define S_TREFMSKI    0
69742 #define M_TREFMSKI    0xffU
69746 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
69747 #define A_MC_UPCTL_DFITRCFG0 0x402ac
69750 #define M_DFI_WRLVL_RANK_SEL    0xfU
69755 #define M_DFI_RDLVL_EDGE    0x1ffU
69759 #define S_DFI_RDLVL_RANK_SEL    0
69760 #define M_DFI_RDLVL_RANK_SEL    0xfU
69764 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
69767 #define M_DFI_WRLVL_MODE    0x3U
69772 #define M_DFI_RDLVL_GATE_MODE    0x3U
69776 #define S_DFI_RDLVL_MODE    0
69777 #define M_DFI_RDLVL_MODE    0x3U
69781 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
69783 #define S_DFI_WRLVL_EN    0
69784 #define M_DFI_WRLVL_EN    0x1ffU
69788 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
69790 #define S_DFI_RDLVL_EN    0
69791 #define M_DFI_RDLVL_EN    0x1ffU
69795 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
69797 #define S_DFI_RDLVL_GATE_EN    0
69798 #define M_DFI_RDLVL_GATE_EN    0x1ffU
69802 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
69805 #define M_DFI_DATA_BYTE_DISABLE    0x1ffU
69810 #define M_DFI_FREQ_RATIO    0x3U
69818 #define S_DFI_INIT_COMPLETE    0
69822 #define A_MC_UPCTL_DFISTCFG0 0x402c4
69832 #define S_DFI_INIT_START    0
69836 #define A_MC_UPCTL_DFISTCFG1 0x402c8
69842 #define S_DFI_DRAM_CLK_DISABLE_EN    0
69846 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
69848 #define S_TDRAM_CLK_ENABLE    0
69849 #define M_TDRAM_CLK_ENABLE    0xfU
69853 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
69855 #define S_TDRAM_CLK_DISABLE    0
69856 #define M_TDRAM_CLK_DISABLE    0xfU
69860 #define A_MC_UPCTL_DFISTCFG2 0x402d8
69866 #define S_PARITY_INTR_EN    0
69870 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
69876 #define S_PARITY_INTR_CLR    0
69880 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
69881 #define A_MC_UPCTL_DFILPCFG0 0x402f0
69884 #define M_DFI_LP_WAKEUP_DPD    0xfU
69893 #define M_DFI_TLP_RESP    0xfU
69902 #define M_DFI_LP_WAKEUP_PD    0xfU
69906 #define S_DFI_LP_EN_PD    0
69910 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
69911 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
69912 #define A_MC_LMC_CALSTAT 0x40304
69915 #define M_PHYUPD_ERR    0xfU
69923 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
69925 #define S_DFI_WRLVL_RESP2    0
69926 #define M_DFI_WRLVL_RESP2    0xffU
69930 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
69931 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
69932 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
69934 #define S_DFI_RDLVL_RESP2    0
69935 #define M_DFI_RDLVL_RESP2    0xffU
69939 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
69940 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
69941 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
69943 #define S_DFI_WRLVL_DELAY2    0
69944 #define M_DFI_WRLVL_DELAY2    0xffU
69948 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
69949 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
69950 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
69952 #define S_DFI_RDLVL_DELAY2    0
69953 #define M_DFI_RDLVL_DELAY2    0xffU
69957 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
69958 #define A_MC_LMC_T_PHYUPD0 0x40330
69959 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
69960 #define A_MC_LMC_T_PHYUPD1 0x40334
69961 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
69963 #define S_DFI_RDLVL_GATE_DELAY2    0
69964 #define M_DFI_RDLVL_GATE_DELAY2    0xffU
69968 #define A_MC_LMC_T_PHYUPD2 0x40338
69969 #define A_MC_UPCTL_DFITRCMD 0x4033c
69976 #define M_DFITRCMD_EN    0x1ffU
69980 #define S_DFITRCMD_OPCODE    0
69981 #define M_DFITRCMD_OPCODE    0x3U
69985 #define A_MC_LMC_T_PHYUPD3 0x4033c
69986 #define A_MC_UPCTL_IPVR 0x403f8
69987 #define A_MC_UPCTL_IPTR 0x403fc
69988 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
69991 #define M_PHY_DRAM_WL    0x1fU
70016 #define M_T6_PHY_DRAM_WL    0xfU
70020 #define A_MC_P_PERFORMANCE_CTRL 0x41304
70023 #define M_BUF_USE_TH    0x7U
70028 #define M_MC_IDLE_TH    0xfU
70052 #define A_MC_P_ECC_CTRL 0x41308
70053 #define A_MC_P_PAR_ENABLE 0x4130c
70054 #define A_MC_P_PAR_CAUSE 0x41310
70055 #define A_MC_P_INT_ENABLE 0x41314
70056 #define A_MC_P_INT_CAUSE 0x41318
70057 #define A_MC_P_ECC_STATUS 0x4131c
70058 #define A_MC_P_PHY_CTRL 0x41320
70059 #define A_MC_P_STATIC_CFG_STATUS 0x41324
70066 #define M_STATIC_SWLAT    0x1fU
70079 #define M_STATIC_SLAT    0x1fU
70099 #define A_MC_P_CORE_PCTL_STAT 0x41328
70100 #define A_MC_P_DEBUG_CNT 0x4132c
70101 #define A_MC_CE_ERR_DATA_RDATA 0x41330
70102 #define A_MC_CE_COR_DATA_RDATA 0x41350
70103 #define A_MC_UE_ERR_DATA_RDATA 0x41370
70104 #define A_MC_UE_COR_DATA_RDATA 0x41390
70105 #define A_MC_CE_ADDR 0x413b0
70106 #define A_MC_UE_ADDR 0x413b4
70107 #define A_MC_P_DEEP_SLEEP 0x413b8
70113 #define S_SLEEPREQ    0
70117 #define A_MC_P_FPGA_BONUS 0x413bc
70118 #define A_MC_P_DEBUG_CFG 0x413c0
70119 #define A_MC_P_DEBUG_RPT 0x413c4
70120 #define A_MC_P_PHY_ADR_CK_EN 0x413c8
70122 #define S_ADR_CK_EN    0
70126 #define A_MC_CE_ERR_ECC_DATA0 0x413d0
70127 #define A_MC_CE_ERR_ECC_DATA1 0x413d4
70128 #define A_MC_UE_ERR_ECC_DATA0 0x413d8
70129 #define A_MC_UE_ERR_ECC_DATA1 0x413dc
70130 #define A_MC_P_RMW_PRIO 0x413f0
70133 #define M_WR_HI_TH    0xffU
70138 #define M_WR_MID_TH    0xffU
70143 #define M_RD_HI_TH    0xffU
70147 #define S_RD_MID_TH    0
70148 #define M_RD_MID_TH    0xffU
70152 #define A_MC_P_BIST_CMD 0x41400
70155 #define M_BURST_LEN    0x3U
70159 #define A_MC_P_BIST_CMD_ADDR 0x41404
70160 #define A_MC_P_BIST_CMD_LEN 0x41408
70161 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
70162 #define A_MC_P_BIST_USER_WDATA0 0x41414
70163 #define A_MC_P_BIST_USER_WMASK0 0x41414
70164 #define A_MC_P_BIST_USER_WDATA1 0x41418
70165 #define A_MC_P_BIST_USER_WMASK1 0x41418
70166 #define A_MC_P_BIST_USER_WDATA2 0x4141c
70169 #define M_USER_DATA_MASK    0x1ffU
70173 #define A_MC_P_BIST_USER_WMASK2 0x4141c
70183 #define S_USER_MASK_ECC    0
70184 #define M_USER_MASK_ECC    0xffU
70188 #define A_MC_P_BIST_NUM_ERR 0x41480
70189 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
70190 #define A_MC_P_BIST_STATUS_RDATA 0x41488
70191 #define A_MC_P_BIST_CRC_SEED 0x414d0
70192 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
70194 #define S_DATA_BIT_ENABLE_0_15    0
70195 #define M_DATA_BIT_ENABLE_0_15    0xffffU
70199 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
70202 #define M_DATA_BIT_ENABLE_16_23    0xffU
70230 #define S_MRS_CMD_DATA_N3    0
70242 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
70244 #define S_DATA_BIT_DIR_0_15    0
70245 #define M_DATA_BIT_DIR_0_15    0xffffU
70249 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
70252 #define M_DATA_BIT_DIR_16_23    0xffU
70284 #define S_ATEST_MUX_CTL3    0
70288 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
70346 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
70352 #define S_QUAD3_CLK18_BIT15    0
70356 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
70359 #define M_PEAK_AMP_CTL_SIDE0    0x7U
70364 #define M_PEAK_AMP_CTL_SIDE1    0x7U
70369 #define M_SXMCVREF_0_3    0xfU
70381 #define S_READ_CENTERING_MODE    0
70382 #define M_READ_CENTERING_MODE    0x3U
70386 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
70392 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
70414 #define S_DIGITAL_EYE_VALUE    0
70415 #define M_DIGITAL_EYE_VALUE    0xffU
70419 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
70422 #define M_DQSCLK_SELECT0    0x3U
70427 #define M_RDCLK_SELECT0    0x3U
70432 #define M_DQSCLK_SELECT1    0x3U
70437 #define M_RDCLK_SELECT1    0x3U
70442 #define M_DQSCLK_SELECT2    0x3U
70447 #define M_RDCLK_SELECT2    0x3U
70452 #define M_DQSCLK_SELECT3    0x3U
70456 #define S_RDCLK_SELECT3    0
70457 #define M_RDCLK_SELECT3    0x3U
70461 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
70464 #define M_MIN_RD_EYE_SIZE    0x3fU
70468 #define S_MAX_DQS_DRIFT    0
70469 #define M_MAX_DQS_DRIFT    0x3fU
70473 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
70476 #define M_HS_PROBE_A_SEL    0x1fU
70481 #define M_HS_PROBE_B_SEL    0x1fU
70486 #define M_RD_DEBUG_SEL    0x7U
70490 #define S_WR_DEBUG_SEL    0
70491 #define M_WR_DEBUG_SEL    0x7U
70496 #define M_DP18_HS_PROBE_A_SEL    0x1fU
70501 #define M_DP18_HS_PROBE_B_SEL    0x1fU
70505 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
70508 #define M_OFFSET_BITS1_7    0x7fU
70512 #define S_OFFSET_BITS9_15    0
70513 #define M_OFFSET_BITS9_15    0x7fU
70517 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
70518 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
70520 #define S_LEADING_EDGE_NOT_FOUND_0    0
70521 #define M_LEADING_EDGE_NOT_FOUND_0    0xffffU
70525 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
70528 #define M_LEADING_EDGE_NOT_FOUND_1    0xffU
70532 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
70534 #define S_TRAILING_EDGE_NOT_FOUND    0
70535 #define M_TRAILING_EDGE_NOT_FOUND    0xffffU
70539 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
70542 #define M_TRAILING_EDGE_NOT_FOUND_16_23    0xffU
70546 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
70572 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
70575 #define M_DQS_GATE_DELAY_N0    0x7U
70580 #define M_DQS_GATE_DELAY_N1    0x7U
70585 #define M_DQS_GATE_DELAY_N2    0x7U
70589 #define S_DQS_GATE_DELAY_N3    0
70590 #define M_DQS_GATE_DELAY_N3    0x7U
70594 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
70656 #define S_MIN_EYE    0
70660 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
70722 #define S_MIN_EYE_MASK    0
70726 #define A_MC_DDRPHY_DP18_WRCLK_CNTL 0x44058
70729 #define M_PRBS_WAIT    0x3U
70746 #define M_SS_QUAD    0x3U
70758 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
70761 #define M_CLK_LEVEL    0x3U
70797 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
70800 #define M_BIT_CENTERED    0x1fU
70832 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
70835 #define M_FW_LEFT_SIDE    0x7ffU
70839 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
70842 #define M_FW_RIGHT_SIDE    0x7ffU
70846 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
70892 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
70946 #define S_ADVANCE_PR_VALUE    0
70950 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
70957 #define M_DP18_DFT_SYNC    0x3fU
70961 #define S_ERROR    0
70962 #define M_ERROR    0x3fU
70970 #define S_DP18_DFT_ERROR    0
70971 #define M_DP18_DFT_ERROR    0x3fU
70975 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
70978 #define M_SYSCLK_RDCLK_OFFSET    0x7fU
70982 #define S_SYSCLK_DQSCLK_OFFSET    0
70983 #define M_SYSCLK_DQSCLK_OFFSET    0x7fU
70988 #define M_T6_SYSCLK_DQSCLK_OFFSET    0x7fU
70992 #define S_T6_SYSCLK_RDCLK_OFFSET    0
70993 #define M_T6_SYSCLK_RDCLK_OFFSET    0x7fU
70997 #define A_MC_DDRPHY_DP18_WRCLK_AUX_CNTL 0x4407c
70998 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
71001 #define M_DQSCLK_ROT_CLK_N0_N2    0x7fU
71005 #define S_DQSCLK_ROT_CLK_N1_N3    0
71006 #define M_DQSCLK_ROT_CLK_N1_N3    0x7fU
71010 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
71011 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
71014 #define M_MEMINTD00_POS    0x3U
71019 #define M_MEMINTD01_PO    0x3U
71024 #define M_MEMINTD02_POS    0x3U
71029 #define M_MEMINTD03_POS    0x3U
71034 #define M_MEMINTD04_POS    0x3U
71039 #define M_MEMINTD05_POS    0x3U
71044 #define M_MEMINTD06_POS    0x3U
71048 #define S_MEMINTD07_POS    0
71049 #define M_MEMINTD07_POS    0x3U
71053 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
71056 #define M_MEMINTD08_POS    0x3U
71061 #define M_MEMINTD09_POS    0x3U
71066 #define M_MEMINTD10_POS    0x3U
71071 #define M_MEMINTD11_POS    0x3U
71076 #define M_MEMINTD12_POS    0x3U
71081 #define M_MEMINTD13_POS    0x3U
71086 #define M_MEMINTD14_POS    0x3U
71090 #define S_MEMINTD15_POS    0
71091 #define M_MEMINTD15_POS    0x3U
71095 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
71098 #define M_MEMINTD16_POS    0x3U
71103 #define M_MEMINTD17_POS    0x3U
71108 #define M_MEMINTD18_POS    0x3U
71113 #define M_MEMINTD19_POS    0x3U
71118 #define M_MEMINTD20_POS    0x3U
71123 #define M_MEMINTD21_POS    0x3U
71128 #define M_MEMINTD22_POS    0x3U
71132 #define S_MEMINTD23_POS    0
71133 #define M_MEMINTD23_POS    0x3U
71137 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
71140 #define M_DQS_ALIGN_SM    0x1fU
71145 #define M_DQS_ALIGN_CNTR    0xfU
71153 #define S_DQS_ALIGN_ITER_CNTR    0
71154 #define M_DQS_ALIGN_ITER_CNTR    0x3fU
71158 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
71161 #define M_CALIBRATE_BIT    0x7U
71166 #define M_DQS_ALIGN_QUAD    0x3U
71171 #define M_DQS_QUAD_CONFIG    0x7U
71176 #define M_OPERATE_MODE    0xfU
71192 #define S_MAX_DQS_ITER    0
71196 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
71199 #define M_DQS_OFFSET    0x7fU
71203 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
71206 #define M_WR_DELAY    0x3ffU
71210 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
71211 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
71212 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
71213 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
71214 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
71215 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
71216 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
71217 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
71218 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
71219 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
71220 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
71221 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
71222 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
71223 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
71224 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
71225 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
71226 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
71227 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
71228 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
71229 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
71230 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
71231 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
71232 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
71233 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
71236 #define M_RD_DELAY_BITS0_6    0x7fU
71241 #define M_RD_DELAY_BITS8_14    0x7fU
71245 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
71246 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
71247 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
71248 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
71249 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
71250 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
71251 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
71252 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
71253 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
71254 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
71255 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
71256 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
71259 #define M_INITIAL_DQS_ROT_N0_N2    0x7fU
71263 #define S_INITIAL_DQS_ROT_N1_N3    0
71264 #define M_INITIAL_DQS_ROT_N1_N3    0x7fU
71268 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
71269 #define A_MC_DDRPHY_DP18_WRCLK_STATUS 0x44178
71327 #define S_QUAD0_CAVEAT    0
71331 #define A_MC_DDRPHY_DP18_WRCLK_EDGE 0x4417c
71334 #define M_FAIL_PASS_VALUE    0x7fU
71338 #define S_PASS_FAIL_VALUE    0
71339 #define M_PASS_FAIL_VALUE    0xffU
71343 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
71346 #define M_RD_EYE_SIZE_BITS2_7    0x3fU
71350 #define S_RD_EYE_SIZE_BITS10_15    0
71351 #define M_RD_EYE_SIZE_BITS10_15    0x3fU
71355 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
71356 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
71357 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
71358 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
71359 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
71360 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
71361 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
71362 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
71363 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
71364 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
71365 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
71366 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
71369 #define M_DESIRED_EDGE_CNTR_TARGET_HIGH    0xffU
71373 #define S_DESIRED_EDGE_CNTR_TARGET_LOW    0
71374 #define M_DESIRED_EDGE_CNTR_TARGET_LOW    0xffU
71378 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
71384 #define A_MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL 0x441bc
71387 #define M_QUAD0_PWR_CTL    0xfU
71392 #define M_QUAD1_PWR_CTL    0xfU
71397 #define M_QUAD2_PWR_CTL    0xfU
71401 #define S_QUAD3_PWR_CTL    0
71402 #define M_QUAD3_PWR_CTL    0xfU
71406 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
71409 #define M_REFERENCE_BITS1_7    0x7fU
71413 #define S_REFERENCE_BITS9_15    0
71414 #define M_REFERENCE_BITS9_15    0x7fU
71418 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
71419 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
71422 #define M_REFERENCE    0x7fU
71426 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
71427 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
71428 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
71431 #define M_INTERP_SIG_SLEW    0xfU
71436 #define M_POST_CURSOR    0xfU
71441 #define M_SLEW_CTL    0xfU
71445 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
71446 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
71468 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
71471 #define M_EN_SLICE_N_WR    0xffU
71475 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
71476 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
71479 #define M_EN_TERM_N_WR    0xffU
71484 #define M_EN_TERM_N_WR_FFE    0xfU
71488 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
71491 #define M_EN_TERM_P_WR    0xffU
71496 #define M_EN_TERM_P_WR_FFE    0xfU
71500 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
71502 #define S_DATA_BIT_DISABLE_0_15    0
71503 #define M_DATA_BIT_DISABLE_0_15    0xffffU
71507 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
71510 #define M_DATA_BIT_DISABLE_16_23    0xffU
71514 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
71517 #define M_DQ_WR_OFFSET_N0    0xfU
71522 #define M_DQ_WR_OFFSET_N1    0xfU
71527 #define M_DQ_WR_OFFSET_N2    0xfU
71531 #define S_DQ_WR_OFFSET_N3    0
71532 #define M_DQ_WR_OFFSET_N3    0xfU
71536 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
71547 #define M_DP18_RX_PD    0x3U
71555 #define S_VCC_REG_PD    0
71559 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
71562 #define M_BIT_ENABLE_0_11    0xfffU
71566 #define S_BIT_ENABLE_12_15    0
71567 #define M_BIT_ENABLE_12_15    0xfU
71571 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
71605 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
71608 #define M_ADR_DELAY_BITS1_7    0x7fU
71612 #define S_ADR_DELAY_BITS9_15    0
71613 #define M_ADR_DELAY_BITS9_15    0x7fU
71617 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
71618 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
71619 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
71620 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
71621 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
71622 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
71623 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
71624 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
71627 #define M_ADR_TEST_LANE_PAIR_FAIL    0xffU
71636 #define M_DADR_TEST_MODE    0x3U
71656 #define S_ADR_TEST_CHECK_EN    0
71660 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
71663 #define M_EN_SLICE_N_WR_0    0xffU
71668 #define M_EN_SLICE_N_WR_FFE    0xfU
71672 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
71675 #define M_EN_SLICE_N_WR_1    0xffU
71679 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
71682 #define M_EN_SLICE_N_WR_2    0xffU
71686 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
71689 #define M_EN_SLICE_N_WR_3    0xffU
71693 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
71696 #define M_EN_SLICE_P_WR    0xffU
71701 #define M_EN_SLICE_P_WR_FFE    0xfU
71705 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
71706 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
71707 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
71708 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
71711 #define M_POST_CURSOR0    0xfU
71716 #define M_POST_CURSOR1    0xfU
71721 #define M_POST_CURSOR2    0xfU
71725 #define S_POST_CURSOR3    0
71726 #define M_POST_CURSOR3    0xfU
71730 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
71733 #define M_SLEW_CTL0    0xfU
71738 #define M_SLEW_CTL1    0xfU
71743 #define M_SLEW_CTL2    0xfU
71747 #define S_SLEW_CTL3    0
71748 #define M_SLEW_CTL3    0xfU
71752 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
71755 #define M_SLICE_SEL_REG_BITS0_1    0x3U
71760 #define M_SLICE_SEL_REG_BITS2_3    0x3U
71765 #define M_SLICE_SEL_REG_BITS4_5    0x3U
71770 #define M_SLICE_SEL_REG_BITS6_7    0x3U
71775 #define M_SLICE_SEL_REG_BITS8_9    0x3U
71780 #define M_SLICE_SEL_REG_BITS10_11    0x3U
71785 #define M_SLICE_SEL_REG_BITS12_13    0x3U
71789 #define S_SLICE_SEL_REG_BITS14_15    0
71790 #define M_SLICE_SEL_REG_BITS14_15    0x3U
71794 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
71795 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
71798 #define M_POST_CUR_SEL_BITS0_1    0x3U
71803 #define M_POST_CUR_SEL_BITS2_3    0x3U
71808 #define M_POST_CUR_SEL_BITS4_5    0x3U
71813 #define M_POST_CUR_SEL_BITS6_7    0x3U
71818 #define M_POST_CUR_SEL_BITS8_9    0x3U
71823 #define M_POST_CUR_SEL_BITS10_11    0x3U
71828 #define M_POST_CUR_SEL_BITS12_13    0x3U
71832 #define S_POST_CUR_SEL_BITS14_15    0
71833 #define M_POST_CUR_SEL_BITS14_15    0x3U
71837 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
71838 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
71841 #define M_SLEW_CTL_SEL_BITS0_1    0x3U
71846 #define M_SLEW_CTL_SEL_BITS2_3    0x3U
71851 #define M_SLEW_CTL_SEL_BITS4_5    0x3U
71856 #define M_SLEW_CTL_SEL_BITS6_7    0x3U
71861 #define M_SLEW_CTL_SEL_BITS8_9    0x3U
71866 #define M_SLEW_CTL_SEL_BITS10_11    0x3U
71871 #define M_SLEW_CTL_SEL_BITS12_13    0x3U
71875 #define S_SLEW_CTL_SEL_BITS14_15    0
71876 #define M_SLEW_CTL_SEL_BITS14_15    0x3U
71880 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
71881 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
71884 #define M_ADR_LANE_0_11_PD    0xfffU
71888 #define S_ADR_LANE_12_15_PD    0
71889 #define M_ADR_LANE_12_15_PD    0xfU
71893 #define A_T6_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45800
71894 #define A_T6_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45804
71895 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY0 0x45810
71896 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY1 0x45814
71897 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY2 0x45818
71898 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY3 0x4581c
71899 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY4 0x45820
71900 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY5 0x45824
71901 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY6 0x45828
71902 #define A_T6_MC_ADR_DDRPHY_ADR_DELAY7 0x4582c
71903 #define A_T6_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45830
71906 #define M_ADR_TEST_MODE    0x3U
71910 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45840
71911 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45844
71912 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45848
71913 #define A_T6_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4584c
71914 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45850
71915 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45854
71916 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45858
71917 #define A_T6_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4585c
71918 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45860
71919 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45868
71920 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45880
71921 #define A_T6_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45884
71922 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x458a0
71923 #define A_T6_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x458a4
71924 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x458a8
71925 #define A_T6_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x458ac
71926 #define A_T6_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x458b0
71927 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
71930 #define M_PLL_TUNE_0_2    0x7U
71935 #define M_PLL_TUNECP_0_2    0x7U
71940 #define M_PLL_TUNEF_0_5    0x3fU
71945 #define M_PLL_TUNEVCO_0_1    0x3U
71949 #define S_PLL_PLLXTR_0_1    0
71950 #define M_PLL_PLLXTR_0_1    0x3U
71954 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0 0x460c0
71955 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
71958 #define M_PLL_TUNETDIV_0_2    0x7U
71963 #define M_PLL_TUNEMDIV_0_1    0x3U
71972 #define M_VREG_RANGE_0_1    0x3U
71981 #define M_VREG_VCCTUNE_0_1    0x3U
71986 #define M_INTERP_SIG_SLEW_0_3    0xfU
71990 #define S_ANALOG_WRAPON    0
71994 #define A_MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1 0x460c4
71995 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
72002 #define M_SYSCLK_ROT_OVERRIDE    0x7fU
72030 #define S_CE0DLTVCC    0
72031 #define M_CE0DLTVCC    0x3U
72035 #define A_MC_DDRPHY_AD32S_SYSCLK_CNTL_PR 0x460c8
72036 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
72039 #define M_TSYS_WRCLK    0x7fU
72043 #define A_MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
72044 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
72051 #define M_SYSCLK_ROT    0x7fU
72064 #define M_SLEW_DONE_STATUS    0x3U
72068 #define S_SLEW_CNTL    0
72069 #define M_SLEW_CNTL    0xfU
72073 #define A_MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO 0x460d0
72074 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
72089 #define M_HS_PROBE_A_SEL_    0xfU
72094 #define M_HS_PROBE_B_SEL_    0xfU
72110 #define S_ATEST1CTL3    0
72114 #define A_MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL 0x460d4
72121 #define M_AD32S_HS_PROBE_A_SEL    0xfU
72126 #define M_AD32S_HS_PROBE_B_SEL    0xfU
72130 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
72132 #define S_GIANT_MUX_TEST_RESULTS    0
72133 #define M_GIANT_MUX_TEST_RESULTS    0xffffU
72137 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0 0x460d8
72139 #define S_OUTPUT_DRIVER_FORCE_VALUE    0
72140 #define M_OUTPUT_DRIVER_FORCE_VALUE    0xffffU
72144 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
72145 #define A_MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1 0x460dc
72146 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
72161 #define M_SYSCLK_CLK_GATE    0x3U
72177 #define S_DVCC_REG_PD    0
72181 #define A_MC_DDRPHY_AD32S_POWERDOWN_1 0x460e0
72182 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
72197 #define M_SLEW_CAL_OVERRIDE    0xfU
72201 #define S_SLEW_TARGET_PR_OFFSET    0
72202 #define M_SLEW_TARGET_PR_OFFSET    0x1fU
72206 #define A_MC_DDRPHY_AD32S_SLEW_CAL_CNTL 0x460e4
72207 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
72210 #define M_DP18_PLL_LOCK    0x7fffU
72214 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
72217 #define M_AD32S_PLL_LOCK    0x3U
72221 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
72224 #define M_RANK_PAIR0_PRI    0x7U
72233 #define M_RANK_PAIR0_SEC    0x7U
72242 #define M_RANK_PAIR1_PRI    0x7U
72251 #define M_RANK_PAIR1_SEC    0x7U
72255 #define S_RANK_PAIR1_SEC_V    0
72259 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
72262 #define M_RANK_PAIR2_PRI    0x7U
72271 #define M_RANK_PAIR2_SEC    0x7U
72280 #define M_RANK_PAIR3_PRI    0x7U
72289 #define M_RANK_PAIR3_SEC    0x7U
72293 #define S_RANK_PAIR3_SEC_V    0
72297 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
72299 #define S_PERIODIC_BASE_CNTR0    0
72300 #define M_PERIODIC_BASE_CNTR0    0xffffU
72304 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
72310 #define S_PERIODIC_RELOAD_VALUE0    0
72311 #define M_PERIODIC_RELOAD_VALUE0    0x7fffU
72315 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
72317 #define S_PERIODIC_BASE_CNTR1    0
72318 #define M_PERIODIC_BASE_CNTR1    0xffffU
72322 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
72324 #define S_PERIODIC_CAL_TIMER    0
72325 #define M_PERIODIC_CAL_TIMER    0xffffU
72329 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
72331 #define S_PERIODIC_TIMER_RELOAD_VALUE    0
72332 #define M_PERIODIC_TIMER_RELOAD_VALUE    0xffffU
72336 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
72338 #define S_PERIODIC_ZCAL_TIMER    0
72339 #define M_PERIODIC_ZCAL_TIMER    0xffffU
72343 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
72344 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
72347 #define M_PER_ENA_RANK_PAIR    0xfU
72372 #define M_PER_NEXT_RANK_PAIR    0x3U
72396 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
72399 #define M_PROTOCOL_DDR    0xfU
72420 #define M_RANK_OVERRIDE_VALUE    0x7U
72437 #define M_DDRPHY_PROTOCOL    0xfU
72449 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
72452 #define M_WRITE_LATENCY_OFFSET    0xfU
72457 #define M_READ_LATENCY_OFFSET    0xfU
72478 #define M_MEMORY_TYPE    0x7U
72486 #define A_MC_DDRPHY_PC_RESETS 0x47038
72496 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
72499 #define M_PER_ZCAL_ENA_RANK    0xffU
72504 #define M_PER_ZCAL_NEXT_RANK    0x7U
72512 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
72547 #define M_RANK_GROUPING    0x3U
72571 #define S_ADDR_MIRROR_BG0_BG1    0
72575 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
72601 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
72627 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
72630 #define M_PVTP    0x1fU
72635 #define M_PVTN    0x1fU
72647 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
72654 #define M_VREFDQ0D    0xfU
72663 #define M_VREFDQ1D    0xfU
72675 #define S_ANALOG_PD_DIV    0
72676 #define M_ANALOG_PD_DIV    0x3U
72680 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
72730 #define S_ENA_RANK_PAIR    0
72731 #define M_ENA_RANK_PAIR    0xfU
72735 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
72738 #define M_REFRESH_COUNT    0xfU
72743 #define M_REFRESH_CONTROL    0x3U
72751 #define S_REFRESH_INTERVAL    0
72752 #define M_REFRESH_INTERVAL    0x7fU
72756 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
72802 #define S_ERROR_RANK_PAIR    0
72803 #define M_ERROR_RANK_PAIR    0xfU
72807 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
72810 #define M_INIT_CAL_COMPLETE    0xfU
72818 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
72864 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
72865 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
72867 #define S_MODEREGISTER0VALUE    0
72868 #define M_MODEREGISTER0VALUE    0xffffU
72872 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
72874 #define S_MODEREGISTER1VALUE    0
72875 #define M_MODEREGISTER1VALUE    0xffffU
72879 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
72881 #define S_MODEREGISTER2VALUE    0
72882 #define M_MODEREGISTER2VALUE    0xffffU
72886 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
72888 #define S_MODEREGISTER3VALUE    0
72889 #define M_MODEREGISTER3VALUE    0xffffU
72893 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
72894 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
72895 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
72896 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
72898 #define S_MODE_REGISTER_3_VALUE    0
72899 #define M_MODE_REGISTER_3_VALUE    0xffffU
72903 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
72905 #define S_DRD_WR_DATA_REG    0
72906 #define M_DRD_WR_DATA_REG    0xffffU
72910 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
72911 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
72922 #define M_MR_MASK_EN    0xfU
72950 #define S_X16_DEVICE    0
72954 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
72955 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
72956 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
72957 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
72958 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
72959 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
72974 #define M_MULTIPLE_REQ_SOURCE    0x7U
72979 #define M_INVALID_REQTYPE    0xfU
72984 #define M_INVALID_REQ_SOURCE    0x7U
72988 #define S_EARLY_REQ_SOURCE    0
72989 #define M_EARLY_REQ_SOURCE    0x7U
72993 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
73007 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
73010 #define M_ODT_WR_VALUES_BITS0_7    0xffU
73014 #define S_ODT_WR_VALUES_BITS8_15    0
73015 #define M_ODT_WR_VALUES_BITS8_15    0xffU
73019 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
73020 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
73021 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
73022 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
73025 #define M_ODT_RD_VALUES_X2    0xffU
73029 #define S_ODT_RD_VALUES_X2PLUS1    0
73030 #define M_ODT_RD_VALUES_X2PLUS1    0xffU
73034 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
73035 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
73036 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
73037 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
73040 #define M_TMOD_CYCLES    0xfU
73045 #define M_TRCD_CYCLES    0xfU
73050 #define M_TRP_CYCLES    0xfU
73054 #define S_TRFC_CYCLES    0
73055 #define M_TRFC_CYCLES    0xfU
73059 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
73062 #define M_TZQINIT_CYCLES    0xfU
73067 #define M_TZQCS_CYCLES    0xfU
73072 #define M_TWLDQSEN_CYCLES    0xfU
73076 #define S_TWRMRD_CYCLES    0
73077 #define M_TWRMRD_CYCLES    0xfU
73081 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
73084 #define M_TODTLON_OFF_CYCLES    0xfU
73089 #define M_TRC_CYCLES    0xfU
73094 #define M_TMRSC_CYCLES    0xfU
73098 #define S_MRS_CMD_SPACE    0
73099 #define M_MRS_CMD_SPACE    0xfU
73103 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
73106 #define M_GLOBAL_PHY_OFFSET    0xfU
73138 #define S_STAGGERED_PATTERN    0
73146 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
73149 #define M_OUTER_LOOP_CNT    0x3fffU
73153 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
73156 #define M_CONSEQ_PASS    0x1fU
73161 #define M_BURST_WINDOW    0x3U
73173 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
73179 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
73185 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
73188 #define M_FINE_CAL_STEP_SIZE    0x7U
73193 #define M_COARSE_CAL_STEP_SIZE    0xfU
73198 #define M_DQ_SEL_QUAD    0x3U
73203 #define M_DQ_SEL_LANE    0x7U
73207 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
73208 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
73211 #define M_TWLO_TWLOE    0xffU
73220 #define M_FW_WR_RD    0x3fU
73224 #define S_CUSTOM_INIT_WRITE    0
73228 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
73231 #define M_BIG_STEP    0xfU
73236 #define M_SMALL_STEP    0x7U
73241 #define M_WR_PRE_DLY    0x3fU
73245 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
73248 #define M_NUM_VALID_SAMPLES    0xfU
73253 #define M_FW_RD_WR    0x3fU
73257 #define S_EN_RESET_WR_DELAY_WL    0
73262 #define M_TWR_MPR    0xfU
73266 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
73272 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
73278 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
73285 #define M_MRS_CMD_DQ_ON    0x3fU
73290 #define M_MRS_CMD_DQ_OFF    0x3fU
73294 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
73304 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
73323 #define M_DEBUG_BUS_SEL_HI    0xfU
73327 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
73337 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
73347 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
73409 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
73443 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
73446 #define M_ATEST_CNTL    0x3fU
73450 #define A_MC_DDRPHY_APB_MTCTL_REG0 0x47820
73465 #define M_MT_GLOBAL_PHY_OFFSET    0xfU
73470 #define M_MT_DQ_SEL_QUAD    0x3U
73486 #define A_MC_DDRPHY_APB_MTCTL_REG1 0x47824
73493 #define M_MT_PVTP    0x1fU
73498 #define M_MT_PVTN    0x1fU
73502 #define A_MC_DDRPHY_APB_MTSTAT_REG0 0x47828
73503 #define A_MC_DDRPHY_APB_MTSTAT_REG1 0x4782c
73509 #define S_MT_DP18_PLL_LOCK_SUM    0
73514 #define MC_1_BASE_ADDR 0x48000
73517 #define EDC_T50_BASE_ADDR 0x50000
73519 #define A_EDC_H_REF 0x50000
73533 #define A_EDC_H_BIST_CMD 0x50004
73534 #define A_EDC_H_BIST_CMD_ADDR 0x50008
73535 #define A_EDC_H_BIST_CMD_LEN 0x5000c
73536 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
73537 #define A_EDC_H_BIST_USER_WDATA0 0x50014
73538 #define A_EDC_H_BIST_USER_WDATA1 0x50018
73539 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
73540 #define A_EDC_H_BIST_NUM_ERR 0x50020
73541 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
73542 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
73543 #define A_EDC_H_PAR_ENABLE 0x50070
73545 #define S_PERR_PAR_ENABLE    0
73549 #define A_EDC_H_INT_ENABLE 0x50074
73550 #define A_EDC_H_INT_CAUSE 0x50078
73564 #define A_EDC_H_ECC_STATUS 0x5007c
73565 #define A_EDC_H_ECC_ERR_SEL 0x50080
73567 #define S_CFG    0
73568 #define M_CFG    0x3U
73572 #define A_EDC_H_ECC_ERR_ADDR 0x50084
73574 #define S_ECC_ADDR    0
73575 #define M_ECC_ADDR    0x7fffffU
73579 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
73580 #define A_EDC_H_BIST_CRC_SEED 0x50400
73583 #define EDC_T51_BASE_ADDR 0x50800
73586 #define HMA_T5_BASE_ADDR 0x51000
73588 #define A_HMA_TABLE_ACCESS 0x51000
73598 #define S_L_SEL    0
73599 #define M_L_SEL    0xfU
73603 #define A_HMA_TABLE_LINE0 0x51004
73605 #define S_CLIENT_EN    0
73606 #define M_CLIENT_EN    0x1fffU
73610 #define A_HMA_TABLE_LINE1 0x51008
73611 #define A_HMA_TABLE_LINE2 0x5100c
73612 #define A_HMA_TABLE_LINE3 0x51010
73613 #define A_HMA_TABLE_LINE4 0x51014
73614 #define A_HMA_TABLE_LINE5 0x51018
73617 #define M_FID    0x7ffU
73629 #define A_HMA_COOKIE 0x5101c
73636 #define M_C_FID    0x7ffU
73641 #define M_C_VAL    0x3ffU
73645 #define S_C_SEL    0
73646 #define M_C_SEL    0xfU
73650 #define A_HMA_PAR_ENABLE 0x51300
73651 #define A_HMA_INT_ENABLE 0x51304
73652 #define A_HMA_INT_CAUSE 0x51308
73655 #define EDC_T60_BASE_ADDR 0x50000
73658 #define M_QDR_CLKPHASE    0x7U
73663 #define M_MAXOPSPERTRC    0x7U
73668 #define M_NUMPIPESTAGES    0x3U
73673 #define M_DRAMREFENABLE    0x3U
73677 #define A_EDC_H_DBG_MA_CMD_INTF 0x50300
73680 #define M_MCMDADDR    0xfffffU
73685 #define M_MCMDLEN    0x7fU
73705 #define S_MCMDVLD    0
73709 #define A_EDC_H_DBG_MA_WDATA_INTF 0x50304
73719 #define S_MWDATA    0
73720 #define M_MWDATA    0x3fffffffU
73724 #define A_EDC_H_DBG_MA_RDATA_INTF 0x50308
73734 #define S_MRSPDATA    0
73735 #define M_MRSPDATA    0x3fffffffU
73739 #define A_EDC_H_DBG_BIST_CMD_INTF 0x5030c
73742 #define M_BCMDADDR    0x7fffffU
73747 #define M_BCMDLEN    0x3fU
73759 #define S_BCMDVLD    0
73763 #define A_EDC_H_DBG_BIST_WDATA_INTF 0x50310
73773 #define S_BWDATA    0
73774 #define M_BWDATA    0x3fffffffU
73778 #define A_EDC_H_DBG_BIST_RDATA_INTF 0x50314
73788 #define S_BRSPDATA    0
73789 #define M_BRSPDATA    0x3fffffffU
73793 #define A_EDC_H_DBG_EDRAM_CMD_INTF 0x50318
73796 #define M_EDRAMADDR    0xffffU
73801 #define M_EDRAMDWSN    0xffU
73806 #define M_EDRAMCRA    0x7U
73826 #define S_EDRAM0RDENLO    0
73830 #define A_EDC_H_DBG_EDRAM_WDATA_INTF 0x5031c
73833 #define M_EDRAMWDATA    0x7fffffU
73837 #define S_EDRAMWBYTEEN    0
73838 #define M_EDRAMWBYTEEN    0x1ffU
73842 #define A_EDC_H_DBG_EDRAM0_RDATA_INTF 0x50320
73843 #define A_EDC_H_DBG_EDRAM1_RDATA_INTF 0x50324
73844 #define A_EDC_H_DBG_MA_WR_REQ_CNT 0x50328
73845 #define A_EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT 0x5032c
73846 #define A_EDC_H_DBG_MA_WR_DAT_CYC_CNT 0x50330
73847 #define A_EDC_H_DBG_MA_RD_REQ_CNT 0x50334
73848 #define A_EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT 0x50338
73849 #define A_EDC_H_DBG_MA_RD_DAT_CYC_CNT 0x5033c
73850 #define A_EDC_H_DBG_BIST_WR_REQ_CNT 0x50340
73851 #define A_EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT 0x50344
73852 #define A_EDC_H_DBG_BIST_WR_DAT_CYC_CNT 0x50348
73853 #define A_EDC_H_DBG_BIST_RD_REQ_CNT 0x5034c
73854 #define A_EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT 0x50350
73855 #define A_EDC_H_DBG_BIST_RD_DAT_CYC_CNT 0x50354
73856 #define A_EDC_H_DBG_EDRAM0_WR_REQ_CNT 0x50358
73857 #define A_EDC_H_DBG_EDRAM0_RD_REQ_CNT 0x5035c
73858 #define A_EDC_H_DBG_EDRAM0_RMW_CNT 0x50360
73859 #define A_EDC_H_DBG_EDRAM1_WR_REQ_CNT 0x50364
73860 #define A_EDC_H_DBG_EDRAM1_RD_REQ_CNT 0x50368
73861 #define A_EDC_H_DBG_EDRAM1_RMW_CNT 0x5036c
73862 #define A_EDC_H_DBG_EDRAM_REF_BURST_CNT 0x50370
73863 #define A_EDC_H_DBG_FIFO_STATUS 0x50374
73902 #define M_RDDQ_RDCNT    0x1fU
73918 #define S_STG_WRDQ_NOTEMPTY    0
73922 #define A_EDC_H_DBG_FSM_STATE 0x50378
73928 #define S_CMDFSM    0
73929 #define M_CMDFSM    0x7U
73933 #define A_EDC_H_DBG_STALL_CYCLES 0x5037c
74011 #define S_DEAD_CYCLE1_POST_REF_RMW    0
74015 #define A_EDC_H_DBG_CMD_QUEUE 0x50380
74030 #define M_ECMDLEN    0x7fU
74034 #define S_ECMDADDR    0
74035 #define M_ECMDADDR    0x3fffffU
74039 #define A_EDC_H_DBG_REFRESH 0x50384
74050 #define M_REFPTR    0x7U
74054 #define S_REFCNT    0
74055 #define M_REFCNT    0xffU
74059 #define A_EDC_H_PAR_CAUSE 0x50404
74089 #define S_RDDQ_PARERR_CAUSE    0
74094 #define EDC_T61_BASE_ADDR 0x50800
74097 #define HMA_T6_BASE_ADDR 0x51000
74099 #define S_T7_CLIENT_EN    0
74100 #define M_T7_CLIENT_EN    0x7fffU
74105 #define M_TPH    0x3U
74113 #define S_DCA    0
74114 #define M_DCA    0x7ffU
74118 #define A_HMA_CFG 0x51020
74132 #define A_HMA_TLB_ACCESS 0x51028
74142 #define S_E_SEL    0
74143 #define M_E_SEL    0x1fU
74147 #define A_HMA_TLB_BITS 0x5102c
74150 #define M_VA    0xfffffU
74166 #define S_REGION    0
74167 #define M_REGION    0x3U
74172 #define M_T7_VA    0xffffffU
74176 #define A_HMA_TLB_DESC_0_H 0x51030
74177 #define A_HMA_TLB_DESC_0_L 0x51034
74178 #define A_HMA_TLB_DESC_1_H 0x51038
74179 #define A_HMA_TLB_DESC_1_L 0x5103c
74180 #define A_HMA_TLB_DESC_2_H 0x51040
74181 #define A_HMA_TLB_DESC_2_L 0x51044
74182 #define A_HMA_TLB_DESC_3_H 0x51048
74183 #define A_HMA_TLB_DESC_3_L 0x5104c
74184 #define A_HMA_TLB_DESC_4_H 0x51050
74185 #define A_HMA_TLB_DESC_4_L 0x51054
74186 #define A_HMA_TLB_DESC_5_H 0x51058
74187 #define A_HMA_TLB_DESC_5_L 0x5105c
74188 #define A_HMA_TLB_DESC_6_H 0x51060
74189 #define A_HMA_TLB_DESC_6_L 0x51064
74190 #define A_HMA_TLB_DESC_7_H 0x51068
74191 #define A_HMA_TLB_DESC_7_L 0x5106c
74192 #define A_HMA_REG0_MIN 0x51070
74195 #define M_ADDR0_MIN    0xfffffU
74200 #define M_REG0MINADDR0MIN    0xffffffU
74204 #define A_HMA_REG0_MAX 0x51074
74207 #define M_ADDR0_MAX    0xfffffU
74212 #define M_REG0MAXADDR0MAX    0xffffffU
74216 #define A_HMA_REG0_MASK 0x51078
74219 #define M_PAGE_SIZE0    0xfffffU
74223 #define A_HMA_REG0_BASE 0x5107c
74224 #define A_HMA_REG0_BASE_LSB 0x5107c
74225 #define A_HMA_REG1_MIN 0x51080
74228 #define M_ADDR1_MIN    0xfffffU
74233 #define M_REG1MINADDR1MIN    0xffffffU
74237 #define A_HMA_REG1_MAX 0x51084
74240 #define M_ADDR1_MAX    0xfffffU
74245 #define M_REG1MAXADDR1MAX    0xffffffU
74249 #define A_HMA_REG1_MASK 0x51088
74252 #define M_PAGE_SIZE1    0xfffffU
74256 #define A_HMA_REG1_BASE 0x5108c
74257 #define A_HMA_REG1_BASE_LSB 0x5108c
74258 #define A_HMA_REG2_MIN 0x51090
74261 #define M_ADDR2_MIN    0xfffffU
74266 #define M_REG2MINADDR2MIN    0xffffffU
74270 #define A_HMA_REG2_MAX 0x51094
74273 #define M_ADDR2_MAX    0xfffffU
74278 #define M_REG2MAXADDR2MAX    0xffffffU
74282 #define A_HMA_REG2_MASK 0x51098
74285 #define M_PAGE_SIZE2    0xfffffU
74289 #define A_HMA_REG2_BASE 0x5109c
74290 #define A_HMA_REG2_BASE_LSB 0x5109c
74291 #define A_HMA_REG3_MIN 0x510a0
74294 #define M_ADDR3_MIN    0xfffffU
74299 #define M_REG3MINADDR3MIN    0xffffffU
74303 #define A_HMA_REG3_MAX 0x510a4
74306 #define M_ADDR3_MAX    0xfffffU
74311 #define M_REG3MAXADDR3MAX    0xffffffU
74315 #define A_HMA_REG3_MASK 0x510a8
74318 #define M_PAGE_SIZE3    0xfffffU
74322 #define A_HMA_REG3_BASE 0x510ac
74323 #define A_HMA_REG3_BASE_LSB 0x510ac
74324 #define A_HMA_SW_SYNC 0x510b0
74334 #define A_HMA_GC_MODE_SEL 0x510b4
74337 #define M_MODE_SEL    0x3U
74345 #define S_CLEAR_REQ    0
74349 #define A_HMA_REG0_BASE_MSB 0x510b8
74351 #define S_BASE0_MSB    0
74352 #define M_BASE0_MSB    0xfU
74356 #define A_HMA_REG1_BASE_MSB 0x510bc
74358 #define S_BASE1_MSB    0
74359 #define M_BASE1_MSB    0xfU
74363 #define A_HMA_REG2_BASE_MSB 0x510c0
74365 #define S_BASE2_MSB    0
74366 #define M_BASE2_MSB    0xfU
74370 #define A_HMA_REG3_BASE_MSB 0x510c4
74372 #define S_BASE3_MSB    0
74373 #define M_BASE3_MSB    0xfU
74377 #define A_HMA_DBG_CTL 0x51104
74378 #define A_HMA_DBG_DATA 0x51108
74379 #define A_HMA_H_BIST_CMD 0x51200
74380 #define A_HMA_H_BIST_CMD_ADDR 0x51204
74381 #define A_HMA_H_BIST_CMD_LEN 0x51208
74382 #define A_HMA_H_BIST_DATA_PATTERN 0x5120c
74383 #define A_HMA_H_BIST_USER_WDATA0 0x51210
74384 #define A_HMA_H_BIST_USER_WDATA1 0x51214
74385 #define A_HMA_H_BIST_USER_WDATA2 0x51218
74386 #define A_HMA_H_BIST_NUM_ERR 0x5121c
74387 #define A_HMA_H_BIST_ERR_FIRST_ADDR 0x51220
74388 #define A_HMA_H_BIST_STATUS_RDATA 0x51224
74389 #define A_HMA_H_BIST_CRC_SEED 0x5126c
74390 #define A_HMA_TABLE_LINE1_MSB 0x51270
74392 #define S_STARTA    0
74393 #define M_STARTA    0xfU
74397 #define A_HMA_TABLE_LINE2_MSB 0x51274
74399 #define S_ENDA    0
74400 #define M_ENDA    0xfU
74460 #define A_HMA_MA_MST_ERR 0x5130c
74461 #define A_HMA_RTF_ERR 0x51310
74462 #define A_HMA_OTF_ERR 0x51314
74463 #define A_HMA_IDTF_ERR 0x51318
74464 #define A_HMA_EXIT_TF 0x5131c
74478 #define A_HMA_LOCAL_DEBUG_CFG 0x51320
74479 #define A_HMA_LOCAL_DEBUG_RPT 0x51324
74480 #define A_HMA_DEBUG_FSM_0 0xa000
74483 #define M_EDC_FSM    0x1fU
74488 #define M_RAS_FSM_SLV    0x7U
74493 #define M_FC_FSM    0x1fU
74498 #define M_COOKIE_ARB_FSM    0x3U
74503 #define M_PCIE_CHUNK_FSM    0x3U
74508 #define M_WTRANSFER_FSM    0x3U
74513 #define M_WD_FSM    0x3U
74517 #define S_RD_FSM    0
74518 #define M_RD_FSM    0x3U
74522 #define A_HMA_DEBUG_FSM_1 0xa001
74525 #define M_SYNC_FSM    0x3ffU
74530 #define M_OCHK_FSM    0x3U
74535 #define M_TLB_FSM    0xfU
74539 #define S_PIO_FSM    0
74540 #define M_PIO_FSM    0x1fU
74544 #define A_HMA_DEBUG_PCIE_INTF 0xa002
74595 #define M_PCIE_LEN    0xffU
74631 #define S_PCIE_TRRERR    0
74635 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_LO 0xa003
74636 #define A_HMA_DEBUG_PCIE_ADDR_INTERNAL_HI 0xa004
74637 #define A_HMA_DEBUG_PCIE_REQ_DATA_EXTERNAL 0xa005
74640 #define M_REQDATA2    0xffU
74645 #define M_REQDATA1    0x7U
74649 #define S_REQDATA0    0
74650 #define M_REQDATA0    0x1fffffU
74654 #define A_HMA_DEBUG_PCIE_RSP_DATA_EXTERNAL 0xa006
74657 #define M_RSPDATA3    0xffU
74662 #define M_RSPDATA2    0xffU
74667 #define M_RSPDATA1    0xffU
74671 #define S_RSPDATA0    0
74672 #define M_RSPDATA0    0xffU
74676 #define A_HMA_DEBUG_MA_SLV_CTL 0xa007
74683 #define M_MA_CLNT    0xfU
74692 #define M_MA_LEN    0xffU
74716 #define S_MAS_TLB_ERR    0
74720 #define A_HMA_DEBUG_MA_SLV_ADDR_INTERNAL 0xa008
74721 #define A_HMA_DEBUG_TLB_HIT_ENTRY 0xa009
74722 #define A_HMA_DEBUG_TLB_HIT_CNT 0xa00a
74723 #define A_HMA_DEBUG_TLB_MISS_CNT 0xa00b
74724 #define A_HMA_DEBUG_PAGE_TBL_LKP_CTL 0xa00c
74731 #define M_LKP_DESC_SEL    0x7U
74735 #define S_LKP_RSP_VLD    0
74739 #define A_HMA_DEBUG_PAGE_TBL_LKP_REQ_ADDR 0xa00d
74740 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_0 0xa00e
74741 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_1 0xa00f
74742 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_2 0xa010
74743 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_3 0xa011
74744 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_4 0xa012
74745 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_5 0xa013
74746 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_6 0xa014
74747 #define A_HMA_DEBUG_PAGE_TBL_LKP_RSP_7 0xa015
74748 #define A_HMA_DEBUG_PHYS_DESC_INTERNAL_LO 0xa016
74749 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_LO 0xa017
74750 #define A_HMA_DEBUG_PCIE_RD_REQ_CNT_HI 0xa018
74751 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_LO 0xa019
74752 #define A_HMA_DEBUG_PCIE_WR_REQ_CNT_HI 0xa01a
74753 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_LO 0xa01b
74754 #define A_HMA_DEBUG_PCIE_RD_DATA_CYC_CNT_HI 0xa01c
74755 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_LO 0xa01d
74756 #define A_HMA_DEBUG_PCIE_WR_DATA_CYC_CNT_HI 0xa01e
74757 #define A_HMA_DEBUG_PCIE_SOP_EOP_CNT 0xa01f
74760 #define M_WR_EOP_CNT    0xffU
74765 #define M_RD_SOP_CNT    0xffU
74769 #define S_RD_EOP_CNT    0
74770 #define M_RD_EOP_CNT    0xffU
74775 #define M_DEBUG_PCIE_SOP_EOP_CNTWR_EOP_CNT    0xffU
74780 #define M_DEBUG_PCIE_SOP_EOP_CNTRD_SOP_CNT    0xffU
74784 #define S_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0
74785 #define M_DEBUG_PCIE_SOP_EOP_CNTRD_EOP_CNT    0xffU
74790 #define MAC_T7_BASE_ADDR 0x38000
74793 #define M_T7_PORT_MAP    0x7U
74798 #define M_T7_SMUX_RX_LOOP    0xfU
74815 #define M_T7_SMUXTXSEL    0xfU
74820 #define M_T7_PORTSPEED    0xfU
74833 #define M_T7_LED1_CFG1    0x7U
74838 #define M_T7_LED0_CFG1    0x7U
74842 #define A_T7_MAC_PORT_MAGIC_MACID_LO 0x820
74843 #define A_T7_MAC_PORT_MAGIC_MACID_HI 0x824
74844 #define A_T7_MAC_PORT_LINK_STATUS 0x828
74854 #define A_T7_MAC_PORT_PERR_INT_EN_100G 0x82c
74940 #define S_PERR_PCSR_80_16_0    0
74944 #define A_T7_MAC_PORT_PERR_INT_CAUSE_100G 0x830
74945 #define A_T7_MAC_PORT_PERR_ENABLE_100G 0x834
74946 #define A_MAC_PORT_MAC10G100G_CONFIG_0 0x838
74953 #define M_PEER_DELAY    0x3fffffffU
74957 #define S_MODE1S_ENA    0
74961 #define A_MAC_PORT_MAC10G100G_CONFIG_1 0x83c
74972 #define M_TX_TS_ID    0xfffU
74981 #define M_XOFF_GEN    0xffU
74989 #define S_TX_LOC_FAULT    0
74993 #define A_MAC_PORT_MAC10G100G_CONFIG_2 0x840
74995 #define S_FF_TX_RX_TS_NS    0
74996 #define M_FF_TX_RX_TS_NS    0x3fffffffU
75000 #define A_MAC_PORT_MAC10G100G_STATUS 0x844
75039 #define M_PAUSE_ON    0xffU
75059 #define S_FF_RX_EMPTY    0
75063 #define A_MAC_PORT_MAC_AN_STATE_STATUS0 0x848
75078 #define M_AN_SELECT_AN    0x1fU
75098 #define S_AN_STATE    0
75099 #define M_AN_STATE    0xfU
75103 #define A_MAC_PORT_MAC_AN_STATE_STATUS1 0x84c
75104 #define A_T7_MAC_PORT_EPIO_DATA0 0x850
75105 #define A_T7_MAC_PORT_EPIO_DATA1 0x854
75106 #define A_T7_MAC_PORT_EPIO_DATA2 0x858
75107 #define A_T7_MAC_PORT_EPIO_DATA3 0x85c
75108 #define A_T7_MAC_PORT_EPIO_OP 0x860
75109 #define A_T7_MAC_PORT_WOL_STATUS 0x864
75110 #define A_T7_MAC_PORT_INT_EN 0x868
75184 #define S_MAC_RXFIFO_ERR_INT_EN    0
75188 #define A_T7_MAC_PORT_INT_CAUSE 0x86c
75262 #define S_MAC_RXFIFO_ERR_INT_CAUSE    0
75266 #define A_T7_MAC_PORT_PERR_INT_EN 0x870
75267 #define A_T7_MAC_PORT_PERR_INT_CAUSE 0x874
75268 #define A_T7_MAC_PORT_PERR_ENABLE 0x878
75269 #define A_T7_MAC_PORT_PERR_INJECT 0x87c
75272 #define M_T7_MEMSEL_PERR    0xffU
75276 #define A_T7_MAC_PORT_RUNT_FRAME 0x880
75277 #define A_T7_MAC_PORT_EEE_STATUS 0x884
75278 #define A_T7_MAC_PORT_TX_TS_ID 0x888
75284 #define A_T7_MAC_PORT_TX_TS_VAL_LO 0x88c
75285 #define A_T7_MAC_PORT_TX_TS_VAL_HI 0x890
75286 #define A_T7_MAC_PORT_EEE_CTL 0x894
75287 #define A_T7_MAC_PORT_EEE_TX_CTL 0x898
75288 #define A_T7_MAC_PORT_EEE_RX_CTL 0x89c
75289 #define A_T7_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x8a0
75290 #define A_T7_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x8a4
75291 #define A_T7_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x8a8
75292 #define A_T7_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x8b8
75293 #define A_T7_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x8bc
75294 #define A_T7_MAC_PORT_EEE_RX_10G_WF_TIMER 0x8c0
75295 #define A_T7_MAC_PORT_EEE_WF_COUNT 0x8cc
75296 #define A_MAC_PORT_WOL_EN 0x8d0
75302 #define S_WOL_INDICATOR    0
75306 #define A_MAC_PORT_INT_TRACE 0x8d4
75308 #define S_INTERRUPT    0
75309 #define M_INTERRUPT    0x7fffffffU
75313 #define A_MAC_PORT_TRACE_TS_LO 0x8d8
75314 #define A_MAC_PORT_TRACE_TS_HI 0x8dc
75315 #define A_MAC_PORT_MTIP_10G100G_REVISION 0x900
75318 #define M_VER_10G100G    0xffU
75322 #define S_REV_10G100G    0
75323 #define M_REV_10G100G    0xffU
75327 #define A_MAC_PORT_MTIP_10G100G_SCRATCH 0x904
75328 #define A_MAC_PORT_MTIP_10G100G_COMMAND_CONFIG 0x908
75346 #define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_0 0x90c
75347 #define A_MAC_PORT_MTIP_10G100G_MAC_ADDR_1 0x910
75348 #define A_MAC_PORT_MTIP_10G100G_FRM_LENGTH_TX_MTU 0x914
75349 #define A_MAC_PORT_MTIP_10G100G_RX_FIFO_SECTIONS 0x91c
75352 #define M_RX10G100G_EMPTY    0xffffU
75356 #define S_RX10G100G_AVAIL    0
75357 #define M_RX10G100G_AVAIL    0xffffU
75361 #define A_MAC_PORT_MTIP_10G100G_TX_FIFO_SECTIONS 0x920
75364 #define M_TX10G100G_EMPTY    0xffffU
75368 #define S_TX10G100G_AVAIL    0
75369 #define M_TX10G100G_AVAIL    0xffffU
75373 #define A_MAC_PORT_MTIP_10G100G_RX_FIFO_ALMOST_F_E 0x924
75374 #define A_MAC_PORT_MTIP_10G100G_TX_FIFO_ALMOST_F_E 0x928
75375 #define A_MAC_PORT_MTIP_10G100G_MDIO_CFG_STATUS 0x930
75376 #define A_MAC_PORT_MTIP_10G100G_MDIO_COMMAND 0x934
75377 #define A_MAC_PORT_MTIP_10G100G_MDIO_DATA 0x938
75378 #define A_MAC_PORT_MTIP_10G100G_MDIO_REGADDR 0x93c
75379 #define A_MAC_PORT_MTIP_10G100G_STATUS 0x940
75385 #define A_MAC_PORT_MTIP_10G100G_TX_IPG_LENGTH 0x944
75388 #define M_IPG_COMP_CNT    0xffffU
75393 #define M_AVG_IPG_LEN    0xfU
75397 #define S_DSBL_DIC    0
75401 #define A_MAC_PORT_MTIP_10G100G_CRC_MODE 0x948
75402 #define A_MAC_PORT_MTIP_10G100G_CL01_PAUSE_QUANTA 0x954
75403 #define A_MAC_PORT_MTIP_10G100G_CL23_PAUSE_QUANTA 0x958
75404 #define A_MAC_PORT_MTIP_10G100G_CL45_PAUSE_QUANTA 0x95c
75405 #define A_MAC_PORT_MTIP_10G100G_CL67_PAUSE_QUANTA 0x960
75406 #define A_MAC_PORT_MTIP_10G100G_CL01_QUANTA_THRESH 0x964
75407 #define A_MAC_PORT_MTIP_10G100G_CL23_QUANTA_THRESH 0x968
75408 #define A_MAC_PORT_MTIP_10G100G_CL45_QUANTA_THRESH 0x96c
75409 #define A_MAC_PORT_MTIP_10G100G_CL67_QUANTA_THRESH 0x970
75410 #define A_MAC_PORT_MTIP_10G100G_RX_PAUSE_STATUS 0x974
75411 #define A_MAC_PORT_MTIP_10G100G_TS_TIMESTAMP 0x97c
75412 #define A_MAC_PORT_MTIP_10G100G_XIF_MODE 0x980
75450 #define S_XGMII_ENA    0
75454 #define A_MAC_PORT_MTIP_CR4_0_CONTROL_1 0xa00
75455 #define A_MAC_PORT_MTIP_CR4_0_STATUS_1 0xa04
75461 #define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID0 0xa08
75463 #define S_CR4_0_DEVICE_ID0    0
75464 #define M_CR4_0_DEVICE_ID0    0xffffU
75468 #define A_MAC_PORT_MTIP_CR4_0_DEVICE_ID1 0xa0c
75470 #define S_CR4_0_DEVICE_ID1    0
75471 #define M_CR4_0_DEVICE_ID1    0xffffU
75475 #define A_MAC_PORT_MTIP_CR4_0_SPEED_ABILITY 0xa10
75485 #define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG1 0xa14
75486 #define A_MAC_PORT_MTIP_CR4_0_DEVICES_IN_PKG2 0xa18
75487 #define A_MAC_PORT_MTIP_CR4_0_CONTROL_2 0xa1c
75489 #define S_T7_PCS_TYPE_SELECTION    0
75490 #define M_T7_PCS_TYPE_SELECTION    0xfU
75494 #define A_MAC_PORT_MTIP_CR4_0_STATUS_2 0xa20
75504 #define A_MAC_PORT_MTIP_CR4_0_PKG_ID0 0xa38
75505 #define A_MAC_PORT_MTIP_CR4_0_PKG_ID1 0xa3c
75506 #define A_MAC_PORT_MTIP_CR4_0_EEE_CTRL 0xa50
75541 #define M_FAST_WAKE    0x1fU
75545 #define S_DEEP_SLEEP    0
75549 #define A_MAC_PORT_MTIP_CR4_0_WAKE_ERROR_COUNTER 0xa58
75551 #define S_WAKE_ERROR_COUNTER    0
75552 #define M_WAKE_ERROR_COUNTER    0x1ffffU
75556 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_1 0xa80
75558 #define S_CR4_0_BR_BLOCK_LOCK    0
75562 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_STATUS_2 0xa84
75563 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_0 0xa88
75565 #define S_SEED_A_0    0
75566 #define M_SEED_A_0    0xffffU
75570 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_1 0xa8c
75572 #define S_SEED_A_1    0
75573 #define M_SEED_A_1    0xffffU
75577 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_2 0xa90
75579 #define S_SEED_A_2    0
75580 #define M_SEED_A_2    0xffffU
75584 #define A_MAC_PORT_MTIP_CR4_0_SEED_A_3 0xa94
75586 #define S_SEED_A_3    0
75587 #define M_SEED_A_3    0xffffU
75591 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_0 0xa98
75593 #define S_SEED_B_0    0
75594 #define M_SEED_B_0    0xffffU
75598 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_1 0xa9c
75600 #define S_SEED_B_1    0
75601 #define M_SEED_B_1    0xffffU
75605 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_2 0xaa0
75607 #define S_SEED_B_2    0
75608 #define M_SEED_B_2    0xffffU
75612 #define A_MAC_PORT_MTIP_CR4_0_SEED_B_3 0xaa4
75614 #define S_SEED_B_3    0
75615 #define M_SEED_B_3    0xffffU
75619 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_PATTERN_CONTROL 0xaa8
75625 #define A_MAC_PORT_MTIP_CR4_0_BASE_R_TEST_ERR_CNT 0xaac
75626 #define A_MAC_PORT_MTIP_CR4_0_BER_HIGH_ORDER_CNT 0xab0
75628 #define S_BASE_R_BER_HIGH_ORDER_CNT    0
75629 #define M_BASE_R_BER_HIGH_ORDER_CNT    0xffffU
75633 #define A_MAC_PORT_MTIP_CR4_0_ERR_BLK_HIGH_ORDER_CNT 0xab4
75634 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_1 0xac8
75635 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_2 0xacc
75636 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_3 0xad0
75637 #define A_MAC_PORT_MTIP_CR4_0_MULTI_LANE_ALIGN_STATUS_4 0xad4
75638 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_0 0xad8
75639 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_1 0xadc
75640 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_2 0xae0
75641 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_3 0xae4
75642 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_4 0xae8
75643 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_5 0xaec
75644 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_6 0xaf0
75645 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_7 0xaf4
75646 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_8 0xaf8
75647 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_9 0xafc
75648 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_10 0xb00
75649 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_11 0xb04
75650 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_12 0xb08
75651 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_13 0xb0c
75652 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_14 0xb10
75653 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_15 0xb14
75654 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_16 0xb18
75655 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_17 0xb1c
75656 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_18 0xb20
75657 #define A_MAC_PORT_MTIP_CR4_0_BIP_ERR_CNTLANE_19 0xb24
75658 #define A_MAC_PORT_MTIP_CR4_0_LANE_0_MAPPING 0xb28
75659 #define A_MAC_PORT_MTIP_CR4_0_LANE_1_MAPPING 0xb2c
75660 #define A_MAC_PORT_MTIP_CR4_0_LANE_2_MAPPING 0xb30
75661 #define A_MAC_PORT_MTIP_CR4_0_LANE_3_MAPPING 0xb34
75662 #define A_MAC_PORT_MTIP_CR4_0_LANE_4_MAPPING 0xb38
75663 #define A_MAC_PORT_MTIP_CR4_0_LANE_5_MAPPING 0xb3c
75664 #define A_MAC_PORT_MTIP_CR4_0_LANE_6_MAPPING 0xb40
75665 #define A_MAC_PORT_MTIP_CR4_0_LANE_7_MAPPING 0xb44
75666 #define A_MAC_PORT_MTIP_CR4_0_LANE_8_MAPPING 0xb48
75667 #define A_MAC_PORT_MTIP_CR4_0_LANE_9_MAPPING 0xb4c
75668 #define A_MAC_PORT_MTIP_CR4_0_LANE_10_MAPPING 0xb50
75669 #define A_MAC_PORT_MTIP_CR4_0_LANE_11_MAPPING 0xb54
75670 #define A_MAC_PORT_MTIP_CR4_0_LANE_12_MAPPING 0xb58
75671 #define A_MAC_PORT_MTIP_CR4_0_LANE_13_MAPPING 0xb5c
75672 #define A_MAC_PORT_MTIP_CR4_0_LANE_14_MAPPING 0xb60
75673 #define A_MAC_PORT_MTIP_CR4_0_LANE_15_MAPPING 0xb64
75674 #define A_MAC_PORT_MTIP_CR4_0_LANE_16_MAPPING 0xb68
75675 #define A_MAC_PORT_MTIP_CR4_0_LANE_17_MAPPING 0xb6c
75676 #define A_MAC_PORT_MTIP_CR4_0_LANE_18_MAPPING 0xb70
75677 #define A_MAC_PORT_MTIP_CR4_0_LANE_19_MAPPING 0xb74
75678 #define A_MAC_PORT_MTIP_CR4_0_SCRATCH 0xb78
75679 #define A_MAC_PORT_MTIP_CR4_0_CORE_REVISION 0xb7c
75680 #define A_MAC_PORT_MTIP_CR4_0_VL_INTVL 0xb80
75682 #define S_VL_INTCL    0
75683 #define M_VL_INTCL    0xffffU
75687 #define A_MAC_PORT_MTIP_CR4_0_TX_LANE_THRESH 0xb84
75690 #define M_LANE6_LANE7    0xfU
75695 #define M_LANE4_LANE5    0xfU
75700 #define M_LANE2_LANE3    0xfU
75704 #define S_LANE0_LANE1    0
75705 #define M_LANE0_LANE1    0xfU
75709 #define A_MAC_PORT_MTIP_CR4_0_VL0_0 0xb98
75712 #define M_M1    0xffU
75716 #define S_M0    0
75717 #define M_M0    0xffU
75721 #define A_MAC_PORT_MTIP_CR4_0_VL0_1 0xb9c
75723 #define S_M2    0
75724 #define M_M2    0xffU
75728 #define A_MAC_PORT_MTIP_CR4_0_VL1_0 0xba0
75729 #define A_MAC_PORT_MTIP_CR4_0_VL1_1 0xba4
75730 #define A_MAC_PORT_MTIP_CR4_0_VL2_0 0xba8
75731 #define A_MAC_PORT_MTIP_CR4_0_VL2_1 0xbac
75732 #define A_MAC_PORT_MTIP_CR4_0_VL3_0 0xbb0
75733 #define A_MAC_PORT_MTIP_CR4_0_VL3_1 0xbb4
75734 #define A_MAC_PORT_MTIP_CR4_0_PCS_MODE 0xbb8
75752 #define S_ENA_CLAUSE49    0
75756 #define A_MAC_PORT_MTIP_CR4_0_VL4_0 0xc98
75757 #define A_MAC_PORT_MTIP_CR4_0_VL4_1 0xc9c
75758 #define A_MAC_PORT_MTIP_CR4_0_VL5_0 0xca0
75759 #define A_MAC_PORT_MTIP_CR4_0_VL5_1 0xca4
75760 #define A_MAC_PORT_MTIP_CR4_0_VL6_0 0xca8
75761 #define A_MAC_PORT_MTIP_CR4_0_VL6_1 0xcac
75762 #define A_MAC_PORT_MTIP_CR4_0_VL7_0 0xcb0
75763 #define A_MAC_PORT_MTIP_CR4_0_VL7_1 0xcb4
75764 #define A_MAC_PORT_MTIP_CR4_0_VL8_0 0xcb8
75765 #define A_MAC_PORT_MTIP_CR4_0_VL8_1 0xcbc
75766 #define A_MAC_PORT_MTIP_CR4_0_VL9_0 0xcc0
75767 #define A_MAC_PORT_MTIP_CR4_0_VL9_1 0xcc4
75768 #define A_MAC_PORT_MTIP_CR4_0_VL10_0 0xcc8
75769 #define A_MAC_PORT_MTIP_CR4_0_VL10_1 0xccc
75770 #define A_MAC_PORT_MTIP_CR4_0_VL11_0 0xcd0
75771 #define A_MAC_PORT_MTIP_CR4_0_VL11_1 0xcd4
75772 #define A_MAC_PORT_MTIP_CR4_0_VL12_0 0xcd8
75773 #define A_MAC_PORT_MTIP_CR4_0_VL12_1 0xcdc
75774 #define A_MAC_PORT_MTIP_CR4_0_VL13_0 0xce0
75775 #define A_MAC_PORT_MTIP_CR4_0_VL13_1 0xce4
75776 #define A_MAC_PORT_MTIP_CR4_0_VL14_0 0xce8
75777 #define A_MAC_PORT_MTIP_CR4_0_VL14_1 0xcec
75778 #define A_MAC_PORT_MTIP_CR4_0_VL15_0 0xcf0
75779 #define A_MAC_PORT_MTIP_CR4_0_VL15_1 0xcf4
75780 #define A_MAC_PORT_MTIP_CR4_0_VL16_0 0xcf8
75781 #define A_MAC_PORT_MTIP_CR4_0_VL16_1 0xcfc
75782 #define A_MAC_PORT_MTIP_CR4_0_VL17_0 0xd00
75783 #define A_MAC_PORT_MTIP_CR4_0_VL17_1 0xd04
75784 #define A_MAC_PORT_MTIP_CR4_0_VL18_0 0xd08
75785 #define A_MAC_PORT_MTIP_CR4_0_VL18_1 0xd0c
75786 #define A_MAC_PORT_MTIP_CR4_0_VL19_0 0xd10
75787 #define A_MAC_PORT_MTIP_CR4_0_VL19_1 0xd14
75788 #define A_MAC_PORT_MTIP_CR4_1_CONTROL_1 0x1000
75789 #define A_MAC_PORT_MTIP_CR4_1_STATUS_1 0x1004
75795 #define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID0 0x1008
75797 #define S_CR4_1_DEVICE_ID0    0
75798 #define M_CR4_1_DEVICE_ID0    0xffffU
75802 #define A_MAC_PORT_MTIP_CR4_1_DEVICE_ID1 0x100c
75804 #define S_CR4_1_DEVICE_ID1    0
75805 #define M_CR4_1_DEVICE_ID1    0xffffU
75809 #define A_MAC_PORT_MTIP_CR4_1_SPEED_ABILITY 0x1010
75810 #define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG1 0x1014
75811 #define A_MAC_PORT_MTIP_CR4_1_DEVICES_IN_PKG2 0x1018
75812 #define A_MAC_PORT_MTIP_CR4_1_CONTROL_2 0x101c
75813 #define A_MAC_PORT_MTIP_CR4_1_STATUS_2 0x1020
75814 #define A_MAC_PORT_MTIP_CR4_1_PKG_ID0 0x1038
75815 #define A_MAC_PORT_MTIP_CR4_1_PKG_ID1 0x103c
75816 #define A_MAC_PORT_MTIP_CR4_1_EEE_CTRL 0x1050
75817 #define A_MAC_PORT_MTIP_CR4_1_WAKE_ERROR_COUNTER 0x1058
75818 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_1 0x1080
75820 #define S_CR4_1_BR_BLOCK_LOCK    0
75824 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_STATUS_2 0x1084
75825 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_0 0x1088
75826 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_1 0x108c
75827 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_2 0x1090
75828 #define A_MAC_PORT_MTIP_CR4_1_SEED_A_3 0x1094
75829 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_0 0x1098
75830 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_1 0x109c
75831 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_2 0x10a0
75832 #define A_MAC_PORT_MTIP_CR4_1_SEED_B_3 0x10a4
75833 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_PATTERN_CONTROL 0x10a8
75834 #define A_MAC_PORT_MTIP_CR4_1_BASE_R_TEST_ERR_CNT 0x10ac
75835 #define A_MAC_PORT_MTIP_CR4_1_BER_HIGH_ORDER_CNT 0x10b0
75836 #define A_MAC_PORT_MTIP_CR4_1_ERR_BLK_HIGH_ORDER_CNT 0x10b4
75837 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_1 0x10c8
75838 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_2 0x10cc
75839 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_3 0x10d0
75840 #define A_MAC_PORT_MTIP_CR4_1_MULTI_LANE_ALIGN_STATUS_4 0x10d4
75841 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_0 0x10d8
75842 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_1 0x10dc
75843 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_2 0x10e0
75844 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_3 0x10e4
75845 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_4 0x10e8
75846 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_5 0x10ec
75847 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_6 0x10f0
75848 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_7 0x10f4
75849 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_8 0x10f8
75850 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_9 0x10fc
75851 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_10 0x1100
75852 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_11 0x1104
75853 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_12 0x1108
75854 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_13 0x110c
75855 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_14 0x1110
75856 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_15 0x1114
75857 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_16 0x1118
75858 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_17 0x111c
75859 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_18 0x1120
75860 #define A_MAC_PORT_MTIP_CR4_1_BIP_ERR_CNTLANE_19 0x1124
75861 #define A_MAC_PORT_MTIP_CR4_1_LANE_0_MAPPING 0x1128
75862 #define A_MAC_PORT_MTIP_CR4_1_LANE_1_MAPPING 0x112c
75863 #define A_MAC_PORT_MTIP_CR4_1_LANE_2_MAPPING 0x1130
75864 #define A_MAC_PORT_MTIP_CR4_1_LANE_3_MAPPING 0x1134
75865 #define A_MAC_PORT_MTIP_CR4_1_LANE_4_MAPPING 0x1138
75866 #define A_MAC_PORT_MTIP_CR4_1_LANE_5_MAPPING 0x113c
75867 #define A_MAC_PORT_MTIP_CR4_1_LANE_6_MAPPING 0x1140
75868 #define A_MAC_PORT_MTIP_CR4_1_LANE_7_MAPPING 0x1144
75869 #define A_MAC_PORT_MTIP_CR4_1_LANE_8_MAPPING 0x1148
75870 #define A_MAC_PORT_MTIP_CR4_1_LANE_9_MAPPING 0x114c
75871 #define A_MAC_PORT_MTIP_CR4_1_LANE_10_MAPPING 0x1150
75872 #define A_MAC_PORT_MTIP_CR4_1_LANE_11_MAPPING 0x1154
75873 #define A_MAC_PORT_MTIP_CR4_1_LANE_12_MAPPING 0x1158
75874 #define A_MAC_PORT_MTIP_CR4_1_LANE_13_MAPPING 0x115c
75875 #define A_MAC_PORT_MTIP_CR4_1_LANE_14_MAPPING 0x1160
75876 #define A_MAC_PORT_MTIP_CR4_1_LANE_15_MAPPING 0x1164
75877 #define A_MAC_PORT_MTIP_CR4_1_LANE_16_MAPPING 0x1168
75878 #define A_MAC_PORT_MTIP_CR4_1_LANE_17_MAPPING 0x116c
75879 #define A_MAC_PORT_MTIP_CR4_1_LANE_18_MAPPING 0x1170
75880 #define A_MAC_PORT_MTIP_CR4_1_LANE_19_MAPPING 0x1174
75881 #define A_MAC_PORT_MTIP_CR4_1_SCRATCH 0x1178
75882 #define A_MAC_PORT_MTIP_CR4_1_CORE_REVISION 0x117c
75883 #define A_MAC_PORT_MTIP_CR4_1_VL_INTVL 0x1180
75884 #define A_MAC_PORT_MTIP_CR4_1_TX_LANE_THRESH 0x1184
75885 #define A_MAC_PORT_MTIP_CR4_1_VL0_0 0x1198
75886 #define A_MAC_PORT_MTIP_CR4_1_VL0_1 0x119c
75887 #define A_MAC_PORT_MTIP_CR4_1_VL1_0 0x11a0
75888 #define A_MAC_PORT_MTIP_CR4_1_VL1_1 0x11a4
75889 #define A_MAC_PORT_MTIP_CR4_1_VL2_0 0x11a8
75890 #define A_MAC_PORT_MTIP_CR4_1_VL2_1 0x11ac
75891 #define A_MAC_PORT_MTIP_CR4_1_VL3_0 0x11b0
75892 #define A_MAC_PORT_MTIP_CR4_1_VL3_1 0x11b4
75893 #define A_MAC_PORT_MTIP_CR4_1_PCS_MODE 0x11b8
75894 #define A_MAC_COMMON_CFG_0 0x38000
75897 #define M_T7_RX_POLARITY_INV    0xffU
75902 #define M_T7_TX_POLARITY_INV    0xffU
75907 #define M_T7_DEBUG_PORT_SEL    0x3U
75912 #define M_MAC_SEPTY_CTL    0x3fU
75920 #define S_MAC_RDY_CTL    0
75921 #define M_MAC_RDY_CTL    0x3fU
75925 #define A_MAC_MTIP_RESET_CTRL_0 0x38004
76043 #define S_XGMII_CLK_RESET_0    0
76047 #define A_MAC_MTIP_RESET_CTRL_1 0x38008
76173 #define S_RESET_SD_TX_CLK_AN_7_I    0
76177 #define A_MAC_MTIP_RESET_CTRL_2 0x3800c
76303 #define S_RESET_REG_CLK_AN_7_I    0
76307 #define A_MAC_MTIP_CLK_CTRL_0 0x38010
76429 #define A_MAC_MTIP_CLK_CTRL_1 0x38014
76555 #define S_SD_TX_CLK_AN_7_I_G    0
76559 #define A_MAC_MTIP_CLK_CTRL_2 0x38018
76685 #define S_SD_TX_CLK_AEC_7_G    0
76689 #define A_MAC_MTIP_CLK_CTRL_3 0x3801c
76815 #define S_SD_TX_CLK_EN_7    0
76819 #define A_MAC_MTIP_CLK_CTRL_4 0x38020
76849 #define S_SGMII_RX_CLK_3_G    0
76853 #define A_MAC_PCS_CONFIG_0 0x38024
76856 #define M_KP_MODE_IN    0xffU
76861 #define M_FEC91_ENA_IN    0xffU
76866 #define M_SD_8X    0xffU
76870 #define S_SD_N2    0
76871 #define M_SD_N2    0xffU
76875 #define A_MAC_PCS_CONFIG_1 0x38028
76878 #define M_FAST_1LANE_MODE    0xffU
76883 #define M_PACER_10G    0xffU
76888 #define M_PCS400_ENA_IN    0x3U
76944 #define S_FEC91_LANE_IN0    0
76948 #define A_MAC_PCS_CONFIG_2 0x3802c
76967 #define M_CFG_CLOCK_RATE    0xfU
76972 #define M_FEC_ERR_ENA    0xffU
76977 #define M_FEC_ENA    0xffU
76982 #define M_PCS001_TX_AM_SF    0x7U
76986 #define S_PCS000_TX_AM_SF    0
76987 #define M_PCS000_TX_AM_SF    0x7U
76991 #define A_MAC_PCS_STATUS_0 0x38030
76994 #define M_PCS000_ALIGN_LOCK    0x3U
76999 #define M_PCS000_HI_SER    0x3U
77004 #define M_BER_TIMER_DONE    0xffU
77009 #define M_T7_AMPS_LOCK    0xffffU
77013 #define S_T7_ALIGN_DONE    0
77014 #define M_T7_ALIGN_DONE    0xfU
77018 #define A_MAC_PCS_STATUS_1 0x38034
77019 #define A_MAC_PCS_STATUS_2 0x38038
77022 #define M_RSFEC_ALIGNED    0xffU
77027 #define M_T7_FEC_LOCKED    0xffffU
77031 #define S_T7_BLOCK_LOCK    0
77032 #define M_T7_BLOCK_LOCK    0xffU
77036 #define A_MAC_PCS_STATUS_3 0x3803c
77039 #define M_FEC_NCERR    0xffffU
77043 #define S_FEC_CERR    0
77044 #define M_FEC_CERR    0xffffU
77048 #define A_MAC_PCS_STATUS_4 0x38040
77051 #define M_MAC1_RES_SPEED    0xffU
77056 #define M_MAC0_RES_SPEED    0xffU
77061 #define M_PCS400_ENA_IN_REF    0x3U
77066 #define M_PCS000_DEGRADE_SER    0x3U
77071 #define M_P4X_SIGNAL_OK    0x3U
77084 #define M_PCS001_RX_AM_SF    0x7U
77088 #define S_PCS000_RX_AM_SF    0
77089 #define M_PCS000_RX_AM_SF    0x7U
77093 #define A_MAC_PCS_STATUS_5 0x38044
77096 #define M_MAC5_RES_SPEED    0xffU
77101 #define M_MAC4_RES_SPEED    0xffU
77106 #define M_MAC3_RES_SPEED    0xffU
77110 #define S_MAC2_RES_SPEED    0
77111 #define M_MAC2_RES_SPEED    0xffU
77115 #define A_MAC_PCS_STATUS_6 0x38048
77118 #define M_MARKER_INS_CNT_100_00    0x7fffU
77123 #define M_MAC7_RES_SPEED    0xffU
77127 #define S_MAC6_RES_SPEED    0
77128 #define M_MAC6_RES_SPEED    0xffU
77132 #define A_MAC_PCS_STATUS_7 0x3804c
77135 #define M_PCS000_LINK_STATUS    0x3U
77140 #define M_MARKER_INS_CNT_100_02    0x7fffU
77144 #define S_MARKER_INS_CNT_100_01    0
77145 #define M_MARKER_INS_CNT_100_01    0x7fffU
77149 #define A_MAC_PCS_STATUS_8 0x38050
77152 #define M_MARKER_INS_CNT_25_1    0xffffU
77156 #define S_MARKER_INS_CNT_100_03    0
77157 #define M_MARKER_INS_CNT_100_03    0x7fffU
77161 #define A_MAC_PCS_STATUS_9 0x38054
77164 #define M_MARKER_INS_CNT_25_5    0xffffU
77168 #define S_MARKER_INS_CNT_25_3    0
77169 #define M_MARKER_INS_CNT_25_3    0xffffU
77173 #define A_MAC_PCS_STATUS_10 0x38058
77176 #define M_MARKER_INS_CNT_25_50_2    0xffffU
77180 #define S_MARKER_INS_CNT_25_50_0    0
77181 #define M_MARKER_INS_CNT_25_50_0    0xffffU
77185 #define A_MAC_PCS_STATUS_11 0x3805c
77188 #define M_MARKER_INS_CNT_25_50_6    0xffffU
77192 #define S_MARKER_INS_CNT_25_50_4    0
77193 #define M_MARKER_INS_CNT_25_50_4    0xffffU
77197 #define A_MAC_PCS_STATUS_12 0x38060
77200 #define M_T7_LINK_STATUS    0xffU
77205 #define M_T7_HI_BER    0xffU
77209 #define S_MARKER_INS_CNT_25_7    0
77210 #define M_MARKER_INS_CNT_25_7    0xffffU
77214 #define A_MAC_MAC200G400G_0_CONFIG_0 0x38064
77215 #define A_MAC_MAC200G400G_0_CONFIG_1 0x38068
77225 #define A_MAC_MAC200G400G_0_CONFIG_2 0x3806c
77226 #define A_MAC_MAC200G400G_0_CONFIG_3 0x38070
77227 #define A_MAC_MAC200G400G_0_CONFIG_4 0x38074
77229 #define S_FRC_DELTA    0
77230 #define M_FRC_DELTA    0xffffU
77234 #define A_MAC_MAC200G400G_0_STATUS 0x38078
77252 #define A_MAC_MAC200G400G_1_CONFIG_0 0x3807c
77253 #define A_MAC_MAC200G400G_1_CONFIG_1 0x38080
77254 #define A_MAC_MAC200G400G_1_CONFIG_2 0x38084
77255 #define A_MAC_MAC200G400G_1_CONFIG_3 0x38088
77256 #define A_MAC_MAC200G400G_1_CONFIG_4 0x3808c
77257 #define A_MAC_MAC200G400G_1_STATUS 0x38090
77258 #define A_MAC_AN_CFG_0 0x38094
77261 #define M_T7_AN_DATA_CTL    0xffU
77266 #define M_T7_AN_ENA    0xffU
77270 #define A_MAC_AN_CFG_1 0x38098
77300 #define S_AN_DIS_TIMER_AN_0    0
77304 #define A_MAC_AN_SERDES25G_ENA 0x3809c
77366 #define S_AN_SD25_RX_ENA_0    0
77370 #define A_MAC_PLL_CFG_0 0x380a0
77377 #define M_HSSPLLSEL0    0x3U
77382 #define M_HSSTXDIV2CLK_SEL0    0x3U
77394 #define S_HSSCLK32DIV2_RESET0    0
77398 #define A_MAC_PLL_CFG_1 0x380a4
77401 #define M_HSSPLLSEL1    0x3U
77406 #define M_HSSTXDIV2CLK_SEL1    0x3U
77418 #define S_HSSCLK32DIV2_RESET1    0
77422 #define A_MAC_PLL_CFG_2 0x380a8
77425 #define M_HSSPLLSEL2    0x3U
77430 #define M_HSSTXDIV2CLK_SEL2    0x3U
77442 #define S_HSSCLK32DIV2_RESET2    0
77446 #define A_MAC_PLL_CFG_3 0x380ac
77449 #define M_HSSPLLSEL3    0x3U
77454 #define M_HSSTXDIV2CLK_SEL3    0x3U
77466 #define S_HSSCLK32DIV2_RESET3    0
77470 #define A_MAC_HSS_STATUS 0x380b0
77473 #define M_TX_LANE_PLL_SEL_3    0x3U
77478 #define M_TX_LANE_PLL_SEL_2    0x3U
77483 #define M_TX_LANE_PLL_SEL_1    0x3U
77488 #define M_TX_LANE_PLL_SEL_0    0x3U
77520 #define S_HSSPLLLOCKA_HSS0    0
77524 #define A_MAC_HSS_SIGDET_STATUS 0x380b4
77527 #define M_HSS3_SIGDET    0x3U
77532 #define M_HSS2_SIGDET    0x3U
77537 #define M_HSS1_SIGDET    0x3U
77541 #define S_HSS0_SIGDET    0
77542 #define M_HSS0_SIGDET    0x3U
77546 #define A_MAC_FPGA_CFG_0 0x380b8
77547 #define A_MAC_PMD_STATUS 0x380bc
77549 #define S_SIGNAL_DETECT    0
77550 #define M_SIGNAL_DETECT    0xffU
77554 #define A_MAC_PMD_AN_CONFIG0 0x380c0
77557 #define M_AN3_RATE_SELECT    0x1fU
77566 #define M_AN2_RATE_SELECT    0x1fU
77575 #define M_AN1_RATE_SELECT    0x1fU
77584 #define M_AN0_RATE_SELECT    0x1fU
77588 #define S_AN0_STATUS    0
77592 #define A_MAC_PMD_AN_CONFIG1 0x380c4
77595 #define M_AN7_RATE_SELECT    0x1fU
77604 #define M_AN6_RATE_SELECT    0x1fU
77613 #define M_AN5_RATE_SELECT    0x1fU
77622 #define M_AN4_RATE_SELECT    0x1fU
77626 #define S_AN4_STATUS    0
77630 #define A_MAC_INT_EN_CMN 0x380c8
77716 #define S_LOCK_LOST    0
77720 #define A_MAC_INT_CAUSE_CMN 0x380cc
77786 #define A_MAC_PERR_INT_EN_MTIP 0x380d0
77864 #define S_PERR_MAC_STAT5_TX    0
77868 #define A_MAC_PERR_INT_CAUSE_MTIP 0x380d4
77882 #define A_MAC_PERR_ENABLE_MTIP 0x380d8
77883 #define A_MAC_PCS_1G_CONFIG_0 0x380dc
77902 #define M_TX_LANE_THRESH_3    0xfU
77907 #define M_TX_LANE_THRESH_2    0xfU
77912 #define M_TX_LANE_THRESH_1    0xfU
77916 #define S_TX_LANE_THRESH_0    0
77917 #define M_TX_LANE_THRESH_0    0xfU
77921 #define A_MAC_PCS_1G_CONFIG_1 0x380e0
77924 #define M_TX_LANE_CKMULT_3    0x7U
77929 #define M_TX_LANE_CKMULT_2    0x7U
77934 #define M_TX_LANE_CKMULT_1    0x7U
77938 #define S_TX_LANE_CKMULT_0    0
77939 #define M_TX_LANE_CKMULT_0    0x7U
77943 #define A_MAC_PTP_TIMER_RD0_LO 0x380e4
77944 #define A_MAC_PTP_TIMER_RD0_HI 0x380e8
77945 #define A_MAC_PTP_TIMER_RD1_LO 0x380ec
77946 #define A_MAC_PTP_TIMER_RD1_HI 0x380f0
77947 #define A_MAC_PTP_TIMER_WR_LO 0x380f4
77948 #define A_MAC_PTP_TIMER_WR_HI 0x380f8
77949 #define A_MAC_PTP_TIMER_OFFSET_0 0x380fc
77950 #define A_MAC_PTP_TIMER_OFFSET_1 0x38100
77951 #define A_MAC_PTP_TIMER_OFFSET_2 0x38104
77952 #define A_MAC_PTP_SUM_LO 0x38108
77953 #define A_MAC_PTP_SUM_HI 0x3810c
77954 #define A_MAC_PTP_TIMER_INCR0 0x38110
77955 #define A_MAC_PTP_TIMER_INCR1 0x38114
77956 #define A_MAC_PTP_DRIFT_ADJUST_COUNT 0x38118
77957 #define A_MAC_PTP_OFFSET_ADJUST_FINE 0x3811c
77958 #define A_MAC_PTP_OFFSET_ADJUST_TOTAL 0x38120
77959 #define A_MAC_PTP_CFG 0x38124
77960 #define A_MAC_PTP_PPS 0x38128
77961 #define A_MAC_PTP_SINGLE_ALARM 0x3812c
77962 #define A_MAC_PTP_PERIODIC_ALARM 0x38130
77963 #define A_MAC_PTP_STATUS 0x38134
77964 #define A_MAC_STS_GPIO_SEL 0x38140
77970 #define S_STSINSEL    0
77974 #define A_MAC_CERR_INT_EN_MTIP 0x38150
78020 #define S_CERR_MAC5_RX    0
78024 #define A_MAC_CERR_INT_CAUSE_MTIP 0x38154
78025 #define A_MAC_1G_PCS0_STATUS 0x38160
78048 #define M_1G_PCS0_SPEED_SEL    0x3U
78072 #define S_1G_PCS0_RX_WAKE_ERR    0
78076 #define A_MAC_1G_PCS1_STATUS 0x38164
78099 #define M_1G_PCS1_SPEED_SEL    0x3U
78123 #define S_1G_PCS1_RX_WAKE_ERR    0
78127 #define A_MAC_1G_PCS2_STATUS 0x38168
78150 #define M_1G_PCS2_SPEED_SEL    0x3U
78174 #define S_1G_PCS2_RX_WAKE_ERR    0
78178 #define A_MAC_1G_PCS3_STATUS 0x3816c
78201 #define M_1G_PCS3_SPEED_SEL    0x3U
78225 #define S_1G_PCS3_RX_WAKE_ERR    0
78229 #define A_MAC_PCS_LPI_STATUS_0 0x38170
78231 #define S_TX_LPI_STATE    0
78232 #define M_TX_LPI_STATE    0xffffffU
78236 #define A_MAC_PCS_LPI_STATUS_1 0x38174
78238 #define S_TX_LPI_MODE    0
78239 #define M_TX_LPI_MODE    0xffffU
78243 #define A_MAC_PCS_LPI_STATUS_2 0x38178
78246 #define M_RX_LPI_MODE    0xffU
78250 #define S_RX_LPI_STATE    0
78251 #define M_RX_LPI_STATE    0xffffffU
78255 #define A_MAC_PCS_LPI_STATUS_3 0x3817c
78257 #define S_T7_RX_LPI_ACTIVE    0
78258 #define M_T7_RX_LPI_ACTIVE    0xffU
78262 #define A_MAC_TX0_CLK_DIV 0x38180
78263 #define A_MAC_TX1_CLK_DIV 0x38184
78264 #define A_MAC_TX2_CLK_DIV 0x38188
78265 #define A_MAC_TX3_CLK_DIV 0x3818c
78266 #define A_MAC_TX4_CLK_DIV 0x38190
78267 #define A_MAC_TX5_CLK_DIV 0x38194
78268 #define A_MAC_TX6_CLK_DIV 0x38198
78269 #define A_MAC_TX7_CLK_DIV 0x3819c
78270 #define A_MAC_RX0_CLK_DIV 0x381a0
78271 #define A_MAC_RX1_CLK_DIV 0x381a4
78272 #define A_MAC_RX2_CLK_DIV 0x381a8
78273 #define A_MAC_RX3_CLK_DIV 0x381ac
78274 #define A_MAC_RX4_CLK_DIV 0x381b0
78275 #define A_MAC_RX5_CLK_DIV 0x381b4
78276 #define A_MAC_RX6_CLK_DIV 0x381b8
78277 #define A_MAC_RX7_CLK_DIV 0x381bc
78278 #define A_MAC_SYNC_E_CDR_LANE_SEL 0x381c0
78293 #define M_LOC_FAULT_PORT_SEL    0x3U
78298 #define M_TX_CDR_LANE_SEL    0x7U
78302 #define S_RX_CDR_LANE_SEL    0
78303 #define M_RX_CDR_LANE_SEL    0x7U
78307 #define A_MAC_DEBUG_PL_IF_1 0x381c4
78308 #define A_MAC_HSS0_ANALOG_TEST_CTRL 0x381d0
78310 #define S_WP_PMT_IN_I    0
78311 #define M_WP_PMT_IN_I    0xfU
78315 #define A_MAC_HSS1_ANALOG_TEST_CTRL 0x381d4
78316 #define A_MAC_HSS2_ANALOG_TEST_CTRL 0x381d8
78317 #define A_MAC_HSS3_ANALOG_TEST_CTRL 0x381dc
78318 #define A_MAC_HSS0_ANALOG_TEST_STATUS 0x381e0
78320 #define S_WP_PMT_OUT_O    0
78321 #define M_WP_PMT_OUT_O    0xfU
78325 #define A_MAC_HSS1_ANALOG_TEST_STATUS 0x381e4
78326 #define A_MAC_HSS2_ANALOG_TEST_STATUS 0x381e8
78327 #define A_MAC_HSS3_ANALOG_TEST_STATUS 0x381ec
78328 #define A_MAC_SIGNAL_DETECT_CTRL 0x381f0
78390 #define S_SIGDETCTRL_LN0    0
78394 #define A_MAC_FPGA_STATUS_FRM_BOARD 0x381f4
78456 #define S_QSFP0_MOD_PRES    0
78460 #define A_MAC_FPGA_CONTROL_TO_BOARD 0x381f8
78463 #define M_T7_1_LB_MODE    0x3U
78503 #define S_QSFP0_RESET_L    0
78507 #define A_MAC_FPGA_LINK_STATUS 0x381fc
78521 #define S_PORT0_FPGA_LINK_UP    0
78525 #define A_MAC_MTIP_MAC400G_0_MTIP_REVISION 0x38200
78527 #define S_MTIP_REV_400G_0    0
78528 #define M_MTIP_REV_400G_0    0xffU
78532 #define A_MAC_MTIP_MAC400G_0_MTIP_SCRATCH 0x38204
78533 #define A_MAC_MTIP_MAC400G_0_MTIP_COMMAND_CONFIG 0x38208
78547 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_0 0x3820c
78548 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_ADDR_1 0x38210
78549 #define A_MAC_MTIP_MAC400G_0_MTIP_FRM_LENGTH 0x38214
78550 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_SECTIONS 0x3821c
78551 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_SECTIONS 0x38220
78552 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_FIFO_ALMOST_F_E 0x38224
78553 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_FIFO_ALMOST_F_E 0x38228
78554 #define A_MAC_MTIP_MAC400G_0_MTIP_HASHTABLE_LOAD 0x3822c
78555 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_STATUS 0x38240
78556 #define A_MAC_MTIP_MAC400G_0_MTIP_TX_IPG_LENGTH 0x38244
78559 #define M_T7_IPG    0x1fffU
78563 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA 0x38254
78564 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA 0x38258
78565 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA 0x3825c
78566 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA 0x38260
78567 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38264
78570 #define M_CL1_PAUSE_QUANTA_THRESH    0xffffU
78574 #define S_CL0_PAUSE_QUANTA_THRESH    0
78575 #define M_CL0_PAUSE_QUANTA_THRESH    0xffffU
78579 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38268
78582 #define M_CL3_PAUSE_QUANTA_THRESH    0xffffU
78586 #define S_CL2_PAUSE_QUANTA_THRESH    0
78587 #define M_CL2_PAUSE_QUANTA_THRESH    0xffffU
78591 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3826c
78594 #define M_CL5_PAUSE_QUANTA_THRESH    0xffffU
78598 #define S_CL4_PAUSE_QUANTA_THRESH    0
78599 #define M_CL4_PAUSE_QUANTA_THRESH    0xffffU
78603 #define A_MAC_MTIP_MAC400G_0_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38270
78606 #define M_CL7_PAUSE_QUANTA_THRESH    0xffffU
78610 #define S_CL6_PAUSE_QUANTA_THRESH    0
78611 #define M_CL6_PAUSE_QUANTA_THRESH    0xffffU
78615 #define A_MAC_MTIP_MAC400G_0_MTIP_RX_PAUSE_STATUS 0x38274
78617 #define S_RX_PAUSE_STATUS    0
78618 #define M_RX_PAUSE_STATUS    0xffU
78622 #define A_MAC_MTIP_MAC400G_0_MTIP_TS_TIMESTAMP 0x3827c
78623 #define A_MAC_MTIP_MAC400G_0_MTIP_XIF_MODE 0x38280
78624 #define A_MAC_MTIP_MAC400G_1_MTIP_REVISION 0x38300
78626 #define S_MTIP_REV_400G_1    0
78627 #define M_MTIP_REV_400G_1    0xffU
78631 #define A_MAC_MTIP_MAC400G_1_MTIP_SCRATCH 0x38304
78632 #define A_MAC_MTIP_MAC400G_1_MTIP_COMMAND_CONFIG 0x38308
78642 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_0 0x3830c
78643 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_ADDR_1 0x38310
78644 #define A_MAC_MTIP_MAC400G_1_MTIP_FRM_LENGTH 0x38314
78645 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_SECTIONS 0x3831c
78646 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_SECTIONS 0x38320
78647 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_FIFO_ALMOST_F_E 0x38324
78648 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_FIFO_ALMOST_F_E 0x38328
78649 #define A_MAC_MTIP_MAC400G_1_MTIP_HASHTABLE_LOAD 0x3832c
78655 #define S_HASHTABLE_ADDR_400G_1    0
78656 #define M_HASHTABLE_ADDR_400G_1    0x3fU
78660 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_STATUS 0x38340
78661 #define A_MAC_MTIP_MAC400G_1_MTIP_TX_IPG_LENGTH 0x38344
78662 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA 0x38354
78663 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA 0x38358
78664 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA 0x3835c
78665 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA 0x38360
78666 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL01_PAUSE_QUANTA_THRESH 0x38364
78667 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL23_PAUSE_QUANTA_THRESH 0x38368
78668 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL45_PAUSE_QUANTA_THRESH 0x3836c
78669 #define A_MAC_MTIP_MAC400G_1_MTIP_MAC_CL67_PAUSE_QUANTA_THRESH 0x38370
78670 #define A_MAC_MTIP_MAC400G_1_MTIP_RX_PAUSE_STATUS 0x38374
78671 #define A_MAC_MTIP_MAC400G_1_MTIP_TS_TIMESTAMP 0x3837c
78672 #define A_MAC_MTIP_MAC400G_1_MTIP_XIF_MODE 0x38380
78673 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_1 0x38400
78679 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_1 0x38404
78685 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID0 0x38408
78687 #define S_400G_DEVICE_ID0_0    0
78688 #define M_400G_DEVICE_ID0_0    0xffffU
78692 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICE_ID1 0x3840c
78694 #define S_400G_DEVICE_ID1_0    0
78695 #define M_400G_DEVICE_ID1_0    0xffffU
78699 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_SPEED_ABILITY 0x38410
78709 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG1 0x38414
78715 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DEVICES_IN_PKG2 0x38418
78716 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CONTROL_2 0x3841c
78718 #define S_400G_PCS_TYPE_SELECTION_0    0
78719 #define M_400G_PCS_TYPE_SELECTION_0    0xfU
78723 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_2 0x38420
78724 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_STATUS_3 0x38424
78727 #define M_T7_DEVICE_PRESENT    0x3fffU
78735 #define S_200GBASE_R    0
78739 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID0 0x38438
78740 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_PKG_ID1 0x3843c
78741 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_1 0x38480
78742 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_STATUS_2 0x38484
78743 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_CONTROL 0x384a8
78744 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BASE_R_TEST_ERR_CNT 0x384ac
78745 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_BER_HIGH_ORDER_CNT 0x384b0
78746 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x384b4
78752 #define S_ERROR_BLOCK_COUNTER    0
78753 #define M_ERROR_BLOCK_COUNTER    0x3fffU
78757 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x384c8
78758 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x384cc
78759 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x384d0
78760 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x384d4
78761 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_0_MAPPING 0x384d8
78763 #define S_T7_LANE_0_MAPPING    0
78764 #define M_T7_LANE_0_MAPPING    0xfU
78768 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_1_MAPPING 0x384dc
78770 #define S_T7_LANE_1_MAPPING    0
78771 #define M_T7_LANE_1_MAPPING    0xfU
78775 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_2_MAPPING 0x384e0
78777 #define S_T7_LANE_2_MAPPING    0
78778 #define M_T7_LANE_2_MAPPING    0xfU
78782 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_3_MAPPING 0x384e4
78784 #define S_T7_LANE_3_MAPPING    0
78785 #define M_T7_LANE_3_MAPPING    0xfU
78789 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_4_MAPPING 0x384e8
78791 #define S_T7_LANE_4_MAPPING    0
78792 #define M_T7_LANE_4_MAPPING    0xfU
78796 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_5_MAPPING 0x384ec
78798 #define S_T7_LANE_5_MAPPING    0
78799 #define M_T7_LANE_5_MAPPING    0xfU
78803 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_6_MAPPING 0x384f0
78805 #define S_T7_LANE_6_MAPPING    0
78806 #define M_T7_LANE_6_MAPPING    0xfU
78810 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_7_MAPPING 0x384f4
78812 #define S_T7_LANE_7_MAPPING    0
78813 #define M_T7_LANE_7_MAPPING    0xfU
78817 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_8_MAPPING 0x384f8
78819 #define S_T7_LANE_8_MAPPING    0
78820 #define M_T7_LANE_8_MAPPING    0xfU
78824 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_9_MAPPING 0x384fc
78826 #define S_T7_LANE_9_MAPPING    0
78827 #define M_T7_LANE_9_MAPPING    0xfU
78831 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_10_MAPPING 0x38500
78833 #define S_T7_LANE_10_MAPPING    0
78834 #define M_T7_LANE_10_MAPPING    0xfU
78838 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_11_MAPPING 0x38504
78840 #define S_T7_LANE_11_MAPPING    0
78841 #define M_T7_LANE_11_MAPPING    0xfU
78845 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_12_MAPPING 0x38508
78847 #define S_T7_LANE_12_MAPPING    0
78848 #define M_T7_LANE_12_MAPPING    0xfU
78852 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_13_MAPPING 0x3850c
78854 #define S_T7_LANE_13_MAPPING    0
78855 #define M_T7_LANE_13_MAPPING    0xfU
78859 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_14_MAPPING 0x38510
78861 #define S_T7_LANE_14_MAPPING    0
78862 #define M_T7_LANE_14_MAPPING    0xfU
78866 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_LANE_15_MAPPING 0x38514
78868 #define S_T7_LANE_15_MAPPING    0
78869 #define M_T7_LANE_15_MAPPING    0xfU
78873 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_SCRATCH 0x38600
78874 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CORE_REVISION 0x38604
78875 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_CL_INTVL 0x38608
78877 #define S_T7_VL_INTVL    0
78878 #define M_T7_VL_INTVL    0xffffU
78882 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_LANE_THRESH 0x3860c
78884 #define S_TX_LANE_THRESH    0
78885 #define M_TX_LANE_THRESH    0xfU
78889 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_TX_CDMII_PACE 0x3861c
78891 #define S_TX_CDMII_PACE    0
78892 #define M_TX_CDMII_PACE    0xfU
78896 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_0 0x38620
78898 #define S_AM_0    0
78899 #define M_AM_0    0xffffU
78903 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_AM_1 0x38624
78905 #define S_AM_1    0
78906 #define M_AM_1    0xffffU
78910 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO0 0x38800
78912 #define S_DBGINFO0    0
78913 #define M_DBGINFO0    0xffffU
78917 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO1 0x38804
78919 #define S_DBGINFO1    0
78920 #define M_DBGINFO1    0xffffU
78924 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO2 0x38808
78926 #define S_DBGINFO2    0
78927 #define M_DBGINFO2    0xffffU
78931 #define A_MAC_MTIP_PCS400G_0_MTIP_400G_DBGINFO3 0x3880c
78933 #define S_DBGINFO3    0
78934 #define M_DBGINFO3    0xffffU
78938 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_1 0x38900
78939 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_1 0x38904
78945 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID0 0x38908
78947 #define S_400G_DEVICE_ID0_1    0
78948 #define M_400G_DEVICE_ID0_1    0xffffU
78952 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICE_ID1 0x3890c
78954 #define S_400G_DEVICE_ID1_1    0
78955 #define M_400G_DEVICE_ID1_1    0xffffU
78959 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_SPEED_ABILITY 0x38910
78969 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG1 0x38914
78970 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DEVICES_IN_PKG2 0x38918
78971 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CONTROL_2 0x3891c
78973 #define S_400G_PCS_TYPE_SELECTION_1    0
78974 #define M_400G_PCS_TYPE_SELECTION_1    0xfU
78978 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_2 0x38920
78979 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_STATUS_3 0x38924
78980 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID0 0x38938
78981 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_PKG_ID1 0x3893c
78982 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_1 0x38980
78983 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_STATUS_2 0x38984
78984 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_CONTROL 0x389a8
78985 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BASE_R_TEST_ERR_CNT 0x389ac
78986 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_BER_HIGH_ORDER_CNT 0x389b0
78987 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_ERR_BLK_HIGH_ORDER_CNT 0x389b4
78988 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_1 0x389c8
78989 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_2 0x389cc
78990 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_3 0x389d0
78991 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_MULTI_LANE_ALIGN_STATUS_4 0x389d4
78992 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_0_MAPPING 0x389d8
78993 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_1_MAPPING 0x389dc
78994 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_2_MAPPING 0x389e0
78995 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_3_MAPPING 0x389e4
78996 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_4_MAPPING 0x389e8
78997 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_5_MAPPING 0x389ec
78998 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_6_MAPPING 0x389f0
78999 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_7_MAPPING 0x389f4
79000 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_8_MAPPING 0x389f8
79001 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_9_MAPPING 0x389fc
79002 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_10_MAPPING 0x38a00
79003 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_11_MAPPING 0x38a04
79004 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_12_MAPPING 0x38a08
79005 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_13_MAPPING 0x38a0c
79006 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_14_MAPPING 0x38a10
79007 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_LANE_15_MAPPING 0x38a14
79008 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_SCRATCH 0x38b00
79009 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CORE_REVISION 0x38b04
79010 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_CL_INTVL 0x38b08
79011 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_LANE_THRESH 0x38b0c
79012 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_TX_CDMII_PACE 0x38b1c
79013 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_0 0x38b20
79014 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_AM_1 0x38b24
79015 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO0 0x38d00
79016 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO1 0x38d04
79017 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO2 0x38d08
79018 #define A_MAC_MTIP_PCS400G_1_MTIP_400G_DBGINFO3 0x38d0c
79019 #define A_MAC_MTIP_RS_FEC_CONTROL_0_0 0x38e00
79041 #define A_MAC_MTIP_RS_FEC_STATUS_0_0 0x38e04
79048 #define M_FEC_STATUS_0_11    0xfU
79080 #define S_FEC_STATUS_0_0    0
79084 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_0 0x38e08
79085 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_0 0x38e0c
79086 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_0 0x38e10
79087 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_0 0x38e14
79088 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_0 0x38e18
79089 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_0 0x38e1c
79091 #define S_DEC_TRESH    0
79092 #define M_DEC_TRESH    0x3fU
79096 #define A_MAC_MTIP_RS_FEC_CONTROL_0_1 0x38e20
79097 #define A_MAC_MTIP_RS_FEC_STATUS_0_1 0x38e24
79104 #define M_FEC_STATUS_1_11    0xfU
79136 #define S_FEC_STATUS_1_0    0
79140 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_1 0x38e28
79141 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_1 0x38e2c
79142 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_1 0x38e30
79143 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_1 0x38e34
79144 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_1 0x38e38
79145 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_1 0x38e3c
79146 #define A_MAC_MTIP_RS_FEC_CONTROL_0_2 0x38e40
79147 #define A_MAC_MTIP_RS_FEC_STATUS_0_2 0x38e44
79154 #define M_FEC_STATUS_2_11    0xfU
79186 #define S_FEC_STATUS_2_0    0
79190 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_2 0x38e48
79191 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_2 0x38e4c
79192 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_2 0x38e50
79193 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_2 0x38e54
79194 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_2 0x38e58
79195 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_2 0x38e5c
79196 #define A_MAC_MTIP_RS_FEC_CONTROL_0_3 0x38e60
79197 #define A_MAC_MTIP_RS_FEC_STATUS_0_3 0x38e64
79204 #define M_FEC_STATUS_3_11    0xfU
79236 #define S_FEC_STATUS_3_0    0
79240 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_3 0x38e68
79241 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_3 0x38e6c
79242 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_3 0x38e70
79243 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_3 0x38e74
79244 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_3 0x38e78
79245 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_3 0x38e7c
79246 #define A_MAC_MTIP_RS_FEC_CONTROL_0_4 0x38e80
79247 #define A_MAC_MTIP_RS_FEC_STATUS_0_4 0x38e84
79254 #define M_FEC_STATUS_4_11    0xfU
79286 #define S_FEC_STATUS_4_0    0
79290 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_4 0x38e88
79291 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_4 0x38e8c
79292 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_4 0x38e90
79293 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_4 0x38e94
79294 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_4 0x38e98
79295 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_4 0x38e9c
79296 #define A_MAC_MTIP_RS_FEC_CONTROL_0_5 0x38ea0
79297 #define A_MAC_MTIP_RS_FEC_STATUS_0_5 0x38ea4
79304 #define M_FEC_STATUS_5_11    0xfU
79336 #define S_FEC_STATUS_5_0    0
79340 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_5 0x38ea8
79341 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_5 0x38eac
79342 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_5 0x38eb0
79343 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_5 0x38eb4
79344 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_5 0x38eb8
79345 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_5 0x38ebc
79346 #define A_MAC_MTIP_RS_FEC_CONTROL_0_6 0x38ec0
79347 #define A_MAC_MTIP_RS_FEC_STATUS_0_6 0x38ec4
79354 #define M_FEC_STATUS_6_11    0xfU
79386 #define S_FEC_STATUS_6_0    0
79390 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_6 0x38ec8
79391 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_6 0x38ecc
79392 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_6 0x38ed0
79393 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_6 0x38ed4
79394 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_6 0x38ed8
79395 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_6 0x38edc
79396 #define A_MAC_MTIP_RS_FEC_CONTROL_0_7 0x38ee0
79397 #define A_MAC_MTIP_RS_FEC_STATUS_0_7 0x38ee4
79404 #define M_FEC_STATUS_7_11    0xfU
79436 #define S_FEC_STATUS_7_0    0
79440 #define A_MAC_MTIP_RS_FEC_CCW_LO_0_7 0x38ee8
79441 #define A_MAC_MTIP_RS_FEC_CCW_HI_0_7 0x38eec
79442 #define A_MAC_MTIP_RS_FEC_NCCW_LO_0_7 0x38ef0
79443 #define A_MAC_MTIP_RS_FEC_NCCW_HI_0_7 0x38ef4
79444 #define A_MAC_MTIP_RS_FEC_LANEMAPRS_FEC_0_7 0x38ef8
79445 #define A_MAC_MTIP_RS_FEC_DEC_THRESH_0_7 0x38efc
79446 #define A_MAC_MTIP_RS_FEC_HISER_CW 0x38f00
79448 #define S_HISER_CW    0
79449 #define M_HISER_CW    0xffffU
79453 #define A_MAC_MTIP_RS_FEC_HISER_THRESH 0x38f04
79455 #define S_HISER_THRESH    0
79456 #define M_HISER_THRESH    0xffffU
79460 #define A_MAC_MTIP_RS_FEC_HISER_TIME 0x38f08
79462 #define S_HISER_TIME    0
79463 #define M_HISER_TIME    0xffffU
79467 #define A_MAC_MTIP_RS_DEGRADE_SET_CW 0x38f10
79469 #define S_DEGRADE_SET_CW    0
79470 #define M_DEGRADE_SET_CW    0xffffU
79474 #define A_MAC_MTIP_RS_DEGRADE_SET_CW_HI 0x38f14
79476 #define S_DEGRADE_SET_CW_HI    0
79477 #define M_DEGRADE_SET_CW_HI    0xffffU
79481 #define A_MAC_MTIP_RS_DEGRADE_SET_THRESH 0x38f18
79483 #define S_DEGRADE_SET_THRESH    0
79484 #define M_DEGRADE_SET_THRESH    0xffffU
79488 #define A_MAC_MTIP_RS_DEGRADE_SET_THRESH_HI 0x38f1c
79490 #define S_DEGRADE_SET_THRESH_HI    0
79491 #define M_DEGRADE_SET_THRESH_HI    0xffffU
79495 #define A_MAC_MTIP_RS_DEGRADE_CLEAR 0x38f20
79497 #define S_DEGRADE_SET_CLEAR    0
79498 #define M_DEGRADE_SET_CLEAR    0xffffU
79502 #define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_HI 0x38f24
79504 #define S_DEGRADE_SET_CLEAR_HI    0
79505 #define M_DEGRADE_SET_CLEAR_HI    0xffffU
79509 #define A_MAC_MTIP_RS_DEGRADE_CLEAR_THRESH 0x38f28
79511 #define S_DEGRADE_SET_CLEAR_THRESH    0
79512 #define M_DEGRADE_SET_CLEAR_THRESH    0xffffU
79516 #define A_MAC_MTIP_RS_DEGRADE_SET_CLEAR_THRESH_HI 0x38f2c
79518 #define S_DEGRADE_SET_CLEAR_THRESH_HI    0
79519 #define M_DEGRADE_SET_CLEAR_THRESH_HI    0xffffU
79523 #define A_MAC_MTIP_RS_VL0_0 0x38f80
79524 #define A_MAC_MTIP_RS_VL0_1 0x38f84
79525 #define A_MAC_MTIP_RS_VL1_0 0x38f88
79526 #define A_MAC_MTIP_RS_VL1_1 0x38f8c
79527 #define A_MAC_MTIP_RS_VL2_0 0x38f90
79528 #define A_MAC_MTIP_RS_VL2_1 0x38f94
79529 #define A_MAC_MTIP_RS_VL3_0 0x38f98
79530 #define A_MAC_MTIP_RS_VL3_1 0x38f9c
79531 #define A_MAC_MTIP_RS_VL4_0 0x38fa0
79532 #define A_MAC_MTIP_RS_VL4_1 0x38fa4
79533 #define A_MAC_MTIP_RS_VL5_0 0x38fa8
79534 #define A_MAC_MTIP_RS_VL5_1 0x38fac
79535 #define A_MAC_MTIP_RS_VL6_0 0x38fb0
79536 #define A_MAC_MTIP_RS_VL6_1 0x38fb4
79537 #define A_MAC_MTIP_RS_VL7_0 0x38fb8
79538 #define A_MAC_MTIP_RS_VL7_1 0x38fbc
79539 #define A_MAC_MTIP_RS_VL8_0 0x38fc0
79540 #define A_MAC_MTIP_RS_VL8_1 0x38fc4
79541 #define A_MAC_MTIP_RS_VL9_0 0x38fc8
79542 #define A_MAC_MTIP_RS_VL9_1 0x38fcc
79543 #define A_MAC_MTIP_RS_VL10_0 0x38fd0
79544 #define A_MAC_MTIP_RS_VL10_1 0x38fd4
79545 #define A_MAC_MTIP_RS_VL11_0 0x38fd8
79546 #define A_MAC_MTIP_RS_VL11_1 0x38fdc
79547 #define A_MAC_MTIP_RS_VL12_0 0x38fe0
79548 #define A_MAC_MTIP_RS_VL12_1 0x38fe4
79549 #define A_MAC_MTIP_RS_VL13_0 0x38fe8
79550 #define A_MAC_MTIP_RS_VL13_1 0x38fec
79551 #define A_MAC_MTIP_RS_VL14_0 0x38ff0
79552 #define A_MAC_MTIP_RS_VL14_1 0x38ff4
79553 #define A_MAC_MTIP_RS_VL15_0 0x38ff8
79554 #define A_MAC_MTIP_RS_VL15_1 0x38ffc
79555 #define A_MAC_MTIP_RS_FEC_SYMBLERR0_LO 0x39000
79556 #define A_MAC_MTIP_RS_FEC_SYMBLERR0_HI 0x39004
79557 #define A_MAC_MTIP_RS_FEC_SYMBLERR1_LO 0x39008
79558 #define A_MAC_MTIP_RS_FEC_SYMBLERR1_HI 0x3900c
79559 #define A_MAC_MTIP_RS_FEC_SYMBLERR2_LO 0x39010
79560 #define A_MAC_MTIP_RS_FEC_SYMBLERR2_HI 0x39014
79561 #define A_MAC_MTIP_RS_FEC_SYMBLERR3_LO 0x39018
79562 #define A_MAC_MTIP_RS_FEC_SYMBLERR3_HI 0x3901c
79563 #define A_MAC_MTIP_RS_FEC_SYMBLERR4_LO 0x39020
79565 #define S_RS_FEC_SYMBLERR4_LO    0
79569 #define A_MAC_MTIP_RS_FEC_SYMBLERR4_HI 0x39024
79571 #define S_RS_FEC_SYMBLERR4_HI    0
79575 #define A_MAC_MTIP_RS_FEC_SYMBLERR5_LO 0x39028
79577 #define S_RS_FEC_SYMBLERR5_LO    0
79581 #define A_MAC_MTIP_RS_FEC_SYMBLERR5_HI 0x3902c
79583 #define S_RS_FEC_SYMBLERR5_HI    0
79587 #define A_MAC_MTIP_RS_FEC_SYMBLERR6_LO 0x39030
79589 #define S_RS_FEC_SYMBLERR6_LO    0
79593 #define A_MAC_MTIP_RS_FEC_SYMBLERR6_HI 0x39034
79595 #define S_RS_FEC_SYMBLERR6_HI    0
79599 #define A_MAC_MTIP_RS_FEC_SYMBLERR7_LO 0x39038
79601 #define S_RS_FEC_SYMBLERR7_LO    0
79605 #define A_MAC_MTIP_RS_FEC_SYMBLERR7_HI 0x3903c
79607 #define S_RS_FEC_SYMBLERR7_HI    0
79611 #define A_MAC_MTIP_RS_FEC_SYMBLERR8_LO 0x39040
79613 #define S_RS_FEC_SYMBLERR8_LO    0
79617 #define A_MAC_MTIP_RS_FEC_SYMBLERR8_HI 0x39044
79619 #define S_RS_FEC_SYMBLERR8_HI    0
79623 #define A_MAC_MTIP_RS_FEC_SYMBLERR9_LO 0x39048
79625 #define S_RS_FEC_SYMBLERR9_LO    0
79629 #define A_MAC_MTIP_RS_FEC_SYMBLERR9_HI 0x3904c
79631 #define S_RS_FEC_SYMBLERR9_HI    0
79635 #define A_MAC_MTIP_RS_FEC_SYMBLERR10_LO 0x39050
79637 #define S_RS_FEC_SYMBLERR10_LO    0
79641 #define A_MAC_MTIP_RS_FEC_SYMBLERR10_HI 0x39054
79643 #define S_RS_FEC_SYMBLERR10_HI    0
79647 #define A_MAC_MTIP_RS_FEC_SYMBLERR11_LO 0x39058
79649 #define S_RS_FEC_SYMBLERR11_LO    0
79653 #define A_MAC_MTIP_RS_FEC_SYMBLERR11_HI 0x3905c
79655 #define S_RS_FEC_SYMBLERR11_HI    0
79659 #define A_MAC_MTIP_RS_FEC_SYMBLERR12_LO 0x39060
79661 #define S_RS_FEC_SYMBLERR12_LO    0
79665 #define A_MAC_MTIP_RS_FEC_SYMBLERR12_HI 0x39064
79667 #define S_RS_FEC_SYMBLERR12_HI    0
79671 #define A_MAC_MTIP_RS_FEC_SYMBLERR13_LO 0x39068
79673 #define S_RS_FEC_SYMBLERR13_LO    0
79677 #define A_MAC_MTIP_RS_FEC_SYMBLERR13_HI 0x3906c
79679 #define S_RS_FEC_SYMBLERR13_HI    0
79683 #define A_MAC_MTIP_RS_FEC_SYMBLERR14_LO 0x39070
79685 #define S_RS_FEC_SYMBLERR14_LO    0
79689 #define A_MAC_MTIP_RS_FEC_SYMBLERR14_HI 0x39074
79691 #define S_RS_FEC_SYMBLERR14_HI    0
79695 #define A_MAC_MTIP_RS_FEC_SYMBLERR15_LO 0x39078
79697 #define S_RS_FEC_SYMBLERR15_LO    0
79701 #define A_MAC_MTIP_RS_FEC_SYMBLERR15_HI 0x3907c
79703 #define S_RS_FEC_SYMBLERR15_HI    0
79707 #define A_MAC_MTIP_RS_FEC_VENDOR_CONTROL 0x39080
79708 #define A_MAC_MTIP_RS_FEC_VENDOR_INFO_1 0x39084
79710 #define S_VENDOR_INFO_1_AMPS_LOCK    0
79714 #define A_MAC_MTIP_RS_FEC_VENDOR_INFO_2 0x39088
79716 #define S_VENDOR_INFO_2_AMPS_LOCK    0
79717 #define M_VENDOR_INFO_2_AMPS_LOCK    0xffffU
79721 #define A_MAC_MTIP_RS_FEC_VENDOR_REVISION 0x3908c
79722 #define A_MAC_MTIP_RS_FEC_VENDOR_ALIGN_STATUS 0x39090
79724 #define S_RS_FEC_VENDOR_ALIGN_STATUS    0
79725 #define M_RS_FEC_VENDOR_ALIGN_STATUS    0xffffU
79729 #define A_MAC_MTIP_FEC74_FEC_ABILITY_0 0x39100
79735 #define S_FEC74_FEC_ABILITY_0_B0    0
79739 #define A_MAC_MTIP_FEC74_FEC_CONTROL_0 0x39104
79745 #define S_T7_FEC_ENABLE    0
79749 #define A_MAC_MTIP_FEC74_FEC_STATUS_0 0x39108
79755 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_0 0x3910c
79757 #define S_VL0_CCW_LO    0
79758 #define M_VL0_CCW_LO    0xffffU
79762 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_0 0x39110
79764 #define S_VL0_NCCW_LO    0
79765 #define M_VL0_NCCW_LO    0xffffU
79769 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_0 0x39114
79771 #define S_VL1_CCW_LO    0
79772 #define M_VL1_CCW_LO    0xffffU
79776 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_0 0x39118
79778 #define S_VL1_NCCW_LO    0
79779 #define M_VL1_NCCW_LO    0xffffU
79783 #define A_MAC_MTIP_FEC74_COUNTER_HI_0 0x3911c
79785 #define S_COUNTER_HI    0
79786 #define M_COUNTER_HI    0xffffU
79790 #define A_MAC_MTIP_FEC74_FEC_ABILITY_1 0x39120
79796 #define S_FEC74_FEC_ABILITY_1_B0    0
79800 #define A_MAC_MTIP_FEC74_FEC_CONTROL_1 0x39124
79801 #define A_MAC_MTIP_FEC74_FEC_STATUS_1 0x39128
79802 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_1 0x3912c
79803 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_1 0x39130
79804 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_1 0x39134
79805 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_1 0x39138
79806 #define A_MAC_MTIP_FEC74_COUNTER_HI_1 0x3913c
79807 #define A_MAC_MTIP_FEC74_FEC_ABILITY_2 0x39140
79813 #define S_FEC74_FEC_ABILITY_2_B0    0
79817 #define A_MAC_MTIP_FEC74_FEC_CONTROL_2 0x39144
79818 #define A_MAC_MTIP_FEC74_FEC_STATUS_2 0x39148
79819 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_2 0x3914c
79820 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_2 0x39150
79821 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_2 0x39154
79822 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_2 0x39158
79823 #define A_MAC_MTIP_FEC74_COUNTER_HI_2 0x3915c
79824 #define A_MAC_MTIP_FEC74_FEC_ABILITY_3 0x39160
79830 #define S_FEC74_FEC_ABILITY_3_B0    0
79834 #define A_MAC_MTIP_FEC74_FEC_CONTROL_3 0x39164
79835 #define A_MAC_MTIP_FEC74_FEC_STATUS_3 0x39168
79836 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_3 0x3916c
79837 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_3 0x39170
79838 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_3 0x39174
79839 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_3 0x39178
79840 #define A_MAC_MTIP_FEC74_COUNTER_HI_3 0x3917c
79841 #define A_MAC_MTIP_FEC74_FEC_ABILITY_4 0x39180
79847 #define S_FEC74_FEC_ABILITY_4_B0    0
79851 #define A_MAC_MTIP_FEC74_FEC_CONTROL_4 0x39184
79852 #define A_MAC_MTIP_FEC74_FEC_STATUS_4 0x39188
79853 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_4 0x3918c
79854 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_4 0x39190
79855 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_4 0x39194
79856 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_4 0x39198
79857 #define A_MAC_MTIP_FEC74_COUNTER_HI_4 0x3919c
79858 #define A_MAC_MTIP_FEC74_FEC_ABILITY_5 0x391a0
79864 #define S_FEC74_FEC_ABILITY_5_B0    0
79868 #define A_MAC_MTIP_FEC74_FEC_CONTROL_5 0x391a4
79869 #define A_MAC_MTIP_FEC74_FEC_STATUS_5 0x391a8
79870 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_5 0x391ac
79871 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_5 0x391b0
79872 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_5 0x391b4
79873 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_5 0x391b8
79874 #define A_MAC_MTIP_FEC74_COUNTER_HI_5 0x391bc
79875 #define A_MAC_MTIP_FEC74_FEC_ABILITY_6 0x391c0
79881 #define S_FEC74_FEC_ABILITY_6_B0    0
79885 #define A_MAC_MTIP_FEC74_FEC_CONTROL_6 0x391c4
79886 #define A_MAC_MTIP_FEC74_FEC_STATUS_6 0x391c8
79887 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_6 0x391cc
79888 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_6 0x391d0
79889 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_6 0x391d4
79890 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_6 0x391d8
79891 #define A_MAC_MTIP_FEC74_COUNTER_HI_6 0x391dc
79892 #define A_MAC_MTIP_FEC74_FEC_ABILITY_7 0x391e0
79898 #define S_FEC74_FEC_ABILITY_7_B0    0
79902 #define A_MAC_MTIP_FEC74_FEC_CONTROL_7 0x391e4
79903 #define A_MAC_MTIP_FEC74_FEC_STATUS_7 0x391e8
79904 #define A_MAC_MTIP_FEC74_VL0_CCW_LO_7 0x391ec
79905 #define A_MAC_MTIP_FEC74_VL0_NCCW_LO_7 0x391f0
79906 #define A_MAC_MTIP_FEC74_VL1_CCW_LO_7 0x391f4
79907 #define A_MAC_MTIP_FEC74_VL1_NCCW_LO_7 0x391f8
79908 #define A_MAC_MTIP_FEC74_COUNTER_HI_7 0x391fc
79909 #define A_MAC_BEAN0_CTL 0x39200
79910 #define A_MAC_BEAN0_STATUS 0x39204
79911 #define A_MAC_BEAN0_ABILITY_0 0x39208
79917 #define A_MAC_BEAN0_ABILITY_1 0x3920c
79918 #define A_MAC_BEAN0_ABILITY_2 0x39210
79921 #define M_BEAN0_AB_2_15_12    0xfU
79925 #define S_BEAN0_AB_2_11_0    0
79926 #define M_BEAN0_AB_2_11_0    0xfffU
79930 #define A_MAC_BEAN0_REM_ABILITY_0 0x39214
79936 #define A_MAC_BEAN0_REM_ABILITY_1 0x39218
79937 #define A_MAC_BEAN0_REM_ABILITY_2 0x3921c
79940 #define M_BEAN0_REM_AB_15_12    0xfU
79944 #define S_BEAN0_REM_AB_11_0    0
79945 #define M_BEAN0_REM_AB_11_0    0xfffU
79949 #define A_MAC_BEAN0_MS_COUNT 0x39220
79950 #define A_MAC_BEAN0_XNP_0 0x39224
79951 #define A_MAC_BEAN0_XNP_1 0x39228
79952 #define A_MAC_BEAN0_XNP_2 0x3922c
79953 #define A_MAC_LP_BEAN0_XNP_0 0x39230
79954 #define A_MAC_LP_BEAN0_XNP_1 0x39234
79955 #define A_MAC_LP_BEAN0_XNP_2 0x39238
79956 #define A_MAC_BEAN0_ETH_STATUS 0x3923c
79982 #define A_MAC_BEAN0_ETH_STATUS_2 0x39240
80008 #define S_50GKRCR    0
80012 #define A_MAC_BEAN1_CTL 0x39300
80013 #define A_MAC_BEAN1_STATUS 0x39304
80014 #define A_MAC_BEAN1_ABILITY_0 0x39308
80020 #define A_MAC_BEAN1_ABILITY_1 0x3930c
80021 #define A_MAC_BEAN1_ABILITY_2 0x39310
80024 #define M_BEAN1_AB_2_15_12    0xfU
80028 #define S_BEAN1_AB_2_11_0    0
80029 #define M_BEAN1_AB_2_11_0    0xfffU
80033 #define A_MAC_BEAN1_REM_ABILITY_0 0x39314
80039 #define A_MAC_BEAN1_REM_ABILITY_1 0x39318
80040 #define A_MAC_BEAN1_REM_ABILITY_2 0x3931c
80043 #define M_BEAN1_REM_AB_15_12    0xfU
80047 #define S_BEAN1_REM_AB_11_0    0
80048 #define M_BEAN1_REM_AB_11_0    0xfffU
80052 #define A_MAC_BEAN1_MS_COUNT 0x39320
80053 #define A_MAC_BEAN1_XNP_0 0x39324
80054 #define A_MAC_BEAN1_XNP_1 0x39328
80055 #define A_MAC_BEAN1_XNP_2 0x3932c
80056 #define A_MAC_LP_BEAN1_XNP_0 0x39330
80057 #define A_MAC_LP_BEAN1_XNP_1 0x39334
80058 #define A_MAC_LP_BEAN1_XNP_2 0x39338
80059 #define A_MAC_BEAN1_ETH_STATUS 0x3933c
80060 #define A_MAC_BEAN1_ETH_STATUS_2 0x39340
80061 #define A_MAC_BEAN2_CTL 0x39400
80062 #define A_MAC_BEAN2_STATUS 0x39404
80063 #define A_MAC_BEAN2_ABILITY_0 0x39408
80069 #define A_MAC_BEAN2_ABILITY_1 0x3940c
80070 #define A_MAC_BEAN2_ABILITY_2 0x39410
80073 #define M_BEAN2_AB_2_15_12    0xfU
80077 #define S_BEAN2_AB_2_11_0    0
80078 #define M_BEAN2_AB_2_11_0    0xfffU
80082 #define A_MAC_BEAN2_REM_ABILITY_0 0x39414
80088 #define A_MAC_BEAN2_REM_ABILITY_1 0x39418
80089 #define A_MAC_BEAN2_REM_ABILITY_2 0x3941c
80092 #define M_BEAN2_REM_AB_15_12    0xfU
80096 #define S_BEAN2_REM_AB_11_0    0
80097 #define M_BEAN2_REM_AB_11_0    0xfffU
80101 #define A_MAC_BEAN2_MS_COUNT 0x39420
80102 #define A_MAC_BEAN2_XNP_0 0x39424
80103 #define A_MAC_BEAN2_XNP_1 0x39428
80104 #define A_MAC_BEAN2_XNP_2 0x3942c
80105 #define A_MAC_LP_BEAN2_XNP_0 0x39430
80106 #define A_MAC_LP_BEAN2_XNP_1 0x39434
80107 #define A_MAC_LP_BEAN2_XNP_2 0x39438
80108 #define A_MAC_BEAN2_ETH_STATUS 0x3943c
80109 #define A_MAC_BEAN2_ETH_STATUS_2 0x39440
80110 #define A_MAC_BEAN3_CTL 0x39500
80111 #define A_MAC_BEAN3_STATUS 0x39504
80112 #define A_MAC_BEAN3_ABILITY_0 0x39508
80118 #define A_MAC_BEAN3_ABILITY_1 0x3950c
80119 #define A_MAC_BEAN3_ABILITY_2 0x39510
80122 #define M_BEAN3_AB_2_15_12    0xfU
80126 #define S_BEAN3_AB_2_11_0    0
80127 #define M_BEAN3_AB_2_11_0    0xfffU
80131 #define A_MAC_BEAN3_REM_ABILITY_0 0x39514
80137 #define A_MAC_BEAN3_REM_ABILITY_1 0x39518
80138 #define A_MAC_BEAN3_REM_ABILITY_2 0x3951c
80141 #define M_BEAN3_REM_AB_15_12    0xfU
80145 #define S_BEAN3_REM_AB_11_0    0
80146 #define M_BEAN3_REM_AB_11_0    0xfffU
80150 #define A_MAC_BEAN3_MS_COUNT 0x39520
80151 #define A_MAC_BEAN3_XNP_0 0x39524
80152 #define A_MAC_BEAN3_XNP_1 0x39528
80153 #define A_MAC_BEAN3_XNP_2 0x3952c
80154 #define A_MAC_LP_BEAN3_XNP_0 0x39530
80155 #define A_MAC_LP_BEAN3_XNP_1 0x39534
80156 #define A_MAC_LP_BEAN3_XNP_2 0x39538
80157 #define A_MAC_BEAN3_ETH_STATUS 0x3953c
80158 #define A_MAC_BEAN3_ETH_STATUS_2 0x39540
80159 #define A_MAC_BEAN4_CTL 0x39600
80160 #define A_MAC_BEAN4_STATUS 0x39604
80161 #define A_MAC_BEAN4_ABILITY_0 0x39608
80167 #define A_MAC_BEAN4_ABILITY_1 0x3960c
80168 #define A_MAC_BEAN4_ABILITY_2 0x39610
80171 #define M_BEAN4_AB_2_15_12    0xfU
80175 #define S_BEAN4_AB_2_11_0    0
80176 #define M_BEAN4_AB_2_11_0    0xfffU
80180 #define A_MAC_BEAN4_REM_ABILITY_0 0x39614
80186 #define A_MAC_BEAN4_REM_ABILITY_1 0x39618
80187 #define A_MAC_BEAN4_REM_ABILITY_2 0x3961c
80190 #define M_BEAN4_REM_AB_15_12    0xfU
80194 #define S_BEAN4_REM_AB_11_0    0
80195 #define M_BEAN4_REM_AB_11_0    0xfffU
80199 #define A_MAC_BEAN4_MS_COUNT 0x39620
80200 #define A_MAC_BEAN4_XNP_0 0x39624
80201 #define A_MAC_BEAN4_XNP_1 0x39628
80202 #define A_MAC_BEAN4_XNP_2 0x3962c
80203 #define A_MAC_LP_BEAN4_XNP_0 0x39630
80204 #define A_MAC_LP_BEAN4_XNP_1 0x39634
80205 #define A_MAC_LP_BEAN4_XNP_2 0x39638
80206 #define A_MAC_BEAN4_ETH_STATUS 0x3963c
80207 #define A_MAC_BEAN4_ETH_STATUS_2 0x39640
80208 #define A_MAC_BEAN5_CTL 0x39700
80209 #define A_MAC_BEAN5_STATUS 0x39704
80210 #define A_MAC_BEAN5_ABILITY_0 0x39708
80216 #define A_MAC_BEAN5_ABILITY_1 0x3970c
80217 #define A_MAC_BEAN5_ABILITY_2 0x39710
80220 #define M_BEAN5_AB_2_15_12    0xfU
80224 #define S_BEAN5_AB_2_11_0    0
80225 #define M_BEAN5_AB_2_11_0    0xfffU
80229 #define A_MAC_BEAN5_REM_ABILITY_0 0x39714
80235 #define A_MAC_BEAN5_REM_ABILITY_1 0x39718
80236 #define A_MAC_BEAN5_REM_ABILITY_2 0x3971c
80239 #define M_BEAN5_REM_AB_15_12    0xfU
80243 #define S_BEAN5_REM_AB_11_0    0
80244 #define M_BEAN5_REM_AB_11_0    0xfffU
80248 #define A_MAC_BEAN5_MS_COUNT 0x39720
80249 #define A_MAC_BEAN5_XNP_0 0x39724
80250 #define A_MAC_BEAN5_XNP_1 0x39728
80251 #define A_MAC_BEAN5_XNP_2 0x3972c
80252 #define A_MAC_LP_BEAN5_XNP_0 0x39730
80253 #define A_MAC_LP_BEAN5_XNP_1 0x39734
80254 #define A_MAC_LP_BEAN5_XNP_2 0x39738
80255 #define A_MAC_BEAN5_ETH_STATUS 0x3973c
80256 #define A_MAC_BEAN5_ETH_STATUS_2 0x39740
80257 #define A_MAC_BEAN6_CTL 0x39800
80258 #define A_MAC_BEAN6_STATUS 0x39804
80259 #define A_MAC_BEAN6_ABILITY_0 0x39808
80265 #define A_MAC_BEAN6_ABILITY_1 0x3980c
80266 #define A_MAC_BEAN6_ABILITY_2 0x39810
80269 #define M_BEAN6_AB_2_15_12    0xfU
80273 #define S_BEAN6_AB_2_11_0    0
80274 #define M_BEAN6_AB_2_11_0    0xfffU
80278 #define A_MAC_BEAN6_REM_ABILITY_0 0x39814
80284 #define A_MAC_BEAN6_REM_ABILITY_1 0x39818
80285 #define A_MAC_BEAN6_REM_ABILITY_2 0x3981c
80288 #define M_BEAN6_REM_AB_15_12    0xfU
80292 #define S_BEAN6_REM_AB_11_0    0
80293 #define M_BEAN6_REM_AB_11_0    0xfffU
80297 #define A_MAC_BEAN6_MS_COUNT 0x39820
80298 #define A_MAC_BEAN6_XNP_0 0x39824
80299 #define A_MAC_BEAN6_XNP_1 0x39828
80300 #define A_MAC_BEAN6_XNP_2 0x3982c
80301 #define A_MAC_LP_BEAN6_XNP_0 0x39830
80302 #define A_MAC_LP_BEAN6_XNP_1 0x39834
80303 #define A_MAC_LP_BEAN6_XNP_2 0x39838
80304 #define A_MAC_BEAN6_ETH_STATUS 0x3983c
80305 #define A_MAC_BEAN6_ETH_STATUS_2 0x39840
80306 #define A_MAC_BEAN7_CTL 0x39900
80307 #define A_MAC_BEAN7_STATUS 0x39904
80308 #define A_MAC_BEAN7_ABILITY_0 0x39908
80314 #define A_MAC_BEAN7_ABILITY_1 0x3990c
80315 #define A_MAC_BEAN7_ABILITY_2 0x39910
80318 #define M_BEAN7_AB_2_15_12    0xfU
80322 #define S_BEAN7_AB_2_11_0    0
80323 #define M_BEAN7_AB_2_11_0    0xfffU
80327 #define A_MAC_BEAN7_REM_ABILITY_0 0x39914
80333 #define A_MAC_BEAN7_REM_ABILITY_1 0x39918
80334 #define A_MAC_BEAN7_REM_ABILITY_2 0x3991c
80337 #define M_BEAN7_REM_AB_15_12    0xfU
80341 #define S_BEAN7_REM_AB_11_0    0
80342 #define M_BEAN7_REM_AB_11_0    0xfffU
80346 #define A_MAC_BEAN7_MS_COUNT 0x39920
80347 #define A_MAC_BEAN7_XNP_0 0x39924
80348 #define A_MAC_BEAN7_XNP_1 0x39928
80349 #define A_MAC_BEAN7_XNP_2 0x3992c
80350 #define A_MAC_LP_BEAN7_XNP_0 0x39930
80351 #define A_MAC_LP_BEAN7_XNP_1 0x39934
80352 #define A_MAC_LP_BEAN7_XNP_2 0x39938
80353 #define A_MAC_BEAN7_ETH_STATUS 0x3993c
80354 #define A_MAC_BEAN7_ETH_STATUS_2 0x39940
80355 #define A_MAC_MTIP_ETHERSTATS_DATA_HI 0x39a00
80356 #define A_MAC_MTIP_ETHERSTATS_STATN_STATUS 0x39a04
80357 #define A_MAC_MTIP_ETHERSTATS_STATN_CONFIG 0x39a08
80363 #define A_MAC_MTIP_ETHERSTATS_STATN_CONTROL 0x39a0c
80385 #define S_PORTMASK    0
80386 #define M_PORTMASK    0xffU
80390 #define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_LO 0x39a10
80392 #define S_STATN_CLEARVALUE_LO    0
80396 #define A_MAC_MTIP_ETHERSTATS_STATN_CLEARVALUE_HI 0x39a14
80398 #define S_STATN_CLEARVALUE_HI    0
80402 #define A_MAC_MTIP_ETHERSTATS_DATA_HI_1 0x39a1c
80403 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_0 0x39a20
80404 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_1 0x39a24
80405 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_2 0x39a28
80406 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_3 0x39a2c
80407 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_4 0x39a30
80408 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_5 0x39a34
80409 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_6 0x39a38
80410 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_7 0x39a3c
80411 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_8 0x39a40
80412 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_9 0x39a44
80413 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_10 0x39a48
80414 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_11 0x39a4c
80415 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_12 0x39a50
80416 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_13 0x39a54
80417 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_14 0x39a58
80418 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_15 0x39a5c
80419 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_16 0x39a60
80420 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_17 0x39a64
80421 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_18 0x39a68
80422 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_19 0x39a6c
80423 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_20 0x39a70
80424 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_21 0x39a74
80425 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_22 0x39a78
80426 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_23 0x39a7c
80427 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_24 0x39a80
80428 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_25 0x39a84
80429 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_26 0x39a88
80430 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_27 0x39a8c
80431 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_28 0x39a90
80432 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_29 0x39a94
80433 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_30 0x39a98
80434 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_31 0x39a9c
80435 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_32 0x39aa0
80436 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_33 0x39aa4
80437 #define A_MAC_MTIP_ETHERSTATS_CAPTURED_PAGE_34 0x39aa8
80438 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS 0x39b00
80439 #define A_MAC_MTIP_ETHERSTATS0_OCTETSRECEIVEDOK 0x39b04
80440 #define A_MAC_MTIP_ETHERSTATS0_AALIGNMENTERRORS 0x39b08
80441 #define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESRECEIVED 0x39b0c
80442 #define A_MAC_MTIP_ETHERSTATS0_AFRAMETOOLONGERRORS 0x39b10
80443 #define A_MAC_MTIP_ETHERSTATS0_AINRANGELENGTHERRORS 0x39b14
80444 #define A_MAC_MTIP_ETHERSTATS0_AFRAMESRECEIVEDOK 0x39b18
80445 #define A_MAC_MTIP_ETHERSTATS0_AFRAMECHECKSEQUENCEERRORS 0x39b1c
80446 #define A_MAC_MTIP_ETHERSTATS0_VLANRECEIVEDOK 0x39b20
80447 #define A_MAC_MTIP_ETHERSTATS0_IFINERRORS_RX 0x39b24
80448 #define A_MAC_MTIP_ETHERSTATS0_IFINUCASTPKTS_RX 0x39b28
80449 #define A_MAC_MTIP_ETHERSTATS0_IFINMULTICASTPKTS_RX 0x39b2c
80450 #define A_MAC_MTIP_ETHERSTATS0_IFINBROADCASTPKTS_RX 0x39b30
80451 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSDROPEVENTS_RX 0x39b34
80452 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_RX 0x39b38
80453 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSUNDERSIZEPKTS_RX 0x39b3c
80454 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_RX 0x39b40
80455 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_RX 0x39b44
80456 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_RX 0x39b48
80457 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_RX 0x39b4c
80458 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39b50
80459 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39b54
80460 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39b58
80461 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOVERSIZEPKTS_RX 0x39b5c
80462 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSJABBERS_RX 0x39b60
80463 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSFRAGMENTS_RX 0x39b64
80464 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39b68
80465 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39b6c
80466 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39b70
80467 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39b74
80468 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39b78
80469 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39b7c
80470 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39b80
80471 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39b84
80472 #define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESRECEIVED_RX 0x39b88
80473 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS 0x39b8c
80474 #define A_MAC_MTIP_ETHERSTATS1_OCTETSRECEIVEDOK 0x39b90
80475 #define A_MAC_MTIP_ETHERSTATS1_AALIGNMENTERRORS 0x39b94
80476 #define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESRECEIVED 0x39b98
80477 #define A_MAC_MTIP_ETHERSTATS1_AFRAMETOOLONGERRORS 0x39b9c
80478 #define A_MAC_MTIP_ETHERSTATS1_AINRANGELENGTHERRORS 0x39ba0
80479 #define A_MAC_MTIP_ETHERSTATS1_AFRAMESRECEIVEDOK 0x39ba4
80480 #define A_MAC_MTIP_ETHERSTATS1_AFRAMECHECKSEQUENCEERRORS 0x39ba8
80481 #define A_MAC_MTIP_ETHERSTATS1_VLANRECEIVEDOK 0x39bac
80482 #define A_MAC_MTIP_ETHERSTATS1_IFINERRORS_RX 0x39bb0
80483 #define A_MAC_MTIP_ETHERSTATS1_IFINUCASTPKTS_RX 0x39bb4
80484 #define A_MAC_MTIP_ETHERSTATS1_IFINMULTICASTPKTS_RX 0x39bb8
80485 #define A_MAC_MTIP_ETHERSTATS1_IFINBROADCASTPKTS_RX 0x39bbc
80486 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSDROPEVENTS_RX 0x39bc0
80487 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_RX 0x39bc4
80488 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSUNDERSIZEPKTS_RX 0x39bc8
80489 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_RX 0x39bcc
80490 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_RX 0x39bd0
80491 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_RX 0x39bd4
80492 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_RX 0x39bd8
80493 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39bdc
80494 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39be0
80495 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39be4
80496 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOVERSIZEPKTS_RX 0x39be8
80497 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSJABBERS_RX 0x39bec
80498 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSFRAGMENTS_RX 0x39bf0
80499 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39bf4
80500 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39bf8
80501 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39bfc
80502 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c00
80503 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c04
80504 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c08
80505 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c0c
80506 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c10
80507 #define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESRECEIVED_RX 0x39c14
80508 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS 0x39c18
80509 #define A_MAC_MTIP_ETHERSTATS2_OCTETSRECEIVEDOK 0x39c1c
80510 #define A_MAC_MTIP_ETHERSTATS2_AALIGNMENTERRORS 0x39c20
80511 #define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESRECEIVED 0x39c24
80512 #define A_MAC_MTIP_ETHERSTATS2_AFRAMETOOLONGERRORS 0x39c28
80513 #define A_MAC_MTIP_ETHERSTATS2_AINRANGELENGTHERRORS 0x39c2c
80514 #define A_MAC_MTIP_ETHERSTATS2_AFRAMESRECEIVEDOK 0x39c30
80515 #define A_MAC_MTIP_ETHERSTATS2_AFRAMECHECKSEQUENCEERRORS 0x39c34
80516 #define A_MAC_MTIP_ETHERSTATS2_VLANRECEIVEDOK 0x39c38
80517 #define A_MAC_MTIP_ETHERSTATS2_IFINERRORS_RX 0x39c3c
80518 #define A_MAC_MTIP_ETHERSTATS2_IFINUCASTPKTS_RX 0x39c40
80519 #define A_MAC_MTIP_ETHERSTATS2_IFINMULTICASTPKTS_RX 0x39c44
80520 #define A_MAC_MTIP_ETHERSTATS2_IFINBROADCASTPKTS_RX 0x39c48
80521 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSDROPEVENTS_RX 0x39c4c
80522 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_RX 0x39c50
80523 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSUNDERSIZEPKTS_RX 0x39c54
80524 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_RX 0x39c58
80525 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_RX 0x39c5c
80526 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_RX 0x39c60
80527 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_RX 0x39c64
80528 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39c68
80529 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39c6c
80530 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39c70
80531 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOVERSIZEPKTS_RX 0x39c74
80532 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSJABBERS_RX 0x39c78
80533 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSFRAGMENTS_RX 0x39c7c
80534 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39c80
80535 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39c84
80536 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39c88
80537 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39c8c
80538 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39c90
80539 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39c94
80540 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39c98
80541 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39c9c
80542 #define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESRECEIVED_RX 0x39ca0
80543 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS 0x39ca4
80544 #define A_MAC_MTIP_ETHERSTATS3_OCTETSRECEIVEDOK 0x39ca8
80545 #define A_MAC_MTIP_ETHERSTATS3_AALIGNMENTERRORS 0x39cac
80546 #define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESRECEIVED 0x39cb0
80547 #define A_MAC_MTIP_ETHERSTATS3_AFRAMETOOLONGERRORS 0x39cb4
80548 #define A_MAC_MTIP_ETHERSTATS3_AINRANGELENGTHERRORS 0x39cb8
80549 #define A_MAC_MTIP_ETHERSTATS3_AFRAMESRECEIVEDOK 0x39cbc
80550 #define A_MAC_MTIP_ETHERSTATS3_AFRAMECHECKSEQUENCEERRORS 0x39cc0
80551 #define A_MAC_MTIP_ETHERSTATS3_VLANRECEIVEDOK 0x39cc4
80552 #define A_MAC_MTIP_ETHERSTATS3_IFINERRORS_RX 0x39cc8
80553 #define A_MAC_MTIP_ETHERSTATS3_IFINUCASTPKTS_RX 0x39ccc
80554 #define A_MAC_MTIP_ETHERSTATS3_IFINMULTICASTPKTS_RX 0x39cd0
80555 #define A_MAC_MTIP_ETHERSTATS3_IFINBROADCASTPKTS_RX 0x39cd4
80556 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSDROPEVENTS_RX 0x39cd8
80557 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_RX 0x39cdc
80558 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSUNDERSIZEPKTS_RX 0x39ce0
80559 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_RX 0x39ce4
80560 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_RX 0x39ce8
80561 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_RX 0x39cec
80562 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_RX 0x39cf0
80563 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_RX 0x39cf4
80564 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_RX 0x39cf8
80565 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_RX 0x39cfc
80566 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOVERSIZEPKTS_RX 0x39d00
80567 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSJABBERS_RX 0x39d04
80568 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSFRAGMENTS_RX 0x39d08
80569 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_0_RX 0x39d0c
80570 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_1_RX 0x39d10
80571 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_2_RX 0x39d14
80572 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_3_RX 0x39d18
80573 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_4_RX 0x39d1c
80574 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_5_RX 0x39d20
80575 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_6_RX 0x39d24
80576 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESRECEIVED_7_RX 0x39d28
80577 #define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESRECEIVED_RX 0x39d2c
80578 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSOCTETS_TX 0x39d30
80579 #define A_MAC_MTIP_ETHERSTATS0_OCTETSTRANSMITTEDOK_TX 0x39d34
80580 #define A_MAC_MTIP_ETHERSTATS0_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39d38
80581 #define A_MAC_MTIP_ETHERSTATS0_AFRAMESTRANSMITTEDOK_TX 0x39d3c
80582 #define A_MAC_MTIP_ETHERSTATS0_VLANTRANSMITTEDOK_TX 0x39d40
80583 #define A_MAC_MTIP_ETHERSTATS0_IFOUTERRORS_TX 0x39d44
80584 #define A_MAC_MTIP_ETHERSTATS0_IFOUTUCASTPKTS_TX 0x39d48
80585 #define A_MAC_MTIP_ETHERSTATS0IFOUTMULTICASTPKTS_TX 0x39d4c
80586 #define A_MAC_MTIP_ETHERSTATS0_IFOUTBROADCASTPKTS_TX 0x39d50
80587 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS64OCTETS_TX 0x39d54
80588 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS65TO127OCTETS_TX 0x39d58
80589 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS128TO255OCTETS_TX 0x39d5c
80590 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS256TO511OCTETS_TX 0x39d60
80591 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39d64
80592 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39d68
80593 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39d6c
80594 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39d70
80595 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39d74
80596 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39d78
80597 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39d7c
80598 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39d80
80599 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39d84
80600 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39d88
80601 #define A_MAC_MTIP_ETHERSTATS0_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39d8c
80602 #define A_MAC_MTIP_ETHERSTATS0_AMACCONTROLFRAMESTRANSMITTED_TX 0x39d90
80603 #define A_MAC_MTIP_ETHERSTATS0_ETHERSTATSPKTS_TX 0x39d94
80604 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSOCTETS_TX 0x39d98
80605 #define A_MAC_MTIP_ETHERSTATS1_OCTETSTRANSMITTEDOK_TX 0x39d9c
80606 #define A_MAC_MTIP_ETHERSTATS1_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39da0
80607 #define A_MAC_MTIP_ETHERSTATS1_AFRAMESTRANSMITTEDOK_TX 0x39da4
80608 #define A_MAC_MTIP_ETHERSTATS1_VLANTRANSMITTEDOK_TX 0x39da8
80609 #define A_MAC_MTIP_ETHERSTATS1_IFOUTERRORS_TX 0x39dac
80610 #define A_MAC_MTIP_ETHERSTATS1_IFOUTUCASTPKTS_TX 0x39db0
80611 #define A_MAC_MTIP_ETHERSTATS1IFOUTMULTICASTPKTS_TX 0x39db4
80612 #define A_MAC_MTIP_ETHERSTATS1_IFOUTBROADCASTPKTS_TX 0x39db8
80613 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS64OCTETS_TX 0x39dbc
80614 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS65TO127OCTETS_TX 0x39dc0
80615 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS128TO255OCTETS_TX 0x39dc4
80616 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS256TO511OCTETS_TX 0x39dc8
80617 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39dcc
80618 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39dd0
80619 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39dd4
80620 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39dd8
80621 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39ddc
80622 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39de0
80623 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39de4
80624 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39de8
80625 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39dec
80626 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39df0
80627 #define A_MAC_MTIP_ETHERSTATS1_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39df4
80628 #define A_MAC_MTIP_ETHERSTATS1_AMACCONTROLFRAMESTRANSMITTED_TX 0x39df8
80629 #define A_MAC_MTIP_ETHERSTATS1_ETHERSTATSPKTS_TX 0x39dfc
80630 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSOCTETS_TX 0x39e00
80631 #define A_MAC_MTIP_ETHERSTATS2_OCTETSTRANSMITTEDOK_TX 0x39e04
80632 #define A_MAC_MTIP_ETHERSTATS2_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e08
80633 #define A_MAC_MTIP_ETHERSTATS2_AFRAMESTRANSMITTEDOK_TX 0x39e0c
80634 #define A_MAC_MTIP_ETHERSTATS2_VLANTRANSMITTEDOK_TX 0x39e10
80635 #define A_MAC_MTIP_ETHERSTATS2_IFOUTERRORS_TX 0x39e14
80636 #define A_MAC_MTIP_ETHERSTATS2_IFOUTUCASTPKTS_TX 0x39e18
80637 #define A_MAC_MTIP_ETHERSTATS2IFOUTMULTICASTPKTS_TX 0x39e1c
80638 #define A_MAC_MTIP_ETHERSTATS2_IFOUTBROADCASTPKTS_TX 0x39e20
80639 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS64OCTETS_TX 0x39e24
80640 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e28
80641 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e2c
80642 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e30
80643 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e34
80644 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39e38
80645 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39e3c
80646 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39e40
80647 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39e44
80648 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39e48
80649 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39e4c
80650 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39e50
80651 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39e54
80652 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39e58
80653 #define A_MAC_MTIP_ETHERSTATS2_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39e5c
80654 #define A_MAC_MTIP_ETHERSTATS2_AMACCONTROLFRAMESTRANSMITTED_TX 0x39e60
80655 #define A_MAC_MTIP_ETHERSTATS2_ETHERSTATSPKTS_TX 0x39e64
80656 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSOCTETS_TX 0x39e68
80657 #define A_MAC_MTIP_ETHERSTATS3_OCTETSTRANSMITTEDOK_TX 0x39e6c
80658 #define A_MAC_MTIP_ETHERSTATS3_APAUSEMACCTRLFRAMESTRANSMITTED_TX 0x39e70
80659 #define A_MAC_MTIP_ETHERSTATS3_AFRAMESTRANSMITTEDOK_TX 0x39e74
80660 #define A_MAC_MTIP_ETHERSTATS3_VLANTRANSMITTEDOK_TX 0x39e78
80661 #define A_MAC_MTIP_ETHERSTATS3_IFOUTERRORS_TX 0x39e7c
80662 #define A_MAC_MTIP_ETHERSTATS3_IFOUTUCASTPKTS_TX 0x39e80
80663 #define A_MAC_MTIP_ETHERSTATS3IFOUTMULTICASTPKTS_TX 0x39e84
80664 #define A_MAC_MTIP_ETHERSTATS3_IFOUTBROADCASTPKTS_TX 0x39e88
80665 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS64OCTETS_TX 0x39e8c
80666 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS65TO127OCTETS_TX 0x39e90
80667 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS128TO255OCTETS_TX 0x39e94
80668 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS256TO511OCTETS_TX 0x39e98
80669 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS512TO1023OCTETS_TX 0x39e9c
80670 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1024TO1518OCTETS_TX 0x39ea0
80671 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS1519TOMAXOCTETS_TX 0x39ea4
80672 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_0_TX 0x39ea8
80673 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_1_TX 0x39eac
80674 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_2_TX 0x39eb0
80675 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_3_TX 0x39eb4
80676 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_4_TX 0x39eb8
80677 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_5_TX 0x39ebc
80678 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_6_TX 0x39ec0
80679 #define A_MAC_MTIP_ETHERSTATS3_ACBFCPAUSEFRAMESTRANSMITTED_7_TX 0x39ec4
80680 #define A_MAC_MTIP_ETHERSTATS3_AMACCONTROLFRAMESTRANSMITTED_TX 0x39ec8
80681 #define A_MAC_MTIP_ETHERSTATS3_ETHERSTATSPKTS_TX 0x39ecc
80682 #define A_MAC_IOS_CTRL 0x3a000
80685 #define M_SUB_BLOCK_SEL    0x7U
80697 #define S_T7_2_ADDR    0
80698 #define M_T7_2_ADDR    0x7ffffU
80702 #define A_MAC_IOS_DATA 0x3a004
80703 #define A_MAC_IOS_BGR_RST 0x3a050
80705 #define S_BGR_RSTN    0
80709 #define A_MAC_IOS_BGR_CFG 0x3a054
80711 #define S_SOC_REFCLK_EN    0
80715 #define A_MAC_IOS_QUAD0_CFG 0x3a058
80737 #define S_PLL0_RSTN    0
80741 #define A_MAC_IOS_QUAD1_CFG 0x3a05c
80763 #define S_PLL1_RSTN    0
80767 #define A_MAC_IOS_SCRATCHPAD0 0x3a060
80768 #define A_MAC_IOS_SCRATCHPAD1 0x3a064
80769 #define A_MAC_IOS_SCRATCHPAD2 0x3a068
80770 #define A_MAC_IOS_SCRATCHPAD3 0x3a06c
80773 #define M_DATA0    0x7fffffffU
80777 #define S_I2C_MODE    0
80781 #define A_MAC_IOS_BGR_DBG_COUNTER 0x3a070
80782 #define A_MAC_IOS_QUAD0_DBG_COUNTER 0x3a074
80783 #define A_MAC_IOS_PLL0_DBG_COUNTER 0x3a078
80784 #define A_MAC_IOS_QUAD1_DBG_COUNTER 0x3a07c
80785 #define A_MAC_IOS_PLL1_DBG_COUNTER 0x3a080
80786 #define A_MAC_IOS_DBG_CLK_CFG 0x3a084
80792 #define S_DBG_CLK_MUX_SEL    0
80793 #define M_DBG_CLK_MUX_SEL    0x7U
80797 #define A_MAC_IOS_INTR_EN_QUAD0 0x3a090
80895 #define S_Q0_LOS_0_ASSERT    0
80899 #define A_MAC_IOS_INTR_CAUSE_QUAD0 0x3a094
80900 #define A_MAC_IOS_INTR_EN_QUAD1 0x3a098
80998 #define S_Q1_LOS_0_ASSERT    0
81002 #define A_MAC_IOS_INTR_CAUSE_QUAD1 0x3a09c
81003 #define A_MAC_HSS0_PMD_RECEIVE_SIGNAL_DETECT 0x3a93c
81021 #define A_MAC_HSS1_PMD_RECEIVE_SIGNAL_DETECT 0x3b93c
81022 #define A_MAC_HSS2_PMD_RECEIVE_SIGNAL_DETECT 0x3c93c
81023 #define A_MAC_HSS3_PMD_RECEIVE_SIGNAL_DETECT 0x3d93c
81024 #define A_MAC_MTIP_PCS_1G_0_CONTROL 0x3e000
81046 #define A_MAC_MTIP_PCS_1G_0_STATUS 0x3e004
81096 #define S_EXTENDED_CAPABILITY    0
81100 #define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_0 0x3e008
81101 #define A_MAC_MTIP_PCS_1G_0_PHY_IDENTIFIER_1 0x3e00c
81102 #define A_MAC_MTIP_PCS_1G_0_DEV_ABILITY 0x3e010
81108 #define A_MAC_MTIP_PCS_1G_0_PARTNER_ABILITY 0x3e014
81119 #define M_COPPER_SPEED    0x3U
81131 #define A_MAC_MTIP_PCS_1G_0_AN_EXPANSION 0x3e018
81132 #define A_MAC_MTIP_PCS_1G_0_NP_TX 0x3e01c
81133 #define A_MAC_MTIP_PCS_1G_0_LP_NP_RX 0x3e020
81135 #define S_T7_DATA    0
81136 #define M_T7_DATA    0x7ffU
81140 #define A_MAC_MTIP_PCS_1G_0_EXTENDED_STATUS 0x3e03c
81141 #define A_MAC_MTIP_PCS_1G_0_SCRATCH 0x3e040
81142 #define A_MAC_MTIP_PCS_1G_0_REV 0x3e044
81143 #define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_0 0x3e048
81145 #define S_LINK_TIMER_VAL    0
81146 #define M_LINK_TIMER_VAL    0xffffU
81150 #define A_MAC_MTIP_PCS_1G_0_LINK_TIMER_1 0x3e04c
81152 #define S_T7_LINK_TIMER_VAL    0
81153 #define M_T7_LINK_TIMER_VAL    0x1fU
81157 #define A_MAC_MTIP_PCS_1G_0_IF_MODE 0x3e050
81158 #define A_MAC_MTIP_PCS_1G_0_DEC_ERR_CNT 0x3e054
81159 #define A_MAC_MTIP_PCS_1G_0_VENDOR_CONTROL 0x3e058
81166 #define M_T7_CFG_CLOCK_RATE    0xfU
81170 #define S_SGPCS_ENA_R    0
81174 #define A_MAC_MTIP_PCS_1G_0_SD_BIT_SLIP 0x3e05c
81176 #define S_SD_BIT_SLIP    0
81177 #define M_SD_BIT_SLIP    0xfU
81181 #define A_MAC_MTIP_PCS_1G_1_CONTROL 0x3e100
81182 #define A_MAC_MTIP_PCS_1G_1_STATUS 0x3e104
81183 #define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_0 0x3e108
81184 #define A_MAC_MTIP_PCS_1G_1_PHY_IDENTIFIER_1 0x3e10c
81185 #define A_MAC_MTIP_PCS_1G_1_DEV_ABILITY 0x3e110
81186 #define A_MAC_MTIP_PCS_1G_1_PARTNER_ABILITY 0x3e114
81187 #define A_MAC_MTIP_PCS_1G_1_AN_EXPANSION 0x3e118
81188 #define A_MAC_MTIP_PCS_1G_1_NP_TX 0x3e11c
81189 #define A_MAC_MTIP_PCS_1G_1_LP_NP_RX 0x3e120
81190 #define A_MAC_MTIP_PCS_1G_1_EXTENDED_STATUS 0x3e13c
81191 #define A_MAC_MTIP_PCS_1G_1_SCRATCH 0x3e140
81192 #define A_MAC_MTIP_PCS_1G_1_REV 0x3e144
81193 #define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_0 0x3e148
81194 #define A_MAC_MTIP_PCS_1G_1_LINK_TIMER_1 0x3e14c
81195 #define A_MAC_MTIP_PCS_1G_1_IF_MODE 0x3e150
81196 #define A_MAC_MTIP_PCS_1G_1_DEC_ERR_CNT 0x3e154
81197 #define A_MAC_MTIP_PCS_1G_1_VENDOR_CONTROL 0x3e158
81198 #define A_MAC_MTIP_PCS_1G_1_SD_BIT_SLIP 0x3e15c
81199 #define A_MAC_MTIP_PCS_1G_2_CONTROL 0x3e200
81200 #define A_MAC_MTIP_PCS_1G_2_STATUS 0x3e204
81201 #define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_0 0x3e208
81202 #define A_MAC_MTIP_PCS_1G_2_PHY_IDENTIFIER_1 0x3e20c
81203 #define A_MAC_MTIP_PCS_1G_2_DEV_ABILITY 0x3e210
81204 #define A_MAC_MTIP_PCS_1G_2_PARTNER_ABILITY 0x3e214
81205 #define A_MAC_MTIP_PCS_1G_2_AN_EXPANSION 0x3e218
81206 #define A_MAC_MTIP_PCS_1G_2_NP_TX 0x3e21c
81207 #define A_MAC_MTIP_PCS_1G_2_LP_NP_RX 0x3e220
81208 #define A_MAC_MTIP_PCS_1G_2_EXTENDED_STATUS 0x3e23c
81209 #define A_MAC_MTIP_PCS_1G_2_SCRATCH 0x3e240
81210 #define A_MAC_MTIP_PCS_1G_2_REV 0x3e244
81211 #define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_0 0x3e248
81212 #define A_MAC_MTIP_PCS_1G_2_LINK_TIMER_1 0x3e24c
81213 #define A_MAC_MTIP_PCS_1G_2_IF_MODE 0x3e250
81214 #define A_MAC_MTIP_PCS_1G_2_DEC_ERR_CNT 0x3e254
81215 #define A_MAC_MTIP_PCS_1G_2_VENDOR_CONTROL 0x3e258
81216 #define A_MAC_MTIP_PCS_1G_2_SD_BIT_SLIP 0x3e25c
81217 #define A_MAC_MTIP_PCS_1G_3_CONTROL 0x3e300
81218 #define A_MAC_MTIP_PCS_1G_3_STATUS 0x3e304
81219 #define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_0 0x3e308
81220 #define A_MAC_MTIP_PCS_1G_3_PHY_IDENTIFIER_1 0x3e30c
81221 #define A_MAC_MTIP_PCS_1G_3_DEV_ABILITY 0x3e310
81222 #define A_MAC_MTIP_PCS_1G_3_PARTNER_ABILITY 0x3e314
81223 #define A_MAC_MTIP_PCS_1G_3_AN_EXPANSION 0x3e318
81224 #define A_MAC_MTIP_PCS_1G_3_NP_TX 0x3e31c
81225 #define A_MAC_MTIP_PCS_1G_3_LP_NP_RX 0x3e320
81226 #define A_MAC_MTIP_PCS_1G_3_EXTENDED_STATUS 0x3e33c
81227 #define A_MAC_MTIP_PCS_1G_3_SCRATCH 0x3e340
81228 #define A_MAC_MTIP_PCS_1G_3_REV 0x3e344
81229 #define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_0 0x3e348
81230 #define A_MAC_MTIP_PCS_1G_3_LINK_TIMER_1 0x3e34c
81231 #define A_MAC_MTIP_PCS_1G_3_IF_MODE 0x3e350
81232 #define A_MAC_MTIP_PCS_1G_3_DEC_ERR_CNT 0x3e354
81233 #define A_MAC_MTIP_PCS_1G_3_VENDOR_CONTROL 0x3e358
81234 #define A_MAC_MTIP_PCS_1G_3_SD_BIT_SLIP 0x3e35c
81235 #define A_MAC_DPLL_CTRL_0 0x3f000
81249 #define S_CNTOFFSET    0
81250 #define M_CNTOFFSET    0xffffU
81254 #define A_MAC_DPLL_CTRL_1 0x3f004
81256 #define S_DELAYK    0
81257 #define M_DELAYK    0xffffffU
81261 #define A_MAC_DPLL_CTRL_2 0x3f008
81264 #define M_DIVFFB    0xffffU
81268 #define S_DIVFIN    0
81269 #define M_DIVFIN    0xffffU
81273 #define A_MAC_DPLL_CTRL_3 0x3f00c
81276 #define M_ISHIFT_HOLD    0xfU
81281 #define M_ISHIFT    0xfU
81286 #define M_INT_PRESET    0xfffU
81291 #define M_FMI    0xffU
81307 #define S_FDONLY    0
81311 #define A_MAC_DPLL_CTRL_4 0x3f010
81314 #define M_FKI    0x1fU
81318 #define S_FRAC_PRESET    0
81319 #define M_FRAC_PRESET    0xffffffU
81323 #define A_MAC_DPLL_CTRL_5 0x3f014
81326 #define M_PH_STEP_CNT_HOLD    0x1fU
81335 #define M_PH_STEP_CNT    0x1fU
81339 #define S_OTDLY    0
81340 #define M_OTDLY    0xffffU
81344 #define A_MAC_DPLL_CTRL_6 0x3f018
81347 #define M_TARGETCNT    0xffffU
81352 #define M_PKP    0x1fU
81356 #define S_PMP    0
81357 #define M_PMP    0xffU
81361 #define A_MAC_DPLL_CTRL_7 0x3f01c
81362 #define A_MAC_DPLL_STATUS_0 0x3f020
81364 #define S_FRAC    0
81365 #define M_FRAC    0xffffffU
81369 #define A_MAC_DPLL_STATUS_1 0x3f024
81371 #define S_FRAC_PD_OUT    0
81372 #define M_FRAC_PD_OUT    0xffffffU
81376 #define A_MAC_DPLL_STATUS_2 0x3f028
81379 #define M_INT    0xfffU
81383 #define S_INT_PD_OUT    0
81384 #define M_INT_PD_OUT    0xfffU
81388 #define A_MAC_FRAC_N_PLL_CTRL_0 0x3f02c
81391 #define M_FRAC_N_DSKEWCALCNT    0x7U
81400 #define M_T7_BYPASS    0xfU
81405 #define M_POSTDIV3A    0x7U
81410 #define M_POSTDIV3B    0x7U
81415 #define M_POSTDIV2A    0x7U
81420 #define M_POSTDIV2B    0x7U
81425 #define M_POSTDIV1A    0x7U
81430 #define M_POSTDIV1B    0x7U
81435 #define M_POSTDIV0A    0x7U
81439 #define S_POSTDIV0B    0
81440 #define M_POSTDIV0B    0x7U
81444 #define A_MAC_FRAC_N_PLL_CTRL_1 0x3f030
81447 #define M_FRAC_N_FRAC_N_FOUTEN    0xfU
81452 #define M_FRAC_N_DSKEWCALIN    0xfffU
81457 #define M_FRAC_N_REFDIV    0x3fU
81493 #define A_MAC_FRAC_N_PLL_STATUS_0 0x3f034
81499 #define S_DSKEWCALOUT    0
81500 #define M_DSKEWCALOUT    0xfffU
81504 #define A_MAC_MTIP_PCS_STATUS_0 0x3f100
81507 #define M_XLGMII7_TX_TSU    0x3U
81512 #define M_XLGMII6_TX_TSU    0x3U
81517 #define M_XLGMII5_TX_TSU    0x3U
81522 #define M_XLGMII4_TX_TSU    0x3U
81527 #define M_XLGMII3_TX_TSU    0x3U
81532 #define M_XLGMII2_TX_TSU    0x3U
81537 #define M_XLGMII1_TX_TSU    0x3U
81542 #define M_XLGMII0_TX_TSU    0x3U
81547 #define M_CGMII3_TX_TSU    0x3U
81552 #define M_CGMII2_TX_TSU    0x3U
81557 #define M_CGMII1_TX_TSU    0x3U
81561 #define S_CGMII0_TX_TSU    0
81562 #define M_CGMII0_TX_TSU    0x3U
81566 #define A_MAC_MTIP_PCS_STATUS_1 0x3f104
81569 #define M_CDMII1_RX_TSU    0x3U
81574 #define M_CDMII0_RX_TSU    0x3U
81579 #define M_XLGMII7_RX_TSU    0x3U
81584 #define M_XLGMII6_RX_TSU    0x3U
81589 #define M_XLGMII5_RX_TSU    0x3U
81594 #define M_XLGMII4_RX_TSU    0x3U
81599 #define M_XLGMII3_RX_TSU    0x3U
81604 #define M_XLGMII2_RX_TSU    0x3U
81609 #define M_XLGMII1_RX_TSU    0x3U
81614 #define M_XLGMII0_RX_TSU    0x3U
81619 #define M_CGMII3_RX_TSU    0x3U
81624 #define M_CGMII2_RX_TSU    0x3U
81629 #define M_CGMII1_RX_TSU    0x3U
81633 #define S_CGMII0_RX_TSU    0
81634 #define M_CGMII0_RX_TSU    0x3U
81638 #define A_MAC_MTIP_PCS_STATUS_2 0x3f108
81640 #define S_SD_BIT_SLIP_0    0
81641 #define M_SD_BIT_SLIP_0    0x3fffffffU
81645 #define A_MAC_MTIP_PCS_STATUS_3 0x3f10c
81647 #define S_SD_BIT_SLIP_1    0
81648 #define M_SD_BIT_SLIP_1    0x3ffffU
81652 #define A_MAC_MTIP_PCS_STATUS_4 0x3f110
81654 #define S_TSU_RX_SD    0
81655 #define M_TSU_RX_SD    0xffffU
81659 #define A_MAC_MTIP_PCS_STATUS_5 0x3f114
81661 #define S_RSFEC_XSTATS_STRB    0
81662 #define M_RSFEC_XSTATS_STRB    0xffffffU
81666 #define A_MAC_MTIP_PCS_STATUS_6 0x3f118
81667 #define A_MAC_MTIP_PCS_STATUS_7 0x3f11c
81668 #define A_MAC_MTIP_MAC_10G_100G_STATUS_0 0x3f120
81671 #define M_TSV_XON_STB_2    0xffU
81676 #define M_TSV_XOFF_STB_2    0xffU
81681 #define M_RSV_XON_STB_2    0xffU
81685 #define S_RSV_XOFF_STB_2    0
81686 #define M_RSV_XOFF_STB_2    0xffU
81690 #define A_MAC_MTIP_MAC_10G_100G_STATUS_1 0x3f124
81693 #define M_TSV_XON_STB_3    0xffU
81698 #define M_TSV_XOFF_STB_3    0xffU
81703 #define M_RSV_XON_STB_3    0xffU
81707 #define S_RSV_XOFF_STB_3    0
81708 #define M_RSV_XOFF_STB_3    0xffU
81712 #define A_MAC_MTIP_MAC_10G_100G_STATUS_2 0x3f128
81715 #define M_TSV_XON_STB_4    0xffU
81720 #define M_TSV_XOFF_STB_4    0xffU
81725 #define M_RSV_XON_STB_4    0xffU
81729 #define S_RSV_XOFF_STB_4    0
81730 #define M_RSV_XOFF_STB_4    0xffU
81734 #define A_MAC_MTIP_MAC_10G_100G_STATUS_3 0x3f12c
81737 #define M_TSV_XON_STB_5    0xffU
81742 #define M_TSV_XOFF_STB_5    0xffU
81747 #define M_RSV_XON_STB_5    0xffU
81751 #define S_RSV_XOFF_STB_5    0
81752 #define M_RSV_XOFF_STB_5    0xffU
81756 #define A_MAC_MTIP_MAC_10G_100G_STATUS_4 0x3f130
81834 #define S_TS_SFD_ENA_2    0
81838 #define A_MAC_STS_CONFIG 0x3f200
81852 #define S_DEBOUNCE_CNT    0
81853 #define M_DEBOUNCE_CNT    0xfffffffU
81857 #define A_MAC_STS_COUNTER 0x3f204
81858 #define A_MAC_STS_COUNT_1 0x3f208
81859 #define A_MAC_STS_COUNT_2 0x3f20c
81860 #define A_MAC_STS_N_PPS_COUNT_HI 0x3f210
81861 #define A_MAC_STS_N_PPS_COUNT_LO 0x3f214
81862 #define A_MAC_STS_N_PPS_COUNTER 0x3f218
81863 #define A_MAC_BGR_PQ0_FIRMWARE_COMMON_0 0x4030
81865 #define S_MAC_BGR_BGR_REG_APB_SEL    0
81869 #define A_MAC_BGR_TOP_DIG_CTRL1_REG_LSB 0x4430
81880 #define M_MAC_BGR_BGR_TEST_CLK_DIV    0x7U
81889 #define M_MAC_BGR_BGR_TEST_CLK_BGRSEL    0x3U
81893 #define S_MAC_BGR_BGR_TEST_CLK_SEL    0
81894 #define M_MAC_BGR_BGR_TEST_CLK_SEL    0x1fU
81898 #define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_0 0x6000
81900 #define S_MAC_BGR_BGR_REG_PRG_EN    0
81904 #define A_MAC_BGR_PQ0_FIRMWARE_SEQ0_1 0x6020
81906 #define S_MAC_BGR_BGR_REG_GPO    0
81910 #define A_MAC_BGR_MGMT_SPINE_MACRO_PMA_0 0x40000
81912 #define S_MAC_BGR_CUREFCLKSEL1    0
81913 #define M_MAC_BGR_CUREFCLKSEL1    0x3U
81917 #define A_MAC_BGR_REFCLK_CONTROL_1 0x40004
81919 #define S_MAC_BGR_IM_CUREFCLKLR_EN    0
81923 #define A_MAC_BGR_REFCLK_CONTROL_2 0x40080
81925 #define S_MAC_BGR_IM_REF_EN    0
81929 #define A_MAC_PLL0_PLL_TOP_CUPLL_LOCK 0x4438
81939 #define S_MAC_PLL0_PLL0_LOCK_STATUS    0
81943 #define A_MAC_PLL0_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
81945 #define S_MAC_PLL0_PLL_PRG_EN    0
81946 #define M_MAC_PLL0_PLL_PRG_EN    0xfU
81950 #define A_MAC_PLL0_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
81952 #define S_MAC_PLL0_PMA_MACRO_SELECT    0
81953 #define M_MAC_PLL0_PMA_MACRO_SELECT    0x3ffU
81957 #define A_MAC_PLL1_PLL_TOP_CUPLL_LOCK 0x4438
81967 #define S_MAC_PLL1_PLL0_LOCK_STATUS    0
81971 #define A_MAC_PLL1_PLL_PQ0_FIRMWARE_SEQ0_1 0x6020
81973 #define S_MAC_PLL1_PLL_PRG_EN    0
81974 #define M_MAC_PLL1_PLL_PRG_EN    0xfU
81978 #define A_MAC_PLL1_PLL_CMUTOP_KV16_MGMT_PLL_MACRO_SELECT_0 0x7fc00
81980 #define S_MAC_PLL1_PMA_MACRO_SELECT    0
81981 #define M_MAC_PLL1_PMA_MACRO_SELECT    0x3ffU
81986 #define CRYPTO_0_BASE_ADDR 0x44000
81988 #define A_TLS_TX_CH_CONFIG 0x44000
81991 #define M_SMALL_LEN_THRESH    0xffffU
81996 #define M_CIPH0_CTL_SEL    0x7U
82001 #define M_CIPHN_CTL_SEL    0x7U
82006 #define M_MAC_CTL_SEL    0x7U
82030 #define S_MAC_DP_SEL    0
82034 #define A_TLS_TX_CH_PERR_INJECT 0x44004
82035 #define A_TLS_TX_CH_INT_ENABLE 0x44008
82049 #define A_TLS_TX_CH_INT_CAUSE 0x4400c
82055 #define A_TLS_TX_CH_PERR_ENABLE 0x44010
82056 #define A_TLS_TX_CH_DEBUG_FLAGS 0x44014
82057 #define A_TLS_TX_CH_HMACCTRL_CFG 0x44020
82058 #define A_TLS_TX_CH_ERR_RSP_HDR 0x44024
82059 #define A_TLS_TX_CH_HANG_TIMEOUT 0x44028
82061 #define S_T7_TIMEOUT    0
82062 #define M_T7_TIMEOUT    0xffU
82066 #define A_TLS_TX_CH_DBG_STEP_CTRL 0x44030
82072 #define S_DBG_STEP_EN    0
82076 #define A_TLS_TX_DBG_SELL_DATA 0x44714
82077 #define A_TLS_TX_DBG_SELH_DATA 0x44718
82078 #define A_TLS_TX_DBG_SEL_CTRL 0x44730
82079 #define A_TLS_TX_GLOBAL_CONFIG 0x447c0
82089 #define S_IPSEC_IDX_CTL    0
82093 #define A_TLS_TX_CGEN 0x447f0
82095 #define S_CHCGEN    0
82096 #define M_CHCGEN    0x3fU
82100 #define A_TLS_TX_IND_ADDR 0x447f8
82102 #define S_T7_3_ADDR    0
82103 #define M_T7_3_ADDR    0xfffU
82107 #define A_TLS_TX_IND_DATA 0x447fc
82108 #define A_TLS_TX_CH_IND_ING_BYTE_CNT_LO 0x0
82109 #define A_TLS_TX_CH_IND_ING_BYTE_CNT_HI 0x1
82110 #define A_TLS_TX_CH_IND_ING_PKT_CNT 0x2
82111 #define A_TLS_TX_CH_IND_DISPATCH_PKT_CNT 0x4
82112 #define A_TLS_TX_CH_IND_ERROR_CNTS0 0x5
82113 #define A_TLS_TX_CH_IND_DEC_ERROR_CNTS 0x7
82114 #define A_TLS_TX_CH_IND_DBG_SPP_CFG 0x1f
82156 #define S_DIS_OFF_ERR    0
82160 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID0 0x20
82161 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID1 0x21
82162 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID2 0x22
82163 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID3 0x23
82164 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID4 0x24
82165 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID5 0x25
82166 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID6 0x26
82167 #define A_TLS_TX_CH_IND_DBG_SPP_PKTID7 0x27
82168 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W0 0x28
82169 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W1 0x29
82170 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W2 0x2a
82171 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_CPL_W3 0x2b
82172 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W0 0x2c
82173 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W1 0x2d
82174 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W2 0x2e
82175 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_SMD_W3 0x2f
82176 #define A_TLS_TX_CH_IND_DBG_SPP_SPR_ERR 0x30
82177 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_BP 0x31
82178 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_M 0x32
82179 #define A_TLS_TX_CH_IND_DBG_SPP_SFO_CTL_L 0x33
82180 #define A_TLS_TX_CH_IND_DBG_PKT_STAT 0x3f
82183 #define CRYPTO_1_BASE_ADDR 0x45000
82186 #define CRYPTO_KEY_BASE_ADDR 0x46000
82188 #define A_CRYPTO_KEY_CONFIG 0x46000
82191 #define M_ESNWIN    0x7U
82195 #define S_INGKEY96    0
82199 #define A_CRYPTO_KEY_RST 0x46004
82205 #define S_CORE0RST    0
82209 #define A_CRYPTO_KEY_INT_ENABLE 0x46008
82295 #define S_EGR_SEQ_WRAP_LP    0
82299 #define A_CRYPTO_KEY_INT_CAUSE 0x4600c
82300 #define A_CRYPTO_KEY_PERR_ENABLE 0x46010
82301 #define A_CRYPTO_KEY_EGR_SEQ_WRAP_LP_KEY_ID 0x46018
82307 #define S_KEY_ID    0
82308 #define M_KEY_ID    0x7fffffffU
82312 #define A_CRYPTO_KEY_EGR_SEQ_WRAP_HP_KEY_ID 0x4601c
82313 #define A_CRYPTO_KEY_TCAM_DATA0 0x46020
82314 #define A_CRYPTO_KEY_TCAM_DATA1 0x46024
82315 #define A_CRYPTO_KEY_TCAM_DATA2 0x46028
82316 #define A_CRYPTO_KEY_TCAM_DATA3 0x4602c
82317 #define A_CRYPTO_KEY_TCAM_CTL 0x46030
82344 #define M_CMDTYPE    0x3U
82348 #define S_TCAMINDEX    0
82349 #define M_TCAMINDEX    0x3fffU
82353 #define A_CRYPTO_KEY_TCAM_CONFIG 0x46034
82367 #define S_T7_TCAMDEEPSLEEP    0
82371 #define A_CRYPTO_KEY_TX_CMM_CONFIG 0x46040
82372 #define A_CRYPTO_KEY_TX_TNL_BASE 0x46044
82373 #define A_CRYPTO_KEY_TX_TRN_BASE 0x46048
82374 #define A_CRYPTO_KEY_TX_MAX_KEYS 0x4604c
82377 #define M_TNL_MAX    0xffffU
82381 #define S_TRN_MAX    0
82382 #define M_TRN_MAX    0xffffU
82386 #define A_CRYPTO_KEY_TX_SEQ_STAT 0x46050
82393 #define M_SEQHI    0xfU
82397 #define S_KEYID    0
82398 #define M_KEYID    0xfffffU
82402 #define A_CRYPTO_KEY_RX_CMM_CONFIG 0x46060
82403 #define A_CRYPTO_KEY_RX_BASE 0x46064
82404 #define A_CRYPTO_KEY_RX_MAX_KEYS 0x46068
82406 #define S_MAXKEYS    0
82407 #define M_MAXKEYS    0xffffU
82411 #define A_CRYPTO_KEY_CRYPTO_REVISION 0x4606c
82412 #define A_CRYPTO_KEY_RX_SEQ_STAT 0x46070
82413 #define A_CRYPTO_KEY_TCAM_BIST_CTRL 0x46074
82414 #define A_CRYPTO_KEY_TCAM_BIST_CB_PASS 0x46078
82415 #define A_CRYPTO_KEY_TCAM_BIST_CB_BUSY 0x4607c
82416 #define A_CRYPTO_KEY_DBG_SEL_CTRL 0x46080
82423 #define M_T7_1_SELH    0xffU
82427 #define S_T7_1_SELL    0
82428 #define M_T7_1_SELL    0xffU
82432 #define A_CRYPTO_KEY_DBG_SELL_DATA 0x46084
82433 #define A_CRYPTO_KEY_DBG_SELH_DATA 0x46088
82436 #define ARM_BASE_ADDR 0x47000
82438 #define A_ARM_CPU_POR_RST 0x47000
82452 #define S_CPUPORRSTN0    0
82456 #define A_ARM_CPU_CORE_RST 0x47004
82470 #define S_CPUCORERSTN0    0
82474 #define A_ARM_CPU_WARM_RST_REQ 0x47008
82488 #define S_CPUWARMRSTREQ0    0
82492 #define A_ARM_CPU_L2_RST 0x4700c
82494 #define S_CPUL2RSTN    0
82498 #define A_ARM_CPU_L2_RST_DIS 0x47010
82500 #define S_CPUL2RSTDISABLE    0
82504 #define A_ARM_CPU_PRESET_DBG 0x47014
82506 #define S_CPUPRESETDBGN    0
82510 #define A_ARM_PL_DMA_AW_OFFSET 0x47018
82512 #define S_PL_DMA_AW_OFFSET    0
82513 #define M_PL_DMA_AW_OFFSET    0x3fffffffU
82517 #define A_ARM_PL_DMA_AR_OFFSET 0x4701c
82519 #define S_PL_DMA_AR_OFFSET    0
82520 #define M_PL_DMA_AR_OFFSET    0x3fffffffU
82524 #define A_ARM_CPU_RESET_VECTOR_BASE_ADDR0 0x47020
82525 #define A_ARM_CPU_RESET_VECTOR_BASE_ADDR1 0x47024
82527 #define S_CPURESETVECBA1    0
82528 #define M_CPURESETVECBA1    0x3ffU
82532 #define A_ARM_CPU_PMU_EVENT 0x47028
82534 #define S_CPUPMUEVENT    0
82535 #define M_CPUPMUEVENT    0x1ffffffU
82539 #define A_ARM_DMA_RST 0x4702c
82541 #define S_DMA_PL_RST_N    0
82545 #define A_ARM_PLM_RID_CFG 0x4703c
82546 #define A_ARM_PLM_EROM_CFG 0x47040
82547 #define A_ARM_PL_ARM_HDR_CFG 0x4704c
82548 #define A_ARM_RC_INT_STATUS 0x4705c
82550 #define S_RC_INT_STATUS_REG    0
82551 #define M_RC_INT_STATUS_REG    0x3fU
82555 #define A_ARM_CPU_DBG_PWR_UP_REQ 0x47060
82569 #define S_CPUDBGPWRUPREQ0    0
82573 #define A_ARM_CPU_STANDBY_WFE_WFI 0x47064
82607 #define S_CPUSTANDBYWFE0    0
82611 #define A_ARM_CPU_SMPEN 0x47068
82625 #define S_CPUSMPEN0    0
82629 #define A_ARM_CPU_QACTIVE 0x4706c
82643 #define S_CPUQACTIVE0    0
82647 #define A_ARM_CPU_QREQ 0x47070
82669 #define S_CPUQREQ0N    0
82673 #define A_ARM_CPU_QREQ_STATUS 0x47074
82715 #define S_CPUQACCEPT0N    0
82719 #define A_ARM_CPU_DBG_EN 0x47078
82833 #define S_CPUDBGEN0    0
82837 #define A_ARM_CPU_DBG_ACK 0x4707c
82883 #define S_CPUDBGACK0    0
82887 #define A_ARM_CPU_PMU_SNAPSHOT_REQ 0x47080
82901 #define S_CPUPMUSNAPSHOTREQ0    0
82905 #define A_ARM_CPU_PMU_SNAPSHOT_ACK 0x47084
82919 #define S_CPUPMUSNAPSHOTACK0    0
82923 #define A_ARM_EMMC_CTRL 0x47088
82926 #define M_EMMC_DATA_P2    0xffU
82931 #define M_EMMC_DATA_P1    0xffU
82952 #define M_EMMC_GP_IN_P2    0x3U
82957 #define M_EMMC_GP_IN_P1    0x3U
82961 #define S_EMMC_CLK_SEL    0
82962 #define M_EMMC_CLK_SEL    0xffU
82966 #define A_ARM_CPU_CFG_END_VINI_TE 0x4708c
83060 #define S_CPUCFGEND0    0
83064 #define A_ARM_CPU_CP15_SDISABLE 0x47090
83078 #define S_CPUCP15SDISABLE0    0
83082 #define A_ARM_CPU_CLUSTER_ID_AFF 0x47094
83085 #define M_CPUCLUSTERIDAFF2    0xffU
83089 #define S_CPUCLUSTERIDAFF1    0
83090 #define M_CPUCLUSTERIDAFF1    0xffU
83094 #define A_ARM_CPU_CLK_CFG 0x47098
83100 #define S_CPUACLKENM    0
83104 #define A_ARM_NVME_DB_EMU_INT_CAUSE 0x4709c
83118 #define S_INVALID_AXI_ADDR_CFG    0
83122 #define A_ARM_CS_RST 0x470c0
83160 #define S_CPU_DBGEN    0
83164 #define A_ARM_CS_ADDRL 0x470c4
83165 #define A_ARM_CS_ADDRH 0x470c8
83166 #define A_ARM_CS_DFT_CONTROL 0x470cc
83169 #define M_DFTMBISTADDR    0x7ffU
83185 #define S_DFTSE    0
83189 #define A_ARM_CS_DFT_IN 0x470d0
83190 #define A_ARM_CS_DFT_OUT 0x470d4
83191 #define A_ARM_CPU_EVENT_I 0x47100
83193 #define S_CPUEVENTI    0
83197 #define A_ARM_CPU_EVENT_O 0x47104
83199 #define S_CPUEVENTO    0
83203 #define A_ARM_CPU_CLR_EXMON_REQ 0x47108
83205 #define S_CPUCLREXMONREQ    0
83209 #define A_ARM_CPU_CLR_EXMON_ACK 0x4710c
83211 #define S_CPUCLREXMONACK    0
83215 #define A_ARM_UART_MSTR_RXD 0x47110
83216 #define A_ARM_UART_MSTR_RXC 0x47114
83218 #define S_UART_MSTR_RXC    0
83222 #define A_ARM_UART_MSTR_TXD 0x47118
83223 #define A_ARM_UART_MSTR_TXC 0x4711c
83229 #define S_UART_MSTC_TXC    0
83233 #define A_ARM_UART_SLV_SEL 0x47120
83235 #define S_UART_SLV_SEL    0
83239 #define A_ARM_CPU_PERIPH_BASE 0x47124
83240 #define A_ARM_PERR_INT_ENB2 0x47128
83241 #define A_ARM_PERR_ENABLE2 0x4712c
83242 #define A_ARM_UART_CONFIG 0x47130
83243 #define A_ARM_UART_STAT 0x47134
83246 #define M_RSV1    0x3ffffffU
83270 #define S_CTL_TXRDY    0
83274 #define A_ARM_UART_TX_DATA 0x47138
83276 #define S_TX_DATA    0
83277 #define M_TX_DATA    0xffU
83281 #define A_ARM_UART_RX_DATA 0x4713c
83283 #define S_RX_DATA    0
83284 #define M_RX_DATA    0xffU
83288 #define A_ARM_UART_DBG0 0x47140
83289 #define A_ARM_UART_DBG1 0x47144
83290 #define A_ARM_UART_DBG2 0x47148
83291 #define A_ARM_UART_DBG3 0x4714c
83292 #define A_ARM_ARM_CPU_PC0 0x47150
83293 #define A_ARM_ARM_CPU_PC1 0x47154
83294 #define A_ARM_ARM_UART_INT_CAUSE 0x47158
83300 #define S_TX_FIFO_EMPTY    0
83304 #define A_ARM_ARM_UART_INT_EN 0x4715c
83310 #define S_TX_FIFO_INT_EMPTY    0
83314 #define A_ARM_ARM_UART_GPIO_SEL 0x47160
83317 #define M_PC_SEL    0x7U
83321 #define S_UART_GPIO_SEL    0
83325 #define A_ARM_ARM_SCRATCH_PAD0 0x47164
83326 #define A_ARM_ARM_SCRATCH_PAD1 0x47168
83327 #define A_ARM_ARM_SCRATCH_PAD2 0x4716c
83328 #define A_ARM_PERR_INT_CAUSE0 0x47170
83343 #define M_ARM_DB_SRAM_PERR    0x3U
83364 #define M_RC_SRAM_PERR    0x3U
83448 #define S_APB2PL_RSPDATAPERR    0
83452 #define A_ARM_PERR_INT_ENB0 0x47174
83453 #define A_ARM_SCRATCH_PAD3 0x47178
83460 #define M_TIMER_SEL    0x7U
83465 #define M_TIMER    0xffffffU
83469 #define S_T7_1_INT    0
83470 #define M_T7_1_INT    0x3U
83474 #define A_ARM_PERR_INT_CAUSE2 0x4717c
83500 #define A_ARM_MA2AXI_AW_ATTR 0x47180
83507 #define M_AWCACHER1    0xfU
83512 #define M_AWPROTR1    0xfU
83517 #define M_AWSNOOPR1    0x7U
83522 #define M_AWDOMAINR1    0x3U
83531 #define M_AWCACHER0    0xfU
83536 #define M_AWPROTR0    0xfU
83541 #define M_AWSNOOPR0    0x7U
83545 #define S_AWDOMAINR0    0
83546 #define M_AWDOMAINR0    0x3U
83550 #define A_ARM_MA2AXI_AR_ATTR 0x47184
83557 #define M_ARCACHER1    0xfU
83562 #define M_ARPROTR1    0xfU
83567 #define M_ARSNOOPR1    0x7U
83572 #define M_ARDOMAINR1    0x3U
83581 #define M_ARCACHER0    0xfU
83586 #define M_ARPROTR0    0xfU
83591 #define M_ARSNOOPR0    0x7U
83595 #define S_ARDOMAINR0    0
83596 #define M_ARDOMAINR0    0x3U
83600 #define A_ARM_MA2AXI_SNOOP_RGN 0x47188
83603 #define M_SNOOP_END    0xffffU
83607 #define S_SNOOP_START    0
83608 #define M_SNOOP_START    0xffffU
83612 #define A_ARM_PERIPHERAL_INT_CAUSE 0x4718c
83634 #define S_USB_DMA_INT    0
83638 #define A_ARM_SCRATCH_PAD4 0x47190
83641 #define M_PAD4    0x1ffffU
83645 #define S_ARM_DB_CNT    0
83646 #define M_ARM_DB_CNT    0x7fffU
83650 #define A_ARM_SCRATCH_PAD5 0x47194
83651 #define A_ARM_SCRATCH_PAD6 0x47198
83652 #define A_ARM_SCRATCH_PAD7 0x4719c
83653 #define A_ARM_NVME_DB_EMU_INDEX 0x471a0
83654 #define A_ARM_NVME_DB_EMU_REGION_CTL 0x471a4
83672 #define S_RGN0_INT_EN    0
83676 #define A_ARM_NVME_DB_EMU_DEVICE_CTL 0x471a8
83679 #define M_DEVICE_SIZE    0xfU
83684 #define M_RGN1_SIZE    0xfU
83688 #define S_RGN0_SIZE    0
83689 #define M_RGN0_SIZE    0xfU
83693 #define A_ARM_NVME_DB_EMU_WINDOW_START_ADDR 0x471b0
83695 #define S_T7_4_ADDR    0
83696 #define M_T7_4_ADDR    0xfffffffU
83700 #define A_ARM_NVME_DB_EMU_WINDOW_END_ADDR 0x471b4
83701 #define A_ARM_NVME_DB_EMU_QBASE_ADDR 0x471b8
83702 #define A_ARM_NVME_DB_EMU_QUEUE_CID 0x471bc
83704 #define S_T7_CID    0
83705 #define M_T7_CID    0x1ffffU
83709 #define A_ARM_NVME_DB_EMU_QUEUE_CTL 0x471c0
83716 #define M_THRESHOLD    0x1ffffU
83720 #define S_T7_1_SIZE    0
83721 #define M_T7_1_SIZE    0x3ffU
83725 #define A_ARM_NVME_DB_EMU_MSIX_ADDR_L 0x471c4
83726 #define A_ARM_NVME_DB_EMU_MSIX_ADDR_H 0x471c8
83727 #define A_ARM_NVME_DB_EMU_MSIX_OFFSET 0x471cc
83728 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_L 0x471d0
83729 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_ADDR_H 0x471d4
83730 #define A_ARM_NVME_DB_EMU_QUEUE_MSIX_OFFSET 0x471d8
83731 #define A_ARM_CERR_INT_CAUSE0 0x471dc
83778 #define M_RC_SRAM_CERR    0x3U
83803 #define M_ARM_DB_SRAM_CERR    0x3U
83819 #define A_ARM_NVME_DB_EMU_QUEUE_CTL_2 0x471e0
83821 #define S_INTERRUPT_CLEAR    0
83825 #define A_ARM_PERIPHERAL_INT_ENB 0x471e4
83826 #define A_ARM_CERR_INT_ENB0 0x471e8
83827 #define A_ARM_CPU_DBG_ROM_ADDR0 0x47200
83829 #define S_CPUDBGROMADDR0    0
83830 #define M_CPUDBGROMADDR0    0xfffffU
83834 #define A_ARM_CPU_DBG_ROM_ADDR1 0x47204
83836 #define S_CPUDBGROMADDR1    0
83837 #define M_CPUDBGROMADDR1    0x3ffU
83841 #define A_ARM_CPU_DBG_ROM_ADDR_VALID 0x47208
83843 #define S_CPUDBGROMADDRVALID    0
83847 #define A_ARM_PERR_ENABLE0 0x4720c
83848 #define A_ARM_SRAM2_WRITE_DATA3 0x47210
83849 #define A_ARM_SRAM2_READ_DATA3 0x4721c
83850 #define A_ARM_CPU_DFT_CFG 0x47220
83896 #define S_CPUDFTCLKBYPASS    0
83900 #define A_ARM_APB_CFG 0x47224
83902 #define S_APB_CFG    0
83903 #define M_APB_CFG    0x3ffffU
83907 #define A_ARM_EMMC_BUFS 0x47228
83910 #define M_EMMC_BUFS_OEN    0x3U
83914 #define S_EMMC_BUFS_I    0
83915 #define M_EMMC_BUFS_I    0x3U
83919 #define A_ARM_SWP_EN 0x4722c
83920 #define A_ARM_ADB_PWR_DWN_REQ_N 0x47230
83922 #define S_ADBPWRDWNREQN    0
83926 #define A_ARM_GIC_USER 0x47238
83928 #define S_CPU_GIC_USER    0
83929 #define M_CPU_GIC_USER    0x7fU
83933 #define A_ARM_DBPROC_SRAM_TH_ADDR 0x47240
83935 #define S_DBPROC_TH_ADDR    0
83936 #define M_DBPROC_TH_ADDR    0x1ffU
83940 #define A_ARM_DBPROC_SRAM_TH_READ_DATA0 0x47244
83941 #define A_ARM_DBPROC_SRAM_TH_READ_DATA1 0x47248
83942 #define A_ARM_DBPROC_SRAM_TH_READ_DATA2 0x4724c
83943 #define A_ARM_DBPROC_SRAM_TH_READ_DATA3 0x47250
83944 #define A_ARM_DBPROC_SRAM_TH_WR_DATA0 0x47254
83945 #define A_ARM_DBPROC_SRAM_TH_WR_DATA1 0x47258
83946 #define A_ARM_DBPROC_SRAM_TH_WR_DATA2 0x4725c
83947 #define A_ARM_DBPROC_SRAM_TH_WR_DATA3 0x47260
83948 #define A_ARM_SWP_EN_2 0x47264
83950 #define S_SWP_EN_2    0
83951 #define M_SWP_EN_2    0x3U
83955 #define A_ARM_GIC_ERR 0x47268
83961 #define S_AXIM_ERR    0
83965 #define A_ARM_CPU_STAT 0x4726c
84015 #define S_PWRQACCEPTNS_ADB    0
84019 #define A_ARM_DEBUG_INT_WRITE_DATA 0x47270
84021 #define S_DEBUG_INT_WRITE_DATA    0
84022 #define M_DEBUG_INT_WRITE_DATA    0xfffU
84026 #define A_ARM_DEBUG_INT_STAT 0x47274
84028 #define S_DEBUG_INT_STATUS_REG    0
84029 #define M_DEBUG_INT_STATUS_REG    0xfffU
84033 #define A_ARM_DEBUG_STAT 0x47278
84035 #define S_ARM_DEBUG_STAT    0
84036 #define M_ARM_DEBUG_STAT    0x3fffU
84040 #define A_ARM_SIZE_STAT 0x4727c
84042 #define S_ARM_SIZE_STAT    0
84043 #define M_ARM_SIZE_STAT    0x3fffffffU
84047 #define A_ARM_CCI_CFG0 0x47280
84050 #define M_CCIBROADCASTCACHEMAINT    0x7U
84055 #define M_CCISTRIPINGGRANULE    0x7U
84059 #define S_CCIPERIPHBASE    0
84060 #define M_CCIPERIPHBASE    0x1ffffffU
84064 #define A_ARM_CCI_CFG1 0x47284
84079 #define M_CCIACCHANNELN    0x1fU
84084 #define M_CCIQOSOVERRIDE    0x1fU
84089 #define M_CCIBUFFERABLEOVERRIDE    0x7U
84093 #define S_CCIBARRIERTERMINATE    0
84094 #define M_CCIBARRIERTERMINATE    0x7U
84098 #define A_ARM_CCI_CFG2 0x47288
84101 #define M_CCIADDRMAP15    0x3U
84106 #define M_CCIADDRMAP14    0x3U
84111 #define M_CCIADDRMAP13    0x3U
84116 #define M_CCIADDRMAP12    0x3U
84121 #define M_CCIADDRMAP11    0x3U
84126 #define M_CCIADDRMAP10    0x3U
84131 #define M_CCIADDRMAP9    0x3U
84136 #define M_CCIADDRMAP8    0x3U
84141 #define M_CCIADDRMAP7    0x3U
84146 #define M_CCIADDRMAP6    0x3U
84151 #define M_CCIADDRMAP5    0x3U
84156 #define M_CCIADDRMAP4    0x3U
84161 #define M_CCIADDRMAP3    0x3U
84166 #define M_CCIADDRMAP2    0x3U
84171 #define M_CCIADDRMAP1    0x3U
84175 #define S_CCIADDRMAP0    0
84176 #define M_CCIADDRMAP0    0x3U
84180 #define A_ARM_CCI_STATUS 0x4728c
84190 #define S_CCINEVNTCNTOVERFLOW    0
84191 #define M_CCINEVNTCNTOVERFLOW    0x1fU
84195 #define A_ARM_CCIM_CCI_QVN_MASTER_CFG 0x47290
84246 #define M_CCIQVNPREALLOCWM    0xfU
84251 #define M_CCIQVNPREALLOCRM    0xfU
84255 #define S_CCIQVNENABLEM    0
84259 #define A_ARM_CCIM_CCI_QVN_MASTER_STATUS 0x47294
84278 #define M_CCIVARQOSN3M    0xfU
84299 #define M_CCIVARQOSN2M    0xfU
84320 #define M_CCIVARQOSN1M    0xfU
84340 #define S_CCIVARQOSN0M    0
84341 #define M_CCIVARQOSN0M    0xfU
84345 #define A_ARM_CCIS_CCI_QVN_SLAVE_CFG 0x472d0
84347 #define S_CCIQVNVNETS    0
84348 #define M_CCIQVNVNETS    0x3U
84352 #define A_ARM_CCIS_CCI_QVN_SLAVE_STATUS 0x472d4
84355 #define M_CCIEVNTAWQOS    0xfU
84359 #define S_CCIEVNTARQOS    0
84360 #define M_CCIEVNTARQOS    0xfU
84364 #define A_ARM_CCI_EVNTBUS 0x47300
84365 #define A_ARM_CCI_RST_N 0x47318
84367 #define S_CCIRSTN    0
84371 #define A_ARM_CCI_CSYREQ 0x4731c
84373 #define S_CCICSYSREQ    0
84377 #define A_ARM_CCI_TR_DEBUGS0 0x47320
84380 #define M_CCIS0RCNT    0xffU
84385 #define M_CCIS0ARCNT    0xffU
84390 #define M_CCIS0WCNT    0xffU
84394 #define S_CCIS0AWCNT    0
84395 #define M_CCIS0AWCNT    0xffU
84399 #define A_ARM_CCI_TR_DEBUGS1 0x47324
84402 #define M_CCIS1RCNT    0xffU
84407 #define M_CCIS1ARCNT    0xffU
84412 #define M_CCIS1WCNT    0xffU
84416 #define S_CCIS1AWCNT    0
84417 #define M_CCIS1AWCNT    0xffU
84421 #define A_ARM_CCI_TR_DEBUGS2 0x47328
84424 #define M_CCIS2RCNT    0xffU
84429 #define M_CCIS2ARCNT    0xffU
84434 #define M_CCIS2WCNT    0xffU
84438 #define S_CCIS2AWCNT    0
84439 #define M_CCIS2AWCNT    0xffU
84443 #define A_ARM_CCI_TR_DEBUGS3 0x4732c
84446 #define M_CCIS3RCNT    0xffU
84451 #define M_CCIS3ARCNT    0xffU
84456 #define M_CCIS3WCNT    0xffU
84460 #define S_CCIS3AWCNT    0
84461 #define M_CCIS3AWCNT    0xffU
84465 #define A_ARM_CCI_TR_DEBUGS4 0x47330
84468 #define M_CCIS4RCNT    0xffU
84473 #define M_CCIS4ARCNT    0xffU
84478 #define M_CCIS4WCNT    0xffU
84482 #define S_CCIS4AWCNT    0
84483 #define M_CCIS4AWCNT    0xffU
84487 #define A_ARM_CCI_TR_DEBUGS34 0x47334
84490 #define M_CCIS4RSPCNT    0xffU
84495 #define M_CCIS4ACCNT    0xffU
84500 #define M_CCIS3RSPCNT    0xffU
84504 #define S_CCIS3ACCNT    0
84505 #define M_CCIS3ACCNT    0xffU
84509 #define A_ARM_CCI_TR_DEBUGM0 0x47338
84512 #define M_CCIM0RCNT    0xffU
84517 #define M_CCIM0ARCNT    0xffU
84522 #define M_CCIM0WCNT    0xffU
84526 #define S_CCIM0AWCNT    0
84527 #define M_CCIM0AWCNT    0xffU
84531 #define A_ARM_CCI_TR_DEBUGM1 0x4733c
84534 #define M_CCIM1RCNT    0xffU
84539 #define M_CCIM1ARCNT    0xffU
84544 #define M_CCIM1WCNT    0xffU
84548 #define S_CCIM1AWCNT    0
84549 #define M_CCIM1AWCNT    0xffU
84553 #define A_ARM_CCI_TR_DEBUGM2 0x47340
84556 #define M_CCIM2RCNT    0xffU
84561 #define M_CCIM2ARCNT    0xffU
84566 #define M_CCIM2WCNT    0xffU
84570 #define S_CCIM2AWCNT    0
84571 #define M_CCIM2AWCNT    0xffU
84575 #define A_ARM_MA_TR_DEBUG 0x47344
84578 #define M_MA1_RD_CNT    0xffU
84583 #define M_MA1_WR_CNT    0xffU
84588 #define M_MA0_RD_CNT    0xffU
84592 #define S_MA0_WR_CNT    0
84593 #define M_MA0_WR_CNT    0xffU
84597 #define A_ARM_GP_INT 0x47348
84599 #define S_GP_INT    0
84600 #define M_GP_INT    0xffU
84604 #define A_ARM_DMA_CFG0 0x47350
84605 #define A_ARM_DMA_CFG1 0x47354
84608 #define M_DMABOOTPERIPHNS    0x3ffU
84613 #define M_DMABOOTIRQNS    0x3ffU
84621 #define S_DMABOOTFROMPC    0
84625 #define A_ARM_ARM_CFG0 0x47380
84635 #define S_PCIEBYPASS    0
84639 #define A_ARM_ARM_CFG1 0x47384
84640 #define A_ARM_ARM_CFG2 0x47390
84641 #define A_ARM_PCIE_MA_ADDR_REGION0 0x47400
84643 #define S_ADDRREG0    0
84644 #define M_ADDRREG0    0xfffffffU
84648 #define A_ARM_PCIE_MA_ADDR_REGION1 0x47404
84650 #define S_ADDRREG1    0
84651 #define M_ADDRREG1    0xfffffffU
84655 #define A_ARM_PCIE_MA_ADDR_REGION2 0x47408
84657 #define S_ADDRREG2    0
84658 #define M_ADDRREG2    0xfffffffU
84662 #define A_ARM_PCIE_MA_ADDR_REGION3 0x4740c
84664 #define S_ADDRREG3    0
84665 #define M_ADDRREG3    0xfffffffU
84669 #define A_ARM_PCIE_MA_ADDR_REGION4 0x47410
84671 #define S_ADDRREG4    0
84672 #define M_ADDRREG4    0xfffffffU
84676 #define A_ARM_PCIE_MA_ADDR_REGION5 0x47414
84678 #define S_ADDRREG5    0
84679 #define M_ADDRREG5    0xfffffffU
84683 #define A_ARM_PCIE_MA_ADDR_REGION6 0x47418
84685 #define S_ADDRREG6    0
84686 #define M_ADDRREG6    0xfffffffU
84690 #define A_ARM_PCIE_MA_ADDR_REGION7 0x4741c
84692 #define S_ADDRREG7    0
84693 #define M_ADDRREG7    0xfffffffU
84697 #define A_ARM_INTERRUPT_GEN 0x47420
84699 #define S_INT_GEN    0
84700 #define M_INT_GEN    0x3U
84704 #define A_ARM_INTERRUPT_CLEAR 0x47424
84706 #define S_INT_CLEAR    0
84707 #define M_INT_CLEAR    0x3U
84711 #define A_ARM_DEBUG_STATUS_0 0x47428
84712 #define A_ARM_DBPROC_CONTROL 0x4742c
84714 #define S_NO_OF_INTERRUPTS    0
84715 #define M_NO_OF_INTERRUPTS    0x3U
84719 #define A_ARM_PERR_INT_CAUSE1 0x47430
84845 #define S_ITE_CACHE_PERR    0
84849 #define A_ARM_PERR_INT_ENB1 0x47434
84850 #define A_ARM_PERR_ENABLE1 0x47438
84851 #define A_ARM_DEBUG_STATUS_1 0x4743c
84852 #define A_ARM_PCIE_MA_ADDR_REGION_DST 0x47440
84854 #define S_ADDRREGDST    0
84855 #define M_ADDRREGDST    0x1ffU
84859 #define A_ARM_ERR_INT_CAUSE0 0x47444
84885 #define A_ARM_ERR_INT_ENB0 0x47448
84886 #define A_ARM_DEBUG_INDEX 0x47450
84887 #define A_ARM_DEBUG_DATA_HIGH 0x47454
84888 #define A_ARM_DEBUG_DATA_LOW 0x47458
84889 #define A_ARM_MSG_PCIE_MESSAGE2AXI_BA0 0x47500
84890 #define A_ARM_MSG_PCIE_MESSAGE2AXI_BA1 0x47504
84892 #define S_BASEADDRESS    0
84893 #define M_BASEADDRESS    0x3U
84897 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG0 0x47508
84900 #define M_WATERMARK    0x3ffU
84904 #define S_SIZEMAX    0
84905 #define M_SIZEMAX    0x3ffU
84909 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG1 0x4750c
84910 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG2 0x47510
84912 #define S_CPUREADADDRESS    0
84913 #define M_CPUREADADDRESS    0x3ffU
84917 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG3 0x47514
84919 #define S_CPUREADADDRESSVLD    0
84923 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG4 0x47518
84924 #define A_ARM_APB2MSI_INTERRUPT_0_STATUS 0x47600
84925 #define A_ARM_APB2MSI_INTERRUPT_1_STATUS 0x47604
84926 #define A_ARM_APB2MSI_INTERRUPT_2_STATUS 0x47608
84927 #define A_ARM_APB2MSI_INTERRUPT_3_STATUS 0x4760c
84928 #define A_ARM_APB2MSI_INTERRUPT_0_ENABLE 0x47610
84929 #define A_ARM_APB2MSI_INTERRUPT_1_ENABLE 0x47614
84930 #define A_ARM_APB2MSI_INTERRUPT_2_ENABLE 0x47618
84931 #define A_ARM_APB2MSI_INTERRUPT_3_ENABLE 0x4761c
84932 #define A_ARM_APB2MSI_INTERRUPT_PRIORITY_LEVEL 0x47620
84934 #define S_ARM_APB2MSI_INT_PRIORITY_LEVEL    0
84935 #define M_ARM_APB2MSI_INT_PRIORITY_LEVEL    0x7U
84939 #define A_ARM_APB2MSI_MEM_READ_ADDR 0x47624
84941 #define S_ARM_APB2MSI_MEM_READ_ADDR    0
84942 #define M_ARM_APB2MSI_MEM_READ_ADDR    0x7fU
84946 #define A_ARM_MSI_MEMORY_DATA 0x47628
84947 #define A_ARM_MSI_MEMORY_ADDR 0x4762c
84948 #define A_ARM_MSG_PCIE_MESSAGE2AXI_CFG5 0x47630
84950 #define S_CONFIGDONE    0
84954 #define A_ARM_AXI2MA_TIMERCNT 0x47640
84955 #define A_ARM_AXI2MA_TRTYPE 0x47644
84969 #define S_ARMMA2AXI0AWTRTYPE    0
84973 #define A_ARM_AXI2PCIE_VENDOR 0x47660
84976 #define M_T7_VENDORID    0xffffU
84980 #define S_OBFFCODE    0
84981 #define M_OBFFCODE    0xfU
84985 #define A_ARM_AXI2PCIE_VENMSGHDR_DW3 0x47664
84986 #define A_ARM_CLUSTER_SEL 0x47668
84988 #define S_ARM_CLUSTER_SEL    0
84992 #define A_ARM_PWRREQ_PERMIT_ADB 0x4766c
84998 #define S_PWRQREQNS_ADB    0
85002 #define A_ARM_CLK_REQ_ADB 0x47670
85004 #define S_CLKQREQNS_ADB    0
85008 #define A_ARM_WAKEUPM 0x47674
85018 #define S_WAKEUPM_I_ADB    0
85022 #define A_ARM_CC_APB_FILTERING 0x47678
85032 #define S_CC_APB_FILTERING    0
85033 #define M_CC_APB_FILTERING    0x3ffU
85037 #define A_ARM_DCU_EN0 0x4767c
85038 #define A_ARM_DCU_EN1 0x47680
85039 #define A_ARM_DCU_EN2 0x47684
85040 #define A_ARM_DCU_EN3 0x47688
85041 #define A_ARM_DCU_LOCK0 0x4768c
85042 #define A_ARM_DCU_LOCK1 0x47690
85043 #define A_ARM_DCU_LOCK2 0x47694
85044 #define A_ARM_DCU_LOCK3 0x47698
85045 #define A_ARM_GPPC 0x4769c
85064 #define M_CC_LOCK_BITS    0x1ffU
85073 #define M_CC_LCS    0x7U
85077 #define S_CC_GPPC    0
85078 #define M_CC_GPPC    0xffU
85082 #define A_ARM_EMMC 0x47700
85097 #define M_EMMC_UHS1_DRV_STH    0x3U
85106 #define M_EMMC_SD_VDD1_SEL    0x7U
85115 #define M_EMMC_CARD_CLK_FREQ_SEL    0x3ffU
85163 #define S_EMMC_FIFOINJDATAERR    0
85167 #define A_ARM_WAKEUPS 0x47704
85169 #define S_WAKEUPS_I_ADB    0
85173 #define A_ARM_CLKREQNM_ADB 0x47708
85175 #define S_CLKQREQNM_ADB    0
85179 #define A_ARM_ATOMICDATA0_0 0x4770c
85180 #define A_ARM_ATOMICDATA1_0 0x47710
85181 #define A_ARM_NVME_DB_EMU_INT_ENABLE 0x47740
85182 #define A_ARM_TCAM_WRITE_DATA 0x47744
85184 #define S_TCAM_WRITE_DATA    0
85185 #define M_TCAM_WRITE_DATA    0x3fffffffU
85189 #define A_ARM_TCAM_WRITE_ADDR 0x47748
85191 #define S_TCAM_WRITE_ADDR    0
85192 #define M_TCAM_WRITE_ADDR    0x1ffU
85196 #define A_ARM_TCAM_READ_ADDR 0x4774c
85198 #define S_TCAM_READ_ADDR    0
85199 #define M_TCAM_READ_ADDR    0x1ffU
85203 #define A_ARM_TCAM_CTL 0x47750
85229 #define S_TCAM_ENABLE    0
85233 #define A_ARM_TCAM_READ_DATA 0x4775c
85235 #define S_TCAM_READ_DATA    0
85236 #define M_TCAM_READ_DATA    0x3fffffffU
85240 #define A_ARM_SRAM1_WRITE_DATA 0x47760
85242 #define S_SRAM1_WRITE_DATA    0
85243 #define M_SRAM1_WRITE_DATA    0x7fffffU
85247 #define A_ARM_SRAM1_WRITE_ADDR 0x47764
85249 #define S_SRAM1_WRITE_ADDR    0
85250 #define M_SRAM1_WRITE_ADDR    0x1ffU
85254 #define A_ARM_SRAM1_READ_ADDR 0x47768
85256 #define S_SRAM1_READ_ADDR    0
85257 #define M_SRAM1_READ_ADDR    0x1ffU
85261 #define A_ARM_SRAM1_CTL 0x4776c
85267 #define S_SRAM1_ENABLE    0
85271 #define A_ARM_SRAM1_READ_DATA 0x47770
85273 #define S_SRAM1_READ_DATA    0
85274 #define M_SRAM1_READ_DATA    0x7fffffU
85278 #define A_ARM_SRAM2_WRITE_DATA0 0x47774
85279 #define A_ARM_SRAM2_WRITE_DATA1 0x47778
85280 #define A_ARM_SRAM2_WRITE_DATA2 0x4777c
85281 #define A_ARM_SRAM2_WRITE_ADDR 0x47780
85283 #define S_SRAM2_WRITE_ADDR    0
85284 #define M_SRAM2_WRITE_ADDR    0x1fffU
85288 #define A_ARM_SRAM2_READ_ADDR 0x47784
85290 #define S_SRAM2_READ_ADDR    0
85291 #define M_SRAM2_READ_ADDR    0x1fffU
85295 #define A_ARM_SRAM2_CTL 0x47788
85301 #define S_SRAM2_ENABLE    0
85305 #define A_ARM_SRAM2_READ_DATA0 0x4778c
85306 #define A_ARM_SRAM2_READ_DATA1 0x47790
85307 #define A_ARM_SRAM2_READ_DATA2 0x47794
85308 #define A_ARM_DBPROC_SRAM_CTL 0x47798
85310 #define S_DBPROC_RD_EN    0
85314 #define A_ARM_DBPROC_SRAM_READ_ADDR 0x4779c
85316 #define S_DBPROC_RD_ADDR    0
85317 #define M_DBPROC_RD_ADDR    0x1ffU
85321 #define A_ARM_DBPROC_SRAM_READ_DATA0 0x477a0
85322 #define A_ARM_DBPROC_SRAM_READ_DATA1 0x477a4
85323 #define A_ARM_DBPROC_SRAM_READ_DATA2 0x477a8
85324 #define A_ARM_DBPROC_SRAM_READ_DATA3 0x477ac
85325 #define A_ARM_ATOMICDATA0_1 0x477b0
85326 #define A_ARM_ATOMICDATA1_1 0x477b4
85327 #define A_ARM_SPIDEN 0x477b8
85329 #define S_SPIDEN    0
85333 #define A_ARM_RC_INT_WRITE_DATA 0x477bc
85335 #define S_RC_INT_STATUS_WRITE_DATA    0
85336 #define M_RC_INT_STATUS_WRITE_DATA    0x3fU
85340 #define A_ARM_DFT_MBI 0x477c4
85354 #define S_DFTCGEN    0
85358 #define A_ARM_DBPROC_SRAM_TH_CTL 0x477c8
85364 #define S_DBPROC_TH_RD_EN    0
85368 #define A_ARM_MBISTACK 0x477d4
85370 #define S_MBISTACK    0
85374 #define A_ARM_MBISTADDR 0x477d8
85376 #define S_MBISTADDR    0
85377 #define M_MBISTADDR    0xfffU
85381 #define A_ARM_MBISTREADEN 0x477dc
85383 #define S_MBISTREADEN    0
85387 #define A_ARM_MBISTWRITEEN 0x477e0
85389 #define S_MBISTWRITEEN    0
85393 #define A_ARM_MBISTARRAY 0x477e4
85395 #define S_MBISTARRAY    0
85396 #define M_MBISTARRAY    0x3U
85400 #define A_ARM_MBISTCFG 0x477e8
85402 #define S_MBISTCFG    0
85406 #define A_ARM_MBISTINDATA0 0x477ec
85407 #define A_ARM_MBISTINDATA1 0x477f0
85408 #define A_ARM_MBISTOUTDATA1 0x477f4
85409 #define A_ARM_MBISTOUTDATA0 0x477f8
85410 #define A_ARM_NVME_DB_EMU_EN 0x477fc
85412 #define S_NVME_DB_EN    0
85417 #define MC_T70_BASE_ADDR 0x48000
85419 #define A_MC_IND_ADDR 0x48000
85422 #define M_T7_AUTOINCR    0x3U
85426 #define S_IND_ADDR_ADDR    0
85427 #define M_IND_ADDR_ADDR    0x1ffffffU
85431 #define A_MC_IND_DATA 0x48004
85432 #define A_MC_DBG_CTL 0x48018
85433 #define A_MC_DBG_DATA 0x4801c
85434 #define A_T7_MC_P_DDRPHY_RST_CTRL 0x49300
85435 #define A_T7_MC_P_PERFORMANCE_CTRL 0x49304
85436 #define A_T7_MC_P_ECC_CTRL 0x49308
85439 #define M_BISTECCHBWCTL    0x3U
85448 #define M_RMW_CTL_CFG    0x3U
85452 #define A_MC_P_DDRCTL_INT_ENABLE 0x4930c
85474 #define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_ENABLE    0
85478 #define A_MC_P_DDRCTL_INT_CAUSE 0x49310
85580 #define S_HIF_RDATA_ADDR_ERR_INTR_DCH0_CAUSE    0
85584 #define A_T7_MC_P_PAR_ENABLE 0x49314
85638 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_ENABLE    0
85642 #define A_T7_MC_P_PAR_CAUSE 0x49318
85696 #define S_HIF_WDATA_MASK_FIFO_PARERR_DCH0_CAUSE    0
85700 #define A_T7_MC_P_INT_ENABLE 0x4931c
85718 #define A_T7_MC_P_INT_CAUSE 0x49320
85736 #define A_MC_P_ECC_UE_INT_ENABLE 0x49324
85738 #define S_BIST_RSP_SRAM_UERR_ENABLE    0
85742 #define A_MC_P_ECC_UE_INT_CAUSE 0x49328
85744 #define S_BIST_RSP_SRAM_UERR_CAUSE    0
85748 #define A_T7_MC_P_ECC_STATUS 0x4932c
85749 #define A_T7_MC_P_PHY_CTRL 0x49330
85750 #define A_T7_MC_P_STATIC_CFG_STATUS 0x49334
85768 #define A_T7_MC_P_CORE_PCTL_STAT 0x49338
85769 #define A_T7_MC_P_DEBUG_CNT 0x4933c
85770 #define A_T7_MC_CE_ERR_DATA_RDATA 0x49340
85771 #define A_T7_MC_UE_ERR_DATA_RDATA 0x49380
85772 #define A_T7_MC_CE_ADDR 0x493c0
85773 #define A_T7_MC_UE_ADDR 0x493c4
85774 #define A_T7_MC_P_DEEP_SLEEP 0x493c8
85775 #define A_T7_MC_P_FPGA_BONUS 0x493cc
85776 #define A_T7_MC_P_DEBUG_CFG 0x493d0
85777 #define A_T7_MC_P_DEBUG_RPT 0x493d4
85778 #define A_T7_MC_P_PHY_ADR_CK_EN 0x493d8
85779 #define A_MC_P_WDATARAM_INIT 0x493dc
85785 #define S_ENABLE_DCH0    0
85789 #define A_T7_MC_CE_ERR_ECC_DATA0 0x493e0
85790 #define A_T7_MC_CE_ERR_ECC_DATA1 0x493e4
85791 #define A_T7_MC_UE_ERR_ECC_DATA0 0x493e8
85792 #define A_T7_MC_UE_ERR_ECC_DATA1 0x493ec
85793 #define A_T7_MC_P_RMW_PRIO 0x493f0
85794 #define A_T7_MC_P_BIST_CMD 0x49400
85800 #define A_T7_MC_P_BIST_CMD_ADDR 0x49404
85802 #define S_T7_VALUE    0
85803 #define M_T7_VALUE    0x1fffffffU
85807 #define A_MC_P_BIST_NUM_BURST 0x49408
85808 #define A_T7_MC_P_BIST_DATA_PATTERN 0x4940c
85810 #define S_DATA_TYPE    0
85811 #define M_DATA_TYPE    0xfU
85815 #define A_T7_MC_P_BIST_CRC_SEED 0x49410
85816 #define A_T7_MC_P_BIST_NUM_ERR 0x49460
85817 #define A_MC_P_BIST_ERR_ADDR 0x49464
85819 #define S_ERROR_ADDR    0
85820 #define M_ERROR_ADDR    0x3fffffffU
85824 #define A_MC_P_BIST_USER_RWEDATA 0x49468
85825 #define A_MC_REGB_DDRC_CH0_SCHED0 0x10380
85840 #define M_LPR_NUM_ENTRIES    0x3fU
85868 #define A_MC_REGB_DDRC_CH0_ECCCFG0 0x10600
85875 #define M_ECC_TYPE    0x3U
85883 #define S_ECC_MODE    0
85884 #define M_ECC_MODE    0x7U
85888 #define A_MC_REGB_DDRC_CH0_ECCCFG1 0x10604
85894 #define S_DATA_POISON_EN    0
85898 #define A_MC_REGB_DDRC_CH0_ECCSTAT 0x10608
85901 #define M_ECC_UNCORRECTED_ERR    0xffU
85906 #define M_ECC_CORRECTED_ERR    0xffU
85910 #define S_ECC_CORRECTED_BIT_NUM    0
85911 #define M_ECC_CORRECTED_BIT_NUM    0x7fU
85915 #define A_MC_REGB_DDRC_CH0_ECCCTL 0x1060c
85945 #define S_ECC_CORRECTED_ERR_CLR    0
85949 #define A_MC_REGB_DDRC_CH0_ECCERRCNT 0x10610
85952 #define M_ECC_UNCORR_ERR_CNT    0xffffU
85956 #define S_ECC_CORR_ERR_CNT    0
85957 #define M_ECC_CORR_ERR_CNT    0xffffU
85961 #define A_MC_REGB_DDRC_CH0_ECCCADDR0 0x10614
85967 #define S_ECC_CORR_ROW    0
85968 #define M_ECC_CORR_ROW    0x3ffffU
85972 #define A_MC_REGB_DDRC_CH0_ECCCADDR1 0x10618
85975 #define M_ECC_CORR_BG    0x7U
85980 #define M_ECC_CORR_BANK    0x3U
85984 #define S_ECC_CORR_COL    0
85985 #define M_ECC_CORR_COL    0x7ffU
85989 #define A_MC_REGB_DDRC_CH0_ECCCSYN0 0x1061c
85990 #define A_MC_REGB_DDRC_CH0_ECCCSYN1 0x10620
85991 #define A_MC_REGB_DDRC_CH0_ECCCSYN2 0x10624
85994 #define M_CB_CORR_SYNDROME    0xffU
85998 #define S_ECC_CORR_SYNDROMES_71_64    0
85999 #define M_ECC_CORR_SYNDROMES_71_64    0xffU
86003 #define A_MC_REGB_DDRC_CH0_ECCBITMASK0 0x10628
86004 #define A_MC_REGB_DDRC_CH0_ECCBITMASK1 0x1062c
86005 #define A_MC_REGB_DDRC_CH0_ECCBITMASK2 0x10630
86007 #define S_ECC_CORR_BIT_MASK_71_64    0
86008 #define M_ECC_CORR_BIT_MASK_71_64    0xffU
86012 #define A_MC_REGB_DDRC_CH0_ECCUADDR0 0x10634
86018 #define S_ECC_UNCORR_ROW    0
86019 #define M_ECC_UNCORR_ROW    0x3ffffU
86023 #define A_MC_REGB_DDRC_CH0_ECCUADDR1 0x10638
86026 #define M_ECC_UNCORR_BG    0x7U
86031 #define M_ECC_UNCORR_BANK    0x3U
86035 #define S_ECC_UNCORR_COL    0
86036 #define M_ECC_UNCORR_COL    0x7ffU
86040 #define A_MC_REGB_DDRC_CH0_ECCUSYN0 0x1063c
86041 #define A_MC_REGB_DDRC_CH0_ECCUSYN1 0x10640
86042 #define A_MC_REGB_DDRC_CH0_ECCUSYN2 0x10644
86045 #define M_CB_UNCORR_SYNDROME    0xffU
86049 #define S_ECC_UNCORR_SYNDROMES_71_64    0
86050 #define M_ECC_UNCORR_SYNDROMES_71_64    0xffU
86054 #define A_MC_REGB_DDRC_CH0_ECCPOISONADDR0 0x10648
86060 #define S_ECC_POISON_COL    0
86061 #define M_ECC_POISON_COL    0xfffU
86065 #define A_MC_REGB_DDRC_CH0_ECCPOISONADDR1 0x1064c
86068 #define M_ECC_POISON_BG    0x7U
86073 #define M_ECC_POISON_BANK    0x3U
86077 #define S_ECC_POISON_ROW    0
86078 #define M_ECC_POISON_ROW    0x3ffffU
86082 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT0 0x10658
86083 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT1 0x1065c
86084 #define A_MC_REGB_DDRC_CH0_ECCPOISONPAT2 0x10660
86086 #define S_ECC_POISON_DATA_71_64    0
86087 #define M_ECC_POISON_DATA_71_64    0xffU
86091 #define A_MC_REGB_DDRC_CH0_ECCCFG2 0x10668
86094 #define M_FLIP_BIT_POS1    0x7fU
86099 #define M_FLIP_BIT_POS0    0x7fU
86103 #define A_MC_REGB_DDRC_CH1_ECCCTL 0x1160c
86104 #define A_MC_REGB_DDRC_CH1_ECCERRCNT 0x11610
86105 #define A_MC_REGB_DDRC_CH1_ECCCADDR0 0x11614
86106 #define A_MC_REGB_DDRC_CH1_ECCCADDR1 0x11618
86107 #define A_MC_REGB_DDRC_CH1_ECCCSYN0 0x1161c
86108 #define A_MC_REGB_DDRC_CH1_ECCCSYN1 0x11620
86109 #define A_MC_REGB_DDRC_CH1_ECCCSYN2 0x11624
86110 #define A_MC_REGB_DDRC_CH1_ECCBITMASK0 0x11628
86111 #define A_MC_REGB_DDRC_CH1_ECCBITMASK1 0x1162c
86112 #define A_MC_REGB_DDRC_CH1_ECCBITMASK2 0x11630
86113 #define A_MC_REGB_DDRC_CH1_ECCUADDR0 0x11634
86114 #define A_MC_REGB_DDRC_CH1_ECCUADDR1 0x11638
86115 #define A_MC_REGB_DDRC_CH1_ECCUSYN0 0x1163c
86116 #define A_MC_REGB_DDRC_CH1_ECCUSYN1 0x11640
86117 #define A_MC_REGB_DDRC_CH1_ECCUSYN2 0x11644
86118 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTENABLE 0x20100
86153 #define M_PHYFWRESERVEDEN    0x1fU
86165 #define S_PHYTRNGCMPLTEN    0
86169 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTFWCONTROL 0x20101
86172 #define M_PHYFWRESERVEDFW    0x1fU
86184 #define S_PHYTRNGCMPLTFW    0
86188 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTMASK 0x20102
86223 #define M_PHYFWRESERVEDMSK    0x1fU
86235 #define S_PHYTRNGCMPLTMSK    0
86239 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTCLEAR 0x20103
86274 #define M_PHYFWRESERVEDCLR    0x1fU
86286 #define S_PHYTRNGCMPLTCLR    0
86290 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTSTATUS 0x20104
86325 #define M_PHYFWRESERVED    0x1fU
86337 #define S_PHYTRNGCMPLT    0
86341 #define A_MC_DWC_DDRPHYA_MASTER0_BASE0_PHYINTERRUPTOVERRIDE 0x20107
86343 #define S_PHYINTERRUPTOVERRIDE    0
86344 #define M_PHYINTERRUPTOVERRIDE    0xffffU
86349 #define MC_T71_BASE_ADDR 0x58000
86352 #define GCACHE_BASE_ADDR 0x51400
86354 #define A_GCACHE_MODE_SEL0 0x51400
86360 #define A_GCACHE_MEMZONE0_REGION1 0x51404
86374 #define S_END1    0
86375 #define M_END1    0xffffU
86379 #define A_GCACHE_MEMZONE0_REGION2 0x51408
86393 #define S_END2    0
86394 #define M_END2    0xffffU
86398 #define A_GCACHE_MEMZONE0_REGION3 0x5140c
86412 #define S_END3    0
86413 #define M_END3    0xffffU
86417 #define A_GCACHE_MEMZONE0_REGION4 0x51410
86431 #define S_END4    0
86432 #define M_END4    0xffffU
86436 #define A_GCACHE_MEMZONE0_REGION5 0x51414
86450 #define S_END5    0
86451 #define M_END5    0xffffU
86455 #define A_GCACHE_MEMZONE0_REGION6 0x51418
86469 #define S_END6    0
86470 #define M_END6    0xffffU
86474 #define A_GCACHE_MEMZONE0_REGION7 0x5141c
86488 #define S_END7    0
86489 #define M_END7    0xffffU
86493 #define A_GCACHE_MEMZONE0_REGION8 0x51420
86507 #define S_END8    0
86508 #define M_END8    0xffffU
86512 #define A_GCACHE_REG0_BASE_MSB 0x51424
86513 #define A_GCACHE_MEMZONE0_REGION1_MSB 0x51428
86515 #define S_START1    0
86516 #define M_START1    0xffffU
86520 #define A_GCACHE_MEMZONE0_REGION2_MSB 0x5142c
86522 #define S_START2    0
86523 #define M_START2    0xffffU
86527 #define A_GCACHE_MEMZONE0_REGION3_MSB 0x51430
86529 #define S_START3    0
86530 #define M_START3    0xffffU
86534 #define A_GCACHE_MEMZONE0_REGION4_MSB 0x51434
86536 #define S_START4    0
86537 #define M_START4    0xffffU
86541 #define A_GCACHE_MEMZONE0_REGION5_MSB 0x51438
86543 #define S_START5    0
86544 #define M_START5    0xffffU
86548 #define A_GCACHE_MEMZONE0_REGION6_MSB 0x5143c
86550 #define S_START6    0
86551 #define M_START6    0xffffU
86555 #define A_GCACHE_MEMZONE0_REGION7_MSB 0x51440
86557 #define S_START7    0
86558 #define M_START7    0xffffU
86562 #define A_GCACHE_MEMZONE0_REGION8_MSB 0x51444
86564 #define S_START8    0
86565 #define M_START8    0xffffU
86569 #define A_GCACHE_MODE_SEL1 0x51448
86570 #define A_GCACHE_MEMZONE1_REGION1 0x5144c
86571 #define A_GCACHE_MEMZONE1_REGION2 0x51450
86572 #define A_GCACHE_MEMZONE1_REGION3 0x51454
86573 #define A_GCACHE_MEMZONE1_REGION4 0x51458
86574 #define A_GCACHE_MEMZONE1_REGION5 0x5145c
86575 #define A_GCACHE_MEMZONE1_REGION6 0x51460
86576 #define A_GCACHE_MEMZONE1_REGION7 0x51464
86577 #define A_GCACHE_MEMZONE1_REGION8 0x51468
86578 #define A_GCACHE_MEMZONE1_REGION1_MSB 0x5146c
86579 #define A_GCACHE_MEMZONE1_REGION2_MSB 0x51470
86580 #define A_GCACHE_MEMZONE1_REGION3_MSB 0x51474
86581 #define A_GCACHE_MEMZONE1_REGION4_MSB 0x51478
86582 #define A_GCACHE_MEMZONE1_REGION5_MSB 0x5147c
86583 #define A_GCACHE_MEMZONE1_REGION6_MSB 0x51480
86584 #define A_GCACHE_MEMZONE1_REGION7_MSB 0x51484
86585 #define A_GCACHE_MEMZONE1_REGION8_MSB 0x51488
86586 #define A_GCACHE_HMA_MC1_EN 0x5148c
86592 #define S_HMA_EN    0
86596 #define A_GCACHE_P_BIST_CMD 0x51490
86597 #define A_GCACHE_P_BIST_CMD_ADDR 0x51494
86598 #define A_GCACHE_P_BIST_CMD_LEN 0x51498
86599 #define A_GCACHE_P_BIST_DATA_PATTERN 0x5149c
86600 #define A_GCACHE_P_BIST_USER_WDATA0 0x514a0
86601 #define A_GCACHE_P_BIST_USER_WDATA1 0x514a4
86602 #define A_GCACHE_P_BIST_USER_WDATA2 0x514a8
86603 #define A_GCACHE_P_BIST_NUM_ERR 0x514ac
86604 #define A_GCACHE_P_BIST_ERR_FIRST_ADDR 0x514b0
86605 #define A_GCACHE_P_BIST_STATUS_RDATA 0x514b4
86606 #define A_GCACHE_P_BIST_CRC_SEED 0x514fc
86607 #define A_GCACHE_CACHE_SIZE 0x51500
86613 #define S_MC0_2MB    0
86617 #define A_GCACHE_HINT_MAPPING 0x51504
86620 #define M_CLIENT_HINT_EN    0x7fffU
86636 #define S_LE_HINT_HMA_MC    0
86640 #define A_GCACHE_PERF_EN 0x51508
86654 #define S_PERF_EN_GC0    0
86658 #define A_GCACHE_PERF_GC0_RD_HIT 0x5150c
86659 #define A_GCACHE_PERF_GC1_RD_HIT 0x51510
86660 #define A_GCACHE_PERF_GC0_WR_HIT 0x51514
86661 #define A_GCACHE_PERF_GC1_WR_HIT 0x51518
86662 #define A_GCACHE_PERF_GC0_RD_MISS 0x5151c
86663 #define A_GCACHE_PERF_GC1_RD_MISS 0x51520
86664 #define A_GCACHE_PERF_GC0_WR_MISS 0x51524
86665 #define A_GCACHE_PERF_GC1_WR_MISS 0x51528
86666 #define A_GCACHE_PERF_GC0_RD_REQ 0x5152c
86667 #define A_GCACHE_PERF_GC1_RD_REQ 0x51530
86668 #define A_GCACHE_PERF_GC0_WR_REQ 0x51534
86669 #define A_GCACHE_PERF_GC1_WR_REQ 0x51538
86670 #define A_GCACHE_PAR_CAUSE 0x5153c
86780 #define S_ILLADDRACCESS0_PAR_CAUSE    0
86784 #define A_GCACHE_PAR_ENABLE 0x51540
86894 #define S_ILLADDRACCESS0_PAR_ENABLE    0
86898 #define A_GCACHE_INT_ENABLE 0x51544
87008 #define S_ILLADDRACCESS0_INT_ENABLE    0
87012 #define A_GCACHE_INT_CAUSE 0x51548
87122 #define S_ILLADDRACCESS0_INT_CAUSE    0
87126 #define A_GCACHE_DBG_SEL_CTRL 0x51550
87137 #define M_DBG_SEL_CTRLSELH    0xffU
87141 #define S_DBG_SEL_CTRLSELL    0
87142 #define M_DBG_SEL_CTRLSELL    0xffU
87146 #define A_GCACHE_LOCAL_DEBUG_RPT 0x51554
87147 #define A_GCACHE_DBG_ILL_ACC 0x5155c
87148 #define A_GCACHE_DBG_ILL_ADDR0 0x51560
87149 #define A_GCACHE_DBG_ILL_ADDR1 0x51564
87150 #define A_GCACHE_GC0_DBG_ADDR_0_32 0x51568
87151 #define A_GCACHE_GC0_DBG_ADDR_32_32 0x5156c
87152 #define A_GCACHE_GC0_DBG_ADDR_64_32 0x51570
87153 #define A_GCACHE_GC0_DBG_ADDR_96_32 0x51574
87154 #define A_GCACHE_GC0_DBG_ADDR_0_64 0x51578
87155 #define A_GCACHE_GC0_DBG_ADDR_64_64 0x5157c
87156 #define A_GCACHE_GC0_DBG_ADDR_0_96 0x51580
87157 #define A_GCACHE_GC0_DBG_ADDR_32_96 0x51584
87158 #define A_GCACHE_GC1_DBG_ADDR_0_32 0x5158c
87159 #define A_GCACHE_GC1_DBG_ADDR_32_32 0x51590
87160 #define A_GCACHE_GC1_DBG_ADDR_64_32 0x51594
87161 #define A_GCACHE_GC1_DBG_ADDR_96_32 0x51598
87162 #define A_GCACHE_GC1_DBG_ADDR_0_64 0x5159c
87163 #define A_GCACHE_GC1_DBG_ADDR_64_64 0x515a0
87164 #define A_GCACHE_GC1_DBG_ADDR_0_96 0x515a4
87165 #define A_GCACHE_GC1_DBG_ADDR_32_96 0x515a8
87166 #define A_GCACHE_GC0_DBG_ADDR_32_64 0x515ac
87167 #define A_GCACHE_GC1_DBG_ADDR_32_64 0x515b0
87168 #define A_GCACHE_PERF_GC0_EVICT 0x515b4
87169 #define A_GCACHE_PERF_GC1_EVICT 0x515b8
87170 #define A_GCACHE_PERF_GC0_CE_COUNT 0x515bc
87171 #define A_GCACHE_PERF_GC1_CE_COUNT 0x515c0
87172 #define A_GCACHE_PERF_GC0_UE_COUNT 0x515c4
87173 #define A_GCACHE_PERF_GC1_UE_COUNT 0x515c8
87174 #define A_GCACHE_DBG_CTL 0x515f0
87175 #define A_GCACHE_DBG_DATA 0x515f4