Lines Matching +full:1 +full:x
9 * 1. Redistributions of source code must retain the above copyright
184 CPL_ERR_TCAM_PARITY = 1,
249 CPL_CONN_POLICY_ASK = 1,
266 ULP_CRC_HEADER = 1 << 0,
267 ULP_CRC_DATA = 1 << 1
283 TX_CSUM_UDP = 1,
297 PKTYPE_HASH_UCAST = 1,
320 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
332 LE_SZ_33 = 1,
345 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
346 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
347 #define G_TID(x) ((x) & 0xFFFFFF)
366 #define V_TID_TID(x) ((x) << S_TID_TID)
367 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
371 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE)
372 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE)
376 #define V_TID_QID(x) ((x) << S_TID_QID)
377 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
389 __u8 unknown:1;
390 __u8 ecn:1;
391 __u8 sack:1;
392 __u8 tstamp:1;
394 __u8 tstamp:1;
395 __u8 sack:1;
396 __u8 ecn:1;
397 __u8 unknown:1;
406 __u8 filter_hit:1;
407 __u8 filter_tid:1;
409 __u8 ipv6:1;
410 __u8 send2fw:1;
412 __u8 send2fw:1;
413 __u8 ipv6:1;
415 __u8 filter_tid:1;
416 __u8 filter_hit:1;
425 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
429 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
447 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
448 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
453 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
454 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
466 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
467 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
471 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
472 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
475 #define V_NO_CONG(x) ((x) << S_NO_CONG)
476 #define F_NO_CONG V_NO_CONG(1U)
479 #define V_DELACK(x) ((x) << S_DELACK)
480 #define F_DELACK V_DELACK(1U)
483 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
484 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
487 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
488 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
492 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
493 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
497 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
498 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
502 #define V_DSCP(x) ((x) << S_DSCP)
503 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
507 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
508 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
512 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
513 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
516 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
517 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
520 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
521 #define F_NAGLE V_NAGLE(1ULL)
525 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
526 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
529 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
530 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
534 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
535 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
538 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
539 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
543 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
544 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
546 /* option 1 fields */
548 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
549 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
551 #define S_SYN_RSS_USE_HASH 1
552 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
553 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
557 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
558 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
562 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
563 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
566 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
567 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
570 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
571 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
575 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
576 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
580 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO)
581 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO)
585 #define V_FILT_INFO(x) ((x) << S_FILT_INFO)
586 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO)
591 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
592 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
595 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
596 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
599 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
600 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
604 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
605 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
609 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
610 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
614 #define V_PACE(x) ((x) << S_PACE)
615 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
618 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
619 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
622 #define V_T5_ISS(x) ((x) << S_T5_ISS)
623 #define F_T5_ISS V_T5_ISS(1U)
626 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
627 #define F_PACE_VALID V_PACE_VALID(1U)
630 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
631 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
634 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
635 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
638 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
639 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
643 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
644 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
647 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
648 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
651 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
652 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
655 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
656 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
659 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
660 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
663 #define V_SACK_EN(x) ((x) << S_SACK_EN)
664 #define F_SACK_EN V_SACK_EN(1U)
667 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID)
668 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U)
715 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
716 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
720 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
721 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
726 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK)
727 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK)
731 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK)
732 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK)
736 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP)
737 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP)
741 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE)
742 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE)
746 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS)
747 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS)
764 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
765 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
769 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
770 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
773 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN)
774 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN)
778 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
779 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
782 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN)
783 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN)
787 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
788 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
792 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN)
793 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN)
798 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
799 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
802 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
803 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
807 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
808 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
826 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \
827 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN)
828 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \
829 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) & \
832 V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(1U)
836 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \
837 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE)
838 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \
839 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) & \
844 #define V_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \
845 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN)
846 #define G_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \
847 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) & \
852 #define V_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \
853 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN)
854 #define G_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \
855 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) & \
860 #define V_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \
861 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN)
862 #define G_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \
863 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) & \
868 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \
869 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN)
870 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \
871 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) & \
876 #define V_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \
877 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL)
878 #define G_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \
879 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) & \
884 #define V_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \
885 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE)
886 #define G_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \
887 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) & \
892 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \
893 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH)
894 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \
895 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) & \
898 V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(1U)
902 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \
903 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX)
904 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \
905 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) & M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX)
909 #define V_CPL_T7_PASS_ACCEPT_REQ_TOS(x) ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TOS)
910 #define G_CPL_T7_PASS_ACCEPT_REQ_TOS(x) \
911 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TOS) & M_CPL_T7_PASS_ACCEPT_REQ_TOS)
915 #define V_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \
916 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_PTID)
917 #define G_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \
918 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_PTID) & M_CPL_T7_PASS_ACCEPT_REQ_PTID)
922 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \
923 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP)
924 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \
925 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) & \
928 V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(1U)
932 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \
933 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK)
934 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \
935 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) & \
938 V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(1U)
942 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \
943 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPECN)
944 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \
945 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) & M_CPL_T7_PASS_ACCEPT_REQ_TCPECN)
947 V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(1U)
951 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \
952 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN)
953 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \
954 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) & \
957 V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(1U)
992 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
993 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
1025 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK)
1026 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U)
1043 #define S_T7_FILTER_TUPLE 1
1045 #define V_T7_FILTER_TUPLE(x) ((x) << S_T7_FILTER_TUPLE)
1046 #define G_T7_FILTER_TUPLE(x) (((x) >> S_T7_FILTER_TUPLE) & M_T7_FILTER_TUPLE)
1120 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
1121 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
1125 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
1126 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
1149 #define V_QUEUENO(x) ((x) << S_QUEUENO)
1150 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
1154 #define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO)
1155 #define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO)
1158 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
1159 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
1163 #define V_T7_REPLY_CHAN(x) ((x) << S_T7_REPLY_CHAN)
1164 #define G_T7_REPLY_CHAN(x) (((x) >> S_T7_REPLY_CHAN) & M_T7_REPLY_CHAN)
1167 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
1168 #define F_NO_REPLY V_NO_REPLY(1U)
1205 #define V_WORD(x) ((x) << S_WORD)
1206 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
1210 #define V_COOKIE(x) ((x) << S_COOKIE)
1211 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
1246 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
1247 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
1258 #define V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \
1259 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY)
1260 #define G_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \
1261 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) & \
1264 V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(1U)
1268 #define V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \
1269 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6)
1270 #define G_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \
1271 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) & M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6)
1273 V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(1U)
1277 #define V_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \
1278 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE)
1279 #define G_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \
1280 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) & \
1305 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS)
1306 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS)
1310 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX)
1311 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX)
1315 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1)
1316 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ
1317 * bit[2] specifies whether to disable the mmgr (1) or not (0)
1390 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
1391 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
1396 #define V_TX_PORT(x) ((x) << S_TX_PORT)
1397 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
1401 #define V_TX_MSS(x) ((x) << S_TX_MSS)
1402 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
1406 #define V_TX_QOS(x) ((x) << S_TX_QOS)
1407 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
1411 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
1412 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
1424 #define V_TX_DATA_MSS(x) ((x) << S_TX_DATA_MSS)
1425 #define G_TX_DATA_MSS(x) (((x) >> S_TX_DATA_MSS) & M_TX_DATA_MSS)
1429 #define V_TX_LENGTH(x) ((x) << S_TX_LENGTH)
1430 #define G_TX_LENGTH(x) (((x) >> S_TX_LENGTH) & M_TX_LENGTH)
1434 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
1435 #define F_TX_PROXY V_TX_PROXY(1U)
1439 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
1440 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
1444 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
1445 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
1448 #define V_TX_FORCE(x) ((x) << S_TX_FORCE)
1449 #define F_TX_FORCE V_TX_FORCE(1U)
1452 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
1453 #define F_TX_SHOVE V_TX_SHOVE(1U)
1456 #define V_TX_MORE(x) ((x) << S_TX_MORE)
1457 #define F_TX_MORE V_TX_MORE(1U)
1460 #define V_TX_URG(x) ((x) << S_TX_URG)
1461 #define F_TX_URG V_TX_URG(1U)
1464 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
1465 #define F_TX_FLUSH V_TX_FLUSH(1U)
1468 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
1469 #define F_TX_SAVE V_TX_SAVE(1U)
1472 #define V_TX_TNL(x) ((x) << S_TX_TNL)
1473 #define F_TX_TNL V_TX_TNL(1U)
1476 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE)
1477 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U)
1480 #define V_TX_BYPASS(x) ((x) << S_TX_BYPASS)
1481 #define F_TX_BYPASS V_TX_BYPASS(1U)
1484 #define V_TX_PUSH(x) ((x) << S_TX_PUSH)
1485 #define F_TX_PUSH V_TX_PUSH(1U)
1490 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
1491 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
1494 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
1495 #define F_TX_CLOSE V_TX_CLOSE(1U)
1498 #define V_TX_INIT(x) ((x) << S_TX_INIT)
1499 #define F_TX_INIT V_TX_INIT(1U)
1502 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
1503 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
1506 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
1507 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
1541 #define V_CPL_TX_DATA_REQ_TID(x) ((x) << S_CPL_TX_DATA_REQ_TID)
1542 #define G_CPL_TX_DATA_REQ_TID(x) \
1543 (((x) >> S_CPL_TX_DATA_REQ_TID) & M_CPL_TX_DATA_REQ_TID)
1567 #define V_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \
1568 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIEVALUE)
1569 #define G_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \
1570 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) & \
1575 #define V_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \
1576 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIESEL)
1577 #define G_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \
1578 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIESEL) & M_CPL_SGE_FLR_FLUSH_COOKIESEL)
1604 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1605 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1609 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1610 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1613 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1614 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1618 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1619 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1623 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX)
1624 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \
1629 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1630 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1633 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1634 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1637 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS)
1638 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U)
1641 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1642 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1645 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN)
1646 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U)
1649 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1650 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1653 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1654 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1657 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP)
1658 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U)
1662 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1663 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1668 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1669 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1673 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1674 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1678 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1679 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1683 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1684 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1687 #define G_T6_TXPKT_IPHDR_LEN(x) \
1688 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN)
1692 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1693 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1697 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1698 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1702 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
1703 #define G_T6_TXPKT_ETHHDR_LEN(x) \
1704 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
1708 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1709 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1713 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1714 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1717 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1718 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1721 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1722 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1725 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1726 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1729 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1730 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1744 #define V_CPL_TX_PKT_XT_OPCODE(x) ((x) << S_CPL_TX_PKT_XT_OPCODE)
1745 #define G_CPL_TX_PKT_XT_OPCODE(x) \
1746 (((x) >> S_CPL_TX_PKT_XT_OPCODE) & M_CPL_TX_PKT_XT_OPCODE)
1750 #define V_CPL_TX_PKT_XT_TIMESTAMP(x) ((x) << S_CPL_TX_PKT_XT_TIMESTAMP)
1751 #define G_CPL_TX_PKT_XT_TIMESTAMP(x) \
1752 (((x) >> S_CPL_TX_PKT_XT_TIMESTAMP) & M_CPL_TX_PKT_XT_TIMESTAMP)
1753 #define F_CPL_TX_PKT_XT_TIMESTAMP V_CPL_TX_PKT_XT_TIMESTAMP(1U)
1757 #define V_CPL_TX_PKT_XT_STATDISABLE(x) ((x) << S_CPL_TX_PKT_XT_STATDISABLE)
1758 #define G_CPL_TX_PKT_XT_STATDISABLE(x) \
1759 (((x) >> S_CPL_TX_PKT_XT_STATDISABLE) & M_CPL_TX_PKT_XT_STATDISABLE)
1760 #define F_CPL_TX_PKT_XT_STATDISABLE V_CPL_TX_PKT_XT_STATDISABLE(1U)
1764 #define V_CPL_TX_PKT_XT_FCSDIS(x) ((x) << S_CPL_TX_PKT_XT_FCSDIS)
1765 #define G_CPL_TX_PKT_XT_FCSDIS(x) \
1766 (((x) >> S_CPL_TX_PKT_XT_FCSDIS) & M_CPL_TX_PKT_XT_FCSDIS)
1767 #define F_CPL_TX_PKT_XT_FCSDIS V_CPL_TX_PKT_XT_FCSDIS(1U)
1771 #define V_CPL_TX_PKT_XT_STATSPECIAL(x) ((x) << S_CPL_TX_PKT_XT_STATSPECIAL)
1772 #define G_CPL_TX_PKT_XT_STATSPECIAL(x) \
1773 (((x) >> S_CPL_TX_PKT_XT_STATSPECIAL) & M_CPL_TX_PKT_XT_STATSPECIAL)
1774 #define F_CPL_TX_PKT_XT_STATSPECIAL V_CPL_TX_PKT_XT_STATSPECIAL(1U)
1778 #define V_CPL_TX_PKT_XT_INTERFACE(x) ((x) << S_CPL_TX_PKT_XT_INTERFACE)
1779 #define G_CPL_TX_PKT_XT_INTERFACE(x) \
1780 (((x) >> S_CPL_TX_PKT_XT_INTERFACE) & M_CPL_TX_PKT_XT_INTERFACE)
1784 #define V_CPL_TX_PKT_XT_OVLAN(x) ((x) << S_CPL_TX_PKT_XT_OVLAN)
1785 #define G_CPL_TX_PKT_XT_OVLAN(x) \
1786 (((x) >> S_CPL_TX_PKT_XT_OVLAN) & M_CPL_TX_PKT_XT_OVLAN)
1787 #define F_CPL_TX_PKT_XT_OVLAN V_CPL_TX_PKT_XT_OVLAN(1U)
1791 #define V_CPL_TX_PKT_XT_OVLANIDX(x) ((x) << S_CPL_TX_PKT_XT_OVLANIDX)
1792 #define G_CPL_TX_PKT_XT_OVLANIDX(x) \
1793 (((x) >> S_CPL_TX_PKT_XT_OVLANIDX) & M_CPL_TX_PKT_XT_OVLANIDX)
1797 #define V_CPL_TX_PKT_XT_VFVALID(x) ((x) << S_CPL_TX_PKT_XT_VFVALID)
1798 #define G_CPL_TX_PKT_XT_VFVALID(x) \
1799 (((x) >> S_CPL_TX_PKT_XT_VFVALID) & M_CPL_TX_PKT_XT_VFVALID)
1800 #define F_CPL_TX_PKT_XT_VFVALID V_CPL_TX_PKT_XT_VFVALID(1U)
1804 #define V_CPL_TX_PKT_XT_PF(x) ((x) << S_CPL_TX_PKT_XT_PF)
1805 #define G_CPL_TX_PKT_XT_PF(x) \
1806 (((x) >> S_CPL_TX_PKT_XT_PF) & M_CPL_TX_PKT_XT_PF)
1810 #define V_CPL_TX_PKT_XT_VF(x) ((x) << S_CPL_TX_PKT_XT_VF)
1811 #define G_CPL_TX_PKT_XT_VF(x) \
1812 (((x) >> S_CPL_TX_PKT_XT_VF) & M_CPL_TX_PKT_XT_VF)
1817 #define V_CPL_TX_PKT_XT_L4CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L4CHKDISABLE)
1818 #define G_CPL_TX_PKT_XT_L4CHKDISABLE(x) \
1819 (((x) >> S_CPL_TX_PKT_XT_L4CHKDISABLE) & M_CPL_TX_PKT_XT_L4CHKDISABLE)
1820 #define F_CPL_TX_PKT_XT_L4CHKDISABLE V_CPL_TX_PKT_XT_L4CHKDISABLE(1U)
1824 #define V_CPL_TX_PKT_XT_L3CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L3CHKDISABLE)
1825 #define G_CPL_TX_PKT_XT_L3CHKDISABLE(x) \
1826 (((x) >> S_CPL_TX_PKT_XT_L3CHKDISABLE) & M_CPL_TX_PKT_XT_L3CHKDISABLE)
1827 #define F_CPL_TX_PKT_XT_L3CHKDISABLE V_CPL_TX_PKT_XT_L3CHKDISABLE(1U)
1831 #define V_CPL_TX_PKT_XT_OUTL4CHKEN(x) ((x) << S_CPL_TX_PKT_XT_OUTL4CHKEN)
1832 #define G_CPL_TX_PKT_XT_OUTL4CHKEN(x) \
1833 (((x) >> S_CPL_TX_PKT_XT_OUTL4CHKEN) & M_CPL_TX_PKT_XT_OUTL4CHKEN)
1834 #define F_CPL_TX_PKT_XT_OUTL4CHKEN V_CPL_TX_PKT_XT_OUTL4CHKEN(1U)
1838 #define V_CPL_TX_PKT_XT_IVLAN(x) ((x) << S_CPL_TX_PKT_XT_IVLAN)
1839 #define G_CPL_TX_PKT_XT_IVLAN(x) \
1840 (((x) >> S_CPL_TX_PKT_XT_IVLAN) & M_CPL_TX_PKT_XT_IVLAN)
1841 #define F_CPL_TX_PKT_XT_IVLAN V_CPL_TX_PKT_XT_IVLAN(1U)
1845 #define V_CPL_TX_PKT_XT_IVLANTAG(x) ((x) << S_CPL_TX_PKT_XT_IVLANTAG)
1846 #define G_CPL_TX_PKT_XT_IVLANTAG(x) \
1847 (((x) >> S_CPL_TX_PKT_XT_IVLANTAG) & M_CPL_TX_PKT_XT_IVLANTAG)
1851 #define V_CPL_TX_PKT_XT_CHKTYPE(x) ((x) << S_CPL_TX_PKT_XT_CHKTYPE)
1852 #define G_CPL_TX_PKT_XT_CHKTYPE(x) \
1853 (((x) >> S_CPL_TX_PKT_XT_CHKTYPE) & M_CPL_TX_PKT_XT_CHKTYPE)
1857 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \
1858 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI)
1859 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \
1860 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) & \
1865 #define V_CPL_TX_PKT_XT_ETHHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_ETHHDRLEN)
1866 #define G_CPL_TX_PKT_XT_ETHHDRLEN(x) \
1867 (((x) >> S_CPL_TX_PKT_XT_ETHHDRLEN) & M_CPL_TX_PKT_XT_ETHHDRLEN)
1871 #define V_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \
1872 ((x) << S_CPL_TX_PKT_XT_ROCECHKINSMODE)
1873 #define G_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \
1874 (((x) >> S_CPL_TX_PKT_XT_ROCECHKINSMODE) & M_CPL_TX_PKT_XT_ROCECHKINSMODE)
1878 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \
1879 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI)
1880 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \
1881 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) & \
1886 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \
1887 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO)
1888 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \
1889 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \
1895 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \
1896 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO)
1897 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \
1898 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) & \
1903 #define V_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \
1904 ((x) << S_CPL_TX_PKT_XT_CHKSTARTOFFSET)
1905 #define G_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \
1906 (((x) >> S_CPL_TX_PKT_XT_CHKSTARTOFFSET) & M_CPL_TX_PKT_XT_CHKSTARTOFFSET)
1910 #define V_CPL_TX_PKT_XT_IPHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_IPHDRLEN)
1911 #define G_CPL_TX_PKT_XT_IPHDRLEN(x) \
1912 (((x) >> S_CPL_TX_PKT_XT_IPHDRLEN) & M_CPL_TX_PKT_XT_IPHDRLEN)
1916 #define V_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \
1917 ((x) << S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET)
1918 #define G_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \
1919 (((x) >> S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) & \
1924 #define V_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \
1925 ((x) << S_CPL_TX_PKT_XT_CHKSTOPOFFSET)
1926 #define G_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \
1927 (((x) >> S_CPL_TX_PKT_XT_CHKSTOPOFFSET) & M_CPL_TX_PKT_XT_CHKSTOPOFFSET)
1931 #define V_CPL_TX_PKT_XT_IPSECIDX(x) ((x) << S_CPL_TX_PKT_XT_IPSECIDX)
1932 #define G_CPL_TX_PKT_XT_IPSECIDX(x) \
1933 (((x) >> S_CPL_TX_PKT_XT_IPSECIDX) & M_CPL_TX_PKT_XT_IPSECIDX)
1937 #define V_CPL_TX_TNL_LSO_BTH_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE)
1938 #define G_CPL_TX_TNL_LSO_BTH_OPCODE(x) \
1939 (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \
1944 #define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \
1945 ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN)
1946 #define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \
1947 (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \
1952 #define V_CPL_TX_TNL_LSO_MSS_TVER(x) ((x) << S_CPL_TX_TNL_LSO_MSS_TVER)
1953 #define G_CPL_TX_TNL_LSO_MSS_TVER(x) \
1954 (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER)
1958 #define V_CPL_TX_TNL_LSO_MSS_M(x) ((x) << S_CPL_TX_TNL_LSO_MSS_M)
1959 #define G_CPL_TX_TNL_LSO_MSS_M(x) \
1960 (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M)
1964 #define V_CPL_TX_TNL_LSO_MSS_PMTU(x) ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU)
1965 #define G_CPL_TX_TNL_LSO_MSS_PMTU(x) \
1966 (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU)
1970 #define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \
1971 ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR)
1972 #define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \
1973 (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR)
1975 #define S_CPL_TX_TNL_LSO_MSS_ACKREQ 1
1977 #define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x) ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ)
1978 #define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x) \
1979 (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ)
1983 #define V_CPL_TX_TNL_LSO_MSS_SE(x) ((x) << S_CPL_TX_TNL_LSO_MSS_SE)
1984 #define G_CPL_TX_TNL_LSO_MSS_SE(x) \
1985 (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE)
2021 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
2022 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
2026 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
2027 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
2031 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
2032 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
2035 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
2036 #define F_LSO_IPV6 V_LSO_IPV6(1U)
2039 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
2040 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
2043 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
2044 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
2047 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
2048 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
2052 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
2053 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
2057 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
2058 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
2063 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
2064 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
2067 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
2068 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
2082 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS)
2083 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U)
2086 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR)
2087 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U)
2091 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN)
2092 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN)
2122 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP)
2123 #define G_CPL_TX_DATA_ISO_OP(x) \
2124 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP)
2128 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST)
2129 #define G_CPL_TX_DATA_ISO_FIRST(x) \
2130 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST)
2131 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U)
2135 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST)
2136 #define G_CPL_TX_DATA_ISO_LAST(x) \
2137 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST)
2138 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U)
2142 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN)
2143 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \
2144 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN)
2145 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U)
2149 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC)
2150 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \
2151 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC)
2152 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U)
2156 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC)
2157 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \
2158 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC)
2159 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U)
2163 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE)
2164 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \
2165 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE)
2166 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U)
2170 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI)
2171 #define G_CPL_TX_DATA_ISO_SCSI(x) \
2172 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI)
2177 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
2178 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET)
2179 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \
2180 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \
2198 #define V_CPL_T7_TX_DATA_ISO_OPCODE(x) ((x) << S_CPL_T7_TX_DATA_ISO_OPCODE)
2199 #define G_CPL_T7_TX_DATA_ISO_OPCODE(x) \
2200 (((x) >> S_CPL_T7_TX_DATA_ISO_OPCODE) & M_CPL_T7_TX_DATA_ISO_OPCODE)
2204 #define V_CPL_T7_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_T7_TX_DATA_ISO_FIRST)
2205 #define G_CPL_T7_TX_DATA_ISO_FIRST(x) \
2206 (((x) >> S_CPL_T7_TX_DATA_ISO_FIRST) & M_CPL_T7_TX_DATA_ISO_FIRST)
2207 #define F_CPL_T7_TX_DATA_ISO_FIRST V_CPL_T7_TX_DATA_ISO_FIRST(1U)
2211 #define V_CPL_T7_TX_DATA_ISO_LAST(x) ((x) << S_CPL_T7_TX_DATA_ISO_LAST)
2212 #define G_CPL_T7_TX_DATA_ISO_LAST(x) \
2213 (((x) >> S_CPL_T7_TX_DATA_ISO_LAST) & M_CPL_T7_TX_DATA_ISO_LAST)
2214 #define F_CPL_T7_TX_DATA_ISO_LAST V_CPL_T7_TX_DATA_ISO_LAST(1U)
2218 #define V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \
2219 ((x) << S_CPL_T7_TX_DATA_ISO_CPLHDRLEN)
2220 #define G_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \
2221 (((x) >> S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) & M_CPL_T7_TX_DATA_ISO_CPLHDRLEN)
2222 #define F_CPL_T7_TX_DATA_ISO_CPLHDRLEN V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(1U)
2226 #define V_CPL_T7_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_HDRCRC)
2227 #define G_CPL_T7_TX_DATA_ISO_HDRCRC(x) \
2228 (((x) >> S_CPL_T7_TX_DATA_ISO_HDRCRC) & M_CPL_T7_TX_DATA_ISO_HDRCRC)
2229 #define F_CPL_T7_TX_DATA_ISO_HDRCRC V_CPL_T7_TX_DATA_ISO_HDRCRC(1U)
2233 #define V_CPL_T7_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_PLDCRC)
2234 #define G_CPL_T7_TX_DATA_ISO_PLDCRC(x) \
2235 (((x) >> S_CPL_T7_TX_DATA_ISO_PLDCRC) & M_CPL_T7_TX_DATA_ISO_PLDCRC)
2236 #define F_CPL_T7_TX_DATA_ISO_PLDCRC V_CPL_T7_TX_DATA_ISO_PLDCRC(1U)
2240 #define V_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \
2241 ((x) << S_CPL_T7_TX_DATA_ISO_IMMEDIATE)
2242 #define G_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \
2243 (((x) >> S_CPL_T7_TX_DATA_ISO_IMMEDIATE) & M_CPL_T7_TX_DATA_ISO_IMMEDIATE)
2245 V_CPL_T7_TX_DATA_ISO_IMMEDIATE(1U)
2249 #define V_CPL_T7_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_T7_TX_DATA_ISO_SCSI)
2250 #define G_CPL_T7_TX_DATA_ISO_SCSI(x) \
2251 (((x) >> S_CPL_T7_TX_DATA_ISO_SCSI) & M_CPL_T7_TX_DATA_ISO_SCSI)
2255 #define V_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \
2256 ((x) << S_CPL_T7_TX_DATA_ISO_NVME_TCP)
2257 #define G_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \
2258 (((x) >> S_CPL_T7_TX_DATA_ISO_NVME_TCP) & M_CPL_T7_TX_DATA_ISO_NVME_TCP)
2260 V_CPL_T7_TX_DATA_ISO_NVME_TCP(1U)
2264 #define V_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \
2265 ((x) << S_CPL_T7_TX_DATA_ISO_NUMPIBYTES)
2266 #define G_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \
2267 (((x) >> S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) & M_CPL_T7_TX_DATA_ISO_NUMPIBYTES)
2271 #define V_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \
2272 ((x) << S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET)
2273 #define G_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \
2274 (((x) >> S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) & \
2291 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
2292 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
2295 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
2296 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
2318 __u8 psh:1;
2319 __u8 heartbeat:1;
2320 __u8 ddp_off:1;
2324 __u8 ddp_off:1;
2325 __u8 heartbeat:1;
2326 __u8 psh:1;
2351 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL)
2352 #define G_FCOE_FCHDR_RCTL(x) \
2353 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL)
2357 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL)
2358 #define G_FCOE_FCHDR_FCTL(x) \
2359 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL)
2398 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
2399 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
2402 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
2403 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
2406 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
2407 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
2410 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
2411 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
2415 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
2416 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
2419 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
2420 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
2515 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
2516 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
2519 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
2520 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
2523 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
2524 #define F_DDP_PDU V_DDP_PDU(1U)
2527 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
2528 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
2531 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
2532 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
2535 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
2536 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
2539 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
2540 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
2543 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
2544 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
2547 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
2548 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
2551 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
2552 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
2555 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
2556 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
2559 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
2560 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
2563 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
2564 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
2567 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
2568 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
2572 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
2573 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
2578 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
2579 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
2583 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
2584 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
2587 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
2588 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
2591 #define V_DDP_URG(x) ((x) << S_DDP_URG)
2592 #define F_DDP_URG V_DDP_URG(1U)
2595 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
2596 #define F_DDP_PSH V_DDP_PSH(1U)
2599 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
2600 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
2603 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
2604 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
2607 #define V_DDP_INV(x) ((x) << S_DDP_INV)
2608 #define F_DDP_INV V_DDP_INV(1U)
2615 __u8 csum_calc:1;
2616 __u8 ipmi_pkt:1;
2617 __u8 vlan_ex:1;
2618 __u8 ip_frag:1;
2620 __u8 ip_frag:1;
2621 __u8 vlan_ex:1;
2622 __u8 ipmi_pkt:1;
2623 __u8 csum_calc:1;
2637 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
2638 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
2642 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
2643 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
2646 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN)
2650 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
2651 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
2655 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE)
2656 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE)
2660 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
2661 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
2665 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE)
2666 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE)
2670 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
2671 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
2674 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
2675 #define F_RXF_PSH V_RXF_PSH(1U)
2678 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
2679 #define F_RXF_SYN V_RXF_SYN(1U)
2682 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
2683 #define F_RXF_UDP V_RXF_UDP(1U)
2686 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
2687 #define F_RXF_TCP V_RXF_TCP(1U)
2690 #define V_RXF_IP(x) ((x) << S_RXF_IP)
2691 #define F_RXF_IP V_RXF_IP(1U)
2694 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
2695 #define F_RXF_IP6 V_RXF_IP6(1U)
2698 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
2699 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
2702 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
2703 #define F_RXF_FCOE V_RXF_FCOE(1U)
2706 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
2707 #define F_RXF_LRO V_RXF_LRO(1U)
2711 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
2712 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
2717 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
2718 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
2722 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
2723 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
2727 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
2728 #define F_RXERR_OR V_RXERR_OR(1U)
2730 #define S_RXERR_MAC 1
2731 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
2732 #define F_RXERR_MAC V_RXERR_MAC(1U)
2735 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
2736 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
2739 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
2740 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
2743 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
2744 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
2747 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
2748 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
2751 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
2752 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
2755 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
2756 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
2759 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
2760 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
2763 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
2764 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
2767 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
2768 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
2771 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
2772 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
2775 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
2776 #define F_RXERR_PING V_RXERR_PING(1U)
2788 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
2789 #define G_T6_COMPR_RXERR_VEC(x) \
2790 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
2793 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC)
2794 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U)
2799 #define S_T6_COMPR_RXERR_LEN 1
2800 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN)
2801 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U)
2804 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT)
2805 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U)
2808 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT)
2809 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U)
2813 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM)
2814 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U)
2820 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC)
2821 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U)
2825 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE)
2826 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE)
2828 #define RX_PKT_TNL_TYPE_NVGRE 1
2834 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN)
2835 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN)
2845 __u8 err:1;
2846 __u8 trunc:1;
2850 __u8 trunc:1;
2851 __u8 err:1;
2867 __u8 err:1;
2868 __u8 trunc:1;
2872 __u8 trunc:1;
2873 __u8 err:1;
2891 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
2892 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
2896 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
2897 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
2900 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
2901 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
2922 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
2923 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
2926 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
2927 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
2932 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
2933 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
2937 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
2938 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
2961 __u32 select:1;
2963 __u32 select:1;
2981 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
2982 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
2986 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
2987 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
2990 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK)
2991 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U)
2994 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS)
2995 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U)
2998 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
2999 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
3005 #define V_L2T_VLANTAG(x) ((x) << S_L2T_VLANTAG)
3006 #define G_L2T_VLANTAG(x) (((x) >> S_L2T_VLANTAG) & M_L2T_VLANTAG)
3010 #define V_L2T_VLANPRIO(x) ((x) << S_L2T_VLANPRIO)
3011 #define G_L2T_VLANPRIO(x) (((x) >> S_L2T_VLANPRIO) & M_L2T_VLANPRIO)
3071 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN)
3072 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN)
3076 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE)
3077 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE)
3081 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID)
3082 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID)
3086 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX)
3087 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX)
3103 #define V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \
3104 ((x) << S_CPL_T7_SRQ_TABLE_REQ_NOREPLY)
3105 #define G_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \
3106 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) & M_CPL_T7_SRQ_TABLE_REQ_NOREPLY)
3108 V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(1U)
3112 #define V_CPL_T7_SRQ_TABLE_REQ_WRITE(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_WRITE)
3113 #define G_CPL_T7_SRQ_TABLE_REQ_WRITE(x) \
3114 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_WRITE) & M_CPL_T7_SRQ_TABLE_REQ_WRITE)
3115 #define F_CPL_T7_SRQ_TABLE_REQ_WRITE V_CPL_T7_SRQ_TABLE_REQ_WRITE(1U)
3119 #define V_CPL_T7_SRQ_TABLE_REQ_INCR(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INCR)
3120 #define G_CPL_T7_SRQ_TABLE_REQ_INCR(x) \
3121 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INCR) & M_CPL_T7_SRQ_TABLE_REQ_INCR)
3125 #define V_CPL_T7_SRQ_TABLE_REQ_OVER(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_OVER)
3126 #define G_CPL_T7_SRQ_TABLE_REQ_OVER(x) \
3127 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_OVER) & M_CPL_T7_SRQ_TABLE_REQ_OVER)
3131 #define V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \
3132 ((x) << S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD)
3133 #define G_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \
3134 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) & M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD)
3135 #define F_CPL_T7_SRQ_TABLE_REQ_LIMITUPD V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(1U)
3139 #define V_CPL_T7_SRQ_TABLE_REQ_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INDEX)
3140 #define G_CPL_T7_SRQ_TABLE_REQ_INDEX(x) \
3141 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INDEX) & M_CPL_T7_SRQ_TABLE_REQ_INDEX)
3145 #define V_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \
3146 ((x) << S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT)
3147 #define G_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \
3148 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT)
3152 #define V_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \
3153 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUELEN)
3154 #define G_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \
3155 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUELEN) & M_CPL_T7_SRQ_TABLE_REQ_QUELEN)
3159 #define V_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \
3160 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUEBASE)
3161 #define G_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \
3162 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) & M_CPL_T7_SRQ_TABLE_REQ_QUEBASE)
3166 #define V_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \
3167 ((x) << S_CPL_T7_SRQ_TABLE_REQ_CURMSN)
3168 #define G_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \
3169 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_CURMSN) & M_CPL_T7_SRQ_TABLE_REQ_CURMSN)
3173 #define V_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \
3174 ((x) << S_CPL_T7_SRQ_TABLE_REQ_MAXMSN)
3175 #define G_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \
3176 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) & M_CPL_T7_SRQ_TABLE_REQ_MAXMSN)
3192 #define V_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \
3193 ((x) << S_CPL_T7_SRQ_TABLE_RPL_STATUS)
3194 #define G_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \
3195 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_STATUS) & M_CPL_T7_SRQ_TABLE_RPL_STATUS)
3199 #define V_CPL_T7_SRQ_TABLE_RPL_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_RPL_INDEX)
3200 #define G_CPL_T7_SRQ_TABLE_RPL_INDEX(x) \
3201 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_INDEX) & M_CPL_T7_SRQ_TABLE_RPL_INDEX)
3205 #define V_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \
3206 ((x) << S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT)
3207 #define G_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \
3208 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT)
3212 #define V_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \
3213 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUELEN)
3214 #define G_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \
3215 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUELEN) & M_CPL_T7_SRQ_TABLE_RPL_QUELEN)
3219 #define V_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \
3220 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUEBASE)
3221 #define G_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \
3222 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) & M_CPL_T7_SRQ_TABLE_RPL_QUEBASE)
3226 #define V_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \
3227 ((x) << S_CPL_T7_SRQ_TABLE_RPL_CURMSN)
3228 #define G_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \
3229 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_CURMSN) & M_CPL_T7_SRQ_TABLE_RPL_CURMSN)
3233 #define V_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \
3234 ((x) << S_CPL_T7_SRQ_TABLE_RPL_MAXMSN)
3235 #define G_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \
3236 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) & M_CPL_T7_SRQ_TABLE_RPL_MAXMSN)
3246 #define V_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \
3247 ((x) << S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE)
3248 #define G_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \
3249 (((x) >> S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) & \
3254 #define V_CPL_RDMA_ASYNC_EVENT_INDEX(x) ((x) << S_CPL_RDMA_ASYNC_EVENT_INDEX)
3255 #define G_CPL_RDMA_ASYNC_EVENT_INDEX(x) \
3256 (((x) >> S_CPL_RDMA_ASYNC_EVENT_INDEX) & M_CPL_RDMA_ASYNC_EVENT_INDEX)
3307 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
3308 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
3312 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
3313 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
3316 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX)
3319 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
3320 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
3325 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
3326 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
3330 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
3331 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
3334 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
3335 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
3361 #define V_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \
3362 ((x) << S_CPL_T7_SMT_WRITE_REQ_NOREPLY)
3363 #define G_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \
3364 (((x) >> S_CPL_T7_SMT_WRITE_REQ_NOREPLY) & M_CPL_T7_SMT_WRITE_REQ_NOREPLY)
3366 V_CPL_T7_SMT_WRITE_REQ_NOREPLY(1U)
3370 #define V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \
3371 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGINSERT)
3372 #define G_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \
3373 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) & \
3376 V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(1U)
3380 #define V_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \
3381 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGTYPE)
3382 #define G_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \
3383 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) & M_CPL_T7_SMT_WRITE_REQ_TAGTYPE)
3387 #define V_CPL_T7_SMT_WRITE_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_INDEX)
3388 #define G_CPL_T7_SMT_WRITE_REQ_INDEX(x) \
3389 (((x) >> S_CPL_T7_SMT_WRITE_REQ_INDEX) & M_CPL_T7_SMT_WRITE_REQ_INDEX)
3393 #define V_CPL_T7_SMT_WRITE_REQ_OVLAN(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_OVLAN)
3394 #define G_CPL_T7_SMT_WRITE_REQ_OVLAN(x) \
3395 (((x) >> S_CPL_T7_SMT_WRITE_REQ_OVLAN) & M_CPL_T7_SMT_WRITE_REQ_OVLAN)
3399 #define V_CPL_T7_SMT_WRITE_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_IPSEC)
3400 #define G_CPL_T7_SMT_WRITE_REQ_IPSEC(x) \
3401 (((x) >> S_CPL_T7_SMT_WRITE_REQ_IPSEC) & M_CPL_T7_SMT_WRITE_REQ_IPSEC)
3402 #define F_CPL_T7_SMT_WRITE_REQ_IPSEC V_CPL_T7_SMT_WRITE_REQ_IPSEC(1U)
3406 #define V_CPL_T7_SMT_WRITE_REQ_MTU(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_MTU)
3407 #define G_CPL_T7_SMT_WRITE_REQ_MTU(x) \
3408 (((x) >> S_CPL_T7_SMT_WRITE_REQ_MTU) & M_CPL_T7_SMT_WRITE_REQ_MTU)
3412 #define V_CPL_T7_SMT_WRITE_REQ_PFVF(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_PFVF)
3413 #define G_CPL_T7_SMT_WRITE_REQ_PFVF(x) \
3414 (((x) >> S_CPL_T7_SMT_WRITE_REQ_PFVF) & M_CPL_T7_SMT_WRITE_REQ_PFVF)
3418 #define V_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \
3419 ((x) << S_CPL_T7_SMT_WRITE_REQ_SMAC_HI)
3420 #define G_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \
3421 (((x) >> S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) & M_CPL_T7_SMT_WRITE_REQ_SMAC_HI)
3431 #define V_CPL_T7_SMT_READ_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_READ_REQ_INDEX)
3432 #define G_CPL_T7_SMT_READ_REQ_INDEX(x) \
3433 (((x) >> S_CPL_SMT_READ_REQ_INDEX) & M_CPL_T7_SMT_READ_REQ_INDEX)
3437 #define V_CPL_T7_SMT_READ_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_READ_REQ_IPSEC)
3438 #define G_CPL_T7_SMT_READ_REQ_IPSEC(x) \
3439 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSEC) & M_CPL_T7_SMT_READ_REQ_IPSEC)
3440 #define F_CPL_T7_SMT_READ_REQ_IPSEC V_CPL_T7_SMT_READ_REQ_IPSEC(1U)
3444 #define V_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \
3445 ((x) << S_CPL_T7_SMT_READ_REQ_IPSECIDX)
3446 #define G_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \
3447 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSECIDX) & M_CPL_T7_SMT_READ_REQ_IPSECIDX)
3476 __u8 tag_len:1;
3478 __u8 ins_enable:1;
3480 __u8 ins_enable:1;
3482 __u8 tag_len:1;
3493 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX)
3494 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX)
3497 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN)
3498 #define F_TAGW_LEN V_TAGW_LEN(1U)
3501 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE)
3502 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U)
3505 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL)
3506 #define F_TAGW_NORPL V_TAGW_NORPL(1U)
3519 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
3520 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
3548 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
3549 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
3553 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
3554 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
3558 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
3559 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
3563 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
3564 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
3568 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
3569 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
3573 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN)
3574 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN)
3578 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
3579 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
3592 #define V_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \
3593 ((x) << S_CPL_T7_PKT_NOTIFY_ETHHDRLEN)
3594 #define G_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \
3595 (((x) >> S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) & M_CPL_T7_PKT_NOTIFY_ETHHDRLEN)
3599 #define V_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) ((x) << S_CPL_T7_PKT_NOTIFY_IPHDRLEN)
3600 #define G_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) \
3601 (((x) >> S_CPL_T7_PKT_NOTIFY_IPHDRLEN) & M_CPL_T7_PKT_NOTIFY_IPHDRLEN)
3605 #define V_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \
3606 ((x) << S_CPL_T7_PKT_NOTIFY_TCPHDRLEN)
3607 #define G_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \
3608 (((x) >> S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) & M_CPL_T7_PKT_NOTIFY_TCPHDRLEN)
3612 #define V_CPL_T7_PKT_NOTIFY_INTERFACE(x) \
3613 ((x) << S_CPL_T7_PKT_NOTIFY_INTERFACE)
3614 #define G_CPL_T7_PKT_NOTIFY_INTERFACE(x) \
3615 (((x) >> S_CPL_T7_PKT_NOTIFY_INTERFACE) & M_CPL_T7_PKT_NOTIFY_INTERFACE)
3619 #define V_CPL_T7_PKT_NOTIFY_MACINDEX(x) ((x) << S_CPL_T7_PKT_NOTIFY_MACINDEX)
3620 #define G_CPL_T7_PKT_NOTIFY_MACINDEX(x) \
3621 (((x) >> S_CPL_T7_PKT_NOTIFY_MACINDEX) & M_CPL_T7_PKT_NOTIFY_MACINDEX)
3635 #define V_CPL_RDMA_CQE_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_RSSCTRL)
3636 #define G_CPL_RDMA_CQE_RSSCTRL(x) \
3637 (((x) >> S_CPL_RDMA_CQE_RSSCTRL) & M_CPL_RDMA_CQE_RSSCTRL)
3641 #define V_CPL_RDMA_CQE_CQID(x) ((x) << S_CPL_RDMA_CQE_CQID)
3642 #define G_CPL_RDMA_CQE_CQID(x) \
3643 (((x) >> S_CPL_RDMA_CQE_CQID) & M_CPL_RDMA_CQE_CQID)
3647 #define V_CPL_RDMA_CQE_TID(x) ((x) << S_CPL_RDMA_CQE_TID)
3648 #define G_CPL_RDMA_CQE_TID(x) \
3649 (((x) >> S_CPL_RDMA_CQE_TID) & M_CPL_RDMA_CQE_TID)
3653 #define V_CPL_RDMA_CQE_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_FLITCNT)
3654 #define G_CPL_RDMA_CQE_FLITCNT(x) \
3655 (((x) >> S_CPL_RDMA_CQE_FLITCNT) & M_CPL_RDMA_CQE_FLITCNT)
3659 #define V_CPL_RDMA_CQE_QPID(x) ((x) << S_CPL_RDMA_CQE_QPID)
3660 #define G_CPL_RDMA_CQE_QPID(x) \
3661 (((x) >> S_CPL_RDMA_CQE_QPID) & M_CPL_RDMA_CQE_QPID)
3665 #define V_CPL_RDMA_CQE_GENERATION_BIT(x) \
3666 ((x) << S_CPL_RDMA_CQE_GENERATION_BIT)
3667 #define G_CPL_RDMA_CQE_GENERATION_BIT(x) \
3668 (((x) >> S_CPL_RDMA_CQE_GENERATION_BIT) & M_CPL_RDMA_CQE_GENERATION_BIT)
3669 #define F_CPL_RDMA_CQE_GENERATION_BIT V_CPL_RDMA_CQE_GENERATION_BIT(1U)
3673 #define V_CPL_RDMA_CQE_STATUS(x) ((x) << S_CPL_RDMA_CQE_STATUS)
3674 #define G_CPL_RDMA_CQE_STATUS(x) \
3675 (((x) >> S_CPL_RDMA_CQE_STATUS) & M_CPL_RDMA_CQE_STATUS)
3679 #define V_CPL_RDMA_CQE_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_CQE_TYPE)
3680 #define G_CPL_RDMA_CQE_CQE_TYPE(x) \
3681 (((x) >> S_CPL_RDMA_CQE_CQE_TYPE) & M_CPL_RDMA_CQE_CQE_TYPE)
3682 #define F_CPL_RDMA_CQE_CQE_TYPE V_CPL_RDMA_CQE_CQE_TYPE(1U)
3686 #define V_CPL_RDMA_CQE_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_WR_TYPE)
3687 #define G_CPL_RDMA_CQE_WR_TYPE(x) \
3688 (((x) >> S_CPL_RDMA_CQE_WR_TYPE) & M_CPL_RDMA_CQE_WR_TYPE)
3704 #define V_CPL_RDMA_CQE_SRQ_OPCODE(x) ((x) << S_CPL_RDMA_CQE_SRQ_OPCODE)
3705 #define G_CPL_RDMA_CQE_SRQ_OPCODE(x) \
3706 (((x) >> S_CPL_RDMA_CQE_SRQ_OPCODE) & M_CPL_RDMA_CQE_SRQ_OPCODE)
3710 #define V_CPL_RDMA_CQE_SRQ_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_SRQ_RSSCTRL)
3711 #define G_CPL_RDMA_CQE_SRQ_RSSCTRL(x) \
3712 (((x) >> S_CPL_RDMA_CQE_SRQ_RSSCTRL) & M_CPL_RDMA_CQE_SRQ_RSSCTRL)
3716 #define V_CPL_RDMA_CQE_SRQ_CQID(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQID)
3717 #define G_CPL_RDMA_CQE_SRQ_CQID(x) \
3718 (((x) >> S_CPL_RDMA_CQE_SRQ_CQID) & M_CPL_RDMA_CQE_SRQ_CQID)
3722 #define V_CPL_RDMA_CQE_SRQ_TID(x) ((x) << S_CPL_RDMA_CQE_SRQ_TID)
3723 #define G_CPL_RDMA_CQE_SRQ_TID(x) \
3724 (((x) >> S_CPL_RDMA_CQE_SRQ_TID) & M_CPL_RDMA_CQE_SRQ_TID)
3728 #define V_CPL_RDMA_CQE_SRQ_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_SRQ_FLITCNT)
3729 #define G_CPL_RDMA_CQE_SRQ_FLITCNT(x) \
3730 (((x) >> S_CPL_RDMA_CQE_SRQ_FLITCNT) & M_CPL_RDMA_CQE_SRQ_FLITCNT)
3734 #define V_CPL_RDMA_CQE_SRQ_QPID(x) ((x) << S_CPL_RDMA_CQE_SRQ_QPID)
3735 #define G_CPL_RDMA_CQE_SRQ_QPID(x) \
3736 (((x) >> S_CPL_RDMA_CQE_SRQ_QPID) & M_CPL_RDMA_CQE_SRQ_QPID)
3740 #define V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \
3741 ((x) << S_CPL_RDMA_CQE_SRQ_GENERATION_BIT)
3742 #define G_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \
3743 (((x) >> S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) & \
3746 V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(1U)
3750 #define V_CPL_RDMA_CQE_SRQ_STATUS(x) ((x) << S_CPL_RDMA_CQE_SRQ_STATUS)
3751 #define G_CPL_RDMA_CQE_SRQ_STATUS(x) \
3752 (((x) >> S_CPL_RDMA_CQE_SRQ_STATUS) & M_CPL_RDMA_CQE_SRQ_STATUS)
3756 #define V_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQE_TYPE)
3757 #define G_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) \
3758 (((x) >> S_CPL_RDMA_CQE_SRQ_CQE_TYPE) & M_CPL_RDMA_CQE_SRQ_CQE_TYPE)
3759 #define F_CPL_RDMA_CQE_SRQ_CQE_TYPE V_CPL_RDMA_CQE_SRQ_CQE_TYPE(1U)
3763 #define V_CPL_RDMA_CQE_SRQ_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_WR_TYPE)
3764 #define G_CPL_RDMA_CQE_SRQ_WR_TYPE(x) \
3765 (((x) >> S_CPL_RDMA_CQE_SRQ_WR_TYPE) & M_CPL_RDMA_CQE_SRQ_WR_TYPE)
3779 #define V_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \
3780 ((x) << S_CPL_RDMA_CQE_READ_RSP_RSSCTRL)
3781 #define G_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \
3782 (((x) >> S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) & \
3787 #define V_CPL_RDMA_CQE_READ_RSP_CQID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_CQID)
3788 #define G_CPL_RDMA_CQE_READ_RSP_CQID(x) \
3789 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQID) & M_CPL_RDMA_CQE_READ_RSP_CQID)
3793 #define V_CPL_RDMA_CQE_READ_RSP_TID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_TID)
3794 #define G_CPL_RDMA_CQE_READ_RSP_TID(x) \
3795 (((x) >> S_CPL_RDMA_CQE_READ_RSP_TID) & M_CPL_RDMA_CQE_READ_RSP_TID)
3799 #define V_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \
3800 ((x) << S_CPL_RDMA_CQE_READ_RSP_FLITCNT)
3801 #define G_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \
3802 (((x) >> S_CPL_RDMA_CQE_READ_RSP_FLITCNT) & \
3807 #define V_CPL_RDMA_CQE_READ_RSP_QPID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_QPID)
3808 #define G_CPL_RDMA_CQE_READ_RSP_QPID(x) \
3809 (((x) >> S_CPL_RDMA_CQE_READ_RSP_QPID) & M_CPL_RDMA_CQE_READ_RSP_QPID)
3813 #define V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \
3814 ((x) << S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT)
3815 #define G_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \
3816 (((x) >> S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) & \
3819 V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(1U)
3823 #define V_CPL_RDMA_CQE_READ_RSP_STATUS(x) \
3824 ((x) << S_CPL_RDMA_CQE_READ_RSP_STATUS)
3825 #define G_CPL_RDMA_CQE_READ_RSP_STATUS(x) \
3826 (((x) >> S_CPL_RDMA_CQE_READ_RSP_STATUS) & M_CPL_RDMA_CQE_READ_RSP_STATUS)
3830 #define V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \
3831 ((x) << S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE)
3832 #define G_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \
3833 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) & \
3835 #define F_CPL_RDMA_CQE_READ_RSP_CQE_TYPE V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(1U)
3839 #define V_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \
3840 ((x) << S_CPL_RDMA_CQE_READ_RSP_WR_TYPE)
3841 #define G_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \
3842 (((x) >> S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) & \
3857 #define V_CPL_RDMA_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_ERR_RSSCTRL)
3858 #define G_CPL_RDMA_CQE_ERR_RSSCTRL(x) \
3859 (((x) >> S_CPL_RDMA_CQE_ERR_RSSCTRL) & M_CPL_RDMA_CQE_ERR_RSSCTRL)
3863 #define V_CPL_RDMA_CQE_ERR_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_CQID)
3864 #define G_CPL_RDMA_CQE_ERR_CQID(x) \
3865 (((x) >> S_CPL_RDMA_CQE_ERR_CQID) & M_CPL_RDMA_CQE_ERR_CQID)
3869 #define V_CPL_RDMA_CQE_ERR_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_TID)
3870 #define G_CPL_RDMA_CQE_ERR_TID(x) \
3871 (((x) >> S_CPL_RDMA_CQE_ERR_TID) & M_CPL_RDMA_CQE_ERR_TID)
3875 #define V_CPL_RDMA_CQE_ERR_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_ERR_FLITCNT)
3876 #define G_CPL_RDMA_CQE_ERR_FLITCNT(x) \
3877 (((x) >> S_CPL_RDMA_CQE_ERR_FLITCNT) & M_CPL_RDMA_CQE_ERR_FLITCNT)
3881 #define V_CPL_RDMA_CQE_ERR_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_QPID)
3882 #define G_CPL_RDMA_CQE_ERR_QPID(x) \
3883 (((x) >> S_CPL_RDMA_CQE_ERR_QPID) & M_CPL_RDMA_CQE_ERR_QPID)
3887 #define V_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \
3888 ((x) << S_CPL_RDMA_CQE_ERR_GENERATION_BIT)
3889 #define G_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \
3890 (((x) >> S_CPL_RDMA_CQE_ERR_GENERATION_BIT) & \
3893 V_CPL_RDMA_CQE_ERR_GENERATION_BIT(1U)
3897 #define V_CPL_RDMA_CQE_ERR_STATUS(x) ((x) << S_CPL_RDMA_CQE_ERR_STATUS)
3898 #define G_CPL_RDMA_CQE_ERR_STATUS(x) \
3899 (((x) >> S_CPL_RDMA_CQE_ERR_STATUS) & M_CPL_RDMA_CQE_ERR_STATUS)
3903 #define V_CPL_RDMA_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_CQE_TYPE)
3904 #define G_CPL_RDMA_CQE_ERR_CQE_TYPE(x) \
3905 (((x) >> S_CPL_RDMA_CQE_ERR_CQE_TYPE) & M_CPL_RDMA_CQE_ERR_CQE_TYPE)
3906 #define F_CPL_RDMA_CQE_ERR_CQE_TYPE V_CPL_RDMA_CQE_ERR_CQE_TYPE(1U)
3910 #define V_CPL_RDMA_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_WR_TYPE)
3911 #define G_CPL_RDMA_CQE_ERR_WR_TYPE(x) \
3912 (((x) >> S_CPL_RDMA_CQE_ERR_WR_TYPE) & M_CPL_RDMA_CQE_ERR_WR_TYPE)
3923 #define V_CPL_RDMA_READ_REQ_SRQ(x) ((x) << S_CPL_RDMA_READ_REQ_SRQ)
3924 #define G_CPL_RDMA_READ_REQ_SRQ(x) \
3925 (((x) >> S_CPL_RDMA_READ_REQ_SRQ) & M_CPL_RDMA_READ_REQ_SRQ)
3943 #define V_CPL_RDMA_ATOMIC_REQ_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_OPCODE)
3944 #define G_CPL_RDMA_ATOMIC_REQ_OPCODE(x) \
3945 (((x) >> S_CPL_RDMA_ATOMIC_REQ_OPCODE) & M_CPL_RDMA_ATOMIC_REQ_OPCODE)
3949 #define V_CPL_RDMA_ATOMIC_REQ_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_SRQ)
3950 #define G_CPL_RDMA_ATOMIC_REQ_SRQ(x) \
3951 (((x) >> S_CPL_RDMA_ATOMIC_REQ_SRQ) & M_CPL_RDMA_ATOMIC_REQ_SRQ)
3962 #define V_CPL_RDMA_ATOMIC_RPL_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_OPCODE)
3963 #define G_CPL_RDMA_ATOMIC_RPL_OPCODE(x) \
3964 (((x) >> S_CPL_RDMA_ATOMIC_RPL_OPCODE) & M_CPL_RDMA_ATOMIC_RPL_OPCODE)
3968 #define V_CPL_RDMA_ATOMIC_RPL_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_SRQ)
3969 #define G_CPL_RDMA_ATOMIC_RPL_SRQ(x) \
3970 (((x) >> S_CPL_RDMA_ATOMIC_RPL_SRQ) & M_CPL_RDMA_ATOMIC_RPL_SRQ)
3996 #define V_CPL_RDMA_INV_REQ_CQID(x) ((x) << S_CPL_RDMA_INV_REQ_CQID)
3997 #define G_CPL_RDMA_INV_REQ_CQID(x) \
3998 (((x) >> S_CPL_RDMA_INV_REQ_CQID) & M_CPL_RDMA_INV_REQ_CQID)
4002 #define V_CPL_RDMA_INV_REQ_PDID_HI(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_HI)
4003 #define G_CPL_RDMA_INV_REQ_PDID_HI(x) \
4004 (((x) >> S_CPL_RDMA_INV_REQ_PDID_HI) & M_CPL_RDMA_INV_REQ_PDID_HI)
4008 #define V_CPL_RDMA_INV_REQ_PDID_LO(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_LO)
4009 #define G_CPL_RDMA_INV_REQ_PDID_LO(x) \
4010 (((x) >> S_CPL_RDMA_INV_REQ_PDID_LO) & M_CPL_RDMA_INV_REQ_PDID_LO)
4014 #define V_CPL_RDMA_INV_REQ_QPID(x) ((x) << S_CPL_RDMA_INV_REQ_QPID)
4015 #define G_CPL_RDMA_INV_REQ_QPID(x) \
4016 (((x) >> S_CPL_RDMA_INV_REQ_QPID) & M_CPL_RDMA_INV_REQ_QPID)
4034 #define V_CPL_RDMA_CQE_EXT_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_EXT_RSSCTRL)
4035 #define G_CPL_RDMA_CQE_EXT_RSSCTRL(x) \
4036 (((x) >> S_CPL_RDMA_CQE_EXT_RSSCTRL) & M_CPL_RDMA_CQE_EXT_RSSCTRL)
4040 #define V_CPL_RDMA_CQE_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_EXT_CQID)
4041 #define G_CPL_RDMA_CQE_EXT_CQID(x) \
4042 (((x) >> S_CPL_RDMA_CQE_EXT_CQID) & M_CPL_RDMA_CQE_EXT_CQID)
4046 #define V_CPL_RDMA_CQE_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_EXT_TID)
4047 #define G_CPL_RDMA_CQE_EXT_TID(x) \
4048 (((x) >> S_CPL_RDMA_CQE_EXT_TID) & M_CPL_RDMA_CQE_EXT_TID)
4052 #define V_CPL_RDMA_CQE_EXT_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_EXT_FLITCNT)
4053 #define G_CPL_RDMA_CQE_EXT_FLITCNT(x) \
4054 (((x) >> S_CPL_RDMA_CQE_EXT_FLITCNT) & M_CPL_RDMA_CQE_EXT_FLITCNT)
4058 #define V_CPL_RDMA_CQE_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_EXT_QPID)
4059 #define G_CPL_RDMA_CQE_EXT_QPID(x) \
4060 (((x) >> S_CPL_RDMA_CQE_EXT_QPID) & M_CPL_RDMA_CQE_EXT_QPID)
4064 #define V_CPL_RDMA_CQE_EXT_EXTMODE(x) ((x) << S_CPL_RDMA_CQE_EXT_EXTMODE)
4065 #define G_CPL_RDMA_CQE_EXT_EXTMODE(x) \
4066 (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE)
4067 #define F_CPL_RDMA_CQE_EXT_EXTMODE V_CPL_RDMA_CQE_EXT_EXTMODE(1U)
4071 #define V_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \
4072 ((x) << S_CPL_RDMA_CQE_EXT_GENERATION_BIT)
4073 #define G_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \
4074 (((x) >> S_CPL_RDMA_CQE_EXT_GENERATION_BIT) & \
4077 V_CPL_RDMA_CQE_EXT_GENERATION_BIT(1U)
4081 #define V_CPL_RDMA_CQE_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_EXT_STATUS)
4082 #define G_CPL_RDMA_CQE_EXT_STATUS(x) \
4083 (((x) >> S_CPL_RDMA_CQE_EXT_STATUS) & M_CPL_RDMA_CQE_EXT_STATUS)
4087 #define V_CPL_RDMA_CQE_EXT_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_CQE_TYPE)
4088 #define G_CPL_RDMA_CQE_EXT_CQE_TYPE(x) \
4089 (((x) >> S_CPL_RDMA_CQE_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_EXT_CQE_TYPE)
4090 #define F_CPL_RDMA_CQE_EXT_CQE_TYPE V_CPL_RDMA_CQE_EXT_CQE_TYPE(1U)
4094 #define V_CPL_RDMA_CQE_EXT_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE)
4095 #define G_CPL_RDMA_CQE_EXT_WR_TYPE(x) \
4096 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE) & M_CPL_RDMA_CQE_EXT_WR_TYPE)
4100 #define V_CPL_RDMA_CQE_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_EXT_SE)
4101 #define G_CPL_RDMA_CQE_EXT_SE(x) \
4102 (((x) >> S_CPL_RDMA_CQE_EXT_SE) & M_CPL_RDMA_CQE_EXT_SE)
4103 #define F_CPL_RDMA_CQE_EXT_SE V_CPL_RDMA_CQE_EXT_SE(1U)
4107 #define V_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \
4108 ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT)
4109 #define G_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \
4110 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) & M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT)
4114 #define V_CPL_RDMA_CQE_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_EXT_SRQ)
4115 #define G_CPL_RDMA_CQE_EXT_SRQ(x) \
4116 (((x) >> S_CPL_RDMA_CQE_EXT_SRQ) & M_CPL_RDMA_CQE_EXT_SRQ)
4134 #define V_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \
4135 ((x) << S_CPL_RDMA_CQE_FW_EXT_RSSCTRL)
4136 #define G_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \
4137 (((x) >> S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) & M_CPL_RDMA_CQE_FW_EXT_RSSCTRL)
4141 #define V_CPL_RDMA_CQE_FW_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_CQID)
4142 #define G_CPL_RDMA_CQE_FW_EXT_CQID(x) \
4143 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQID) & M_CPL_RDMA_CQE_FW_EXT_CQID)
4147 #define V_CPL_RDMA_CQE_FW_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_TID)
4148 #define G_CPL_RDMA_CQE_FW_EXT_TID(x) \
4149 (((x) >> S_CPL_RDMA_CQE_FW_EXT_TID) & M_CPL_RDMA_CQE_FW_EXT_TID)
4153 #define V_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \
4154 ((x) << S_CPL_RDMA_CQE_FW_EXT_FLITCNT)
4155 #define G_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \
4156 (((x) >> S_CPL_RDMA_CQE_FW_EXT_FLITCNT) & M_CPL_RDMA_CQE_FW_EXT_FLITCNT)
4160 #define V_CPL_RDMA_CQE_FW_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_QPID)
4161 #define G_CPL_RDMA_CQE_FW_EXT_QPID(x) \
4162 (((x) >> S_CPL_RDMA_CQE_FW_EXT_QPID) & M_CPL_RDMA_CQE_FW_EXT_QPID)
4166 #define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \
4167 ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE)
4168 #define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \
4169 (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE)
4170 #define F_CPL_RDMA_CQE_FW_EXT_EXTMODE V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U)
4174 #define V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \
4175 ((x) << S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT)
4176 #define G_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \
4177 (((x) >> S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) & \
4180 V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(1U)
4184 #define V_CPL_RDMA_CQE_FW_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_STATUS)
4185 #define G_CPL_RDMA_CQE_FW_EXT_STATUS(x) \
4186 (((x) >> S_CPL_RDMA_CQE_FW_EXT_STATUS) & M_CPL_RDMA_CQE_FW_EXT_STATUS)
4190 #define V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \
4191 ((x) << S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE)
4192 #define G_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \
4193 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE)
4194 #define F_CPL_RDMA_CQE_FW_EXT_CQE_TYPE V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(1U)
4198 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \
4199 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE)
4200 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \
4201 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) & M_CPL_RDMA_CQE_FW_EXT_WR_TYPE)
4205 #define V_CPL_RDMA_CQE_FW_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SE)
4206 #define G_CPL_RDMA_CQE_FW_EXT_SE(x) \
4207 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SE) & M_CPL_RDMA_CQE_FW_EXT_SE)
4208 #define F_CPL_RDMA_CQE_FW_EXT_SE V_CPL_RDMA_CQE_FW_EXT_SE(1U)
4212 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \
4213 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT)
4214 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \
4215 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) & \
4220 #define V_CPL_RDMA_CQE_FW_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SRQ)
4221 #define G_CPL_RDMA_CQE_FW_EXT_SRQ(x) \
4222 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SRQ) & M_CPL_RDMA_CQE_FW_EXT_SRQ)
4240 #define V_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \
4241 ((x) << S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL)
4242 #define G_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \
4243 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) & M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL)
4247 #define V_CPL_RDMA_CQE_ERR_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQID)
4248 #define G_CPL_RDMA_CQE_ERR_EXT_CQID(x) \
4249 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQID) & M_CPL_RDMA_CQE_ERR_EXT_CQID)
4253 #define V_CPL_RDMA_CQE_ERR_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_TID)
4254 #define G_CPL_RDMA_CQE_ERR_EXT_TID(x) \
4255 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_TID) & M_CPL_RDMA_CQE_ERR_EXT_TID)
4259 #define V_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \
4260 ((x) << S_CPL_RDMA_CQE_ERR_EXT_FLITCNT)
4261 #define G_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \
4262 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) & M_CPL_RDMA_CQE_ERR_EXT_FLITCNT)
4266 #define V_CPL_RDMA_CQE_ERR_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_QPID)
4267 #define G_CPL_RDMA_CQE_ERR_EXT_QPID(x) \
4268 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_QPID) & M_CPL_RDMA_CQE_ERR_EXT_QPID)
4272 #define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \
4273 ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE)
4274 #define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \
4275 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE)
4276 #define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U)
4280 #define V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \
4281 ((x) << S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT)
4282 #define G_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \
4283 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) & \
4286 V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(1U)
4290 #define V_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \
4291 ((x) << S_CPL_RDMA_CQE_ERR_EXT_STATUS)
4292 #define G_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \
4293 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_STATUS) & M_CPL_RDMA_CQE_ERR_EXT_STATUS)
4297 #define V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \
4298 ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE)
4299 #define G_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \
4300 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) & \
4302 #define F_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(1U)
4306 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \
4307 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE)
4308 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \
4309 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) & M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE)
4313 #define V_CPL_RDMA_CQE_ERR_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SE)
4314 #define G_CPL_RDMA_CQE_ERR_EXT_SE(x) \
4315 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SE) & M_CPL_RDMA_CQE_ERR_EXT_SE)
4316 #define F_CPL_RDMA_CQE_ERR_EXT_SE V_CPL_RDMA_CQE_ERR_EXT_SE(1U)
4320 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \
4321 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT)
4322 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \
4323 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) & \
4328 #define V_CPL_RDMA_CQE_ERR_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SRQ)
4329 #define G_CPL_RDMA_CQE_ERR_EXT_SRQ(x) \
4330 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SRQ) & M_CPL_RDMA_CQE_ERR_EXT_SRQ)
4346 #define V_LE_REQ_RXCHANNEL(x) ((x) << S_LE_REQ_RXCHANNEL)
4347 #define G_LE_REQ_RXCHANNEL(x) \
4348 (((x) >> S_LE_REQ_RXCHANNEL) & M_LE_REQ_RXCHANNEL)
4349 #define F_LE_REQ_RXCHANNEL V_LE_REQ_RXCHANNEL(1U)
4352 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
4353 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
4358 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
4359 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
4363 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
4364 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
4367 #define V_LE_MORE(x) ((x) << S_LE_MORE)
4368 #define F_LE_MORE V_LE_MORE(1U)
4372 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
4373 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
4377 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
4378 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
4392 #define V_CPL_T7_SET_LE_REQ_INDEX(x) ((x) << S_CPL_T7_SET_LE_REQ_INDEX)
4393 #define G_CPL_T7_SET_LE_REQ_INDEX(x) \
4394 (((x) >> S_CPL_T7_SET_LE_REQ_INDEX) & M_CPL_T7_SET_LE_REQ_INDEX)
4398 #define V_CPL_T7_SET_LE_REQ_NOREPLY(x) ((x) << S_CPL_T7_SET_LE_REQ_NOREPLY)
4399 #define G_CPL_T7_SET_LE_REQ_NOREPLY(x) \
4400 (((x) >> S_CPL_T7_SET_LE_REQ_NOREPLY) & M_CPL_T7_SET_LE_REQ_NOREPLY)
4401 #define F_CPL_T7_SET_LE_REQ_NOREPLY V_CPL_T7_SET_LE_REQ_NOREPLY(1U)
4405 #define V_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \
4406 ((x) << S_CPL_T7_SET_LE_REQ_RXCHANNEL)
4407 #define G_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \
4408 (((x) >> S_CPL_T7_SET_LE_REQ_RXCHANNEL) & M_CPL_T7_SET_LE_REQ_RXCHANNEL)
4412 #define V_CPL_T7_SET_LE_REQ_QUEUE(x) ((x) << S_CPL_T7_SET_LE_REQ_QUEUE)
4413 #define G_CPL_T7_SET_LE_REQ_QUEUE(x) \
4414 (((x) >> S_CPL_T7_SET_LE_REQ_QUEUE) & M_CPL_T7_SET_LE_REQ_QUEUE)
4418 #define V_CPL_T7_SET_LE_REQ_REQCMD(x) ((x) << S_CPL_T7_SET_LE_REQ_REQCMD)
4419 #define G_CPL_T7_SET_LE_REQ_REQCMD(x) \
4420 (((x) >> S_CPL_T7_SET_LE_REQ_REQCMD) & M_CPL_T7_SET_LE_REQ_REQCMD)
4424 #define V_CPL_T7_SET_LE_REQ_REQSIZE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQSIZE)
4425 #define G_CPL_T7_SET_LE_REQ_REQSIZE(x) \
4426 (((x) >> S_CPL_T7_SET_LE_REQ_REQSIZE) & M_CPL_T7_SET_LE_REQ_REQSIZE)
4430 #define V_CPL_T7_SET_LE_REQ_MORE(x) ((x) << S_CPL_T7_SET_LE_REQ_MORE)
4431 #define G_CPL_T7_SET_LE_REQ_MORE(x) \
4432 (((x) >> S_CPL_T7_SET_LE_REQ_MORE) & M_CPL_T7_SET_LE_REQ_MORE)
4433 #define F_CPL_T7_SET_LE_REQ_MORE V_CPL_T7_SET_LE_REQ_MORE(1U)
4437 #define V_CPL_T7_SET_LE_REQ_OFFSET(x) ((x) << S_CPL_T7_SET_LE_REQ_OFFSET)
4438 #define G_CPL_T7_SET_LE_REQ_OFFSET(x) \
4439 (((x) >> S_CPL_T7_SET_LE_REQ_OFFSET) & M_CPL_T7_SET_LE_REQ_OFFSET)
4443 #define V_CPL_T7_SET_LE_REQ_REQTYPE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQTYPE)
4444 #define G_CPL_T7_SET_LE_REQ_REQTYPE(x) \
4445 (((x) >> S_CPL_T7_SET_LE_REQ_REQTYPE) & M_CPL_T7_SET_LE_REQ_REQTYPE)
4446 #define F_CPL_T7_SET_LE_REQ_REQTYPE V_CPL_T7_SET_LE_REQ_REQTYPE(1U)
4450 #define V_CPL_T7_SET_LE_REQ_CHANNEL(x) ((x) << S_CPL_T7_SET_LE_REQ_CHANNEL)
4451 #define G_CPL_T7_SET_LE_REQ_CHANNEL(x) \
4452 (((x) >> S_CPL_T7_SET_LE_REQ_CHANNEL) & M_CPL_T7_SET_LE_REQ_CHANNEL)
4465 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
4466 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
4470 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
4471 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
4474 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
4475 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
4487 #define V_AUTOEQU(x) ((x) << S_AUTOEQU)
4488 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU)
4492 #define V_EGR_QID(x) ((x) << S_EGR_QID)
4493 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
4498 FW_TYPE_WR_RPL = 1,
4567 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE)
4568 #define G_CPL_FW4_ACK_OPCODE(x) \
4569 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE)
4573 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID)
4574 #define G_CPL_FW4_ACK_FLOWID(x) \
4575 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID)
4579 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR)
4580 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR)
4584 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL)
4585 #define G_CPL_FW4_ACK_SEQVAL(x) \
4586 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL)
4587 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U)
4638 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
4642 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
4645 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
4646 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
4683 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
4684 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE)
4701 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
4702 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
4705 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
4706 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
4709 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
4710 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
4714 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID)
4719 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
4722 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
4723 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
4728 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
4732 #define V_T7_ULP_MEMIO_DATA_LEN(x) ((x) << S_T7_ULP_MEMIO_DATA_LEN)
4750 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY)
4751 #define G_ULP_TXPKT_DATAMODIFY(x) \
4752 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_)
4753 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U)
4757 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID)
4758 #define G_ULP_TXPKT_CHANNELID(x) \
4759 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID)
4760 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U)
4764 #define V_T7_ULP_TXPKT_CHANNELID(x) ((x) << S_T7_ULP_TXPKT_CHANNELID)
4765 #define G_T7_ULP_TXPKT_CHANNELID(x) \
4766 (((x) >> S_T7_ULP_TXPKT_CHANNELID) & M_T7_ULP_TXPKT_CHANNELID)
4767 #define F_T7_ULP_TXPKT_CHANNELID V_T7_ULP_TXPKT_CHANNELID(1U)
4772 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
4776 #define V_ULP_TXPKT_CMDMORE(x) ((x) << S_ULP_TXPKT_CMDMORE)
4777 #define G_ULP_TXPKT_CMDMORE(x) \
4778 (((x) >> S_ULP_TXPKT_CMDMORE) & M_ULP_TXPKT_CMDMORE)
4779 #define F_ULP_TXPKT_CMDMORE V_ULP_TXPKT_CMDMORE(1U)
4783 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
4786 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
4787 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
4813 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE)
4814 #define G_CPL_TX_TNL_LSO_OPCODE(x) \
4815 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE)
4819 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST)
4820 #define G_CPL_TX_TNL_LSO_FIRST(x) \
4821 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST)
4822 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U)
4826 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST)
4827 #define G_CPL_TX_TNL_LSO_LAST(x) \
4828 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST)
4829 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U)
4833 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
4834 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
4835 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \
4836 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT)
4837 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U)
4841 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT)
4842 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \
4843 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT)
4844 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U)
4848 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
4849 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT)
4850 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \
4851 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT)
4855 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT)
4856 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \
4857 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT)
4861 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT)
4862 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \
4863 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT)
4864 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U)
4868 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT)
4869 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \
4870 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT)
4871 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U)
4873 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1
4875 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT)
4876 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \
4877 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT)
4878 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U)
4882 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
4883 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT)
4884 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \
4885 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT)
4886 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U)
4890 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
4891 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT)
4892 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \
4893 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT)
4894 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U)
4898 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
4899 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT)
4900 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \
4901 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT)
4902 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U)
4906 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE)
4907 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \
4908 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE)
4912 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN)
4913 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \
4914 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN)
4918 #define V_CPL_TX_TNL_LSO_IPSECEN(x) ((x) << S_CPL_TX_TNL_LSO_IPSECEN)
4919 #define G_CPL_TX_TNL_LSO_IPSECEN(x) \
4920 (((x) >> S_CPL_TX_TNL_LSO_IPSECEN) & M_CPL_TX_TNL_LSO_IPSECEN)
4921 #define F_CPL_TX_TNL_LSO_IPSECEN V_CPL_TX_TNL_LSO_IPSECEN(1U)
4925 #define V_CPL_TX_TNL_LSO_ENCAPDIS(x) ((x) << S_CPL_TX_TNL_LSO_ENCAPDIS)
4926 #define G_CPL_TX_TNL_LSO_ENCAPDIS(x) \
4927 (((x) >> S_CPL_TX_TNL_LSO_ENCAPDIS) & M_CPL_TX_TNL_LSO_ENCAPDIS)
4928 #define F_CPL_TX_TNL_LSO_ENCAPDIS V_CPL_TX_TNL_LSO_ENCAPDIS(1U)
4932 #define V_CPL_TX_TNL_LSO_IPSECMODE(x) ((x) << S_CPL_TX_TNL_LSO_IPSECMODE)
4933 #define G_CPL_TX_TNL_LSO_IPSECMODE(x) \
4934 (((x) >> S_CPL_TX_TNL_LSO_IPSECMODE) & M_CPL_TX_TNL_LSO_IPSECMODE)
4935 #define F_CPL_TX_TNL_LSO_IPSECMODE V_CPL_TX_TNL_LSO_IPSECMODE(1U)
4939 #define V_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \
4940 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPV6)
4941 #define G_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \
4942 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPV6) & M_CPL_TX_TNL_LSO_IPSECTNLIPV6)
4943 #define F_CPL_TX_TNL_LSO_IPSECTNLIPV6 V_CPL_TX_TNL_LSO_IPSECTNLIPV6(1U)
4947 #define V_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \
4948 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN)
4949 #define G_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \
4950 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) & \
4955 #define V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \
4956 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT)
4957 #define G_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \
4958 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) & \
4961 V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(1U)
4965 #define V_CPL_TX_TNL_LSO_ROCEV2(x) ((x) << S_CPL_TX_TNL_LSO_ROCEV2)
4966 #define G_CPL_TX_TNL_LSO_ROCEV2(x) \
4967 (((x) >> S_CPL_TX_TNL_LSO_ROCEV2) & M_CPL_TX_TNL_LSO_ROCEV2)
4968 #define F_CPL_TX_TNL_LSO_ROCEV2 V_CPL_TX_TNL_LSO_ROCEV2(1U)
4972 #define V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \
4973 ((x) << S_CPL_TX_TNL_LSO_UDPCHKUPDOUT)
4974 #define G_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \
4975 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) & M_CPL_TX_TNL_LSO_UDPCHKUPDOUT)
4976 #define F_CPL_TX_TNL_LSO_UDPCHKUPDOUT V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(1U)
4980 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW)
4981 #define G_CPL_TX_TNL_LSO_FLOW(x) \
4982 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW)
4983 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U)
4987 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6)
4988 #define G_CPL_TX_TNL_LSO_IPV6(x) \
4989 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6)
4990 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U)
4994 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
4995 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
4996 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
5000 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN)
5001 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \
5002 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN)
5006 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN)
5007 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \
5008 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN)
5012 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT)
5013 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \
5014 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT)
5015 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U)
5019 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX)
5020 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \
5021 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX)
5022 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U)
5026 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS)
5027 #define G_CPL_TX_TNL_LSO_MSS(x) \
5028 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS)
5032 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
5033 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET)
5034 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \
5035 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET)
5039 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE)
5040 #define G_CPL_TX_TNL_LSO_SIZE(x) \
5041 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE)
5050 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP)
5051 #define G_CPL_RX_MPS_PKT_OP(x) \
5052 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP)
5056 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE)
5057 #define G_CPL_RX_MPS_PKT_TYPE(x) \
5058 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
5062 #define V_CPL_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_RX_MPS_PKT_LENGTH)
5063 #define G_CPL_RX_MPS_PKT_LENGTH(x) \
5064 (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH)
5069 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0)
5070 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1)
5071 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2)
5072 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3)
5082 #define V_CPL_T7_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_T7_RX_MPS_PKT_TYPE)
5083 #define G_CPL_T7_RX_MPS_PKT_TYPE(x) \
5084 (((x) >> S_CPL_T7_RX_MPS_PKT_TYPE) & M_CPL_T7_RX_MPS_PKT_TYPE)
5088 #define V_CPL_T7_RX_MPS_PKT_INTERFACE(x) \
5089 ((x) << S_CPL_T7_RX_MPS_PKT_INTERFACE)
5090 #define G_CPL_T7_RX_MPS_PKT_INTERFACE(x) \
5091 (((x) >> S_CPL_T7_RX_MPS_PKT_INTERFACE) & M_CPL_T7_RX_MPS_PKT_INTERFACE)
5095 #define V_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \
5096 ((x) << S_CPL_T7_RX_MPS_PKT_TRUNCATED)
5097 #define G_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \
5098 (((x) >> S_CPL_T7_RX_MPS_PKT_TRUNCATED) & M_CPL_T7_RX_MPS_PKT_TRUNCATED)
5099 #define F_CPL_T7_RX_MPS_PKT_TRUNCATED V_CPL_T7_RX_MPS_PKT_TRUNCATED(1U)
5103 #define V_CPL_T7_RX_MPS_PKT_PKTERR(x) ((x) << S_CPL_T7_RX_MPS_PKT_PKTERR)
5104 #define G_CPL_T7_RX_MPS_PKT_PKTERR(x) \
5105 (((x) >> S_CPL_T7_RX_MPS_PKT_PKTERR) & M_CPL_T7_RX_MPS_PKT_PKTERR)
5106 #define F_CPL_T7_RX_MPS_PKT_PKTERR V_CPL_T7_RX_MPS_PKT_PKTERR(1U)
5110 #define V_CPL_T7_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_T7_RX_MPS_PKT_LENGTH)
5111 #define G_CPL_T7_RX_MPS_PKT_LENGTH(x) \
5112 (((x) >> S_CPL_T7_RX_MPS_PKT_LENGTH) & M_CPL_T7_RX_MPS_PKT_LENGTH)
5126 #define V_CPL_TX_TLS_PDU_DATATYPE(x) ((x) << S_CPL_TX_TLS_PDU_DATATYPE)
5127 #define G_CPL_TX_TLS_PDU_DATATYPE(x) \
5128 (((x) >> S_CPL_TX_TLS_PDU_DATATYPE) & M_CPL_TX_TLS_PDU_DATATYPE)
5132 #define V_CPL_TX_TLS_PDU_CPLLEN(x) ((x) << S_CPL_TX_TLS_PDU_CPLLEN)
5133 #define G_CPL_TX_TLS_PDU_CPLLEN(x) \
5134 (((x) >> S_CPL_TX_TLS_PDU_CPLLEN) & M_CPL_TX_TLS_PDU_CPLLEN)
5138 #define V_CPL_TX_TLS_PDU_PLDLEN(x) ((x) << S_CPL_TX_TLS_PDU_PLDLEN)
5139 #define G_CPL_TX_TLS_PDU_PLDLEN(x) \
5140 (((x) >> S_CPL_TX_TLS_PDU_PLDLEN) & M_CPL_TX_TLS_PDU_PLDLEN)
5144 #define V_CPL_TX_TLS_PDU_CUSTOMTYPE(x) ((x) << S_CPL_TX_TLS_PDU_CUSTOMTYPE)
5145 #define G_CPL_TX_TLS_PDU_CUSTOMTYPE(x) \
5146 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMTYPE) & M_CPL_TX_TLS_PDU_CUSTOMTYPE)
5150 #define V_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \
5151 ((x) << S_CPL_TX_TLS_PDU_CUSTOMPROTOVER)
5152 #define G_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \
5153 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) & \
5169 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE)
5170 #define G_CPL_TX_TLS_SFO_OPCODE(x) \
5171 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE)
5175 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE)
5176 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \
5177 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE)
5181 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN)
5182 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \
5183 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN)
5187 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN)
5188 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \
5189 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN)
5193 #define V_CPL_TX_TLS_SFO_PLDLEN(x) ((x) << S_CPL_TX_TLS_SFO_PLDLEN)
5194 #define G_CPL_TX_TLS_SFO_PLDLEN(x) \
5195 (((x) >> S_CPL_TX_TLS_SFO_PLDLEN) & M_CPL_TX_TLS_SFO_PLDLEN)
5199 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE)
5200 #define G_CPL_TX_TLS_SFO_TYPE(x) \
5201 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE)
5205 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER)
5206 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \
5207 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER)
5219 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE)
5220 #define G_CPL_TLS_DATA_OPCODE(x) \
5221 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE)
5225 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID)
5226 #define G_CPL_TLS_DATA_TID(x) \
5227 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID)
5231 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH)
5232 #define G_CPL_TLS_DATA_LENGTH(x) \
5233 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH)
5247 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE)
5248 #define G_CPL_RX_TLS_CMP_OPCODE(x) \
5249 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE)
5253 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID)
5254 #define G_CPL_RX_TLS_CMP_TID(x) \
5255 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID)
5259 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH)
5260 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \
5261 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH)
5265 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH)
5266 #define G_CPL_RX_TLS_CMP_LENGTH(x) \
5267 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH)
5271 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL)
5272 #define G_SCMD_SEQ_NO_CTRL(x) \
5273 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL)
5278 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT)
5279 #define G_SCMD_STATUS_PRESENT(x) \
5280 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT)
5281 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U)
5283 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic,
5287 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION)
5288 #define G_SCMD_PROTO_VERSION(x) \
5289 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION)
5291 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */
5294 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL)
5295 #define G_SCMD_ENC_DEC_CTRL(x) \
5296 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL)
5297 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U)
5302 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \
5303 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL)
5304 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \
5305 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL)
5306 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U)
5308 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR,
5312 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE)
5313 #define G_SCMD_CIPH_MODE(x) \
5314 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE)
5316 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256
5320 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE)
5321 #define G_SCMD_AUTH_MODE(x) \
5322 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE)
5324 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation
5329 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL)
5330 #define G_SCMD_HMAC_CTRL(x) \
5331 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL)
5336 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE)
5337 #define G_SCMD_IV_SIZE(x) \
5338 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE)
5343 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS)
5344 #define G_SCMD_NUM_IVS(x) \
5345 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS)
5354 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID)
5355 #define G_SCMD_ENB_DBGID(x) \
5356 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID)
5361 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL)
5362 #define G_SCMD_IV_GEN_CTRL(x) \
5363 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL)
5364 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U)
5369 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS)
5370 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS)
5375 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG)
5376 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG)
5381 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU)
5382 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU)
5387 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE)
5388 #define G_SCMD_KEY_CTX_INLINE(x) \
5389 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE)
5390 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U)
5392 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */
5395 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE)
5396 #define G_SCMD_TLS_FRAG_ENABLE(x) \
5397 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE)
5398 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U)
5405 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY)
5406 #define G_SCMD_MAC_ONLY(x) \
5407 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY)
5408 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U)
5415 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP)
5416 #define G_SCMD_AADIVDROP(x) \
5417 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP)
5418 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U)
5424 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN)
5425 #define G_SCMD_HDR_LEN(x) \
5426 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN)
5440 #define V_CPL_RX_PKT_IPSEC_OPCODE(x) ((x) << S_CPL_RX_PKT_IPSEC_OPCODE)
5441 #define G_CPL_RX_PKT_IPSEC_OPCODE(x) \
5442 (((x) >> S_CPL_RX_PKT_IPSEC_OPCODE) & M_CPL_RX_PKT_IPSEC_OPCODE)
5446 #define V_CPL_RX_PKT_IPSEC_IPFRAG(x) ((x) << S_CPL_RX_PKT_IPSEC_IPFRAG)
5447 #define G_CPL_RX_PKT_IPSEC_IPFRAG(x) \
5448 (((x) >> S_CPL_RX_PKT_IPSEC_IPFRAG) & M_CPL_RX_PKT_IPSEC_IPFRAG)
5449 #define F_CPL_RX_PKT_IPSEC_IPFRAG V_CPL_RX_PKT_IPSEC_IPFRAG(1U)
5453 #define V_CPL_RX_PKT_IPSEC_VLAN_EX(x) ((x) << S_CPL_RX_PKT_IPSEC_VLAN_EX)
5454 #define G_CPL_RX_PKT_IPSEC_VLAN_EX(x) \
5455 (((x) >> S_CPL_RX_PKT_IPSEC_VLAN_EX) & M_CPL_RX_PKT_IPSEC_VLAN_EX)
5456 #define F_CPL_RX_PKT_IPSEC_VLAN_EX V_CPL_RX_PKT_IPSEC_VLAN_EX(1U)
5460 #define V_CPL_RX_PKT_IPSEC_IPMI(x) ((x) << S_CPL_RX_PKT_IPSEC_IPMI)
5461 #define G_CPL_RX_PKT_IPSEC_IPMI(x) \
5462 (((x) >> S_CPL_RX_PKT_IPSEC_IPMI) & M_CPL_RX_PKT_IPSEC_IPMI)
5463 #define F_CPL_RX_PKT_IPSEC_IPMI V_CPL_RX_PKT_IPSEC_IPMI(1U)
5467 #define V_CPL_RX_PKT_IPSEC_INTERFACE(x) ((x) << S_CPL_RX_PKT_IPSEC_INTERFACE)
5468 #define G_CPL_RX_PKT_IPSEC_INTERFACE(x) \
5469 (((x) >> S_CPL_RX_PKT_IPSEC_INTERFACE) & M_CPL_RX_PKT_IPSEC_INTERFACE)
5473 #define V_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \
5474 ((x) << S_CPL_RX_PKT_IPSEC_IPSECEXTERR)
5475 #define G_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \
5476 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECEXTERR) & M_CPL_RX_PKT_IPSEC_IPSECEXTERR)
5480 #define V_CPL_RX_PKT_IPSEC_IPSECTYPE(x) ((x) << S_CPL_RX_PKT_IPSEC_IPSECTYPE)
5481 #define G_CPL_RX_PKT_IPSEC_IPSECTYPE(x) \
5482 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECTYPE) & M_CPL_RX_PKT_IPSEC_IPSECTYPE)
5486 #define V_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \
5487 ((x) << S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN)
5488 #define G_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \
5489 (((x) >> S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) & M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN)
5493 #define V_CPL_RX_PKT_IPSEC_RXCHANNEL(x) ((x) << S_CPL_RX_PKT_IPSEC_RXCHANNEL)
5494 #define G_CPL_RX_PKT_IPSEC_RXCHANNEL(x) \
5495 (((x) >> S_CPL_RX_PKT_IPSEC_RXCHANNEL) & M_CPL_RX_PKT_IPSEC_RXCHANNEL)
5499 #define V_CPL_RX_PKT_IPSEC_FLAGS(x) ((x) << S_CPL_RX_PKT_IPSEC_FLAGS)
5500 #define G_CPL_RX_PKT_IPSEC_FLAGS(x) \
5501 (((x) >> S_CPL_RX_PKT_IPSEC_FLAGS) & M_CPL_RX_PKT_IPSEC_FLAGS)
5505 #define V_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \
5506 ((x) << S_CPL_RX_PKT_IPSEC_MACMATCHTYPE)
5507 #define G_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \
5508 (((x) >> S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) & \
5513 #define V_CPL_RX_PKT_IPSEC_MACINDEX(x) ((x) << S_CPL_RX_PKT_IPSEC_MACINDEX)
5514 #define G_CPL_RX_PKT_IPSEC_MACINDEX(x) \
5515 (((x) >> S_CPL_RX_PKT_IPSEC_MACINDEX) & M_CPL_RX_PKT_IPSEC_MACINDEX)
5519 #define V_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_ETHHDRLEN)
5520 #define G_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) \
5521 (((x) >> S_CPL_RX_PKT_IPSEC_ETHHDRLEN) & M_CPL_RX_PKT_IPSEC_ETHHDRLEN)
5525 #define V_CPL_RX_PKT_IPSEC_IPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_IPHDRLEN)
5526 #define G_CPL_RX_PKT_IPSEC_IPHDRLEN(x) \
5527 (((x) >> S_CPL_RX_PKT_IPSEC_IPHDRLEN) & M_CPL_RX_PKT_IPSEC_IPHDRLEN)
5531 #define V_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_TCPHDRLEN)
5532 #define G_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) \
5533 (((x) >> S_CPL_RX_PKT_IPSEC_TCPHDRLEN) & M_CPL_RX_PKT_IPSEC_TCPHDRLEN)
5537 #define V_CPL_RX_PKT_IPSEC_RXERROR(x) ((x) << S_CPL_RX_PKT_IPSEC_RXERROR)
5538 #define G_CPL_RX_PKT_IPSEC_RXERROR(x) \
5539 (((x) >> S_CPL_RX_PKT_IPSEC_RXERROR) & M_CPL_RX_PKT_IPSEC_RXERROR)
5553 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE)
5554 #define G_CPL_TX_SEC_PDU_OPCODE(x) \
5555 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE)
5560 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID)
5561 #define G_CPL_TX_SEC_PDU_RXCHID(x) \
5562 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID)
5563 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U)
5567 #define V_T7_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_T7_CPL_TX_SEC_PDU_RXCHID)
5568 #define G_T7_CPL_TX_SEC_PDU_RXCHID(x) \
5569 (((x) >> S_T7_CPL_TX_SEC_PDU_RXCHID) & M_T7_CPL_TX_SEC_PDU_RXCHID)
5570 #define F_T7_CPL_TX_SEC_PDU_RXCHID V_T7_CPL_TX_SEC_PDU_RXCHID(1U)
5575 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS)
5576 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \
5577 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS)
5578 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U)
5583 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK)
5584 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \
5585 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK)
5586 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U)
5591 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN)
5592 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \
5593 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN)
5597 #define V_CPL_TX_SEC_PDU_ACKNEXT(x) ((x) << S_CPL_TX_SEC_PDU_ACKNEXT)
5598 #define G_CPL_TX_SEC_PDU_ACKNEXT(x) \
5599 (((x) >> S_CPL_TX_SEC_PDU_ACKNEXT) & M_CPL_TX_SEC_PDU_ACKNEXT)
5600 #define F_CPL_TX_SEC_PDU_ACKNEXT V_CPL_TX_SEC_PDU_ACKNEXT(1U)
5605 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER)
5606 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \
5607 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \
5613 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST)
5614 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \
5615 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \
5620 #define V_CPL_TX_SEC_PDU_PLDLEN(x) ((x) << S_CPL_TX_SEC_PDU_PLDLEN)
5621 #define G_CPL_TX_SEC_PDU_PLDLEN(x) \
5622 (((x) >> S_CPL_TX_SEC_PDU_PLDLEN) & M_CPL_TX_SEC_PDU_PLDLEN)
5630 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART)
5631 #define G_CPL_TX_SEC_PDU_AADSTART(x) \
5632 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \
5639 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP)
5640 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \
5641 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP)
5648 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART)
5649 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \
5650 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \
5657 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \
5658 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI)
5659 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \
5660 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \
5665 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \
5666 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO)
5667 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \
5668 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \
5676 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART)
5677 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \
5678 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \
5685 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP)
5686 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \
5687 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \
5694 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT)
5695 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \
5696 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \
5707 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE)
5708 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \
5709 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE)
5713 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA)
5714 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \
5715 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA)
5716 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U)
5720 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1)
5721 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \
5722 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1)
5726 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \
5727 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER)
5728 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \
5729 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \
5731 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U)
5735 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \
5736 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP)
5737 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \
5738 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \
5740 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U)
5744 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \
5745 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB)
5746 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \
5747 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \
5749 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U)
5753 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT)
5754 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \
5755 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \
5760 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID)
5761 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \
5762 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \
5767 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \
5768 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR)
5769 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \
5770 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \
5782 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \
5783 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI)
5784 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \
5785 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) & \
5790 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \
5791 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO)
5792 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \
5793 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) & \
5798 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \
5799 ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR)
5800 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \
5801 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) & M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR)
5802 #define F_CPL_T7_RX_PHYS_DSGL_NUMSGEERR V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(1U)
5806 #define V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \
5807 ((x) << S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE)
5808 #define G_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \
5809 (((x) >> S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) & \
5812 V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(1U)
5816 #define V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \
5817 ((x) << S_CPL_T7_RX_PHYS_DSGL_SPLITMODE)
5818 #define G_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \
5819 (((x) >> S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) & M_CPL_T7_RX_PHYS_DSGL_SPLITMODE)
5821 V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(1U)
5825 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGE)
5826 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) \
5827 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGE) & M_CPL_T7_RX_PHYS_DSGL_NUMSGE)
5838 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE)
5839 #define G_CPL_TX_TLS_ACK_OPCODE(x) \
5840 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE)
5844 #define V_T7_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_T7_CPL_TX_TLS_ACK_RXCHID)
5845 #define G_T7_CPL_TX_TLS_ACK_RXCHID(x) \
5846 (((x) >> S_T7_CPL_TX_TLS_ACK_RXCHID) & M_T7_CPL_TX_TLS_ACK_RXCHID)
5850 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID)
5851 #define G_CPL_TX_TLS_ACK_RXCHID(x) \
5852 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID)
5853 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U)
5857 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG)
5858 #define G_CPL_TX_TLS_ACK_FWMSG(x) \
5859 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG)
5860 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U)
5864 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK)
5865 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \
5866 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK)
5867 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U)
5871 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN)
5872 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \
5873 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN)
5877 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR)
5878 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \
5879 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR)
5880 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U)
5884 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB)
5885 #define G_CPL_TX_TLS_ACK_LCB(x) \
5886 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB)
5887 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U)
5891 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH)
5892 #define G_CPL_TX_TLS_ACK_PHASH(x) \
5893 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH)
5894 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U)
5898 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2)
5899 #define G_CPL_TX_TLS_ACK_RSVD2(x) \
5900 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2)
5904 #define V_CPL_TX_TLS_ACK_PLDLEN(x) ((x) << S_CPL_TX_TLS_ACK_PLDLEN)
5905 #define G_CPL_TX_TLS_ACK_PLDLEN(x) \
5906 (((x) >> S_CPL_TX_TLS_ACK_PLDLEN) & M_CPL_TX_TLS_ACK_PLDLEN)
5919 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE)
5920 #define G_CPL_RCB_UPD_OPCODE(x) \
5921 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE)
5925 #define V_CPL_RCB_UPD_TID(x) ((x) << S_CPL_RCB_UPD_TID)
5926 #define G_CPL_RCB_UPD_TID(x) \
5927 (((x) >> S_CPL_RCB_UPD_TID) & M_CPL_RCB_UPD_TID)
5931 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE)
5932 #define G_CPL_RCB_UPD_OPCODE(x) \
5933 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE)
5937 #define V_CPL_RCB_UPD_PSN(x) ((x) << S_CPL_RCB_UPD_PSN)
5938 #define G_CPL_RCB_UPD_PSN(x) \
5939 (((x) >> S_CPL_RCB_UPD_PSN) & M_CPL_RCB_UPD_PSN)
5943 #define V_CPL_RCB_UPD_NODATA(x) ((x) << S_CPL_RCB_UPD_NODATA)
5944 #define G_CPL_RCB_UPD_NODATA(x) \
5945 (((x) >> S_CPL_RCB_UPD_NODATA) & M_CPL_RCB_UPD_NODATA)
5946 #define F_CPL_RCB_UPD_NODATA V_CPL_RCB_UPD_NODATA(1U)
5950 #define V_CPL_RCB_UPD_RTTSTAMP(x) ((x) << S_CPL_RCB_UPD_RTTSTAMP)
5951 #define G_CPL_RCB_UPD_RTTSTAMP(x) \
5952 (((x) >> S_CPL_RCB_UPD_RTTSTAMP) & M_CPL_RCB_UPD_RTTSTAMP)
5953 #define F_CPL_RCB_UPD_RTTSTAMP V_CPL_RCB_UPD_RTTSTAMP(1U)
5957 #define V_CPL_RCB_UPD_ECNREPCLR(x) ((x) << S_CPL_RCB_UPD_ECNREPCLR)
5958 #define G_CPL_RCB_UPD_ECNREPCLR(x) \
5959 (((x) >> S_CPL_RCB_UPD_ECNREPCLR) & M_CPL_RCB_UPD_ECNREPCLR)
5960 #define F_CPL_RCB_UPD_ECNREPCLR V_CPL_RCB_UPD_ECNREPCLR(1U)
5964 #define V_CPL_RCB_UPD_NAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_NAKSEQCLR)
5965 #define G_CPL_RCB_UPD_NAKSEQCLR(x) \
5966 (((x) >> S_CPL_RCB_UPD_NAKSEQCLR) & M_CPL_RCB_UPD_NAKSEQCLR)
5967 #define F_CPL_RCB_UPD_NAKSEQCLR V_CPL_RCB_UPD_NAKSEQCLR(1U)
5971 #define V_CPL_RCB_UPD_QPERRSET(x) ((x) << S_CPL_RCB_UPD_QPERRSET)
5972 #define G_CPL_RCB_UPD_QPERRSET(x) \
5973 (((x) >> S_CPL_RCB_UPD_QPERRSET) & M_CPL_RCB_UPD_QPERRSET)
5974 #define F_CPL_RCB_UPD_QPERRSET V_CPL_RCB_UPD_QPERRSET(1U)
5978 #define V_CPL_RCB_UPD_RRQUPDEN(x) ((x) << S_CPL_RCB_UPD_RRQUPDEN)
5979 #define G_CPL_RCB_UPD_RRQUPDEN(x) \
5980 (((x) >> S_CPL_RCB_UPD_RRQUPDEN) & M_CPL_RCB_UPD_RRQUPDEN)
5981 #define F_CPL_RCB_UPD_RRQUPDEN V_CPL_RCB_UPD_RRQUPDEN(1U)
5983 #define S_CPL_RCB_UPD_RQUPDEN 1
5985 #define V_CPL_RCB_UPD_RQUPDEN(x) ((x) << S_CPL_RCB_UPD_RQUPDEN)
5986 #define G_CPL_RCB_UPD_RQUPDEN(x) \
5987 (((x) >> S_CPL_RCB_UPD_RQUPDEN) & M_CPL_RCB_UPD_RQUPDEN)
5988 #define F_CPL_RCB_UPD_RQUPDEN V_CPL_RCB_UPD_RQUPDEN(1U)
5992 #define V_CPL_RCB_UPD_CNPREPCLR(x) ((x) << S_CPL_RCB_UPD_CNPREPCLR)
5993 #define G_CPL_RCB_UPD_CNPREPCLR(x) \
5994 (((x) >> S_CPL_RCB_UPD_CNPREPCLR) & M_CPL_RCB_UPD_CNPREPCLR)
5995 #define F_CPL_RCB_UPD_CNPREPCLR V_CPL_RCB_UPD_CNPREPCLR(1U)
5999 #define V_CPL_RCB_UPD_RSPNAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_RSPNAKSEQCLR)
6000 #define G_CPL_RCB_UPD_RSPNAKSEQCLR(x) \
6001 (((x) >> S_CPL_RCB_UPD_RSPNAKSEQCLR) & M_CPL_RCB_UPD_RSPNAKSEQCLR)
6002 #define F_CPL_RCB_UPD_RSPNAKSEQCLR V_CPL_RCB_UPD_RSPNAKSEQCLR(1U)
6012 #define V_CPL_ROCE_FW_NOTIFY_OPCODE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_OPCODE)
6013 #define G_CPL_ROCE_FW_NOTIFY_OPCODE(x) \
6014 (((x) >> S_CPL_ROCE_FW_NOTIFY_OPCODE) & M_CPL_ROCE_FW_NOTIFY_OPCODE)
6018 #define V_CPL_ROCE_FW_NOTIFY_TID(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TID)
6019 #define G_CPL_ROCE_FW_NOTIFY_TID(x) \
6020 (((x) >> S_CPL_ROCE_FW_NOTIFY_TID) & M_CPL_ROCE_FW_NOTIFY_TID)
6024 #define V_CPL_ROCE_FW_NOTIFY_TYPE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TYPE)
6025 #define G_CPL_ROCE_FW_NOTIFY_TYPE(x) \
6026 (((x) >> S_CPL_ROCE_FW_NOTIFY_TYPE) & M_CPL_ROCE_FW_NOTIFY_TYPE)
6039 #define V_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \
6040 ((x) << S_CPL_ROCE_ACK_NAK_REQ_OPCODE)
6041 #define G_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \
6042 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_OPCODE)
6046 #define V_CPL_ROCE_ACK_NAK_REQ_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TID)
6047 #define G_CPL_ROCE_ACK_NAK_REQ_TID(x) \
6048 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TID) & M_CPL_ROCE_ACK_NAK_REQ_TID)
6052 #define V_CPL_ROCE_ACK_NAK_REQ_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TYPE)
6053 #define G_CPL_ROCE_ACK_NAK_REQ_TYPE(x) \
6054 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TYPE) & M_CPL_ROCE_ACK_NAK_REQ_TYPE)
6058 #define V_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \
6059 ((x) << S_CPL_ROCE_ACK_NAK_REQ_STATUS)
6060 #define G_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \
6061 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_STATUS) & M_CPL_ROCE_ACK_NAK_REQ_STATUS)
6065 #define V_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \
6066 ((x) << S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE)
6067 #define G_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \
6068 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE)
6072 #define V_CPL_ROCE_ACK_NAK_REQ_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_PSN)
6073 #define G_CPL_ROCE_ACK_NAK_REQ_PSN(x) \
6074 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_PSN) & M_CPL_ROCE_ACK_NAK_REQ_PSN)
6078 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \
6079 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_HI)
6080 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \
6081 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) & M_CPL_ROCE_ACK_NAK_REQ_MSN_HI)
6085 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \
6086 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_LO)
6087 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \
6088 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) & M_CPL_ROCE_ACK_NAK_REQ_MSN_LO)
6101 #define V_CPL_ROCE_ACK_NAK_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_OPCODE)
6102 #define G_CPL_ROCE_ACK_NAK_OPCODE(x) \
6103 (((x) >> S_CPL_ROCE_ACK_NAK_OPCODE) & M_CPL_ROCE_ACK_NAK_OPCODE)
6107 #define V_CPL_ROCE_ACK_NAK_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_TID)
6108 #define G_CPL_ROCE_ACK_NAK_TID(x) \
6109 (((x) >> S_CPL_ROCE_ACK_NAK_TID) & M_CPL_ROCE_ACK_NAK_TID)
6113 #define V_CPL_ROCE_ACK_NAK_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_TYPE)
6114 #define G_CPL_ROCE_ACK_NAK_TYPE(x) \
6115 (((x) >> S_CPL_ROCE_ACK_NAK_TYPE) & M_CPL_ROCE_ACK_NAK_TYPE)
6119 #define V_CPL_ROCE_ACK_NAK_STATUS(x) ((x) << S_CPL_ROCE_ACK_NAK_STATUS)
6120 #define G_CPL_ROCE_ACK_NAK_STATUS(x) \
6121 (((x) >> S_CPL_ROCE_ACK_NAK_STATUS) & M_CPL_ROCE_ACK_NAK_STATUS)
6125 #define V_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_WIRE_OPCODE)
6126 #define G_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) \
6127 (((x) >> S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_WIRE_OPCODE)
6131 #define V_CPL_ROCE_ACK_NAK_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_PSN)
6132 #define G_CPL_ROCE_ACK_NAK_PSN(x) \
6133 (((x) >> S_CPL_ROCE_ACK_NAK_PSN) & M_CPL_ROCE_ACK_NAK_PSN)
6137 #define V_CPL_ROCE_ACK_NAK_RTT_HI(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_HI)
6138 #define G_CPL_ROCE_ACK_NAK_RTT_HI(x) \
6139 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_HI) & M_CPL_ROCE_ACK_NAK_RTT_HI)
6143 #define V_CPL_ROCE_ACK_NAK_RTT_LO(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_LO)
6144 #define G_CPL_ROCE_ACK_NAK_RTT_LO(x) \
6145 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_LO) & M_CPL_ROCE_ACK_NAK_RTT_LO)
6149 #define V_CPL_ROCE_ACK_NAK_RTTVALID(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTVALID)
6150 #define G_CPL_ROCE_ACK_NAK_RTTVALID(x) \
6151 (((x) >> S_CPL_ROCE_ACK_NAK_RTTVALID) & M_CPL_ROCE_ACK_NAK_RTTVALID)
6152 #define F_CPL_ROCE_ACK_NAK_RTTVALID V_CPL_ROCE_ACK_NAK_RTTVALID(1U)
6156 #define V_CPL_ROCE_ACK_NAK_RTTBAD(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTBAD)
6157 #define G_CPL_ROCE_ACK_NAK_RTTBAD(x) \
6158 (((x) >> S_CPL_ROCE_ACK_NAK_RTTBAD) & M_CPL_ROCE_ACK_NAK_RTTBAD)
6159 #define F_CPL_ROCE_ACK_NAK_RTTBAD V_CPL_ROCE_ACK_NAK_RTTBAD(1U)
6177 #define V_CPL_ROCE_CQE_OPCODE(x) ((x) << S_CPL_ROCE_CQE_OPCODE)
6178 #define G_CPL_ROCE_CQE_OPCODE(x) \
6179 (((x) >> S_CPL_ROCE_CQE_OPCODE) & M_CPL_ROCE_CQE_OPCODE)
6183 #define V_CPL_ROCE_CQE_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_RSSCTRL)
6184 #define G_CPL_ROCE_CQE_RSSCTRL(x) \
6185 (((x) >> S_CPL_ROCE_CQE_RSSCTRL) & M_CPL_ROCE_CQE_RSSCTRL)
6189 #define V_CPL_ROCE_CQE_TID(x) ((x) << S_CPL_ROCE_CQE_TID)
6190 #define G_CPL_ROCE_CQE_TID(x) \
6191 (((x) >> S_CPL_ROCE_CQE_TID) & M_CPL_ROCE_CQE_TID)
6195 #define V_CPL_ROCE_CQE_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FLITCNT)
6196 #define G_CPL_ROCE_CQE_FLITCNT(x) \
6197 (((x) >> S_CPL_ROCE_CQE_FLITCNT) & M_CPL_ROCE_CQE_FLITCNT)
6201 #define V_CPL_ROCE_CQE_QPID(x) ((x) << S_CPL_ROCE_CQE_QPID)
6202 #define G_CPL_ROCE_CQE_QPID(x) \
6203 (((x) >> S_CPL_ROCE_CQE_QPID) & M_CPL_ROCE_CQE_QPID)
6207 #define V_CPL_ROCE_CQE_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_EXTMODE)
6208 #define G_CPL_ROCE_CQE_EXTMODE(x) \
6209 (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE)
6210 #define F_CPL_ROCE_CQE_EXTMODE V_CPL_ROCE_CQE_EXTMODE(1U)
6214 #define V_CPL_ROCE_CQE_GENERATION_BIT(x) \
6215 ((x) << S_CPL_ROCE_CQE_GENERATION_BIT)
6216 #define G_CPL_ROCE_CQE_GENERATION_BIT(x) \
6217 (((x) >> S_CPL_ROCE_CQE_GENERATION_BIT) & M_CPL_ROCE_CQE_GENERATION_BIT)
6218 #define F_CPL_ROCE_CQE_GENERATION_BIT V_CPL_ROCE_CQE_GENERATION_BIT(1U)
6222 #define V_CPL_ROCE_CQE_STATUS(x) ((x) << S_CPL_ROCE_CQE_STATUS)
6223 #define G_CPL_ROCE_CQE_STATUS(x) \
6224 (((x) >> S_CPL_ROCE_CQE_STATUS) & M_CPL_ROCE_CQE_STATUS)
6228 #define V_CPL_ROCE_CQE_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_CQE_TYPE)
6229 #define G_CPL_ROCE_CQE_CQE_TYPE(x) \
6230 (((x) >> S_CPL_ROCE_CQE_CQE_TYPE) & M_CPL_ROCE_CQE_CQE_TYPE)
6231 #define F_CPL_ROCE_CQE_CQE_TYPE V_CPL_ROCE_CQE_CQE_TYPE(1U)
6235 #define V_CPL_ROCE_CQE_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE)
6236 #define G_CPL_ROCE_CQE_WR_TYPE(x) \
6237 (((x) >> S_CPL_ROCE_CQE_WR_TYPE) & M_CPL_ROCE_CQE_WR_TYPE)
6241 #define V_CPL_ROCE_CQE_SE(x) ((x) << S_CPL_ROCE_CQE_SE)
6242 #define G_CPL_ROCE_CQE_SE(x) \
6243 (((x) >> S_CPL_ROCE_CQE_SE) & M_CPL_ROCE_CQE_SE)
6244 #define F_CPL_ROCE_CQE_SE V_CPL_ROCE_CQE_SE(1U)
6248 #define V_CPL_ROCE_CQE_WR_TYPE_EXT(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE_EXT)
6249 #define G_CPL_ROCE_CQE_WR_TYPE_EXT(x) \
6250 (((x) >> S_CPL_ROCE_CQE_WR_TYPE_EXT) & M_CPL_ROCE_CQE_WR_TYPE_EXT)
6254 #define V_CPL_ROCE_CQE_SRQ(x) ((x) << S_CPL_ROCE_CQE_SRQ)
6255 #define G_CPL_ROCE_CQE_SRQ(x) \
6256 (((x) >> S_CPL_ROCE_CQE_SRQ) & M_CPL_ROCE_CQE_SRQ)
6273 #define V_CPL_ROCE_CQE_FW_OPCODE(x) ((x) << S_CPL_ROCE_CQE_FW_OPCODE)
6274 #define G_CPL_ROCE_CQE_FW_OPCODE(x) \
6275 (((x) >> S_CPL_ROCE_CQE_FW_OPCODE) & M_CPL_ROCE_CQE_FW_OPCODE)
6279 #define V_CPL_ROCE_CQE_FW_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_FW_RSSCTRL)
6280 #define G_CPL_ROCE_CQE_FW_RSSCTRL(x) \
6281 (((x) >> S_CPL_ROCE_CQE_FW_RSSCTRL) & M_CPL_ROCE_CQE_FW_RSSCTRL)
6285 #define V_CPL_ROCE_CQE_FW_CQID(x) ((x) << S_CPL_ROCE_CQE_FW_CQID)
6286 #define G_CPL_ROCE_CQE_FW_CQID(x) \
6287 (((x) >> S_CPL_ROCE_CQE_FW_CQID) & M_CPL_ROCE_CQE_FW_CQID)
6291 #define V_CPL_ROCE_CQE_FW_TID(x) ((x) << S_CPL_ROCE_CQE_FW_TID)
6292 #define G_CPL_ROCE_CQE_FW_TID(x) \
6293 (((x) >> S_CPL_ROCE_CQE_FW_TID) & M_CPL_ROCE_CQE_FW_TID)
6297 #define V_CPL_ROCE_CQE_FW_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FW_FLITCNT)
6298 #define G_CPL_ROCE_CQE_FW_FLITCNT(x) \
6299 (((x) >> S_CPL_ROCE_CQE_FW_FLITCNT) & M_CPL_ROCE_CQE_FW_FLITCNT)
6303 #define V_CPL_ROCE_CQE_FW_QPID(x) ((x) << S_CPL_ROCE_CQE_FW_QPID)
6304 #define G_CPL_ROCE_CQE_FW_QPID(x) \
6305 (((x) >> S_CPL_ROCE_CQE_FW_QPID) & M_CPL_ROCE_CQE_FW_QPID)
6309 #define V_CPL_ROCE_CQE_FW_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_FW_EXTMODE)
6310 #define G_CPL_ROCE_CQE_FW_EXTMODE(x) \
6311 (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE)
6312 #define F_CPL_ROCE_CQE_FW_EXTMODE V_CPL_ROCE_CQE_FW_EXTMODE(1U)
6316 #define V_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \
6317 ((x) << S_CPL_ROCE_CQE_FW_GENERATION_BIT)
6318 #define G_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \
6319 (((x) >> S_CPL_ROCE_CQE_FW_GENERATION_BIT) & \
6321 #define F_CPL_ROCE_CQE_FW_GENERATION_BIT V_CPL_ROCE_CQE_FW_GENERATION_BIT(1U)
6325 #define V_CPL_ROCE_CQE_FW_STATUS(x) ((x) << S_CPL_ROCE_CQE_FW_STATUS)
6326 #define G_CPL_ROCE_CQE_FW_STATUS(x) \
6327 (((x) >> S_CPL_ROCE_CQE_FW_STATUS) & M_CPL_ROCE_CQE_FW_STATUS)
6331 #define V_CPL_ROCE_CQE_FW_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_CQE_TYPE)
6332 #define G_CPL_ROCE_CQE_FW_CQE_TYPE(x) \
6333 (((x) >> S_CPL_ROCE_CQE_FW_CQE_TYPE) & M_CPL_ROCE_CQE_FW_CQE_TYPE)
6334 #define F_CPL_ROCE_CQE_FW_CQE_TYPE V_CPL_ROCE_CQE_FW_CQE_TYPE(1U)
6338 #define V_CPL_ROCE_CQE_FW_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE)
6339 #define G_CPL_ROCE_CQE_FW_WR_TYPE(x) \
6340 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE) & M_CPL_ROCE_CQE_FW_WR_TYPE)
6344 #define V_CPL_ROCE_CQE_FW_SE(x) ((x) << S_CPL_ROCE_CQE_FW_SE)
6345 #define G_CPL_ROCE_CQE_FW_SE(x) \
6346 (((x) >> S_CPL_ROCE_CQE_FW_SE) & M_CPL_ROCE_CQE_FW_SE)
6347 #define F_CPL_ROCE_CQE_FW_SE V_CPL_ROCE_CQE_FW_SE(1U)
6351 #define V_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \
6352 ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE_EXT)
6353 #define G_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \
6354 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) & M_CPL_ROCE_CQE_FW_WR_TYPE_EXT)
6358 #define V_CPL_ROCE_CQE_FW_SRQ(x) ((x) << S_CPL_ROCE_CQE_FW_SRQ)
6359 #define G_CPL_ROCE_CQE_FW_SRQ(x) \
6360 (((x) >> S_CPL_ROCE_CQE_FW_SRQ) & M_CPL_ROCE_CQE_FW_SRQ)
6377 #define V_CPL_ROCE_CQE_ERR_OPCODE(x) ((x) << S_CPL_ROCE_CQE_ERR_OPCODE)
6378 #define G_CPL_ROCE_CQE_ERR_OPCODE(x) \
6379 (((x) >> S_CPL_ROCE_CQE_ERR_OPCODE) & M_CPL_ROCE_CQE_ERR_OPCODE)
6383 #define V_CPL_ROCE_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_ERR_RSSCTRL)
6384 #define G_CPL_ROCE_CQE_ERR_RSSCTRL(x) \
6385 (((x) >> S_CPL_ROCE_CQE_ERR_RSSCTRL) & M_CPL_ROCE_CQE_ERR_RSSCTRL)
6389 #define V_CPL_ROCE_CQE_ERR_CQID(x) ((x) << S_CPL_ROCE_CQE_ERR_CQID)
6390 #define G_CPL_ROCE_CQE_ERR_CQID(x) \
6391 (((x) >> S_CPL_ROCE_CQE_ERR_CQID) & M_CPL_ROCE_CQE_ERR_CQID)
6395 #define V_CPL_ROCE_CQE_ERR_TID(x) ((x) << S_CPL_ROCE_CQE_ERR_TID)
6396 #define G_CPL_ROCE_CQE_ERR_TID(x) \
6397 (((x) >> S_CPL_ROCE_CQE_ERR_TID) & M_CPL_ROCE_CQE_ERR_TID)
6401 #define V_CPL_ROCE_CQE_ERR_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_ERR_FLITCNT)
6402 #define G_CPL_ROCE_CQE_ERR_FLITCNT(x) \
6403 (((x) >> S_CPL_ROCE_CQE_ERR_FLITCNT) & M_CPL_ROCE_CQE_ERR_FLITCNT)
6407 #define V_CPL_ROCE_CQE_ERR_QPID(x) ((x) << S_CPL_ROCE_CQE_ERR_QPID)
6408 #define G_CPL_ROCE_CQE_ERR_QPID(x) \
6409 (((x) >> S_CPL_ROCE_CQE_ERR_QPID) & M_CPL_ROCE_CQE_ERR_QPID)
6413 #define V_CPL_ROCE_CQE_ERR_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_ERR_EXTMODE)
6414 #define G_CPL_ROCE_CQE_ERR_EXTMODE(x) \
6415 (((x) >> S_CPL_ROCE_CQE_ERR_EXTMODE) & M_CPL_ROCE_CQE_ERR_EXTMODE)
6416 #define F_CPL_ROCE_CQE_ERR_EXTMODE V_CPL_ROCE_CQE_ERR_EXTMODE(1U)
6420 #define V_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \
6421 ((x) << S_CPL_ROCE_CQE_ERR_GENERATION_BIT)
6422 #define G_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \
6423 (((x) >> S_CPL_ROCE_CQE_ERR_GENERATION_BIT) & \
6426 V_CPL_ROCE_CQE_ERR_GENERATION_BIT(1U)
6430 #define V_CPL_ROCE_CQE_ERR_STATUS(x) ((x) << S_CPL_ROCE_CQE_ERR_STATUS)
6431 #define G_CPL_ROCE_CQE_ERR_STATUS(x) \
6432 (((x) >> S_CPL_ROCE_CQE_ERR_STATUS) & M_CPL_ROCE_CQE_ERR_STATUS)
6436 #define V_CPL_ROCE_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_CQE_TYPE)
6437 #define G_CPL_ROCE_CQE_ERR_CQE_TYPE(x) \
6438 (((x) >> S_CPL_ROCE_CQE_ERR_CQE_TYPE) & M_CPL_ROCE_CQE_ERR_CQE_TYPE)
6439 #define F_CPL_ROCE_CQE_ERR_CQE_TYPE V_CPL_ROCE_CQE_ERR_CQE_TYPE(1U)
6443 #define V_CPL_ROCE_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE)
6444 #define G_CPL_ROCE_CQE_ERR_WR_TYPE(x) \
6445 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE) & M_CPL_ROCE_CQE_ERR_WR_TYPE)
6449 #define V_CPL_ROCE_CQE_ERR_SE(x) ((x) << S_CPL_ROCE_CQE_ERR_SE)
6450 #define G_CPL_ROCE_CQE_ERR_SE(x) \
6451 (((x) >> S_CPL_ROCE_CQE_ERR_SE) & M_CPL_ROCE_CQE_ERR_SE)
6452 #define F_CPL_ROCE_CQE_ERR_SE V_CPL_ROCE_CQE_ERR_SE(1U)
6456 #define V_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \
6457 ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT)
6458 #define G_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \
6459 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) & M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT)
6463 #define V_CPL_ROCE_CQE_ERR_SRQ(x) ((x) << S_CPL_ROCE_CQE_ERR_SRQ)
6464 #define G_CPL_ROCE_CQE_ERR_SRQ(x) \
6465 (((x) >> S_CPL_ROCE_CQE_ERR_SRQ) & M_CPL_ROCE_CQE_ERR_SRQ)
6475 #define V_CPL_ACCELERATOR_HDR_OPCODE(x) ((x) << S_CPL_ACCELERATOR_HDR_OPCODE)
6476 #define G_CPL_ACCELERATOR_HDR_OPCODE(x) \
6477 (((x) >> S_CPL_ACCELERATOR_HDR_OPCODE) & M_CPL_ACCELERATOR_HDR_OPCODE)
6481 #define V_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \
6482 ((x) << S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID)
6483 #define G_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \
6484 (((x) >> S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) & \
6489 #define V_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \
6490 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD)
6491 #define G_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \
6492 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) & \
6497 #define V_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \
6498 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD)
6499 #define G_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \
6500 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) & \
6505 #define V_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \
6506 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_ACK)
6507 #define G_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \
6508 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_ACK) & \
6513 #define V_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \
6514 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_ACK)
6515 #define G_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \
6516 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_ACK) & \
6521 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \
6522 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK)
6523 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \
6524 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) & \
6529 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \
6530 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD)
6531 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \
6532 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) & \
6537 #define V_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \
6538 ((x) << S_CPL_ACCELERATOR_HDR_STATUS_LOC)
6539 #define G_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \
6540 (((x) >> S_CPL_ACCELERATOR_HDR_STATUS_LOC) & \
6554 #define V_CPL_ACCELERATOR_ACK_OPCODE(x) ((x) << S_CPL_ACCELERATOR_ACK_OPCODE)
6555 #define G_CPL_ACCELERATOR_ACK_OPCODE(x) \
6556 (((x) >> S_CPL_ACCELERATOR_ACK_OPCODE) & M_CPL_ACCELERATOR_ACK_OPCODE)
6560 #define V_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \
6561 ((x) << S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID)
6562 #define G_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \
6563 (((x) >> S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) & \
6577 #define V_CPL_NVMT_DATA_OPCODE(x) ((x) << S_CPL_NVMT_DATA_OPCODE)
6578 #define G_CPL_NVMT_DATA_OPCODE(x) \
6579 (((x) >> S_CPL_NVMT_DATA_OPCODE) & M_CPL_NVMT_DATA_OPCODE)
6583 #define V_CPL_NVMT_DATA_TID(x) ((x) << S_CPL_NVMT_DATA_TID)
6584 #define G_CPL_NVMT_DATA_TID(x) \
6585 (((x) >> S_CPL_NVMT_DATA_TID) & M_CPL_NVMT_DATA_TID)
6589 #define V_CPL_NVMT_DATA_STATUS(x) ((x) << S_CPL_NVMT_DATA_STATUS)
6590 #define G_CPL_NVMT_DATA_STATUS(x) \
6591 (((x) >> S_CPL_NVMT_DATA_STATUS) & M_CPL_NVMT_DATA_STATUS)
6606 #define V_CPL_NVMT_CMP_OPCODE(x) ((x) << S_CPL_NVMT_CMP_OPCODE)
6607 #define G_CPL_NVMT_CMP_OPCODE(x) \
6608 (((x) >> S_CPL_NVMT_CMP_OPCODE) & M_CPL_NVMT_CMP_OPCODE)
6612 #define V_CPL_NVMT_CMP_TID(x) ((x) << S_CPL_NVMT_CMP_TID)
6613 #define G_CPL_NVMT_CMP_TID(x) \
6614 (((x) >> S_CPL_NVMT_CMP_TID) & M_CPL_NVMT_CMP_TID)
6630 #define V_CPL_NVMT_CMP_IMM_OPCODE(x) ((x) << S_CPL_NVMT_CMP_IMM_OPCODE)
6631 #define G_CPL_NVMT_CMP_IMM_OPCODE(x) \
6632 (((x) >> S_CPL_NVMT_CMP_IMM_OPCODE) & M_CPL_NVMT_CMP_IMM_OPCODE)
6636 #define V_CPL_NVMT_CMP_IMM_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_IMM_RSSCTRL)
6637 #define G_CPL_NVMT_CMP_IMM_RSSCTRL(x) \
6638 (((x) >> S_CPL_NVMT_CMP_IMM_RSSCTRL) & M_CPL_NVMT_CMP_IMM_RSSCTRL)
6642 #define V_CPL_NVMT_CMP_IMM_CQID(x) ((x) << S_CPL_NVMT_CMP_IMM_CQID)
6643 #define G_CPL_NVMT_CMP_IMM_CQID(x) \
6644 (((x) >> S_CPL_NVMT_CMP_IMM_CQID) & M_CPL_NVMT_CMP_IMM_CQID)
6648 #define V_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \
6649 ((x) << S_CPL_NVMT_CMP_IMM_GENERATION_BIT)
6650 #define G_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \
6651 (((x) >> S_CPL_NVMT_CMP_IMM_GENERATION_BIT) & \
6654 V_CPL_NVMT_CMP_IMM_GENERATION_BIT(1U)
6658 #define V_CPL_NVMT_CMP_IMM_TID(x) ((x) << S_CPL_NVMT_CMP_IMM_TID)
6659 #define G_CPL_NVMT_CMP_IMM_TID(x) \
6660 (((x) >> S_CPL_NVMT_CMP_IMM_TID) & M_CPL_NVMT_CMP_IMM_TID)
6664 #define V_CPL_NVMT_CMP_IMM_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_IMM_OPRQINC)
6665 #define G_CPL_NVMT_CMP_IMM_OPRQINC(x) \
6666 (((x) >> S_CPL_NVMT_CMP_IMM_OPRQINC) & M_CPL_NVMT_CMP_IMM_OPRQINC)
6682 #define V_CPL_NVMT_CMP_SRQ_OPCODE(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPCODE)
6683 #define G_CPL_NVMT_CMP_SRQ_OPCODE(x) \
6684 (((x) >> S_CPL_NVMT_CMP_SRQ_OPCODE) & M_CPL_NVMT_CMP_SRQ_OPCODE)
6688 #define V_CPL_NVMT_CMP_SRQ_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_SRQ_RSSCTRL)
6689 #define G_CPL_NVMT_CMP_SRQ_RSSCTRL(x) \
6690 (((x) >> S_CPL_NVMT_CMP_SRQ_RSSCTRL) & M_CPL_NVMT_CMP_SRQ_RSSCTRL)
6694 #define V_CPL_NVMT_CMP_SRQ_CQID(x) ((x) << S_CPL_NVMT_CMP_SRQ_CQID)
6695 #define G_CPL_NVMT_CMP_SRQ_CQID(x) \
6696 (((x) >> S_CPL_NVMT_CMP_SRQ_CQID) & M_CPL_NVMT_CMP_SRQ_CQID)
6700 #define V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \
6701 ((x) << S_CPL_NVMT_CMP_SRQ_GENERATION_BIT)
6702 #define G_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \
6703 (((x) >> S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) & \
6706 V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(1U)
6710 #define V_CPL_NVMT_CMP_SRQ_TID(x) ((x) << S_CPL_NVMT_CMP_SRQ_TID)
6711 #define G_CPL_NVMT_CMP_SRQ_TID(x) \
6712 (((x) >> S_CPL_NVMT_CMP_SRQ_TID) & M_CPL_NVMT_CMP_SRQ_TID)
6716 #define V_CPL_NVMT_CMP_SRQ_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPRQINC)
6717 #define G_CPL_NVMT_CMP_SRQ_OPRQINC(x) \
6718 (((x) >> S_CPL_NVMT_CMP_SRQ_OPRQINC) & M_CPL_NVMT_CMP_SRQ_OPRQINC)