4053 	int enable_reg;		/* INT_ENABLE register */  member
4078 	enable = t4_read_reg(adap, ii->enable_reg);  in t4_show_intr_info()
4080 		fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);  in t4_show_intr_info()
4119 		cause &= t4_read_reg(adap, ii->enable_reg);  in t4_handle_intr()
4124 		fatal &= t4_read_reg(adap, ii->enable_reg);  in t4_handle_intr()
4159 		.enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,  in pcie_intr_handler()
4180 		.enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,  in pcie_intr_handler()
4257 		.enable_reg = A_PCIE_INT_ENABLE,  in pcie_intr_handler()
4291 		.enable_reg = A_TP_INT_ENABLE,  in tp_intr_handler()
4309 		.enable_reg = A_SGE_INT_ENABLE1,  in sge_intr_handler()
4318 		.enable_reg = A_SGE_INT_ENABLE2,  in sge_intr_handler()
4398 		.enable_reg = A_SGE_INT_ENABLE3,  in sge_intr_handler()
4407 		.enable_reg = A_SGE_INT_ENABLE4,  in sge_intr_handler()
4416 		.enable_reg = A_SGE_INT_ENABLE5,  in sge_intr_handler()
4425 		.enable_reg = A_SGE_INT_ENABLE6,  in sge_intr_handler()
4509 		.enable_reg = A_CIM_HOST_INT_ENABLE,  in cim_intr_handler()
4560 		.enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,  in cim_intr_handler()
4569 		.enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),  in cim_intr_handler()
4621 		.enable_reg = A_ULP_RX_INT_ENABLE,  in ulprx_intr_handler()
4630 		.enable_reg = A_ULP_RX_INT_ENABLE_2,  in ulprx_intr_handler()
4660 		.enable_reg = A_ULP_TX_INT_ENABLE,  in ulptx_intr_handler()
4669 		.enable_reg = A_ULP_TX_INT_ENABLE_2,  in ulptx_intr_handler()
4727 		.enable_reg = A_PM_TX_INT_ENABLE,  in pmtx_intr_handler()
4767 		.enable_reg = A_PM_RX_INT_ENABLE,  in pmrx_intr_handler()
4799 		.enable_reg = A_CPL_INTR_ENABLE,  in cplsw_intr_handler()
4857 		.enable_reg = A_LE_DB_INT_ENABLE,  in le_intr_handler()
4887 		.enable_reg = A_MPS_RX_PERR_INT_ENABLE,  in mps_intr_handler()
4907 		.enable_reg = A_MPS_TX_INT_ENABLE,  in mps_intr_handler()
4922 		.enable_reg = A_MPS_TRC_INT_ENABLE,  in mps_intr_handler()
4935 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,  in mps_intr_handler()
4948 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,  in mps_intr_handler()
4961 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,  in mps_intr_handler()
4976 		.enable_reg = A_MPS_CLS_INT_ENABLE,  in mps_intr_handler()
4989 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,  in mps_intr_handler()
5043 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);  in mem_intr_handler()
5049 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);  in mem_intr_handler()
5056 			ii.enable_reg = A_MC_INT_ENABLE;  in mem_intr_handler()
5060 			ii.enable_reg = A_MC_P_INT_ENABLE;  in mem_intr_handler()
5067 		ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);  in mem_intr_handler()
5120 		.enable_reg = A_MA_INT_ENABLE,  in ma_intr_handler()
5129 		.enable_reg = A_MA_PARITY_ERROR_ENABLE1,  in ma_intr_handler()
5138 		.enable_reg = A_MA_PARITY_ERROR_ENABLE2,  in ma_intr_handler()
5169 		.enable_reg = A_SMB_INT_ENABLE,  in smb_intr_handler()
5194 		.enable_reg = A_NCSI_INT_ENABLE,  in ncsi_intr_handler()
5223 		ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);  in mac_intr_handler()
5232 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);  in mac_intr_handler()
5244 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);  in mac_intr_handler()
5256 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);  in mac_intr_handler()
5295 		.enable_reg = A_PL_PL_INT_ENABLE,  in plpl_intr_handler()
5352 		.enable_reg = A_PL_PERR_ENABLE,  in t4_slow_intr_handler()
5387 		.enable_reg = A_PL_INT_ENABLE,  in t4_slow_intr_handler()
5401 			perr |= t4_read_reg(adap, pl_intr_info.enable_reg);  in t4_slow_intr_handler()