167 	if (chip_id(adap) <= CHELSIO_T5)  in t4_hw_pci_read_cfg4()
249 	if (chip_id(adap) > CHELSIO_T4)  in t4_port_reg()
792 	unsigned int chip_version = chip_id(adapter);  in t4_get_regs_len()
2645 	unsigned int chip_version = chip_id(adap);  in t4_get_regs()
3555 		hdr->chip, chip_id(adap));  in t4_fw_matches_chip()
4435 	if (chip_id(adap) <= CHELSIO_T5) {  in sge_intr_handler()
4446 	if (chip_id(adap) >= CHELSIO_T5)  in sge_intr_handler()
4448 	if (chip_id(adap) >= CHELSIO_T6)  in sge_intr_handler()
4864 	if (chip_id(adap) <= CHELSIO_T5) {  in le_intr_handler()
5006 	if (chip_id(adap) > CHELSIO_T4) {  in mps_intr_handler()
5149 	if (chip_id(adap) > CHELSIO_T4)  in ma_intr_handler()
5240 	if (chip_id(adap) >= CHELSIO_T5) {  in mac_intr_handler()
5252 	if (chip_id(adap) >= CHELSIO_T6) {  in mac_intr_handler()
5426 	if (chip_id(adap) <= CHELSIO_T5)  in t4_intr_enable()
5859 	if ((chip_id(adap) > CHELSIO_T5) &&  in t4_write_rss_key()
5925 	if (chip_id(adapter) <= CHELSIO_T5) {  in t4_read_rss_vf_config()
5963 	if (chip_id(adapter) <= CHELSIO_T5) {  in t4_write_rss_vf_config()
6752 	if (n == 2 && chip_id(adap) <= CHELSIO_T5)  in t4_get_mps_bg_map()
6767 	if (n == 2 && chip_id(adap) <= CHELSIO_T5)  in t4_get_rx_e_chan_map()
6892 	if (chip_id(adap) >= CHELSIO_T5) {  in t4_get_port_stats()
6931 	if (chip_id(adap) >= CHELSIO_T5) {  in t4_get_port_stats()
7334 	unsigned int chip_version = chip_id(adapter);  in t4_sge_decode_idma_state()
8460 				if (chip_id(adap) <= CHELSIO_T5)  in t4_change_mac()
9294 	adapter->chip_params = t4_get_chip_params(chip_id(adapter));  in t4_prep_adapter()
9307 	if (device_id >> 12 == chip_id(adapter))  in t4_prep_adapter()
9553 	if (chip_id(adapter) >= CHELSIO_T6) {  in t4_init_sge_params()
9602 	if (chip_id(adapter) <= CHELSIO_T5) {  in t4_init_sge_params()
9678 		if (chip_id(adap) > CHELSIO_T4) {  in read_filter_mode_and_ingress_config()
9728 	if (chip_id(adap) > CHELSIO_T5) {  in t4_init_tp_params()
11512 				if (chip_id(adap) <= CHELSIO_T5)  in t4_add_mac()