Lines Matching +full:touch +full:- +full:hold +full:- +full:ms
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 * t4_wait_op_done_val - wait until an operation is completed
52 * @mask: a single-bit field within @reg that indicates completion
61 * operation completes and -EAGAIN otherwise.
74 if (--attempts == 0) in t4_wait_op_done_val()
75 return -EAGAIN; in t4_wait_op_done_val()
89 * t4_set_reg_field - set a register field to a value
108 * t4_read_indirect - read indirectly addressed registers
123 while (nregs--) { in t4_read_indirect()
131 * t4_write_indirect - write indirectly addressed registers
146 while (nregs--) { in t4_write_indirect()
153 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
164 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); in t4_hw_pci_read_cfg4()
182 * read-modify-write via t4_set_reg_field().) in t4_hw_pci_read_cfg4()
190 * t4_report_fw_error - report firmware error
219 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
224 for ( ; nflit; nflit--, mbox_addr += 8) in get_mbox_rpl()
235 asrt->u.assert.filename_0_7, in fw_asrt()
236 be32_to_cpu(asrt->u.assert.line), in fw_asrt()
237 be32_to_cpu(asrt->u.assert.x), in fw_asrt()
238 be32_to_cpu(asrt->u.assert.y)); in fw_asrt()
262 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); in read_tx_state_one()
263 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); in read_tx_state_one()
300 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
339 int i, ms, delay_idx, ret, next_tx_check; in t4_wr_mbox_meat_timeout() local
347 if (adap->flags & CHK_MBOX_ACCESS) in t4_wr_mbox_meat_timeout()
351 return -EINVAL; in t4_wr_mbox_meat_timeout()
353 if (adap->flags & IS_VF) { in t4_wr_mbox_meat_timeout()
366 timeout = -timeout; in t4_wr_mbox_meat_timeout()
373 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
389 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
394 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
418 if (adap->flags & IS_VF) { in t4_wr_mbox_meat_timeout()
424 * to the VF's PL-register-backed Mailbox Control can in t4_wr_mbox_meat_timeout()
425 * race in front of the writes to the MA-backed VF in t4_wr_mbox_meat_timeout()
427 * read-back on at least one byte of the VF Mailbox in t4_wr_mbox_meat_timeout()
438 ms = delay[0]; in t4_wr_mbox_meat_timeout()
444 for (i = 0; i < timeout; i += ms) { in t4_wr_mbox_meat_timeout()
445 if (!(adap->flags & IS_VF)) { in t4_wr_mbox_meat_timeout()
457 ms = delay[delay_idx]; /* last element may repeat */ in t4_wr_mbox_meat_timeout()
458 if (delay_idx < ARRAY_SIZE(delay) - 1) in t4_wr_mbox_meat_timeout()
460 msleep(ms); in t4_wr_mbox_meat_timeout()
462 mdelay(ms); in t4_wr_mbox_meat_timeout()
488 return -G_FW_CMD_RETVAL((int)res); in t4_wr_mbox_meat_timeout()
502 adap->flags &= ~FW_OK; in t4_wr_mbox_meat_timeout()
503 ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT; in t4_wr_mbox_meat_timeout()
554 * t4_mc_read - read from MC through backdoor accesses
559 * @ecc: where to store the corresponding 64-bit ECC word
561 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
563 * is assigned the 64-bit ECC word for the read data.
588 return -EBUSY; in t4_mc_read()
600 for (i = 15; i >= 0; i--) in t4_mc_read()
609 * t4_edc_read - read from EDC through backdoor accesses
614 * @ecc: where to store the corresponding 64-bit ECC word
616 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
618 * is assigned the 64-bit ECC word for the read data.
639 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) in t4_edc_read()
653 return -EBUSY; in t4_edc_read()
665 for (i = 15; i >= 0; i--) in t4_edc_read()
674 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
683 * 32-bit boudaries. The memory is returned as a raw byte sequence from
685 * contain multi-byte integers, it's the callers responsibility to
698 return -EINVAL; in t4_mem_read()
703 * copying out of the first line at (addr - start) a word at a time. in t4_mem_read()
707 offset = (addr - start)/sizeof(__be32); in t4_mem_read()
716 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); in t4_mem_read()
727 len -= sizeof(__be32); in t4_mem_read()
735 * Return the specified PCI-E Configuration Space register from our Physical
745 * retrieve the specified PCI-E Configuration Space register. in t4_read_pcie_cfg4()
760 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); in t4_read_pcie_cfg4()
767 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
774 reg, -ret); in t4_read_pcie_cfg4()
778 * Read the desired Configuration Space register via the PCI-E in t4_read_pcie_cfg4()
785 * t4_get_regs_len - return the size of the chips register set
796 if (adapter->flags & IS_VF) in t4_get_regs_len()
802 if (adapter->flags & IS_VF) in t4_get_regs_len()
813 * t4_get_regs - read chip registers into provided buffer
1292 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
2069 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
2639 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), in t4_get_regs()
2653 if (adap->flags & IS_VF) { in t4_get_regs()
2663 if (adap->flags & IS_VF) { in t4_get_regs()
2673 if (adap->flags & IS_VF) { in t4_get_regs()
2711 * header followed by one or more VPD-R sections, each with its own header.
2725 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2728 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */
2740 * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2743 * Request before any in-flight VPD reguest has completed.
2747 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_wait()
2754 if (!adapter->vpd_busy) in t4_seeprom_wait()
2772 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { in t4_seeprom_wait()
2773 adapter->vpd_busy = 0; in t4_seeprom_wait()
2776 } while (--max_poll); in t4_seeprom_wait()
2785 return -ETIMEDOUT; in t4_seeprom_wait()
2789 * t4_seeprom_read - read a serial EEPROM location
2794 * Read a 32-bit word from a location in serial EEPROM using the card's PCI
2800 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_read()
2804 * VPD Accesses must alway be 4-byte aligned! in t4_seeprom_read()
2807 return -EINVAL; in t4_seeprom_read()
2826 adapter->vpd_busy = 1; in t4_seeprom_read()
2827 adapter->vpd_flag = PCI_VPD_ADDR_F; in t4_seeprom_read()
2844 * t4_seeprom_write - write a serial EEPROM location
2849 * Write a 32-bit word to a location in serial EEPROM using the card's PCI
2855 unsigned int base = adapter->params.pci.vpd_cap_addr; in t4_seeprom_write()
2861 * VPD Accesses must alway be 4-byte aligned! in t4_seeprom_write()
2864 return -EINVAL; in t4_seeprom_write()
2886 adapter->vpd_busy = 1; in t4_seeprom_write()
2887 adapter->vpd_flag = 0; in t4_seeprom_write()
2903 } while ((stats_reg & 0x1) && --max_poll); in t4_seeprom_write()
2905 return -ETIMEDOUT; in t4_seeprom_write()
2912 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2915 * @sz: size of function-specific area
2922 * [0..1K) -> [31K..32K)
2923 * [1K..1K+A) -> [ES-A..ES)
2924 * [1K+A..ES) -> [0..ES-A-1K)
2934 return EEPROMSIZE - fn + phys_addr - 1024; in t4_eeprom_ptov()
2936 return phys_addr - 1024 - fn; in t4_eeprom_ptov()
2937 return -EINVAL; in t4_eeprom_ptov()
2941 * t4_seeprom_wp - enable/disable EEPROM write protection
2953 * get_vpd_keyword_val - Locates an information field keyword in the VPD
2959 * -ENOENT otherwise.
2969 tag = vpdr->vpdr_tag; in get_vpd_keyword_val()
2970 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
2971 while (region--) { in get_vpd_keyword_val()
2974 if (++tag != vpdr->vpdr_tag) in get_vpd_keyword_val()
2975 return -ENOENT; in get_vpd_keyword_val()
2976 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
2981 return -ENOENT; in get_vpd_keyword_val()
2993 return -ENOENT; in get_vpd_keyword_val()
2998 * get_vpd_params - read VPD parameters from VPD EEPROM
3040 return -EINVAL; \ in get_vpd_params()
3045 for (csum = 0; i >= 0; i--) in get_vpd_params()
3051 return -EINVAL; in get_vpd_params()
3060 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); in get_vpd_params()
3061 strstrip(p->id); in get_vpd_params()
3062 memcpy(p->ec, vpd + ec, EC_LEN); in get_vpd_params()
3063 strstrip(p->ec); in get_vpd_params()
3064 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3065 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); in get_vpd_params()
3066 strstrip(p->sn); in get_vpd_params()
3067 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3068 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); in get_vpd_params()
3069 strstrip((char *)p->pn); in get_vpd_params()
3070 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3071 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); in get_vpd_params()
3072 strstrip((char *)p->na); in get_vpd_params()
3079 snprintf(p->md, sizeof(p->md), "unknown"); in get_vpd_params()
3081 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; in get_vpd_params()
3082 memcpy(p->md, vpd + md, min(i, MD_LEN)); in get_vpd_params()
3083 strstrip((char *)p->md); in get_vpd_params()
3104 * sf1_read - read data from the serial flash
3121 return -EINVAL; in sf1_read()
3123 return -EBUSY; in sf1_read()
3125 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
3133 * sf1_write - write data to the serial flash
3148 return -EINVAL; in sf1_write()
3150 return -EBUSY; in sf1_write()
3153 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); in sf1_write()
3158 * flash_wait_op - wait for a flash operation to complete
3161 * @delay: delay between polls in ms
3176 if (--attempts == 0) in flash_wait_op()
3177 return -EAGAIN; in flash_wait_op()
3184 * t4_read_flash - read words from serial flash
3187 * @nwords: how many 32-bit words to read
3191 * Read the specified number of 32-bit words from the serial flash.
3193 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3201 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
3202 return -EINVAL; in t4_read_flash()
3210 for ( ; nwords; nwords--, data++) { in t4_read_flash()
3223 * t4_write_flash - write up to a page of data to the serial flash
3233 * (i.e. matches what on disk), otherwise in big-endian.
3242 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
3243 return -EINVAL; in t4_write_flash()
3251 for (left = n; left; left -= c) { in t4_write_flash()
3275 if (memcmp(data - n, (u8 *)buf + offset, n)) { in t4_write_flash()
3279 return -EIO; in t4_write_flash()
3289 * t4_get_fw_version - read the firmware version
3303 * t4_get_fw_hdr - read the firmware header
3316 * t4_get_bs_version - read the firmware bootstrap version
3330 * t4_get_tp_version - read the TP microcode version
3344 * t4_get_exprom_version - return the Expansion ROM version (if any)
3351 * 0 on success, -ENOENT if no Expansion ROM is present.
3370 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) in t4_get_exprom_version()
3371 return -ENOENT; in t4_get_exprom_version()
3373 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | in t4_get_exprom_version()
3374 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | in t4_get_exprom_version()
3375 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | in t4_get_exprom_version()
3376 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); in t4_get_exprom_version()
3381 * t4_get_scfg_version - return the Serial Configuration version
3391 * to retrieve the Serial Configuration version, so we zero-out the
3392 * return-value parameter in that case to avoid leaving it with
3410 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_scfg_version()
3418 * t4_get_vpd_version - return the VPD version
3428 * to retrieve the VPD version, so we zero-out the return-value parameter
3445 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_version()
3453 * t4_get_version_info - extract various chip/firmware version information
3472 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); in t4_get_version_info()
3473 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); in t4_get_version_info()
3474 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); in t4_get_version_info()
3475 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); in t4_get_version_info()
3476 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); in t4_get_version_info()
3477 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); in t4_get_version_info()
3485 * t4_flash_erase_sectors - erase a range of flash sectors
3496 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
3497 return -EINVAL; in t4_flash_erase_sectors()
3516 * t4_flash_cfg_addr - return the address of the flash configuration file
3526 * If the device FLASH isn't large enough to hold a Firmware in t4_flash_cfg_addr()
3529 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) in t4_flash_cfg_addr()
3530 return -ENOSPC; in t4_flash_cfg_addr()
3548 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3549 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3550 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3555 hdr->chip, chip_id(adap)); in t4_fw_matches_chip()
3560 * t4_load_fw - download firmware
3575 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3580 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { in t4_load_fw()
3592 return -EINVAL; in t4_load_fw()
3597 return -EINVAL; in t4_load_fw()
3599 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { in t4_load_fw()
3602 return -EINVAL; in t4_load_fw()
3607 return -EFBIG; in t4_load_fw()
3610 return -EINVAL; in t4_load_fw()
3618 return -EINVAL; in t4_load_fw()
3622 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
3632 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); in t4_load_fw()
3638 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_fw()
3648 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); in t4_load_fw()
3657 * t4_fwcache - firmware cache operation
3669 V_FW_PARAMS_CMD_PFN(adap->pf) | in t4_fwcache()
3677 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
3751 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3752 * @caps16: a 16-bit Port Capabilities value
3754 * Returns the equivalent 32-bit Port Capabilities value.
3789 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3790 * @caps32: a 32-bit Port Capabilities value
3792 * Returns the equivalent 16-bit Port Capabilities value. Note that
3793 * not all 32-bit Port Capabilities can be represented in the 16-bit
3866 * t4_link_l1cfg - apply link configuration to MAC/PHY
3872 * - If the PHY can auto-negotiate first decide what to advertise, then
3873 * enable/disable auto-negotiation as desired, and reset.
3874 * - If the PHY does not auto-negotiate just reset it.
3875 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3876 * otherwise do it later based on the outcome of auto-negotiation.
3886 if (lc->requested_fc & PAUSE_RX) in t4_link_l1cfg()
3888 if (lc->requested_fc & PAUSE_TX) in t4_link_l1cfg()
3890 if (!(lc->requested_fc & PAUSE_AUTONEG)) in t4_link_l1cfg()
3893 if (lc->requested_aneg == AUTONEG_DISABLE) in t4_link_l1cfg()
3895 else if (lc->requested_aneg == AUTONEG_ENABLE) in t4_link_l1cfg()
3898 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; in t4_link_l1cfg()
3901 speed = lc->pcaps & in t4_link_l1cfg()
3903 } else if (lc->requested_speed != 0) in t4_link_l1cfg()
3904 speed = speed_to_fwcap(lc->requested_speed); in t4_link_l1cfg()
3906 speed = fwcap_top_speed(lc->pcaps); in t4_link_l1cfg()
3912 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) in t4_link_l1cfg()
3913 force_fec = lc->force_fec; in t4_link_l1cfg()
3917 if (lc->requested_fec == FEC_AUTO) { in t4_link_l1cfg()
3943 fec |= fec_to_fwcap(lc->fec_hint); in t4_link_l1cfg()
3966 fec |= fec_to_fwcap(lc->requested_fec & in t4_link_l1cfg()
3968 if (lc->requested_fec & FEC_MODULE) in t4_link_l1cfg()
3969 fec |= fec_to_fwcap(lc->fec_hint); in t4_link_l1cfg()
3982 if (isset(&adap->bt_map, port)) in t4_link_l1cfg()
3983 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; in t4_link_l1cfg()
3986 if ((rcap | lc->pcaps) != lc->pcaps) { in t4_link_l1cfg()
3989 lc->pcaps, rcap & (rcap ^ lc->pcaps)); in t4_link_l1cfg()
3991 rcap &= lc->pcaps; in t4_link_l1cfg()
3999 if (adap->params.port_caps32) { in t4_link_l1cfg()
4011 lc->requested_caps = rcap; in t4_link_l1cfg()
4016 * t4_restart_aneg - restart autonegotiation
4068 return ('-'); in intr_alert_char()
4078 enable = t4_read_reg(adap, ii->enable_reg); in t4_show_intr_info()
4079 if (ii->flags & NONFATAL_IF_DISABLED) in t4_show_intr_info()
4080 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); in t4_show_intr_info()
4082 fatal = ii->fatal; in t4_show_intr_info()
4085 alert, ii->name, ii->cause_reg, cause, enable, fatal); in t4_show_intr_info()
4088 for (details = ii->details; details && details->mask != 0; details++) { in t4_show_intr_info()
4089 u32 msgbits = details->mask & cause; in t4_show_intr_info()
4092 alert = intr_alert_char(msgbits, enable, ii->fatal); in t4_show_intr_info()
4094 details->msg); in t4_show_intr_info()
4117 cause = t4_read_reg(adap, ii->cause_reg); in t4_handle_intr()
4118 if (ii->cause_reg == A_PL_INT_CAUSE) in t4_handle_intr()
4119 cause &= t4_read_reg(adap, ii->enable_reg); in t4_handle_intr()
4122 fatal = cause & ii->fatal; in t4_handle_intr()
4123 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) in t4_handle_intr()
4124 fatal &= t4_read_reg(adap, ii->enable_reg); in t4_handle_intr()
4130 for (action = ii->actions; action && action->mask != 0; action++) { in t4_handle_intr()
4131 if (!(action->mask & cause)) in t4_handle_intr()
4133 rc |= (action->action)(adap, action->arg, verbose); in t4_handle_intr()
4137 t4_write_reg(adap, ii->cause_reg, cause); in t4_handle_intr()
4138 (void)t4_read_reg(adap, ii->cause_reg); in t4_handle_intr()
4191 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, in pcie_intr_handler()
4192 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, in pcie_intr_handler()
4193 { F_MSIXDATAPERR, "MSI-X data parity error" }, in pcie_intr_handler()
4194 { F_MSIXDIPERR, "MSI-X DI parity error" }, in pcie_intr_handler()
4222 { F_NONFATALERR, "PCIe non-fatal error" }, in pcie_intr_handler()
4245 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, in pcie_intr_handler()
4246 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, in pcie_intr_handler()
4247 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, in pcie_intr_handler()
4248 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, in pcie_intr_handler()
4249 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, in pcie_intr_handler()
4335 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
4340 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
4370 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
4375 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
4476 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, in cim_intr_handler()
4494 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, in cim_intr_handler()
4500 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, in cim_intr_handler()
4691 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, in pmtx_dump_dbg_stats()
4711 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, in pmtx_intr_handler()
4751 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, in pmrx_intr_handler()
4793 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, in cplsw_intr_handler()
4842 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, in le_intr_handler()
4843 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, in le_intr_handler()
4844 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, in le_intr_handler()
4845 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, in le_intr_handler()
4900 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, in mps_intr_handler()
5100 "MA address wrap-around error by client %u to address %#x\n", in ma_wrap_status()
5180 * NC-SI interrupt handler.
5185 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, in ncsi_intr_handler()
5186 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, in ncsi_intr_handler()
5187 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, in ncsi_intr_handler()
5188 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, in ncsi_intr_handler()
5306 * t4_slow_intr_handler - control path interrupt handler
5310 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
5341 { F_NCSI, "NC-SI" }, in t4_slow_intr_handler()
5360 { F_ULP_TX, -1, ulptx_intr_handler }, in t4_slow_intr_handler()
5361 { F_SGE, -1, sge_intr_handler }, in t4_slow_intr_handler()
5362 { F_CPL_SWITCH, -1, cplsw_intr_handler }, in t4_slow_intr_handler()
5363 { F_ULP_RX, -1, ulprx_intr_handler }, in t4_slow_intr_handler()
5364 { F_PM_RX, -1, pmrx_intr_handler}, in t4_slow_intr_handler()
5365 { F_PM_TX, -1, pmtx_intr_handler}, in t4_slow_intr_handler()
5366 { F_MA, -1, ma_intr_handler }, in t4_slow_intr_handler()
5367 { F_TP, -1, tp_intr_handler }, in t4_slow_intr_handler()
5368 { F_LE, -1, le_intr_handler }, in t4_slow_intr_handler()
5372 { F_PCIE, -1, pcie_intr_handler }, in t4_slow_intr_handler()
5377 { F_SMB, -1, smb_intr_handler}, in t4_slow_intr_handler()
5378 { F_PL, -1, plpl_intr_handler }, in t4_slow_intr_handler()
5379 { F_NCSI, -1, ncsi_intr_handler}, in t4_slow_intr_handler()
5380 { F_MPS, -1, mps_intr_handler }, in t4_slow_intr_handler()
5381 { F_CIM, -1, cim_intr_handler }, in t4_slow_intr_handler()
5410 * t4_intr_enable - enable interrupts
5413 * Enable PF-specific interrupts for the calling function and the top-level
5419 * non PF-specific interrupts from the various HW modules. Only one PCI
5439 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); in t4_intr_enable()
5443 * t4_intr_disable - disable interrupts
5446 * Disable interrupts. We only disable the top-level interrupt
5454 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); in t4_intr_disable()
5458 * hash_mac_addr - return the hash value of a MAC address
5459 * @addr: the 48-bit Ethernet MAC address
5475 * t4_config_rss_range - configure a portion of the RSS mapping table
5508 * a 32-bit word as 10-bit values with the upper remaining 2 bits in t4_config_rss_range()
5527 n -= nq; in t4_config_rss_range()
5539 * current 3-tuple position within the commad. in t4_config_rss_range()
5545 nq -= nqbuf; in t4_config_rss_range()
5548 nqbuf--; in t4_config_rss_range()
5571 * t4_config_glbl_rss - configure the global RSS mode
5575 * @flags: mode-specific flags
5596 return -EINVAL; in t4_config_glbl_rss()
5601 * t4_config_vi_rss - configure per VI RSS settings
5607 * @skeyidx: RSS secret key table index for non-global mode
5610 * Configures VI-specific RSS properties.
5641 * t4_read_rss - read the contents of the RSS mapping table
5645 * Reads the contents of the RSS hash->queue mapping table.
5651 int rss_nentries = adapter->chip_params->rss_nentries; in t4_read_rss()
5664 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5694 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, in t4_tp_fw_ldst_rw()
5706 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5723 int rc = -EINVAL; in t4_tp_indirect_rw()
5757 * t4_tp_pio_read - Read TP PIO registers
5774 * t4_tp_pio_write - Write TP PIO registers
5791 * t4_tp_tm_pio_read - Read TP TM PIO registers
5808 * t4_tp_mib_read - Read TP MIB registers
5825 * t4_read_rss_key - read the global RSS key
5827 * @key: 10-entry array holding the 320-bit RSS key
5830 * Reads the global 320-bit RSS key.
5838 * t4_write_rss_key - program one of the RSS keys
5840 * @key: 10-entry array holding the 320-bit RSS key
5844 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5855 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), in t4_write_rss_key()
5856 * allows access to key addresses 16-63 by using KeyWrAddrX in t4_write_rss_key()
5877 * t4_read_rss_pf_config - read PF RSS Configuration Table
5893 * t4_write_rss_pf_config - write PF RSS Configuration Table
5910 * t4_read_rss_vf_config - read VF RSS Configuration Table
5948 * t4_write_rss_vf_config - write VF RSS Configuration Table
5987 * t4_read_rss_pf_map - read PF RSS Map
6003 * t4_write_rss_pf_map - write PF RSS Map
6015 * t4_read_rss_pf_mask - read PF RSS Mask
6031 * t4_write_rss_pf_mask - write PF RSS Mask
6043 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
6055 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; in t4_tp_get_tcp_stats()
6057 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) in t4_tp_get_tcp_stats()
6064 v4->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
6065 v4->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
6066 v4->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
6067 v4->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
6072 v6->tcp_out_rsts = STAT(OUT_RST); in t4_tp_get_tcp_stats()
6073 v6->tcp_in_segs = STAT64(IN_SEG); in t4_tp_get_tcp_stats()
6074 v6->tcp_out_segs = STAT64(OUT_SEG); in t4_tp_get_tcp_stats()
6075 v6->tcp_retrans_segs = STAT64(RXT_SEG); in t4_tp_get_tcp_stats()
6083 * t4_tp_get_err_stats - read TP's error MIB counters
6093 int nchan = adap->chip_params->nchan; in t4_tp_get_err_stats()
6095 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, in t4_tp_get_err_stats()
6098 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, in t4_tp_get_err_stats()
6101 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, in t4_tp_get_err_stats()
6104 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, in t4_tp_get_err_stats()
6107 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, in t4_tp_get_err_stats()
6110 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, in t4_tp_get_err_stats()
6113 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, in t4_tp_get_err_stats()
6116 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, in t4_tp_get_err_stats()
6119 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, in t4_tp_get_err_stats()
6124 * t4_tp_get_err_stats - read TP's error MIB counters
6134 int nchan = adap->chip_params->nchan; in t4_tp_get_tnl_stats()
6136 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, in t4_tp_get_tnl_stats()
6138 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, in t4_tp_get_tnl_stats()
6143 * t4_tp_get_proxy_stats - read TP's proxy MIB counters
6152 int nchan = adap->chip_params->nchan; in t4_tp_get_proxy_stats()
6154 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); in t4_tp_get_proxy_stats()
6158 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
6168 int nchan = adap->chip_params->nchan; in t4_tp_get_cpl_stats()
6170 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); in t4_tp_get_cpl_stats()
6172 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); in t4_tp_get_cpl_stats()
6176 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6185 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, in t4_tp_get_rdma_stats()
6190 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6203 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, in t4_get_fcoe_stats()
6206 t4_tp_mib_read(adap, &st->frames_drop, 1, in t4_get_fcoe_stats()
6212 st->octets_ddp = ((u64)val[0] << 32) | val[1]; in t4_get_fcoe_stats()
6216 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6221 * Returns the values of TP's counters for non-TCP directly-placed packets.
6230 st->frames = val[0]; in t4_get_usm_stats()
6231 st->drops = val[1]; in t4_get_usm_stats()
6232 st->octets = ((u64)val[2] << 32) | val[3]; in t4_get_usm_stats()
6236 * t4_tp_get_tid_stats - read TP's tid MIB counters.
6247 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); in t4_tp_get_tid_stats()
6251 * t4_read_mtu_tbl - returns the values in the HW path MTU table
6254 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
6274 * t4_read_cong_tbl - reads the congestion control table
6295 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6312 * init_cong_ctrl - initialize congestion control parameters
6359 * t4_load_mtus - write the MTU and congestion control HW tables
6365 * Write the HW MTU table with the supplied MTUs and the high-speed
6386 log2--; in t4_load_mtus()
6393 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], in t4_load_mtus()
6403 * t4_set_pace_tbl - set the pace table
6418 return -ERANGE; in t4_set_pace_tbl()
6424 return -ERANGE; in t4_set_pace_tbl()
6426 return -ERANGE; in t4_set_pace_tbl()
6434 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6444 unsigned int clk = adap->params.vpd.cclk * 1000; in t4_set_sched_bps()
6448 kbps *= 125; /* -> bytes */ in t4_set_sched_bps()
6454 delta = v >= kbps ? v - kbps : kbps - v; in t4_set_sched_bps()
6464 return -EINVAL; in t4_set_sched_bps()
6467 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); in t4_set_sched_bps()
6478 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6487 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t4_set_sched_ipg()
6493 return -EINVAL; in t4_set_sched_ipg()
6507 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6518 u64 v = (u64)bytes256 * adap->params.vpd.cclk; in chan_rate()
6524 * t4_get_chan_txrate - get the current per channel Tx rates
6539 if (adap->chip_params->nchan > 2) { in t4_get_chan_txrate()
6547 if (adap->chip_params->nchan > 2) { in t4_get_chan_txrate()
6554 * t4_set_trace_filter - configure one of the tracing filters
6572 return -EINVAL; in t4_set_trace_filter()
6581 * TODO - After T4 data book is updated, specify the exact in t4_set_trace_filter()
6584 * See T4 data book - MPS section for a complete description in t4_set_trace_filter()
6595 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) in t4_set_trace_filter()
6596 return -EINVAL; in t4_set_trace_filter()
6603 if (tp->snap_len > 9600 || idx) in t4_set_trace_filter()
6604 return -EINVAL; in t4_set_trace_filter()
6607 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
6608 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || in t4_set_trace_filter()
6609 tp->min_len > M_TFMINPKTSIZE) in t4_set_trace_filter()
6610 return -EINVAL; in t4_set_trace_filter()
6615 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); in t4_set_trace_filter()
6620 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
6621 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
6624 V_TFCAPTUREMAX(tp->snap_len) | in t4_set_trace_filter()
6625 V_TFMINPKTSIZE(tp->min_len)); in t4_set_trace_filter()
6627 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | in t4_set_trace_filter()
6629 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : in t4_set_trace_filter()
6630 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); in t4_set_trace_filter()
6636 * t4_get_trace_filter - query one of the tracing filters
6640 * @enabled: non-zero if the filter is enabled
6656 tp->port = G_TFPORT(ctla); in t4_get_trace_filter()
6657 tp->invert = !!(ctla & F_TFINVERTMATCH); in t4_get_trace_filter()
6660 tp->port = G_T5_TFPORT(ctla); in t4_get_trace_filter()
6661 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); in t4_get_trace_filter()
6663 tp->snap_len = G_TFCAPTUREMAX(ctlb); in t4_get_trace_filter()
6664 tp->min_len = G_TFMINPKTSIZE(ctlb); in t4_get_trace_filter()
6665 tp->skip_ofst = G_TFOFFSET(ctla); in t4_get_trace_filter()
6666 tp->skip_len = G_TFLENGTH(ctla); in t4_get_trace_filter()
6668 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; in t4_get_trace_filter()
6673 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
6674 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
6679 * t4_pmtx_get_stats - returns the HW stats from PMTX
6691 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmtx_get_stats()
6706 * t4_pmrx_get_stats - returns the HW stats from PMRX
6718 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmrx_get_stats()
6733 * t4_get_mps_bg_map - return the buffer groups associated with a port
6745 if (adap->params.mps_bg_map != UINT32_MAX) in t4_get_mps_bg_map()
6746 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); in t4_get_mps_bg_map()
6748 n = adap->params.nports; in t4_get_mps_bg_map()
6758 * TP RX e-channels associated with the port.
6762 const u32 n = adap->params.nports; in t4_get_rx_e_chan_map()
6763 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; in t4_get_rx_e_chan_map()
6773 * TP RX c-channel associated with the port.
6777 if (adap->params.tp_ch_map != UINT32_MAX) in t4_get_rx_c_chan()
6778 return (adap->params.tp_ch_map >> (8 * idx)) & 0xff; in t4_get_rx_c_chan()
6783 * TP TX c-channel associated with the port.
6791 * t4_get_port_type_description - return Port Type string description
6828 * t4_get_port_stats_offset - collect port stats relative to a previous
6846 *s -= *o; in t4_get_port_stats_offset()
6850 * t4_get_port_stats - collect port statistics
6859 struct port_info *pi = adap->port[idx]; in t4_get_port_stats()
6860 u32 bgmap = pi->mps_bg_map; in t4_get_port_stats()
6865 t4_port_reg(adap, pi->tx_chan, A_MPS_PORT_STAT_##name##_L)); in t4_get_port_stats()
6868 p->tx_pause = GET_STAT(TX_PORT_PAUSE); in t4_get_port_stats()
6869 p->tx_octets = GET_STAT(TX_PORT_BYTES); in t4_get_port_stats()
6870 p->tx_frames = GET_STAT(TX_PORT_FRAMES); in t4_get_port_stats()
6871 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); in t4_get_port_stats()
6872 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); in t4_get_port_stats()
6873 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); in t4_get_port_stats()
6874 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); in t4_get_port_stats()
6875 p->tx_frames_64 = GET_STAT(TX_PORT_64B); in t4_get_port_stats()
6876 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); in t4_get_port_stats()
6877 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); in t4_get_port_stats()
6878 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); in t4_get_port_stats()
6879 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); in t4_get_port_stats()
6880 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); in t4_get_port_stats()
6881 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); in t4_get_port_stats()
6882 p->tx_drop = GET_STAT(TX_PORT_DROP); in t4_get_port_stats()
6883 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); in t4_get_port_stats()
6884 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); in t4_get_port_stats()
6885 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); in t4_get_port_stats()
6886 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); in t4_get_port_stats()
6887 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); in t4_get_port_stats()
6888 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); in t4_get_port_stats()
6889 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); in t4_get_port_stats()
6890 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); in t4_get_port_stats()
6894 p->tx_frames -= p->tx_pause; in t4_get_port_stats()
6895 p->tx_octets -= p->tx_pause * 64; in t4_get_port_stats()
6898 p->tx_mcast_frames -= p->tx_pause; in t4_get_port_stats()
6901 p->rx_pause = GET_STAT(RX_PORT_PAUSE); in t4_get_port_stats()
6902 p->rx_octets = GET_STAT(RX_PORT_BYTES); in t4_get_port_stats()
6903 p->rx_frames = GET_STAT(RX_PORT_FRAMES); in t4_get_port_stats()
6904 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); in t4_get_port_stats()
6905 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); in t4_get_port_stats()
6906 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); in t4_get_port_stats()
6907 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); in t4_get_port_stats()
6908 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); in t4_get_port_stats()
6909 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); in t4_get_port_stats()
6910 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); in t4_get_port_stats()
6911 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); in t4_get_port_stats()
6912 p->rx_frames_64 = GET_STAT(RX_PORT_64B); in t4_get_port_stats()
6913 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); in t4_get_port_stats()
6914 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); in t4_get_port_stats()
6915 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); in t4_get_port_stats()
6916 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); in t4_get_port_stats()
6917 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); in t4_get_port_stats()
6918 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); in t4_get_port_stats()
6919 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); in t4_get_port_stats()
6920 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); in t4_get_port_stats()
6921 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); in t4_get_port_stats()
6922 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); in t4_get_port_stats()
6923 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); in t4_get_port_stats()
6924 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); in t4_get_port_stats()
6925 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); in t4_get_port_stats()
6926 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); in t4_get_port_stats()
6928 if (pi->fcs_reg != -1) in t4_get_port_stats()
6929 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; in t4_get_port_stats()
6933 p->rx_frames -= p->rx_pause; in t4_get_port_stats()
6934 p->rx_octets -= p->rx_pause * 64; in t4_get_port_stats()
6937 p->rx_mcast_frames -= p->rx_pause; in t4_get_port_stats()
6940 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6941 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6942 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6943 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6944 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6945 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6946 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6947 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6954 * t4_get_lb_stats - collect loopback port statistics
6969 p->octets = GET_STAT(BYTES); in t4_get_lb_stats()
6970 p->frames = GET_STAT(FRAMES); in t4_get_lb_stats()
6971 p->bcast_frames = GET_STAT(BCAST); in t4_get_lb_stats()
6972 p->mcast_frames = GET_STAT(MCAST); in t4_get_lb_stats()
6973 p->ucast_frames = GET_STAT(UCAST); in t4_get_lb_stats()
6974 p->error_frames = GET_STAT(ERROR); in t4_get_lb_stats()
6976 p->frames_64 = GET_STAT(64B); in t4_get_lb_stats()
6977 p->frames_65_127 = GET_STAT(65B_127B); in t4_get_lb_stats()
6978 p->frames_128_255 = GET_STAT(128B_255B); in t4_get_lb_stats()
6979 p->frames_256_511 = GET_STAT(256B_511B); in t4_get_lb_stats()
6980 p->frames_512_1023 = GET_STAT(512B_1023B); in t4_get_lb_stats()
6981 p->frames_1024_1518 = GET_STAT(1024B_1518B); in t4_get_lb_stats()
6982 p->frames_1519_max = GET_STAT(1519B_MAX); in t4_get_lb_stats()
6983 p->drop = GET_STAT(DROP_FRAMES); in t4_get_lb_stats()
6985 if (idx < adap->params.nports) { in t4_get_lb_stats()
6986 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; in t4_get_lb_stats()
6988 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6989 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6990 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6991 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6992 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6993 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6994 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6995 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
7003 * t4_wol_magic_enable - enable/disable magic packet WoL
7008 * Enables/disables magic packet wake-on-LAN for the selected port.
7037 * t4_wol_pat_enable - enable/disable pattern-based WoL
7041 * @mask0: byte mask for bytes 0-63 of a packet
7042 * @mask1: byte mask for bytes 64-127 of a packet
7048 * the resulting packet against @crc. If @enable is %true pattern-based
7067 return -EINVAL; in t4_wol_pat_enable()
7086 return -ETIMEDOUT; in t4_wol_pat_enable()
7093 return -ETIMEDOUT; in t4_wol_pat_enable()
7101 /* t4_mk_filtdelwr - create a delete filter WR
7112 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); in t4_mk_filtdelwr()
7113 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); in t4_mk_filtdelwr()
7114 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | in t4_mk_filtdelwr()
7116 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); in t4_mk_filtdelwr()
7118 wr->rx_chan_rx_rpl_iq = in t4_mk_filtdelwr()
7149 * t4_mdio_rd - read a PHY register through MDIO
7183 * t4_mdio_wr - write a PHY register through MDIO
7215 * t4_sge_decode_idma_state - decode the idma state
7371 * t4_sge_ctxt_flush - flush the SGE context cache
7399 * t4_fw_hello - establish communication with FW
7404 * @state: returns the current device state (if non-NULL)
7439 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) in t4_fw_hello()
7459 * Note that we also do this wait if we're a non-Master-capable PF and in t4_fw_hello()
7481 waiting -= 50; in t4_fw_hello()
7492 if (retries-- > 0) in t4_fw_hello()
7495 return -ETIMEDOUT; in t4_fw_hello()
7527 * t4_fw_bye - end communication with FW
7543 * t4_fw_reset - issue a reset to FW
7561 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7584 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { in t4_fw_halt()
7621 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7630 int ms; in t4_fw_restart() local
7633 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { in t4_fw_restart()
7637 ms += 100; in t4_fw_restart()
7640 return -ETIMEDOUT; in t4_fw_restart()
7644 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7669 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; in t4_fw_upgrade()
7673 return -EINVAL; in t4_fw_upgrade()
7689 * t4_fw_initialize - ask FW to initialize the device
7706 * t4_query_params_rw - query FW or device parameters
7728 return -EINVAL; in t4_query_params_rw()
7768 * t4_set_params_timeout - sets FW or device parameters
7790 return -EINVAL; in t4_set_params_timeout()
7799 while (nparams--) { in t4_set_params_timeout()
7808 * t4_set_params - sets FW or device parameters
7829 * t4_cfg_pfvf - configure PF/VF resource limits
7836 * @rxqi: the max number of interrupt-capable ingress queues
7877 * t4_alloc_vi_func - allocate a virtual interface
7892 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7894 * Returns a negative error number or the non-negative VI id.
7913 c.nmac = nmac - 1; in t4_alloc_vi_func()
7938 *vfvld = adap->params.viid_smt_extn_support ? in t4_alloc_vi_func()
7943 *vin = adap->params.viid_smt_extn_support ? in t4_alloc_vi_func()
7952 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7975 * t4_free_vi - free a virtual interface
8002 * t4_set_rxmode - set Rx properties of a virtual interface
8006 * @mtu: the new MTU or -1
8007 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
8008 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
8009 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
8010 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
8048 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
8080 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_alloc_encap_mac_filt()
8082 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_alloc_encap_mac_filt()
8083 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); in t4_alloc_encap_mac_filt()
8085 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | in t4_alloc_encap_mac_filt()
8088 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); in t4_alloc_encap_mac_filt()
8090 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_encap_mac_filt()
8092 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_alloc_encap_mac_filt()
8097 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
8129 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); in t4_alloc_raw_mac_filt()
8132 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | in t4_alloc_raw_mac_filt()
8135 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | in t4_alloc_raw_mac_filt()
8139 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
8140 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
8142 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_raw_mac_filt()
8144 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); in t4_alloc_raw_mac_filt()
8146 ret = -ENOMEM; in t4_alloc_raw_mac_filt()
8153 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
8164 * Allocates an exact-match filter for each of the supplied addresses and
8181 unsigned int max_naddr = adap->chip_params->mps_tcam_size; in t4_alloc_mac_filt()
8185 return -EINVAL; in t4_alloc_mac_filt()
8206 p->valid_to_idx = in t4_alloc_mac_filt()
8209 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_alloc_mac_filt()
8218 if (ret && ret != -FW_ENOMEM) in t4_alloc_mac_filt()
8223 be16_to_cpu(p->valid_to_idx)); in t4_alloc_mac_filt()
8237 rem -= fw_naddr; in t4_alloc_mac_filt()
8240 if (ret == 0 || ret == -FW_ENOMEM) in t4_alloc_mac_filt()
8246 * t4_free_encap_mac_filt - frees MPS entry at given index
8276 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_free_encap_mac_filt()
8278 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_free_encap_mac_filt()
8280 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_encap_mac_filt()
8285 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
8317 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | in t4_free_raw_mac_filt()
8321 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | in t4_free_raw_mac_filt()
8324 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | in t4_free_raw_mac_filt()
8328 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
8329 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
8331 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_raw_mac_filt()
8335 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8343 * Frees the exact-match filter for each of the supplied addresses
8354 unsigned int max_naddr = adap->chip_params->mps_tcam_size; in t4_free_mac_filt()
8358 return -EINVAL; in t4_free_mac_filt()
8380 p->valid_to_idx = cpu_to_be16( in t4_free_mac_filt()
8383 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); in t4_free_mac_filt()
8392 be16_to_cpu(p->valid_to_idx)); in t4_free_mac_filt()
8399 rem -= fw_naddr; in t4_free_mac_filt()
8408 * t4_change_mac - modifies the exact-match filter for a MAC address
8412 * @idx: index of existing filter for old value of MAC address, or -1
8417 * Modifies an exact-match filter and sets it to the new MAC address if
8435 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_change_mac()
8446 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_change_mac()
8449 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_change_mac()
8453 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_change_mac()
8455 ret = -ENOMEM; in t4_change_mac()
8457 if (adap->params.viid_smt_extn_support) in t4_change_mac()
8471 * t4_set_addr_hash - program the MAC inexact-match hash filter
8479 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8499 * t4_enable_vi_params - enable/disable a virtual interface
8527 * t4_enable_vi - enable/disable a virtual interface
8544 * t4_identify_port - identify a VI's port by blinking its LED
8567 * t4_iq_stop - stop an ingress queue and its FLs
8600 * t4_iq_free - free an ingress queue and its FLs
8631 * t4_eth_eq_stop - stop an Ethernet egress queue
8657 * t4_eth_eq_free - free an Ethernet egress queue
8682 * t4_ctrl_eq_free - free a control egress queue
8707 * t4_ofld_eq_free - free an offload egress queue
8732 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8742 "Auto-negotiation Failure", in t4_link_down_rc_str()
8835 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8839 * 32-bit Port Capabilities value.
8847 * 16-bit Port Information message isn't the same as the in lstatus_to_fwcap()
8848 * 16-bit Port Capabilities bitfield used everywhere else ... in lstatus_to_fwcap()
8872 * based on information provided by the firmware. Does not touch any
8878 struct link_config old_lc, *lc = &pi->link_cfg; in handle_port_info()
8883 old_ptype = pi->port_type; in handle_port_info()
8884 old_mtype = pi->mod_type; in handle_port_info()
8887 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); in handle_port_info()
8889 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); in handle_port_info()
8890 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); in handle_port_info()
8891 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? in handle_port_info()
8892 G_FW_PORT_CMD_MDIOADDR(stat) : -1; in handle_port_info()
8894 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); in handle_port_info()
8895 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); in handle_port_info()
8896 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); in handle_port_info()
8897 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; in handle_port_info()
8898 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); in handle_port_info()
8902 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); in handle_port_info()
8904 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); in handle_port_info()
8905 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); in handle_port_info()
8906 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? in handle_port_info()
8907 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; in handle_port_info()
8909 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); in handle_port_info()
8910 lc->acaps = be32_to_cpu(p->u.info32.acaps32); in handle_port_info()
8911 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); in handle_port_info()
8912 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; in handle_port_info()
8913 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); in handle_port_info()
8915 linkattr = be32_to_cpu(p->u.info32.linkattr32); in handle_port_info()
8917 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); in handle_port_info()
8921 lc->speed = fwcap_to_speed(linkattr); in handle_port_info()
8922 lc->fec = fwcap_to_fec(linkattr, true); in handle_port_info()
8929 lc->fc = fc; in handle_port_info()
8935 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || in handle_port_info()
8936 old_lc.pcaps != lc->pcaps) { in handle_port_info()
8937 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) in handle_port_info()
8938 lc->fec_hint = fwcap_to_fec(lc->acaps, true); in handle_port_info()
8942 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || in handle_port_info()
8943 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { in handle_port_info()
8950 * t4_update_port_info - retrieve and update port information if changed
8959 struct adapter *sc = pi->adapter; in t4_update_port_info()
8967 V_FW_PORT_CMD_PORTID(pi->tx_chan)); in t4_update_port_info()
8968 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : in t4_update_port_info()
8972 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); in t4_update_port_info()
8981 * t4_handle_fw_rpl - process a FW reply message
8992 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); in t4_handle_fw_rpl()
9000 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); in t4_handle_fw_rpl()
9005 if (pi->tx_chan == chan) in t4_handle_fw_rpl()
9021 return -EINVAL; in t4_handle_fw_rpl()
9027 * get_pci_mode - determine a card's PCI mode
9043 p->speed = val & PCI_EXP_LNKSTA_CLS; in get_pci_mode()
9044 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; in get_pci_mode()
9056 * Table for non-standard supported Flash parts. Note, all Flash in t4_get_flash_params()
9083 * Check to see if it's one of our non-standard supported Flash parts. in t4_get_flash_params()
9087 adapter->params.sf_size = in t4_get_flash_params()
9089 adapter->params.sf_nsec = in t4_get_flash_params()
9090 adapter->params.sf_size / SF_SEC_SIZE; in t4_get_flash_params()
9107 * This Density -> Size decoding table is taken from Micron in t4_get_flash_params()
9124 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ in t4_get_flash_params()
9126 * This Density -> Size decoding table is taken from ISSI in t4_get_flash_params()
9138 * This Density -> Size decoding table is taken from Macronix in t4_get_flash_params()
9150 * This Density -> Size decoding table is taken from Winbond in t4_get_flash_params()
9175 adapter->params.sf_size = size; in t4_get_flash_params()
9176 adapter->params.sf_nsec = size / SF_SEC_SIZE; in t4_get_flash_params()
9184 if (adapter->params.sf_size < FLASH_MIN_SIZE) in t4_get_flash_params()
9186 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); in t4_get_flash_params()
9256 chipid -= CHELSIO_T4; in t4_get_chip_params()
9264 * t4_prep_adapter - prepare SW and HW for operation
9278 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
9281 adapter->params.chipid = G_CHIPID(pl_rev); in t4_prep_adapter()
9282 adapter->params.rev = G_REV(pl_rev); in t4_prep_adapter()
9283 if (adapter->params.chipid == 0) { in t4_prep_adapter()
9285 adapter->params.chipid = CHELSIO_T4; in t4_prep_adapter()
9288 if (adapter->params.rev == 1) { in t4_prep_adapter()
9290 return -EINVAL; in t4_prep_adapter()
9294 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); in t4_prep_adapter()
9295 if (adapter->chip_params == NULL) in t4_prep_adapter()
9296 return -EINVAL; in t4_prep_adapter()
9298 adapter->params.pci.vpd_cap_addr = in t4_prep_adapter()
9308 adapter->params.cim_la_size = adapter->chip_params->cim_la_size; in t4_prep_adapter()
9311 adapter->params.fpga = 1; in t4_prep_adapter()
9312 adapter->params.cim_la_size = 2 * adapter->chip_params->cim_la_size; in t4_prep_adapter()
9315 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); in t4_prep_adapter()
9319 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
9324 adapter->params.nports = 1; in t4_prep_adapter()
9325 adapter->params.portvec = 1; in t4_prep_adapter()
9326 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
9334 * t4_shutdown_adapter - shut down adapter, host & wire
9342 * the port Link Status to go down -- if register writes work --
9348 const bool bt = adapter->bt_map != 0; in t4_shutdown_adapter()
9377 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9417 return -EINVAL; in t4_bar2_sge_qregs()
9421 page_shift = adapter->params.sge.page_shift; in t4_bar2_sge_qregs()
9427 ? adapter->params.sge.eq_s_qpp in t4_bar2_sge_qregs()
9428 : adapter->params.sge.iq_s_qpp); in t4_bar2_sge_qregs()
9429 qpp_mask = (1 << qpp_shift) - 1; in t4_bar2_sge_qregs()
9451 * from the writes to the registers -- the Write Combined Doorbell in t4_bar2_sge_qregs()
9469 * t4_init_devlog_params - initialize adapter->params.devlog
9478 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
9493 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); in t4_init_devlog_params()
9494 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; in t4_init_devlog_params()
9498 dparams->size = nentries * sizeof(struct fw_devlog_e); in t4_init_devlog_params()
9513 return -ENXIO; in t4_init_devlog_params()
9521 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
9528 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); in t4_init_devlog_params()
9529 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; in t4_init_devlog_params()
9530 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); in t4_init_devlog_params()
9536 * t4_init_sge_params - initialize adap->params.sge
9544 struct sge_params *sp = &adapter->params.sge; in t4_init_sge_params()
9548 sp->counter_val[0] = G_THRESHOLD_0(r); in t4_init_sge_params()
9549 sp->counter_val[1] = G_THRESHOLD_1(r); in t4_init_sge_params()
9550 sp->counter_val[2] = G_THRESHOLD_2(r); in t4_init_sge_params()
9551 sp->counter_val[3] = G_THRESHOLD_3(r); in t4_init_sge_params()
9563 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; in t4_init_sge_params()
9564 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; in t4_init_sge_params()
9566 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; in t4_init_sge_params()
9567 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; in t4_init_sge_params()
9569 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; in t4_init_sge_params()
9570 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; in t4_init_sge_params()
9573 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; in t4_init_sge_params()
9575 sp->fl_starve_threshold2 = sp->fl_starve_threshold; in t4_init_sge_params()
9577 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; in t4_init_sge_params()
9579 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; in t4_init_sge_params()
9584 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; in t4_init_sge_params()
9585 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; in t4_init_sge_params()
9590 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; in t4_init_sge_params()
9591 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; in t4_init_sge_params()
9595 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; in t4_init_sge_params()
9596 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; in t4_init_sge_params()
9599 sp->sge_control = r; in t4_init_sge_params()
9600 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; in t4_init_sge_params()
9601 sp->fl_pktshift = G_PKTSHIFT(r); in t4_init_sge_params()
9603 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + in t4_init_sge_params()
9606 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + in t4_init_sge_params()
9610 sp->pack_boundary = sp->pad_boundary; in t4_init_sge_params()
9614 sp->pack_boundary = 16; in t4_init_sge_params()
9616 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); in t4_init_sge_params()
9619 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, in t4_init_sge_params()
9638 mask = (1 << width[i]) - 1; in hashmask_to_filtermask()
9655 struct tp_params *tpp = &adap->params.tp; in read_filter_mode_and_ingress_config()
9664 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); in read_filter_mode_and_ingress_config()
9666 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); in read_filter_mode_and_ingress_config()
9667 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); in read_filter_mode_and_ingress_config()
9668 tpp->vnic_mode = val[1]; in read_filter_mode_and_ingress_config()
9675 tpp->filter_mode = v & 0xffff; in read_filter_mode_and_ingress_config()
9684 tpp->filter_mask = hashmask_to_filtermask(hash_mask, in read_filter_mode_and_ingress_config()
9685 tpp->filter_mode); in read_filter_mode_and_ingress_config()
9689 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; in read_filter_mode_and_ingress_config()
9691 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; in read_filter_mode_and_ingress_config()
9699 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); in read_filter_mode_and_ingress_config()
9700 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); in read_filter_mode_and_ingress_config()
9701 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); in read_filter_mode_and_ingress_config()
9702 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); in read_filter_mode_and_ingress_config()
9703 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); in read_filter_mode_and_ingress_config()
9704 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); in read_filter_mode_and_ingress_config()
9705 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); in read_filter_mode_and_ingress_config()
9706 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); in read_filter_mode_and_ingress_config()
9707 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); in read_filter_mode_and_ingress_config()
9708 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); in read_filter_mode_and_ingress_config()
9712 * t4_init_tp_params - initialize adap->params.tp
9720 struct tp_params *tpp = &adap->params.tp; in t4_init_tp_params()
9723 tpp->tre = G_TIMERRESOLUTION(v); in t4_init_tp_params()
9724 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); in t4_init_tp_params()
9730 tpp->rx_pkt_encap = v & F_CRXPKTENC; in t4_init_tp_params()
9732 tpp->rx_pkt_encap = false; in t4_init_tp_params()
9746 tpp->max_tx_pdu = tx_len; in t4_init_tp_params()
9747 tpp->max_rx_pdu = rx_len; in t4_init_tp_params()
9753 * t4_filter_field_shift - calculate filter field shift
9763 const unsigned int filter_mode = adap->params.tp.filter_mode; in t4_filter_field_shift()
9768 return -1; in t4_filter_field_shift()
9813 struct vi_info *vi = &p->vi[0]; in t4_port_init()
9815 for (i = 0, j = -1; i <= p->port_id; i++) { in t4_port_init()
9818 } while ((adap->params.portvec & (1 << j)) == 0); in t4_port_init()
9821 p->tx_chan = t4_get_tx_c_chan(adap, j); in t4_port_init()
9822 p->rx_chan = t4_get_rx_c_chan(adap, j); in t4_port_init()
9823 p->mps_bg_map = t4_get_mps_bg_map(adap, j); in t4_port_init()
9824 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); in t4_port_init()
9825 p->lport = j; in t4_port_init()
9827 if (!(adap->flags & IS_VF) || in t4_port_init()
9828 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { in t4_port_init()
9832 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, in t4_port_init()
9833 &vi->vfvld, &vi->vin); in t4_port_init()
9837 vi->viid = ret; in t4_port_init()
9842 V_FW_PARAMS_PARAM_YZ(vi->viid); in t4_port_init()
9845 vi->rss_base = 0xffff; in t4_port_init()
9848 vi->rss_base = val & 0xffff; in t4_port_init()
9855 * t4_read_cimq_cfg - read CIM queue configuration
9867 int cim_num_obq = adap->chip_params->cim_num_obq; in t4_read_cimq_cfg()
9873 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9876 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ in t4_read_cimq_cfg()
9882 /* value is in 256-byte units */ in t4_read_cimq_cfg()
9889 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9893 * @n: capacity of @data in 32-bit words
9897 * error and the number of 32-bit words actually read on success.
9906 return -EINVAL; in t4_read_cim_ibq()
9912 /* It might take 3-10ms before the IBQ debug read access is allowed. in t4_read_cim_ibq()
9931 * t4_read_cim_obq - read the contents of a CIM outbound queue
9935 * @n: capacity of @data in 32-bit words
9939 * error and the number of 32-bit words actually read on success.
9945 int cim_num_obq = adap->chip_params->cim_num_obq; in t4_read_cim_obq()
9947 if ((qid > (cim_num_obq - 1)) || (n & 3)) in t4_read_cim_obq()
9948 return -EINVAL; in t4_read_cim_obq()
9954 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ in t4_read_cim_obq()
9981 * t4_cim_read - read a block from CIM internal address space
9987 * Reads a block of 4-byte words from the CIM intenal address space.
9995 return -EBUSY; in t4_cim_read()
9997 for ( ; !ret && n--; addr += 4) { in t4_cim_read()
10008 * t4_cim_write - write a block into CIM internal address space
10014 * Writes a block of 4-byte words into the CIM intenal address space.
10022 return -EBUSY; in t4_cim_write()
10024 for ( ; !ret && n--; addr += 4) { in t4_cim_write()
10040 * t4_cim_ctl_read - read a block from CIM control region
10046 * Reads a block of 4-byte words from the CIM control region.
10055 * t4_cim_read_la - read CIM LA capture buffer
10087 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
10096 ret = -ETIMEDOUT; in t4_cim_read_la()
10103 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to in t4_cim_read_la()
10104 * identify the 32-bit portion of the full 312-bit data in t4_cim_read_la()
10124 * t4_tp_read_la - read TP LA capture buffer
10141 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); in t4_tp_read_la()
10153 val |= adap->params.tp.la_mask; in t4_tp_read_la()
10163 la_buf[TPLA_SIZE - 1] = ~0ULL; in t4_tp_read_la()
10167 cfg | adap->params.tp.la_mask); in t4_tp_read_la()
10182 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10203 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ in t4_idma_monitor_init()
10204 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; in t4_idma_monitor_init()
10208 * t4_idma_monitor - monitor SGE Ingress DMA state
10240 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { in t4_idma_monitor()
10241 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) in t4_idma_monitor()
10244 i, idma->idma_qid[i], in t4_idma_monitor()
10245 idma->idma_stalled[i]/hz); in t4_idma_monitor()
10246 idma->idma_stalled[i] = 0; in t4_idma_monitor()
10259 if (idma->idma_stalled[i] == 0) { in t4_idma_monitor()
10260 idma->idma_stalled[i] = hz; in t4_idma_monitor()
10261 idma->idma_warn[i] = 0; in t4_idma_monitor()
10263 idma->idma_stalled[i] += ticks; in t4_idma_monitor()
10264 idma->idma_warn[i] -= ticks; in t4_idma_monitor()
10267 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) in t4_idma_monitor()
10272 if (idma->idma_warn[i] > 0) in t4_idma_monitor()
10274 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; in t4_idma_monitor()
10282 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; in t4_idma_monitor()
10286 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; in t4_idma_monitor()
10290 i, idma->idma_qid[i], idma->idma_state[i], in t4_idma_monitor()
10291 idma->idma_stalled[i]/hz, in t4_idma_monitor()
10293 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); in t4_idma_monitor()
10298 * t4_set_vf_mac - Set MAC address for the specified VF
10336 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); in t4_set_vf_mac()
10340 * t4_read_pace_tbl - read the pace table
10358 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10372 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; in t4_get_tx_sched()
10381 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ in t4_get_tx_sched()
10386 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; in t4_get_tx_sched()
10396 * t4_load_cfg - download config file
10408 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_cfg()
10420 return -EFBIG; in t4_load_cfg()
10426 flash_cfg_start_sec + i - 1); in t4_load_cfg()
10429 * with the on-adapter Firmware Configuration File. in t4_load_cfg()
10436 if ( (size - i) < SF_PAGE_SIZE) in t4_load_cfg()
10437 n = size - i; in t4_load_cfg()
10456 * t5_fw_init_extern_mem - initialize the external memory
10472 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, in t5_fw_init_extern_mem()
10507 * 0x2-0xFFFF: Reserved
10528 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10530 * 0x02: Hewlett-Packard PA RISC. HP reserved
10532 * 0x04-0xFF: Reserved.
10550 * modify_device_id - Modifies the device ID of the Boot BIOS image
10568 le16_to_cpu(*(u16*)header->pcir_offset)]; in modify_device_id()
10575 * 0x04-0xFF: Do not modify in modify_device_id()
10577 if (pcir_header->code_type == 0x00) { in modify_device_id()
10584 *(u16*) pcir_header->device_id = device_id; in modify_device_id()
10590 header->cksum = 0x0; in modify_device_id()
10595 for (i = 0; i < (header->size512 * 512); i++) in modify_device_id()
10602 boot_data[cur_header + 7] = -csum; in modify_device_id()
10604 } else if (pcir_header->code_type == 0x03) { in modify_device_id()
10609 *(u16*) pcir_header->device_id = device_id; in modify_device_id()
10618 if (pcir_header->indicator & 0x80) in modify_device_id()
10624 cur_header += header->size512 * 512; in modify_device_id()
10629 * t4_load_boot - download boot flash
10636 * The boot image has the following sections: a 28-byte header and the
10649 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_boot()
10656 return -EFBIG; in t4_load_boot()
10660 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, in t4_load_boot()
10667 (boot_sector >> 16) + i - 1); in t4_load_boot()
10671 * with the on-adapter option ROM file in t4_load_boot()
10678 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); in t4_load_boot()
10689 return -EFBIG; in t4_load_boot()
10696 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { in t4_load_boot()
10698 return -EINVAL; in t4_load_boot()
10704 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { in t4_load_boot()
10706 return -EINVAL; in t4_load_boot()
10712 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { in t4_load_boot()
10714 return -EINVAL; in t4_load_boot()
10728 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { in t4_load_boot()
10743 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { in t4_load_boot()
10761 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10771 * If the device FLASH isn't large enough to hold a Firmware in t4_flash_bootcfg_addr()
10774 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) in t4_flash_bootcfg_addr()
10775 return -ENOSPC; in t4_flash_bootcfg_addr()
10785 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_bootcfg()
10797 return -EFBIG; in t4_load_bootcfg()
10803 flash_cfg_start_sec + i - 1); in t4_load_bootcfg()
10807 * with the on-adapter OptionROM Configuration File. in t4_load_bootcfg()
10814 if ( (size - i) < SF_PAGE_SIZE) in t4_load_bootcfg()
10815 n = size - i; in t4_load_bootcfg()
10834 * t4_set_filter_cfg - set up filter mode/mask and ingress config.
10851 const int maxbits = adap->chip_params->filter_opt_len; in t4_set_filter_cfg()
10853 if (mode != -1 || mask != -1) { in t4_set_filter_cfg()
10854 if (mode != -1) { in t4_set_filter_cfg()
10866 return -E2BIG; in t4_set_filter_cfg()
10884 fmask = fmode & adap->params.tp.filter_mask; in t4_set_filter_cfg()
10885 if (fmask != adap->params.tp.filter_mask) { in t4_set_filter_cfg()
10889 adap->params.tp.filter_mask, fmask, fmode); in t4_set_filter_cfg()
10892 fmode = adap->params.tp.filter_mode; in t4_set_filter_cfg()
10898 return -EINVAL; in t4_set_filter_cfg()
10907 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
10913 if (vnic_mode != -1) { in t4_set_filter_cfg()
10918 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
10931 * t4_clr_port_stats - clear port statistics
10940 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; in t4_clr_port_stats()
10964 * t4_i2c_io - read/write I2C data from adapter
10966 * @port: Port number if per-port device; <0 if not
10967 * @devid: per-port device ID or absolute device ID
10985 return -EINVAL; in t4_i2c_io()
10989 return -EINVAL; in t4_i2c_io()
11019 len -= i2c_len; in t4_i2c_io()
11042 * t4_sge_ctxt_rd - read an SGE context through FW
11086 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
11123 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_config()
11154 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params()
11176 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_ch_rl()
11186 return -EINVAL; in t4_sched_params_cl_wrr()
11201 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_cl_wrr()
11227 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), in t4_sched_params_cl_rl_kbps()
11232 * t4_config_watchdog - configure (enable/disable) a watchdog timer
11237 * @timeout: watchdog timeout in ms
11241 * action. Configure one of the watchdog timers by setting a non-zero
11252 * The watchdog command expects a timeout in units of 10ms so we need in t4_config_watchdog()
11253 * to convert it here (via rounding) and force a minimum of one 10ms in t4_config_watchdog()
11254 * "tick" if the timeout is non-zero but the conversion results in 0 in t4_config_watchdog()
11283 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, in t4_get_devlog_level()
11302 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, in t4_set_devlog_level()
11311 adap->params.smac_add_support = 0; in t4_configure_add_smac()
11320 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_add_smac()
11325 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, in t4_configure_add_smac()
11331 adap->params.smac_add_support = 1; in t4_configure_add_smac()
11349 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
11361 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
11373 * t4_set_vlan_acl - Set a VLAN id for the specified VF
11406 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); in t4_set_vlan_acl()
11410 * t4_del_mac - Removes the exact-match filter for a MAC address
11417 * Modifies an exact-match filter and sets it to the new MAC address if
11430 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_del_mac()
11440 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_del_mac()
11441 p->valid_to_idx = cpu_to_be16( in t4_del_mac()
11447 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_del_mac()
11449 return -ENOMEM; in t4_del_mac()
11456 * t4_add_mac - Adds an exact-match filter for a MAC address
11460 * @idx: index of existing filter for old value of MAC address, or -1
11466 * Modifies an exact-match filter and sets it to the new MAC address if
11479 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; in t4_add_mac()
11492 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | in t4_add_mac()
11495 memcpy(p->macaddr, addr, sizeof(p->macaddr)); in t4_add_mac()
11499 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); in t4_add_mac()
11501 return -ENOMEM; in t4_add_mac()
11504 if (adap->params.viid_smt_extn_support) in t4_add_mac()