Lines Matching +full:0 +full:x27200
46 } while (0)
60 * at the time it indicated completion is stored there. Returns 0 if the
72 return 0; in t4_wait_op_done_val()
74 if (--attempts == 0) in t4_wait_op_done_val()
179 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
181 * F_ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
184 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); in t4_hw_pci_read_cfg4()
213 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", in t4_report_fw_error()
291 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); in check_tx_state()
298 #define X_CIM_PF_NOACCESS 0xeeeeeeee
321 * The return value is 0 on success or a negative errno on failure. A
350 if (size <= 0 || (size & 15) || size > MBOX_LEN) in t4_wr_mbox_meat_timeout()
364 if (timeout < 0) { in t4_wr_mbox_meat_timeout()
372 pcie_fw = 0; in t4_wr_mbox_meat_timeout()
378 for (i = 0; i < 4; i++) { in t4_wr_mbox_meat_timeout()
412 memset(cmd_rpl, 0, sizeof(cmd_rpl)); in t4_wr_mbox_meat_timeout()
414 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); in t4_wr_mbox_meat_timeout()
415 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) in t4_wr_mbox_meat_timeout()
435 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ in t4_wr_mbox_meat_timeout()
437 delay_idx = 0; in t4_wr_mbox_meat_timeout()
438 ms = delay[0]; in t4_wr_mbox_meat_timeout()
444 for (i = 0; i < timeout; i += ms) { in t4_wr_mbox_meat_timeout()
452 check_tx_state(adap, &tx_state[0]); in t4_wr_mbox_meat_timeout()
479 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); in t4_wr_mbox_meat_timeout()
482 res = be64_to_cpu(cmd_rpl[0]); in t4_wr_mbox_meat_timeout()
497 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", in t4_wr_mbox_meat_timeout()
499 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); in t4_wr_mbox_meat_timeout()
523 return 0; in t4_edc_err_read()
527 return 0; in t4_edc_err_read()
534 "edc%d err addr 0x%x: 0x%x.\n", in t4_edc_err_read()
538 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", in t4_edc_err_read()
550 return 0; in t4_edc_err_read()
589 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); in t4_mc_read()
591 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); in t4_mc_read()
594 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); in t4_mc_read()
600 for (i = 15; i >= 0; i--) in t4_mc_read()
605 return 0; in t4_mc_read()
654 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); in t4_edc_read()
656 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); in t4_edc_read()
659 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); in t4_edc_read()
665 for (i = 15; i >= 0; i--) in t4_edc_read()
670 return 0; in t4_edc_read()
674 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer
697 if ((addr & 0x3) || (len & 0x3)) in t4_mem_read()
709 for (pos = start; pos < end; pos += 64, offset = 0) { in t4_mem_read()
725 while (offset < 16 && len > 0) { in t4_mem_read()
731 return 0; in t4_mem_read()
736 * Function. We try first via a Firmware LDST Command (if fw_attach != 0)
744 * If fw_attach != 0, construct and send the Firmware LDST Command to in t4_read_pcie_cfg4()
747 if (drv_fw_attach != 0) { in t4_read_pcie_cfg4()
751 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); in t4_read_pcie_cfg4()
769 if (ret == 0) in t4_read_pcie_cfg4()
770 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); in t4_read_pcie_cfg4()
809 return 0; in t4_get_regs_len()
825 0x1008, 0x1108, in t4_get_regs()
826 0x1180, 0x1184, in t4_get_regs()
827 0x1190, 0x1194, in t4_get_regs()
828 0x11a0, 0x11a4, in t4_get_regs()
829 0x11b0, 0x11b4, in t4_get_regs()
830 0x11fc, 0x123c, in t4_get_regs()
831 0x1300, 0x173c, in t4_get_regs()
832 0x1800, 0x18fc, in t4_get_regs()
833 0x3000, 0x30d8, in t4_get_regs()
834 0x30e0, 0x30e4, in t4_get_regs()
835 0x30ec, 0x5910, in t4_get_regs()
836 0x5920, 0x5924, in t4_get_regs()
837 0x5960, 0x5960, in t4_get_regs()
838 0x5968, 0x5968, in t4_get_regs()
839 0x5970, 0x5970, in t4_get_regs()
840 0x5978, 0x5978, in t4_get_regs()
841 0x5980, 0x5980, in t4_get_regs()
842 0x5988, 0x5988, in t4_get_regs()
843 0x5990, 0x5990, in t4_get_regs()
844 0x5998, 0x5998, in t4_get_regs()
845 0x59a0, 0x59d4, in t4_get_regs()
846 0x5a00, 0x5ae0, in t4_get_regs()
847 0x5ae8, 0x5ae8, in t4_get_regs()
848 0x5af0, 0x5af0, in t4_get_regs()
849 0x5af8, 0x5af8, in t4_get_regs()
850 0x6000, 0x6098, in t4_get_regs()
851 0x6100, 0x6150, in t4_get_regs()
852 0x6200, 0x6208, in t4_get_regs()
853 0x6240, 0x6248, in t4_get_regs()
854 0x6280, 0x62b0, in t4_get_regs()
855 0x62c0, 0x6338, in t4_get_regs()
856 0x6370, 0x638c, in t4_get_regs()
857 0x6400, 0x643c, in t4_get_regs()
858 0x6500, 0x6524, in t4_get_regs()
859 0x6a00, 0x6a04, in t4_get_regs()
860 0x6a14, 0x6a38, in t4_get_regs()
861 0x6a60, 0x6a70, in t4_get_regs()
862 0x6a78, 0x6a78, in t4_get_regs()
863 0x6b00, 0x6b0c, in t4_get_regs()
864 0x6b1c, 0x6b84, in t4_get_regs()
865 0x6bf0, 0x6bf8, in t4_get_regs()
866 0x6c00, 0x6c0c, in t4_get_regs()
867 0x6c1c, 0x6c84, in t4_get_regs()
868 0x6cf0, 0x6cf8, in t4_get_regs()
869 0x6d00, 0x6d0c, in t4_get_regs()
870 0x6d1c, 0x6d84, in t4_get_regs()
871 0x6df0, 0x6df8, in t4_get_regs()
872 0x6e00, 0x6e0c, in t4_get_regs()
873 0x6e1c, 0x6e84, in t4_get_regs()
874 0x6ef0, 0x6ef8, in t4_get_regs()
875 0x6f00, 0x6f0c, in t4_get_regs()
876 0x6f1c, 0x6f84, in t4_get_regs()
877 0x6ff0, 0x6ff8, in t4_get_regs()
878 0x7000, 0x700c, in t4_get_regs()
879 0x701c, 0x7084, in t4_get_regs()
880 0x70f0, 0x70f8, in t4_get_regs()
881 0x7100, 0x710c, in t4_get_regs()
882 0x711c, 0x7184, in t4_get_regs()
883 0x71f0, 0x71f8, in t4_get_regs()
884 0x7200, 0x720c, in t4_get_regs()
885 0x721c, 0x7284, in t4_get_regs()
886 0x72f0, 0x72f8, in t4_get_regs()
887 0x7300, 0x730c, in t4_get_regs()
888 0x731c, 0x7384, in t4_get_regs()
889 0x73f0, 0x73f8, in t4_get_regs()
890 0x7400, 0x7450, in t4_get_regs()
891 0x7500, 0x7530, in t4_get_regs()
892 0x7600, 0x760c, in t4_get_regs()
893 0x7614, 0x761c, in t4_get_regs()
894 0x7680, 0x76cc, in t4_get_regs()
895 0x7700, 0x7798, in t4_get_regs()
896 0x77c0, 0x77fc, in t4_get_regs()
897 0x7900, 0x79fc, in t4_get_regs()
898 0x7b00, 0x7b58, in t4_get_regs()
899 0x7b60, 0x7b84, in t4_get_regs()
900 0x7b8c, 0x7c38, in t4_get_regs()
901 0x7d00, 0x7d38, in t4_get_regs()
902 0x7d40, 0x7d80, in t4_get_regs()
903 0x7d8c, 0x7ddc, in t4_get_regs()
904 0x7de4, 0x7e04, in t4_get_regs()
905 0x7e10, 0x7e1c, in t4_get_regs()
906 0x7e24, 0x7e38, in t4_get_regs()
907 0x7e40, 0x7e44, in t4_get_regs()
908 0x7e4c, 0x7e78, in t4_get_regs()
909 0x7e80, 0x7ea4, in t4_get_regs()
910 0x7eac, 0x7edc, in t4_get_regs()
911 0x7ee8, 0x7efc, in t4_get_regs()
912 0x8dc0, 0x8e04, in t4_get_regs()
913 0x8e10, 0x8e1c, in t4_get_regs()
914 0x8e30, 0x8e78, in t4_get_regs()
915 0x8ea0, 0x8eb8, in t4_get_regs()
916 0x8ec0, 0x8f6c, in t4_get_regs()
917 0x8fc0, 0x9008, in t4_get_regs()
918 0x9010, 0x9058, in t4_get_regs()
919 0x9060, 0x9060, in t4_get_regs()
920 0x9068, 0x9074, in t4_get_regs()
921 0x90fc, 0x90fc, in t4_get_regs()
922 0x9400, 0x9408, in t4_get_regs()
923 0x9410, 0x9458, in t4_get_regs()
924 0x9600, 0x9600, in t4_get_regs()
925 0x9608, 0x9638, in t4_get_regs()
926 0x9640, 0x96bc, in t4_get_regs()
927 0x9800, 0x9808, in t4_get_regs()
928 0x9820, 0x983c, in t4_get_regs()
929 0x9850, 0x9864, in t4_get_regs()
930 0x9c00, 0x9c6c, in t4_get_regs()
931 0x9c80, 0x9cec, in t4_get_regs()
932 0x9d00, 0x9d6c, in t4_get_regs()
933 0x9d80, 0x9dec, in t4_get_regs()
934 0x9e00, 0x9e6c, in t4_get_regs()
935 0x9e80, 0x9eec, in t4_get_regs()
936 0x9f00, 0x9f6c, in t4_get_regs()
937 0x9f80, 0x9fec, in t4_get_regs()
938 0xd004, 0xd004, in t4_get_regs()
939 0xd010, 0xd03c, in t4_get_regs()
940 0xdfc0, 0xdfe0, in t4_get_regs()
941 0xe000, 0xea7c, in t4_get_regs()
942 0xf000, 0x11110, in t4_get_regs()
943 0x11118, 0x11190, in t4_get_regs()
944 0x19040, 0x1906c, in t4_get_regs()
945 0x19078, 0x19080, in t4_get_regs()
946 0x1908c, 0x190e4, in t4_get_regs()
947 0x190f0, 0x190f8, in t4_get_regs()
948 0x19100, 0x19110, in t4_get_regs()
949 0x19120, 0x19124, in t4_get_regs()
950 0x19150, 0x19194, in t4_get_regs()
951 0x1919c, 0x191b0, in t4_get_regs()
952 0x191d0, 0x191e8, in t4_get_regs()
953 0x19238, 0x1924c, in t4_get_regs()
954 0x193f8, 0x1943c, in t4_get_regs()
955 0x1944c, 0x19474, in t4_get_regs()
956 0x19490, 0x194e0, in t4_get_regs()
957 0x194f0, 0x194f8, in t4_get_regs()
958 0x19800, 0x19c08, in t4_get_regs()
959 0x19c10, 0x19c90, in t4_get_regs()
960 0x19ca0, 0x19ce4, in t4_get_regs()
961 0x19cf0, 0x19d40, in t4_get_regs()
962 0x19d50, 0x19d94, in t4_get_regs()
963 0x19da0, 0x19de8, in t4_get_regs()
964 0x19df0, 0x19e40, in t4_get_regs()
965 0x19e50, 0x19e90, in t4_get_regs()
966 0x19ea0, 0x19f4c, in t4_get_regs()
967 0x1a000, 0x1a004, in t4_get_regs()
968 0x1a010, 0x1a06c, in t4_get_regs()
969 0x1a0b0, 0x1a0e4, in t4_get_regs()
970 0x1a0ec, 0x1a0f4, in t4_get_regs()
971 0x1a100, 0x1a108, in t4_get_regs()
972 0x1a114, 0x1a120, in t4_get_regs()
973 0x1a128, 0x1a130, in t4_get_regs()
974 0x1a138, 0x1a138, in t4_get_regs()
975 0x1a190, 0x1a1c4, in t4_get_regs()
976 0x1a1fc, 0x1a1fc, in t4_get_regs()
977 0x1e040, 0x1e04c, in t4_get_regs()
978 0x1e284, 0x1e28c, in t4_get_regs()
979 0x1e2c0, 0x1e2c0, in t4_get_regs()
980 0x1e2e0, 0x1e2e0, in t4_get_regs()
981 0x1e300, 0x1e384, in t4_get_regs()
982 0x1e3c0, 0x1e3c8, in t4_get_regs()
983 0x1e440, 0x1e44c, in t4_get_regs()
984 0x1e684, 0x1e68c, in t4_get_regs()
985 0x1e6c0, 0x1e6c0, in t4_get_regs()
986 0x1e6e0, 0x1e6e0, in t4_get_regs()
987 0x1e700, 0x1e784, in t4_get_regs()
988 0x1e7c0, 0x1e7c8, in t4_get_regs()
989 0x1e840, 0x1e84c, in t4_get_regs()
990 0x1ea84, 0x1ea8c, in t4_get_regs()
991 0x1eac0, 0x1eac0, in t4_get_regs()
992 0x1eae0, 0x1eae0, in t4_get_regs()
993 0x1eb00, 0x1eb84, in t4_get_regs()
994 0x1ebc0, 0x1ebc8, in t4_get_regs()
995 0x1ec40, 0x1ec4c, in t4_get_regs()
996 0x1ee84, 0x1ee8c, in t4_get_regs()
997 0x1eec0, 0x1eec0, in t4_get_regs()
998 0x1eee0, 0x1eee0, in t4_get_regs()
999 0x1ef00, 0x1ef84, in t4_get_regs()
1000 0x1efc0, 0x1efc8, in t4_get_regs()
1001 0x1f040, 0x1f04c, in t4_get_regs()
1002 0x1f284, 0x1f28c, in t4_get_regs()
1003 0x1f2c0, 0x1f2c0, in t4_get_regs()
1004 0x1f2e0, 0x1f2e0, in t4_get_regs()
1005 0x1f300, 0x1f384, in t4_get_regs()
1006 0x1f3c0, 0x1f3c8, in t4_get_regs()
1007 0x1f440, 0x1f44c, in t4_get_regs()
1008 0x1f684, 0x1f68c, in t4_get_regs()
1009 0x1f6c0, 0x1f6c0, in t4_get_regs()
1010 0x1f6e0, 0x1f6e0, in t4_get_regs()
1011 0x1f700, 0x1f784, in t4_get_regs()
1012 0x1f7c0, 0x1f7c8, in t4_get_regs()
1013 0x1f840, 0x1f84c, in t4_get_regs()
1014 0x1fa84, 0x1fa8c, in t4_get_regs()
1015 0x1fac0, 0x1fac0, in t4_get_regs()
1016 0x1fae0, 0x1fae0, in t4_get_regs()
1017 0x1fb00, 0x1fb84, in t4_get_regs()
1018 0x1fbc0, 0x1fbc8, in t4_get_regs()
1019 0x1fc40, 0x1fc4c, in t4_get_regs()
1020 0x1fe84, 0x1fe8c, in t4_get_regs()
1021 0x1fec0, 0x1fec0, in t4_get_regs()
1022 0x1fee0, 0x1fee0, in t4_get_regs()
1023 0x1ff00, 0x1ff84, in t4_get_regs()
1024 0x1ffc0, 0x1ffc8, in t4_get_regs()
1025 0x20000, 0x2002c, in t4_get_regs()
1026 0x20100, 0x2013c, in t4_get_regs()
1027 0x20190, 0x201a0, in t4_get_regs()
1028 0x201a8, 0x201b8, in t4_get_regs()
1029 0x201c4, 0x201c8, in t4_get_regs()
1030 0x20200, 0x20318, in t4_get_regs()
1031 0x20400, 0x204b4, in t4_get_regs()
1032 0x204c0, 0x20528, in t4_get_regs()
1033 0x20540, 0x20614, in t4_get_regs()
1034 0x21000, 0x21040, in t4_get_regs()
1035 0x2104c, 0x21060, in t4_get_regs()
1036 0x210c0, 0x210ec, in t4_get_regs()
1037 0x21200, 0x21268, in t4_get_regs()
1038 0x21270, 0x21284, in t4_get_regs()
1039 0x212fc, 0x21388, in t4_get_regs()
1040 0x21400, 0x21404, in t4_get_regs()
1041 0x21500, 0x21500, in t4_get_regs()
1042 0x21510, 0x21518, in t4_get_regs()
1043 0x2152c, 0x21530, in t4_get_regs()
1044 0x2153c, 0x2153c, in t4_get_regs()
1045 0x21550, 0x21554, in t4_get_regs()
1046 0x21600, 0x21600, in t4_get_regs()
1047 0x21608, 0x2161c, in t4_get_regs()
1048 0x21624, 0x21628, in t4_get_regs()
1049 0x21630, 0x21634, in t4_get_regs()
1050 0x2163c, 0x2163c, in t4_get_regs()
1051 0x21700, 0x2171c, in t4_get_regs()
1052 0x21780, 0x2178c, in t4_get_regs()
1053 0x21800, 0x21818, in t4_get_regs()
1054 0x21820, 0x21828, in t4_get_regs()
1055 0x21830, 0x21848, in t4_get_regs()
1056 0x21850, 0x21854, in t4_get_regs()
1057 0x21860, 0x21868, in t4_get_regs()
1058 0x21870, 0x21870, in t4_get_regs()
1059 0x21878, 0x21898, in t4_get_regs()
1060 0x218a0, 0x218a8, in t4_get_regs()
1061 0x218b0, 0x218c8, in t4_get_regs()
1062 0x218d0, 0x218d4, in t4_get_regs()
1063 0x218e0, 0x218e8, in t4_get_regs()
1064 0x218f0, 0x218f0, in t4_get_regs()
1065 0x218f8, 0x21a18, in t4_get_regs()
1066 0x21a20, 0x21a28, in t4_get_regs()
1067 0x21a30, 0x21a48, in t4_get_regs()
1068 0x21a50, 0x21a54, in t4_get_regs()
1069 0x21a60, 0x21a68, in t4_get_regs()
1070 0x21a70, 0x21a70, in t4_get_regs()
1071 0x21a78, 0x21a98, in t4_get_regs()
1072 0x21aa0, 0x21aa8, in t4_get_regs()
1073 0x21ab0, 0x21ac8, in t4_get_regs()
1074 0x21ad0, 0x21ad4, in t4_get_regs()
1075 0x21ae0, 0x21ae8, in t4_get_regs()
1076 0x21af0, 0x21af0, in t4_get_regs()
1077 0x21af8, 0x21c18, in t4_get_regs()
1078 0x21c20, 0x21c20, in t4_get_regs()
1079 0x21c28, 0x21c30, in t4_get_regs()
1080 0x21c38, 0x21c38, in t4_get_regs()
1081 0x21c80, 0x21c98, in t4_get_regs()
1082 0x21ca0, 0x21ca8, in t4_get_regs()
1083 0x21cb0, 0x21cc8, in t4_get_regs()
1084 0x21cd0, 0x21cd4, in t4_get_regs()
1085 0x21ce0, 0x21ce8, in t4_get_regs()
1086 0x21cf0, 0x21cf0, in t4_get_regs()
1087 0x21cf8, 0x21d7c, in t4_get_regs()
1088 0x21e00, 0x21e04, in t4_get_regs()
1089 0x22000, 0x2202c, in t4_get_regs()
1090 0x22100, 0x2213c, in t4_get_regs()
1091 0x22190, 0x221a0, in t4_get_regs()
1092 0x221a8, 0x221b8, in t4_get_regs()
1093 0x221c4, 0x221c8, in t4_get_regs()
1094 0x22200, 0x22318, in t4_get_regs()
1095 0x22400, 0x224b4, in t4_get_regs()
1096 0x224c0, 0x22528, in t4_get_regs()
1097 0x22540, 0x22614, in t4_get_regs()
1098 0x23000, 0x23040, in t4_get_regs()
1099 0x2304c, 0x23060, in t4_get_regs()
1100 0x230c0, 0x230ec, in t4_get_regs()
1101 0x23200, 0x23268, in t4_get_regs()
1102 0x23270, 0x23284, in t4_get_regs()
1103 0x232fc, 0x23388, in t4_get_regs()
1104 0x23400, 0x23404, in t4_get_regs()
1105 0x23500, 0x23500, in t4_get_regs()
1106 0x23510, 0x23518, in t4_get_regs()
1107 0x2352c, 0x23530, in t4_get_regs()
1108 0x2353c, 0x2353c, in t4_get_regs()
1109 0x23550, 0x23554, in t4_get_regs()
1110 0x23600, 0x23600, in t4_get_regs()
1111 0x23608, 0x2361c, in t4_get_regs()
1112 0x23624, 0x23628, in t4_get_regs()
1113 0x23630, 0x23634, in t4_get_regs()
1114 0x2363c, 0x2363c, in t4_get_regs()
1115 0x23700, 0x2371c, in t4_get_regs()
1116 0x23780, 0x2378c, in t4_get_regs()
1117 0x23800, 0x23818, in t4_get_regs()
1118 0x23820, 0x23828, in t4_get_regs()
1119 0x23830, 0x23848, in t4_get_regs()
1120 0x23850, 0x23854, in t4_get_regs()
1121 0x23860, 0x23868, in t4_get_regs()
1122 0x23870, 0x23870, in t4_get_regs()
1123 0x23878, 0x23898, in t4_get_regs()
1124 0x238a0, 0x238a8, in t4_get_regs()
1125 0x238b0, 0x238c8, in t4_get_regs()
1126 0x238d0, 0x238d4, in t4_get_regs()
1127 0x238e0, 0x238e8, in t4_get_regs()
1128 0x238f0, 0x238f0, in t4_get_regs()
1129 0x238f8, 0x23a18, in t4_get_regs()
1130 0x23a20, 0x23a28, in t4_get_regs()
1131 0x23a30, 0x23a48, in t4_get_regs()
1132 0x23a50, 0x23a54, in t4_get_regs()
1133 0x23a60, 0x23a68, in t4_get_regs()
1134 0x23a70, 0x23a70, in t4_get_regs()
1135 0x23a78, 0x23a98, in t4_get_regs()
1136 0x23aa0, 0x23aa8, in t4_get_regs()
1137 0x23ab0, 0x23ac8, in t4_get_regs()
1138 0x23ad0, 0x23ad4, in t4_get_regs()
1139 0x23ae0, 0x23ae8, in t4_get_regs()
1140 0x23af0, 0x23af0, in t4_get_regs()
1141 0x23af8, 0x23c18, in t4_get_regs()
1142 0x23c20, 0x23c20, in t4_get_regs()
1143 0x23c28, 0x23c30, in t4_get_regs()
1144 0x23c38, 0x23c38, in t4_get_regs()
1145 0x23c80, 0x23c98, in t4_get_regs()
1146 0x23ca0, 0x23ca8, in t4_get_regs()
1147 0x23cb0, 0x23cc8, in t4_get_regs()
1148 0x23cd0, 0x23cd4, in t4_get_regs()
1149 0x23ce0, 0x23ce8, in t4_get_regs()
1150 0x23cf0, 0x23cf0, in t4_get_regs()
1151 0x23cf8, 0x23d7c, in t4_get_regs()
1152 0x23e00, 0x23e04, in t4_get_regs()
1153 0x24000, 0x2402c, in t4_get_regs()
1154 0x24100, 0x2413c, in t4_get_regs()
1155 0x24190, 0x241a0, in t4_get_regs()
1156 0x241a8, 0x241b8, in t4_get_regs()
1157 0x241c4, 0x241c8, in t4_get_regs()
1158 0x24200, 0x24318, in t4_get_regs()
1159 0x24400, 0x244b4, in t4_get_regs()
1160 0x244c0, 0x24528, in t4_get_regs()
1161 0x24540, 0x24614, in t4_get_regs()
1162 0x25000, 0x25040, in t4_get_regs()
1163 0x2504c, 0x25060, in t4_get_regs()
1164 0x250c0, 0x250ec, in t4_get_regs()
1165 0x25200, 0x25268, in t4_get_regs()
1166 0x25270, 0x25284, in t4_get_regs()
1167 0x252fc, 0x25388, in t4_get_regs()
1168 0x25400, 0x25404, in t4_get_regs()
1169 0x25500, 0x25500, in t4_get_regs()
1170 0x25510, 0x25518, in t4_get_regs()
1171 0x2552c, 0x25530, in t4_get_regs()
1172 0x2553c, 0x2553c, in t4_get_regs()
1173 0x25550, 0x25554, in t4_get_regs()
1174 0x25600, 0x25600, in t4_get_regs()
1175 0x25608, 0x2561c, in t4_get_regs()
1176 0x25624, 0x25628, in t4_get_regs()
1177 0x25630, 0x25634, in t4_get_regs()
1178 0x2563c, 0x2563c, in t4_get_regs()
1179 0x25700, 0x2571c, in t4_get_regs()
1180 0x25780, 0x2578c, in t4_get_regs()
1181 0x25800, 0x25818, in t4_get_regs()
1182 0x25820, 0x25828, in t4_get_regs()
1183 0x25830, 0x25848, in t4_get_regs()
1184 0x25850, 0x25854, in t4_get_regs()
1185 0x25860, 0x25868, in t4_get_regs()
1186 0x25870, 0x25870, in t4_get_regs()
1187 0x25878, 0x25898, in t4_get_regs()
1188 0x258a0, 0x258a8, in t4_get_regs()
1189 0x258b0, 0x258c8, in t4_get_regs()
1190 0x258d0, 0x258d4, in t4_get_regs()
1191 0x258e0, 0x258e8, in t4_get_regs()
1192 0x258f0, 0x258f0, in t4_get_regs()
1193 0x258f8, 0x25a18, in t4_get_regs()
1194 0x25a20, 0x25a28, in t4_get_regs()
1195 0x25a30, 0x25a48, in t4_get_regs()
1196 0x25a50, 0x25a54, in t4_get_regs()
1197 0x25a60, 0x25a68, in t4_get_regs()
1198 0x25a70, 0x25a70, in t4_get_regs()
1199 0x25a78, 0x25a98, in t4_get_regs()
1200 0x25aa0, 0x25aa8, in t4_get_regs()
1201 0x25ab0, 0x25ac8, in t4_get_regs()
1202 0x25ad0, 0x25ad4, in t4_get_regs()
1203 0x25ae0, 0x25ae8, in t4_get_regs()
1204 0x25af0, 0x25af0, in t4_get_regs()
1205 0x25af8, 0x25c18, in t4_get_regs()
1206 0x25c20, 0x25c20, in t4_get_regs()
1207 0x25c28, 0x25c30, in t4_get_regs()
1208 0x25c38, 0x25c38, in t4_get_regs()
1209 0x25c80, 0x25c98, in t4_get_regs()
1210 0x25ca0, 0x25ca8, in t4_get_regs()
1211 0x25cb0, 0x25cc8, in t4_get_regs()
1212 0x25cd0, 0x25cd4, in t4_get_regs()
1213 0x25ce0, 0x25ce8, in t4_get_regs()
1214 0x25cf0, 0x25cf0, in t4_get_regs()
1215 0x25cf8, 0x25d7c, in t4_get_regs()
1216 0x25e00, 0x25e04, in t4_get_regs()
1217 0x26000, 0x2602c, in t4_get_regs()
1218 0x26100, 0x2613c, in t4_get_regs()
1219 0x26190, 0x261a0, in t4_get_regs()
1220 0x261a8, 0x261b8, in t4_get_regs()
1221 0x261c4, 0x261c8, in t4_get_regs()
1222 0x26200, 0x26318, in t4_get_regs()
1223 0x26400, 0x264b4, in t4_get_regs()
1224 0x264c0, 0x26528, in t4_get_regs()
1225 0x26540, 0x26614, in t4_get_regs()
1226 0x27000, 0x27040, in t4_get_regs()
1227 0x2704c, 0x27060, in t4_get_regs()
1228 0x270c0, 0x270ec, in t4_get_regs()
1229 0x27200, 0x27268, in t4_get_regs()
1230 0x27270, 0x27284, in t4_get_regs()
1231 0x272fc, 0x27388, in t4_get_regs()
1232 0x27400, 0x27404, in t4_get_regs()
1233 0x27500, 0x27500, in t4_get_regs()
1234 0x27510, 0x27518, in t4_get_regs()
1235 0x2752c, 0x27530, in t4_get_regs()
1236 0x2753c, 0x2753c, in t4_get_regs()
1237 0x27550, 0x27554, in t4_get_regs()
1238 0x27600, 0x27600, in t4_get_regs()
1239 0x27608, 0x2761c, in t4_get_regs()
1240 0x27624, 0x27628, in t4_get_regs()
1241 0x27630, 0x27634, in t4_get_regs()
1242 0x2763c, 0x2763c, in t4_get_regs()
1243 0x27700, 0x2771c, in t4_get_regs()
1244 0x27780, 0x2778c, in t4_get_regs()
1245 0x27800, 0x27818, in t4_get_regs()
1246 0x27820, 0x27828, in t4_get_regs()
1247 0x27830, 0x27848, in t4_get_regs()
1248 0x27850, 0x27854, in t4_get_regs()
1249 0x27860, 0x27868, in t4_get_regs()
1250 0x27870, 0x27870, in t4_get_regs()
1251 0x27878, 0x27898, in t4_get_regs()
1252 0x278a0, 0x278a8, in t4_get_regs()
1253 0x278b0, 0x278c8, in t4_get_regs()
1254 0x278d0, 0x278d4, in t4_get_regs()
1255 0x278e0, 0x278e8, in t4_get_regs()
1256 0x278f0, 0x278f0, in t4_get_regs()
1257 0x278f8, 0x27a18, in t4_get_regs()
1258 0x27a20, 0x27a28, in t4_get_regs()
1259 0x27a30, 0x27a48, in t4_get_regs()
1260 0x27a50, 0x27a54, in t4_get_regs()
1261 0x27a60, 0x27a68, in t4_get_regs()
1262 0x27a70, 0x27a70, in t4_get_regs()
1263 0x27a78, 0x27a98, in t4_get_regs()
1264 0x27aa0, 0x27aa8, in t4_get_regs()
1265 0x27ab0, 0x27ac8, in t4_get_regs()
1266 0x27ad0, 0x27ad4, in t4_get_regs()
1267 0x27ae0, 0x27ae8, in t4_get_regs()
1268 0x27af0, 0x27af0, in t4_get_regs()
1269 0x27af8, 0x27c18, in t4_get_regs()
1270 0x27c20, 0x27c20, in t4_get_regs()
1271 0x27c28, 0x27c30, in t4_get_regs()
1272 0x27c38, 0x27c38, in t4_get_regs()
1273 0x27c80, 0x27c98, in t4_get_regs()
1274 0x27ca0, 0x27ca8, in t4_get_regs()
1275 0x27cb0, 0x27cc8, in t4_get_regs()
1276 0x27cd0, 0x27cd4, in t4_get_regs()
1277 0x27ce0, 0x27ce8, in t4_get_regs()
1278 0x27cf0, 0x27cf0, in t4_get_regs()
1279 0x27cf8, 0x27d7c, in t4_get_regs()
1280 0x27e00, 0x27e04, in t4_get_regs()
1296 0x1008, 0x10c0, in t4_get_regs()
1297 0x10cc, 0x10f8, in t4_get_regs()
1298 0x1100, 0x1100, in t4_get_regs()
1299 0x110c, 0x1148, in t4_get_regs()
1300 0x1180, 0x1184, in t4_get_regs()
1301 0x1190, 0x1194, in t4_get_regs()
1302 0x11a0, 0x11a4, in t4_get_regs()
1303 0x11b0, 0x11b4, in t4_get_regs()
1304 0x11fc, 0x123c, in t4_get_regs()
1305 0x1280, 0x173c, in t4_get_regs()
1306 0x1800, 0x18fc, in t4_get_regs()
1307 0x3000, 0x3028, in t4_get_regs()
1308 0x3060, 0x30b0, in t4_get_regs()
1309 0x30b8, 0x30d8, in t4_get_regs()
1310 0x30e0, 0x30fc, in t4_get_regs()
1311 0x3140, 0x357c, in t4_get_regs()
1312 0x35a8, 0x35cc, in t4_get_regs()
1313 0x35ec, 0x35ec, in t4_get_regs()
1314 0x3600, 0x5624, in t4_get_regs()
1315 0x56cc, 0x56ec, in t4_get_regs()
1316 0x56f4, 0x5720, in t4_get_regs()
1317 0x5728, 0x575c, in t4_get_regs()
1318 0x580c, 0x5814, in t4_get_regs()
1319 0x5890, 0x589c, in t4_get_regs()
1320 0x58a4, 0x58ac, in t4_get_regs()
1321 0x58b8, 0x58bc, in t4_get_regs()
1322 0x5940, 0x59c8, in t4_get_regs()
1323 0x59d0, 0x59dc, in t4_get_regs()
1324 0x59fc, 0x5a18, in t4_get_regs()
1325 0x5a60, 0x5a70, in t4_get_regs()
1326 0x5a80, 0x5a9c, in t4_get_regs()
1327 0x5b94, 0x5bfc, in t4_get_regs()
1328 0x6000, 0x6020, in t4_get_regs()
1329 0x6028, 0x6040, in t4_get_regs()
1330 0x6058, 0x609c, in t4_get_regs()
1331 0x60a8, 0x614c, in t4_get_regs()
1332 0x7700, 0x7798, in t4_get_regs()
1333 0x77c0, 0x78fc, in t4_get_regs()
1334 0x7b00, 0x7b58, in t4_get_regs()
1335 0x7b60, 0x7b84, in t4_get_regs()
1336 0x7b8c, 0x7c54, in t4_get_regs()
1337 0x7d00, 0x7d38, in t4_get_regs()
1338 0x7d40, 0x7d80, in t4_get_regs()
1339 0x7d8c, 0x7ddc, in t4_get_regs()
1340 0x7de4, 0x7e04, in t4_get_regs()
1341 0x7e10, 0x7e1c, in t4_get_regs()
1342 0x7e24, 0x7e38, in t4_get_regs()
1343 0x7e40, 0x7e44, in t4_get_regs()
1344 0x7e4c, 0x7e78, in t4_get_regs()
1345 0x7e80, 0x7edc, in t4_get_regs()
1346 0x7ee8, 0x7efc, in t4_get_regs()
1347 0x8dc0, 0x8de0, in t4_get_regs()
1348 0x8df8, 0x8e04, in t4_get_regs()
1349 0x8e10, 0x8e84, in t4_get_regs()
1350 0x8ea0, 0x8f84, in t4_get_regs()
1351 0x8fc0, 0x9058, in t4_get_regs()
1352 0x9060, 0x9060, in t4_get_regs()
1353 0x9068, 0x90f8, in t4_get_regs()
1354 0x9400, 0x9408, in t4_get_regs()
1355 0x9410, 0x9470, in t4_get_regs()
1356 0x9600, 0x9600, in t4_get_regs()
1357 0x9608, 0x9638, in t4_get_regs()
1358 0x9640, 0x96f4, in t4_get_regs()
1359 0x9800, 0x9808, in t4_get_regs()
1360 0x9810, 0x9864, in t4_get_regs()
1361 0x9c00, 0x9c6c, in t4_get_regs()
1362 0x9c80, 0x9cec, in t4_get_regs()
1363 0x9d00, 0x9d6c, in t4_get_regs()
1364 0x9d80, 0x9dec, in t4_get_regs()
1365 0x9e00, 0x9e6c, in t4_get_regs()
1366 0x9e80, 0x9eec, in t4_get_regs()
1367 0x9f00, 0x9f6c, in t4_get_regs()
1368 0x9f80, 0xa020, in t4_get_regs()
1369 0xd000, 0xd004, in t4_get_regs()
1370 0xd010, 0xd03c, in t4_get_regs()
1371 0xdfc0, 0xdfe0, in t4_get_regs()
1372 0xe000, 0x1106c, in t4_get_regs()
1373 0x11074, 0x11088, in t4_get_regs()
1374 0x1109c, 0x11110, in t4_get_regs()
1375 0x11118, 0x1117c, in t4_get_regs()
1376 0x11190, 0x11204, in t4_get_regs()
1377 0x19040, 0x1906c, in t4_get_regs()
1378 0x19078, 0x19080, in t4_get_regs()
1379 0x1908c, 0x190e8, in t4_get_regs()
1380 0x190f0, 0x190f8, in t4_get_regs()
1381 0x19100, 0x19110, in t4_get_regs()
1382 0x19120, 0x19124, in t4_get_regs()
1383 0x19150, 0x19194, in t4_get_regs()
1384 0x1919c, 0x191b0, in t4_get_regs()
1385 0x191d0, 0x191e8, in t4_get_regs()
1386 0x19238, 0x19290, in t4_get_regs()
1387 0x193f8, 0x19428, in t4_get_regs()
1388 0x19430, 0x19444, in t4_get_regs()
1389 0x1944c, 0x1946c, in t4_get_regs()
1390 0x19474, 0x19474, in t4_get_regs()
1391 0x19490, 0x194cc, in t4_get_regs()
1392 0x194f0, 0x194f8, in t4_get_regs()
1393 0x19c00, 0x19c08, in t4_get_regs()
1394 0x19c10, 0x19c60, in t4_get_regs()
1395 0x19c94, 0x19ce4, in t4_get_regs()
1396 0x19cf0, 0x19d40, in t4_get_regs()
1397 0x19d50, 0x19d94, in t4_get_regs()
1398 0x19da0, 0x19de8, in t4_get_regs()
1399 0x19df0, 0x19e10, in t4_get_regs()
1400 0x19e50, 0x19e90, in t4_get_regs()
1401 0x19ea0, 0x19f24, in t4_get_regs()
1402 0x19f34, 0x19f34, in t4_get_regs()
1403 0x19f40, 0x19f50, in t4_get_regs()
1404 0x19f90, 0x19fb4, in t4_get_regs()
1405 0x19fc4, 0x19fe4, in t4_get_regs()
1406 0x1a000, 0x1a004, in t4_get_regs()
1407 0x1a010, 0x1a06c, in t4_get_regs()
1408 0x1a0b0, 0x1a0e4, in t4_get_regs()
1409 0x1a0ec, 0x1a0f8, in t4_get_regs()
1410 0x1a100, 0x1a108, in t4_get_regs()
1411 0x1a114, 0x1a130, in t4_get_regs()
1412 0x1a138, 0x1a1c4, in t4_get_regs()
1413 0x1a1fc, 0x1a1fc, in t4_get_regs()
1414 0x1e008, 0x1e00c, in t4_get_regs()
1415 0x1e040, 0x1e044, in t4_get_regs()
1416 0x1e04c, 0x1e04c, in t4_get_regs()
1417 0x1e284, 0x1e290, in t4_get_regs()
1418 0x1e2c0, 0x1e2c0, in t4_get_regs()
1419 0x1e2e0, 0x1e2e0, in t4_get_regs()
1420 0x1e300, 0x1e384, in t4_get_regs()
1421 0x1e3c0, 0x1e3c8, in t4_get_regs()
1422 0x1e408, 0x1e40c, in t4_get_regs()
1423 0x1e440, 0x1e444, in t4_get_regs()
1424 0x1e44c, 0x1e44c, in t4_get_regs()
1425 0x1e684, 0x1e690, in t4_get_regs()
1426 0x1e6c0, 0x1e6c0, in t4_get_regs()
1427 0x1e6e0, 0x1e6e0, in t4_get_regs()
1428 0x1e700, 0x1e784, in t4_get_regs()
1429 0x1e7c0, 0x1e7c8, in t4_get_regs()
1430 0x1e808, 0x1e80c, in t4_get_regs()
1431 0x1e840, 0x1e844, in t4_get_regs()
1432 0x1e84c, 0x1e84c, in t4_get_regs()
1433 0x1ea84, 0x1ea90, in t4_get_regs()
1434 0x1eac0, 0x1eac0, in t4_get_regs()
1435 0x1eae0, 0x1eae0, in t4_get_regs()
1436 0x1eb00, 0x1eb84, in t4_get_regs()
1437 0x1ebc0, 0x1ebc8, in t4_get_regs()
1438 0x1ec08, 0x1ec0c, in t4_get_regs()
1439 0x1ec40, 0x1ec44, in t4_get_regs()
1440 0x1ec4c, 0x1ec4c, in t4_get_regs()
1441 0x1ee84, 0x1ee90, in t4_get_regs()
1442 0x1eec0, 0x1eec0, in t4_get_regs()
1443 0x1eee0, 0x1eee0, in t4_get_regs()
1444 0x1ef00, 0x1ef84, in t4_get_regs()
1445 0x1efc0, 0x1efc8, in t4_get_regs()
1446 0x1f008, 0x1f00c, in t4_get_regs()
1447 0x1f040, 0x1f044, in t4_get_regs()
1448 0x1f04c, 0x1f04c, in t4_get_regs()
1449 0x1f284, 0x1f290, in t4_get_regs()
1450 0x1f2c0, 0x1f2c0, in t4_get_regs()
1451 0x1f2e0, 0x1f2e0, in t4_get_regs()
1452 0x1f300, 0x1f384, in t4_get_regs()
1453 0x1f3c0, 0x1f3c8, in t4_get_regs()
1454 0x1f408, 0x1f40c, in t4_get_regs()
1455 0x1f440, 0x1f444, in t4_get_regs()
1456 0x1f44c, 0x1f44c, in t4_get_regs()
1457 0x1f684, 0x1f690, in t4_get_regs()
1458 0x1f6c0, 0x1f6c0, in t4_get_regs()
1459 0x1f6e0, 0x1f6e0, in t4_get_regs()
1460 0x1f700, 0x1f784, in t4_get_regs()
1461 0x1f7c0, 0x1f7c8, in t4_get_regs()
1462 0x1f808, 0x1f80c, in t4_get_regs()
1463 0x1f840, 0x1f844, in t4_get_regs()
1464 0x1f84c, 0x1f84c, in t4_get_regs()
1465 0x1fa84, 0x1fa90, in t4_get_regs()
1466 0x1fac0, 0x1fac0, in t4_get_regs()
1467 0x1fae0, 0x1fae0, in t4_get_regs()
1468 0x1fb00, 0x1fb84, in t4_get_regs()
1469 0x1fbc0, 0x1fbc8, in t4_get_regs()
1470 0x1fc08, 0x1fc0c, in t4_get_regs()
1471 0x1fc40, 0x1fc44, in t4_get_regs()
1472 0x1fc4c, 0x1fc4c, in t4_get_regs()
1473 0x1fe84, 0x1fe90, in t4_get_regs()
1474 0x1fec0, 0x1fec0, in t4_get_regs()
1475 0x1fee0, 0x1fee0, in t4_get_regs()
1476 0x1ff00, 0x1ff84, in t4_get_regs()
1477 0x1ffc0, 0x1ffc8, in t4_get_regs()
1478 0x30000, 0x30030, in t4_get_regs()
1479 0x30100, 0x30144, in t4_get_regs()
1480 0x30190, 0x301a0, in t4_get_regs()
1481 0x301a8, 0x301b8, in t4_get_regs()
1482 0x301c4, 0x301c8, in t4_get_regs()
1483 0x301d0, 0x301d0, in t4_get_regs()
1484 0x30200, 0x30318, in t4_get_regs()
1485 0x30400, 0x304b4, in t4_get_regs()
1486 0x304c0, 0x3052c, in t4_get_regs()
1487 0x30540, 0x3061c, in t4_get_regs()
1488 0x30800, 0x30828, in t4_get_regs()
1489 0x30834, 0x30834, in t4_get_regs()
1490 0x308c0, 0x30908, in t4_get_regs()
1491 0x30910, 0x309ac, in t4_get_regs()
1492 0x30a00, 0x30a14, in t4_get_regs()
1493 0x30a1c, 0x30a2c, in t4_get_regs()
1494 0x30a44, 0x30a50, in t4_get_regs()
1495 0x30a74, 0x30a74, in t4_get_regs()
1496 0x30a7c, 0x30afc, in t4_get_regs()
1497 0x30b08, 0x30c24, in t4_get_regs()
1498 0x30d00, 0x30d00, in t4_get_regs()
1499 0x30d08, 0x30d14, in t4_get_regs()
1500 0x30d1c, 0x30d20, in t4_get_regs()
1501 0x30d3c, 0x30d3c, in t4_get_regs()
1502 0x30d48, 0x30d50, in t4_get_regs()
1503 0x31200, 0x3120c, in t4_get_regs()
1504 0x31220, 0x31220, in t4_get_regs()
1505 0x31240, 0x31240, in t4_get_regs()
1506 0x31600, 0x3160c, in t4_get_regs()
1507 0x31a00, 0x31a1c, in t4_get_regs()
1508 0x31e00, 0x31e20, in t4_get_regs()
1509 0x31e38, 0x31e3c, in t4_get_regs()
1510 0x31e80, 0x31e80, in t4_get_regs()
1511 0x31e88, 0x31ea8, in t4_get_regs()
1512 0x31eb0, 0x31eb4, in t4_get_regs()
1513 0x31ec8, 0x31ed4, in t4_get_regs()
1514 0x31fb8, 0x32004, in t4_get_regs()
1515 0x32200, 0x32200, in t4_get_regs()
1516 0x32208, 0x32240, in t4_get_regs()
1517 0x32248, 0x32280, in t4_get_regs()
1518 0x32288, 0x322c0, in t4_get_regs()
1519 0x322c8, 0x322fc, in t4_get_regs()
1520 0x32600, 0x32630, in t4_get_regs()
1521 0x32a00, 0x32abc, in t4_get_regs()
1522 0x32b00, 0x32b10, in t4_get_regs()
1523 0x32b20, 0x32b30, in t4_get_regs()
1524 0x32b40, 0x32b50, in t4_get_regs()
1525 0x32b60, 0x32b70, in t4_get_regs()
1526 0x33000, 0x33028, in t4_get_regs()
1527 0x33030, 0x33048, in t4_get_regs()
1528 0x33060, 0x33068, in t4_get_regs()
1529 0x33070, 0x3309c, in t4_get_regs()
1530 0x330f0, 0x33128, in t4_get_regs()
1531 0x33130, 0x33148, in t4_get_regs()
1532 0x33160, 0x33168, in t4_get_regs()
1533 0x33170, 0x3319c, in t4_get_regs()
1534 0x331f0, 0x33238, in t4_get_regs()
1535 0x33240, 0x33240, in t4_get_regs()
1536 0x33248, 0x33250, in t4_get_regs()
1537 0x3325c, 0x33264, in t4_get_regs()
1538 0x33270, 0x332b8, in t4_get_regs()
1539 0x332c0, 0x332e4, in t4_get_regs()
1540 0x332f8, 0x33338, in t4_get_regs()
1541 0x33340, 0x33340, in t4_get_regs()
1542 0x33348, 0x33350, in t4_get_regs()
1543 0x3335c, 0x33364, in t4_get_regs()
1544 0x33370, 0x333b8, in t4_get_regs()
1545 0x333c0, 0x333e4, in t4_get_regs()
1546 0x333f8, 0x33428, in t4_get_regs()
1547 0x33430, 0x33448, in t4_get_regs()
1548 0x33460, 0x33468, in t4_get_regs()
1549 0x33470, 0x3349c, in t4_get_regs()
1550 0x334f0, 0x33528, in t4_get_regs()
1551 0x33530, 0x33548, in t4_get_regs()
1552 0x33560, 0x33568, in t4_get_regs()
1553 0x33570, 0x3359c, in t4_get_regs()
1554 0x335f0, 0x33638, in t4_get_regs()
1555 0x33640, 0x33640, in t4_get_regs()
1556 0x33648, 0x33650, in t4_get_regs()
1557 0x3365c, 0x33664, in t4_get_regs()
1558 0x33670, 0x336b8, in t4_get_regs()
1559 0x336c0, 0x336e4, in t4_get_regs()
1560 0x336f8, 0x33738, in t4_get_regs()
1561 0x33740, 0x33740, in t4_get_regs()
1562 0x33748, 0x33750, in t4_get_regs()
1563 0x3375c, 0x33764, in t4_get_regs()
1564 0x33770, 0x337b8, in t4_get_regs()
1565 0x337c0, 0x337e4, in t4_get_regs()
1566 0x337f8, 0x337fc, in t4_get_regs()
1567 0x33814, 0x33814, in t4_get_regs()
1568 0x3382c, 0x3382c, in t4_get_regs()
1569 0x33880, 0x3388c, in t4_get_regs()
1570 0x338e8, 0x338ec, in t4_get_regs()
1571 0x33900, 0x33928, in t4_get_regs()
1572 0x33930, 0x33948, in t4_get_regs()
1573 0x33960, 0x33968, in t4_get_regs()
1574 0x33970, 0x3399c, in t4_get_regs()
1575 0x339f0, 0x33a38, in t4_get_regs()
1576 0x33a40, 0x33a40, in t4_get_regs()
1577 0x33a48, 0x33a50, in t4_get_regs()
1578 0x33a5c, 0x33a64, in t4_get_regs()
1579 0x33a70, 0x33ab8, in t4_get_regs()
1580 0x33ac0, 0x33ae4, in t4_get_regs()
1581 0x33af8, 0x33b10, in t4_get_regs()
1582 0x33b28, 0x33b28, in t4_get_regs()
1583 0x33b3c, 0x33b50, in t4_get_regs()
1584 0x33bf0, 0x33c10, in t4_get_regs()
1585 0x33c28, 0x33c28, in t4_get_regs()
1586 0x33c3c, 0x33c50, in t4_get_regs()
1587 0x33cf0, 0x33cfc, in t4_get_regs()
1588 0x34000, 0x34030, in t4_get_regs()
1589 0x34100, 0x34144, in t4_get_regs()
1590 0x34190, 0x341a0, in t4_get_regs()
1591 0x341a8, 0x341b8, in t4_get_regs()
1592 0x341c4, 0x341c8, in t4_get_regs()
1593 0x341d0, 0x341d0, in t4_get_regs()
1594 0x34200, 0x34318, in t4_get_regs()
1595 0x34400, 0x344b4, in t4_get_regs()
1596 0x344c0, 0x3452c, in t4_get_regs()
1597 0x34540, 0x3461c, in t4_get_regs()
1598 0x34800, 0x34828, in t4_get_regs()
1599 0x34834, 0x34834, in t4_get_regs()
1600 0x348c0, 0x34908, in t4_get_regs()
1601 0x34910, 0x349ac, in t4_get_regs()
1602 0x34a00, 0x34a14, in t4_get_regs()
1603 0x34a1c, 0x34a2c, in t4_get_regs()
1604 0x34a44, 0x34a50, in t4_get_regs()
1605 0x34a74, 0x34a74, in t4_get_regs()
1606 0x34a7c, 0x34afc, in t4_get_regs()
1607 0x34b08, 0x34c24, in t4_get_regs()
1608 0x34d00, 0x34d00, in t4_get_regs()
1609 0x34d08, 0x34d14, in t4_get_regs()
1610 0x34d1c, 0x34d20, in t4_get_regs()
1611 0x34d3c, 0x34d3c, in t4_get_regs()
1612 0x34d48, 0x34d50, in t4_get_regs()
1613 0x35200, 0x3520c, in t4_get_regs()
1614 0x35220, 0x35220, in t4_get_regs()
1615 0x35240, 0x35240, in t4_get_regs()
1616 0x35600, 0x3560c, in t4_get_regs()
1617 0x35a00, 0x35a1c, in t4_get_regs()
1618 0x35e00, 0x35e20, in t4_get_regs()
1619 0x35e38, 0x35e3c, in t4_get_regs()
1620 0x35e80, 0x35e80, in t4_get_regs()
1621 0x35e88, 0x35ea8, in t4_get_regs()
1622 0x35eb0, 0x35eb4, in t4_get_regs()
1623 0x35ec8, 0x35ed4, in t4_get_regs()
1624 0x35fb8, 0x36004, in t4_get_regs()
1625 0x36200, 0x36200, in t4_get_regs()
1626 0x36208, 0x36240, in t4_get_regs()
1627 0x36248, 0x36280, in t4_get_regs()
1628 0x36288, 0x362c0, in t4_get_regs()
1629 0x362c8, 0x362fc, in t4_get_regs()
1630 0x36600, 0x36630, in t4_get_regs()
1631 0x36a00, 0x36abc, in t4_get_regs()
1632 0x36b00, 0x36b10, in t4_get_regs()
1633 0x36b20, 0x36b30, in t4_get_regs()
1634 0x36b40, 0x36b50, in t4_get_regs()
1635 0x36b60, 0x36b70, in t4_get_regs()
1636 0x37000, 0x37028, in t4_get_regs()
1637 0x37030, 0x37048, in t4_get_regs()
1638 0x37060, 0x37068, in t4_get_regs()
1639 0x37070, 0x3709c, in t4_get_regs()
1640 0x370f0, 0x37128, in t4_get_regs()
1641 0x37130, 0x37148, in t4_get_regs()
1642 0x37160, 0x37168, in t4_get_regs()
1643 0x37170, 0x3719c, in t4_get_regs()
1644 0x371f0, 0x37238, in t4_get_regs()
1645 0x37240, 0x37240, in t4_get_regs()
1646 0x37248, 0x37250, in t4_get_regs()
1647 0x3725c, 0x37264, in t4_get_regs()
1648 0x37270, 0x372b8, in t4_get_regs()
1649 0x372c0, 0x372e4, in t4_get_regs()
1650 0x372f8, 0x37338, in t4_get_regs()
1651 0x37340, 0x37340, in t4_get_regs()
1652 0x37348, 0x37350, in t4_get_regs()
1653 0x3735c, 0x37364, in t4_get_regs()
1654 0x37370, 0x373b8, in t4_get_regs()
1655 0x373c0, 0x373e4, in t4_get_regs()
1656 0x373f8, 0x37428, in t4_get_regs()
1657 0x37430, 0x37448, in t4_get_regs()
1658 0x37460, 0x37468, in t4_get_regs()
1659 0x37470, 0x3749c, in t4_get_regs()
1660 0x374f0, 0x37528, in t4_get_regs()
1661 0x37530, 0x37548, in t4_get_regs()
1662 0x37560, 0x37568, in t4_get_regs()
1663 0x37570, 0x3759c, in t4_get_regs()
1664 0x375f0, 0x37638, in t4_get_regs()
1665 0x37640, 0x37640, in t4_get_regs()
1666 0x37648, 0x37650, in t4_get_regs()
1667 0x3765c, 0x37664, in t4_get_regs()
1668 0x37670, 0x376b8, in t4_get_regs()
1669 0x376c0, 0x376e4, in t4_get_regs()
1670 0x376f8, 0x37738, in t4_get_regs()
1671 0x37740, 0x37740, in t4_get_regs()
1672 0x37748, 0x37750, in t4_get_regs()
1673 0x3775c, 0x37764, in t4_get_regs()
1674 0x37770, 0x377b8, in t4_get_regs()
1675 0x377c0, 0x377e4, in t4_get_regs()
1676 0x377f8, 0x377fc, in t4_get_regs()
1677 0x37814, 0x37814, in t4_get_regs()
1678 0x3782c, 0x3782c, in t4_get_regs()
1679 0x37880, 0x3788c, in t4_get_regs()
1680 0x378e8, 0x378ec, in t4_get_regs()
1681 0x37900, 0x37928, in t4_get_regs()
1682 0x37930, 0x37948, in t4_get_regs()
1683 0x37960, 0x37968, in t4_get_regs()
1684 0x37970, 0x3799c, in t4_get_regs()
1685 0x379f0, 0x37a38, in t4_get_regs()
1686 0x37a40, 0x37a40, in t4_get_regs()
1687 0x37a48, 0x37a50, in t4_get_regs()
1688 0x37a5c, 0x37a64, in t4_get_regs()
1689 0x37a70, 0x37ab8, in t4_get_regs()
1690 0x37ac0, 0x37ae4, in t4_get_regs()
1691 0x37af8, 0x37b10, in t4_get_regs()
1692 0x37b28, 0x37b28, in t4_get_regs()
1693 0x37b3c, 0x37b50, in t4_get_regs()
1694 0x37bf0, 0x37c10, in t4_get_regs()
1695 0x37c28, 0x37c28, in t4_get_regs()
1696 0x37c3c, 0x37c50, in t4_get_regs()
1697 0x37cf0, 0x37cfc, in t4_get_regs()
1698 0x38000, 0x38030, in t4_get_regs()
1699 0x38100, 0x38144, in t4_get_regs()
1700 0x38190, 0x381a0, in t4_get_regs()
1701 0x381a8, 0x381b8, in t4_get_regs()
1702 0x381c4, 0x381c8, in t4_get_regs()
1703 0x381d0, 0x381d0, in t4_get_regs()
1704 0x38200, 0x38318, in t4_get_regs()
1705 0x38400, 0x384b4, in t4_get_regs()
1706 0x384c0, 0x3852c, in t4_get_regs()
1707 0x38540, 0x3861c, in t4_get_regs()
1708 0x38800, 0x38828, in t4_get_regs()
1709 0x38834, 0x38834, in t4_get_regs()
1710 0x388c0, 0x38908, in t4_get_regs()
1711 0x38910, 0x389ac, in t4_get_regs()
1712 0x38a00, 0x38a14, in t4_get_regs()
1713 0x38a1c, 0x38a2c, in t4_get_regs()
1714 0x38a44, 0x38a50, in t4_get_regs()
1715 0x38a74, 0x38a74, in t4_get_regs()
1716 0x38a7c, 0x38afc, in t4_get_regs()
1717 0x38b08, 0x38c24, in t4_get_regs()
1718 0x38d00, 0x38d00, in t4_get_regs()
1719 0x38d08, 0x38d14, in t4_get_regs()
1720 0x38d1c, 0x38d20, in t4_get_regs()
1721 0x38d3c, 0x38d3c, in t4_get_regs()
1722 0x38d48, 0x38d50, in t4_get_regs()
1723 0x39200, 0x3920c, in t4_get_regs()
1724 0x39220, 0x39220, in t4_get_regs()
1725 0x39240, 0x39240, in t4_get_regs()
1726 0x39600, 0x3960c, in t4_get_regs()
1727 0x39a00, 0x39a1c, in t4_get_regs()
1728 0x39e00, 0x39e20, in t4_get_regs()
1729 0x39e38, 0x39e3c, in t4_get_regs()
1730 0x39e80, 0x39e80, in t4_get_regs()
1731 0x39e88, 0x39ea8, in t4_get_regs()
1732 0x39eb0, 0x39eb4, in t4_get_regs()
1733 0x39ec8, 0x39ed4, in t4_get_regs()
1734 0x39fb8, 0x3a004, in t4_get_regs()
1735 0x3a200, 0x3a200, in t4_get_regs()
1736 0x3a208, 0x3a240, in t4_get_regs()
1737 0x3a248, 0x3a280, in t4_get_regs()
1738 0x3a288, 0x3a2c0, in t4_get_regs()
1739 0x3a2c8, 0x3a2fc, in t4_get_regs()
1740 0x3a600, 0x3a630, in t4_get_regs()
1741 0x3aa00, 0x3aabc, in t4_get_regs()
1742 0x3ab00, 0x3ab10, in t4_get_regs()
1743 0x3ab20, 0x3ab30, in t4_get_regs()
1744 0x3ab40, 0x3ab50, in t4_get_regs()
1745 0x3ab60, 0x3ab70, in t4_get_regs()
1746 0x3b000, 0x3b028, in t4_get_regs()
1747 0x3b030, 0x3b048, in t4_get_regs()
1748 0x3b060, 0x3b068, in t4_get_regs()
1749 0x3b070, 0x3b09c, in t4_get_regs()
1750 0x3b0f0, 0x3b128, in t4_get_regs()
1751 0x3b130, 0x3b148, in t4_get_regs()
1752 0x3b160, 0x3b168, in t4_get_regs()
1753 0x3b170, 0x3b19c, in t4_get_regs()
1754 0x3b1f0, 0x3b238, in t4_get_regs()
1755 0x3b240, 0x3b240, in t4_get_regs()
1756 0x3b248, 0x3b250, in t4_get_regs()
1757 0x3b25c, 0x3b264, in t4_get_regs()
1758 0x3b270, 0x3b2b8, in t4_get_regs()
1759 0x3b2c0, 0x3b2e4, in t4_get_regs()
1760 0x3b2f8, 0x3b338, in t4_get_regs()
1761 0x3b340, 0x3b340, in t4_get_regs()
1762 0x3b348, 0x3b350, in t4_get_regs()
1763 0x3b35c, 0x3b364, in t4_get_regs()
1764 0x3b370, 0x3b3b8, in t4_get_regs()
1765 0x3b3c0, 0x3b3e4, in t4_get_regs()
1766 0x3b3f8, 0x3b428, in t4_get_regs()
1767 0x3b430, 0x3b448, in t4_get_regs()
1768 0x3b460, 0x3b468, in t4_get_regs()
1769 0x3b470, 0x3b49c, in t4_get_regs()
1770 0x3b4f0, 0x3b528, in t4_get_regs()
1771 0x3b530, 0x3b548, in t4_get_regs()
1772 0x3b560, 0x3b568, in t4_get_regs()
1773 0x3b570, 0x3b59c, in t4_get_regs()
1774 0x3b5f0, 0x3b638, in t4_get_regs()
1775 0x3b640, 0x3b640, in t4_get_regs()
1776 0x3b648, 0x3b650, in t4_get_regs()
1777 0x3b65c, 0x3b664, in t4_get_regs()
1778 0x3b670, 0x3b6b8, in t4_get_regs()
1779 0x3b6c0, 0x3b6e4, in t4_get_regs()
1780 0x3b6f8, 0x3b738, in t4_get_regs()
1781 0x3b740, 0x3b740, in t4_get_regs()
1782 0x3b748, 0x3b750, in t4_get_regs()
1783 0x3b75c, 0x3b764, in t4_get_regs()
1784 0x3b770, 0x3b7b8, in t4_get_regs()
1785 0x3b7c0, 0x3b7e4, in t4_get_regs()
1786 0x3b7f8, 0x3b7fc, in t4_get_regs()
1787 0x3b814, 0x3b814, in t4_get_regs()
1788 0x3b82c, 0x3b82c, in t4_get_regs()
1789 0x3b880, 0x3b88c, in t4_get_regs()
1790 0x3b8e8, 0x3b8ec, in t4_get_regs()
1791 0x3b900, 0x3b928, in t4_get_regs()
1792 0x3b930, 0x3b948, in t4_get_regs()
1793 0x3b960, 0x3b968, in t4_get_regs()
1794 0x3b970, 0x3b99c, in t4_get_regs()
1795 0x3b9f0, 0x3ba38, in t4_get_regs()
1796 0x3ba40, 0x3ba40, in t4_get_regs()
1797 0x3ba48, 0x3ba50, in t4_get_regs()
1798 0x3ba5c, 0x3ba64, in t4_get_regs()
1799 0x3ba70, 0x3bab8, in t4_get_regs()
1800 0x3bac0, 0x3bae4, in t4_get_regs()
1801 0x3baf8, 0x3bb10, in t4_get_regs()
1802 0x3bb28, 0x3bb28, in t4_get_regs()
1803 0x3bb3c, 0x3bb50, in t4_get_regs()
1804 0x3bbf0, 0x3bc10, in t4_get_regs()
1805 0x3bc28, 0x3bc28, in t4_get_regs()
1806 0x3bc3c, 0x3bc50, in t4_get_regs()
1807 0x3bcf0, 0x3bcfc, in t4_get_regs()
1808 0x3c000, 0x3c030, in t4_get_regs()
1809 0x3c100, 0x3c144, in t4_get_regs()
1810 0x3c190, 0x3c1a0, in t4_get_regs()
1811 0x3c1a8, 0x3c1b8, in t4_get_regs()
1812 0x3c1c4, 0x3c1c8, in t4_get_regs()
1813 0x3c1d0, 0x3c1d0, in t4_get_regs()
1814 0x3c200, 0x3c318, in t4_get_regs()
1815 0x3c400, 0x3c4b4, in t4_get_regs()
1816 0x3c4c0, 0x3c52c, in t4_get_regs()
1817 0x3c540, 0x3c61c, in t4_get_regs()
1818 0x3c800, 0x3c828, in t4_get_regs()
1819 0x3c834, 0x3c834, in t4_get_regs()
1820 0x3c8c0, 0x3c908, in t4_get_regs()
1821 0x3c910, 0x3c9ac, in t4_get_regs()
1822 0x3ca00, 0x3ca14, in t4_get_regs()
1823 0x3ca1c, 0x3ca2c, in t4_get_regs()
1824 0x3ca44, 0x3ca50, in t4_get_regs()
1825 0x3ca74, 0x3ca74, in t4_get_regs()
1826 0x3ca7c, 0x3cafc, in t4_get_regs()
1827 0x3cb08, 0x3cc24, in t4_get_regs()
1828 0x3cd00, 0x3cd00, in t4_get_regs()
1829 0x3cd08, 0x3cd14, in t4_get_regs()
1830 0x3cd1c, 0x3cd20, in t4_get_regs()
1831 0x3cd3c, 0x3cd3c, in t4_get_regs()
1832 0x3cd48, 0x3cd50, in t4_get_regs()
1833 0x3d200, 0x3d20c, in t4_get_regs()
1834 0x3d220, 0x3d220, in t4_get_regs()
1835 0x3d240, 0x3d240, in t4_get_regs()
1836 0x3d600, 0x3d60c, in t4_get_regs()
1837 0x3da00, 0x3da1c, in t4_get_regs()
1838 0x3de00, 0x3de20, in t4_get_regs()
1839 0x3de38, 0x3de3c, in t4_get_regs()
1840 0x3de80, 0x3de80, in t4_get_regs()
1841 0x3de88, 0x3dea8, in t4_get_regs()
1842 0x3deb0, 0x3deb4, in t4_get_regs()
1843 0x3dec8, 0x3ded4, in t4_get_regs()
1844 0x3dfb8, 0x3e004, in t4_get_regs()
1845 0x3e200, 0x3e200, in t4_get_regs()
1846 0x3e208, 0x3e240, in t4_get_regs()
1847 0x3e248, 0x3e280, in t4_get_regs()
1848 0x3e288, 0x3e2c0, in t4_get_regs()
1849 0x3e2c8, 0x3e2fc, in t4_get_regs()
1850 0x3e600, 0x3e630, in t4_get_regs()
1851 0x3ea00, 0x3eabc, in t4_get_regs()
1852 0x3eb00, 0x3eb10, in t4_get_regs()
1853 0x3eb20, 0x3eb30, in t4_get_regs()
1854 0x3eb40, 0x3eb50, in t4_get_regs()
1855 0x3eb60, 0x3eb70, in t4_get_regs()
1856 0x3f000, 0x3f028, in t4_get_regs()
1857 0x3f030, 0x3f048, in t4_get_regs()
1858 0x3f060, 0x3f068, in t4_get_regs()
1859 0x3f070, 0x3f09c, in t4_get_regs()
1860 0x3f0f0, 0x3f128, in t4_get_regs()
1861 0x3f130, 0x3f148, in t4_get_regs()
1862 0x3f160, 0x3f168, in t4_get_regs()
1863 0x3f170, 0x3f19c, in t4_get_regs()
1864 0x3f1f0, 0x3f238, in t4_get_regs()
1865 0x3f240, 0x3f240, in t4_get_regs()
1866 0x3f248, 0x3f250, in t4_get_regs()
1867 0x3f25c, 0x3f264, in t4_get_regs()
1868 0x3f270, 0x3f2b8, in t4_get_regs()
1869 0x3f2c0, 0x3f2e4, in t4_get_regs()
1870 0x3f2f8, 0x3f338, in t4_get_regs()
1871 0x3f340, 0x3f340, in t4_get_regs()
1872 0x3f348, 0x3f350, in t4_get_regs()
1873 0x3f35c, 0x3f364, in t4_get_regs()
1874 0x3f370, 0x3f3b8, in t4_get_regs()
1875 0x3f3c0, 0x3f3e4, in t4_get_regs()
1876 0x3f3f8, 0x3f428, in t4_get_regs()
1877 0x3f430, 0x3f448, in t4_get_regs()
1878 0x3f460, 0x3f468, in t4_get_regs()
1879 0x3f470, 0x3f49c, in t4_get_regs()
1880 0x3f4f0, 0x3f528, in t4_get_regs()
1881 0x3f530, 0x3f548, in t4_get_regs()
1882 0x3f560, 0x3f568, in t4_get_regs()
1883 0x3f570, 0x3f59c, in t4_get_regs()
1884 0x3f5f0, 0x3f638, in t4_get_regs()
1885 0x3f640, 0x3f640, in t4_get_regs()
1886 0x3f648, 0x3f650, in t4_get_regs()
1887 0x3f65c, 0x3f664, in t4_get_regs()
1888 0x3f670, 0x3f6b8, in t4_get_regs()
1889 0x3f6c0, 0x3f6e4, in t4_get_regs()
1890 0x3f6f8, 0x3f738, in t4_get_regs()
1891 0x3f740, 0x3f740, in t4_get_regs()
1892 0x3f748, 0x3f750, in t4_get_regs()
1893 0x3f75c, 0x3f764, in t4_get_regs()
1894 0x3f770, 0x3f7b8, in t4_get_regs()
1895 0x3f7c0, 0x3f7e4, in t4_get_regs()
1896 0x3f7f8, 0x3f7fc, in t4_get_regs()
1897 0x3f814, 0x3f814, in t4_get_regs()
1898 0x3f82c, 0x3f82c, in t4_get_regs()
1899 0x3f880, 0x3f88c, in t4_get_regs()
1900 0x3f8e8, 0x3f8ec, in t4_get_regs()
1901 0x3f900, 0x3f928, in t4_get_regs()
1902 0x3f930, 0x3f948, in t4_get_regs()
1903 0x3f960, 0x3f968, in t4_get_regs()
1904 0x3f970, 0x3f99c, in t4_get_regs()
1905 0x3f9f0, 0x3fa38, in t4_get_regs()
1906 0x3fa40, 0x3fa40, in t4_get_regs()
1907 0x3fa48, 0x3fa50, in t4_get_regs()
1908 0x3fa5c, 0x3fa64, in t4_get_regs()
1909 0x3fa70, 0x3fab8, in t4_get_regs()
1910 0x3fac0, 0x3fae4, in t4_get_regs()
1911 0x3faf8, 0x3fb10, in t4_get_regs()
1912 0x3fb28, 0x3fb28, in t4_get_regs()
1913 0x3fb3c, 0x3fb50, in t4_get_regs()
1914 0x3fbf0, 0x3fc10, in t4_get_regs()
1915 0x3fc28, 0x3fc28, in t4_get_regs()
1916 0x3fc3c, 0x3fc50, in t4_get_regs()
1917 0x3fcf0, 0x3fcfc, in t4_get_regs()
1918 0x40000, 0x4000c, in t4_get_regs()
1919 0x40040, 0x40050, in t4_get_regs()
1920 0x40060, 0x40068, in t4_get_regs()
1921 0x4007c, 0x4008c, in t4_get_regs()
1922 0x40094, 0x400b0, in t4_get_regs()
1923 0x400c0, 0x40144, in t4_get_regs()
1924 0x40180, 0x4018c, in t4_get_regs()
1925 0x40200, 0x40254, in t4_get_regs()
1926 0x40260, 0x40264, in t4_get_regs()
1927 0x40270, 0x40288, in t4_get_regs()
1928 0x40290, 0x40298, in t4_get_regs()
1929 0x402ac, 0x402c8, in t4_get_regs()
1930 0x402d0, 0x402e0, in t4_get_regs()
1931 0x402f0, 0x402f0, in t4_get_regs()
1932 0x40300, 0x4033c, in t4_get_regs()
1933 0x403f8, 0x403fc, in t4_get_regs()
1934 0x41304, 0x413c4, in t4_get_regs()
1935 0x41400, 0x4140c, in t4_get_regs()
1936 0x41414, 0x4141c, in t4_get_regs()
1937 0x41480, 0x414d0, in t4_get_regs()
1938 0x44000, 0x44054, in t4_get_regs()
1939 0x4405c, 0x44078, in t4_get_regs()
1940 0x440c0, 0x44174, in t4_get_regs()
1941 0x44180, 0x441ac, in t4_get_regs()
1942 0x441b4, 0x441b8, in t4_get_regs()
1943 0x441c0, 0x44254, in t4_get_regs()
1944 0x4425c, 0x44278, in t4_get_regs()
1945 0x442c0, 0x44374, in t4_get_regs()
1946 0x44380, 0x443ac, in t4_get_regs()
1947 0x443b4, 0x443b8, in t4_get_regs()
1948 0x443c0, 0x44454, in t4_get_regs()
1949 0x4445c, 0x44478, in t4_get_regs()
1950 0x444c0, 0x44574, in t4_get_regs()
1951 0x44580, 0x445ac, in t4_get_regs()
1952 0x445b4, 0x445b8, in t4_get_regs()
1953 0x445c0, 0x44654, in t4_get_regs()
1954 0x4465c, 0x44678, in t4_get_regs()
1955 0x446c0, 0x44774, in t4_get_regs()
1956 0x44780, 0x447ac, in t4_get_regs()
1957 0x447b4, 0x447b8, in t4_get_regs()
1958 0x447c0, 0x44854, in t4_get_regs()
1959 0x4485c, 0x44878, in t4_get_regs()
1960 0x448c0, 0x44974, in t4_get_regs()
1961 0x44980, 0x449ac, in t4_get_regs()
1962 0x449b4, 0x449b8, in t4_get_regs()
1963 0x449c0, 0x449fc, in t4_get_regs()
1964 0x45000, 0x45004, in t4_get_regs()
1965 0x45010, 0x45030, in t4_get_regs()
1966 0x45040, 0x45060, in t4_get_regs()
1967 0x45068, 0x45068, in t4_get_regs()
1968 0x45080, 0x45084, in t4_get_regs()
1969 0x450a0, 0x450b0, in t4_get_regs()
1970 0x45200, 0x45204, in t4_get_regs()
1971 0x45210, 0x45230, in t4_get_regs()
1972 0x45240, 0x45260, in t4_get_regs()
1973 0x45268, 0x45268, in t4_get_regs()
1974 0x45280, 0x45284, in t4_get_regs()
1975 0x452a0, 0x452b0, in t4_get_regs()
1976 0x460c0, 0x460e4, in t4_get_regs()
1977 0x47000, 0x4703c, in t4_get_regs()
1978 0x47044, 0x4708c, in t4_get_regs()
1979 0x47200, 0x47250, in t4_get_regs()
1980 0x47400, 0x47408, in t4_get_regs()
1981 0x47414, 0x47420, in t4_get_regs()
1982 0x47600, 0x47618, in t4_get_regs()
1983 0x47800, 0x47814, in t4_get_regs()
1984 0x48000, 0x4800c, in t4_get_regs()
1985 0x48040, 0x48050, in t4_get_regs()
1986 0x48060, 0x48068, in t4_get_regs()
1987 0x4807c, 0x4808c, in t4_get_regs()
1988 0x48094, 0x480b0, in t4_get_regs()
1989 0x480c0, 0x48144, in t4_get_regs()
1990 0x48180, 0x4818c, in t4_get_regs()
1991 0x48200, 0x48254, in t4_get_regs()
1992 0x48260, 0x48264, in t4_get_regs()
1993 0x48270, 0x48288, in t4_get_regs()
1994 0x48290, 0x48298, in t4_get_regs()
1995 0x482ac, 0x482c8, in t4_get_regs()
1996 0x482d0, 0x482e0, in t4_get_regs()
1997 0x482f0, 0x482f0, in t4_get_regs()
1998 0x48300, 0x4833c, in t4_get_regs()
1999 0x483f8, 0x483fc, in t4_get_regs()
2000 0x49304, 0x493c4, in t4_get_regs()
2001 0x49400, 0x4940c, in t4_get_regs()
2002 0x49414, 0x4941c, in t4_get_regs()
2003 0x49480, 0x494d0, in t4_get_regs()
2004 0x4c000, 0x4c054, in t4_get_regs()
2005 0x4c05c, 0x4c078, in t4_get_regs()
2006 0x4c0c0, 0x4c174, in t4_get_regs()
2007 0x4c180, 0x4c1ac, in t4_get_regs()
2008 0x4c1b4, 0x4c1b8, in t4_get_regs()
2009 0x4c1c0, 0x4c254, in t4_get_regs()
2010 0x4c25c, 0x4c278, in t4_get_regs()
2011 0x4c2c0, 0x4c374, in t4_get_regs()
2012 0x4c380, 0x4c3ac, in t4_get_regs()
2013 0x4c3b4, 0x4c3b8, in t4_get_regs()
2014 0x4c3c0, 0x4c454, in t4_get_regs()
2015 0x4c45c, 0x4c478, in t4_get_regs()
2016 0x4c4c0, 0x4c574, in t4_get_regs()
2017 0x4c580, 0x4c5ac, in t4_get_regs()
2018 0x4c5b4, 0x4c5b8, in t4_get_regs()
2019 0x4c5c0, 0x4c654, in t4_get_regs()
2020 0x4c65c, 0x4c678, in t4_get_regs()
2021 0x4c6c0, 0x4c774, in t4_get_regs()
2022 0x4c780, 0x4c7ac, in t4_get_regs()
2023 0x4c7b4, 0x4c7b8, in t4_get_regs()
2024 0x4c7c0, 0x4c854, in t4_get_regs()
2025 0x4c85c, 0x4c878, in t4_get_regs()
2026 0x4c8c0, 0x4c974, in t4_get_regs()
2027 0x4c980, 0x4c9ac, in t4_get_regs()
2028 0x4c9b4, 0x4c9b8, in t4_get_regs()
2029 0x4c9c0, 0x4c9fc, in t4_get_regs()
2030 0x4d000, 0x4d004, in t4_get_regs()
2031 0x4d010, 0x4d030, in t4_get_regs()
2032 0x4d040, 0x4d060, in t4_get_regs()
2033 0x4d068, 0x4d068, in t4_get_regs()
2034 0x4d080, 0x4d084, in t4_get_regs()
2035 0x4d0a0, 0x4d0b0, in t4_get_regs()
2036 0x4d200, 0x4d204, in t4_get_regs()
2037 0x4d210, 0x4d230, in t4_get_regs()
2038 0x4d240, 0x4d260, in t4_get_regs()
2039 0x4d268, 0x4d268, in t4_get_regs()
2040 0x4d280, 0x4d284, in t4_get_regs()
2041 0x4d2a0, 0x4d2b0, in t4_get_regs()
2042 0x4e0c0, 0x4e0e4, in t4_get_regs()
2043 0x4f000, 0x4f03c, in t4_get_regs()
2044 0x4f044, 0x4f08c, in t4_get_regs()
2045 0x4f200, 0x4f250, in t4_get_regs()
2046 0x4f400, 0x4f408, in t4_get_regs()
2047 0x4f414, 0x4f420, in t4_get_regs()
2048 0x4f600, 0x4f618, in t4_get_regs()
2049 0x4f800, 0x4f814, in t4_get_regs()
2050 0x50000, 0x50084, in t4_get_regs()
2051 0x50090, 0x500cc, in t4_get_regs()
2052 0x50400, 0x50400, in t4_get_regs()
2053 0x50800, 0x50884, in t4_get_regs()
2054 0x50890, 0x508cc, in t4_get_regs()
2055 0x50c00, 0x50c00, in t4_get_regs()
2056 0x51000, 0x5101c, in t4_get_regs()
2057 0x51300, 0x51308, in t4_get_regs()
2073 0x1008, 0x101c, in t4_get_regs()
2074 0x1024, 0x10a8, in t4_get_regs()
2075 0x10b4, 0x10f8, in t4_get_regs()
2076 0x1100, 0x1114, in t4_get_regs()
2077 0x111c, 0x112c, in t4_get_regs()
2078 0x1138, 0x113c, in t4_get_regs()
2079 0x1144, 0x114c, in t4_get_regs()
2080 0x1180, 0x1184, in t4_get_regs()
2081 0x1190, 0x1194, in t4_get_regs()
2082 0x11a0, 0x11a4, in t4_get_regs()
2083 0x11b0, 0x11c4, in t4_get_regs()
2084 0x11fc, 0x123c, in t4_get_regs()
2085 0x1254, 0x1274, in t4_get_regs()
2086 0x1280, 0x133c, in t4_get_regs()
2087 0x1800, 0x18fc, in t4_get_regs()
2088 0x3000, 0x302c, in t4_get_regs()
2089 0x3060, 0x30b0, in t4_get_regs()
2090 0x30b8, 0x30d8, in t4_get_regs()
2091 0x30e0, 0x30fc, in t4_get_regs()
2092 0x3140, 0x357c, in t4_get_regs()
2093 0x35a8, 0x35cc, in t4_get_regs()
2094 0x35ec, 0x35ec, in t4_get_regs()
2095 0x3600, 0x5624, in t4_get_regs()
2096 0x56cc, 0x56ec, in t4_get_regs()
2097 0x56f4, 0x5720, in t4_get_regs()
2098 0x5728, 0x575c, in t4_get_regs()
2099 0x580c, 0x5814, in t4_get_regs()
2100 0x5890, 0x589c, in t4_get_regs()
2101 0x58a4, 0x58ac, in t4_get_regs()
2102 0x58b8, 0x58bc, in t4_get_regs()
2103 0x5940, 0x595c, in t4_get_regs()
2104 0x5980, 0x598c, in t4_get_regs()
2105 0x59b0, 0x59c8, in t4_get_regs()
2106 0x59d0, 0x59dc, in t4_get_regs()
2107 0x59fc, 0x5a18, in t4_get_regs()
2108 0x5a60, 0x5a6c, in t4_get_regs()
2109 0x5a80, 0x5a8c, in t4_get_regs()
2110 0x5a94, 0x5a9c, in t4_get_regs()
2111 0x5b94, 0x5bfc, in t4_get_regs()
2112 0x5c10, 0x5e48, in t4_get_regs()
2113 0x5e50, 0x5e94, in t4_get_regs()
2114 0x5ea0, 0x5eb0, in t4_get_regs()
2115 0x5ec0, 0x5ec0, in t4_get_regs()
2116 0x5ec8, 0x5ed0, in t4_get_regs()
2117 0x5ee0, 0x5ee0, in t4_get_regs()
2118 0x5ef0, 0x5ef0, in t4_get_regs()
2119 0x5f00, 0x5f00, in t4_get_regs()
2120 0x6000, 0x6020, in t4_get_regs()
2121 0x6028, 0x6040, in t4_get_regs()
2122 0x6058, 0x609c, in t4_get_regs()
2123 0x60a8, 0x619c, in t4_get_regs()
2124 0x7700, 0x7798, in t4_get_regs()
2125 0x77c0, 0x7880, in t4_get_regs()
2126 0x78cc, 0x78fc, in t4_get_regs()
2127 0x7b00, 0x7b58, in t4_get_regs()
2128 0x7b60, 0x7b84, in t4_get_regs()
2129 0x7b8c, 0x7c54, in t4_get_regs()
2130 0x7d00, 0x7d38, in t4_get_regs()
2131 0x7d40, 0x7d84, in t4_get_regs()
2132 0x7d8c, 0x7ddc, in t4_get_regs()
2133 0x7de4, 0x7e04, in t4_get_regs()
2134 0x7e10, 0x7e1c, in t4_get_regs()
2135 0x7e24, 0x7e38, in t4_get_regs()
2136 0x7e40, 0x7e44, in t4_get_regs()
2137 0x7e4c, 0x7e78, in t4_get_regs()
2138 0x7e80, 0x7edc, in t4_get_regs()
2139 0x7ee8, 0x7efc, in t4_get_regs()
2140 0x8dc0, 0x8de0, in t4_get_regs()
2141 0x8df8, 0x8e04, in t4_get_regs()
2142 0x8e10, 0x8e84, in t4_get_regs()
2143 0x8ea0, 0x8f88, in t4_get_regs()
2144 0x8fb8, 0x9058, in t4_get_regs()
2145 0x9060, 0x9060, in t4_get_regs()
2146 0x9068, 0x90f8, in t4_get_regs()
2147 0x9100, 0x9124, in t4_get_regs()
2148 0x9400, 0x9470, in t4_get_regs()
2149 0x9600, 0x9600, in t4_get_regs()
2150 0x9608, 0x9638, in t4_get_regs()
2151 0x9640, 0x9704, in t4_get_regs()
2152 0x9710, 0x971c, in t4_get_regs()
2153 0x9800, 0x9808, in t4_get_regs()
2154 0x9810, 0x9864, in t4_get_regs()
2155 0x9c00, 0x9c6c, in t4_get_regs()
2156 0x9c80, 0x9cec, in t4_get_regs()
2157 0x9d00, 0x9d6c, in t4_get_regs()
2158 0x9d80, 0x9dec, in t4_get_regs()
2159 0x9e00, 0x9e6c, in t4_get_regs()
2160 0x9e80, 0x9eec, in t4_get_regs()
2161 0x9f00, 0x9f6c, in t4_get_regs()
2162 0x9f80, 0xa020, in t4_get_regs()
2163 0xd000, 0xd03c, in t4_get_regs()
2164 0xd100, 0xd118, in t4_get_regs()
2165 0xd200, 0xd214, in t4_get_regs()
2166 0xd220, 0xd234, in t4_get_regs()
2167 0xd240, 0xd254, in t4_get_regs()
2168 0xd260, 0xd274, in t4_get_regs()
2169 0xd280, 0xd294, in t4_get_regs()
2170 0xd2a0, 0xd2b4, in t4_get_regs()
2171 0xd2c0, 0xd2d4, in t4_get_regs()
2172 0xd2e0, 0xd2f4, in t4_get_regs()
2173 0xd300, 0xd31c, in t4_get_regs()
2174 0xdfc0, 0xdfe0, in t4_get_regs()
2175 0xe000, 0xf008, in t4_get_regs()
2176 0xf010, 0xf018, in t4_get_regs()
2177 0xf020, 0xf028, in t4_get_regs()
2178 0x11000, 0x11014, in t4_get_regs()
2179 0x11048, 0x1106c, in t4_get_regs()
2180 0x11074, 0x11088, in t4_get_regs()
2181 0x11098, 0x11120, in t4_get_regs()
2182 0x1112c, 0x1117c, in t4_get_regs()
2183 0x11190, 0x112e0, in t4_get_regs()
2184 0x11300, 0x1130c, in t4_get_regs()
2185 0x12000, 0x1206c, in t4_get_regs()
2186 0x19040, 0x1906c, in t4_get_regs()
2187 0x19078, 0x19080, in t4_get_regs()
2188 0x1908c, 0x190e8, in t4_get_regs()
2189 0x190f0, 0x190f8, in t4_get_regs()
2190 0x19100, 0x19110, in t4_get_regs()
2191 0x19120, 0x19124, in t4_get_regs()
2192 0x19150, 0x19194, in t4_get_regs()
2193 0x1919c, 0x191b0, in t4_get_regs()
2194 0x191d0, 0x191e8, in t4_get_regs()
2195 0x19238, 0x19290, in t4_get_regs()
2196 0x192a4, 0x192b0, in t4_get_regs()
2197 0x19348, 0x1934c, in t4_get_regs()
2198 0x193f8, 0x19418, in t4_get_regs()
2199 0x19420, 0x19428, in t4_get_regs()
2200 0x19430, 0x19444, in t4_get_regs()
2201 0x1944c, 0x1946c, in t4_get_regs()
2202 0x19474, 0x19474, in t4_get_regs()
2203 0x19490, 0x194cc, in t4_get_regs()
2204 0x194f0, 0x194f8, in t4_get_regs()
2205 0x19c00, 0x19c48, in t4_get_regs()
2206 0x19c50, 0x19c80, in t4_get_regs()
2207 0x19c94, 0x19c98, in t4_get_regs()
2208 0x19ca0, 0x19cbc, in t4_get_regs()
2209 0x19ce4, 0x19ce4, in t4_get_regs()
2210 0x19cf0, 0x19cf8, in t4_get_regs()
2211 0x19d00, 0x19d28, in t4_get_regs()
2212 0x19d50, 0x19d78, in t4_get_regs()
2213 0x19d94, 0x19d98, in t4_get_regs()
2214 0x19da0, 0x19de0, in t4_get_regs()
2215 0x19df0, 0x19e10, in t4_get_regs()
2216 0x19e50, 0x19e6c, in t4_get_regs()
2217 0x19ea0, 0x19ebc, in t4_get_regs()
2218 0x19ec4, 0x19ef4, in t4_get_regs()
2219 0x19f04, 0x19f2c, in t4_get_regs()
2220 0x19f34, 0x19f34, in t4_get_regs()
2221 0x19f40, 0x19f50, in t4_get_regs()
2222 0x19f90, 0x19fac, in t4_get_regs()
2223 0x19fc4, 0x19fc8, in t4_get_regs()
2224 0x19fd0, 0x19fe4, in t4_get_regs()
2225 0x1a000, 0x1a004, in t4_get_regs()
2226 0x1a010, 0x1a06c, in t4_get_regs()
2227 0x1a0b0, 0x1a0e4, in t4_get_regs()
2228 0x1a0ec, 0x1a0f8, in t4_get_regs()
2229 0x1a100, 0x1a108, in t4_get_regs()
2230 0x1a114, 0x1a130, in t4_get_regs()
2231 0x1a138, 0x1a1c4, in t4_get_regs()
2232 0x1a1fc, 0x1a1fc, in t4_get_regs()
2233 0x1e008, 0x1e00c, in t4_get_regs()
2234 0x1e040, 0x1e044, in t4_get_regs()
2235 0x1e04c, 0x1e04c, in t4_get_regs()
2236 0x1e284, 0x1e290, in t4_get_regs()
2237 0x1e2c0, 0x1e2c0, in t4_get_regs()
2238 0x1e2e0, 0x1e2e0, in t4_get_regs()
2239 0x1e300, 0x1e384, in t4_get_regs()
2240 0x1e3c0, 0x1e3c8, in t4_get_regs()
2241 0x1e408, 0x1e40c, in t4_get_regs()
2242 0x1e440, 0x1e444, in t4_get_regs()
2243 0x1e44c, 0x1e44c, in t4_get_regs()
2244 0x1e684, 0x1e690, in t4_get_regs()
2245 0x1e6c0, 0x1e6c0, in t4_get_regs()
2246 0x1e6e0, 0x1e6e0, in t4_get_regs()
2247 0x1e700, 0x1e784, in t4_get_regs()
2248 0x1e7c0, 0x1e7c8, in t4_get_regs()
2249 0x1e808, 0x1e80c, in t4_get_regs()
2250 0x1e840, 0x1e844, in t4_get_regs()
2251 0x1e84c, 0x1e84c, in t4_get_regs()
2252 0x1ea84, 0x1ea90, in t4_get_regs()
2253 0x1eac0, 0x1eac0, in t4_get_regs()
2254 0x1eae0, 0x1eae0, in t4_get_regs()
2255 0x1eb00, 0x1eb84, in t4_get_regs()
2256 0x1ebc0, 0x1ebc8, in t4_get_regs()
2257 0x1ec08, 0x1ec0c, in t4_get_regs()
2258 0x1ec40, 0x1ec44, in t4_get_regs()
2259 0x1ec4c, 0x1ec4c, in t4_get_regs()
2260 0x1ee84, 0x1ee90, in t4_get_regs()
2261 0x1eec0, 0x1eec0, in t4_get_regs()
2262 0x1eee0, 0x1eee0, in t4_get_regs()
2263 0x1ef00, 0x1ef84, in t4_get_regs()
2264 0x1efc0, 0x1efc8, in t4_get_regs()
2265 0x1f008, 0x1f00c, in t4_get_regs()
2266 0x1f040, 0x1f044, in t4_get_regs()
2267 0x1f04c, 0x1f04c, in t4_get_regs()
2268 0x1f284, 0x1f290, in t4_get_regs()
2269 0x1f2c0, 0x1f2c0, in t4_get_regs()
2270 0x1f2e0, 0x1f2e0, in t4_get_regs()
2271 0x1f300, 0x1f384, in t4_get_regs()
2272 0x1f3c0, 0x1f3c8, in t4_get_regs()
2273 0x1f408, 0x1f40c, in t4_get_regs()
2274 0x1f440, 0x1f444, in t4_get_regs()
2275 0x1f44c, 0x1f44c, in t4_get_regs()
2276 0x1f684, 0x1f690, in t4_get_regs()
2277 0x1f6c0, 0x1f6c0, in t4_get_regs()
2278 0x1f6e0, 0x1f6e0, in t4_get_regs()
2279 0x1f700, 0x1f784, in t4_get_regs()
2280 0x1f7c0, 0x1f7c8, in t4_get_regs()
2281 0x1f808, 0x1f80c, in t4_get_regs()
2282 0x1f840, 0x1f844, in t4_get_regs()
2283 0x1f84c, 0x1f84c, in t4_get_regs()
2284 0x1fa84, 0x1fa90, in t4_get_regs()
2285 0x1fac0, 0x1fac0, in t4_get_regs()
2286 0x1fae0, 0x1fae0, in t4_get_regs()
2287 0x1fb00, 0x1fb84, in t4_get_regs()
2288 0x1fbc0, 0x1fbc8, in t4_get_regs()
2289 0x1fc08, 0x1fc0c, in t4_get_regs()
2290 0x1fc40, 0x1fc44, in t4_get_regs()
2291 0x1fc4c, 0x1fc4c, in t4_get_regs()
2292 0x1fe84, 0x1fe90, in t4_get_regs()
2293 0x1fec0, 0x1fec0, in t4_get_regs()
2294 0x1fee0, 0x1fee0, in t4_get_regs()
2295 0x1ff00, 0x1ff84, in t4_get_regs()
2296 0x1ffc0, 0x1ffc8, in t4_get_regs()
2297 0x30000, 0x30030, in t4_get_regs()
2298 0x30100, 0x30168, in t4_get_regs()
2299 0x30190, 0x301a0, in t4_get_regs()
2300 0x301a8, 0x301b8, in t4_get_regs()
2301 0x301c4, 0x301c8, in t4_get_regs()
2302 0x301d0, 0x301d0, in t4_get_regs()
2303 0x30200, 0x30320, in t4_get_regs()
2304 0x30400, 0x304b4, in t4_get_regs()
2305 0x304c0, 0x3052c, in t4_get_regs()
2306 0x30540, 0x3061c, in t4_get_regs()
2307 0x30800, 0x308a0, in t4_get_regs()
2308 0x308c0, 0x30908, in t4_get_regs()
2309 0x30910, 0x309b8, in t4_get_regs()
2310 0x30a00, 0x30a04, in t4_get_regs()
2311 0x30a0c, 0x30a14, in t4_get_regs()
2312 0x30a1c, 0x30a2c, in t4_get_regs()
2313 0x30a44, 0x30a50, in t4_get_regs()
2314 0x30a74, 0x30a74, in t4_get_regs()
2315 0x30a7c, 0x30afc, in t4_get_regs()
2316 0x30b08, 0x30c24, in t4_get_regs()
2317 0x30d00, 0x30d14, in t4_get_regs()
2318 0x30d1c, 0x30d3c, in t4_get_regs()
2319 0x30d44, 0x30d4c, in t4_get_regs()
2320 0x30d54, 0x30d74, in t4_get_regs()
2321 0x30d7c, 0x30d7c, in t4_get_regs()
2322 0x30de0, 0x30de0, in t4_get_regs()
2323 0x30e00, 0x30ed4, in t4_get_regs()
2324 0x30f00, 0x30fa4, in t4_get_regs()
2325 0x30fc0, 0x30fc4, in t4_get_regs()
2326 0x31000, 0x31004, in t4_get_regs()
2327 0x31080, 0x310fc, in t4_get_regs()
2328 0x31208, 0x31220, in t4_get_regs()
2329 0x3123c, 0x31254, in t4_get_regs()
2330 0x31300, 0x31300, in t4_get_regs()
2331 0x31308, 0x3131c, in t4_get_regs()
2332 0x31338, 0x3133c, in t4_get_regs()
2333 0x31380, 0x31380, in t4_get_regs()
2334 0x31388, 0x313a8, in t4_get_regs()
2335 0x313b4, 0x313b4, in t4_get_regs()
2336 0x31400, 0x31420, in t4_get_regs()
2337 0x31438, 0x3143c, in t4_get_regs()
2338 0x31480, 0x31480, in t4_get_regs()
2339 0x314a8, 0x314a8, in t4_get_regs()
2340 0x314b0, 0x314b4, in t4_get_regs()
2341 0x314c8, 0x314d4, in t4_get_regs()
2342 0x31a40, 0x31a4c, in t4_get_regs()
2343 0x31af0, 0x31b20, in t4_get_regs()
2344 0x31b38, 0x31b3c, in t4_get_regs()
2345 0x31b80, 0x31b80, in t4_get_regs()
2346 0x31ba8, 0x31ba8, in t4_get_regs()
2347 0x31bb0, 0x31bb4, in t4_get_regs()
2348 0x31bc8, 0x31bd4, in t4_get_regs()
2349 0x32140, 0x3218c, in t4_get_regs()
2350 0x321f0, 0x321f4, in t4_get_regs()
2351 0x32200, 0x32200, in t4_get_regs()
2352 0x32218, 0x32218, in t4_get_regs()
2353 0x32400, 0x32400, in t4_get_regs()
2354 0x32408, 0x3241c, in t4_get_regs()
2355 0x32618, 0x32620, in t4_get_regs()
2356 0x32664, 0x32664, in t4_get_regs()
2357 0x326a8, 0x326a8, in t4_get_regs()
2358 0x326ec, 0x326ec, in t4_get_regs()
2359 0x32a00, 0x32abc, in t4_get_regs()
2360 0x32b00, 0x32b18, in t4_get_regs()
2361 0x32b20, 0x32b38, in t4_get_regs()
2362 0x32b40, 0x32b58, in t4_get_regs()
2363 0x32b60, 0x32b78, in t4_get_regs()
2364 0x32c00, 0x32c00, in t4_get_regs()
2365 0x32c08, 0x32c3c, in t4_get_regs()
2366 0x33000, 0x3302c, in t4_get_regs()
2367 0x33034, 0x33050, in t4_get_regs()
2368 0x33058, 0x33058, in t4_get_regs()
2369 0x33060, 0x3308c, in t4_get_regs()
2370 0x3309c, 0x330ac, in t4_get_regs()
2371 0x330c0, 0x330c0, in t4_get_regs()
2372 0x330c8, 0x330d0, in t4_get_regs()
2373 0x330d8, 0x330e0, in t4_get_regs()
2374 0x330ec, 0x3312c, in t4_get_regs()
2375 0x33134, 0x33150, in t4_get_regs()
2376 0x33158, 0x33158, in t4_get_regs()
2377 0x33160, 0x3318c, in t4_get_regs()
2378 0x3319c, 0x331ac, in t4_get_regs()
2379 0x331c0, 0x331c0, in t4_get_regs()
2380 0x331c8, 0x331d0, in t4_get_regs()
2381 0x331d8, 0x331e0, in t4_get_regs()
2382 0x331ec, 0x33290, in t4_get_regs()
2383 0x33298, 0x332c4, in t4_get_regs()
2384 0x332e4, 0x33390, in t4_get_regs()
2385 0x33398, 0x333c4, in t4_get_regs()
2386 0x333e4, 0x3342c, in t4_get_regs()
2387 0x33434, 0x33450, in t4_get_regs()
2388 0x33458, 0x33458, in t4_get_regs()
2389 0x33460, 0x3348c, in t4_get_regs()
2390 0x3349c, 0x334ac, in t4_get_regs()
2391 0x334c0, 0x334c0, in t4_get_regs()
2392 0x334c8, 0x334d0, in t4_get_regs()
2393 0x334d8, 0x334e0, in t4_get_regs()
2394 0x334ec, 0x3352c, in t4_get_regs()
2395 0x33534, 0x33550, in t4_get_regs()
2396 0x33558, 0x33558, in t4_get_regs()
2397 0x33560, 0x3358c, in t4_get_regs()
2398 0x3359c, 0x335ac, in t4_get_regs()
2399 0x335c0, 0x335c0, in t4_get_regs()
2400 0x335c8, 0x335d0, in t4_get_regs()
2401 0x335d8, 0x335e0, in t4_get_regs()
2402 0x335ec, 0x33690, in t4_get_regs()
2403 0x33698, 0x336c4, in t4_get_regs()
2404 0x336e4, 0x33790, in t4_get_regs()
2405 0x33798, 0x337c4, in t4_get_regs()
2406 0x337e4, 0x337fc, in t4_get_regs()
2407 0x33814, 0x33814, in t4_get_regs()
2408 0x33854, 0x33868, in t4_get_regs()
2409 0x33880, 0x3388c, in t4_get_regs()
2410 0x338c0, 0x338d0, in t4_get_regs()
2411 0x338e8, 0x338ec, in t4_get_regs()
2412 0x33900, 0x3392c, in t4_get_regs()
2413 0x33934, 0x33950, in t4_get_regs()
2414 0x33958, 0x33958, in t4_get_regs()
2415 0x33960, 0x3398c, in t4_get_regs()
2416 0x3399c, 0x339ac, in t4_get_regs()
2417 0x339c0, 0x339c0, in t4_get_regs()
2418 0x339c8, 0x339d0, in t4_get_regs()
2419 0x339d8, 0x339e0, in t4_get_regs()
2420 0x339ec, 0x33a90, in t4_get_regs()
2421 0x33a98, 0x33ac4, in t4_get_regs()
2422 0x33ae4, 0x33b10, in t4_get_regs()
2423 0x33b24, 0x33b28, in t4_get_regs()
2424 0x33b38, 0x33b50, in t4_get_regs()
2425 0x33bf0, 0x33c10, in t4_get_regs()
2426 0x33c24, 0x33c28, in t4_get_regs()
2427 0x33c38, 0x33c50, in t4_get_regs()
2428 0x33cf0, 0x33cfc, in t4_get_regs()
2429 0x34000, 0x34030, in t4_get_regs()
2430 0x34100, 0x34168, in t4_get_regs()
2431 0x34190, 0x341a0, in t4_get_regs()
2432 0x341a8, 0x341b8, in t4_get_regs()
2433 0x341c4, 0x341c8, in t4_get_regs()
2434 0x341d0, 0x341d0, in t4_get_regs()
2435 0x34200, 0x34320, in t4_get_regs()
2436 0x34400, 0x344b4, in t4_get_regs()
2437 0x344c0, 0x3452c, in t4_get_regs()
2438 0x34540, 0x3461c, in t4_get_regs()
2439 0x34800, 0x348a0, in t4_get_regs()
2440 0x348c0, 0x34908, in t4_get_regs()
2441 0x34910, 0x349b8, in t4_get_regs()
2442 0x34a00, 0x34a04, in t4_get_regs()
2443 0x34a0c, 0x34a14, in t4_get_regs()
2444 0x34a1c, 0x34a2c, in t4_get_regs()
2445 0x34a44, 0x34a50, in t4_get_regs()
2446 0x34a74, 0x34a74, in t4_get_regs()
2447 0x34a7c, 0x34afc, in t4_get_regs()
2448 0x34b08, 0x34c24, in t4_get_regs()
2449 0x34d00, 0x34d14, in t4_get_regs()
2450 0x34d1c, 0x34d3c, in t4_get_regs()
2451 0x34d44, 0x34d4c, in t4_get_regs()
2452 0x34d54, 0x34d74, in t4_get_regs()
2453 0x34d7c, 0x34d7c, in t4_get_regs()
2454 0x34de0, 0x34de0, in t4_get_regs()
2455 0x34e00, 0x34ed4, in t4_get_regs()
2456 0x34f00, 0x34fa4, in t4_get_regs()
2457 0x34fc0, 0x34fc4, in t4_get_regs()
2458 0x35000, 0x35004, in t4_get_regs()
2459 0x35080, 0x350fc, in t4_get_regs()
2460 0x35208, 0x35220, in t4_get_regs()
2461 0x3523c, 0x35254, in t4_get_regs()
2462 0x35300, 0x35300, in t4_get_regs()
2463 0x35308, 0x3531c, in t4_get_regs()
2464 0x35338, 0x3533c, in t4_get_regs()
2465 0x35380, 0x35380, in t4_get_regs()
2466 0x35388, 0x353a8, in t4_get_regs()
2467 0x353b4, 0x353b4, in t4_get_regs()
2468 0x35400, 0x35420, in t4_get_regs()
2469 0x35438, 0x3543c, in t4_get_regs()
2470 0x35480, 0x35480, in t4_get_regs()
2471 0x354a8, 0x354a8, in t4_get_regs()
2472 0x354b0, 0x354b4, in t4_get_regs()
2473 0x354c8, 0x354d4, in t4_get_regs()
2474 0x35a40, 0x35a4c, in t4_get_regs()
2475 0x35af0, 0x35b20, in t4_get_regs()
2476 0x35b38, 0x35b3c, in t4_get_regs()
2477 0x35b80, 0x35b80, in t4_get_regs()
2478 0x35ba8, 0x35ba8, in t4_get_regs()
2479 0x35bb0, 0x35bb4, in t4_get_regs()
2480 0x35bc8, 0x35bd4, in t4_get_regs()
2481 0x36140, 0x3618c, in t4_get_regs()
2482 0x361f0, 0x361f4, in t4_get_regs()
2483 0x36200, 0x36200, in t4_get_regs()
2484 0x36218, 0x36218, in t4_get_regs()
2485 0x36400, 0x36400, in t4_get_regs()
2486 0x36408, 0x3641c, in t4_get_regs()
2487 0x36618, 0x36620, in t4_get_regs()
2488 0x36664, 0x36664, in t4_get_regs()
2489 0x366a8, 0x366a8, in t4_get_regs()
2490 0x366ec, 0x366ec, in t4_get_regs()
2491 0x36a00, 0x36abc, in t4_get_regs()
2492 0x36b00, 0x36b18, in t4_get_regs()
2493 0x36b20, 0x36b38, in t4_get_regs()
2494 0x36b40, 0x36b58, in t4_get_regs()
2495 0x36b60, 0x36b78, in t4_get_regs()
2496 0x36c00, 0x36c00, in t4_get_regs()
2497 0x36c08, 0x36c3c, in t4_get_regs()
2498 0x37000, 0x3702c, in t4_get_regs()
2499 0x37034, 0x37050, in t4_get_regs()
2500 0x37058, 0x37058, in t4_get_regs()
2501 0x37060, 0x3708c, in t4_get_regs()
2502 0x3709c, 0x370ac, in t4_get_regs()
2503 0x370c0, 0x370c0, in t4_get_regs()
2504 0x370c8, 0x370d0, in t4_get_regs()
2505 0x370d8, 0x370e0, in t4_get_regs()
2506 0x370ec, 0x3712c, in t4_get_regs()
2507 0x37134, 0x37150, in t4_get_regs()
2508 0x37158, 0x37158, in t4_get_regs()
2509 0x37160, 0x3718c, in t4_get_regs()
2510 0x3719c, 0x371ac, in t4_get_regs()
2511 0x371c0, 0x371c0, in t4_get_regs()
2512 0x371c8, 0x371d0, in t4_get_regs()
2513 0x371d8, 0x371e0, in t4_get_regs()
2514 0x371ec, 0x37290, in t4_get_regs()
2515 0x37298, 0x372c4, in t4_get_regs()
2516 0x372e4, 0x37390, in t4_get_regs()
2517 0x37398, 0x373c4, in t4_get_regs()
2518 0x373e4, 0x3742c, in t4_get_regs()
2519 0x37434, 0x37450, in t4_get_regs()
2520 0x37458, 0x37458, in t4_get_regs()
2521 0x37460, 0x3748c, in t4_get_regs()
2522 0x3749c, 0x374ac, in t4_get_regs()
2523 0x374c0, 0x374c0, in t4_get_regs()
2524 0x374c8, 0x374d0, in t4_get_regs()
2525 0x374d8, 0x374e0, in t4_get_regs()
2526 0x374ec, 0x3752c, in t4_get_regs()
2527 0x37534, 0x37550, in t4_get_regs()
2528 0x37558, 0x37558, in t4_get_regs()
2529 0x37560, 0x3758c, in t4_get_regs()
2530 0x3759c, 0x375ac, in t4_get_regs()
2531 0x375c0, 0x375c0, in t4_get_regs()
2532 0x375c8, 0x375d0, in t4_get_regs()
2533 0x375d8, 0x375e0, in t4_get_regs()
2534 0x375ec, 0x37690, in t4_get_regs()
2535 0x37698, 0x376c4, in t4_get_regs()
2536 0x376e4, 0x37790, in t4_get_regs()
2537 0x37798, 0x377c4, in t4_get_regs()
2538 0x377e4, 0x377fc, in t4_get_regs()
2539 0x37814, 0x37814, in t4_get_regs()
2540 0x37854, 0x37868, in t4_get_regs()
2541 0x37880, 0x3788c, in t4_get_regs()
2542 0x378c0, 0x378d0, in t4_get_regs()
2543 0x378e8, 0x378ec, in t4_get_regs()
2544 0x37900, 0x3792c, in t4_get_regs()
2545 0x37934, 0x37950, in t4_get_regs()
2546 0x37958, 0x37958, in t4_get_regs()
2547 0x37960, 0x3798c, in t4_get_regs()
2548 0x3799c, 0x379ac, in t4_get_regs()
2549 0x379c0, 0x379c0, in t4_get_regs()
2550 0x379c8, 0x379d0, in t4_get_regs()
2551 0x379d8, 0x379e0, in t4_get_regs()
2552 0x379ec, 0x37a90, in t4_get_regs()
2553 0x37a98, 0x37ac4, in t4_get_regs()
2554 0x37ae4, 0x37b10, in t4_get_regs()
2555 0x37b24, 0x37b28, in t4_get_regs()
2556 0x37b38, 0x37b50, in t4_get_regs()
2557 0x37bf0, 0x37c10, in t4_get_regs()
2558 0x37c24, 0x37c28, in t4_get_regs()
2559 0x37c38, 0x37c50, in t4_get_regs()
2560 0x37cf0, 0x37cfc, in t4_get_regs()
2561 0x40040, 0x40040, in t4_get_regs()
2562 0x40080, 0x40084, in t4_get_regs()
2563 0x40100, 0x40100, in t4_get_regs()
2564 0x40140, 0x401bc, in t4_get_regs()
2565 0x40200, 0x40214, in t4_get_regs()
2566 0x40228, 0x40228, in t4_get_regs()
2567 0x40240, 0x40258, in t4_get_regs()
2568 0x40280, 0x40280, in t4_get_regs()
2569 0x40304, 0x40304, in t4_get_regs()
2570 0x40330, 0x4033c, in t4_get_regs()
2571 0x41304, 0x413c8, in t4_get_regs()
2572 0x413d0, 0x413dc, in t4_get_regs()
2573 0x413f0, 0x413f0, in t4_get_regs()
2574 0x41400, 0x4140c, in t4_get_regs()
2575 0x41414, 0x4141c, in t4_get_regs()
2576 0x41480, 0x414d0, in t4_get_regs()
2577 0x44000, 0x4407c, in t4_get_regs()
2578 0x440c0, 0x441ac, in t4_get_regs()
2579 0x441b4, 0x4427c, in t4_get_regs()
2580 0x442c0, 0x443ac, in t4_get_regs()
2581 0x443b4, 0x4447c, in t4_get_regs()
2582 0x444c0, 0x445ac, in t4_get_regs()
2583 0x445b4, 0x4467c, in t4_get_regs()
2584 0x446c0, 0x447ac, in t4_get_regs()
2585 0x447b4, 0x4487c, in t4_get_regs()
2586 0x448c0, 0x449ac, in t4_get_regs()
2587 0x449b4, 0x44a7c, in t4_get_regs()
2588 0x44ac0, 0x44bac, in t4_get_regs()
2589 0x44bb4, 0x44c7c, in t4_get_regs()
2590 0x44cc0, 0x44dac, in t4_get_regs()
2591 0x44db4, 0x44e7c, in t4_get_regs()
2592 0x44ec0, 0x44fac, in t4_get_regs()
2593 0x44fb4, 0x4507c, in t4_get_regs()
2594 0x450c0, 0x451ac, in t4_get_regs()
2595 0x451b4, 0x451fc, in t4_get_regs()
2596 0x45800, 0x45804, in t4_get_regs()
2597 0x45810, 0x45830, in t4_get_regs()
2598 0x45840, 0x45860, in t4_get_regs()
2599 0x45868, 0x45868, in t4_get_regs()
2600 0x45880, 0x45884, in t4_get_regs()
2601 0x458a0, 0x458b0, in t4_get_regs()
2602 0x45a00, 0x45a04, in t4_get_regs()
2603 0x45a10, 0x45a30, in t4_get_regs()
2604 0x45a40, 0x45a60, in t4_get_regs()
2605 0x45a68, 0x45a68, in t4_get_regs()
2606 0x45a80, 0x45a84, in t4_get_regs()
2607 0x45aa0, 0x45ab0, in t4_get_regs()
2608 0x460c0, 0x460e4, in t4_get_regs()
2609 0x47000, 0x4703c, in t4_get_regs()
2610 0x47044, 0x4708c, in t4_get_regs()
2611 0x47200, 0x47250, in t4_get_regs()
2612 0x47400, 0x47408, in t4_get_regs()
2613 0x47414, 0x47420, in t4_get_regs()
2614 0x47600, 0x47618, in t4_get_regs()
2615 0x47800, 0x47814, in t4_get_regs()
2616 0x47820, 0x4782c, in t4_get_regs()
2617 0x50000, 0x50084, in t4_get_regs()
2618 0x50090, 0x500cc, in t4_get_regs()
2619 0x50300, 0x50384, in t4_get_regs()
2620 0x50400, 0x50400, in t4_get_regs()
2621 0x50800, 0x50884, in t4_get_regs()
2622 0x50890, 0x508cc, in t4_get_regs()
2623 0x50b00, 0x50b84, in t4_get_regs()
2624 0x50c00, 0x50c00, in t4_get_regs()
2625 0x51000, 0x51020, in t4_get_regs()
2626 0x51028, 0x510b0, in t4_get_regs()
2627 0x51300, 0x51324, in t4_get_regs()
2692 memset(buf, 0, buf_size); in t4_get_regs()
2693 for (range = 0; range < reg_ranges_size; range += 2) { in t4_get_regs()
2730 #define EEPROM_STAT_ADDR 0x7bfc
2731 #define VPD_SIZE 0x800
2732 #define VPD_BASE 0x400
2733 #define VPD_BASE_OLD 0
2736 #define CHELSIO_VPD_UNIQUE_ID 0x82
2755 return 0; in t4_seeprom_wait()
2773 adapter->vpd_busy = 0; in t4_seeprom_wait()
2774 return 0; in t4_seeprom_wait()
2840 return 0; in t4_seeprom_read()
2887 adapter->vpd_flag = 0; in t4_seeprom_write()
2898 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); in t4_seeprom_write()
2903 } while ((stats_reg & 0x1) && --max_poll); in t4_seeprom_write()
2908 return 0; in t4_seeprom_write()
2919 * accessed through virtual addresses starting at 0.
2922 * [0..1K) -> [31K..32K)
2924 * [1K+A..ES) -> [0..ES-A-1K)
2949 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); in t4_seeprom_wp()
2956 * @region: VPD region to search (starting from 0)
2970 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
2976 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); in get_vpd_keyword_val()
2985 if (memcmp(vpd + i , kw , 2) == 0){ in get_vpd_keyword_val()
3015 * it at 0. in get_vpd_params()
3023 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD in get_vpd_params()
3024 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software in get_vpd_params()
3030 for (i = 0; i < VPD_LEN; i += 4) { in get_vpd_params()
3037 var = get_vpd_keyword_val(vpd, name, 0); \ in get_vpd_params()
3038 if (var < 0) { \ in get_vpd_params()
3042 } while (0) in get_vpd_params()
3045 for (csum = 0; i >= 0; i--) in get_vpd_params()
3074 if (device_id & 0x80) in get_vpd_params()
3075 return 0; /* Custom card */ in get_vpd_params()
3078 if (md < 0) { in get_vpd_params()
3086 return 0; in get_vpd_params()
3098 SF_RD_DATA_FAST = 0xb, /* read flash */
3099 SF_RD_ID = 0x9f, /* read ID */
3100 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */
3126 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); in sf1_read()
3154 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); in sf1_write()
3171 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || in flash_wait_op()
3172 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) in flash_wait_op()
3175 return 0; in flash_wait_op()
3176 if (--attempts == 0) in flash_wait_op()
3206 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || in t4_read_flash()
3207 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) in t4_read_flash()
3213 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ in t4_read_flash()
3219 return 0; in t4_read_flash()
3240 unsigned int i, c, left, val, offset = addr & 0xff; in t4_write_flash()
3247 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || in t4_write_flash()
3248 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) in t4_write_flash()
3253 for (val = 0, i = 0; i < c; ++i) in t4_write_flash()
3267 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ in t4_write_flash()
3270 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, in t4_write_flash()
3281 return 0; in t4_write_flash()
3284 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ in t4_write_flash()
3299 vers, 0); in t4_get_fw_version()
3326 vers, 0); in t4_get_bs_version()
3340 1, vers, 0); in t4_get_tp_version()
3351 * 0 on success, -ENOENT if no Expansion ROM is present.
3356 unsigned char hdr_arr[16]; /* must start with 0x55aa */ in t4_get_exprom_version()
3365 0); in t4_get_exprom_version()
3370 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) in t4_get_exprom_version()
3373 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | in t4_get_exprom_version()
3377 return 0; in t4_get_exprom_version()
3388 * adapter specific. Returns 0 on success, an error on failure.
3410 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_scfg_version()
3413 *vers = 0; in t4_get_scfg_version()
3424 * VPD version is adapter specific. Returns 0 on success, an error on
3445 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, in t4_get_vpd_version()
3448 *vers = 0; in t4_get_vpd_version()
3463 int ret = 0; in t4_get_version_info()
3470 } while (0) in t4_get_version_info()
3494 int ret = 0; in t4_flash_erase_sectors()
3500 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || in t4_flash_erase_sectors()
3501 (ret = sf1_write(adapter, 4, 0, 1, in t4_flash_erase_sectors()
3502 SF_ERASE_SECTOR | (start << 8))) != 0 || in t4_flash_erase_sectors()
3503 (ret = flash_wait_op(adapter, 14, 500)) != 0) { in t4_flash_erase_sectors()
3511 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ in t4_flash_erase_sectors()
3556 return 0; in t4_fw_matches_chip()
3612 for (csum = 0, i = 0; i < size / sizeof(csum); i++) in t4_load_fw()
3615 if (csum != 0xffffffff) { in t4_load_fw()
3632 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); in t4_load_fw()
3665 memset(&c, 0, sizeof(c)); in t4_fwcache()
3670 V_FW_PARAMS_CMD_VFN(0)); in t4_fwcache()
3672 c.param[0].mnem = in t4_fwcache()
3675 c.param[0].val = (__force __be32)op; in t4_fwcache()
3699 for (i = 0; i < CIM_PIFLA_SIZE; i++) { in t4_cim_read_pif_la()
3700 for (j = 0; j < 6; j++) { in t4_cim_read_pif_la()
3723 for (i = 0; i < CIM_MALA_SIZE; i++) { in t4_cim_read_ma_la()
3724 for (j = 0; j < 5; j++) { in t4_cim_read_ma_la()
3739 for (i = 0; i < 8; i++) { in t4_ulprx_read_la()
3745 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) in t4_ulprx_read_la()
3758 uint32_t caps32 = 0; in fwcaps16_to_caps32()
3764 } while (0) in fwcaps16_to_caps32()
3798 uint16_t caps16 = 0; in fwcaps32_to_caps16()
3804 } while (0) in fwcaps32_to_caps16()
3830 int8_t fec = 0; in fwcap_to_fec()
3832 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) in fwcap_to_fec()
3833 return (unset_means_none ? FEC_NONE : 0); in fwcap_to_fec()
3846 * Note that 0 is not translated to NO_FEC.
3850 uint32_t caps = 0; in fec_to_fwcap()
3853 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); in fec_to_fwcap()
3885 fc = 0; in t4_link_l1cfg()
3894 aneg = 0; in t4_link_l1cfg()
3903 } else if (lc->requested_speed != 0) in t4_link_l1cfg()
3908 fec = 0; in t4_link_l1cfg()
3915 force_fec = 0; in t4_link_l1cfg()
3918 if (force_fec > 0) { in t4_link_l1cfg()
3964 if (force_fec != 0) in t4_link_l1cfg()
3978 fec = 0; in t4_link_l1cfg()
3988 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, in t4_link_l1cfg()
3995 memset(&c, 0, sizeof(c)); in t4_link_l1cfg()
4027 memset(&c, 0, sizeof(c)); in t4_restart_aneg()
4084 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", in t4_show_intr_info()
4088 for (details = ii->details; details && details->mask != 0; details++) { in t4_show_intr_info()
4090 if (msgbits == 0) in t4_show_intr_info()
4093 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, in t4_show_intr_info()
4097 if (leftover != 0 && leftover != cause) in t4_show_intr_info()
4098 CH_ALERT(adap, " ? [0x%08x]\n", leftover); in t4_show_intr_info()
4120 if (verbose || cause != 0) in t4_handle_intr()
4123 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) in t4_handle_intr()
4126 if (cause == 0) in t4_handle_intr()
4129 rc = fatal != 0; in t4_handle_intr()
4130 for (action = ii->actions; action && action->mask != 0; action++) { in t4_handle_intr()
4154 { 0 } in pcie_intr_handler()
4161 .flags = 0, in pcie_intr_handler()
4175 { 0 } in pcie_intr_handler()
4183 .flags = 0, in pcie_intr_handler()
4218 { 0 } in pcie_intr_handler()
4252 { 0 } in pcie_intr_handler()
4258 .fatal = 0xffffffff, in pcie_intr_handler()
4266 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); in pcie_intr_handler()
4267 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); in pcie_intr_handler()
4273 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); in pcie_intr_handler()
4284 { 0x3fffffff, "TP parity error" }, in tp_intr_handler()
4286 { 0 } in tp_intr_handler()
4292 .fatal = 0x7fffffff, in tp_intr_handler()
4298 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); in tp_intr_handler()
4310 .fatal = 0xffffffff, in sge_intr_handler()
4319 .fatal = 0xffffffff, in sge_intr_handler()
4333 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, in sge_intr_handler()
4335 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
4340 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
4356 { 0x0000000f, "SGE context access for invalid queue" }, in sge_intr_handler()
4357 { 0 } in sge_intr_handler()
4368 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, in sge_intr_handler()
4370 "SGE GTS with timer 0-5 for IQID > 1023" }, in sge_intr_handler()
4375 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, in sge_intr_handler()
4392 { 0x0000000f, "SGE context access for invalid queue" }, in sge_intr_handler()
4393 { 0 } in sge_intr_handler()
4400 .flags = 0, in sge_intr_handler()
4408 .fatal = 0, in sge_intr_handler()
4409 .flags = 0, in sge_intr_handler()
4417 .fatal = 0xffffffff, in sge_intr_handler()
4426 .fatal = 0, in sge_intr_handler()
4427 .flags = 0, in sge_intr_handler()
4442 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); in sge_intr_handler()
4443 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); in sge_intr_handler()
4444 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); in sge_intr_handler()
4445 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); in sge_intr_handler()
4447 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); in sge_intr_handler()
4449 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); in sge_intr_handler()
4504 { 0} in cim_intr_handler()
4510 .fatal = 0x007fffe6, in cim_intr_handler()
4555 {0} in cim_intr_handler()
4561 .fatal = 0x3fffeeff, in cim_intr_handler()
4570 .fatal = 0, in cim_intr_handler()
4571 .flags = 0, in cim_intr_handler()
4592 fatal = (fw_err & F_PCIE_FW_ERR) != 0; in cim_intr_handler()
4593 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); in cim_intr_handler()
4594 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); in cim_intr_handler()
4595 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); in cim_intr_handler()
4610 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, in ulprx_intr_handler()
4614 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, in ulprx_intr_handler()
4615 { 0x007fffff, "ULPRX parity error" }, in ulprx_intr_handler()
4616 { 0 } in ulprx_intr_handler()
4622 .fatal = 0x07ffffff, in ulprx_intr_handler()
4631 .fatal = 0, in ulprx_intr_handler()
4632 .flags = 0, in ulprx_intr_handler()
4638 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); in ulprx_intr_handler()
4639 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); in ulprx_intr_handler()
4653 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, in ulptx_intr_handler()
4654 { 0x0fffffff, "ULPTX parity error" }, in ulptx_intr_handler()
4655 { 0 } in ulptx_intr_handler()
4661 .fatal = 0x0fffffff, in ulptx_intr_handler()
4670 .fatal = 0xf0, in ulptx_intr_handler()
4677 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); in ulptx_intr_handler()
4678 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); in ulptx_intr_handler()
4688 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], in pmtx_dump_dbg_stats()
4690 for (i = 0; i < ARRAY_SIZE(data); i++) { in pmtx_dump_dbg_stats()
4691 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, in pmtx_dump_dbg_stats()
4704 { 0xffffffff, 0, pmtx_dump_dbg_stats }, in pmtx_intr_handler()
4705 { 0 }, in pmtx_intr_handler()
4708 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, in pmtx_intr_handler()
4711 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, in pmtx_intr_handler()
4712 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, in pmtx_intr_handler()
4713 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, in pmtx_intr_handler()
4714 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, in pmtx_intr_handler()
4715 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, in pmtx_intr_handler()
4716 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, in pmtx_intr_handler()
4717 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, in pmtx_intr_handler()
4722 { 0 } in pmtx_intr_handler()
4728 .fatal = 0xffffffff, in pmtx_intr_handler()
4729 .flags = 0, in pmtx_intr_handler()
4734 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); in pmtx_intr_handler()
4744 { 0x18000000, "PMRX ospi overflow" }, in pmrx_intr_handler()
4751 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, in pmrx_intr_handler()
4752 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, in pmrx_intr_handler()
4753 { 0x0003c000, "PMRX iespi Rx framing error" }, in pmrx_intr_handler()
4754 { 0x00003c00, "PMRX iespi Tx framing error" }, in pmrx_intr_handler()
4755 { 0x00000300, "PMRX ocspi Rx framing error" }, in pmrx_intr_handler()
4756 { 0x000000c0, "PMRX ocspi Tx framing error" }, in pmrx_intr_handler()
4757 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, in pmrx_intr_handler()
4762 { 0 } in pmrx_intr_handler()
4768 .fatal = 0x1fffffff, in pmrx_intr_handler()
4774 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); in pmrx_intr_handler()
4794 { 0 } in cplsw_intr_handler()
4800 .fatal = 0xff, in cplsw_intr_handler()
4806 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); in cplsw_intr_handler()
4830 { F_LIP0, "LE 0 LIP error" }, in le_intr_handler()
4831 { 0 } in le_intr_handler()
4849 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, in le_intr_handler()
4852 { 0 } in le_intr_handler()
4858 .fatal = 0, in le_intr_handler()
4872 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); in le_intr_handler()
4881 { 0xffffffff, "MPS Rx parity error" }, in mps_intr_handler()
4882 { 0 } in mps_intr_handler()
4888 .fatal = 0xffffffff, in mps_intr_handler()
4902 { 0 } in mps_intr_handler()
4908 .fatal = 0x1ffff, in mps_intr_handler()
4917 { 0 } in mps_intr_handler()
4924 .flags = 0, in mps_intr_handler()
4929 { 0xffffffff, "MPS statistics SRAM parity error" }, in mps_intr_handler()
4930 { 0 } in mps_intr_handler()
4936 .fatal = 0x1fffffff, in mps_intr_handler()
4942 { 0xffffff, "MPS statistics Tx FIFO parity error" }, in mps_intr_handler()
4943 { 0 } in mps_intr_handler()
4949 .fatal = 0xffffff, in mps_intr_handler()
4955 { 0xffffff, "MPS statistics Rx FIFO parity error" }, in mps_intr_handler()
4956 { 0 } in mps_intr_handler()
4962 .fatal = 0xffffff, in mps_intr_handler()
4963 .flags = 0, in mps_intr_handler()
4971 { 0 } in mps_intr_handler()
4978 .flags = 0, in mps_intr_handler()
4983 { 0xff, "MPS statistics SRAM1 parity error" }, in mps_intr_handler()
4984 { 0 } in mps_intr_handler()
4990 .fatal = 0xff, in mps_intr_handler()
4991 .flags = 0, in mps_intr_handler()
4999 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); in mps_intr_handler()
5000 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); in mps_intr_handler()
5001 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); in mps_intr_handler()
5002 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); in mps_intr_handler()
5003 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); in mps_intr_handler()
5004 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); in mps_intr_handler()
5005 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); in mps_intr_handler()
5007 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, in mps_intr_handler()
5011 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); in mps_intr_handler()
5029 { 0 } in mem_intr_handler()
5034 .flags = 0, in mem_intr_handler()
5042 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); in mem_intr_handler()
5043 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); in mem_intr_handler()
5044 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); in mem_intr_handler()
5072 fatal = t4_handle_intr(adap, &ii, 0, verbose); in mem_intr_handler()
5075 if (v != 0) { in mem_intr_handler()
5076 if (G_ECC_UECNT(v) != 0) { in mem_intr_handler()
5081 if (G_ECC_CECNT(v) != 0) { in mem_intr_handler()
5088 t4_write_reg(adap, count_reg, 0xffffffff); in mem_intr_handler()
5114 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, in ma_intr_handler()
5115 { 0 }, in ma_intr_handler()
5130 .fatal = 0xffffffff, in ma_intr_handler()
5131 .flags = 0, in ma_intr_handler()
5139 .fatal = 0xffffffff, in ma_intr_handler()
5140 .flags = 0, in ma_intr_handler()
5147 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); in ma_intr_handler()
5148 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); in ma_intr_handler()
5150 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); in ma_intr_handler()
5164 { 0 } in smb_intr_handler()
5171 .flags = 0, in smb_intr_handler()
5176 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); in smb_intr_handler()
5189 { 0 } in ncsi_intr_handler()
5197 .flags = 0, in ncsi_intr_handler()
5202 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); in ncsi_intr_handler()
5213 { 0 } in mac_intr_handler()
5221 ii.name = &name[0]; in mac_intr_handler()
5225 ii.flags = 0; in mac_intr_handler()
5230 ii.name = &name[0]; in mac_intr_handler()
5234 ii.flags = 0; in mac_intr_handler()
5238 fatal |= t4_handle_intr(adap, &ii, 0, verbose); in mac_intr_handler()
5242 ii.name = &name[0]; in mac_intr_handler()
5245 ii.fatal = 0; in mac_intr_handler()
5246 ii.flags = 0; in mac_intr_handler()
5249 fatal |= t4_handle_intr(adap, &ii, 0, verbose); in mac_intr_handler()
5254 ii.name = &name[0]; in mac_intr_handler()
5257 ii.fatal = 0; in mac_intr_handler()
5258 ii.flags = 0; in mac_intr_handler()
5261 fatal |= t4_handle_intr(adap, &ii, 0, verbose); in mac_intr_handler()
5270 CH_ALERT(adap, " PL_TIMEOUT_STATUS 0x%08x 0x%08x\n", in pl_timeout_status()
5280 { F_TIMEOUT, 0, pl_timeout_status }, in plpl_intr_handler()
5281 { 0 }, in plpl_intr_handler()
5290 { 0 } in plpl_intr_handler()
5302 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); in plpl_intr_handler()
5347 { 0 } in t4_slow_intr_handler()
5353 .fatal = 0xffffffff, in t4_slow_intr_handler()
5354 .flags = 0, in t4_slow_intr_handler()
5376 { F_MAC0, 0, mac_intr_handler}, in t4_slow_intr_handler()
5382 { 0 } in t4_slow_intr_handler()
5388 .fatal = 0, in t4_slow_intr_handler()
5389 .flags = 0, in t4_slow_intr_handler()
5396 if (verbose || perr != 0) { in t4_slow_intr_handler()
5398 if (perr != 0) in t4_slow_intr_handler()
5424 u32 val = 0; in t4_intr_enable()
5438 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); in t4_intr_enable()
5439 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); in t4_intr_enable()
5453 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); in t4_intr_disable()
5454 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); in t4_intr_disable()
5466 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; in hash_mac_addr()
5471 return a & 0x3f; in hash_mac_addr()
5499 memset(&cmd, 0, sizeof(cmd)); in t4_config_rss_range()
5511 while (n > 0) { in t4_config_rss_range()
5513 int nq_packed = 0; in t4_config_rss_range()
5534 while (nq > 0) { in t4_config_rss_range()
5546 qbuf[0] = qbuf[1] = qbuf[2] = 0; in t4_config_rss_range()
5554 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | in t4_config_rss_range()
5567 return 0; in t4_config_rss_range()
5584 memset(&c, 0, sizeof(c)); in t4_config_glbl_rss()
5618 memset(&c, 0, sizeof(c)); in t4_config_vi_rss()
5635 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); in rd_rss_row()
5637 5, 0, val); in rd_rss_row()
5653 for (i = 0; i < rss_nentries / 2; ++i) { in t4_read_rss()
5660 return 0; in t4_read_rss()
5670 * @rw: Read (1) or Write (0)
5679 int ret = 0; in t4_tp_fw_ldst_rw()
5683 for (i = 0; i < nregs; i++) { in t4_tp_fw_ldst_rw()
5684 memset(&c, 0, sizeof(c)); in t4_tp_fw_ldst_rw()
5693 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); in t4_tp_fw_ldst_rw()
5702 return 0; in t4_tp_fw_ldst_rw()
5713 * @rw: READ(1) or WRITE(0)
5787 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); in t4_tp_pio_write()
5845 * 0..15 the corresponding entry in the RSS key table is written,
5865 if (idx >= 0 && idx < rss_key_addr_cnt) { in t4_write_rss_key()
6212 st->octets_ddp = ((u64)val[0] << 32) | val[1]; in t4_get_fcoe_stats()
6230 st->frames = val[0]; in t4_get_usm_stats()
6263 for (i = 0; i < NMTUS; ++i) { in t4_read_mtu_tbl()
6265 V_MTUINDEX(0xff) | V_MTUVALUE(i)); in t4_read_mtu_tbl()
6285 for (mtu = 0; mtu < NMTUS; ++mtu) in t4_read_cong_tbl()
6286 for (w = 0; w < NCCTRL_WIN; ++w) { in t4_read_cong_tbl()
6288 V_ROWINDEX(0xffff) | (mtu << 5) | w); in t4_read_cong_tbl()
6290 A_TP_CCTRL_TABLE) & 0x1fff; in t4_read_cong_tbl()
6320 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; in init_cong_ctrl()
6345 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; in init_cong_ctrl()
6381 for (i = 0; i < NMTUS; ++i) { in t4_load_mtus()
6390 for (w = 0; w < NCCTRL_WIN; ++w) { in t4_load_mtus()
6421 for (i = 0; i < n; i++, pace_vals++) { in t4_set_pace_tbl()
6423 if (vals[i] > 0x7ff) in t4_set_pace_tbl()
6425 if (*pace_vals && vals[i] == 0) in t4_set_pace_tbl()
6428 for (i = 0; i < n; i++, start++) in t4_set_pace_tbl()
6430 return 0; in t4_set_pace_tbl()
6443 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; in t4_set_sched_bps()
6445 unsigned int selected_cpt = 0, selected_bpt = 0; in t4_set_sched_bps()
6447 if (kbps > 0) { in t4_set_sched_bps()
6452 if (bpt > 0 && bpt <= 255) { in t4_set_sched_bps()
6470 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); in t4_set_sched_bps()
6472 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); in t4_set_sched_bps()
6474 return 0; in t4_set_sched_bps()
6503 return 0; in t4_set_sched_ipg()
6537 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); in t4_get_chan_txrate()
6545 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); in t4_get_chan_txrate()
6571 if (idx < 0 || idx >= NTRACE) in t4_set_trace_filter()
6576 enable ? en : 0); in t4_set_trace_filter()
6577 return 0; in t4_set_trace_filter()
6613 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); in t4_set_trace_filter()
6619 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { in t4_set_trace_filter()
6632 return 0; in t4_set_trace_filter()
6672 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { in t4_get_trace_filter()
6691 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmtx_get_stats()
6700 cycles[i] = (((u64)data[0] << 32) | data[1]); in t4_pmtx_get_stats()
6718 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { in t4_pmrx_get_stats()
6727 cycles[i] = (((u64)data[0] << 32) | data[1]); in t4_pmrx_get_stats()
6746 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); in t4_get_mps_bg_map()
6749 MPASS(n > 0 && n <= MAX_NPORTS); in t4_get_mps_bg_map()
6751 return idx == 0 ? 0xf : 0; in t4_get_mps_bg_map()
6753 return idx < 2 ? (3 << (2 * idx)) : 0; in t4_get_mps_bg_map()
6766 return idx == 0 ? all_chan : 0; in t4_get_rx_e_chan_map()
6768 return idx < 2 ? (3 << (2 * idx)) : 0; in t4_get_rx_e_chan_map()
6778 return (adap->params.tp_ch_map >> (8 * idx)) & 0xff; in t4_get_rx_c_chan()
6779 return 0; in t4_get_rx_c_chan()
6843 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; in t4_get_port_stats_offset()
6940 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6941 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6942 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6943 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; in t4_get_port_stats()
6944 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6945 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6946 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6947 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; in t4_get_port_stats()
6988 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6989 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6990 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6991 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; in t4_get_lb_stats()
6992 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6993 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6994 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
6995 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; in t4_get_lb_stats()
7030 (addr[0] << 8) | addr[1]); in t4_wol_magic_enable()
7041 * @mask0: byte mask for bytes 0-63 of a packet
7063 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); in t4_wol_pat_enable()
7064 return 0; in t4_wol_pat_enable()
7066 if (map > 0xff) in t4_wol_pat_enable()
7077 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { in t4_wol_pat_enable()
7097 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); in t4_wol_pat_enable()
7098 return 0; in t4_wol_pat_enable()
7111 memset(wr, 0, sizeof(*wr)); in t4_mk_filtdelwr()
7115 V_FW_FILTER_WR_NOREPLY(qid < 0)); in t4_mk_filtdelwr()
7117 if (qid >= 0) in t4_mk_filtdelwr()
7127 } while (0)
7135 memset(&c, 0, sizeof(c)); in t4_fwaddrspace_write()
7153 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7166 memset(&c, 0, sizeof(c)); in t4_mdio_rd()
7177 if (ret == 0) in t4_mdio_rd()
7187 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
7199 memset(&c, 0, sizeof(c)); in t4_mdio_wr()
7365 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) in t4_sge_decode_idma_state()
7384 memset(&c, 0, sizeof(c)); in t4_sge_ctxt_flush()
7419 memset(&c, 0, sizeof(c)); in t4_fw_hello()
7439 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) in t4_fw_hello()
7466 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && in t4_fw_hello()
7491 if (waiting <= 0) { in t4_fw_hello()
7492 if (retries-- > 0) in t4_fw_hello()
7537 memset(&c, 0, sizeof(c)); in t4_fw_bye()
7554 memset(&c, 0, sizeof(c)); in t4_fw_reset()
7578 int ret = 0; in t4_fw_halt()
7587 memset(&c, 0, sizeof(c)); in t4_fw_halt()
7607 if (ret == 0 || force) { in t4_fw_halt()
7632 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); in t4_fw_restart()
7633 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { in t4_fw_restart()
7677 if (ret < 0 && !force) in t4_fw_upgrade()
7682 if (ret < 0 || bootstrap) in t4_fw_upgrade()
7700 memset(&c, 0, sizeof(c)); in t4_fw_initialize()
7725 __be32 *p = &c.param[0].mnem; in t4_query_params_rw()
7730 memset(&c, 0, sizeof(c)); in t4_query_params_rw()
7737 for (i = 0; i < nparams; i++) { in t4_query_params_rw()
7752 * ~0UL.) in t4_query_params_rw()
7754 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) in t4_query_params_rw()
7764 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); in t4_query_params()
7787 __be32 *p = &c.param[0].mnem; in t4_set_params_timeout()
7792 memset(&c, 0, sizeof(c)); in t4_set_params_timeout()
7857 memset(&c, 0, sizeof(c)); in t4_cfg_pfvf()
7905 memset(&c, 0, sizeof(c)); in t4_alloc_vi_func()
7971 vfvld, vin, FW_VI_FUNC_ETH, 0); in t4_alloc_vi()
7989 memset(&c, 0, sizeof(c)); in t4_free_vi()
8007 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
8008 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
8009 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
8010 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
8022 if (mtu < 0) in t4_set_rxmode()
8024 if (promisc < 0) in t4_set_rxmode()
8026 if (all_multi < 0) in t4_set_rxmode()
8028 if (bcast < 0) in t4_set_rxmode()
8030 if (vlanex < 0) in t4_set_rxmode()
8033 memset(&c, 0, sizeof(c)); in t4_set_rxmode()
8056 * @lookup_type: MAC address for inner (1) or outer (0) header
8070 int ret = 0; in t4_alloc_encap_mac_filt()
8073 memset(&c, 0, sizeof(c)); in t4_alloc_encap_mac_filt()
8091 if (ret == 0) in t4_alloc_encap_mac_filt()
8104 * @lookup_type: MAC address for inner (1) or outer (0) header
8115 int ret = 0; in t4_alloc_raw_mac_filt()
8120 memset(&c, 0, sizeof(c)); in t4_alloc_raw_mac_filt()
8131 /* Lookup Type. Outer header: 0, Inner header: 1 */ in t4_alloc_raw_mac_filt()
8139 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
8140 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_alloc_raw_mac_filt()
8143 if (ret == 0) { in t4_alloc_raw_mac_filt()
8168 * could not be allocated for an address its index is set to 0xffff.
8178 int offset, ret = 0; in t4_alloc_mac_filt()
8180 unsigned int nfilters = 0; in t4_alloc_mac_filt()
8187 for (offset = 0; offset < naddr ; /**/) { in t4_alloc_mac_filt()
8196 memset(&c, 0, sizeof(c)); in t4_alloc_mac_filt()
8205 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { in t4_alloc_mac_filt()
8221 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { in t4_alloc_mac_filt()
8227 ? 0xffff in t4_alloc_mac_filt()
8240 if (ret == 0 || ret == -FW_ENOMEM) in t4_alloc_mac_filt()
8261 u8 addr[] = {0,0,0,0,0,0}; in t4_free_encap_mac_filt()
8262 int ret = 0; in t4_free_encap_mac_filt()
8265 memset(&c, 0, sizeof(c)); in t4_free_encap_mac_filt()
8269 V_FW_CMD_EXEC(0) | in t4_free_encap_mac_filt()
8272 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | in t4_free_encap_mac_filt()
8291 * @lookup_type: MAC address for inner (1) or outer (0) header
8307 memset(&c, 0, sizeof(c)); in t4_free_raw_mac_filt()
8310 V_FW_CMD_EXEC(0) | in t4_free_raw_mac_filt()
8313 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | in t4_free_raw_mac_filt()
8320 /* Lookup Type. Outer header: 0, Inner header: 1 */ in t4_free_raw_mac_filt()
8328 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
8329 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); in t4_free_raw_mac_filt()
8351 int offset, ret = 0; in t4_free_mac_filt()
8353 unsigned int nfilters = 0; in t4_free_mac_filt()
8360 for (offset = 0; offset < (int)naddr ; /**/) { in t4_free_mac_filt()
8369 memset(&c, 0, sizeof(c)); in t4_free_mac_filt()
8373 V_FW_CMD_EXEC(0) | in t4_free_mac_filt()
8376 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | in t4_free_mac_filt()
8379 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { in t4_free_mac_filt()
8390 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { in t4_free_mac_filt()
8402 if (ret == 0) in t4_free_mac_filt()
8418 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
8437 if (idx < 0) /* new allocation */ in t4_change_mac()
8441 memset(&c, 0, sizeof(c)); in t4_change_mac()
8452 if (ret == 0) { in t4_change_mac()
8487 memset(&c, 0, sizeof(c)); in t4_set_addr_hash()
8503 * @rx_en: 1=enable Rx, 0=disable Rx
8504 * @tx_en: 1=enable Tx, 0=disable Tx
8515 memset(&c, 0, sizeof(c)); in t4_enable_vi_params()
8531 * @rx_en: 1=enable Rx, 0=disable Rx
8532 * @tx_en: 1=enable Tx, 0=disable Tx
8540 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); in t4_enable_vi()
8557 memset(&c, 0, sizeof(c)); in t4_identify_port()
8574 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8575 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8587 memset(&c, 0, sizeof(c)); in t4_iq_stop()
8607 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8608 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8618 memset(&c, 0, sizeof(c)); in t4_iq_free()
8646 memset(&c, 0, sizeof(c)); in t4_eth_eq_stop()
8671 memset(&c, 0, sizeof(c)); in t4_eth_eq_free()
8696 memset(&c, 0, sizeof(c)); in t4_ctrl_eq_free()
8721 memset(&c, 0, sizeof(c)); in t4_ofld_eq_free()
8765 } while (0) in fwcap_to_speed()
8779 return 0; in fwcap_to_speed()
8791 } while (0) in speed_to_fwcap()
8805 return 0; in speed_to_fwcap()
8817 } while (0) in fwcap_top_speed()
8831 return 0; in fwcap_top_speed()
8843 uint32_t linkattr = 0; in lstatus_to_fwcap()
8897 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; in handle_port_info()
8912 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; in handle_port_info()
8917 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); in handle_port_info()
8924 fc = 0; in handle_port_info()
8964 memset(&cmd, 0, sizeof(cmd)); in t4_update_port_info()
8977 return 0; in t4_update_port_info()
9023 return 0; in t4_handle_fw_rpl()
9060 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ in t4_get_flash_params()
9064 u32 flashid = 0; in t4_get_flash_params()
9066 unsigned int density, size = 0; in t4_get_flash_params()
9075 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); in t4_get_flash_params()
9077 ret = sf1_read(adapter, 3, 0, 1, &flashid); in t4_get_flash_params()
9078 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ in t4_get_flash_params()
9079 if (ret < 0) in t4_get_flash_params()
9085 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) in t4_get_flash_params()
9103 manufacturer = flashid & 0xff; in t4_get_flash_params()
9105 case 0x20: /* Micron/Numonix */ in t4_get_flash_params()
9110 density = (flashid >> 16) & 0xff; in t4_get_flash_params()
9112 case 0x14: size = 1 << 20; break; /* 1MB */ in t4_get_flash_params()
9113 case 0x15: size = 1 << 21; break; /* 2MB */ in t4_get_flash_params()
9114 case 0x16: size = 1 << 22; break; /* 4MB */ in t4_get_flash_params()
9115 case 0x17: size = 1 << 23; break; /* 8MB */ in t4_get_flash_params()
9116 case 0x18: size = 1 << 24; break; /* 16MB */ in t4_get_flash_params()
9117 case 0x19: size = 1 << 25; break; /* 32MB */ in t4_get_flash_params()
9118 case 0x20: size = 1 << 26; break; /* 64MB */ in t4_get_flash_params()
9119 case 0x21: size = 1 << 27; break; /* 128MB */ in t4_get_flash_params()
9120 case 0x22: size = 1 << 28; break; /* 256MB */ in t4_get_flash_params()
9124 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ in t4_get_flash_params()
9129 density = (flashid >> 16) & 0xff; in t4_get_flash_params()
9131 case 0x16: size = 1 << 25; break; /* 32MB */ in t4_get_flash_params()
9132 case 0x17: size = 1 << 26; break; /* 64MB */ in t4_get_flash_params()
9136 case 0xc2: /* Macronix */ in t4_get_flash_params()
9141 density = (flashid >> 16) & 0xff; in t4_get_flash_params()
9143 case 0x17: size = 1 << 23; break; /* 8MB */ in t4_get_flash_params()
9144 case 0x18: size = 1 << 24; break; /* 16MB */ in t4_get_flash_params()
9148 case 0xef: /* Winbond */ in t4_get_flash_params()
9153 density = (flashid >> 16) & 0xff; in t4_get_flash_params()
9155 case 0x17: size = 1 << 23; break; /* 8MB */ in t4_get_flash_params()
9156 case 0x18: size = 1 << 24; break; /* 16MB */ in t4_get_flash_params()
9167 if (size == 0) { in t4_get_flash_params()
9188 return 0; in t4_get_flash_params()
9200 val &= 0xfff0; in set_pcie_completion_timeout()
9249 .sge_fl_db = 0, in t4_get_chip_params()
9257 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) in t4_get_chip_params()
9283 if (adapter->params.chipid == 0) { in t4_prep_adapter()
9302 if (ret < 0) in t4_prep_adapter()
9316 if (ret < 0) in t4_prep_adapter()
9329 set_pcie_completion_timeout(adapter, 0xd); in t4_prep_adapter()
9330 return 0; in t4_prep_adapter()
9348 const bool bt = adapter->bt_map != 0; in t4_shutdown_adapter()
9352 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000); in t4_shutdown_adapter()
9371 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); in t4_shutdown_adapter()
9373 return 0; in t4_shutdown_adapter()
9383 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9395 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9397 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9399 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9443 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply in t4_bar2_sge_qregs()
9460 bar2_qid = 0; in t4_bar2_sge_qregs()
9465 return 0; in t4_bar2_sge_qregs()
9500 return 0; in t4_init_devlog_params()
9506 memset(dparams, 0, sizeof *dparams); in t4_init_devlog_params()
9517 memset(&devlog_cmd, 0, sizeof devlog_cmd); in t4_init_devlog_params()
9532 return 0; in t4_init_devlog_params()
9548 sp->counter_val[0] = G_THRESHOLD_0(r); in t4_init_sge_params()
9556 if (tscale == 0) in t4_init_sge_params()
9563 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; in t4_init_sge_params()
9613 if (G_INGPACKBOUNDARY(r) == 0) in t4_init_sge_params()
9618 for (i = 0; i < SGE_FLBUF_SIZES; i++) in t4_init_sge_params()
9622 return 0; in t4_init_sge_params()
9634 filter_mask = 0; in hashmask_to_filtermask()
9636 if ((filter_mode & (1 << i)) == 0) in hashmask_to_filtermask()
9658 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | in read_filter_mode_and_ingress_config()
9664 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); in read_filter_mode_and_ingress_config()
9665 if (rc == 0) { in read_filter_mode_and_ingress_config()
9666 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); in read_filter_mode_and_ingress_config()
9667 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); in read_filter_mode_and_ingress_config()
9675 tpp->filter_mode = v & 0xffff; in read_filter_mode_and_ingress_config()
9677 hash_mask = 0; in read_filter_mode_and_ingress_config()
9749 return 0; in t4_init_tp_params()
9767 if ((filter_mode & filter_sel) == 0) in t4_filter_field_shift()
9770 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { in t4_filter_field_shift()
9813 struct vi_info *vi = &p->vi[0]; in t4_port_init()
9815 for (i = 0, j = -1; i <= p->port_id; i++) { in t4_port_init()
9818 } while ((adap->params.portvec & (1 << j)) == 0); in t4_port_init()
9834 if (ret < 0) in t4_port_init()
9845 vi->rss_base = 0xffff; in t4_port_init()
9848 vi->rss_base = val & 0xffff; in t4_port_init()
9851 return 0; in t4_port_init()
9869 for (i = 0; i < CIM_NUM_IBQ; i++) { in t4_read_cimq_cfg()
9878 for (i = 0; i < cim_num_obq; i++) { in t4_read_cimq_cfg()
9895 * Reads the contents of the selected CIM queue starting at address 0 up
9896 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9917 for (i = 0; i < n; i++, addr++) { in t4_read_cim_ibq()
9920 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, in t4_read_cim_ibq()
9926 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); in t4_read_cim_ibq()
9937 * Reads the contents of the selected CIM queue starting at address 0 up
9938 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9959 for (i = 0; i < n; i++, addr++) { in t4_read_cim_obq()
9962 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, in t4_read_cim_obq()
9968 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); in t4_read_cim_obq()
9973 CIM_QCTL_BASE = 0,
9974 CIM_CTL_BASE = 0x2000,
9975 CIM_PBT_ADDR_BASE = 0x2800,
9976 CIM_PBT_LRF_BASE = 0x3000,
9977 CIM_PBT_DATA_BASE = 0x3800
9992 int ret = 0; in t4_cim_read()
10000 0, 5, 2); in t4_cim_read()
10019 int ret = 0; in t4_cim_write()
10028 0, 5, 2); in t4_cim_write()
10074 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); in t4_cim_read_la()
10087 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
10103 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to in t4_cim_read_la()
10106 if (is_t6(adap) && (idx & 0xf) >= 9) in t4_cim_read_la()
10107 idx = (idx & 0xff0) + 0x10; in t4_cim_read_la()
10110 /* address can't exceed 0xfff */ in t4_cim_read_la()
10138 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; in t4_tp_read_la()
10145 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; in t4_tp_read_la()
10151 val &= 0xffff; in t4_tp_read_la()
10155 for (i = 0; i < TPLA_SIZE; i++) { in t4_tp_read_la()
10163 la_buf[TPLA_SIZE - 1] = ~0ULL; in t4_tp_read_la()
10204 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; in t4_idma_monitor_init()
10224 * 0xffffffff without wrapping around so once they pass the 1s in t4_idma_monitor()
10228 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); in t4_idma_monitor()
10231 for (i = 0; i < 2; i++) { in t4_idma_monitor()
10246 idma->idma_stalled[i] = 0; in t4_idma_monitor()
10259 if (idma->idma_stalled[i] == 0) { in t4_idma_monitor()
10261 idma->idma_warn[i] = 0; in t4_idma_monitor()
10272 if (idma->idma_warn[i] > 0) in t4_idma_monitor()
10280 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); in t4_idma_monitor()
10282 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; in t4_idma_monitor()
10286 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; in t4_idma_monitor()
10310 memset(&cmd, 0, sizeof(cmd)); in t4_set_vf_mac()
10331 case 0: in t4_set_vf_mac()
10350 for (i = 0; i < NTX_SCHED; i++) { in t4_read_pace_tbl()
10351 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); in t4_read_pace_tbl()
10376 bpt = (v >> 8) & 0xff; in t4_get_tx_sched()
10377 cpt = v & 0xff; in t4_get_tx_sched()
10379 *kbps = 0; /* scheduler disabled */ in t4_get_tx_sched()
10390 v &= 0xffff; in t4_get_tx_sched()
10411 if (cfg_addr < 0) in t4_load_cfg()
10428 * If size == 0 then we're simply erasing the FLASH sectors associated in t4_load_cfg()
10431 if (ret || size == 0) in t4_load_cfg()
10435 for (i = 0; i< size; i+= SF_PAGE_SIZE) { in t4_load_cfg()
10451 (size == 0 ? "clear" : "download"), ret); in t4_load_cfg()
10467 return 0; in t5_fw_init_extern_mem()
10469 val[0] = 0xff; /* Initialize all MCs */ in t5_fw_init_extern_mem()
10470 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | in t5_fw_init_extern_mem()
10472 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, in t5_fw_init_extern_mem()
10480 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10487 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */
10497 u8 signature[2]; // ROM signature. The value 0xaa55
10499 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10505 * 0x0: uncompressed
10506 * 0x1: Compressed
10507 * 0x2-0xFFFF: Reserved
10528 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10529 * 0x01: Open Firmware standard for PCI. FCODE
10530 * 0x02: Hewlett-Packard PA RISC. HP reserved
10531 * 0x03: EFI Image. EFI
10532 * 0x04-0xFF: Reserved.
10540 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10541 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */
10545 VENDOR_ID = 0x1425, /* Vendor ID */
10546 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10560 u32 cur_header = 0; in modify_device_id()
10572 * 0x00: Okay to modify in modify_device_id()
10573 * 0x01: FCODE. Do not be modify in modify_device_id()
10574 * 0x03: Okay to modify in modify_device_id()
10575 * 0x04-0xFF: Do not modify in modify_device_id()
10577 if (pcir_header->code_type == 0x00) { in modify_device_id()
10578 u8 csum = 0; in modify_device_id()
10587 * Set checksum temporarily to 0. in modify_device_id()
10590 header->cksum = 0x0; in modify_device_id()
10595 for (i = 0; i < (header->size512 * 512); i++) in modify_device_id()
10604 } else if (pcir_header->code_type == 0x03) { in modify_device_id()
10618 if (pcir_header->indicator & 0x80) in modify_device_id()
10662 * sectors 0 to 7 in flash and live right before the FW image location. in t4_load_boot()
10670 * If size == 0 then we're simply erasing the FLASH sectors associated in t4_load_boot()
10673 if (ret || (size == 0)) in t4_load_boot()
10722 /* Want to deal with PF 0 so I strip off PF 4 indicator */ in t4_load_boot()
10723 device_id = device_id & 0xf0ff; in t4_load_boot()
10746 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); in t4_load_boot()
10752 (const u8 *)header, 0); in t4_load_boot()
10788 if (cfg_addr < 0) in t4_load_bootcfg()
10806 * If size == 0 then we're simply erasing the FLASH sectors associated in t4_load_bootcfg()
10809 if (ret || size == 0) in t4_load_bootcfg()
10813 for (i = 0; i< size; i+= SF_PAGE_SIZE) { in t4_load_bootcfg()
10818 ret = t4_write_flash(adap, addr, n, cfg_data, 0); in t4_load_bootcfg()
10829 (size == 0 ? "clear" : "download"), ret); in t4_load_bootcfg()
10841 * enable in filter tuples. Returns 0 on success and a negative error if
10856 nbits = 0; in t4_set_filter_cfg()
10863 "mode (0x%x) add up to %d bits " in t4_set_filter_cfg()
10887 "filter mask will be changed from 0x%x to " in t4_set_filter_cfg()
10888 "0x%x to comply with the filter mode (0x%x).\n", in t4_set_filter_cfg()
10896 "filter mask (0x%x) must be a subset of " in t4_set_filter_cfg()
10897 "the filter mode (0x%x).\n", fmask, fmode); in t4_set_filter_cfg()
10907 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
10909 if (rc < 0) in t4_set_filter_cfg()
10918 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, in t4_set_filter_cfg()
10920 if (rc < 0) in t4_set_filter_cfg()
10927 return 0; in t4_set_filter_cfg()
10950 t4_write_reg(adap, port_base_addr + i, 0); in t4_clr_port_stats()
10953 t4_write_reg(adap, port_base_addr + i, 0); in t4_clr_port_stats()
10954 for (i = 0; i < 4; i++) in t4_clr_port_stats()
10957 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); in t4_clr_port_stats()
10959 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); in t4_clr_port_stats()
10966 * @port: Port number if per-port device; <0 if not
10982 int ret = 0; in t4_i2c_io()
10991 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); in t4_i2c_io()
10998 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); in t4_i2c_io()
11001 while (len > 0) { in t4_i2c_io()
11066 memset(&c, 0, sizeof(c)); in t4_sge_ctxt_rd()
11074 if (ret == 0) { in t4_sge_ctxt_rd()
11075 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); in t4_sge_ctxt_rd()
11101 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); in t4_sge_ctxt_rd_bd()
11113 memset(&cmd, 0, sizeof(cmd)); in t4_sched_config()
11134 memset(&cmd, 0, sizeof(cmd)); in t4_sched_params()
11163 memset(&cmd, 0, sizeof(cmd)); in t4_sched_params_ch_rl()
11185 if (weight < 0 || weight > 100) in t4_sched_params_cl_wrr()
11188 memset(&cmd, 0, sizeof(cmd)); in t4_sched_params_cl_wrr()
11210 memset(&cmd, 0, sizeof(cmd)); in t4_sched_params_cl_rl_kbps()
11254 * "tick" if the timeout is non-zero but the conversion results in 0 in t4_config_watchdog()
11261 memset(&wdog, 0, sizeof wdog); in t4_config_watchdog()
11279 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); in t4_get_devlog_level()
11289 return 0; in t4_get_devlog_level()
11296 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); in t4_set_devlog_level()
11309 int ret = 0; in t4_configure_add_smac()
11311 adap->params.smac_add_support = 0; in t4_configure_add_smac()
11320 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_add_smac()
11325 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, in t4_configure_add_smac()
11340 int ret = 0; in t4_configure_ringbb()
11349 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
11350 if (ret < 0) { in t4_configure_ringbb()
11361 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); in t4_configure_ringbb()
11362 if (ret < 0) { in t4_configure_ringbb()
11386 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); in t4_set_vlan_acl()
11387 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); in t4_set_vlan_acl()
11400 : 0); in t4_set_vlan_acl()
11401 if (enable != 0) { in t4_set_vlan_acl()
11403 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); in t4_set_vlan_acl()
11418 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
11432 memset(&c, 0, sizeof(c)); in t4_del_mac()
11438 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); in t4_del_mac()
11446 if (ret == 0) { in t4_del_mac()
11467 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
11481 if (idx < 0) /* new allocation */ in t4_add_mac()
11485 memset(&c, 0, sizeof(c)); in t4_add_mac()
11491 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); in t4_add_mac()
11498 if (ret == 0) { in t4_add_mac()