Lines Matching +full:idma +full:- +full:addr
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
75 FEC_RS = 1 << 0, /* Reed-Solomon */
76 FEC_BASER_RS = 1 << 1, /* BASE-R, aka Firecode */
159 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
160 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
161 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
162 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
163 u64 rx_trunc0; /* buffer-group 0 truncated packets */
164 u64 rx_trunc1; /* buffer-group 1 truncated packets */
165 u64 rx_trunc2; /* buffer-group 2 truncated packets */
166 u64 rx_trunc3; /* buffer-group 3 truncated packets */
332 unsigned int tc; /* PCI-E traffic class */
353 u32 addr; /* start address in flat addr space */
375 /* VF-only parameters. */
378 * Global Receive Side Scaling (RSS) parameters in host-native format.
385 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
386 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
387 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
388 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
406 unsigned int tc; /* PCI-E traffic class */
415 struct tp_params tp; /* PF-only */
417 struct pf_resources pfres; /* PF-only */
419 struct devlog_params devlog; /* PF-only */
420 struct rss_params rss; /* VF-only */
421 struct vf_resources vfres; /* VF-only */
488 unsigned int idma_state[2]; /* IDMA Hang detect state */
489 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
505 /* OS-specific code owns all the requested_* fields. */
532 for (iter = 0; iter < (adapter)->params.nports; ++iter)
537 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base &&
538 tid <= sc->tids.ftid_end);
544 return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base &&
545 tid <= sc->tids.hpftid_end);
551 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base &&
552 tid <= sc->tids.etid_end);
557 return adap->params.offload;
562 return adap->params.ethoffload;
567 return adap->params.hash_filter;
572 return adap->cryptocaps & FW_CAPS_CONFIG_TLS_HW ||
573 adap->params.chipid == CHELSIO_T7;
578 return adap->params.chipid;
583 return adap->params.rev;
588 return adap->params.chipid == CHELSIO_T4;
593 return adap->params.chipid == CHELSIO_T5;
598 return adap->params.chipid == CHELSIO_T6;
603 return adap->params.chipid == CHELSIO_T7;
608 return adap->params.fpga;
613 return adap->params.vpd.cclk / 1000;
619 return (us * adap->params.vpd.cclk) / 1000;
626 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
627 adapter->params.vpd.cclk);
633 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
639 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre);
644 return ((uint64_t)ticks << adap->params.tp.tre) /
648 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
691 int t4_hash_mac_addr(const u8 *addr);
695 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
696 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
699 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
701 int t4_write_flash(struct adapter *adapter, unsigned int addr,
770 unsigned int addr, unsigned int n,
773 unsigned int addr, unsigned int n,
799 static inline int t4_cim_read(struct adapter *adap, unsigned int addr,
802 return t4_cim_read_core(adap, 0, 0, addr, n, valp);
805 static inline int t4_cim_write(struct adapter *adap, unsigned int addr,
808 return t4_cim_write_core(adap, 0, 0, addr, n, valp);
819 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
821 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
822 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
825 struct sge_idma_monitor_state *idma);
827 struct sge_idma_monitor_state *idma,
830 unsigned int naddr, u8 *addr);
849 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
883 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
929 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
933 const u8 **addr, bool sleep_ok);
937 const u8 *addr, const u8 *mask, unsigned int idx,
940 const u8 *addr, const u8 *mask, unsigned int idx,
943 const u8 *addr, const u8 *mask, unsigned int vni,
947 int idx, const u8 *addr, bool persist, uint16_t *smt_idx);
949 const u8 *addr, bool smac);
951 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac);
998 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
1051 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
1061 unsigned int *naddr, u8 *addr);
1074 /* Mbps -> Gbps */
1075 return (fwcap_to_speed(pi->link_cfg.pcaps) / 1000);
1093 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
1095 ulpmc->len = htobe32(howmany(LEN__SET_TCB_FIELD_ULP, 16));
1098 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM));
1099 ulpsc->len = htobe32(sizeof(*req));
1104 if (qid == -1) {
1105 req->reply_ctrl = htobe16(F_NO_REPLY);
1106 req->word_cookie = htobe16(V_WORD(word) | V_COOKIE(0));
1109 req->reply_ctrl = htobe16(V_T7_QUEUENO(qid) |
1112 req->reply_ctrl = htobe16(V_QUEUENO(qid) |
1115 req->word_cookie = htobe16(V_WORD(word) |
1118 req->mask = htobe64(mask);
1119 req->val = htobe64(val);
1124 * boundary so it needs to be padded with a no-op.
1128 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
1129 ulpsc->len = htobe32(0);
1138 return (mk_set_tcb_field_ulp_with_rpl(sc, cur, tid, word, mask, val, -1));