Lines Matching defs:adapter_params
359 struct adapter_params { struct
360 struct sge_params sge;
361 struct tp_params tp; /* PF-only */
362 struct vpd_params vpd;
363 struct pci_params pci;
364 struct devlog_params devlog; /* PF-only */
365 struct rss_params rss; /* VF-only */
366 struct vf_resources vfres; /* VF-only */
367 unsigned int core_vdd;
369 unsigned int sf_size; /* serial flash size in bytes */
370 unsigned int sf_nsec; /* # of flash sectors */
372 unsigned int fw_vers; /* firmware version */
373 unsigned int bs_vers; /* bootstrap version */
374 unsigned int tp_vers; /* TP microcode version */
375 unsigned int er_vers; /* expansion ROM version */
376 unsigned int scfg_vers; /* Serial Configuration version */
377 unsigned int vpd_vers; /* VPD version */
379 unsigned short mtus[NMTUS];
380 unsigned short a_wnd[NCCTRL_WIN];
381 unsigned short b_wnd[NCCTRL_WIN];
383 unsigned int cim_la_size;
385 uint8_t nports; /* # of ethernet ports */
386 uint8_t portvec;
387 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
388 unsigned int rev:4; /* chip revision */
389 unsigned int fpga:1; /* this is an FPGA */
390 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
392 unsigned int bypass:1; /* this is a bypass card */
393 unsigned int ethoffload:1;
394 unsigned int hash_filter:1;
395 unsigned int filter2_wr_support:1;
396 unsigned int port_caps32:1;
397 unsigned int smac_add_support:1;
399 unsigned int ofldq_wr_cred;
400 unsigned int eo_wr_cred;
402 unsigned int max_ordird_qp;
403 unsigned int max_ird_adapter;
406 uint32_t mps_bg_map; /* MPS rx buffer group map */
407 uint32_t tp_ch_map; /* TPCHMAP from firmware */
409 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
410 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
411 bool dev_512sgl_mr; /* FW support for 512 SGL per FR MR */
412 bool viid_smt_extn_support; /* FW returns vin, vfvld & smt index? */
413 unsigned int max_pkts_per_eth_tx_pkts_wr;
414 uint8_t nsched_cls; /* # of usable sched classes per port */