Lines Matching +full:0 +full:x60200
35 ELMR_ADDR = 0,
40 ELMR_THRES0 = 0xe000,
41 ELMR_BW = 0xe00c,
42 ELMR_FIFO_SZ = 0xe00d,
43 ELMR_STATS = 0xf000,
57 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); in t3_elmr_blk_write()
59 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, in t3_elmr_blk_write()
60 *vals & 0xffff); in t3_elmr_blk_write()
62 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, in t3_elmr_blk_write()
82 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); in t3_elmr_blk_read()
86 for (i = 0; i < 5; i++) { in t3_elmr_blk_read()
87 ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v); in t3_elmr_blk_read()
100 ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, vals); in t3_elmr_blk_read()
102 ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, in t3_elmr_blk_read()
114 { VSC_REG(7, 15, 0xf), 2 }, in t3_vsc7323_init()
115 { VSC_REG(7, 15, 0x19), 0xd6 }, in t3_vsc7323_init()
116 { VSC_REG(7, 15, 7), 0xc }, in t3_vsc7323_init()
117 { VSC_REG(7, 1, 0), 0x220 }, in t3_vsc7323_init()
120 { VSC_REG(2, 0, 0x2f), 0 }, in t3_vsc7323_init()
121 { VSC_REG(2, 0, 0xf), 0xa0010291 }, in t3_vsc7323_init()
122 { VSC_REG(2, 1, 0x2f), 1 }, in t3_vsc7323_init()
123 { VSC_REG(2, 1, 0xf), 0xa026301 } in t3_vsc7323_init()
126 { VSC_REG(1, 10, 0), 0x600b }, in t3_vsc7323_init()
127 { VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512 in t3_vsc7323_init()
128 { VSC_REG(1, 10, 2), 0x2710 }, in t3_vsc7323_init()
129 { VSC_REG(1, 10, 5), 0x65 }, in t3_vsc7323_init()
130 { VSC_REG(1, 10, 7), 0x23 }, in t3_vsc7323_init()
131 { VSC_REG(1, 10, 0x23), 0x800007bf }, in t3_vsc7323_init()
132 { VSC_REG(1, 10, 0x23), 0x000007bf }, in t3_vsc7323_init()
133 { VSC_REG(1, 10, 0x23), 0x800007bf }, in t3_vsc7323_init()
134 { VSC_REG(1, 10, 0x24), 4 } in t3_vsc7323_init()
139 for (i = 0; i < ARRAY_SIZE(sys_avp); i++) in t3_vsc7323_init()
144 ing_step = 0xc0 / nports; in t3_vsc7323_init()
145 egr_step = 0x40 / nports; in t3_vsc7323_init()
146 ing_bot = egr_bot = 0; in t3_vsc7323_init()
151 for (i = 0; i < nports; i++) { in t3_vsc7323_init()
153 (ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i), in t3_vsc7323_init()
155 (ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i), in t3_vsc7323_init()
156 0x6000bc0)) || in t3_vsc7323_init()
157 (ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) || in t3_vsc7323_init()
158 (ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i), in t3_vsc7323_init()
160 (ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i), in t3_vsc7323_init()
161 0x2000280)) || in t3_vsc7323_init()
162 (ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0))) in t3_vsc7323_init()
168 for (i = 0; i < ARRAY_SIZE(fifo_avp); i++) in t3_vsc7323_init()
173 for (i = 0; i < ARRAY_SIZE(xg_avp); i++) in t3_vsc7323_init()
178 for (i = 0; i < nports; i++) in t3_vsc7323_init()
179 if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) || in t3_vsc7323_init()
181 (i << 12) | 0x63)) || in t3_vsc7323_init()
182 (ret = elmr_write(adap, VSC_REG(1, i, 0xb), 0x96)) || in t3_vsc7323_init()
183 (ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)) || in t3_vsc7323_init()
197 if (speed >= 0) { in t3_vsc7323_set_speed_fc()
207 if ((r = elmr_write(adap, VSC_REG(1, port, 0), in t3_vsc7323_set_speed_fc()
208 0xa590 | (mode << 2))) || in t3_vsc7323_set_speed_fc()
209 (r = elmr_write(adap, VSC_REG(1, port, 0xb), in t3_vsc7323_set_speed_fc()
210 0x91 | (clk << 1))) || in t3_vsc7323_set_speed_fc()
211 (r = elmr_write(adap, VSC_REG(1, port, 0xb), in t3_vsc7323_set_speed_fc()
212 0x90 | (clk << 1))) || in t3_vsc7323_set_speed_fc()
213 (r = elmr_write(adap, VSC_REG(1, port, 0), in t3_vsc7323_set_speed_fc()
214 0xa593 | (mode << 2)))) in t3_vsc7323_set_speed_fc()
218 r = (fc & PAUSE_RX) ? 0x60200 : 0x20200; //QUANTA = 32*1024*8/512 in t3_vsc7323_set_speed_fc()
234 (addr[0] << 16) | (addr[1] << 8) | addr[2]); in t3_vsc7323_set_addr()
246 ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1); in t3_vsc7323_enable()
254 ret = elmr_write(adap, VSC_REG(1, port, 0), v); in t3_vsc7323_enable()
264 ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1); in t3_vsc7323_disable()
272 ret = elmr_write(adap, VSC_REG(1, port, 0), v); in t3_vsc7323_disable()
278 #define STATS1_START 0x24
279 #define NSTATS0 (0x1d - STATS0_START + 1)
280 #define NSTATS1 (0x2a - STATS1_START + 1)
282 #define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg)
342 RMON_UPDATE(mac, tx_underrun, 0); in t3_vsc7323_update_stats()