Lines Matching refs:mc7
141 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, in t3_mc7_bd_read() argument
147 unsigned int size64 = mc7->size / 8; /* # of 64-bit words */ in t3_mc7_bd_read()
148 adapter_t *adap = mc7->adapter; in t3_mc7_bd_read()
153 start *= (8 << mc7->width); in t3_mc7_bd_read()
158 for (i = (1 << mc7->width) - 1; i >= 0; --i) { in t3_mc7_bd_read()
162 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, in t3_mc7_bd_read()
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); in t3_mc7_bd_read()
165 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
168 mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
172 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); in t3_mc7_bd_read()
173 if (mc7->width == 0) { in t3_mc7_bd_read()
175 mc7->offset + A_MC7_BD_DATA0); in t3_mc7_bd_read()
178 if (mc7->width > 1) in t3_mc7_bd_read()
179 val >>= shift[mc7->width]; in t3_mc7_bd_read()
180 val64 |= (u64)val << (step[mc7->width] * i); in t3_mc7_bd_read()
2098 static void mc7_intr_handler(struct mc7 *mc7) in mc7_intr_handler() argument
2100 adapter_t *adapter = mc7->adapter; in mc7_intr_handler()
2101 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); in mc7_intr_handler()
2104 mc7->stats.corr_err++; in mc7_intr_handler()
2106 "data 0x%x 0x%x 0x%x\n", mc7->name, in mc7_intr_handler()
2107 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), in mc7_intr_handler()
2108 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), in mc7_intr_handler()
2109 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), in mc7_intr_handler()
2110 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); in mc7_intr_handler()
2114 mc7->stats.uncorr_err++; in mc7_intr_handler()
2116 "data 0x%x 0x%x 0x%x\n", mc7->name, in mc7_intr_handler()
2117 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), in mc7_intr_handler()
2118 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), in mc7_intr_handler()
2119 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), in mc7_intr_handler()
2120 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); in mc7_intr_handler()
2124 mc7->stats.parity_err++; in mc7_intr_handler()
2126 mc7->name, G_PE(cause)); in mc7_intr_handler()
2134 mc7->offset + A_MC7_ERR_ADDR); in mc7_intr_handler()
2135 mc7->stats.addr_err++; in mc7_intr_handler()
2137 mc7->name, addr); in mc7_intr_handler()
2143 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
3950 static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type) in mc7_init() argument
3965 adapter_t *adapter = mc7->adapter; in mc7_init()
3968 if (!mc7->size) in mc7_init()
3971 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_init()
3976 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3977 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3981 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3982 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL); in mc7_init()
3984 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & in mc7_init()
3987 mc7->name); in mc7_init()
3992 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3998 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
4000 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
4003 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, in mc7_init()
4008 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4009 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || in mc7_init()
4010 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || in mc7_init()
4011 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4015 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
4016 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, in mc7_init()
4021 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4022 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4023 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4024 wrreg_wait(adapter, mc7->offset + A_MC7_MODE, in mc7_init()
4026 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || in mc7_init()
4027 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4034 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
4036 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ in mc7_init()
4038 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, in mc7_init()
4040 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
4041 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
4042 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
4043 (mc7->size << width) - 1); in mc7_init()
4044 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
4045 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ in mc7_init()
4050 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); in mc7_init()
4053 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); in mc7_init()
4058 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); in mc7_init()
4303 static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7, in mc7_prep() argument
4308 mc7->adapter = adapter; in mc7_prep()
4309 mc7->name = name; in mc7_prep()
4310 mc7->offset = base_addr - MC7_PMRX_BASE_ADDR; in mc7_prep()
4311 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_prep()
4312 mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg); in mc7_prep()
4313 mc7->width = G_WIDTH(cfg); in mc7_prep()