Lines Matching full:adapter
39 * @adapter: the adapter performing the operation
52 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, in t3_wait_op_done_val() argument
56 u32 val = t3_read_reg(adapter, reg); in t3_wait_op_done_val()
72 * @adapter: the adapter to program
81 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, in t3_write_regs() argument
85 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
92 * @adapter: the adapter to program
100 void t3_set_reg_field(adapter_t *adapter, unsigned int addr, u32 mask, u32 val) in t3_set_reg_field() argument
102 u32 v = t3_read_reg(adapter, addr) & ~mask; in t3_set_reg_field()
104 t3_write_reg(adapter, addr, v | val); in t3_set_reg_field()
105 (void) t3_read_reg(adapter, addr); /* flush */ in t3_set_reg_field()
110 * @adap: the adapter
148 adapter_t *adap = mc7->adapter; in t3_mc7_bd_read()
205 int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp) in t3_i2c_read8() argument
209 MDIO_LOCK(adapter); in t3_i2c_read8()
210 t3_write_reg(adapter, A_I2C_OP, in t3_i2c_read8()
212 ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0, in t3_i2c_read8()
216 *valp = G_I2C_DATA(t3_read_reg(adapter, A_I2C_DATA)); in t3_i2c_read8()
218 MDIO_UNLOCK(adapter); in t3_i2c_read8()
229 int t3_i2c_write8(adapter_t *adapter, int chained, u8 val) in t3_i2c_write8() argument
233 MDIO_LOCK(adapter); in t3_i2c_write8()
234 t3_write_reg(adapter, A_I2C_DATA, V_I2C_DATA(val)); in t3_i2c_write8()
235 t3_write_reg(adapter, A_I2C_OP, in t3_i2c_write8()
237 ret = t3_wait_op_done_val(adapter, A_I2C_OP, F_I2C_BUSY, 0, in t3_i2c_write8()
241 MDIO_UNLOCK(adapter); in t3_i2c_write8()
261 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, in t3_mi1_read() argument
270 MDIO_LOCK(adapter); in t3_mi1_read()
271 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_read()
272 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_read()
273 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2)); in t3_mi1_read()
274 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_read()
276 *valp = t3_read_reg(adapter, A_MI1_DATA); in t3_mi1_read()
277 MDIO_UNLOCK(adapter); in t3_mi1_read()
281 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, in t3_mi1_write() argument
290 MDIO_LOCK(adapter); in t3_mi1_write()
291 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1)); in t3_mi1_write()
292 t3_write_reg(adapter, A_MI1_ADDR, addr); in t3_mi1_write()
293 t3_write_reg(adapter, A_MI1_DATA, val); in t3_mi1_write()
294 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in t3_mi1_write()
295 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in t3_mi1_write()
296 MDIO_UNLOCK(adapter); in t3_mi1_write()
308 static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_ext_read() argument
314 MDIO_LOCK(adapter); in mi1_ext_read()
315 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); in mi1_ext_read()
316 t3_write_reg(adapter, A_MI1_ADDR, addr); in mi1_ext_read()
317 t3_write_reg(adapter, A_MI1_DATA, reg_addr); in mi1_ext_read()
318 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); in mi1_ext_read()
319 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in mi1_ext_read()
321 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3)); in mi1_ext_read()
322 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_read()
325 *valp = t3_read_reg(adapter, A_MI1_DATA); in mi1_ext_read()
327 MDIO_UNLOCK(adapter); in mi1_ext_read()
331 static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr, in mi1_ext_write() argument
337 MDIO_LOCK(adapter); in mi1_ext_write()
338 t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0); in mi1_ext_write()
339 t3_write_reg(adapter, A_MI1_ADDR, addr); in mi1_ext_write()
340 t3_write_reg(adapter, A_MI1_DATA, reg_addr); in mi1_ext_write()
341 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0)); in mi1_ext_write()
342 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10); in mi1_ext_write()
344 t3_write_reg(adapter, A_MI1_DATA, val); in mi1_ext_write()
345 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1)); in mi1_ext_write()
346 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, in mi1_ext_write()
349 MDIO_UNLOCK(adapter); in mi1_ext_write()
646 * @adapter: adapter to read
655 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data) in t3_seeprom_read() argument
659 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_read()
664 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr); in t3_seeprom_read()
667 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); in t3_seeprom_read()
671 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); in t3_seeprom_read()
674 t3_os_pci_read_config_4(adapter, base + PCI_VPD_DATA, data); in t3_seeprom_read()
681 * @adapter: adapter to write
688 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data) in t3_seeprom_write() argument
692 unsigned int base = adapter->params.pci.vpd_cap_addr; in t3_seeprom_write()
697 t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA, in t3_seeprom_write()
699 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, in t3_seeprom_write()
703 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val); in t3_seeprom_write()
707 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr); in t3_seeprom_write()
715 * @adapter: the adapter
720 int t3_seeprom_wp(adapter_t *adapter, int enable) in t3_seeprom_wp() argument
722 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); in t3_seeprom_wp()
735 * @adapter: the adapter
741 static int get_desc_len(adapter_t *adapter, u32 offset) in get_desc_len() argument
750 ret = t3_seeprom_read(adapter, read_offset, &tmp); in get_desc_len()
758 ret = t3_seeprom_read(adapter, read_offset + 4, &tmp); in get_desc_len()
773 * @adapter: the adapter
778 static int is_end_tag(adapter_t * adapter, u32 offset) in is_end_tag() argument
786 ret = t3_seeprom_read(adapter, read_offset, &tmp); in is_end_tag()
799 * @adapter: the adapter
805 int t3_get_vpd_len(adapter_t * adapter, struct generic_vpd *vpd) in t3_get_vpd_len() argument
813 ret = is_end_tag(adapter, offset); in t3_get_vpd_len()
819 inc = get_desc_len(adapter, offset); in t3_get_vpd_len()
830 * @adapter: the adapter
837 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd) in t3_read_vpd() argument
842 ret = t3_seeprom_read(adapter, vpd->offset + i, in t3_read_vpd()
854 * @adapter: adapter to read
859 static int get_vpd_params(adapter_t *adapter, struct vpd_params *p) in get_vpd_params() argument
868 ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd); in get_vpd_params()
874 ret = t3_seeprom_read(adapter, addr + i, in get_vpd_params()
889 if (adapter->params.rev == 0 && !vpd.port0_data[0]) { in get_vpd_params()
890 p->port_type[0] = uses_xaui(adapter) ? 1 : 2; in get_vpd_params()
891 p->port_type[1] = uses_xaui(adapter) ? 6 : 2; in get_vpd_params()
946 * @adapter: the adapter
955 static int sf1_read(adapter_t *adapter, unsigned int byte_cnt, int cont, in sf1_read() argument
962 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_read()
964 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); in sf1_read()
965 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_read()
967 *valp = t3_read_reg(adapter, A_SF_DATA); in sf1_read()
973 * @adapter: the adapter
982 static int sf1_write(adapter_t *adapter, unsigned int byte_cnt, int cont, in sf1_write() argument
987 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY) in sf1_write()
989 t3_write_reg(adapter, A_SF_DATA, val); in sf1_write()
990 t3_write_reg(adapter, A_SF_OP, in sf1_write()
992 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10); in sf1_write()
997 * @adapter: the adapter
1003 static int flash_wait_op(adapter_t *adapter, int attempts, int delay) in flash_wait_op() argument
1009 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 || in flash_wait_op()
1010 (ret = sf1_read(adapter, 1, 0, &status)) != 0) in flash_wait_op()
1023 * @adapter: the adapter
1034 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, in t3_read_flash() argument
1044 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 || in t3_read_flash()
1045 (ret = sf1_read(adapter, 1, 1, data)) != 0) in t3_read_flash()
1049 ret = sf1_read(adapter, 4, nwords > 1, data); in t3_read_flash()
1060 * @adapter: the adapter
1072 static int t3_write_flash(adapter_t *adapter, unsigned int addr, in t3_write_flash() argument
1085 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_write_flash()
1086 (ret = sf1_write(adapter, 4, 1, val)) != 0) in t3_write_flash()
1096 ret = sf1_write(adapter, c, c != left, val); in t3_write_flash()
1100 if ((ret = flash_wait_op(adapter, 5, 1)) != 0) in t3_write_flash()
1104 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, in t3_write_flash()
1116 * @adapter: the adapter
1121 int t3_get_tp_version(adapter_t *adapter, u32 *vers) in t3_get_tp_version() argument
1126 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0); in t3_get_tp_version()
1127 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0, in t3_get_tp_version()
1132 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); in t3_get_tp_version()
1139 * @adapter: the adapter
1142 int t3_check_tpsram_version(adapter_t *adapter) in t3_check_tpsram_version() argument
1148 if (adapter->params.rev == T3_REV_A) in t3_check_tpsram_version()
1152 ret = t3_get_tp_version(adapter, &vers); in t3_check_tpsram_version()
1156 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1); in t3_check_tpsram_version()
1164 CH_ERR(adapter, "found wrong TP version (%u.%u), " in t3_check_tpsram_version()
1174 * @adapter: the adapter
1178 * Checks if an adapter's tp sram is compatible with the driver.
1181 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size) in t3_check_tpsram() argument
1191 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n", in t3_check_tpsram()
1206 * @adapter: the adapter
1213 int t3_get_fw_version(adapter_t *adapter, u32 *vers) in t3_get_fw_version() argument
1215 int ret = t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0); in t3_get_fw_version()
1219 return t3_read_flash(adapter, FW_VERS_ADDR_PRE8, 1, vers, 0); in t3_get_fw_version()
1224 * @adapter: the adapter
1226 * Checks if an adapter's FW is compatible with the driver. Returns 0
1229 int t3_check_fw_version(adapter_t *adapter) in t3_check_fw_version() argument
1235 ret = t3_get_fw_version(adapter, &vers); in t3_check_fw_version()
1248 CH_WARN(adapter, "found old FW minor version(%u.%u), " in t3_check_fw_version()
1252 CH_WARN(adapter, "found newer FW version(%u.%u), " in t3_check_fw_version()
1262 * @adapter: the adapter
1268 static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end) in t3_flash_erase_sectors() argument
1273 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 || in t3_flash_erase_sectors()
1274 (ret = sf1_write(adapter, 4, 0, in t3_flash_erase_sectors()
1276 (ret = flash_wait_op(adapter, 5, 500)) != 0) in t3_flash_erase_sectors()
1285 * @adapter: the adapter
1294 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size) in t3_load_fw() argument
1319 CH_ERR(adapter, "corrupted firmware image, checksum %u\n", in t3_load_fw()
1324 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector); in t3_load_fw()
1332 ret = t3_write_flash(adapter, addr, chunk_size, fw_data, 1); in t3_load_fw()
1341 ret = t3_write_flash(adapter, fw_version_addr, 4, fw_data, 1); in t3_load_fw()
1344 CH_ERR(adapter, "firmware download failed, error %d\n", ret); in t3_load_fw()
1350 * @adapter: the adapter
1358 int t3_load_boot(adapter_t *adapter, u8 *boot_data, unsigned int size) in t3_load_boot() argument
1372 CH_ERR(adapter, "boot image too small/large\n"); in t3_load_boot()
1376 CH_ERR(adapter, "boot image missing signature\n"); in t3_load_boot()
1380 CH_ERR(adapter, "boot image header length != image length\n"); in t3_load_boot()
1384 ret = t3_flash_erase_sectors(adapter, boot_sector, boot_end); in t3_load_boot()
1391 ret = t3_write_flash(adapter, addr, chunk_size, boot_data, 0); in t3_load_boot()
1402 CH_ERR(adapter, "boot image download failed, error %d\n", ret); in t3_load_boot()
1410 * @adap: the adapter
1442 *rx_cfg = t3_read_reg(mac->adapter, A_XGM_RX_CFG + mac->offset); in t3_gate_rx_traffic()
1443 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, in t3_gate_rx_traffic()
1447 *rx_hash_high = t3_read_reg(mac->adapter, A_XGM_RX_HASH_HIGH + in t3_gate_rx_traffic()
1449 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, 0); in t3_gate_rx_traffic()
1451 *rx_hash_low = t3_read_reg(mac->adapter, A_XGM_RX_HASH_LOW + in t3_gate_rx_traffic()
1453 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, 0); in t3_gate_rx_traffic()
1463 t3_set_reg_field(mac->adapter, A_XGM_RX_CFG + mac->offset, in t3_open_rx_traffic()
1466 t3_write_reg(mac->adapter, A_XGM_RX_HASH_HIGH + mac->offset, in t3_open_rx_traffic()
1468 t3_write_reg(mac->adapter, A_XGM_RX_HASH_LOW + mac->offset, in t3_open_rx_traffic()
1472 static int t3_detect_link_fault(adapter_t *adapter, int port_id) in t3_detect_link_fault() argument
1474 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_detect_link_fault()
1481 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_detect_link_fault()
1484 (void) t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_detect_link_fault()
1485 t3_xgm_intr_enable(adapter, port_id); in t3_detect_link_fault()
1488 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, F_RXEN); in t3_detect_link_fault()
1491 link_fault = t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_detect_link_fault()
1495 static void t3_clear_faults(adapter_t *adapter, int port_id) in t3_clear_faults() argument
1497 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_clear_faults()
1500 if (adapter->params.nports <= 2) { in t3_clear_faults()
1501 t3_xgm_intr_disable(adapter, pi->port_id); in t3_clear_faults()
1502 t3_read_reg(adapter, A_XGM_INT_STATUS + mac->offset); in t3_clear_faults()
1503 t3_write_reg(adapter, A_XGM_INT_CAUSE + mac->offset, F_XGM_INT); in t3_clear_faults()
1504 t3_set_reg_field(adapter, A_XGM_INT_ENABLE + mac->offset, in t3_clear_faults()
1506 t3_xgm_intr_enable(adapter, pi->port_id); in t3_clear_faults()
1512 * @adapter: the adapter
1519 void t3_link_changed(adapter_t *adapter, int port_id) in t3_link_changed() argument
1522 struct port_info *pi = adap2pinfo(adapter, port_id); in t3_link_changed()
1560 if (adapter->params.nports <= 2 && in t3_link_changed()
1563 link_fault = t3_detect_link_fault(adapter, port_id); in t3_link_changed()
1570 if (uses_xaui(adapter)) { in t3_link_changed()
1571 if (adapter->params.rev >= T3_REV_C) in t3_link_changed()
1583 t3_clear_faults(adapter, port_id); in t3_link_changed()
1602 if (adapter->params.rev > 0 && uses_xaui(adapter)) { in t3_link_changed()
1604 if (adapter->params.rev >= T3_REV_C) in t3_link_changed()
1609 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset, in t3_link_changed()
1614 t3_set_reg_field(adapter, A_XGM_TXFIFO_CFG + mac->offset, in t3_link_changed()
1618 t3_set_reg_field(adapter, A_XGM_STAT_CTRL + mac->offset, in t3_link_changed()
1620 t3_clear_faults(adapter, port_id); in t3_link_changed()
1626 if (adapter->params.rev > 0 && uses_xaui(adapter)) { in t3_link_changed()
1627 t3_write_reg(adapter, in t3_link_changed()
1631 t3_xgm_intr_disable(adapter, pi->port_id); in t3_link_changed()
1632 if (adapter->params.nports <= 2) { in t3_link_changed()
1633 t3_set_reg_field(adapter, in t3_link_changed()
1643 t3_set_reg_field(adapter, in t3_link_changed()
1645 t3_write_reg(adapter, A_XGM_RX_CTRL + mac->offset, 0); in t3_link_changed()
1646 t3_write_reg(adapter, in t3_link_changed()
1648 t3_write_reg(adapter, in t3_link_changed()
1653 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc, in t3_link_changed()
1695 if (!is_10G(phy->adapter)) in t3_link_start()
1709 * @adapter: the adapter
1710 * @ports: bitmap of adapter ports to operate on
1715 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on) in t3_set_vlan_accel() argument
1717 t3_set_reg_field(adapter, A_TP_OUT_CONFIG, in t3_set_vlan_accel()
1731 * @adapter: the adapter that generated the interrupt
1744 static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg, in t3_handle_intr_status() argument
1750 unsigned int status = t3_read_reg(adapter, reg) & mask; in t3_handle_intr_status()
1756 CH_ALERT(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1760 CH_WARN(adapter, "%s (0x%x)\n", in t3_handle_intr_status()
1766 t3_write_reg(adapter, reg, status); in t3_handle_intr_status()
1828 static void pci_intr_handler(adapter_t *adapter) in pci_intr_handler() argument
1856 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK, in pci_intr_handler()
1857 pcix1_intr_info, adapter->irq_stats)) in pci_intr_handler()
1858 t3_fatal_err(adapter); in pci_intr_handler()
1864 static void pcie_intr_handler(adapter_t *adapter) in pcie_intr_handler() argument
1886 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR) in pcie_intr_handler()
1887 CH_ALERT(adapter, "PEX error code 0x%x\n", in pcie_intr_handler()
1888 t3_read_reg(adapter, A_PCIE_PEX_ERR)); in pcie_intr_handler()
1890 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK, in pcie_intr_handler()
1891 pcie_intr_info, adapter->irq_stats)) in pcie_intr_handler()
1892 t3_fatal_err(adapter); in pcie_intr_handler()
1898 static void tp_intr_handler(adapter_t *adapter) in tp_intr_handler() argument
1913 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff, in tp_intr_handler()
1914 adapter->params.rev < T3_REV_C ? in tp_intr_handler()
1916 t3_fatal_err(adapter); in tp_intr_handler()
1922 static void cim_intr_handler(adapter_t *adapter) in cim_intr_handler() argument
1952 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, CIM_INTR_MASK, in cim_intr_handler()
1954 t3_fatal_err(adapter); in cim_intr_handler()
1960 static void ulprx_intr_handler(adapter_t *adapter) in ulprx_intr_handler() argument
1974 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff, in ulprx_intr_handler()
1976 t3_fatal_err(adapter); in ulprx_intr_handler()
1982 static void ulptx_intr_handler(adapter_t *adapter) in ulptx_intr_handler() argument
1993 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff, in ulptx_intr_handler()
1994 ulptx_intr_info, adapter->irq_stats)) in ulptx_intr_handler()
1995 t3_fatal_err(adapter); in ulptx_intr_handler()
2010 static void pmtx_intr_handler(adapter_t *adapter) in pmtx_intr_handler() argument
2023 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff, in pmtx_intr_handler()
2025 t3_fatal_err(adapter); in pmtx_intr_handler()
2040 static void pmrx_intr_handler(adapter_t *adapter) in pmrx_intr_handler() argument
2053 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff, in pmrx_intr_handler()
2055 t3_fatal_err(adapter); in pmrx_intr_handler()
2061 static void cplsw_intr_handler(adapter_t *adapter) in cplsw_intr_handler() argument
2073 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff, in cplsw_intr_handler()
2075 t3_fatal_err(adapter); in cplsw_intr_handler()
2081 static void mps_intr_handler(adapter_t *adapter) in mps_intr_handler() argument
2088 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff, in mps_intr_handler()
2090 t3_fatal_err(adapter); in mps_intr_handler()
2100 adapter_t *adapter = mc7->adapter; in mc7_intr_handler() local
2101 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE); in mc7_intr_handler()
2105 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, " in mc7_intr_handler()
2107 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR), in mc7_intr_handler()
2108 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0), in mc7_intr_handler()
2109 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1), in mc7_intr_handler()
2110 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2)); in mc7_intr_handler()
2115 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, " in mc7_intr_handler()
2117 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR), in mc7_intr_handler()
2118 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0), in mc7_intr_handler()
2119 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1), in mc7_intr_handler()
2120 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2)); in mc7_intr_handler()
2125 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n", in mc7_intr_handler()
2132 if (adapter->params.rev > 0) in mc7_intr_handler()
2133 addr = t3_read_reg(adapter, in mc7_intr_handler()
2136 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n", in mc7_intr_handler()
2141 t3_fatal_err(adapter); in mc7_intr_handler()
2143 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause); in mc7_intr_handler()
2208 static int phy_intr_handler(adapter_t *adapter) in phy_intr_handler() argument
2210 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE); in phy_intr_handler()
2212 for_each_port(adapter, i) { in phy_intr_handler()
2213 struct port_info *p = adap2pinfo(adapter, i); in phy_intr_handler()
2218 if (cause & (1 << adapter_info(adapter)->gpio_intr[i])) { in phy_intr_handler()
2226 t3_os_phymod_changed(adapter, i); in phy_intr_handler()
2228 CH_WARN(adapter, "Operation affected due to " in phy_intr_handler()
2234 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause); in phy_intr_handler()
2240 * @adapter: the adapter
2246 int t3_slow_intr_handler(adapter_t *adapter) in t3_slow_intr_handler() argument
2248 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0); in t3_slow_intr_handler()
2250 cause &= adapter->slow_intr_mask; in t3_slow_intr_handler()
2254 if (is_pcie(adapter)) in t3_slow_intr_handler()
2255 pcie_intr_handler(adapter); in t3_slow_intr_handler()
2257 pci_intr_handler(adapter); in t3_slow_intr_handler()
2260 t3_sge_err_intr_handler(adapter); in t3_slow_intr_handler()
2262 mc7_intr_handler(&adapter->pmrx); in t3_slow_intr_handler()
2264 mc7_intr_handler(&adapter->pmtx); in t3_slow_intr_handler()
2266 mc7_intr_handler(&adapter->cm); in t3_slow_intr_handler()
2268 cim_intr_handler(adapter); in t3_slow_intr_handler()
2270 tp_intr_handler(adapter); in t3_slow_intr_handler()
2272 ulprx_intr_handler(adapter); in t3_slow_intr_handler()
2274 ulptx_intr_handler(adapter); in t3_slow_intr_handler()
2276 pmrx_intr_handler(adapter); in t3_slow_intr_handler()
2278 pmtx_intr_handler(adapter); in t3_slow_intr_handler()
2280 cplsw_intr_handler(adapter); in t3_slow_intr_handler()
2282 mps_intr_handler(adapter); in t3_slow_intr_handler()
2284 t3_mc5_intr_handler(&adapter->mc5); in t3_slow_intr_handler()
2286 mac_intr_handler(adapter, 0); in t3_slow_intr_handler()
2288 mac_intr_handler(adapter, 1); in t3_slow_intr_handler()
2290 phy_intr_handler(adapter); in t3_slow_intr_handler()
2293 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause); in t3_slow_intr_handler()
2294 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_slow_intr_handler()
2311 * @adapter: the adapter whose interrupts should be enabled
2317 void t3_intr_enable(adapter_t *adapter) in t3_intr_enable() argument
2333 adapter->slow_intr_mask = PL_INTR_MASK; in t3_intr_enable()
2335 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0); in t3_intr_enable()
2336 t3_write_reg(adapter, A_TP_INT_ENABLE, in t3_intr_enable()
2337 adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff); in t3_intr_enable()
2338 t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK); in t3_intr_enable()
2340 if (adapter->params.rev > 0) { in t3_intr_enable()
2341 t3_write_reg(adapter, A_CPL_INTR_ENABLE, in t3_intr_enable()
2343 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, in t3_intr_enable()
2347 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK); in t3_intr_enable()
2348 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK); in t3_intr_enable()
2351 t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter)); in t3_intr_enable()
2353 if (is_pcie(adapter)) in t3_intr_enable()
2354 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK); in t3_intr_enable()
2356 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK); in t3_intr_enable()
2357 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask); in t3_intr_enable()
2358 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_enable()
2363 * @adapter: the adapter whose interrupts should be disabled
2368 void t3_intr_disable(adapter_t *adapter) in t3_intr_disable() argument
2370 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0); in t3_intr_disable()
2371 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */ in t3_intr_disable()
2372 adapter->slow_intr_mask = 0; in t3_intr_disable()
2377 * @adapter: the adapter whose interrupts should be cleared
2381 void t3_intr_clear(adapter_t *adapter) in t3_intr_clear() argument
2404 for_each_port(adapter, i) in t3_intr_clear()
2405 t3_port_intr_clear(adapter, i); in t3_intr_clear()
2408 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff); in t3_intr_clear()
2410 if (is_pcie(adapter)) in t3_intr_clear()
2411 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff); in t3_intr_clear()
2412 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff); in t3_intr_clear()
2413 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */ in t3_intr_clear()
2416 void t3_xgm_intr_enable(adapter_t *adapter, int idx) in t3_xgm_intr_enable() argument
2418 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_enable()
2420 t3_write_reg(adapter, A_XGM_XGM_INT_ENABLE + pi->mac.offset, in t3_xgm_intr_enable()
2424 void t3_xgm_intr_disable(adapter_t *adapter, int idx) in t3_xgm_intr_disable() argument
2426 struct port_info *pi = adap2pinfo(adapter, idx); in t3_xgm_intr_disable()
2428 t3_write_reg(adapter, A_XGM_XGM_INT_DISABLE + pi->mac.offset, in t3_xgm_intr_disable()
2434 * @adapter: associated adapter
2438 * adapter port.
2440 void t3_port_intr_enable(adapter_t *adapter, int idx) in t3_port_intr_enable() argument
2442 struct port_info *pi = adap2pinfo(adapter, idx); in t3_port_intr_enable()
2444 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK); in t3_port_intr_enable()
2450 * @adapter: associated adapter
2454 * adapter port.
2456 void t3_port_intr_disable(adapter_t *adapter, int idx) in t3_port_intr_disable() argument
2458 struct port_info *pi = adap2pinfo(adapter, idx); in t3_port_intr_disable()
2460 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0); in t3_port_intr_disable()
2466 * @adapter: associated adapter
2470 * adapter port.
2472 void t3_port_intr_clear(adapter_t *adapter, int idx) in t3_port_intr_clear() argument
2474 struct port_info *pi = adap2pinfo(adapter, idx); in t3_port_intr_clear()
2476 t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff); in t3_port_intr_clear()
2484 * @adapter: the adapter
2491 static int t3_sge_write_context(adapter_t *adapter, unsigned int id, in t3_sge_write_context() argument
2501 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2502 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2503 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0x17ffffff); in t3_sge_write_context()
2504 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2506 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff); in t3_sge_write_context()
2507 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff); in t3_sge_write_context()
2508 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff); in t3_sge_write_context()
2509 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff); in t3_sge_write_context()
2511 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_write_context()
2513 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_write_context()
2519 * @adapter: the adapter
2546 * @adapter: the adapter to configure
2561 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, in t3_sge_init_ecntxt() argument
2570 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_ecntxt()
2574 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) | in t3_sge_init_ecntxt()
2576 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) | in t3_sge_init_ecntxt()
2579 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr); in t3_sge_init_ecntxt()
2581 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_ecntxt()
2585 return t3_sge_write_context(adapter, id, F_EGRESS); in t3_sge_init_ecntxt()
2590 * @adapter: the adapter to configure
2604 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, in t3_sge_init_flcntxt() argument
2610 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_flcntxt()
2614 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr); in t3_sge_init_flcntxt()
2616 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, in t3_sge_init_flcntxt()
2619 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) | in t3_sge_init_flcntxt()
2622 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, in t3_sge_init_flcntxt()
2625 return t3_sge_write_context(adapter, id, F_FREELIST); in t3_sge_init_flcntxt()
2630 * @adapter: the adapter to configure
2643 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, in t3_sge_init_rspcntxt() argument
2651 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_rspcntxt()
2655 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) | in t3_sge_init_rspcntxt()
2657 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); in t3_sge_init_rspcntxt()
2659 ctrl = t3_read_reg(adapter, A_SG_CONTROL); in t3_sge_init_rspcntxt()
2665 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_rspcntxt()
2667 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres); in t3_sge_init_rspcntxt()
2668 return t3_sge_write_context(adapter, id, F_RESPONSEQ); in t3_sge_init_rspcntxt()
2673 * @adapter: the adapter to configure
2686 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, in t3_sge_init_cqcntxt() argument
2692 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_init_cqcntxt()
2696 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size)); in t3_sge_init_cqcntxt()
2697 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr); in t3_sge_init_cqcntxt()
2699 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, in t3_sge_init_cqcntxt()
2703 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) | in t3_sge_init_cqcntxt()
2705 return t3_sge_write_context(adapter, id, F_CQ); in t3_sge_init_cqcntxt()
2710 * @adapter: the adapter
2717 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable) in t3_sge_enable_ecntxt() argument
2719 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_enable_ecntxt()
2722 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_enable_ecntxt()
2723 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_enable_ecntxt()
2724 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_enable_ecntxt()
2725 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID); in t3_sge_enable_ecntxt()
2726 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable)); in t3_sge_enable_ecntxt()
2727 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_enable_ecntxt()
2729 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_enable_ecntxt()
2735 * @adapter: the adapter
2741 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id) in t3_sge_disable_fl() argument
2743 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_fl()
2746 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0); in t3_sge_disable_fl()
2747 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_fl()
2748 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE)); in t3_sge_disable_fl()
2749 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_fl()
2750 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0); in t3_sge_disable_fl()
2751 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_fl()
2753 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_fl()
2759 * @adapter: the adapter
2765 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id) in t3_sge_disable_rspcntxt() argument
2767 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_rspcntxt()
2770 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_rspcntxt()
2771 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_rspcntxt()
2772 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_rspcntxt()
2773 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_rspcntxt()
2774 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_rspcntxt()
2775 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_rspcntxt()
2777 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_rspcntxt()
2783 * @adapter: the adapter
2789 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id) in t3_sge_disable_cqcntxt() argument
2791 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_disable_cqcntxt()
2794 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE)); in t3_sge_disable_cqcntxt()
2795 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0); in t3_sge_disable_cqcntxt()
2796 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0); in t3_sge_disable_cqcntxt()
2797 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0); in t3_sge_disable_cqcntxt()
2798 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0); in t3_sge_disable_cqcntxt()
2799 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_disable_cqcntxt()
2801 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_disable_cqcntxt()
2807 * @adapter: the adapter
2819 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, in t3_sge_cqcntxt_op() argument
2824 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_cqcntxt_op()
2827 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16); in t3_sge_cqcntxt_op()
2828 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) | in t3_sge_cqcntxt_op()
2830 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, in t3_sge_cqcntxt_op()
2835 if (adapter->params.rev > 0) in t3_sge_cqcntxt_op()
2838 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2840 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, in t3_sge_cqcntxt_op()
2844 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0)); in t3_sge_cqcntxt_op()
2852 * @adapter: the adapter
2859 static int t3_sge_read_context(unsigned int type, adapter_t *adapter, in t3_sge_read_context() argument
2862 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY) in t3_sge_read_context()
2865 t3_write_reg(adapter, A_SG_CONTEXT_CMD, in t3_sge_read_context()
2867 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0, in t3_sge_read_context()
2870 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0); in t3_sge_read_context()
2871 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1); in t3_sge_read_context()
2872 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2); in t3_sge_read_context()
2873 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3); in t3_sge_read_context()
2879 * @adapter: the adapter
2886 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]) in t3_sge_read_ecntxt() argument
2890 return t3_sge_read_context(F_EGRESS, adapter, id, data); in t3_sge_read_ecntxt()
2895 * @adapter: the adapter
2902 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]) in t3_sge_read_cq() argument
2906 return t3_sge_read_context(F_CQ, adapter, id, data); in t3_sge_read_cq()
2911 * @adapter: the adapter
2918 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]) in t3_sge_read_fl() argument
2922 return t3_sge_read_context(F_FREELIST, adapter, id, data); in t3_sge_read_fl()
2927 * @adapter: the adapter
2934 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]) in t3_sge_read_rspq() argument
2938 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data); in t3_sge_read_rspq()
2943 * @adapter: the adapter
2953 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, in t3_config_rss() argument
2967 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val); in t3_config_rss()
2972 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, in t3_config_rss()
2978 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config); in t3_config_rss()
2983 * @adapter: the adapter
2989 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map) in t3_read_rss() argument
2996 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, in t3_read_rss()
2998 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE); in t3_read_rss()
3007 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE, in t3_read_rss()
3009 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE); in t3_read_rss()
3019 * @adap: the adapter
3033 * @adap: the adapter
3050 * @adap: the adapter
3064 * @adap: the adapter
3100 * @adap: the adapter
3248 * @adap: the adapter to set
3293 * @adap: the adapter
3323 * @adap: the adapter
3409 * @adap: the adapter
3453 * @adap: the adapter
3473 * @adap: the adapter
3495 * @adap: the adapter
3508 * @adap: the adapter
3525 * @adap: the adapter
3570 * @adapter: the adapter
3596 * @adapter: the adapter
3604 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, in t3_config_trace_filter() argument
3625 tp_wr_indirect(adapter, addr++, key[0]); in t3_config_trace_filter()
3626 tp_wr_indirect(adapter, addr++, mask[0]); in t3_config_trace_filter()
3627 tp_wr_indirect(adapter, addr++, key[1]); in t3_config_trace_filter()
3628 tp_wr_indirect(adapter, addr++, mask[1]); in t3_config_trace_filter()
3629 tp_wr_indirect(adapter, addr++, key[2]); in t3_config_trace_filter()
3630 tp_wr_indirect(adapter, addr++, mask[2]); in t3_config_trace_filter()
3631 tp_wr_indirect(adapter, addr++, key[3]); in t3_config_trace_filter()
3632 tp_wr_indirect(adapter, addr, mask[3]); in t3_config_trace_filter()
3633 (void) t3_read_reg(adapter, A_TP_PIO_DATA); in t3_config_trace_filter()
3638 * @adapter: the adapter
3646 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, in t3_query_trace_filter() argument
3652 key[0] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3653 mask[0] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3654 key[1] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3655 mask[1] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3656 key[2] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3657 mask[2] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3658 key[3] = tp_rd_indirect(adapter, addr++); in t3_query_trace_filter()
3659 mask[3] = tp_rd_indirect(adapter, addr); in t3_query_trace_filter()
3683 * @adap: the adapter
3727 * @adap: the adapter
3756 * @adap: the adapter
3796 * @adap: the adapter
3824 * @adap: the adapter
3840 * @adap: the adapter
3883 static int calibrate_xgm(adapter_t *adapter) in calibrate_xgm() argument
3885 if (uses_xaui(adapter)) { in calibrate_xgm()
3889 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0); in calibrate_xgm()
3890 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3892 v = t3_read_reg(adapter, A_XGM_XAUI_IMP); in calibrate_xgm()
3894 t3_write_reg(adapter, A_XGM_XAUI_IMP, in calibrate_xgm()
3899 CH_ERR(adapter, "MAC calibration failed\n"); in calibrate_xgm()
3902 t3_write_reg(adapter, A_XGM_RGMII_IMP, in calibrate_xgm()
3904 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm()
3910 static void calibrate_xgm_t3b(adapter_t *adapter) in calibrate_xgm_t3b() argument
3912 if (!uses_xaui(adapter)) { in calibrate_xgm_t3b()
3913 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET | in calibrate_xgm_t3b()
3915 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0); in calibrate_xgm_t3b()
3916 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, in calibrate_xgm_t3b()
3918 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE, in calibrate_xgm_t3b()
3920 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0); in calibrate_xgm_t3b()
3921 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE); in calibrate_xgm_t3b()
3940 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val) in wrreg_wait() argument
3942 t3_write_reg(adapter, addr, val); in wrreg_wait()
3943 (void) t3_read_reg(adapter, addr); /* flush */ in wrreg_wait()
3944 if (!(t3_read_reg(adapter, addr) & F_BUSY)) in wrreg_wait()
3946 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr); in wrreg_wait()
3965 adapter_t *adapter = mc7->adapter; in mc7_init() local
3971 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_init()
3976 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN); in mc7_init()
3977 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
3981 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN); in mc7_init()
3982 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL); in mc7_init()
3984 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) & in mc7_init()
3986 CH_ERR(adapter, "%s MC7 calibration timed out\n", in mc7_init()
3992 t3_write_reg(adapter, mc7->offset + A_MC7_PARM, in mc7_init()
3998 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, in mc7_init()
4000 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */ in mc7_init()
4003 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB, in mc7_init()
4008 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4009 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) || in mc7_init()
4010 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) || in mc7_init()
4011 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4015 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100); in mc7_init()
4016 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, in mc7_init()
4021 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) || in mc7_init()
4022 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4023 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) || in mc7_init()
4024 wrreg_wait(adapter, mc7->offset + A_MC7_MODE, in mc7_init()
4026 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) || in mc7_init()
4027 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val)) in mc7_init()
4034 t3_write_reg(adapter, mc7->offset + A_MC7_REF, in mc7_init()
4036 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */ in mc7_init()
4038 t3_write_reg(adapter, mc7->offset + A_MC7_ECC, in mc7_init()
4040 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0); in mc7_init()
4041 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0); in mc7_init()
4042 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END, in mc7_init()
4044 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1)); in mc7_init()
4045 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */ in mc7_init()
4050 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); in mc7_init()
4053 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name); in mc7_init()
4058 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY); in mc7_init()
4090 * Gen2 adapter pcie bridge compatibility requires minimum in config_pcie()
4133 * @adapter: the adapter
4144 int t3_init_hw(adapter_t *adapter, u32 fw_params) in t3_init_hw() argument
4147 const struct vpd_params *vpd = &adapter->params.vpd; in t3_init_hw()
4149 if (adapter->params.rev > 0) in t3_init_hw()
4150 calibrate_xgm_t3b(adapter); in t3_init_hw()
4151 else if (calibrate_xgm(adapter)) in t3_init_hw()
4154 if (adapter->params.nports > 2) in t3_init_hw()
4155 t3_mac_init(&adap2pinfo(adapter, 0)->mac); in t3_init_hw()
4158 partition_mem(adapter, &adapter->params.tp); in t3_init_hw()
4160 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4161 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4162 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) || in t3_init_hw()
4163 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers, in t3_init_hw()
4164 adapter->params.mc5.nfilters, in t3_init_hw()
4165 adapter->params.mc5.nroutes)) in t3_init_hw()
4169 if (clear_sge_ctxt(adapter, i, F_CQ)) in t3_init_hw()
4173 if (tp_init(adapter, &adapter->params.tp)) in t3_init_hw()
4176 t3_tp_set_coalescing_size(adapter, in t3_init_hw()
4177 min(adapter->params.sge.max_pkt_size, in t3_init_hw()
4179 t3_tp_set_max_rxsize(adapter, in t3_init_hw()
4180 min(adapter->params.sge.max_pkt_size, 16384U)); in t3_init_hw()
4181 ulp_config(adapter, &adapter->params.tp); in t3_init_hw()
4182 if (is_pcie(adapter)) in t3_init_hw()
4183 config_pcie(adapter); in t3_init_hw()
4185 t3_set_reg_field(adapter, A_PCIX_CFG, 0, in t3_init_hw()
4188 if (adapter->params.rev == T3_REV_C) in t3_init_hw()
4189 t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0, in t3_init_hw()
4192 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff); in t3_init_hw()
4193 t3_write_reg(adapter, A_PM1_RX_MODE, 0); in t3_init_hw()
4194 t3_write_reg(adapter, A_PM1_TX_MODE, 0); in t3_init_hw()
4195 chan_init_hw(adapter, adapter->params.chan_map); in t3_init_hw()
4196 t3_sge_init(adapter, &adapter->params.sge); in t3_init_hw()
4197 t3_set_reg_field(adapter, A_PL_RST, 0, F_FATALPERREN); in t3_init_hw()
4199 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW, calc_gpio_intr(adapter)); in t3_init_hw()
4201 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
4202 t3_write_reg(adapter, A_CIM_BOOT_CFG, in t3_init_hw()
4204 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */ in t3_init_hw()
4209 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts); in t3_init_hw()
4211 CH_ERR(adapter, "uP initialization timed out\n"); in t3_init_hw()
4222 * @adapter: the adapter
4228 static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p) in get_pci_mode() argument
4233 pcie_cap = t3_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); in get_pci_mode()
4239 t3_os_pci_read_config_2(adapter, pcie_cap + PCI_EXP_LNKSTA, in get_pci_mode()
4245 pci_mode = t3_read_reg(adapter, A_PCIX_MODE); in get_pci_mode()
4303 static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7, in mc7_prep() argument
4308 mc7->adapter = adapter; in mc7_prep()
4311 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); in mc7_prep()
4316 void mac_prep(struct cmac *mac, adapter_t *adapter, int index) in mac_prep() argument
4320 mac->adapter = adapter; in mac_prep()
4321 mac->multiport = adapter->params.nports > 2; in mac_prep()
4328 /* Gen2 adapter uses VPD xauicfg[] to notify driver which MAC in mac_prep()
4331 t3_os_pci_read_config_2(adapter, 0x2, &devid); in mac_prep()
4334 (!adapter->params.vpd.xauicfg[1] && (devid==0x37))) in mac_prep()
4339 if (adapter->params.rev == 0 && uses_xaui(adapter)) { in mac_prep()
4340 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset, in mac_prep()
4341 is_10G(adapter) ? 0x2901c04 : 0x2301c04); in mac_prep()
4342 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset, in mac_prep()
4349 * @adapter: the adapter
4350 * @ai: contains information about the adapter type and properties
4356 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai) in early_hw_init() argument
4358 u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ? in early_hw_init()
4362 mi1_init(adapter, ai); in early_hw_init()
4363 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */ in early_hw_init()
4364 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1)); in early_hw_init()
4365 t3_write_reg(adapter, A_T3DBG_GPIO_EN, in early_hw_init()
4367 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0); in early_hw_init()
4368 t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff)); in early_hw_init()
4370 if (adapter->params.rev == 0 || !uses_xaui(adapter)) in early_hw_init()
4374 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
4375 (void) t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
4378 t3_write_reg(adapter, A_XGM_PORT_CFG, val); in early_hw_init()
4379 (void) t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
4380 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val); in early_hw_init()
4381 (void) t3_read_reg(adapter, A_XGM_PORT_CFG); in early_hw_init()
4385 * t3_reset_adapter - reset the adapter
4386 * @adapter: the adapter
4388 * Reset the adapter.
4390 int t3_reset_adapter(adapter_t *adapter) in t3_reset_adapter() argument
4393 adapter->params.rev < T3_REV_B2 && is_pcie(adapter); in t3_reset_adapter()
4397 t3_os_pci_save_state(adapter); in t3_reset_adapter()
4398 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE); in t3_reset_adapter()
4406 t3_os_pci_read_config_2(adapter, 0x00, &devid); in t3_reset_adapter()
4415 t3_os_pci_restore_state(adapter); in t3_reset_adapter()
4451 * @adapter: the adapter
4452 * @ai: contains information about the adapter type and properties
4454 * Initialize adapter SW state for the various HW modules, set initial
4455 * values for some adapter tunables, take PHYs out of reset, and
4458 int __devinit t3_prep_adapter(adapter_t *adapter, in t3_prep_adapter() argument
4464 get_pci_mode(adapter, &adapter->params.pci); in t3_prep_adapter()
4466 adapter->params.info = ai; in t3_prep_adapter()
4467 adapter->params.nports = ai->nports0 + ai->nports1; in t3_prep_adapter()
4468 adapter->params.chan_map = (!!ai->nports0) | (!!ai->nports1 << 1); in t3_prep_adapter()
4469 adapter->params.rev = t3_read_reg(adapter, A_PL_REV); in t3_prep_adapter()
4472 * We used to only run the "adapter check task" once a second if in t3_prep_adapter()
4477 * adapter state once a second ... in t3_prep_adapter()
4479 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
4481 if (adapter->params.nports > 2) in t3_prep_adapter()
4482 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS; in t3_prep_adapter()
4484 adapter->params.stats_update_period = is_10G(adapter) ? in t3_prep_adapter()
4486 adapter->params.pci.vpd_cap_addr = in t3_prep_adapter()
4487 t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); in t3_prep_adapter()
4489 ret = get_vpd_params(adapter, &adapter->params.vpd); in t3_prep_adapter()
4493 if (reset && t3_reset_adapter(adapter)) in t3_prep_adapter()
4496 if (adapter->params.vpd.mclk) { in t3_prep_adapter()
4497 struct tp_params *p = &adapter->params.tp; in t3_prep_adapter()
4499 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX"); in t3_prep_adapter()
4500 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX"); in t3_prep_adapter()
4501 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM"); in t3_prep_adapter()
4503 p->nchan = adapter->params.chan_map == 3 ? 2 : 1; in t3_prep_adapter()
4504 p->pmrx_size = t3_mc7_size(&adapter->pmrx); in t3_prep_adapter()
4505 p->pmtx_size = t3_mc7_size(&adapter->pmtx); in t3_prep_adapter()
4506 p->cm_size = t3_mc7_size(&adapter->cm); in t3_prep_adapter()
4510 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024; in t3_prep_adapter()
4514 adapter->params.rev > 0 ? 12 : 6; in t3_prep_adapter()
4515 p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) - in t3_prep_adapter()
4517 p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */ in t3_prep_adapter()
4520 adapter->params.offload = t3_mc7_size(&adapter->pmrx) && in t3_prep_adapter()
4521 t3_mc7_size(&adapter->pmtx) && in t3_prep_adapter()
4522 t3_mc7_size(&adapter->cm); in t3_prep_adapter()
4524 t3_sge_prep(adapter, &adapter->params.sge); in t3_prep_adapter()
4526 if (is_offload(adapter)) { in t3_prep_adapter()
4527 adapter->params.mc5.nservers = DEFAULT_NSERVERS; in t3_prep_adapter()
4529 adapter->params.mc5.nfilters = 0; in t3_prep_adapter()
4530 adapter->params.mc5.nroutes = 0; in t3_prep_adapter()
4531 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT); in t3_prep_adapter()
4533 init_mtus(adapter->params.mtus); in t3_prep_adapter()
4534 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t3_prep_adapter()
4537 early_hw_init(adapter, ai); in t3_prep_adapter()
4538 ret = init_parity(adapter); in t3_prep_adapter()
4542 if (adapter->params.nports > 2 && in t3_prep_adapter()
4543 (ret = t3_vsc7323_init(adapter, adapter->params.nports))) in t3_prep_adapter()
4546 for_each_port(adapter, i) { in t3_prep_adapter()
4549 struct port_info *p = adap2pinfo(adapter, i); in t3_prep_adapter()
4552 unsigned port_type = adapter->params.vpd.port_type[j]; in t3_prep_adapter()
4561 if (j >= ARRAY_SIZE(adapter->params.vpd.port_type)) in t3_prep_adapter()
4568 mac_prep(&p->mac, adapter, j); in t3_prep_adapter()
4576 memcpy(hw_addr, adapter->params.vpd.eth_base, 5); in t3_prep_adapter()
4577 hw_addr[5] = adapter->params.vpd.eth_base[5] + i; in t3_prep_adapter()
4579 t3_os_set_hw_addr(adapter, i, hw_addr); in t3_prep_adapter()
4585 * changes, schedule a scan of the adapter links at least in t3_prep_adapter()
4589 adapter->params.linkpoll_period > 10) in t3_prep_adapter()
4590 adapter->params.linkpoll_period = 10; in t3_prep_adapter()
4598 * @adapter: the adapter
4644 void t3_led_ready(adapter_t *adapter) in t3_led_ready() argument
4646 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL, in t3_led_ready()
4650 void t3_port_failover(adapter_t *adapter, int port) in t3_port_failover() argument
4655 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, in t3_port_failover()
4659 void t3_failover_done(adapter_t *adapter, int port) in t3_failover_done() argument
4661 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, in t3_failover_done()
4665 void t3_failover_clear(adapter_t *adapter) in t3_failover_clear() argument
4667 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE, in t3_failover_clear()
4671 static int t3_cim_hac_read(adapter_t *adapter, u32 addr, u32 *val) in t3_cim_hac_read() argument
4675 t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); in t3_cim_hac_read()
4676 if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, in t3_cim_hac_read()
4680 *val = t3_read_reg(adapter, A_CIM_HOST_ACC_DATA); in t3_cim_hac_read()
4685 static int t3_cim_hac_write(adapter_t *adapter, u32 addr, u32 val) in t3_cim_hac_write() argument
4689 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, val); in t3_cim_hac_write()
4692 t3_write_reg(adapter, A_CIM_HOST_ACC_CTRL, addr); in t3_cim_hac_write()
4694 if (t3_wait_op_done_val(adapter, A_CIM_HOST_ACC_CTRL, in t3_cim_hac_write()
4700 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, in t3_get_up_la() argument
4709 ret = t3_cim_hac_read(adapter, LA_CTRL, &v); in t3_get_up_la()
4717 ret = t3_cim_hac_write(adapter, LA_CTRL, 0); in t3_get_up_la()
4724 ret = t3_cim_hac_write(adapter, LA_CTRL, v); in t3_get_up_la()
4728 ret = t3_cim_hac_read(adapter, LA_CTRL, &v); in t3_get_up_la()
4736 ret = t3_cim_hac_read(adapter, LA_CTRL, &v); in t3_get_up_la()
4744 ret = t3_cim_hac_read(adapter, LA_DATA, &v); in t3_get_up_la()
4751 ret = t3_cim_hac_read(adapter, LA_CTRL, &v); in t3_get_up_la()
4759 t3_cim_hac_write(adapter, LA_CTRL, 1); in t3_get_up_la()
4763 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data) in t3_get_up_ioqs() argument
4772 ret = t3_cim_hac_read(adapter, (4 * i), &v); in t3_get_up_ioqs()
4783 ret = t3_cim_hac_read(adapter, base_addr + 4 * j, &v); in t3_get_up_ioqs()