Lines Matching +full:0 +full:x594
33 #define SGE3_BASE_ADDR 0x0
35 #define A_SG_CONTROL 0x0
82 #define M_USERSPACESIZE 0x1f
87 #define M_HOSTPAGESIZE 0x7
100 #define M_PKTSHIFT 0x7
124 #define S_GLOBALENABLE 0
128 #define A_SG_KDOORBELL 0x4
134 #define S_EGRCNTX 0
135 #define M_EGRCNTX 0xffff
139 #define A_SG_GTS 0x8
142 #define M_RSPQ 0x7
147 #define M_NEWTIMER 0x1fff
151 #define S_NEWINDEX 0
152 #define M_NEWINDEX 0xffff
156 #define A_SG_CONTEXT_CMD 0xc
159 #define M_CONTEXT_CMD_OPCODE 0xf
168 #define M_CQ_CREDIT 0x7f
188 #define S_CONTEXT 0
189 #define M_CONTEXT 0xffff
193 #define A_SG_CONTEXT_DATA0 0x10
194 #define A_SG_CONTEXT_DATA1 0x14
195 #define A_SG_CONTEXT_DATA2 0x18
196 #define A_SG_CONTEXT_DATA3 0x1c
197 #define A_SG_CONTEXT_MASK0 0x20
198 #define A_SG_CONTEXT_MASK1 0x24
199 #define A_SG_CONTEXT_MASK2 0x28
200 #define A_SG_CONTEXT_MASK3 0x2c
201 #define A_SG_RSPQ_CREDIT_RETURN 0x30
203 #define S_CREDITS 0
204 #define M_CREDITS 0xffff
208 #define A_SG_DATA_INTR 0x34
214 #define S_DATAINTR 0
215 #define M_DATAINTR 0xff
219 #define A_SG_HI_DRB_HI_THRSH 0x38
221 #define S_HIDRBHITHRSH 0
222 #define M_HIDRBHITHRSH 0x3ff
226 #define A_SG_HI_DRB_LO_THRSH 0x3c
228 #define S_HIDRBLOTHRSH 0
229 #define M_HIDRBLOTHRSH 0x3ff
233 #define A_SG_LO_DRB_HI_THRSH 0x40
235 #define S_LODRBHITHRSH 0
236 #define M_LODRBHITHRSH 0x3ff
240 #define A_SG_LO_DRB_LO_THRSH 0x44
242 #define S_LODRBLOTHRSH 0
243 #define M_LODRBLOTHRSH 0x3ff
247 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48
248 #define A_SG_RSPQ_FL_STATUS 0x4c
250 #define S_RSPQ0STARVED 0
282 #define S_RSPQXSTARVED 0
283 #define M_RSPQXSTARVED 0xff
384 #define M_FLXEMPTY 0xffff
388 #define A_SG_EGR_PRI_CNT 0x50
391 #define M_EGRERROPCODE 0xff
396 #define M_EGRHIOPCODE 0xff
401 #define M_EGRLOOPCODE 0xff
405 #define S_EGRPRICNT 0
406 #define M_EGRPRICNT 0x1f
410 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
413 #define M_HIRCQDRBTHRSH 0x7ff
417 #define S_LORCQDRBTHRSH 0
418 #define M_LORCQDRBTHRSH 0x7ff
422 #define A_SG_EGR_CNTX_BADDR 0x58
425 #define M_EGRCNTXBADDR 0x7ffffff
429 #define A_SG_INT_CAUSE 0x5c
448 #define M_FLPARITYERROR 0x3f
453 #define M_ITPARITYERROR 0x3
533 #define S_RSPQSTARVE 0
537 #define A_SG_INT_ENABLE 0x60
538 #define A_SG_CMDQ_CREDIT_TH 0x64
541 #define M_TIMEOUT 0xffffff
545 #define S_THRESHOLD 0
546 #define M_THRESHOLD 0xff
550 #define A_SG_TIMER_TICK 0x68
551 #define A_SG_CQ_CONTEXT_BADDR 0x6c
554 #define M_BASEADDR 0x7ffffff
558 #define A_SG_OCO_BASE 0x70
561 #define M_BASE1 0xffff
565 #define S_BASE0 0
566 #define M_BASE0 0xffff
570 #define A_SG_DRB_PRI_THRESH 0x74
572 #define S_DRBPRITHRSH 0
573 #define M_DRBPRITHRSH 0xffff
577 #define A_SG_DEBUG_INDEX 0x78
578 #define A_SG_DEBUG_DATA 0x7c
581 #define PCIX1_BASE_ADDR 0x80
583 #define A_PCIX_INT_ENABLE 0x80
586 #define M_MSIXPARERR 0x7
591 #define M_CFPARERR 0xf
596 #define M_RFPARERR 0xf
601 #define M_WFPARERR 0x3
649 #define S_MSTDETPARERR 0
653 #define A_PCIX_INT_CAUSE 0x84
654 #define A_PCIX_CFG 0x88
673 #define M_ASYNCINTVEC 0x1f
678 #define M_MAXSPLTRNC 0x7
683 #define M_MAXSPLTRNR 0x7
688 #define M_MAXWRBYTECNT 0x3
700 #define S_PIOACK64EN 0
704 #define A_PCIX_MODE 0x8c
707 #define M_PCLKRANGE 0x3
712 #define M_PCIXINITPAT 0xf
720 #define S_64BIT 0
724 #define A_PCIX_CAL 0x90
731 #define M_PERCALDIV 0xff
752 #define M_ZPDMAN 0x7
757 #define M_ZPUMAN 0x7
762 #define M_ZPDOUT 0x7
767 #define M_ZPUOUT 0x7
772 #define M_ZPDIN 0x7
776 #define S_ZPUIN 0
777 #define M_ZPUIN 0x7
781 #define A_PCIX_WOL 0x94
795 #define S_SLEEPMODE0 0
799 #define A_PCIX_STAT0 0x98
802 #define M_PIOREQFIFOLEVEL 0x3f
807 #define M_RFINIST 0x3
812 #define M_RFRESPRDST 0x3
817 #define M_TARCST 0x7
822 #define M_TARXST 0x7
827 #define M_WFREQWRST 0x7
848 #define M_PIORESPFIFOLEVEL 0x3
876 #define S_SPLTRNPND 0
880 #define A_PCIX_STAT1 0x9c
883 #define M_WFINIST 0xf
888 #define M_ARBST 0x7
893 #define M_PMIST 0x3
898 #define M_CALST 0x3
903 #define M_CFREQRDST 0x3
908 #define M_CFINIST 0x3
913 #define M_CFRESPRDST 0x3
918 #define M_INICST 0x7
923 #define M_INIXST 0x7
928 #define M_INTST 0x7
933 #define M_PIOST 0x3
937 #define S_RFREQRDST 0
938 #define M_RFREQRDST 0x3
943 #define PCIE0_BASE_ADDR 0x80
945 #define A_PCIE_INT_ENABLE 0x80
948 #define M_BISTERR 0xff
969 #define M_PCIE_MSIXPARERR 0x7
1017 #define S_PEXERR 0
1021 #define A_PCIE_INT_CAUSE 0x84
1022 #define A_PCIE_CFG 0x88
1061 #define M_PCIE_MAXSPLTRNC 0xf
1066 #define M_PCIE_MAXSPLTRNR 0x3f
1070 #define S_CRSTWRMMODE 0
1074 #define A_PCIE_MODE 0x8c
1077 #define M_TAR_STATE 0x7
1082 #define M_RF_STATEINI 0x7
1087 #define M_CF_STATEINI 0x7
1092 #define M_PIO_STATEPL 0x7
1097 #define M_PIO_STATEISC 0x3
1102 #define M_NUMFSTTRNSEQRX 0xff
1107 #define M_LNKCNTLSTATE 0xff
1115 #define S_LNKINITIAL 0
1119 #define A_PCIE_STAT 0x90
1122 #define M_INI_STATE 0xf
1127 #define M_WF_STATEINI 0xf
1132 #define M_PLM_REQFIFOCNT 0x3
1161 #define M_PIO_RSPFIFOCNT 0x1f
1166 #define M_PIO_REQFIFOCNT 0x3f
1186 #define S_VPD_REQFIFOEMPTY 0
1190 #define A_PCIE_CAL 0x90
1205 #define M_ZMAN 0x7
1210 #define M_ZOUT 0x1f
1214 #define S_ZIN 0
1215 #define M_ZIN 0x7
1219 #define A_PCIE_WOL 0x94
1222 #define M_CF_RSPSTATE 0x3
1227 #define M_RF_RSPSTATE 0x3
1232 #define M_PME_STATE 0x7
1237 #define M_INT_STATE 0x7
1241 #define A_PCIE_PEX_CTRL0 0x98
1252 #define M_NUMFSTTRNSEQ 0xff
1257 #define M_REPLAYLMT 0xfffff
1265 #define S_CPLPNDCHKEN 0
1269 #define A_PCIE_PEX_CTRL1 0x9c
1276 #define M_DLLPTIMEOUTLMT 0x3ffff
1280 #define S_ACKLAT 0
1281 #define M_ACKLAT 0x1fff
1286 #define M_T3A_DLLPTIMEOUTLMT 0xfffff
1290 #define S_T3A_ACKLAT 0
1291 #define M_T3A_ACKLAT 0x7ff
1295 #define A_PCIE_PEX_CTRL2 0xa0
1318 #define M_L1ASPMTXRXL0STIME 0xfff
1323 #define M_L0SIDLETIME 0x7ff
1335 #define S_ENTERL0SEN 0
1343 #define A_PCIE_PEX_ERR 0xa4
1346 #define M_CPLTIMEOUTID 0x7f
1418 #define S_PSNCPL 0
1422 #define A_PCIE_SERDES_CTRL 0xa8
1428 #define S_LANE 0
1429 #define M_LANE 0x7
1433 #define A_PCIE_PIPE_CTRL 0xa8
1436 #define M_RECDETUSEC 0x7
1441 #define M_PLLLCKCYC 0x1fff
1446 #define M_ELECIDLEDETCYC 0x7
1458 #define S_PCLKOFFINP1 0
1462 #define A_PCIE_SERDES_QUAD_CTRL0 0xac
1465 #define M_TESTSIG 0x7ffff
1470 #define M_OFFSET 0xff
1478 #define S_IDDQB 0
1487 #define M_MANLPBKEN 0x3
1528 #define M_PCIE_CMURANGE 0x7
1553 #define M_PCIE_GAIN 0x1f
1558 #define M_PCIE_BANDGAP 0xf
1566 #define S_PREEMPH 0
1567 #define M_PREEMPH 0x3
1571 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0
1594 #define M_RXEQCTL 0x3
1603 #define M_REFSEL 0x3
1608 #define M_RXTERMADJ 0x3
1613 #define M_TXTERMADJ 0x3
1618 #define M_DEQ 0xf
1623 #define M_DTX 0xf
1651 #define S_PCLKDETECT 0
1655 #define A_PCIE_SERDES_STATUS0 0xb0
1658 #define M_RXERRLANE7 0x7
1663 #define M_RXERRLANE6 0x7
1668 #define M_RXERRLANE5 0x7
1673 #define M_RXERRLANE4 0x7
1678 #define M_PCIE_RXERRLANE3 0x7
1683 #define M_PCIE_RXERRLANE2 0x7
1688 #define M_PCIE_RXERRLANE1 0x7
1692 #define S_PCIE_RXERRLANE0 0
1693 #define M_PCIE_RXERRLANE0 0x7
1697 #define A_PCIE_SERDES_LANE_CTRL 0xb4
1712 #define M_EXTBISTPAT 0x7
1753 #define M_MANFMOFFSET 0x1f
1765 #define S_INTSERLPBK 0
1769 #define A_PCIE_SERDES_STATUS1 0xb4
1867 #define S_PCIE_RXOFLOWLANE0 0
1871 #define A_PCIE_SERDES_LANE_STAT 0xb8
1874 #define M_EXTBISTCHKERRCNT 0xffffff
1902 #define S_TXIDLEDETECT 0
1906 #define A_PCIE_SERDES_STATUS2 0xb8
2032 #define S_PCIE_RXADDSKIPLANE0 0
2036 #define A_PCIE_PEX_WMARK 0xbc
2039 #define M_P_WMARK 0x7ff
2044 #define M_NP_WMARK 0x7f
2048 #define S_CPL_WMARK 0
2049 #define M_CPL_WMARK 0x7ff
2053 #define A_PCIE_SERDES_BIST 0xbc
2056 #define M_PCIE_BISTDONE 0xff
2061 #define M_PCIE_BISTCYCLETHRESH 0xffff
2065 #define S_BISTMODE 0
2066 #define M_BISTMODE 0x7
2071 #define T3DBG_BASE_ADDR 0xc0
2073 #define A_T3DBG_DBG0_CFG 0xc0
2076 #define M_REGSELECT 0xff
2081 #define M_MODULESELECT 0x1f
2085 #define S_CLKSELECT 0
2086 #define M_CLKSELECT 0xf
2090 #define A_T3DBG_DBG0_EN 0xc4
2100 #define S_PORTEN 0
2104 #define A_T3DBG_DBG1_CFG 0xc8
2105 #define A_T3DBG_DBG1_EN 0xcc
2106 #define A_T3DBG_GPIO_EN 0xd0
2200 #define S_GPIO0_OUT_VAL 0
2204 #define A_T3DBG_GPIO_IN 0xd4
2298 #define S_GPIO0_IN 0
2302 #define A_T3DBG_INT_ENABLE 0xd8
2368 #define S_GPIO0 0
2376 #define A_T3DBG_INT_CAUSE 0xdc
2377 #define A_T3DBG_DBG0_RST_VALUE 0xe0
2379 #define S_DEBUGDATA 0
2380 #define M_DEBUGDATA 0xff
2384 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4
2410 #define S_C_OCLK_EN 0
2414 #define A_T3DBG_PLL_LOCK 0xe8
2432 #define S_PLL_C_LOCK 0
2440 #define A_T3DBG_SERDES_RBC_CFG 0xec
2443 #define M_X_RBC_LANE_SEL 0x3
2456 #define M_PE_RBC_LANE_SEL 0x7
2460 #define S_PE_RBC_DBG_EN 0
2464 #define A_T3DBG_GPIO_ACT_LOW 0xf0
2530 #define S_GPIO0_ACT_LOW 0
2538 #define A_T3DBG_PMON_CFG 0xf4
2549 #define M_PMON_FDEL_AUTO 0x3f
2554 #define M_PMON_CDEL_AUTO 0x3f
2559 #define M_PMON_FDEL_MANUAL 0x3f
2564 #define M_PMON_CDEL_MANUAL 0x3f
2572 #define S_PMON_AUTO 0
2576 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8
2587 #define M_PE_REFCLK_TERMADJ 0x3
2596 #define M_X_REFCLK_TERMADJ 0x3
2600 #define S_X_REFCLK_PD 0
2604 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc
2611 #define M_BSINSELLANE7 0x3
2620 #define M_BSINSELLANE6 0x3
2629 #define M_BSINSELLANE5 0x3
2638 #define M_BSINSELLANE4 0x3
2651 #define M_BSINSELLANE3 0x3
2660 #define M_BSINSELLANE2 0x3
2669 #define M_BSINSELLANE1 0x3
2678 #define M_BSINSELLANE0 0x3
2682 #define S_BSENLANE0 0
2687 #define MC7_PMRX_BASE_ADDR 0x100
2689 #define A_MC7_CFG 0x100
2712 #define M_WIDTH 0x3
2729 #define M_DEN 0x7
2737 #define S_CLKEN 0
2741 #define A_MC7_MODE 0x104
2743 #define S_MODE 0
2744 #define M_MODE 0xffff
2748 #define A_MC7_EXT_MODE1 0x108
2755 #define M_OCDCODE 0xf
2759 #define S_EXTMODE1 0
2760 #define M_EXTMODE1 0xffff
2764 #define A_MC7_EXT_MODE2 0x10c
2766 #define S_EXTMODE2 0
2767 #define M_EXTMODE2 0xffff
2771 #define A_MC7_EXT_MODE3 0x110
2773 #define S_EXTMODE3 0
2774 #define M_EXTMODE3 0xffff
2778 #define A_MC7_PRE 0x114
2779 #define A_MC7_REF 0x118
2782 #define M_PREREFDIV 0x3fff
2786 #define S_PERREFEN 0
2790 #define A_MC7_DLL 0x11c
2797 #define M_DLLDELTA 0x7f
2802 #define M_MANDELTA 0x7f
2814 #define S_DLLRST 0
2818 #define A_MC7_PARM 0x120
2821 #define M_ACTTOPREDLY 0xf
2826 #define M_ACTTORDWRDLY 0x7
2831 #define M_PRECYC 0x7
2836 #define M_REFCYC 0x7f
2841 #define M_BKCYC 0x1f
2846 #define M_WRTORDDLY 0xf
2850 #define S_RDTOWRDLY 0
2851 #define M_RDTOWRDLY 0xf
2855 #define A_MC7_HWM_WRR 0x124
2858 #define M_MEM_HWM 0x3f
2863 #define M_ULP_HWM 0xf
2868 #define M_TOT_RLD_WT 0xff
2873 #define M_MEM_RLD_WT 0x7f
2877 #define S_ULP_RLD_WT 0
2878 #define M_ULP_RLD_WT 0x7f
2882 #define A_MC7_CAL 0x128
2893 #define M_PER_CAL_DIV 0xff
2914 #define M_IMP_MAN_PD 0x7
2919 #define M_IMP_MAN_PU 0x7
2924 #define M_IMP_CAL_PD 0x7
2929 #define M_IMP_CAL_PU 0x7
2934 #define M_IMP_SET_PD 0x7
2938 #define S_IMP_SET_PU 0
2939 #define M_IMP_SET_PU 0x7
2943 #define A_MC7_ERR_ADDR 0x12c
2946 #define M_ERRADDRESS 0x1fffffff
2951 #define M_ERRAGENT 0x3
2955 #define S_ERROP 0
2959 #define A_MC7_ECC 0x130
2962 #define M_UECNT 0xff
2967 #define M_CECNT 0xff
2975 #define S_ECCGENEN 0
2979 #define A_MC7_CE_ADDR 0x134
2980 #define A_MC7_CE_DATA0 0x138
2981 #define A_MC7_CE_DATA1 0x13c
2982 #define A_MC7_CE_DATA2 0x140
2984 #define S_DATA 0
2985 #define M_DATA 0xff
2989 #define A_MC7_UE_ADDR 0x144
2990 #define A_MC7_UE_DATA0 0x148
2991 #define A_MC7_UE_DATA1 0x14c
2992 #define A_MC7_UE_DATA2 0x150
2993 #define A_MC7_BD_ADDR 0x154
2996 #define M_ADDR 0x1fffffff
3000 #define A_MC7_BD_DATA0 0x158
3001 #define A_MC7_BD_DATA1 0x15c
3002 #define A_MC7_BD_DATA2 0x160
3003 #define A_MC7_BD_OP 0x164
3005 #define S_OP 0
3009 #define A_MC7_BIST_ADDR_BEG 0x168
3012 #define M_ADDRBEG 0x7ffffff
3016 #define A_MC7_BIST_ADDR_END 0x16c
3019 #define M_ADDREND 0x7ffffff
3023 #define A_MC7_BIST_DATA 0x170
3024 #define A_MC7_BIST_OP 0x174
3027 #define M_GAP 0x1f
3036 #define M_DATAPAT 0x3
3040 #define A_MC7_INT_ENABLE 0x178
3047 #define M_PE 0x7fff
3055 #define S_CE 0
3059 #define A_MC7_INT_CAUSE 0x17c
3062 #define MC7_PMTX_BASE_ADDR 0x180
3065 #define MC7_CM_BASE_ADDR 0x200
3068 #define CIM_BASE_ADDR 0x280
3070 #define A_CIM_BOOT_CFG 0x280
3073 #define M_BOOTADDR 0x3fffffff
3081 #define S_UPCRST 0
3085 #define A_CIM_FLASH_BASE_ADDR 0x284
3088 #define M_FLASHBASEADDR 0x3fffff
3092 #define A_CIM_FLASH_ADDR_SIZE 0x288
3095 #define M_FLASHADDRSIZE 0x3fffff
3099 #define A_CIM_SDRAM_BASE_ADDR 0x28c
3102 #define M_SDRAMBASEADDR 0x3fffffff
3106 #define A_CIM_SDRAM_ADDR_SIZE 0x290
3109 #define M_SDRAMADDRSIZE 0x3fffffff
3113 #define A_CIM_UP_SPARE_INT 0x294
3115 #define S_UPSPAREINT 0
3116 #define M_UPSPAREINT 0x7
3120 #define A_CIM_HOST_INT_ENABLE 0x298
3230 #define S_RSVDSPACEINTEN 0
3234 #define A_CIM_HOST_INT_CAUSE 0x29c
3296 #define S_RSVDSPACEINT 0
3300 #define A_CIM_UP_INT_ENABLE 0x2a0
3306 #define A_CIM_UP_INT_CAUSE 0x2a4
3312 #define A_CIM_IBQ_FULLA_THRSH 0x2a8
3314 #define S_IBQ0FULLTHRSH 0
3315 #define M_IBQ0FULLTHRSH 0x1ff
3320 #define M_IBQ1FULLTHRSH 0x1ff
3324 #define A_CIM_IBQ_FULLB_THRSH 0x2ac
3326 #define S_IBQ2FULLTHRSH 0
3327 #define M_IBQ2FULLTHRSH 0x1ff
3332 #define M_IBQ3FULLTHRSH 0x1ff
3336 #define A_CIM_HOST_ACC_CTRL 0x2b0
3346 #define S_HOSTADDR 0
3347 #define M_HOSTADDR 0xffff
3351 #define A_CIM_HOST_ACC_DATA 0x2b4
3352 #define A_CIM_IBQ_DBG_CFG 0x2c0
3355 #define M_IBQDBGADDR 0x1ff
3360 #define M_IBQDBGQID 0x3
3372 #define S_IBQDBGEN 0
3376 #define A_CIM_OBQ_DBG_CFG 0x2c4
3379 #define M_OBQDBGADDR 0x1ff
3384 #define M_OBQDBGQID 0x3
3396 #define S_OBQDBGEN 0
3400 #define A_CIM_IBQ_DBG_DATA 0x2c8
3401 #define A_CIM_OBQ_DBG_DATA 0x2cc
3402 #define A_CIM_CDEBUGDATA 0x2d0
3405 #define M_CDEBUGDATAH 0xffff
3409 #define S_CDEBUGDATAL 0
3410 #define M_CDEBUGDATAL 0xffff
3414 #define A_CIM_DEBUGCFG 0x2e0
3417 #define M_POLADBGRDPTR 0x1ff
3422 #define M_PILADBGRDPTR 0x1ff
3431 #define M_DEBUGSELHI 0x1f
3435 #define S_DEBUGSELLO 0
3436 #define M_DEBUGSELLO 0x1f
3440 #define A_CIM_DEBUGSTS 0x2e4
3443 #define M_POLADBGWRPTR 0x1ff
3447 #define S_PILADBGWRPTR 0
3448 #define M_PILADBGWRPTR 0x1ff
3452 #define A_CIM_PO_LA_DEBUGDATA 0x2e8
3453 #define A_CIM_PI_LA_DEBUGDATA 0x2ec
3456 #define TP1_BASE_ADDR 0x300
3458 #define A_TP_IN_CONFIG 0x300
3469 #define M_DBMAXOPCNT 0xff
3517 #define S_CTUNNEL 0
3521 #define A_TP_OUT_CONFIG 0x304
3563 #define S_OUT_CETHERNET 0
3567 #define A_TP_GLOBAL_CONFIG 0x308
3570 #define M_SYNCOOKIEPARAMS 0x3f
3603 #define M_FIVETUPLELOOKUP 0x3
3632 #define M_TCAMSERVERUSE 0x3
3636 #define S_IPTTL 0
3637 #define M_IPTTL 0xff
3641 #define A_TP_GLOBAL_RX_CREDIT 0x30c
3642 #define A_TP_CMM_SIZE 0x310
3644 #define S_CMMEMMGRSIZE 0
3645 #define M_CMMEMMGRSIZE 0xfffffff
3649 #define A_TP_CMM_MM_BASE 0x314
3651 #define S_CMMEMMGRBASE 0
3652 #define M_CMMEMMGRBASE 0xfffffff
3656 #define A_TP_CMM_TIMER_BASE 0x318
3659 #define M_CMTIMERMAXNUM 0x3
3663 #define S_CMTIMERBASE 0
3664 #define M_CMTIMERBASE 0xfffffff
3668 #define A_TP_PMM_SIZE 0x31c
3670 #define S_PMSIZE 0
3671 #define M_PMSIZE 0xfffffff
3675 #define A_TP_PMM_TX_BASE 0x320
3676 #define A_TP_PMM_DEFRAG_BASE 0x324
3677 #define A_TP_PMM_RX_BASE 0x328
3678 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
3679 #define A_TP_PMM_RX_MAX_PAGE 0x330
3681 #define S_PMRXMAXPAGE 0
3682 #define M_PMRXMAXPAGE 0x1fffff
3686 #define A_TP_PMM_TX_PAGE_SIZE 0x334
3687 #define A_TP_PMM_TX_MAX_PAGE 0x338
3689 #define S_PMTXMAXPAGE 0
3690 #define M_PMTXMAXPAGE 0x1fffff
3694 #define A_TP_TCP_OPTIONS 0x340
3697 #define M_MTUDEFAULT 0xffff
3714 #define M_SACKMODE 0x3
3719 #define M_WINDOWSCALEMODE 0x3
3723 #define S_TIMESTAMPSMODE 0
3724 #define M_TIMESTAMPSMODE 0x3
3728 #define A_TP_DACK_CONFIG 0x344
3731 #define M_AUTOSTATE3 0x3
3736 #define M_AUTOSTATE2 0x3
3741 #define M_AUTOSTATE1 0x3
3746 #define M_BYTETHRESHOLD 0xfffff
3751 #define M_MSSTHRESHOLD 0x3
3763 #define S_DACK_MODE 0
3767 #define A_TP_PC_CONFIG 0x348
3881 #define S_TABLELATENCYDELTA 0
3882 #define M_TABLELATENCYDELTA 0xf
3886 #define A_TP_PC_CONFIG2 0x34c
3944 #define S_ENABLEOLDRXFORWARD 0
3952 #define A_TP_TCP_BACKOFF_REG0 0x350
3955 #define M_TIMERBACKOFFINDEX3 0xff
3960 #define M_TIMERBACKOFFINDEX2 0xff
3965 #define M_TIMERBACKOFFINDEX1 0xff
3969 #define S_TIMERBACKOFFINDEX0 0
3970 #define M_TIMERBACKOFFINDEX0 0xff
3974 #define A_TP_TCP_BACKOFF_REG1 0x354
3977 #define M_TIMERBACKOFFINDEX7 0xff
3982 #define M_TIMERBACKOFFINDEX6 0xff
3987 #define M_TIMERBACKOFFINDEX5 0xff
3991 #define S_TIMERBACKOFFINDEX4 0
3992 #define M_TIMERBACKOFFINDEX4 0xff
3996 #define A_TP_TCP_BACKOFF_REG2 0x358
3999 #define M_TIMERBACKOFFINDEX11 0xff
4004 #define M_TIMERBACKOFFINDEX10 0xff
4009 #define M_TIMERBACKOFFINDEX9 0xff
4013 #define S_TIMERBACKOFFINDEX8 0
4014 #define M_TIMERBACKOFFINDEX8 0xff
4018 #define A_TP_TCP_BACKOFF_REG3 0x35c
4021 #define M_TIMERBACKOFFINDEX15 0xff
4026 #define M_TIMERBACKOFFINDEX14 0xff
4031 #define M_TIMERBACKOFFINDEX13 0xff
4035 #define S_TIMERBACKOFFINDEX12 0
4036 #define M_TIMERBACKOFFINDEX12 0xff
4040 #define A_TP_PARA_REG0 0x360
4043 #define M_INITCWND 0x7
4048 #define M_DUPACKTHRESH 0xf
4052 #define A_TP_PARA_REG1 0x364
4055 #define M_INITRWND 0xffff
4059 #define S_INITIALSSTHRESH 0
4060 #define M_INITIALSSTHRESH 0xffff
4064 #define A_TP_PARA_REG2 0x368
4067 #define M_MAXRXDATA 0xffff
4071 #define S_RXCOALESCESIZE 0
4072 #define M_RXCOALESCESIZE 0xffff
4076 #define A_TP_PARA_REG3 0x36c
4087 #define M_TXDATAACKIDX 0xf
4092 #define M_RXFRAGENABLE 0x7
4125 #define M_CNGCTRLMODE 0x3
4133 #define S_RXCOALESCEPSHEN 0
4137 #define A_TP_PARA_REG4 0x370
4140 #define M_HIGHSPEEDCFG 0xff
4145 #define M_NEWRENOCFG 0xff
4150 #define M_TAHOECFG 0xff
4154 #define S_RENOCFG 0
4155 #define M_RENOCFG 0xff
4159 #define A_TP_PARA_REG5 0x374
4162 #define M_INDICATESIZE 0xffff
4182 #define S_PUSHTIMERENABLE 0
4186 #define A_TP_PARA_REG6 0x378
4189 #define M_TXPDUSIZEADJ 0xff
4241 #define S_DISABLEPDUXMT 0
4269 #define A_TP_PARA_REG7 0x37c
4272 #define M_PMMAXXFERLEN1 0xffff
4276 #define S_PMMAXXFERLEN0 0
4277 #define M_PMMAXXFERLEN0 0xffff
4281 #define A_TP_TIMER_RESOLUTION 0x390
4284 #define M_TIMERRESOLUTION 0xff
4289 #define M_TIMESTAMPRESOLUTION 0xff
4293 #define S_DELAYEDACKRESOLUTION 0
4294 #define M_DELAYEDACKRESOLUTION 0xff
4298 #define A_TP_MSL 0x394
4300 #define S_MSL 0
4301 #define M_MSL 0x3fffffff
4305 #define A_TP_RXT_MIN 0x398
4307 #define S_RXTMIN 0
4308 #define M_RXTMIN 0x3fffffff
4312 #define A_TP_RXT_MAX 0x39c
4314 #define S_RXTMAX 0
4315 #define M_RXTMAX 0x3fffffff
4319 #define A_TP_PERS_MIN 0x3a0
4321 #define S_PERSMIN 0
4322 #define M_PERSMIN 0x3fffffff
4326 #define A_TP_PERS_MAX 0x3a4
4328 #define S_PERSMAX 0
4329 #define M_PERSMAX 0x3fffffff
4333 #define A_TP_KEEP_IDLE 0x3a8
4335 #define S_KEEPALIVEIDLE 0
4336 #define M_KEEPALIVEIDLE 0x3fffffff
4340 #define A_TP_KEEP_INTVL 0x3ac
4342 #define S_KEEPALIVEINTVL 0
4343 #define M_KEEPALIVEINTVL 0x3fffffff
4347 #define A_TP_INIT_SRTT 0x3b0
4349 #define S_INITSRTT 0
4350 #define M_INITSRTT 0xffff
4354 #define A_TP_DACK_TIMER 0x3b4
4356 #define S_DACKTIME 0
4357 #define M_DACKTIME 0xfff
4361 #define A_TP_FINWAIT2_TIMER 0x3b8
4363 #define S_FINWAIT2TIME 0
4364 #define M_FINWAIT2TIME 0x3fffffff
4368 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc
4370 #define S_FASTFINWAIT2TIME 0
4371 #define M_FASTFINWAIT2TIME 0x3fffffff
4375 #define A_TP_SHIFT_CNT 0x3c0
4378 #define M_SYNSHIFTMAX 0xff
4383 #define M_RXTSHIFTMAXR1 0xf
4388 #define M_RXTSHIFTMAXR2 0xf
4393 #define M_PERSHIFTBACKOFFMAX 0xf
4398 #define M_PERSHIFTMAX 0xf
4402 #define S_KEEPALIVEMAX 0
4403 #define M_KEEPALIVEMAX 0xff
4407 #define A_TP_TIME_HI 0x3c8
4408 #define A_TP_TIME_LO 0x3cc
4409 #define A_TP_MTU_PORT_TABLE 0x3d0
4412 #define M_PORT1MTUVALUE 0xffff
4416 #define S_PORT0MTUVALUE 0
4417 #define M_PORT0MTUVALUE 0xffff
4421 #define A_TP_ULP_TABLE 0x3d4
4424 #define M_ULPTYPE7FIELD 0xf
4429 #define M_ULPTYPE6FIELD 0xf
4434 #define M_ULPTYPE5FIELD 0xf
4439 #define M_ULPTYPE4FIELD 0xf
4444 #define M_ULPTYPE3FIELD 0xf
4449 #define M_ULPTYPE2FIELD 0xf
4454 #define M_ULPTYPE1FIELD 0xf
4458 #define S_ULPTYPE0FIELD 0
4459 #define M_ULPTYPE0FIELD 0xf
4463 #define A_TP_PACE_TABLE 0x3d8
4464 #define A_TP_CCTRL_TABLE 0x3dc
4465 #define A_TP_TOS_TABLE 0x3e0
4466 #define A_TP_MTU_TABLE 0x3e4
4467 #define A_TP_RSS_MAP_TABLE 0x3e8
4468 #define A_TP_RSS_LKP_TABLE 0x3ec
4469 #define A_TP_RSS_CONFIG 0x3f0
4528 #define M_RRCPLCPUSIZE 0x7
4544 #define S_DISABLE 0
4548 #define A_TP_RSS_CONFIG_TNL 0x3f4
4551 #define M_MASKSIZE 0x7
4556 #define M_DEFAULTCPUBASE 0x3f
4561 #define M_DEFAULTCPU 0x3f
4565 #define S_DEFAULTQUEUE 0
4566 #define M_DEFAULTQUEUE 0xffff
4570 #define A_TP_RSS_CONFIG_OFD 0x3f8
4571 #define A_TP_RSS_CONFIG_SYN 0x3fc
4572 #define A_TP_RSS_SECRET_KEY0 0x400
4573 #define A_TP_RSS_SECRET_KEY1 0x404
4574 #define A_TP_RSS_SECRET_KEY2 0x408
4575 #define A_TP_RSS_SECRET_KEY3 0x40c
4576 #define A_TP_TM_PIO_ADDR 0x418
4577 #define A_TP_TM_PIO_DATA 0x41c
4578 #define A_TP_TX_MOD_QUE_TABLE 0x420
4579 #define A_TP_TX_RESOURCE_LIMIT 0x424
4582 #define M_TX_RESOURCE_LIMIT_CH1_PC 0xff
4587 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC 0xff
4592 #define M_TX_RESOURCE_LIMIT_CH0_PC 0xff
4596 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC 0
4597 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC 0xff
4601 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
4604 #define M_RX_MOD_WEIGHT 0xff
4609 #define M_TX_MOD_WEIGHT 0xff
4614 #define M_TX_MOD_TIMER_MODE 0xff
4618 #define S_TX_MOD_QUEUE_REQ_MAP 0
4619 #define M_TX_MOD_QUEUE_REQ_MAP 0xff
4623 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
4626 #define M_TP_TX_MODQ_WGHT7 0xff
4631 #define M_TP_TX_MODQ_WGHT6 0xff
4636 #define M_TP_TX_MODQ_WGHT5 0xff
4640 #define S_TP_TX_MODQ_WGHT4 0
4641 #define M_TP_TX_MODQ_WGHT4 0xff
4645 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
4648 #define M_TP_TX_MODQ_WGHT3 0xff
4653 #define M_TP_TX_MODQ_WGHT2 0xff
4658 #define M_TP_TX_MODQ_WGHT1 0xff
4662 #define S_TP_TX_MODQ_WGHT0 0
4663 #define M_TP_TX_MODQ_WGHT0 0xff
4667 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
4670 #define M_RX_MOD_CHANNEL_WEIGHT1 0xff
4675 #define M_RX_MOD_CHANNEL_WEIGHT0 0xff
4680 #define M_TX_MOD_CHANNEL_WEIGHT1 0xff
4684 #define S_TX_MOD_CHANNEL_WEIGHT0 0
4685 #define M_TX_MOD_CHANNEL_WEIGHT0 0xff
4689 #define A_TP_MOD_RATE_LIMIT 0x438
4692 #define M_RX_MOD_RATE_LIMIT_INC 0xff
4697 #define M_RX_MOD_RATE_LIMIT_TICK 0xff
4702 #define M_TX_MOD_RATE_LIMIT_INC 0xff
4706 #define S_TX_MOD_RATE_LIMIT_TICK 0
4707 #define M_TX_MOD_RATE_LIMIT_TICK 0xff
4711 #define A_TP_PIO_ADDR 0x440
4712 #define A_TP_PIO_DATA 0x444
4713 #define A_TP_RESET 0x44c
4719 #define S_TPRESET 0
4723 #define A_TP_MIB_INDEX 0x450
4724 #define A_TP_MIB_RDATA 0x454
4725 #define A_TP_SYNC_TIME_HI 0x458
4726 #define A_TP_SYNC_TIME_LO 0x45c
4727 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
4729 #define S_CMRXFLSTBASE 0
4730 #define M_CMRXFLSTBASE 0xfffffff
4734 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
4736 #define S_CMTXFLSTBASE 0
4737 #define M_CMTXFLSTBASE 0xfffffff
4741 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
4743 #define S_CMPSFLSTBASE 0
4744 #define M_CMPSFLSTBASE 0xfffffff
4748 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
4750 #define S_CMMAXPSTRUCT 0
4751 #define M_CMMAXPSTRUCT 0x1fffff
4755 #define A_TP_INT_ENABLE 0x470
4877 #define S_CTPINETHFIFOPERR 0
4881 #define A_TP_INT_CAUSE 0x474
4882 #define A_TP_FLM_FREE_PS_CNT 0x480
4884 #define S_FREEPSTRUCTCOUNT 0
4885 #define M_FREEPSTRUCTCOUNT 0x1fffff
4889 #define A_TP_FLM_FREE_RX_CNT 0x484
4891 #define S_FREERXPAGECOUNT 0
4892 #define M_FREERXPAGECOUNT 0x1fffff
4896 #define A_TP_FLM_FREE_TX_CNT 0x488
4898 #define S_FREETXPAGECOUNT 0
4899 #define M_FREETXPAGECOUNT 0x1fffff
4903 #define A_TP_TM_HEAP_PUSH_CNT 0x48c
4904 #define A_TP_TM_HEAP_POP_CNT 0x490
4905 #define A_TP_TM_DACK_PUSH_CNT 0x494
4906 #define A_TP_TM_DACK_POP_CNT 0x498
4907 #define A_TP_TM_MOD_PUSH_CNT 0x49c
4908 #define A_TP_MOD_POP_CNT 0x4a0
4909 #define A_TP_TIMER_SEPARATOR 0x4a4
4910 #define A_TP_DEBUG_SEL 0x4a8
4911 #define A_TP_DEBUG_FLAGS 0x4ac
5001 #define S_TXRCVADVLTMSS 0
5006 #define M_RXDEBUGFLAGS 0xffff
5010 #define S_TXDEBUGFLAGS 0
5011 #define M_TXDEBUGFLAGS 0xffff
5015 #define A_TP_PROXY_FLOW_CNTL 0x4b0
5016 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0
5018 #define S_CMFLOWCACHEDISABLE 0
5022 #define A_TP_PC_CONGESTION_CNTL 0x4b4
5033 #define M_ETHRESHOLD 0x3f
5038 #define M_CTHRESHOLD 0x3f
5042 #define S_TXTHRESHOLD 0
5043 #define M_TXTHRESHOLD 0x3f
5047 #define A_TP_TX_DROP_COUNT 0x4bc
5048 #define A_TP_CLEAR_DEBUG 0x4c0
5050 #define S_CLRDEBUG 0
5054 #define A_TP_DEBUG_VEC 0x4c4
5055 #define A_TP_DEBUG_VEC2 0x4c8
5056 #define A_TP_DEBUG_REG_SEL 0x4cc
5057 #define A_TP_DEBUG 0x4d0
5058 #define A_TP_DBG_LA_CONFIG 0x4d4
5059 #define A_TP_DBG_LA_DATAH 0x4d8
5060 #define A_TP_DBG_LA_DATAL 0x4dc
5061 #define A_TP_EMBED_OP_FIELD0 0x4e8
5062 #define A_TP_EMBED_OP_FIELD1 0x4ec
5063 #define A_TP_EMBED_OP_FIELD2 0x4f0
5064 #define A_TP_EMBED_OP_FIELD3 0x4f4
5065 #define A_TP_EMBED_OP_FIELD4 0x4f8
5066 #define A_TP_EMBED_OP_FIELD5 0x4fc
5067 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
5068 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
5069 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
5070 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
5071 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
5072 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
5073 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
5074 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
5075 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
5076 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
5077 #define A_TP_TX_TRC_KEY0 0x20
5078 #define A_TP_TX_TRC_MASK0 0x21
5079 #define A_TP_TX_TRC_KEY1 0x22
5080 #define A_TP_TX_TRC_MASK1 0x23
5081 #define A_TP_TX_TRC_KEY2 0x24
5082 #define A_TP_TX_TRC_MASK2 0x25
5083 #define A_TP_TX_TRC_KEY3 0x26
5084 #define A_TP_TX_TRC_MASK3 0x27
5085 #define A_TP_IPMI_CFG1 0x28
5103 #define S_VLAN 0
5104 #define M_VLAN 0xffff
5108 #define A_TP_IPMI_CFG2 0x29
5111 #define M_SECUREPORT 0xffff
5115 #define S_PRIMARYPORT 0
5116 #define M_PRIMARYPORT 0xffff
5120 #define A_TP_RX_TRC_KEY0 0x120
5121 #define A_TP_RX_TRC_MASK0 0x121
5122 #define A_TP_RX_TRC_KEY1 0x122
5123 #define A_TP_RX_TRC_MASK1 0x123
5124 #define A_TP_RX_TRC_KEY2 0x124
5125 #define A_TP_RX_TRC_MASK2 0x125
5126 #define A_TP_RX_TRC_KEY3 0x126
5127 #define A_TP_RX_TRC_MASK3 0x127
5128 #define A_TP_QOS_RX_TOS_MAP_H 0x128
5129 #define A_TP_QOS_RX_TOS_MAP_L 0x129
5130 #define A_TP_QOS_RX_MAP_MODE 0x12a
5137 #define M_RXMAPMODE 0x7
5145 #define A_TP_TX_DROP_CFG_CH0 0x12b
5156 #define M_TIMERTHRESHOLD 0x3ffffff
5160 #define S_PACKETDROPS 0
5161 #define M_PACKETDROPS 0xf
5165 #define A_TP_TX_DROP_CFG_CH1 0x12c
5166 #define A_TP_TX_DROP_CNT_CH0 0x12d
5169 #define M_TXDROPCNTCH0SENT 0xffff
5173 #define S_TXDROPCNTCH0RCVD 0
5174 #define M_TXDROPCNTCH0RCVD 0xffff
5178 #define A_TP_TX_DROP_CNT_CH1 0x12e
5181 #define M_TXDROPCNTCH1SENT 0xffff
5185 #define S_TXDROPCNTCH1RCVD 0
5186 #define M_TXDROPCNTCH1RCVD 0xffff
5190 #define A_TP_TX_DROP_MODE 0x12f
5196 #define S_TXDROPMODECH0 0
5200 #define A_TP_VLAN_PRI_MAP 0x137
5203 #define M_VLANPRIMAP7 0x3
5208 #define M_VLANPRIMAP6 0x3
5213 #define M_VLANPRIMAP5 0x3
5218 #define M_VLANPRIMAP4 0x3
5223 #define M_VLANPRIMAP3 0x3
5228 #define M_VLANPRIMAP2 0x3
5233 #define M_VLANPRIMAP1 0x3
5237 #define S_VLANPRIMAP0 0
5238 #define M_VLANPRIMAP0 0x3
5242 #define A_TP_MAC_MATCH_MAP0 0x138
5245 #define M_MACMATCHMAP7 0x7
5250 #define M_MACMATCHMAP6 0x7
5255 #define M_MACMATCHMAP5 0x7
5260 #define M_MACMATCHMAP4 0x7
5265 #define M_MACMATCHMAP3 0x7
5270 #define M_MACMATCHMAP2 0x7
5275 #define M_MACMATCHMAP1 0x7
5279 #define S_MACMATCHMAP0 0
5280 #define M_MACMATCHMAP0 0x7
5284 #define A_TP_MAC_MATCH_MAP1 0x139
5285 #define A_TP_INGRESS_CONFIG 0x141
5308 #define M_BITPOS3 0x3f
5313 #define M_BITPOS2 0x3f
5318 #define M_BITPOS1 0x3f
5322 #define S_BITPOS0 0
5323 #define M_BITPOS0 0x3f
5327 #define A_TP_PREAMBLE_MSB 0x142
5328 #define A_TP_PREAMBLE_LSB 0x143
5329 #define A_TP_EGRESS_CONFIG 0x145
5331 #define S_REWRITEFORCETOSIZE 0
5335 #define A_TP_INTF_FROM_TX_PKT 0x244
5337 #define S_INTFFROMTXPKT 0
5341 #define A_TP_FIFO_CONFIG 0x8c0
5344 #define M_RXFIFOCONFIG 0x3f
5349 #define M_TXFIFOCONFIG 0x3f
5354 #define ULP2_RX_BASE_ADDR 0x500
5356 #define A_ULPRX_CTL 0x500
5359 #define M_PCMD1THRESHOLD 0xff
5364 #define M_PCMD0THRESHOLD 0xff
5384 #define S_TDDPTAGTCB 0
5388 #define A_ULPRX_INT_ENABLE 0x504
5418 #define S_PARERRDATA 0
5422 #define S_PARERR 0
5426 #define A_ULPRX_INT_CAUSE 0x508
5427 #define A_ULPRX_ISCSI_LLIMIT 0x50c
5430 #define M_ISCSILLIMIT 0x3ffffff
5434 #define A_ULPRX_ISCSI_ULIMIT 0x510
5437 #define M_ISCSIULIMIT 0x3ffffff
5441 #define A_ULPRX_ISCSI_TAGMASK 0x514
5444 #define M_ISCSITAGMASK 0x3ffffff
5448 #define A_ULPRX_ISCSI_PSZ 0x518
5451 #define M_HPZ3 0xf
5456 #define M_HPZ2 0xf
5461 #define M_HPZ1 0xf
5465 #define S_HPZ0 0
5466 #define M_HPZ0 0xf
5470 #define A_ULPRX_TDDP_LLIMIT 0x51c
5473 #define M_TDDPLLIMIT 0x3ffffff
5477 #define A_ULPRX_TDDP_ULIMIT 0x520
5480 #define M_TDDPULIMIT 0x3ffffff
5484 #define A_ULPRX_TDDP_TAGMASK 0x524
5487 #define M_TDDPTAGMASK 0x3ffffff
5491 #define A_ULPRX_TDDP_PSZ 0x528
5492 #define A_ULPRX_STAG_LLIMIT 0x52c
5493 #define A_ULPRX_STAG_ULIMIT 0x530
5494 #define A_ULPRX_RQ_LLIMIT 0x534
5495 #define A_ULPRX_RQ_ULIMIT 0x538
5496 #define A_ULPRX_PBL_LLIMIT 0x53c
5497 #define A_ULPRX_PBL_ULIMIT 0x540
5500 #define ULP2_TX_BASE_ADDR 0x580
5502 #define A_ULPTX_CONFIG 0x580
5508 #define S_CFG_RR_ARB 0
5512 #define A_ULPTX_INT_ENABLE 0x584
5542 #define S_PBL_BOUND_ERR_CH0 0
5546 #define A_ULPTX_INT_CAUSE 0x588
5547 #define A_ULPTX_TPT_LLIMIT 0x58c
5548 #define A_ULPTX_TPT_ULIMIT 0x590
5549 #define A_ULPTX_PBL_LLIMIT 0x594
5550 #define A_ULPTX_PBL_ULIMIT 0x598
5551 #define A_ULPTX_CPL_ERR_OFFSET 0x59c
5552 #define A_ULPTX_CPL_ERR_MASK 0x5a0
5553 #define A_ULPTX_CPL_ERR_VALUE 0x5a4
5554 #define A_ULPTX_CPL_PACK_SIZE 0x5a8
5557 #define M_VALUE 0xff
5562 #define M_CH1SIZE2 0xff
5567 #define M_CH1SIZE1 0xff
5572 #define M_CH0SIZE2 0xff
5576 #define S_CH0SIZE1 0
5577 #define M_CH0SIZE1 0xff
5581 #define A_ULPTX_DMA_WEIGHT 0x5ac
5584 #define M_D1_WEIGHT 0xffff
5588 #define S_D0_WEIGHT 0
5589 #define M_D0_WEIGHT 0xffff
5594 #define PM1_RX_BASE_ADDR 0x5c0
5596 #define A_PM1_RX_CFG 0x5c0
5597 #define A_PM1_RX_MODE 0x5c4
5603 #define S_PRIORITY_CH 0
5607 #define A_PM1_RX_STAT_CONFIG 0x5c8
5608 #define A_PM1_RX_STAT_COUNT 0x5cc
5609 #define A_PM1_RX_STAT_MSB 0x5d0
5610 #define A_PM1_RX_STAT_LSB 0x5d4
5611 #define A_PM1_RX_INT_ENABLE 0x5d8
5666 #define M_IESPI_PAR_ERROR 0x7
5670 #define S_OCSPI_PAR_ERROR 0
5671 #define M_OCSPI_PAR_ERROR 0x7
5675 #define A_PM1_RX_INT_CAUSE 0x5dc
5678 #define PM1_TX_BASE_ADDR 0x5e0
5680 #define A_PM1_TX_CFG 0x5e0
5681 #define A_PM1_TX_MODE 0x5e4
5682 #define A_PM1_TX_STAT_CONFIG 0x5e8
5683 #define A_PM1_TX_STAT_COUNT 0x5ec
5684 #define A_PM1_TX_STAT_MSB 0x5f0
5685 #define A_PM1_TX_STAT_LSB 0x5f4
5686 #define A_PM1_TX_INT_ENABLE 0x5f8
5741 #define M_ICSPI_PAR_ERROR 0x7
5745 #define S_OESPI_PAR_ERROR 0
5746 #define M_OESPI_PAR_ERROR 0x7
5750 #define A_PM1_TX_INT_CAUSE 0x5fc
5753 #define MPS0_BASE_ADDR 0x600
5755 #define A_MPS_CFG 0x600
5762 #define M_SGETPQID 0x7
5794 #define S_PORT0ACTIVE 0
5798 #define A_MPS_DRR_CFG1 0x604
5801 #define M_RLDWTTPD1 0x7ff
5805 #define S_RLDWTTPD0 0
5806 #define M_RLDWTTPD0 0x7ff
5810 #define A_MPS_DRR_CFG2 0x608
5812 #define S_RLDWTTOTAL 0
5813 #define M_RLDWTTOTAL 0xfff
5817 #define A_MPS_MCA_STATUS 0x60c
5820 #define M_MCAPKTCNT 0xfffff
5824 #define S_MCADEPTH 0
5825 #define M_MCADEPTH 0xfff
5829 #define A_MPS_TX0_TP_CNT 0x610
5832 #define M_TX0TPDISCNT 0xff
5836 #define S_TX0TPCNT 0
5837 #define M_TX0TPCNT 0xffffff
5841 #define A_MPS_TX1_TP_CNT 0x614
5844 #define M_TX1TPDISCNT 0xff
5848 #define S_TX1TPCNT 0
5849 #define M_TX1TPCNT 0xffffff
5853 #define A_MPS_RX_TP_CNT 0x618
5856 #define M_RXTPDISCNT 0xff
5860 #define S_RXTPCNT 0
5861 #define M_RXTPCNT 0xffffff
5865 #define A_MPS_INT_ENABLE 0x61c
5868 #define M_MCAPARERRENB 0x7
5873 #define M_RXTPPARERRENB 0x3
5878 #define M_TX1TPPARERRENB 0x3
5882 #define S_TX0TPPARERRENB 0
5883 #define M_TX0TPPARERRENB 0x3
5887 #define A_MPS_INT_CAUSE 0x620
5890 #define M_MCAPARERR 0x7
5895 #define M_RXTPPARERR 0x3
5900 #define M_TX1TPPARERR 0x3
5904 #define S_TX0TPPARERR 0
5905 #define M_TX0TPPARERR 0x3
5910 #define CPL_SWITCH_BASE_ADDR 0x640
5912 #define A_CPL_SWITCH_CNTRL 0x640
5915 #define M_CPL_PKT_TID 0xffffff
5935 #define S_CIM_ENABLE 0
5939 #define A_CPL_SWITCH_TBL_IDX 0x644
5941 #define S_SWITCH_TBL_IDX 0
5942 #define M_SWITCH_TBL_IDX 0xf
5946 #define A_CPL_SWITCH_TBL_DATA 0x648
5947 #define A_CPL_SWITCH_ZERO_ERROR 0x64c
5949 #define S_ZERO_CMD 0
5950 #define M_ZERO_CMD 0xff
5954 #define A_CPL_INTR_ENABLE 0x650
5976 #define S_ZERO_SWITCH_ERROR 0
5980 #define A_CPL_INTR_CAUSE 0x654
5981 #define A_CPL_MAP_TBL_IDX 0x658
5983 #define S_CPL_MAP_TBL_IDX 0
5984 #define M_CPL_MAP_TBL_IDX 0xff
5988 #define A_CPL_MAP_TBL_DATA 0x65c
5990 #define S_CPL_MAP_TBL_DATA 0
5991 #define M_CPL_MAP_TBL_DATA 0xff
5996 #define SMB0_BASE_ADDR 0x660
5998 #define A_SMB_GLOBAL_TIME_CFG 0x660
6001 #define M_LADBGWRPTR 0xff
6006 #define M_LADBGRDPTR 0xff
6015 #define M_MACROCNTCFG 0x1f
6019 #define S_MICROCNTCFG 0
6020 #define M_MICROCNTCFG 0xff
6024 #define A_SMB_MST_TIMEOUT_CFG 0x664
6027 #define M_DEBUGSELH 0xf
6032 #define M_DEBUGSELL 0xf
6036 #define S_MSTTIMEOUTCFG 0
6037 #define M_MSTTIMEOUTCFG 0xffffff
6041 #define A_SMB_MST_CTL_CFG 0x668
6052 #define M_MSTRXBYTECFG 0x3f
6057 #define M_MSTTXBYTECFG 0x3f
6065 #define S_MSTCTLEN 0
6069 #define A_SMB_MST_CTL_STS 0x66c
6072 #define M_MSTRXBYTECNT 0x3f
6077 #define M_MSTTXBYTECNT 0x3f
6081 #define S_MSTBUSYSTS 0
6085 #define A_SMB_MST_TX_FIFO_RDWR 0x670
6086 #define A_SMB_MST_RX_FIFO_RDWR 0x674
6087 #define A_SMB_SLV_TIMEOUT_CFG 0x678
6089 #define S_SLVTIMEOUTCFG 0
6090 #define M_SLVTIMEOUTCFG 0xffffff
6094 #define A_SMB_SLV_CTL_CFG 0x67c
6105 #define M_SLVADDRCFG 0x7f
6117 #define S_SLVCTLEN 0
6121 #define A_SMB_SLV_CTL_STS 0x680
6124 #define M_SLVFIFOTXCNT 0x3f
6129 #define M_SLVFIFOCNT 0x3f
6137 #define S_SLVBUSYSTS 0
6141 #define A_SMB_SLV_FIFO_RDWR 0x684
6142 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688
6143 #define A_SMB_INT_ENABLE 0x68c
6173 #define S_MSTDONEINTEN 0
6177 #define A_SMB_INT_CAUSE 0x690
6207 #define S_MSTDONEINT 0
6211 #define A_SMB_DEBUG_DATA 0x694
6214 #define M_DEBUGDATAH 0xffff
6218 #define S_DEBUGDATAL 0
6219 #define M_DEBUGDATAL 0xffff
6223 #define A_SMB_DEBUG_LA 0x69c
6225 #define S_DEBUGLAREQADDR 0
6226 #define M_DEBUGLAREQADDR 0x3ff
6231 #define I2CM0_BASE_ADDR 0x6a0
6233 #define A_I2C_CFG 0x6a0
6235 #define S_I2C_CLKDIV 0
6236 #define M_I2C_CLKDIV 0xfff
6240 #define A_I2C_DATA 0x6a4
6241 #define A_I2C_OP 0x6a8
6247 #define S_I2C_DATA 0
6248 #define M_I2C_DATA 0xff
6264 #define S_I2C_RDWR 0
6266 #define F_I2C_READ V_I2C_RDWR(0U)
6270 #define MI1_BASE_ADDR 0x6b0
6272 #define A_MI1_CFG 0x6b0
6275 #define M_CLKDIV 0xff
6280 #define M_ST 0x3
6292 #define S_MDIEN 0
6296 #define A_MI1_ADDR 0x6b4
6299 #define M_PHYADDR 0x1f
6303 #define S_REGADDR 0
6304 #define M_REGADDR 0x1f
6308 #define A_MI1_DATA 0x6b8
6310 #define S_MDI_DATA 0
6311 #define M_MDI_DATA 0xffff
6315 #define A_MI1_OP 0x6bc
6321 #define S_MDI_OP 0
6322 #define M_MDI_OP 0x3
6327 #define JM1_BASE_ADDR 0x6c0
6329 #define A_JM_CFG 0x6c0
6332 #define M_JM_CLKDIV 0xff
6340 #define S_EN 0
6344 #define A_JM_MODE 0x6c4
6345 #define A_JM_DATA 0x6c8
6346 #define A_JM_OP 0x6cc
6348 #define S_CNT 0
6349 #define M_CNT 0x1f
6354 #define SF1_BASE_ADDR 0x6d8
6356 #define A_SF_DATA 0x6d8
6357 #define A_SF_OP 0x6dc
6360 #define M_BYTECNT 0x3
6365 #define PL3_BASE_ADDR 0x6e0
6367 #define A_PL_INT_ENABLE0 0x6e0
6457 #define S_SGE3 0
6461 #define A_PL_INT_CAUSE0 0x6e4
6462 #define A_PL_INT_ENABLE1 0x6e8
6463 #define A_PL_INT_CAUSE1 0x6ec
6464 #define A_PL_RST 0x6f0
6482 #define A_PL_REV 0x6f4
6484 #define S_REV 0
6485 #define M_REV 0xf
6489 #define A_PL_CLI 0x6f8
6490 #define A_PL_LCK 0x6fc
6492 #define S_LCK 0
6493 #define M_LCK 0x3
6498 #define MC5A_BASE_ADDR 0x700
6500 #define A_MC5_BUF_CONFIG 0x700
6559 #define M_MAN_PU 0x7
6564 #define M_MAN_PD 0x7
6569 #define M_CAL_PU 0x7
6574 #define M_CAL_PD 0x7
6579 #define M_SET_PU 0x7
6583 #define S_SET_PD 0
6584 #define M_SET_PD 0x7
6592 #define A_MC5_DB_CONFIG 0x704
6603 #define M_TMPARTSIZE 0x3
6608 #define M_TMTYPE 0x3
6613 #define M_TMPARTCOUNT 0x3
6618 #define M_NLIP 0x3f
6643 #define M_SYNMODE 0x3
6671 #define S_TMMODE 0
6675 #define A_MC5_MISC 0x708
6677 #define S_LIP_CMP_UNAVAILABLE 0
6678 #define M_LIP_CMP_UNAVAILABLE 0xf
6682 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
6684 #define S_RTINDX 0
6685 #define M_RTINDX 0x3fffff
6689 #define A_MC5_DB_FILTER_TABLE 0x710
6691 #define S_SRINDX 0
6692 #define M_SRINDX 0x3fffff
6696 #define A_MC5_DB_SERVER_INDEX 0x714
6697 #define A_MC5_DB_LIP_RAM_ADDR 0x718
6703 #define S_RAMADDR 0
6704 #define M_RAMADDR 0x3f
6708 #define A_MC5_DB_LIP_RAM_DATA 0x71c
6709 #define A_MC5_DB_RSP_LATENCY 0x720
6712 #define M_RDLAT 0x1f
6717 #define M_LRNLAT 0x1f
6721 #define S_SRCHLAT 0
6722 #define M_SRCHLAT 0x1f
6726 #define A_MC5_DB_PARITY_LATENCY 0x724
6728 #define S_PARLAT 0
6729 #define M_PARLAT 0xf
6733 #define A_MC5_DB_WR_LRN_VERIFY 0x728
6743 #define S_POVEREN 0
6747 #define A_MC5_DB_PART_ID_INDEX 0x72c
6749 #define S_IDINDEX 0
6750 #define M_IDINDEX 0xf
6754 #define A_MC5_DB_RESET_MAX 0x730
6756 #define S_RSTMAX 0
6757 #define M_RSTMAX 0xf
6761 #define A_MC5_DB_ACT_CNT 0x734
6763 #define S_ACTCNT 0
6764 #define M_ACTCNT 0xfffff
6768 #define A_MC5_DB_CLIP_MAP 0x738
6775 #define M_CLIPMAPVAL 0x3f
6779 #define S_CLIPMAPADDR 0
6780 #define M_CLIPMAPADDR 0x3f
6784 #define A_MC5_DB_SIZE 0x73c
6785 #define A_MC5_DB_INT_ENABLE 0x740
6788 #define M_MSGSEL 0xf
6852 #define S_ACTIVEOUTHIT 0
6856 #define A_MC5_DB_INT_CAUSE 0x744
6857 #define A_MC5_DB_INT_TID 0x748
6859 #define S_INTTID 0
6860 #define M_INTTID 0xfffff
6864 #define A_MC5_DB_INT_PTID 0x74c
6866 #define S_INTPTID 0
6867 #define M_INTPTID 0xfffff
6871 #define A_MC5_DB_DBGI_CONFIG 0x774
6874 #define M_WRREQSIZE 0x3ff
6882 #define S_CMDMODE 0
6883 #define M_CMDMODE 0x7
6887 #define A_MC5_DB_DBGI_REQ_CMD 0x778
6889 #define S_MBUSCMD 0
6890 #define M_MBUSCMD 0xf
6895 #define M_IDTCMDHI 0x7
6899 #define S_IDTCMDLO 0
6900 #define M_IDTCMDLO 0xf
6904 #define S_IDTCMD 0
6905 #define M_IDTCMD 0xfffff
6910 #define M_LCMDB 0x7ff
6914 #define S_LCMDA 0
6915 #define M_LCMDA 0x7ff
6919 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
6920 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
6921 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
6923 #define S_DBGIREQADRHI 0
6924 #define M_DBGIREQADRHI 0xff
6928 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
6929 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
6930 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
6931 #define A_MC5_DB_DBGI_REQ_DATA3 0x794
6932 #define A_MC5_DB_DBGI_REQ_DATA4 0x798
6934 #define S_DBGIREQDATA4 0
6935 #define M_DBGIREQDATA4 0xffff
6939 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c
6940 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0
6941 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4
6942 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8
6943 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac
6945 #define S_DBGIREQMSK4 0
6946 #define M_DBGIREQMSK4 0xffff
6950 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
6953 #define M_DBGIRSPMSG 0xf
6965 #define S_DBGIRSPVALID 0
6969 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
6970 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
6971 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
6972 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0
6973 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4
6975 #define S_DBGIRSPDATA3 0
6976 #define M_DBGIRSPDATA3 0xffff
6980 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8
6983 #define M_LASTCMDB 0x7ff
6987 #define S_LASTCMDA 0
6988 #define M_LASTCMDA 0x7ff
6992 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
6994 #define S_PO_DWR 0
6995 #define M_PO_DWR 0xfffff
6999 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
7001 #define S_PO_MWR 0
7002 #define M_PO_MWR 0xfffff
7006 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
7008 #define S_AO_SRCH 0
7009 #define M_AO_SRCH 0xfffff
7013 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
7015 #define S_AO_LRN 0
7016 #define M_AO_LRN 0xfffff
7020 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
7022 #define S_SYN_SRCH 0
7023 #define M_SYN_SRCH 0xfffff
7027 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
7029 #define S_SYN_LRN 0
7030 #define M_SYN_LRN 0xfffff
7034 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
7036 #define S_ACK_SRCH 0
7037 #define M_ACK_SRCH 0xfffff
7041 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
7043 #define S_ACK_LRN 0
7044 #define M_ACK_LRN 0xfffff
7048 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
7050 #define S_I_SRCH 0
7051 #define M_I_SRCH 0xfffff
7055 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
7057 #define S_E_SRCH 0
7058 #define M_E_SRCH 0xfffff
7062 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
7064 #define S_WRITE 0
7065 #define M_WRITE 0xfffff
7069 #define A_MC5_DB_DATA_READ_CMD 0x7f8
7071 #define S_READCMD 0
7072 #define M_READCMD 0xfffff
7076 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc
7078 #define S_MASKWR 0
7079 #define M_MASKWR 0xffff
7084 #define XGMAC0_0_BASE_ADDR 0x800
7086 #define A_XGM_TX_CTRL 0x800
7096 #define S_TXEN 0
7100 #define A_XGM_TX_CFG 0x804
7103 #define M_CFGCLKSPEED 0x7
7111 #define S_TXPAUSEEN 0
7115 #define A_XGM_TX_PAUSE_QUANTA 0x808
7117 #define S_TXPAUSEQUANTA 0
7118 #define M_TXPAUSEQUANTA 0xffff
7122 #define A_XGM_RX_CTRL 0x80c
7124 #define S_RXEN 0
7128 #define A_XGM_RX_CFG 0x810
7178 #define S_COPYALLFRAMES 0
7182 #define A_XGM_RX_HASH_LOW 0x814
7183 #define A_XGM_RX_HASH_HIGH 0x818
7184 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
7185 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
7187 #define S_ADDRESS_HIGH 0
7188 #define M_ADDRESS_HIGH 0xffff
7192 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
7193 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828
7194 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
7195 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830
7196 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
7197 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838
7198 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
7199 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840
7200 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
7201 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848
7202 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
7203 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850
7204 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
7205 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858
7206 #define A_XGM_RX_TYPE_MATCH_1 0x85c
7212 #define S_TYPE 0
7213 #define M_TYPE 0xffff
7217 #define A_XGM_RX_TYPE_MATCH_2 0x860
7218 #define A_XGM_RX_TYPE_MATCH_3 0x864
7219 #define A_XGM_RX_TYPE_MATCH_4 0x868
7220 #define A_XGM_INT_STATUS 0x86c
7262 #define S_FRAMERCVD 0
7266 #define A_XGM_XGM_INT_MASK 0x870
7267 #define A_XGM_XGM_INT_ENABLE 0x874
7268 #define A_XGM_XGM_INT_DISABLE 0x878
7269 #define A_XGM_TX_PAUSE_TIMER 0x87c
7271 #define S_CURPAUSETIMER 0
7272 #define M_CURPAUSETIMER 0xffff
7276 #define A_XGM_STAT_CTRL 0x880
7294 #define S_ENTESTMODEWR 0
7298 #define A_XGM_RXFIFO_CFG 0x884
7309 #define M_RXFIFOPAUSEHWM 0xfff
7314 #define M_RXFIFOPAUSELWM 0xfff
7334 #define S_DISERRFRAMES 0
7338 #define A_XGM_TXFIFO_CFG 0x888
7357 #define M_TXIPG 0xff
7362 #define M_TXFIFOTHRESH 0x1ff
7378 #define S_DISPREAMBLE 0
7382 #define A_XGM_SLOW_TIMER 0x88c
7388 #define S_PAUSESLOWTIMER 0
7389 #define M_PAUSESLOWTIMER 0xfffff
7393 #define A_XGM_PAUSE_TIMER 0x890
7395 #define S_PAUSETIMER 0
7396 #define M_PAUSETIMER 0xfffff
7400 #define A_XGM_SERDES_CTRL 0x890
7411 #define M_CMURANGE 0x7
7436 #define M_GAIN 0x1f
7441 #define M_BANDGAP 0xf
7446 #define M_LPBKEN 0x3
7458 #define A_XGM_XAUI_PCS_TEST 0x894
7461 #define M_TESTPATTERN 0x3
7465 #define S_ENTEST 0
7469 #define A_XGM_RGMII_CTRL 0x898
7472 #define M_PHALIGNFIFOTHRESH 0x3
7476 #define S_TXCLK90SHIFT 0
7480 #define A_XGM_RGMII_IMP 0x89c
7495 #define M_RGMIIIMPPD 0x7
7499 #define S_RGMIIIMPPU 0
7500 #define M_RGMIIIMPPU 0x7
7504 #define A_XGM_XAUI_IMP 0x8a0
7511 #define M_CALIMP 0x1f
7515 #define S_XAUIIMP 0
7516 #define M_XAUIIMP 0x7
7520 #define A_XGM_SERDES_BIST 0x8a4
7523 #define M_BISTDONE 0xf
7528 #define M_BISTCYCLETHRESH 0x1ffff
7532 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
7535 #define M_RXMAXFRAMERSIZE 0x3fff
7551 #define S_RXMAXPKTSIZE 0
7552 #define M_RXMAXPKTSIZE 0x3fff
7556 #define A_XGM_RESET_CTRL 0x8ac
7574 #define S_MAC_RESET_ 0
7578 #define A_XGM_XAUI1G_CTRL 0x8b0
7580 #define S_XAUI1GLINKID 0
7581 #define M_XAUI1GLINKID 0x3
7585 #define A_XGM_SERDES_LANE_CTRL 0x8b4
7592 #define M_TXPOLARITY 0xf
7596 #define S_RXPOLARITY 0
7597 #define M_RXPOLARITY 0xf
7601 #define A_XGM_PORT_CFG 0x8b8
7612 #define M_PORTSPEED 0x3
7616 #define S_ENRGMII 0
7620 #define A_XGM_EPIO_DATA0 0x8c0
7621 #define A_XGM_EPIO_DATA1 0x8c4
7622 #define A_XGM_EPIO_DATA2 0x8c8
7623 #define A_XGM_EPIO_DATA3 0x8cc
7624 #define A_XGM_EPIO_OP 0x8d0
7634 #define S_PIO_ADDRESS 0
7635 #define M_PIO_ADDRESS 0xff
7639 #define A_XGM_INT_ENABLE 0x8d4
7662 #define M_TXFIFO_PRTY_ERR 0x7
7667 #define M_RXFIFO_PRTY_ERR 0x7
7680 #define M_SERDESBISTERR 0xf
7685 #define M_SERDESLOWSIGCHANGE 0xf
7701 #define S_XGM_INT 0
7710 #define M_SERDESBIST_ERR 0xf
7715 #define M_SERDES_LOS 0xf
7719 #define A_XGM_INT_CAUSE 0x8d8
7720 #define A_XGM_XAUI_ACT_CTRL 0x8dc
7726 #define A_XGM_SERDES_CTRL0 0x8e0
7785 #define M_PW23 0x3
7790 #define M_PW01 0x3
7795 #define M_XGM_DEQ 0xf
7800 #define M_XGM_DTX 0xf
7808 #define S_XGM_HIDRV 0
7812 #define A_XGM_SERDES_CTRL1 0x8e4
7815 #define M_FMOFFSET3 0x1f
7824 #define M_FMOFFSET2 0x1f
7833 #define M_FMOFFSET1 0x1f
7842 #define M_FMOFFSET0 0x1f
7846 #define S_FMOFFSETEN0 0
7850 #define A_XGM_SERDES_CTRL2 0x8e8
7896 #define S_RXSLAVE0 0
7900 #define A_XGM_SERDES_CTRL3 0x8ec
7915 #define M_EXTBISTPAT3 0x7
7940 #define M_EXTBISTPAT2 0x7
7965 #define M_EXTBISTPAT1 0x7
7990 #define M_EXTBISTPAT0 0x7
7998 #define S_EXTPARLPBK0 0
8002 #define A_XGM_SERDES_STAT0 0x8f0
8005 #define M_EXTBISTCHKERRCNT0 0xffffff
8021 #define S_LOWSIG0 0
8025 #define A_XGM_SERDES_STAT1 0x8f4
8028 #define M_EXTBISTCHKERRCNT1 0xffffff
8044 #define S_LOWSIG1 0
8048 #define A_XGM_SERDES_STAT2 0x8f8
8051 #define M_EXTBISTCHKERRCNT2 0xffffff
8067 #define S_LOWSIG2 0
8071 #define A_XGM_SERDES_STAT3 0x8fc
8074 #define M_EXTBISTCHKERRCNT3 0xffffff
8090 #define S_LOWSIG3 0
8094 #define A_XGM_STAT_TX_BYTE_LOW 0x900
8095 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
8097 #define S_TXBYTES_HIGH 0
8098 #define M_TXBYTES_HIGH 0x1fff
8102 #define A_XGM_STAT_TX_FRAME_LOW 0x908
8103 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
8105 #define S_TXFRAMES_HIGH 0
8106 #define M_TXFRAMES_HIGH 0xf
8110 #define A_XGM_STAT_TX_BCAST 0x910
8111 #define A_XGM_STAT_TX_MCAST 0x914
8112 #define A_XGM_STAT_TX_PAUSE 0x918
8113 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
8114 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
8115 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
8116 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
8117 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
8118 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
8119 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
8120 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
8121 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
8122 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
8124 #define S_RXBYTES_HIGH 0
8125 #define M_RXBYTES_HIGH 0x1fff
8129 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
8130 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
8132 #define S_RXFRAMES_HIGH 0
8133 #define M_RXFRAMES_HIGH 0xf
8137 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
8138 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
8139 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
8141 #define S_RXPAUSEFRAMES 0
8142 #define M_RXPAUSEFRAMES 0xffff
8146 #define A_XGM_STAT_RX_64B_FRAMES 0x958
8147 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
8148 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
8149 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
8150 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
8151 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
8152 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
8153 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
8155 #define S_RXSHORTFRAMES 0
8156 #define M_RXSHORTFRAMES 0xffff
8160 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
8162 #define S_RXOVERSIZEFRAMES 0
8163 #define M_RXOVERSIZEFRAMES 0xffff
8167 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
8169 #define S_RXJABBERFRAMES 0
8170 #define M_RXJABBERFRAMES 0xffff
8174 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
8176 #define S_RXCRCERRFRAMES 0
8177 #define M_RXCRCERRFRAMES 0xffff
8181 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
8183 #define S_RXLENGTHERRFRAMES 0
8184 #define M_RXLENGTHERRFRAMES 0xffff
8188 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
8190 #define S_RXSYMCODEERRFRAMES 0
8191 #define M_RXSYMCODEERRFRAMES 0xffff
8195 #define A_XGM_SERDES_STATUS0 0x98c
8198 #define M_RXERRLANE3 0x7
8203 #define M_RXERRLANE2 0x7
8208 #define M_RXERRLANE1 0x7
8212 #define S_RXERRLANE0 0
8213 #define M_RXERRLANE0 0x7
8217 #define A_XGM_SERDES_STATUS1 0x990
8263 #define S_RXOFLOWLANE0 0
8267 #define A_XGM_SERDES_STATUS2 0x994
8313 #define S_RXADDSKIPLANE0 0
8317 #define A_XGM_XAUI_PCS_ERR 0x998
8320 #define M_PCS_SYNCSTATUS 0xf
8325 #define M_PCS_CTCFIFOERR 0xf
8329 #define S_PCS_NOTALIGNED 0
8333 #define A_XGM_RGMII_STATUS 0x99c
8340 #define M_GMIISPEED 0x3
8344 #define S_GMIILINKSTATUS 0
8348 #define A_XGM_WOL_STATUS 0x9a0
8354 #define S_MATCHEDFILTER 0
8355 #define M_MATCHEDFILTER 0x7
8359 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
8360 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
8363 #define M_TXSPI4SOPCNT 0xffff
8367 #define S_TXSPI4EOPCNT 0
8368 #define M_TXSPI4EOPCNT 0xffff
8372 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
8375 #define M_RXSPI4SOPCNT 0xffff
8379 #define S_RXSPI4EOPCNT 0
8380 #define M_RXSPI4EOPCNT 0xffff
8385 #define XGMAC0_1_BASE_ADDR 0xa00