1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2004-2005 Nate Lawson (SDG)
47  * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
49  * the newer Pentium-M SpeedStep feature.  It offers only two levels of
51  * SMM code during the power-on process (i.e., choose a lower level if the
57 	int		 bm_rid;	/* Bus-mastering control (PM2REG). */
64 /* Supported PCI IDs. */
154 	 * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0.  in ichss_identify()
157 	 * I/O Controller Hub 2 Mobile (ICH2-M).  in ichss_identify()
234 	return (-1000);  in ichss_probe()
244 	sc->dev = dev;  in ichss_attach()
246 	sc->bm_rid = 0;  in ichss_attach()
247 	sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,  in ichss_attach()
249 	if (sc->bm_reg == NULL) {  in ichss_attach()
253 	sc->ctrl_rid = 1;  in ichss_attach()
254 	sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,  in ichss_attach()
255 	    &sc->ctrl_rid, RF_ACTIVE);  in ichss_attach()
256 	if (sc->ctrl_reg == NULL) {  in ichss_attach()
258 		bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,  in ichss_attach()
259 		    sc->bm_reg);  in ichss_attach()
272 	sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;  in ichss_attach()
273 	sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;  in ichss_attach()
274 	sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;  in ichss_attach()
275 	sc->sets[0].lat = 1000;  in ichss_attach()
276 	sc->sets[0].dev = dev;  in ichss_attach()
277 	sc->sets[1] = sc->sets[0];  in ichss_attach()
286 	/* TODO: teardown BM and CTRL registers. */  in ichss_detach()
311 		if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {  in ichss_settings()
313 			ichss_set(dev, &sc->sets[i]);  in ichss_settings()
314 			ichss_set(dev, &sc->sets[first]);  in ichss_settings()
318 	bcopy(sc->sets, sets, sizeof(sc->sets));  in ichss_settings()
334 	if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))  in ichss_set()
336 	else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))  in ichss_set()
344 	old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;  in ichss_set()
348 	 * register, and then re-enable bus master arbitration.  in ichss_set()
350 	bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;  in ichss_set()
351 	ICH_SET_REG(sc->bm_reg, bmval);  in ichss_set()
352 	ICH_SET_REG(sc->ctrl_reg, old_val | req_val);  in ichss_set()
353 	ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);  in ichss_set()
355 	/* Get the new value and re-enable interrupts. */  in ichss_set()
356 	new_val = ICH_GET_REG(sc->ctrl_reg);  in ichss_set()
361 	    device_printf(sc->dev, "transition to %d failed\n", req_val);  in ichss_set()
365 	/* Re-initialize our cycle counter if we don't know this new state. */  in ichss_set()
366 	if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {  in ichss_set()
368 		sc->sets[req_val].freq = rate / 1000000;  in ichss_set()
370 		    sc->sets[req_val].freq);  in ichss_set()
384 	state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;  in ichss_get()
387 	if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {  in ichss_get()
389 		sc->sets[state].freq = rate / 1000000;  in ichss_get()
391 		    sc->sets[state].freq);  in ichss_get()
393 	*set = sc->sets[state];  in ichss_get()