Lines Matching +full:mode +full:- +full:reg
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
79 if ((sc->flags & RK_CLK_PLL_HAVE_GATE) == 0) in rk_clk_pll_set_gate()
84 val |= 1 << sc->gate_shift; in rk_clk_pll_set_gate()
85 dprintf("sc->gate_shift: %x\n", sc->gate_shift); in rk_clk_pll_set_gate()
86 val |= (1 << sc->gate_shift) << RK_CLK_PLL_MASK_SHIFT; in rk_clk_pll_set_gate()
87 dprintf("Write: gate_offset=%x, val=%x\n", sc->gate_offset, val); in rk_clk_pll_set_gate()
89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
123 uint32_t reg; in rk3066_clk_pll_init() local
128 READ4(clk, sc->mode_reg, ®); in rk3066_clk_pll_init()
131 reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; in rk3066_clk_pll_init()
132 clknode_init_parent_idx(clk, reg); in rk3066_clk_pll_init()
140 uint32_t reg; in rk3066_clk_pll_set_mux() local
145 reg = (idx & RK3066_CLK_PLL_MODE_MASK) << sc->mode_shift; in rk3066_clk_pll_set_mux()
146 reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_mux()
150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
161 uint32_t raw0, raw1, raw2, reg; in rk3066_clk_pll_recalc() local
167 READ4(clk, sc->base_offset, &raw0); in rk3066_clk_pll_recalc()
168 READ4(clk, sc->base_offset + 4, &raw1); in rk3066_clk_pll_recalc()
169 READ4(clk, sc->base_offset + 8, &raw2); in rk3066_clk_pll_recalc()
170 READ4(clk, sc->mode_reg, ®); in rk3066_clk_pll_recalc()
174 reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; in rk3066_clk_pll_recalc()
176 if (reg != RK3066_CLK_PLL_MODE_NORMAL) in rk3066_clk_pll_recalc()
208 uint32_t reg; in rk3066_clk_pll_set_freq() local
213 if (sc->rates == NULL) in rk3066_clk_pll_set_freq()
216 for (rates = sc->rates; rates->freq; rates++) { in rk3066_clk_pll_set_freq()
217 if (rates->freq == *fout) in rk3066_clk_pll_set_freq()
220 if (rates->freq == 0) { in rk3066_clk_pll_set_freq()
227 /* Setting to slow mode during frequency change */ in rk3066_clk_pll_set_freq()
228 reg = (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_freq()
230 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3066_clk_pll_set_freq()
231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
234 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | in rk3066_clk_pll_set_freq()
238 reg = 0; in rk3066_clk_pll_set_freq()
239 reg |= RK3066_CLK_PLL_POSTDIV_MASK << 16; in rk3066_clk_pll_set_freq()
240 reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT; in rk3066_clk_pll_set_freq()
242 reg |= RK3066_CLK_PLL_REFDIV_MASK << 16; in rk3066_clk_pll_set_freq()
243 reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT; in rk3066_clk_pll_set_freq()
245 dprintf("Set PLL_CON0 to %x\n", reg); in rk3066_clk_pll_set_freq()
246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
250 READ4(clk, sc->base_offset + 4, ®); in rk3066_clk_pll_set_freq()
251 reg &= ~RK3066_CLK_PLL_FBDIV_MASK; in rk3066_clk_pll_set_freq()
252 reg |= RK3066_CLK_PLL_FBDIV_MASK << 16; in rk3066_clk_pll_set_freq()
253 reg = (rates->fbdiv - 1) << RK3066_CLK_PLL_FBDIV_SHIFT; in rk3066_clk_pll_set_freq()
255 dprintf("Set PLL_CON1 to %x\n", reg); in rk3066_clk_pll_set_freq()
256 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
259 reg = rates->bwadj - 1; in rk3066_clk_pll_set_freq()
260 dprintf("Set PLL_CON2 to %x (%x)\n", reg, rates->bwadj); in rk3066_clk_pll_set_freq()
261 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
264 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
269 for (timeout = 1000; timeout >= 0; timeout--) { in rk3066_clk_pll_set_freq()
270 READ4(clk, sc->base_offset + 0x4, ®); in rk3066_clk_pll_set_freq()
271 if ((reg & RK3066_CLK_PLL_LOCK_MASK) != 0) in rk3066_clk_pll_set_freq()
279 "%s - Timedout while waiting for lock.\n", in rk3066_clk_pll_set_freq()
281 dprintf("PLL_CON1: %x\n", reg); in rk3066_clk_pll_set_freq()
285 /* Set back to normal mode */ in rk3066_clk_pll_set_freq()
286 reg = (RK3066_CLK_PLL_MODE_NORMAL << sc->mode_shift); in rk3066_clk_pll_set_freq()
287 reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_freq()
289 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3066_clk_pll_set_freq()
290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
318 &clkdef->clkdef); in rk3066_clk_pll_register()
324 sc->base_offset = clkdef->base_offset; in rk3066_clk_pll_register()
325 sc->gate_offset = clkdef->gate_offset; in rk3066_clk_pll_register()
326 sc->gate_shift = clkdef->gate_shift; in rk3066_clk_pll_register()
327 sc->mode_reg = clkdef->mode_reg; in rk3066_clk_pll_register()
328 sc->mode_shift = clkdef->mode_shift; in rk3066_clk_pll_register()
329 sc->flags = clkdef->flags; in rk3066_clk_pll_register()
330 sc->rates = clkdef->rates; in rk3066_clk_pll_register()
331 sc->frac_rates = clkdef->frac_rates; in rk3066_clk_pll_register()
389 READ4(clk, sc->base_offset, &raw1); in rk3328_clk_pll_recalc()
390 READ4(clk, sc->base_offset + 4, &raw2); in rk3328_clk_pll_recalc()
391 READ4(clk, sc->base_offset + 8, &raw3); in rk3328_clk_pll_recalc()
406 /* Fractional mode */ in rk3328_clk_pll_recalc()
427 uint32_t reg; in rk3328_clk_pll_set_freq() local
432 if (sc->rates) in rk3328_clk_pll_set_freq()
433 rates = sc->rates; in rk3328_clk_pll_set_freq()
434 else if (sc->frac_rates) in rk3328_clk_pll_set_freq()
435 rates = sc->frac_rates; in rk3328_clk_pll_set_freq()
439 for (; rates->freq; rates++) { in rk3328_clk_pll_set_freq()
440 if (rates->freq == *fout) in rk3328_clk_pll_set_freq()
443 if (rates->freq == 0) { in rk3328_clk_pll_set_freq()
450 /* Setting to slow mode during frequency change */ in rk3328_clk_pll_set_freq()
451 reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3328_clk_pll_set_freq()
453 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3328_clk_pll_set_freq()
454 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
457 reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) | in rk3328_clk_pll_set_freq()
458 (rates->fbdiv << RK3328_CLK_PLL_FBDIV_SHIFT); in rk3328_clk_pll_set_freq()
459 reg |= (RK3328_CLK_PLL_POSTDIV1_MASK | RK3328_CLK_PLL_FBDIV_MASK) << 16; in rk3328_clk_pll_set_freq()
460 dprintf("Set PLL_CON0 to %x\n", reg); in rk3328_clk_pll_set_freq()
461 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq()
464 reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) | in rk3328_clk_pll_set_freq()
465 (rates->postdiv2 << RK3328_CLK_PLL_POSTDIV2_SHIFT) | in rk3328_clk_pll_set_freq()
466 (rates->refdiv << RK3328_CLK_PLL_REFDIV_SHIFT); in rk3328_clk_pll_set_freq()
467 reg |= (RK3328_CLK_PLL_DSMPD_MASK | in rk3328_clk_pll_set_freq()
470 dprintf("Set PLL_CON1 to %x\n", reg); in rk3328_clk_pll_set_freq()
471 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3328_clk_pll_set_freq()
474 READ4(clk, sc->base_offset + 0x8, ®); in rk3328_clk_pll_set_freq()
475 reg &= ~RK3328_CLK_PLL_FRAC_MASK; in rk3328_clk_pll_set_freq()
476 reg |= rates->frac << RK3328_CLK_PLL_FRAC_SHIFT; in rk3328_clk_pll_set_freq()
477 dprintf("Set PLL_CON2 to %x\n", reg); in rk3328_clk_pll_set_freq()
478 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3328_clk_pll_set_freq()
481 for (timeout = 1000; timeout; timeout--) { in rk3328_clk_pll_set_freq()
482 READ4(clk, sc->base_offset + 0x4, ®); in rk3328_clk_pll_set_freq()
483 if ((reg & RK3328_CLK_PLL_LOCK_MASK) == 0) in rk3328_clk_pll_set_freq()
488 /* Set back to normal mode */ in rk3328_clk_pll_set_freq()
489 reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift); in rk3328_clk_pll_set_freq()
490 reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3328_clk_pll_set_freq()
492 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3328_clk_pll_set_freq()
493 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
520 &clkdef->clkdef); in rk3328_clk_pll_register()
526 sc->base_offset = clkdef->base_offset; in rk3328_clk_pll_register()
527 sc->gate_offset = clkdef->gate_offset; in rk3328_clk_pll_register()
528 sc->gate_shift = clkdef->gate_shift; in rk3328_clk_pll_register()
529 sc->mode_reg = clkdef->mode_reg; in rk3328_clk_pll_register()
530 sc->mode_shift = clkdef->mode_shift; in rk3328_clk_pll_register()
531 sc->flags = clkdef->flags; in rk3328_clk_pll_register()
532 sc->rates = clkdef->rates; in rk3328_clk_pll_register()
533 sc->frac_rates = clkdef->frac_rates; in rk3328_clk_pll_register()
592 uint32_t mode; in rk3399_clk_pll_recalc() local
596 READ4(clk, sc->base_offset, &con1); in rk3399_clk_pll_recalc()
597 READ4(clk, sc->base_offset + 4, &con2); in rk3399_clk_pll_recalc()
598 READ4(clk, sc->base_offset + 8, &con3); in rk3399_clk_pll_recalc()
599 READ4(clk, sc->base_offset + 0xC, &con4); in rk3399_clk_pll_recalc()
603 * if we are in slow mode the output freq in rk3399_clk_pll_recalc()
605 * if we are in deep mode the output freq is 32.768khz in rk3399_clk_pll_recalc()
607 mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT; in rk3399_clk_pll_recalc()
608 if (mode == RK3399_CLK_PLL_MODE_SLOW) { in rk3399_clk_pll_recalc()
609 dprintf("pll in slow mode, con4=%x\n", con4); in rk3399_clk_pll_recalc()
611 } else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) { in rk3399_clk_pll_recalc()
648 /* Fractional mode */ in rk3399_clk_pll_recalc()
651 /* Integer mode */ in rk3399_clk_pll_recalc()
668 uint32_t reg; in rk3399_clk_pll_set_freq() local
673 if (sc->rates) in rk3399_clk_pll_set_freq()
674 rates = sc->rates; in rk3399_clk_pll_set_freq()
675 else if (sc->frac_rates) in rk3399_clk_pll_set_freq()
676 rates = sc->frac_rates; in rk3399_clk_pll_set_freq()
680 for (; rates->freq; rates++) { in rk3399_clk_pll_set_freq()
681 if (rates->freq == *fout) in rk3399_clk_pll_set_freq()
684 if (rates->freq == 0) { in rk3399_clk_pll_set_freq()
691 /* Set to slow mode during frequency change */ in rk3399_clk_pll_set_freq()
692 reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT; in rk3399_clk_pll_set_freq()
693 reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
694 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
697 reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT; in rk3399_clk_pll_set_freq()
698 reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
699 WRITE4(clk, sc->base_offset, reg); in rk3399_clk_pll_set_freq()
702 reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT; in rk3399_clk_pll_set_freq()
703 reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT; in rk3399_clk_pll_set_freq()
704 reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT; in rk3399_clk_pll_set_freq()
705 reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK | in rk3399_clk_pll_set_freq()
707 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3399_clk_pll_set_freq()
710 READ4(clk, sc->base_offset + 0x8, ®); in rk3399_clk_pll_set_freq()
711 reg &= ~RK3399_CLK_PLL_FRAC_MASK; in rk3399_clk_pll_set_freq()
712 reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT; in rk3399_clk_pll_set_freq()
713 WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK); in rk3399_clk_pll_set_freq()
716 reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT; in rk3399_clk_pll_set_freq()
717 reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
718 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
721 for (timeout = 1000; timeout; timeout--) { in rk3399_clk_pll_set_freq()
722 READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, ®); in rk3399_clk_pll_set_freq()
723 if ((reg & RK3399_CLK_PLL_LOCK_MASK) == 0) in rk3399_clk_pll_set_freq()
728 /* Set back to normal mode */ in rk3399_clk_pll_set_freq()
729 reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; in rk3399_clk_pll_set_freq()
730 reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
731 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
758 &clkdef->clkdef); in rk3399_clk_pll_register()
764 sc->base_offset = clkdef->base_offset; in rk3399_clk_pll_register()
765 sc->gate_offset = clkdef->gate_offset; in rk3399_clk_pll_register()
766 sc->gate_shift = clkdef->gate_shift; in rk3399_clk_pll_register()
767 sc->flags = clkdef->flags; in rk3399_clk_pll_register()
768 sc->rates = clkdef->rates; in rk3399_clk_pll_register()
769 sc->frac_rates = clkdef->frac_rates; in rk3399_clk_pll_register()