Lines Matching full:clk

32 #include <dev/clk/clk.h>
34 #include <dev/clk/rockchip/rk_clk_pll.h>
66 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
72 rk_clk_pll_set_gate(struct clknode *clk, bool enable) in rk_clk_pll_set_gate() argument
77 sc = clknode_get_softc(clk); in rk_clk_pll_set_gate()
88 DEVICE_LOCK(clk); in rk_clk_pll_set_gate()
89 WRITE4(clk, sc->gate_offset, val); in rk_clk_pll_set_gate()
90 DEVICE_UNLOCK(clk); in rk_clk_pll_set_gate()
120 rk3066_clk_pll_init(struct clknode *clk, device_t dev) in rk3066_clk_pll_init() argument
125 sc = clknode_get_softc(clk); in rk3066_clk_pll_init()
127 DEVICE_LOCK(clk); in rk3066_clk_pll_init()
128 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_init()
129 DEVICE_UNLOCK(clk); in rk3066_clk_pll_init()
132 clknode_init_parent_idx(clk, reg); in rk3066_clk_pll_init()
138 rk3066_clk_pll_set_mux(struct clknode *clk, int idx) in rk3066_clk_pll_set_mux() argument
143 sc = clknode_get_softc(clk); in rk3066_clk_pll_set_mux()
149 DEVICE_LOCK(clk); in rk3066_clk_pll_set_mux()
150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
151 DEVICE_UNLOCK(clk); in rk3066_clk_pll_set_mux()
156 rk3066_clk_pll_recalc(struct clknode *clk, uint64_t *freq) in rk3066_clk_pll_recalc() argument
163 sc = clknode_get_softc(clk); in rk3066_clk_pll_recalc()
165 DEVICE_LOCK(clk); in rk3066_clk_pll_recalc()
167 READ4(clk, sc->base_offset, &raw0); in rk3066_clk_pll_recalc()
168 READ4(clk, sc->base_offset + 4, &raw1); in rk3066_clk_pll_recalc()
169 READ4(clk, sc->base_offset + 8, &raw2); in rk3066_clk_pll_recalc()
170 READ4(clk, sc->mode_reg, &reg); in rk3066_clk_pll_recalc()
172 DEVICE_UNLOCK(clk); in rk3066_clk_pll_recalc()
203 rk3066_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, in rk3066_clk_pll_set_freq() argument
211 sc = clknode_get_softc(clk); in rk3066_clk_pll_set_freq()
225 DEVICE_LOCK(clk); in rk3066_clk_pll_set_freq()
231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
234 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | in rk3066_clk_pll_set_freq()
246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
250 READ4(clk, sc->base_offset + 4, &reg); in rk3066_clk_pll_set_freq()
256 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
261 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
264 WRITE4(clk, sc->base_offset + 12, in rk3066_clk_pll_set_freq()
270 READ4(clk, sc->base_offset + 0x4, &reg); in rk3066_clk_pll_set_freq()
278 device_printf(clknode_get_device(clk), in rk3066_clk_pll_set_freq()
280 clknode_get_name(clk)); in rk3066_clk_pll_set_freq()
290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
292 DEVICE_UNLOCK(clk); in rk3066_clk_pll_set_freq()
294 rv = clknode_set_parent_by_idx(clk, 1); in rk3066_clk_pll_set_freq()
314 struct clknode *clk; in rk3066_clk_pll_register() local
317 clk = clknode_create(clkdom, &rk3066_clk_pll_clknode_class, in rk3066_clk_pll_register()
319 if (clk == NULL) in rk3066_clk_pll_register()
322 sc = clknode_get_softc(clk); in rk3066_clk_pll_register()
333 clknode_register(clkdom, clk); in rk3066_clk_pll_register()
369 rk3328_clk_pll_init(struct clknode *clk, device_t dev) in rk3328_clk_pll_init() argument
371 clknode_init_parent_idx(clk, 0); in rk3328_clk_pll_init()
377 rk3328_clk_pll_recalc(struct clknode *clk, uint64_t *freq) in rk3328_clk_pll_recalc() argument
385 sc = clknode_get_softc(clk); in rk3328_clk_pll_recalc()
387 DEVICE_LOCK(clk); in rk3328_clk_pll_recalc()
389 READ4(clk, sc->base_offset, &raw1); in rk3328_clk_pll_recalc()
390 READ4(clk, sc->base_offset + 4, &raw2); in rk3328_clk_pll_recalc()
391 READ4(clk, sc->base_offset + 8, &raw3); in rk3328_clk_pll_recalc()
402 DEVICE_UNLOCK(clk); in rk3328_clk_pll_recalc()
422 rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, in rk3328_clk_pll_set_freq() argument
430 sc = clknode_get_softc(clk); in rk3328_clk_pll_set_freq()
448 DEVICE_LOCK(clk); in rk3328_clk_pll_set_freq()
454 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
461 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq()
471 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3328_clk_pll_set_freq()
474 READ4(clk, sc->base_offset + 0x8, &reg); in rk3328_clk_pll_set_freq()
478 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3328_clk_pll_set_freq()
482 READ4(clk, sc->base_offset + 0x4, &reg); in rk3328_clk_pll_set_freq()
493 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
495 DEVICE_UNLOCK(clk); in rk3328_clk_pll_set_freq()
516 struct clknode *clk; in rk3328_clk_pll_register() local
519 clk = clknode_create(clkdom, &rk3328_clk_pll_clknode_class, in rk3328_clk_pll_register()
521 if (clk == NULL) in rk3328_clk_pll_register()
524 sc = clknode_get_softc(clk); in rk3328_clk_pll_register()
535 clknode_register(clkdom, clk); in rk3328_clk_pll_register()
577 rk3399_clk_pll_init(struct clknode *clk, device_t dev) in rk3399_clk_pll_init() argument
579 clknode_init_parent_idx(clk, 0); in rk3399_clk_pll_init()
585 rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq) in rk3399_clk_pll_recalc() argument
593 sc = clknode_get_softc(clk); in rk3399_clk_pll_recalc()
595 DEVICE_LOCK(clk); in rk3399_clk_pll_recalc()
596 READ4(clk, sc->base_offset, &con1); in rk3399_clk_pll_recalc()
597 READ4(clk, sc->base_offset + 4, &con2); in rk3399_clk_pll_recalc()
598 READ4(clk, sc->base_offset + 8, &con3); in rk3399_clk_pll_recalc()
599 READ4(clk, sc->base_offset + 0xC, &con4); in rk3399_clk_pll_recalc()
600 DEVICE_UNLOCK(clk); in rk3399_clk_pll_recalc()
663 rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, in rk3399_clk_pll_set_freq() argument
671 sc = clknode_get_softc(clk); in rk3399_clk_pll_set_freq()
689 DEVICE_LOCK(clk); in rk3399_clk_pll_set_freq()
694 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
699 WRITE4(clk, sc->base_offset, reg); in rk3399_clk_pll_set_freq()
707 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3399_clk_pll_set_freq()
710 READ4(clk, sc->base_offset + 0x8, &reg); in rk3399_clk_pll_set_freq()
713 WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK); in rk3399_clk_pll_set_freq()
718 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
722 READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, &reg); in rk3399_clk_pll_set_freq()
731 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
733 DEVICE_UNLOCK(clk); in rk3399_clk_pll_set_freq()
754 struct clknode *clk; in rk3399_clk_pll_register() local
757 clk = clknode_create(clkdom, &rk3399_clk_pll_clknode_class, in rk3399_clk_pll_register()
759 if (clk == NULL) in rk3399_clk_pll_register()
762 sc = clknode_get_softc(clk); in rk3399_clk_pll_register()
771 clknode_register(clkdom, clk); in rk3399_clk_pll_register()