Lines Matching +full:pmu +full:- +full:gate
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h>
163 GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0),
164 GATE(CLK_RTC_32K, "clk_rtc_32k", "clk_rtc_32k_mux", 0, 1),
165 GATE(PCLK_PDPMU, "pclk_pdpmu", "pclk_pdpmu_pre", 0, 2),
166 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6),
167 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
170 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0),
171 GATE(CLK_I2C0, "clk_i2c0", "clk_i2c0_div", 1, 1),
172 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),
173 GATE(CLK_UART0_DIV, "sclk_uart0_div", "sclk_uart0_div_div", 1, 3),
174 GATE(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_frac_div", 1, 4),
175 GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 1, 5),
176 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 1, 6),
177 GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_div", 1, 7),
178 GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 1, 8),
179 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 1, 9),
180 GATE(DBCLK_GPIO0, "dbclk_gpio0", "dbclk_gpio0_sel", 1, 10),
181 GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 1, 11),
182 GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12),
183 GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 1, 13),
186 GATE(CLK_REF24M, "clk_ref24m", "clk_ref24m_div", 2, 0),
187 GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 2, 1),
188 GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 2, 2),
189 GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 2, 3),
190 GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 2, 4),
191 GATE(CLK_WIFI_DIV, "clk_wifi_div", "clk_wifi_div_div", 2, 5),
192 GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 2, 6),
193 GATE(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "clk_pciephy0_div_div", 2, 7),
194 GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 2, 8),
195 GATE(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "clk_pciephy1_div_div", 2, 9),
196 GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 2, 10),
197 GATE(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "clk_pciephy2_div_div", 2, 11),
198 GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 2, 12),
199 GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 2, 13),
200 GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 2, 14),
201 GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 2, 15),
211 if (ofw_bus_is_compatible(dev, "rockchip,rk3568-pmucru")) { in rk3568_pmucru_probe()
212 device_set_desc(dev, "Rockchip RK3568 PMU Clock & Reset Unit"); in rk3568_pmucru_probe()
225 sc->dev = dev; in rk3568_pmucru_attach()
226 sc->clks = rk3568_clks; in rk3568_pmucru_attach()
227 sc->nclks = nitems(rk3568_clks); in rk3568_pmucru_attach()
228 sc->gates = rk3568_gates; in rk3568_pmucru_attach()
229 sc->ngates = nitems(rk3568_gates); in rk3568_pmucru_attach()
230 sc->reset_offset = 0x200; in rk3568_pmucru_attach()
231 sc->reset_num = 4; in rk3568_pmucru_attach()