Lines Matching refs:PLIST

165 PLIST(mux_pll_p) = { "xin24m" };
166 PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
167 PLIST(mux_armclk_p) = { "apll", "gpll" };
168 PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac",
170 PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac",
172 PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac",
174 PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac",
176 PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac",
178 PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac",
180 PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac",
182 PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" };
183 PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" };
184 PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
185 PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
186 PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
187 PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
188 PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
189 PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
190 PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
191 PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
192 PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
193 PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" };
194 PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" };
195 PLIST(npll_gpll_p) = { "npll", "gpll" };
196 PLIST(cpll_gpll_p) = { "cpll", "gpll" };
197 PLIST(gpll_cpll_p) = { "gpll", "cpll" };
198 PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" };
199 PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" };
200 PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" };
201 PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_…
203 PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" };
204 PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"};
205 PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" };
206 PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" };
207 PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" };
208 PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m",
210 PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" };
211 PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" };
212 PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" };
213 PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" };
214 PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" };
215 PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" };
216 PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" };
217 PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" };
218 PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_…
219 PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
220 PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" …
221 PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" …
222 PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" };
223 PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m",
225 PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" …
226 PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m",
228 PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" };
229 PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" };
230 PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m",
232 PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m",
234 PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25…
236 PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" };
237 PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" …
238 PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
239 PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" };
240 PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m",
242 PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" };
243 PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" };
244 PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" …
245 PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50…
247 PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" };
248 PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" };
249 PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" };
250 PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" };
251 PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
252 PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m",
254 PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m",
256 PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" };
257 PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" };
258 PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0",
260 PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" };
261 PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed",
263 PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" };
264 PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1",
266 PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" };
267 PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed",
269 PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" };
270 PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" };
271 PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" };