Lines Matching +full:pmu +full:- +full:gate
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
94 GATE(SCLK_SPI3_PMU, "clk_spi3_pmu", "clk_spi3_c", 0, 2),
95 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_sel", 0, 3),
96 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_sel", 0, 4),
97 GATE(SCLK_UART4_PMU, "clk_uart4_pmu", "clk_uart4_sel", 0, 5),
98 GATE(0, "clk_uart4_frac", "clk_uart4_frac_frac", 0, 6),
100 GATE(SCLK_WIFI_PMU, "clk_wifi_pmu", "clk_wifi_sel", 0, 8),
101 GATE(SCLK_I2C0_PMU, "clk_i2c0_src", "clk_i2c0_div", 0, 9),
102 GATE(SCLK_I2C4_PMU, "clk_i2c4_src", "clk_i2c4_div", 0, 10),
103 GATE(SCLK_I2C8_PMU, "clk_i2c8_src", "clk_i2c8_div", 0, 11),
107 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 1, 0),
110 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 1, 3),
111 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 1, 4),
114 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 1, 7),
115 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 1, 8),
116 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 1, 9),
117 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 1, 10),
118 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 1, 11),
119 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 1, 12),
120 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 1, 13),
833 if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) { in rk3399_pmucru_probe()
834 device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit"); in rk3399_pmucru_probe()
847 sc->dev = dev; in rk3399_pmucru_attach()
849 sc->gates = rk3399_pmu_gates; in rk3399_pmucru_attach()
850 sc->ngates = nitems(rk3399_pmu_gates); in rk3399_pmucru_attach()
852 sc->clks = rk3399_pmu_clks; in rk3399_pmucru_attach()
853 sc->nclks = nitems(rk3399_pmu_clks); in rk3399_pmucru_attach()
855 sc->reset_offset = 0x110; in rk3399_pmucru_attach()
856 sc->reset_num = 30; in rk3399_pmucru_attach()