Lines Matching +full:7 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
265 /* Bit 13-15 unused */
268 /* Bit 0 unused */
275 GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 1, 7),
293 GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 2, 7),
307 /* Bit 3 gmac_gpll_src_en Unused ? */
308 /* Bit 4 gmac_vpll_src_en Unused ? */
310 /* Bit 6-7 unused */
312 /* Bit 9-15 unused */
322 GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 4, 7),
324 /* Bit 9 clk_usb3phy_ref_25m_en */
326 /* Bit 11-15 unused */
336 /* Bit 7-15 unused */
346 GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 6, 7),
347 /* Bit 8-15 unused */
350 /* Bit 0 aclk_core_en */
351 /* Bit 1 clk_core_periph_en */
352 /* Bit 2 clk_jtag_en */
353 /* Bit 3 unused */
354 /* Bit 4 pclk_ddr_en */
355 /* Bit 5-15 unused */
365 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 8, 7),
369 /* Bit 11-15 unused */
379 GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 9, 7),
380 /* Bit 8-15 unused */
386 /* Bit 3-15 unused */
390 /* Bit 1-3 unused */
392 /* Bit 5-7 unused */
394 /* Bit 9-15 unused */
400 /* Bit 0 aclk_core_niu_en */
401 /* Bit 1 aclk_gic400_en */
402 /* Bit 2-15 unused */
407 /* Bit 2-15 unused */
410 /* Bit 0 aclk_intmem_en Unused */
411 /* Bit 1 aclk_dmac_bus_en Unused */
412 /* Bit 2 hclk_rom_en Unused */
417 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 15, 7),
426 /* Bit 15 pclk_phy_niu_en */
436 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 16, 7),
448 /* Bit 1 unused */
454 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 17, 7),
456 /* Bit 9 unused */
460 /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
465 /* Bit 0 unused */
466 /* Bit 1 pclk_ddr_upctl_en */
467 /* Bit 2 pclk_ddr_msch_en */
468 /* Bit 3 pclk_ddr_mon_en */
469 /* Bit 4 aclk_ddr_upctl_en */
470 /* Bit 5 clk_ddr_upctl_en */
471 /* Bit 6 clk_ddr_msch_en */
472 /* Bit 7 pclk_ddrstdby_en */
473 /* Bit 8-15 unused */
479 /* Bit 3-5 unused */
481 GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 19, 7),
484 /* Bit 10 unused */
495 /* Bit 0-1 unused */
501 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 21, 7),
518 /* Bit 6-15 unused */
525 /* Bit 4-15 unused */
532 /* Bit 4-15 unused */
542 /* Bit 7-15 unused */
551 /* Bit 6-15 unused */
554 /* Bit 0 clk_ddrphy_en */
555 /* Bit 1 clk4x_ddrphy_en */
563 /* Bit 5-15 unused */
632 PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
883 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1),
886 FRACT(0, "clk_i2s0_frac_f", "clk_i2s0_div", 0, 7),
890 COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 8, 0, 7, 15, 1),
898 COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 10, 0, 7, 15, 1),
907 CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7),
915 CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7),
923 CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7),
931 CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7),
938 COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1),
950 COMP(0, "clk_pwm_c", pll_src_cpll_gpll_p, 0, 24, 8, 7, 15, 1),
951 COMP(0, "clk_spi_c", pll_src_cpll_gpll_p, 0, 24, 0, 7, 7, 1),
959 COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1),
962 COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1),
985 COMP(0, "clk_i2c0_c", pll_src_cpll_gpll_p, 0, 34, 0, 7, 7, 1),
986 COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, 34, 8, 7, 15, 1),
989 COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, 35, 0, 7, 7, 1),
990 COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, 35, 8, 7, 15, 1),
1016 MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1),
1027 COMP(0, "clk_ref_usb3otg_src_c", pll_src_cpll_gpll_p, 0, 45, 0, 7, 7, 1),
1075 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { in rk3328_cru_probe()
1089 sc->dev = dev; in rk3328_cru_attach()
1091 sc->gates = rk3328_gates; in rk3328_cru_attach()
1092 sc->ngates = nitems(rk3328_gates); in rk3328_cru_attach()
1094 sc->clks = rk3328_clks; in rk3328_cru_attach()
1095 sc->nclks = nitems(rk3328_clks); in rk3328_cru_attach()
1097 sc->reset_offset = 0x300; in rk3328_cru_attach()
1098 sc->reset_num = 184; in rk3328_cru_attach()