Lines Matching +full:6 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org>
62 #define ARMCLK 6
256 /* Bit 3 bus_src_clk_en */
257 /* Bit 4 clk_ddrphy_src_en */
258 /* Bit 5 clk_ddrpd_src_en */
259 /* Bit 6 clk_ddrmon_en */
260 /* Bit 7-8 unused */
261 /* Bit 9 testclk_en */
265 /* Bit 13-15 unused */
268 /* Bit 0 unused */
274 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 1, 6),
292 GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 2, 6),
307 /* Bit 3 gmac_gpll_src_en Unused ? */
308 /* Bit 4 gmac_vpll_src_en Unused ? */
310 /* Bit 6-7 unused */
312 /* Bit 9-15 unused */
321 GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 4, 6),
324 /* Bit 9 clk_usb3phy_ref_25m_en */
326 /* Bit 11-15 unused */
335 GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 5, 6),
336 /* Bit 7-15 unused */
339 GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 6, 0),
340 GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 6, 1),
341 GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 6, 2),
342 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 6, 3),
343 GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 6, 4),
344 GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 6, 5),
345 GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 6, 6),
346 GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 6, 7),
347 /* Bit 8-15 unused */
350 /* Bit 0 aclk_core_en */
351 /* Bit 1 clk_core_periph_en */
352 /* Bit 2 clk_jtag_en */
353 /* Bit 3 unused */
354 /* Bit 4 pclk_ddr_en */
355 /* Bit 5-15 unused */
364 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 8, 6),
369 /* Bit 11-15 unused */
378 GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 9, 6),
380 /* Bit 8-15 unused */
386 /* Bit 3-15 unused */
390 /* Bit 1-3 unused */
392 /* Bit 5-7 unused */
394 /* Bit 9-15 unused */
400 /* Bit 0 aclk_core_niu_en */
401 /* Bit 1 aclk_gic400_en */
402 /* Bit 2-15 unused */
407 /* Bit 2-15 unused */
410 /* Bit 0 aclk_intmem_en Unused */
411 /* Bit 1 aclk_dmac_bus_en Unused */
412 /* Bit 2 hclk_rom_en Unused */
416 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 15, 6),
426 /* Bit 15 pclk_phy_niu_en */
435 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 16, 6),
448 /* Bit 1 unused */
453 GATE(0, "pclk_sgrf", "pclk_bus", 17, 6),
456 /* Bit 9 unused */
460 /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */
465 /* Bit 0 unused */
466 /* Bit 1 pclk_ddr_upctl_en */
467 /* Bit 2 pclk_ddr_msch_en */
468 /* Bit 3 pclk_ddr_mon_en */
469 /* Bit 4 aclk_ddr_upctl_en */
470 /* Bit 5 clk_ddr_upctl_en */
471 /* Bit 6 clk_ddr_msch_en */
472 /* Bit 7 pclk_ddrstdby_en */
473 /* Bit 8-15 unused */
479 /* Bit 3-5 unused */
480 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 19, 6),
484 /* Bit 10 unused */
495 /* Bit 0-1 unused */
500 GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 21, 6),
518 /* Bit 6-15 unused */
525 /* Bit 4-15 unused */
532 /* Bit 4-15 unused */
541 GATE(0, "aclk_axisram", "hclk_rkvenc", 25, 6),
542 /* Bit 7-15 unused */
551 /* Bit 6-15 unused */
554 /* Bit 0 clk_ddrphy_en */
555 /* Bit 1 clk4x_ddrphy_en */
563 /* Bit 5-15 unused */
604 PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
614 PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
615 PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
620 PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
632 PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
801 .mux_shift = 6,
875 COMP(0, "clk_otp_c", pll_src_cpll_gpll_xin24m_p, 0, 4, 0, 6, 6, 2),
882 MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2),
883 COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1),
954 COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2),
966 COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2),
994 COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2),
997 COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2),
1004 COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2),
1023 COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2),
1037 COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2),
1040 COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2),
1043 COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2),
1047 COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2),
1051 COMP(0, "sclk_wifi_c", pll_src_cpll_gpll_usb480m_p, 0, 51, 0, 6, 6, 2),
1075 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { in rk3328_cru_probe()
1089 sc->dev = dev; in rk3328_cru_attach()
1091 sc->gates = rk3328_gates; in rk3328_cru_attach()
1092 sc->ngates = nitems(rk3328_gates); in rk3328_cru_attach()
1094 sc->clks = rk3328_clks; in rk3328_cru_attach()
1095 sc->nclks = nitems(rk3328_clks); in rk3328_cru_attach()
1097 sc->reset_offset = 0x300; in rk3328_cru_attach()
1098 sc->reset_num = 184; in rk3328_cru_attach()