Lines Matching +full:0 +full:x18c
55 CCU_RESET(RST_R_APB1_TIMER, 0x11c, 16)
56 CCU_RESET(RST_R_APB1_TWD, 0x12c, 16)
57 CCU_RESET(RST_R_APB1_PWM, 0x13c, 16)
58 CCU_RESET(RST_R_APB2_UART, 0x18c, 16)
59 CCU_RESET(RST_R_APB2_I2C, 0x19c, 16)
60 CCU_RESET(RST_R_APB1_IR, 0x1cc, 16)
61 CCU_RESET(RST_R_APB1_W1, 0x1ec, 16)
65 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
66 CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0)
67 CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0)
68 CCU_GATE(CLK_R_APB2_UART, "r_apb1-uart", "r_apb2", 0x18c, 0)
69 CCU_GATE(CLK_R_APB2_I2C, "r_apb1-i2c", "r_apb2", 0x19c, 0)
70 CCU_GATE(CLK_R_APB1_IR, "r_apb1-ir", "r_apb1", 0x1cc, 0)
71 CCU_GATE(CLK_R_APB1_W1, "r_apb1-w1", "r_apb1", 0x1ec, 0)
77 0x00, /* offset */
79 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
80 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
88 0, /* freq */
91 0); /* flags */
97 0x0c, /* offset */
98 0, 2, /* shift, width */
99 0, NULL); /* flags, div table */
104 0x10, /* offset */
106 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
107 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
119 { NULL, 0},
129 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in ccu_sun50i_h6_r_probe()
164 EARLY_DRIVER_MODULE(ccu_sun50i_h6_r, simplebus, ccu_sun50i_h6_r_driver, 0, 0,