Lines Matching +full:8 +full:m
144 CCU_GATE(CLK_MBUS_CSI, "mbus-csi", "mbus", 0x804, 8)
177 CCU_GATE(CLK_BUS_OTG, "bus-otg", "psi-ahb", 0xA8C, 8)
203 8, 8, 0, 0, /* n factor */
215 8, 7, 0, 0, /* n factor */
229 8, 8, 0, 0, /* n factor */
236 /* PLL_PERIPH0(2X) = 24 MHz * N / M / P0 */
243 16, 3, 0, 0, /* m factor */
248 /* PLL_PERIPH0(800M) = 24 MHz * N / M / P1 */
255 20, 3, 0, 0, /* m factor */
260 /* PLL_PERIPH0(1X) = 24 MHz * N / M / P0 / 2 */
271 /* For child clocks: InputFreq * N / M */
278 8, 7, 0, 0, /* n factor */
284 /* PLL_VIDEO0(4X) = InputFreq * N / M / D */
292 0, 1, 0, 0, /* m factor */
297 /* PLL_VIDEO0(2X) = InputFreq * N / M / 2 */
308 /* For child clocks: InputFreq * N / M */
315 8, 7, 0, 0, /* n factor */
321 /* PLL_VIDEO1(4X) = InputFreq * N / M / D */
329 0, 1, 0, 0, /* m factor */
334 /* PLL_VIDEO1(2X) = InputFreq * N / M / 2 */
351 8, 7, 0, 0, /* n factor */
365 8, 7, 0, 0, /* n factor */
394 /* For child clocks: 24MHz * N / M */
401 8, 7, 0, 0, /* n factor */
407 /* PLL_AUDIO1(DIV2) = 24MHz * N / M / P0 */
414 16, 3, 0, 0, /* m factor */
419 /* PLL_AUDIO1(DIV5) = 24MHz * N / M / P1 */
426 20, 3, 0, 0, /* m factor */
438 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */
449 0, 2, 0, 0, /* m factor */
460 8, 2, 0, 0, /* m factor */
470 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
471 0, 2, 0, 0, /* m factor */
480 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
481 0, 2, 0, 0, /* m factor */
490 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
491 0, 2, 0, 0, /* m factor */
509 0, 5, 0, 0, /* m factor */
520 0, 5, 0, 0, /* m factor */
531 0, 5, 0, 0, /* m factor */
541 8, 2, 0, 0, /* n factor */
542 0, 4, 0, 0, /* m factor */
552 0, 5, 0, 0, /* m factor */
563 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
564 0, 2, 0, 0, /* m factor */
576 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
577 0, 4, 0, 0, /* m factor */
589 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
590 0, 4, 0, 0, /* m factor */
602 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
603 0, 4, 0, 0, /* m factor */
614 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
615 0, 4, 0, 0, /* m factor */
626 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
627 0, 4, 0, 0, /* m factor */
640 0, 0, 24, AW_CLK_FACTOR_FIXED, /* m factor */
649 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
650 0, 4, 0, 0, /* m factor */
661 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
662 0, 5, 0, 0, /* m factor */
673 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
674 0, 5, 0, 0, /* m factor */
685 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
686 0, 5, 0, 0, /* m factor */
699 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
700 0, 5, 0, 0, /* m factor */
712 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
713 0, 5, 0, 0, /* m factor */
725 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
726 0, 5, 0, 0, /* m factor */
737 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
738 0, 5, 0, 0, /* m factor */
751 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
752 0, 5, 0, 0, /* m factor */
765 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
766 0, 5, 0, 0, /* m factor */
776 * The clocks have three parents; they output 12M when assigned to the first
798 0, 0, 50, AW_CLK_FACTOR_FIXED, /* m factor */
808 0, 0, 50, AW_CLK_FACTOR_FIXED, /* m factor */
819 0, 4, 0, 0, /* m factor */
830 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
831 0, 4, 0, 0, /* m factor */
842 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
843 0, 4, 0, 0, /* m factor */
854 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
855 0, 4, 0, 0, /* m factor */
866 0, 5, 0, 0, /* m factor */
876 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
877 0, 4, 0, 0, /* m factor */
888 0, 4, 0, 0, /* m factor */
901 0, 5, 0, 0, /* m factor */
912 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */
923 0, 5, 0, 0, /* m factor */
934 0, 5, 0, 0, /* m factor */
950 8, 2, /* shift, width */
960 { .type = AW_CLK_M, .clk.m = &pll_periph0_2x_clk },
961 { .type = AW_CLK_M, .clk.m = &pll_periph0_800m_clk },
964 { .type = AW_CLK_M, .clk.m = &pll_video0_4x_clk },
967 { .type = AW_CLK_M, .clk.m = &pll_video1_4x_clk },
974 { .type = AW_CLK_M, .clk.m = &pll_audio1_div2_clk },
975 { .type = AW_CLK_M, .clk.m = &pll_audio1_div5_clk },
976 { .type = AW_CLK_M, .clk.m = &cpux_clk },
977 { .type = AW_CLK_M, .clk.m = &cpux_axi_clk },
978 { .type = AW_CLK_M, .clk.m = &cpux_apb_clk },
983 { .type = AW_CLK_M, .clk.m = &de_clk },
984 { .type = AW_CLK_M, .clk.m = &di_clk },
985 { .type = AW_CLK_M, .clk.m = &g2d_clk },
987 { .type = AW_CLK_M, .clk.m = &ve_clk },
994 { .type = AW_CLK_M, .clk.m = &emac_25m_clk },
1005 { .type = AW_CLK_M, .clk.m = &usb_ohci0_clk },
1006 { .type = AW_CLK_M, .clk.m = &usb_ohci1_clk },
1007 { .type = AW_CLK_M, .clk.m = &dsi_clk },
1011 { .type = AW_CLK_M, .clk.m = &tvd_clk },
1013 { .type = AW_CLK_M, .clk.m = &csi_top_clk },
1014 { .type = AW_CLK_M, .clk.m = &csi_mclk },
1015 { .type = AW_CLK_M, .clk.m = &tpadc_clk },
1016 { .type = AW_CLK_M, .clk.m = &dsp_clk },
1017 { .type = AW_CLK_M, .clk.m = &riscv_clk },