Lines Matching +full:tx +full:- +full:burst +full:- +full:length
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
88 #define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */
89 #define CAS_INTR_TX_DONE 0x00000004 /* Any TX frame transferred. */
90 #define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */
97 #define CAS_INTR_RX_LEN_MMATCH 0x00000400 /* length field mismatch */
100 #define CAS_INTR_TX_MAC_INT 0x00004000 /* TX MAC interrupt */
106 #define CAS_STATUS_TX_COMP3_MASK 0xfff80000 /* TX completion 3 */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
126 #define CAS_BIM_DIAG_BRST_SM 0x0000007f /* burst ctrl. state machine */
129 #define CAS_RESET_TX 0x00000001 /* Reset TX DMA engine. */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
186 /* TX DMA registers */
187 #define CAS_TX_CONF 0x2004 /* TX configuration */
193 #define CAS_TX_SM1 0x2028 /* TX state machine 1 */
194 #define CAS_TX_SM2 0x202c /* TX state machine 2 */
195 #define CAS_TX_DATA_PTR_LO 0x2030 /* TX data pointer low */
196 #define CAS_TX_DATA_PTR_HI 0x2034 /* TX data pointer high */
197 #define CAS_TX_KICK1 0x2038 /* TX kick 1 */
198 #define CAS_TX_KICK2 0x203c /* TX kick 2 */
199 #define CAS_TX_KICK3 0x2040 /* TX kick 3 */
200 #define CAS_TX_KICK4 0x2044 /* TX kick 4 */
201 #define CAS_TX_COMP1 0x2048 /* TX completion 1 */
202 #define CAS_TX_COMP2 0x204c /* TX completion 2 */
203 #define CAS_TX_COMP3 0x2050 /* TX completion 3 */
204 #define CAS_TX_COMP4 0x2054 /* TX completion 4 */
205 #define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */
206 #define CAS_TX_COMPWB_BASE_HI 0x205c /* TX completion writeback base high */
207 #define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */
208 #define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */
209 #define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */
210 #define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */
211 #define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */
212 #define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */
213 #define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */
214 #define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */
215 #define CAS_TX_MAXBURST1 0x2080 /* TX MaxBurst 1 */
216 #define CAS_TX_MAXBURST2 0x2084 /* TX MaxBurst 2 */
217 #define CAS_TX_MAXBURST3 0x2088 /* TX MaxBurst 3 */
218 #define CAS_TX_MAXBURST4 0x208c /* TX MaxBurst 4 */
219 #define CAS_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
220 #define CAS_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
221 #define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */
222 #define CAS_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data highT1 */
223 #define CAS_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data highT0 */
224 #define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size in 64 byte multiples */
225 #define CAS_TX_RAM_BIST 0x211c /* TX RAM BIST control/status */
227 #define CAS_TX_CONF_TXDMA_EN 0x00000001 /* TX DMA enable */
228 #define CAS_TX_CONF_FIFO_PIO 0x00000002 /* Allow TX FIFO PIO access. */
229 #define CAS_TX_CONF_DESC1_MASK 0x0000003c /* TX descriptor ring 1 size */
231 #define CAS_TX_CONF_DESC2_MASK 0x000003c0 /* TX descriptor ring 2 size */
233 #define CAS_TX_CONF_DESC3_MASK 0x00003c00 /* TX descriptor ring 3 size */
235 #define CAS_TX_CONF_DESC4_MASK 0x0003c000 /* TX descriptor ring 4 size */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
247 #define CAS_TX_COMPWB_ALIGN 2048 /* TX compl. W/B alignment */
249 #define CAS_TX_DESC_ALIGN 2048 /* TX descriptor alignment */
264 #define CAS_TX_SM1_TX_FIFO_LOAD 0x0003f000 /* TX FIFO load state machine */
265 #define CAS_TX_SM1_TX_FIFO_UNLD 0x003c0000 /* TX FIFO unload state mach. */
529 #define CAS_HP_STATUS3_MASK_DLZ 0x00000100 /* Mask data length equal 0. */
560 #define CAS_MAC_TXRESET 0x6000 /* TX MAC software reset command */
563 #define CAS_MAC_TX_STATUS 0x6010 /* TX MAC status */
566 #define CAS_MAC_TX_MASK 0x6020 /* TX MAC mask */
569 #define CAS_MAC_TX_CONF 0x6030 /* TX MAC configuration */
656 #define CAS_MAC_RX_LEN_ERR_CNT 0x61bc /* length error counter */
669 #define CAS_MAC_TX_UNDERRUN 0x00000002 /* TX data starvation */
684 #define CAS_MAC_RX_LEN_EXP 0x00000020 /* length error counter wrap */
695 #define CAS_MAC_TX_CONF_EN 0x00000001 /* TX enable */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
720 #define CAS_MAC_XIF_CONF_TX_OE 0x00000001 /* MII TX output drivers en. */
737 #define CAS_MAC_MAX_BF_BST_MASK 0x3fff0000 /* maximum burst size */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
845 #define CAS_PCS_SM_TX_CTRL_MASK 0x0000000f /* TX control state */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
884 #define CAS_PCS_PKT_CNT_TX_MASK 0x000007ff /* TX packets */
922 #define CAS_TD_BUF_LEN_MASK 0x0000000000003fffULL /* buffer length */
948 #define CAS_RC1_DATA_SIZE_MASK 0x0000000007ffe000ULL /* pkt. data length */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
970 #define CAS_RC2_HDR_SIZE_MASK 0x00000ff800000000ULL /* header length */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */
1000 #define CAS_RC4_PKT_LEN_MASK 0x000000003fff0000ULL /* entire pkt. length */
1009 #define CAS_RC4_LEN_MMATCH 0x8000000000000000ULL /* length field mism. */