Lines Matching +full:mac +full:- +full:base
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
100 #define CAS_INTR_TX_MAC_INT 0x00004000 /* TX MAC interrupt */
101 #define CAS_INTR_RX_MAC_INT 0x00008000 /* RX MAC interrupt */
102 #define CAS_INTR_MAC_CTRL_INT 0x00010000 /* MAC control interrupt */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
184 #define CAS_SATURN_PCFG_LAD 0x00000800 /* MAC LED control active low */
205 #define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */
206 #define CAS_TX_COMPWB_BASE_HI 0x205c /* TX completion writeback base high */
207 #define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */
208 #define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */
209 #define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */
210 #define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */
211 #define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */
212 #define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */
213 #define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */
214 #define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
292 #define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */
293 #define CAS_RX_DESC_BASE_HI 0x402c /* RX descriptor ring base high */
294 #define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */
295 #define CAS_RX_COMP_BASE_HI 0x4034 /* RX completion ring base high */
333 #define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */
334 #define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */
335 #define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */
336 #define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */
337 #define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */
338 #define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */
339 #define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */
340 #define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */
559 /* MAC registers */
560 #define CAS_MAC_TXRESET 0x6000 /* TX MAC software reset command */
561 #define CAS_MAC_RXRESET 0x6004 /* RX MAC software reset command */
563 #define CAS_MAC_TX_STATUS 0x6010 /* TX MAC status */
564 #define CAS_MAC_RX_STATUS 0x6014 /* RX MAC status */
565 #define CAS_MAC_CTRL_STATUS 0x6018 /* MAC control status */
566 #define CAS_MAC_TX_MASK 0x6020 /* TX MAC mask */
567 #define CAS_MAC_RX_MASK 0x6024 /* RX MAC mask */
568 #define CAS_MAC_CTRL_MASK 0x6028 /* MAC control mask */
569 #define CAS_MAC_TX_CONF 0x6030 /* TX MAC configuration */
570 #define CAS_MAC_RX_CONF 0x6034 /* RX MAC configuration */
571 #define CAS_MAC_CTRL_CONF 0x6038 /* MAC control configuration */
582 #define CAS_MAC_CTRL_TYPE 0x6064 /* MAC control type */
583 #define CAS_MAC_ADDR0 0x6080 /* MAC address 0 */
584 #define CAS_MAC_ADDR1 0x6084 /* MAC address 1 */
585 #define CAS_MAC_ADDR2 0x6088 /* MAC address 2 */
586 #define CAS_MAC_ADDR3 0x608c /* MAC address 3 */
587 #define CAS_MAC_ADDR4 0x6090 /* MAC address 4 */
588 #define CAS_MAC_ADDR5 0x6094 /* MAC address 5 */
589 #define CAS_MAC_ADDR6 0x6098 /* MAC address 6 */
590 #define CAS_MAC_ADDR7 0x609c /* MAC address 7 */
591 #define CAS_MAC_ADDR8 0x60a0 /* MAC address 8 */
592 #define CAS_MAC_ADDR9 0x60a4 /* MAC address 9 */
593 #define CAS_MAC_ADDR10 0x60a8 /* MAC address 10 */
594 #define CAS_MAC_ADDR11 0x60ac /* MAC address 11 */
595 #define CAS_MAC_ADDR12 0x60b0 /* MAC address 12 */
596 #define CAS_MAC_ADDR13 0x60b4 /* MAC address 13 */
597 #define CAS_MAC_ADDR14 0x60b8 /* MAC address 14 */
598 #define CAS_MAC_ADDR15 0x60bc /* MAC address 15 */
599 #define CAS_MAC_ADDR16 0x60c0 /* MAC address 16 */
600 #define CAS_MAC_ADDR17 0x60c4 /* MAC address 17 */
601 #define CAS_MAC_ADDR18 0x60c8 /* MAC address 18 */
602 #define CAS_MAC_ADDR19 0x60cc /* MAC address 19 */
603 #define CAS_MAC_ADDR20 0x60d0 /* MAC address 20 */
604 #define CAS_MAC_ADDR21 0x60d4 /* MAC address 21 */
605 #define CAS_MAC_ADDR22 0x60d8 /* MAC address 22 */
606 #define CAS_MAC_ADDR23 0x60dc /* MAC address 23 */
607 #define CAS_MAC_ADDR24 0x60e0 /* MAC address 24 */
608 #define CAS_MAC_ADDR25 0x60e4 /* MAC address 25 */
609 #define CAS_MAC_ADDR26 0x60e8 /* MAC address 26 */
610 #define CAS_MAC_ADDR27 0x60ec /* MAC address 27 */
611 #define CAS_MAC_ADDR28 0x60f0 /* MAC address 28 */
612 #define CAS_MAC_ADDR29 0x60f4 /* MAC address 29 */
613 #define CAS_MAC_ADDR30 0x60f8 /* MAC address 30 */
614 #define CAS_MAC_ADDR31 0x60fc /* MAC address 31 */
615 #define CAS_MAC_ADDR32 0x6100 /* MAC address 32 */
616 #define CAS_MAC_ADDR33 0x6104 /* MAC address 33 */
617 #define CAS_MAC_ADDR34 0x6108 /* MAC address 34 */
618 #define CAS_MAC_ADDR35 0x610c /* MAC address 35 */
619 #define CAS_MAC_ADDR36 0x6110 /* MAC address 36 */
620 #define CAS_MAC_ADDR37 0x6114 /* MAC address 37 */
621 #define CAS_MAC_ADDR38 0x6118 /* MAC address 38 */
622 #define CAS_MAC_ADDR39 0x611c /* MAC address 39 */
623 #define CAS_MAC_ADDR40 0x6120 /* MAC address 40 */
624 #define CAS_MAC_ADDR41 0x6124 /* MAC address 41 */
625 #define CAS_MAC_ADDR42 0x6128 /* MAC address 42 */
626 #define CAS_MAC_ADDR43 0x612c /* MAC address 43 */
627 #define CAS_MAC_ADDR44 0x6130 /* MAC address 44 */
661 #define CAS_MAC_MAC_STATE 0x61d0 /* MAC state machine */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
872 #define CAS_PCS_DATAPATH_MII 0x00000001 /* GMII/MII and MAC loopback */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */