Lines Matching +full:lf +full:- +full:buffer +full:- +full:low +full:- +full:power
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
54 #define CAS_BIM_BUF_ADDR 0x1024 /* BIM buffer address */
55 #define CAS_BIM_BUF_DATA_LO 0x1028 /* BIM buffer data low */
56 #define CAS_BIM_BUF_DATA_HI 0x102c /* BIM buffer data high */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
92 #define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
147 #define CAS_BIM_BUF_ADDR_INDEX 0x0000003f /* buffer entry index */
150 #define CAS_BIM_RAM_BIST_START 0x00000001 /* Start BIST on read buffer. */
151 #define CAS_BIM_RAM_BIST_SUM 0x00000004 /* read buffer pass summary */
152 #define CAS_BIM_RAM_BIST_LO 0x00000010 /* read buf. low bank passes */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
169 #define CAS_INTRN_RX_BUF_NA 0x00000008 /* RX buffer not available */
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
184 #define CAS_SATURN_PCFG_LAD 0x00000800 /* MAC LED control active low */
195 #define CAS_TX_DATA_PTR_LO 0x2030 /* TX data pointer low */
205 #define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */
207 #define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */
209 #define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */
211 #define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */
213 #define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */
221 #define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
292 #define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */
294 #define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */
304 #define CAS_RX_WORKING_DMA_LO 0x4058 /* RX working DMA pointer low */
312 #define CAS_RX_FIFO_DATA_LO 0x4088 /* RX FIFO data low */
316 #define CAS_RX_CTRL_FIFO_LO 0x4098 /* RX control FIFO data low */
321 #define CAS_RX_IPP_DATA_LO 0x410c /* RX IPP FIFO data low */
324 #define CAS_RX_HDR_PAGE_LO 0x4118 /* RX header page pointer low */
326 #define CAS_RX_MTU_PAGE_LO 0x4120 /* RX MTU page pointer low */
329 #define CAS_RX_REAS_DMA_DATA_LO 0x412c /* RX reassembly DMA table data low */
333 #define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */
335 #define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */
337 #define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */
339 #define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */
377 #define CAS_RX_PSZ_MB_STRD_MASK 0x18000000 /* MTU buffer stride */
379 #define CAS_RX_PSZ_MB_OFF_MASK 0xc0000000 /* MTU buffer offset */
387 #define CAS_RX_PSZ_MB_STRD_1K 0x0 /* MTU buffer stride 1Kbyte */
388 #define CAS_RX_PSZ_MB_STRD_2K 0x1 /* MTU buffer stride 2Kbyte */
389 #define CAS_RX_PSZ_MB_STRD_4K 0x2 /* MTU buffer stride 4Kbyte */
390 #define CAS_RX_PSZ_MB_STRD_8K 0x3 /* MTU buffer stride 8Kbyte */
468 #define CAS_HP_IR_DATA_LO 0x4148 /* HP instruction RAM data low */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
811 #define CAS_PCS_CTRL_POWERDOWN 0x00000800 /* power down */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
922 #define CAS_TD_BUF_LEN_MASK 0x0000000000003fffULL /* buffer length */
935 #define CAS_RD_BUF_INDEX_MASK 0x0000000000003fffULL /* data buffer index */
950 #define CAS_RC1_DATA_OFF_MASK 0x000001fff8000000ULL /* data buffer offset */
952 #define CAS_RC1_DATA_INDEX_MASK 0x007ffe0000000000ULL /* data buffer index */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */