Lines Matching +full:fifo +full:- +full:size
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
88 #define CAS_INTR_TX_ALL 0x00000002 /* TX frames trans. to FIFO. */
90 #define CAS_INTR_TX_TAG_ERR 0x00000008 /* TX FIFO tag corrupted. */
93 #define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
157 #define CAS_PROBE_MUX_SELECT_SB 0x000000f0 /* txdma_wr address and size */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
188 #define CAS_TX_FIFO_WR 0x2014 /* FIFO write pointer */
189 #define CAS_TX_FIFO_SDWR 0x2018 /* FIFO shadow write pointer */
190 #define CAS_TX_FIFO_RD 0x201c /* FIFO read pointer */
191 #define CAS_TX_FIFO_SDRD 0x2020 /* FIFO shadow read pointer */
192 #define CAS_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
219 #define CAS_TX_FIFO_ADDR 0x2104 /* TX FIFO address */
220 #define CAS_TX_FIFO_TAG 0x2108 /* TX FIFO tag */
221 #define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */
222 #define CAS_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data highT1 */
223 #define CAS_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data highT0 */
224 #define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size in 64 byte multiples */
228 #define CAS_TX_CONF_FIFO_PIO 0x00000002 /* Allow TX FIFO PIO access. */
229 #define CAS_TX_CONF_DESC1_MASK 0x0000003c /* TX descriptor ring 1 size */
231 #define CAS_TX_CONF_DESC2_MASK 0x000003c0 /* TX descriptor ring 2 size */
233 #define CAS_TX_CONF_DESC3_MASK 0x00003c00 /* TX descriptor ring 3 size */
235 #define CAS_TX_CONF_DESC4_MASK 0x0003c000 /* TX descriptor ring 4 size */
237 #define CAS_TX_CONF_PACED 0x00100000 /* ALL intr. on FIFO empty */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
251 /* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */
264 #define CAS_TX_SM1_TX_FIFO_LOAD 0x0003f000 /* TX FIFO load state machine */
265 #define CAS_TX_SM1_TX_FIFO_UNLD 0x003c0000 /* TX FIFO unload state mach. */
283 #define CAS_RX_PSZ 0x4004 /* RX page size */
284 #define CAS_RX_FIFO_WR 0x4008 /* RX FIFO write pointer */
285 #define CAS_RX_FIFO_RD 0x400c /* RX FIFO read pointer */
286 #define CAS_RX_IPP_WR 0x4010 /* RX IPP FIFO write pointer */
287 #define CAS_RX_IPP_SDWR 0x4014 /* RX IPP FIFO shadow write pointer */
288 #define CAS_RX_IPP_RD 0x4018 /* RX IPP FIFO read pointer */
302 #define CAS_RX_FF 0x4050 /* RX FIFO fullness */
307 #define CAS_RX_CTRL_FIFO_WR 0x4064 /* RX control FIFO write pointer */
308 #define CAS_RX_CTRL_FIFO_RD 0x4068 /* RX control FIFO read pointer */
310 #define CAS_RX_FIFO_ADDR 0x4080 /* RX FIFO address */
311 #define CAS_RX_FIFO_TAG 0x4084 /* RX FIFO tag */
312 #define CAS_RX_FIFO_DATA_LO 0x4088 /* RX FIFO data low */
313 #define CAS_RX_FIFO_DATA_HI_T0 0x408c /* RX FIFO data highT0 */
314 #define CAS_RX_FIFO_DATA_HI_T1 0x4090 /* RX FIFO data highT1 */
315 #define CAS_RX_CTRL_FIFO 0x4094 /* RX control FIFO and batching FIFO */
316 #define CAS_RX_CTRL_FIFO_LO 0x4098 /* RX control FIFO data low */
317 #define CAS_RX_CTRL_FIFO_MD 0x409c /* RX control FIFO data mid */
318 #define CAS_RX_CTRL_FIFO_HI 0x4100 /* RX control FIFO data high, flowID */
319 #define CAS_RX_IPP_ADDR 0x4104 /* RX IPP FIFO address */
320 #define CAS_RX_IPP_TAG 0x4108 /* RX IPP FIFO tag */
321 #define CAS_RX_IPP_DATA_LO 0x410c /* RX IPP FIFO data low */
322 #define CAS_RX_IPP_DATA_HI_T0 0x4110 /* RX IPP FIFO data highT0 */
323 #define CAS_RX_IPP_DATA_HI_T1 0x4114 /* RX IPP FIFO data highT1 */
352 #define CAS_RX_CONF_DESC_MASK 0x0000001e /* RX descriptor ring size */
354 #define CAS_RX_CONF_COMP_MASK 0x000001e0 /* RX complition ring size */
360 #define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */
373 #define CAS_RX_PSZ_MASK 0x00000003 /* RX page size */
382 #define CAS_RX_PSZ_2K 0x0 /* page size 2Kbyte */
383 #define CAS_RX_PSZ_4K 0x1 /* page size 4Kbyte */
384 #define CAS_RX_PSZ_8K 0x2 /* page size 8Kbyte */
385 #define CAS_RX_PSZ_16K 0x3 /* page size 16Kbyte*/
425 #define CAS_RX_RED_4K_6K_MASK 0x000000ff /* 4K < FIFO threshold < 6K */
427 #define CAS_RX_RED_6K_8K_MASK 0x0000ff00 /* 6K < FIFO threshold < 8K */
429 #define CAS_RX_RED_8K_10K_MASK 0x00ff0000 /* 8K < FIFO threshold < 10K */
431 #define CAS_RX_RED_10K_12K_MASK 0xff000000 /* 10K < FIFO threshold < 12K */
435 #define CAS_RX_FF_PKT_MASK 0x000000ff /* # of packets in RX FIFO */
437 #define CAS_RX_FF_IPP_MASK 0x0007ff00 /* IPP FIFO level */
439 #define CAS_RX_FF_FIFO_MASK 0x3ff80000 /* RX FIFO level */
448 #define CAS_RX_BIST_CTRL_33 0x00040000 /* Control FIFO 33 okay */
449 #define CAS_RX_BIST_CTRL_32 0x00080000 /* Control FIFO 32 okay */
512 #define CAS_HP_STATUS2_TSZ_MASK 0x0000ffff /* TCP payload size */
577 #define CAS_MAC_MIN_FRAME 0x6050 /* minimum frame size */
578 #define CAS_MAC_MAX_BF 0x6054 /* maximum bust and frame size */
579 #define CAS_MAC_PREAMBLE_LEN 0x6058 /* PA size */
580 #define CAS_MAC_JAM_SIZE 0x605c /* jam size */
680 #define CAS_MAC_RX_OVERFLOW 0x00000002 /* RX FIFO overflow */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
735 #define CAS_MAC_MAX_BF_FRM_MASK 0x00007fff /* maximum frame size */
737 #define CAS_MAC_MAX_BF_BST_MASK 0x3fff0000 /* maximum burst size */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
906 /* wired RX FIFO size in bytes */
931 #define CAS_TD_INT_ME 0x0000000100000000ULL /* intr. when in FIFO */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */