Lines Matching +full:dma +full:- +full:33 +full:bits
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */
75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */
82 * shared interrupt bits for CAS_STATUS, CAS_INTMASK, CAS_CLEAR_ALIAS and
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
109 /* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */
112 #define CAS_ERROR_DMAW_ZERO 0x00000008 /* zero count DMA write */
113 #define CAS_ERROR_DMAR_ZERO 0x00000010 /* zero count DMA read */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
122 #define CAS_BIM_CONF_DIS_BIM 0x00000200 /* Stop PCI DMA transactions. */
129 #define CAS_RESET_TX 0x00000001 /* Reset TX DMA engine. */
130 #define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
186 /* TX DMA registers */
227 #define CAS_TX_CONF_TXDMA_EN 0x00000001 /* TX DMA enable */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
251 /* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */
281 /* RX DMA registers */
304 #define CAS_RX_WORKING_DMA_LO 0x4058 /* RX working DMA pointer low */
305 #define CAS_RX_WORKING_DMA_HI 0x405c /* RX working DMA pointer high */
328 #define CAS_RX_REAS_DMA_ADDR 0x4128 /* RX reassembly DMA table address */
329 #define CAS_RX_REAS_DMA_DATA_LO 0x412c /* RX reassembly DMA table data low */
330 #define CAS_RX_REAS_DMA_DATA_MD 0x4130 /* RX reassembly DMA table data mid */
331 #define CAS_RX_REAS_DMA_DATA_HI 0x4134 /* RX reassembly DMA table data high */
332 /* The rest of the RX DMA registers are Cassini+/Saturn only. */
351 #define CAS_RX_CONF_RXDMA_EN 0x00000001 /* RX DMA enable */
408 * CAS_RX_BLANK and CAS_RX_BLANK_ALIAS bits
418 /* CAS_RX_AEMPTY_THRS and CAS_RX_AEMPTY_THRS2 bits */
448 #define CAS_RX_BIST_CTRL_33 0x00040000 /* Control FIFO 33 okay */
450 #define CAS_RX_BIST_IPP_33C 0x00100000 /* IPP 33C okay */
452 #define CAS_RX_BIST_IPP_33B 0x00400000 /* IPP 33B okay */
454 #define CAS_RX_BIST_IPP_33A 0x01000000 /* IPP 33A okay */
456 #define CAS_RX_BIST_33C 0x04000000 /* 33C okay */
458 #define CAS_RX_BIST_33B 0x10000000 /* 33B okay */
460 #define CAS_RX_BIST_33A 0x40000000 /* 33A okay */
616 #define CAS_MAC_ADDR33 0x6104 /* MAC address 33 */
667 /* CAS_MAC_TX_STATUS and CAS_MAC_TX_MASK register bits */
678 /* CAS_MAC_RX_STATUS and CAS_MAC_RX_MASK register bits */
687 /* CAS_MAC_CTRL_STATUS and CAS_MAC_CTRL_MASK register bits */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
718 #define CAS_MAC_CTRL_CONF_PASSP 0x00000004 /* Pass PAUSE up to RX DMA. */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
782 /* CAS_MIF_MASK and CAS_MIF_STATUS bits */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
824 /* CAS_PCS_ANAR and CAS_PCS_ANLPAR register bits */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */
1011 #define CAS_GET(reg, bits) (((reg) & (bits ## _MASK)) >> (bits ## _SHFT)) argument
1012 #define CAS_SET(val, bits) (((val) << (bits ## _SHFT)) & (bits ## _MASK)) argument