Lines Matching +full:4 +full:- +full:ring
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius
67 #define CAS_INTMASK4 0x1058 /* interrupt mask 4 for INTD */
68 #define CAS_STATUS4 0x105c /* interrupt status 4 for INTD */
69 #define CAS_CLEAR_ALIAS4 0x1060 /* clear mask alias 4 for INTD */
70 #define CAS_STATUS_ALIAS4 0x1064 /* interrupt status alias 4 for INTD */
84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies
85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS.
94 #define CAS_INTR_RX_COMP_FULL 0x00000080 /* RX completion ring full */
95 #define CAS_INTR_RX_BUF_AEMPTY 0x00000100 /* RX desc. ring almost empty */
96 #define CAS_INTR_RX_COMP_AFULL 0x00000200 /* RX cmpl. ring almost full */
116 #define CAS_BIM_CONF_BD64_DIS 0x00000004 /* 64-bit mode disable */
118 #define CAS_BIM_CONF_BUS32_WIDE 0x00000010 /* PCI bus is 32-bit (ro). */
161 * interrupt bits for CAS_INTMASK[2-4], CAS_STATUS[2-4], CAS_CLEAR_ALIAS[2-4]
162 * and CAS_STATUS_ALIAS[2-4].
163 * CAS_STATUS[2-4] auto-clear when read. CAS_CLEAR_ALIAS[2-4] specifies which
164 * of bits 0-9 auto-clear when reading the corresponding CAS_STATUS_ALIAS[2-4].
167 #define CAS_INTRN_RX_COMP_FULL 0x00000002 /* RX completion ring full */
168 #define CAS_INTRN_RX_COMP_AFULL 0x00000004 /* RX cmpl. ring almost full */
170 #define CAS_INTRN_RX_BUF_AEMPTY 0x00000010 /* RX desc. ring almost empty */
172 /* INTn enable bit for CAS_INTMASK[2-4] */
173 #define CAS_INTMASKN_EN 0x00000080 /* INT[B-D] enable */
179 #define CAS_SATURN_PCFG_RLA 0x00000010 /* PHY full-duplex LED */
200 #define CAS_TX_KICK4 0x2044 /* TX kick 4 */
204 #define CAS_TX_COMP4 0x2054 /* TX completion 4 */
207 #define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */
208 #define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */
209 #define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */
210 #define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */
211 #define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */
212 #define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */
213 #define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */
214 #define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */
218 #define CAS_TX_MAXBURST4 0x208c /* TX MaxBurst 4 */
229 #define CAS_TX_CONF_DESC1_MASK 0x0000003c /* TX descriptor ring 1 size */
231 #define CAS_TX_CONF_DESC2_MASK 0x000003c0 /* TX descriptor ring 2 size */
233 #define CAS_TX_CONF_DESC3_MASK 0x00003c00 /* TX descriptor ring 3 size */
235 #define CAS_TX_CONF_DESC4_MASK 0x0003c000 /* TX descriptor ring 4 size */
243 #define CAS_TX_CONF_PICWB_DIS 0x20000000 /* pre-intr. compl. W/B dis. */
251 /* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */
259 #define CAS_DESC_4K 0x7 /* 4k descriptors */
292 #define CAS_RX_DESC_BASE_LO 0x4028 /* RX descriptor ring base low */
293 #define CAS_RX_DESC_BASE_HI 0x402c /* RX descriptor ring base high */
294 #define CAS_RX_COMP_BASE_LO 0x4030 /* RX completion ring base low */
295 #define CAS_RX_COMP_BASE_HI 0x4034 /* RX completion ring base high */
333 #define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */
334 #define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */
335 #define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */
336 #define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */
337 #define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */
338 #define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */
339 #define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */
340 #define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */
347 #define CAS_RX_COMP_HEAD4 0x4238 /* RX completion head 4 */
348 #define CAS_RX_COMP_TAIL4 0x423c /* RX completion tail 4 */
352 #define CAS_RX_CONF_DESC_MASK 0x0000001e /* RX descriptor ring size */
354 #define CAS_RX_CONF_COMP_MASK 0x000001e0 /* RX complition ring size */
359 /* The RX descriptor ring 2 is Cassini+/Saturn only. */
360 #define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */
368 #define CAS_RX_CONF_COMP_4K 0x5 /* 4k descriptors */
383 #define CAS_RX_PSZ_4K 0x1 /* page size 4Kbyte */
389 #define CAS_RX_PSZ_MB_STRD_4K 0x2 /* MTU buffer stride 4Kbyte */
425 #define CAS_RX_RED_4K_6K_MASK 0x000000ff /* 4K < FIFO threshold < 6K */
476 #define CAS_HP_FLOW_DB4 0x4168 /* HP flow database 4 */
518 #define CAS_HP_STATUS2_AR2_MASK 0xe0000000 /* accu_R2[6:4] */
587 #define CAS_MAC_ADDR4 0x6090 /* MAC address 4 */
637 #define CAS_MAC_HASH4 0x6170 /* hash table 4 */
698 #define CAS_MAC_TX_CONF_EN_IPG0 0x00000008 /* extend RX-to-TX IPG */
742 * The bit-bang registers use the low bit only.
744 #define CAS_MIF_BB_CLOCK 0x6200 /* MIF bit-bang clock */
745 #define CAS_MIF_BB_DATA 0x6204 /* MIF bit-bang data */
746 #define CAS_MIF_BB_OUTPUT_EN 0x6208 /* MIF bit-bang output enable */
774 #define CAS_MIF_CONF_BB_MODE 0x00000004 /* bit-bang mode enable */
808 #define CAS_PCS_CTRL_FDX 0x00000100 /* full-duplex, always 0 */
809 #define CAS_PCS_CTRL_RANEG 0x00000200 /* restart auto-negotiation */
812 #define CAS_PCS_CTRL_ANEG_EN 0x00001000 /* auto-negotiation enable */
819 #define CAS_PCS_STATUS_ANEG_ABL 0x00000008 /* auto-negotiation ability */
821 #define CAS_PCS_STATUS_ANEG_CPT 0x00000020 /* auto-negotiate complete */
825 #define CAS_PCS_ANEG_FDX 0x00000020 /* full-duplex */
826 #define CAS_PCS_ANEG_HDX 0x00000040 /* half-duplex */
829 #define CAS_PCS_ANEG_RFLT_FAIL 0x00001000 /* remote fault - fail */
830 #define CAS_PCS_ANEG_RFLT_OFF 0x00002000 /* remote fault - off-line */
838 #define CAS_PCS_CONF_SDL 0x00000004 /* signal detect active-low */
839 #define CAS_PCS_CONF_JS_NORM 0x00000000 /* jitter study - normal op. */
840 #define CAS_PCS_CONF_JS_HF 0x00000008 /* jitter study - HF test */
841 #define CAS_PCS_CONF_JS_LF 0x00000010 /* jitter study - LF test */
843 #define CAS_PCS_CONF_ANEG_TO 0x00000020 /* auto-neg. timer override */
848 #define CAS_PCS_SM_RX_CTRL_SHFT 4
856 #define CAS_PCS_SM_LOSS_C 0x00100000 /* link-loss due to C codes */
857 #define CAS_PCS_SM_LOSS_SYNC 0x00200000 /* link-loss due to sync-loss */
873 #define CAS_PCS_DATAPATH_SERDES 0x00000002 /* SERDES via 10-bit */
875 #define CAS_PCS_SERDES_CTRL_LBK 0x00000001 /* loopback at 10-bit enable */
910 * descriptor ring structures
939 * receive completion ring structure
963 #define CAS_RC1_TYPE_RNRP 0x8000000000000000ULL /* non-reas. pkt... */
977 #define CAS_RC3_SMALL_PKT 0x0000000000000001ULL /* pkt. <= 256 - SOFF */