Lines Matching refs:CAS_WRITE_4
321 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); in cas_attach()
332 CAS_WRITE_4(sc, CAS_MIF_CONF, v); in cas_attach()
337 CAS_WRITE_4(sc, CAS_SATURN_PCFG, in cas_attach()
354 CAS_WRITE_4(sc, CAS_MIF_CONF, v); in cas_attach()
359 CAS_WRITE_4(sc, CAS_SATURN_PCFG, in cas_attach()
375 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); in cas_attach()
379 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); in cas_attach()
383 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); in cas_attach()
386 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); in cas_attach()
650 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); in cas_tick()
651 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); in cas_tick()
652 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); in cas_tick()
653 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); in cas_tick()
654 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); in cas_tick()
655 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); in cas_tick()
656 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); in cas_tick()
657 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); in cas_tick()
691 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); in cas_reset()
700 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | in cas_reset()
723 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); in cas_stop()
762 CAS_WRITE_4(sc, CAS_RX_CONF, 0); in cas_reset_rx()
769 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | in cas_reset_rx()
789 CAS_WRITE_4(sc, CAS_TX_CONF, 0); in cas_reset_tx()
796 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | in cas_reset_tx()
811 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, in cas_disable_rx()
826 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, in cas_disable_tx()
999 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, in cas_init_locked()
1001 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, in cas_init_locked()
1004 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, in cas_init_locked()
1006 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, in cas_init_locked()
1009 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, in cas_init_locked()
1011 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, in cas_init_locked()
1015 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, in cas_init_locked()
1017 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, in cas_init_locked()
1031 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); in cas_init_locked()
1037 CAS_WRITE_4(sc, CAS_INF_BURST, in cas_init_locked()
1042 CAS_WRITE_4(sc, CAS_INTMASK, in cas_init_locked()
1053 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); in cas_init_locked()
1054 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); in cas_init_locked()
1055 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, in cas_init_locked()
1058 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, in cas_init_locked()
1062 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, in cas_init_locked()
1068 CAS_WRITE_4(sc, CAS_ERROR_MASK, in cas_init_locked()
1073 CAS_WRITE_4(sc, CAS_BIM_CONF, in cas_init_locked()
1081 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | in cas_init_locked()
1094 CAS_WRITE_4(sc, CAS_RX_CONF, in cas_init_locked()
1098 CAS_WRITE_4(sc, CAS_RX_PTHRS, in cas_init_locked()
1102 CAS_WRITE_4(sc, CAS_RX_BLANK, in cas_init_locked()
1106 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, in cas_init_locked()
1110 CAS_WRITE_4(sc, CAS_RX_PSZ, in cas_init_locked()
1117 CAS_WRITE_4(sc, CAS_RX_RED, 0); in cas_init_locked()
1121 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); in cas_init_locked()
1122 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); in cas_init_locked()
1123 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); in cas_init_locked()
1124 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); in cas_init_locked()
1128 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); in cas_init_locked()
1129 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); in cas_init_locked()
1132 CAS_WRITE_4(sc, CAS_RX_CONF, in cas_init_locked()
1152 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); in cas_init_locked()
1157 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); in cas_init_locked()
1158 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); in cas_init_locked()
1160 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); in cas_init_locked()
1325 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); in cas_init_regs()
1326 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); in cas_init_regs()
1327 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); in cas_init_regs()
1330 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); in cas_init_regs()
1332 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, in cas_init_regs()
1338 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); in cas_init_regs()
1339 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); in cas_init_regs()
1340 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); in cas_init_regs()
1341 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); in cas_init_regs()
1344 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, in cas_init_regs()
1350 CAS_WRITE_4(sc, i, 0); in cas_init_regs()
1353 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); in cas_init_regs()
1354 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); in cas_init_regs()
1355 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); in cas_init_regs()
1358 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); in cas_init_regs()
1359 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); in cas_init_regs()
1360 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); in cas_init_regs()
1361 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); in cas_init_regs()
1362 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); in cas_init_regs()
1367 CAS_WRITE_4(sc, i, 0); in cas_init_regs()
1373 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); in cas_init_regs()
1374 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); in cas_init_regs()
1375 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); in cas_init_regs()
1376 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); in cas_init_regs()
1377 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); in cas_init_regs()
1378 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); in cas_init_regs()
1379 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); in cas_init_regs()
1380 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); in cas_init_regs()
1381 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); in cas_init_regs()
1382 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); in cas_init_regs()
1383 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); in cas_init_regs()
1386 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); in cas_init_regs()
1389 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); in cas_init_regs()
1390 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); in cas_init_regs()
1391 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); in cas_init_regs()
1394 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); in cas_init_regs()
1421 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); in cas_txkick()
1846 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); in cas_rint()
1902 CAS_WRITE_4(sc, CAS_RX_KICK, in cas_add_rxdesc()
1944 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); in cas_intr()
2061 CAS_WRITE_4(sc, CAS_INTMASK, in cas_intr_task()
2114 CAS_WRITE_4(sc, CAS_MIF_CONF, in cas_mifinit()
2178 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); in cas_mii_readreg()
2213 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); in cas_mii_writereg()
2222 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); in cas_mii_writereg()
2225 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); in cas_mii_writereg()
2228 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, in cas_mii_writereg()
2232 CAS_WRITE_4(sc, CAS_PCS_CONF, in cas_mii_writereg()
2245 CAS_WRITE_4(sc, reg, val); in cas_mii_writereg()
2257 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); in cas_mii_writereg()
2324 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); in cas_mii_statchg()
2326 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); in cas_mii_statchg()
2336 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); in cas_mii_statchg()
2357 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); in cas_mii_statchg()
2359 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); in cas_mii_statchg()
2364 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, in cas_mii_statchg()
2367 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, in cas_mii_statchg()
2381 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); in cas_mii_statchg()
2386 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, in cas_mii_statchg()
2388 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, in cas_mii_statchg()
2517 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); in cas_setladrf()
2551 CAS_WRITE_4(sc, in cas_setladrf()
2557 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); in cas_setladrf()
2739 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, in cas_pci_attach()
2839 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); in cas_pci_attach()