Lines Matching +full:0 +full:x28c
46 #define CGEM_NET_CTRL 0x000 /* Network Control */
64 #define CGEM_NET_CFG 0x004 /* Network Configuration */
74 #define CGEM_NET_CFG_DBUS_WIDTH_32 (0 << 21)
78 #define CGEM_NET_CFG_MDC_CLK_DIV_8 (0 << 18)
104 #define CGEM_NET_CFG_SPEED100 (1 << 0)
106 #define CGEM_NET_STAT 0x008 /* Network Status */
113 #define CGEM_NET_STAT_PCS_LINK_STATE (1 << 0)
115 #define CGEM_USER_IO 0x00C /* User I/O */
117 #define CGEM_DMA_CFG 0x010 /* DMA Config */
121 #define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff << 16)
125 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_1K (0 << 8)
132 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_1 (1 << 0)
133 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_4 (4 << 0)
134 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_8 (8 << 0)
135 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 (16 << 0)
136 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_MASK (0x1f << 0)
138 #define CGEM_TX_STAT 0x014 /* Transmit Status */
147 #define CGEM_TX_STAT_USED_BIT_READ (1 << 0)
148 #define CGEM_TX_STAT_ALL 0x1ff
150 #define CGEM_RX_QBAR 0x018 /* Receive Buf Q Base Addr */
151 #define CGEM_TX_QBAR 0x01C /* Transmit Buf Q Base Addr */
153 #define CGEM_RX_STAT 0x020 /* Receive Status */
157 #define CGEM_RX_STAT_BUF_NOT_AVAIL (1 << 0)
158 #define CGEM_RX_STAT_ALL 0xf
160 #define CGEM_INTR_STAT 0x024 /* Interrupt Status */
161 #define CGEM_INTR_EN 0x028 /* Interrupt Enable */
162 #define CGEM_INTR_DIS 0x02C /* Interrupt Disable */
163 #define CGEM_INTR_MASK 0x030 /* Interrupt Mask */
188 #define CGEM_INTR_MGMT_SENT (1 << 0)
189 #define CGEM_INTR_ALL 0x7FFFEFF
191 #define CGEM_PHY_MAINT 0x034 /* PHY Maintenenace */
198 #define CGEM_PHY_MAINT_PHY_ADDR_MASK (0x1f << 23)
200 #define CGEM_PHY_MAINT_REG_ADDR_MASK (0x1f << 18)
202 #define CGEM_PHY_MAINT_DATA_MASK 0xffff
204 #define CGEM_RX_PAUSEQ 0x038 /* Received Pause Quantum */
205 #define CGEM_TX_PAUSEQ 0x03C /* Transmit Puase Quantum */
207 #define CGEM_HASH_BOT 0x080 /* Hash Reg Bottom [31:0] */
208 #define CGEM_HASH_TOP 0x084 /* Hash Reg Top [63:32] */
209 #define CGEM_SPEC_ADDR_LOW(n) (0x088 + (n) * 8)
210 #define CGEM_SPEC_ADDR_HI(n) (0x08C + (n) * 8)
212 #define CGEM_TYPE_ID_MATCH1 0x0A8 /* Type ID Match 1 */
214 #define CGEM_TYPE_ID_MATCH2 0x0AC /* Type ID Match 2 */
215 #define CGEM_TYPE_ID_MATCH3 0x0B0 /* Type ID Match 3 */
216 #define CGEM_TYPE_ID_MATCH4 0x0B4 /* Type ID Match 4 */
218 #define CGEM_WAKE_ON_LAN 0x0B8 /* Wake on LAN Register */
223 #define CGEM_WOL_ARP_REQ_IP_ADDR_MASK 0xffff
227 #define CGEM_STACKED_VLAN 0x0C0 /* Stacked VLAN Register */
230 #define CGEM_TX_PFC_PAUSE 0x0C4 /* Transmit PFC Pause Reg */
232 #define CGEM_TX_PFC_PAUSEQ_SEL_MASK (0xff << 8)
233 #define CGEM_TX_PFC_PAUSE_PRI_EN_VEC_VAL_MASK 0xff
235 #define CGEM_SPEC_ADDR1_MASK_BOT 0x0C8 /* Specific Addr Mask1 [31:0]*/
236 #define CGEM_SPEC_ADDR1_MASK_TOP 0x0CC /* Specific Addr Mask1[47:32]*/
237 #define CGEM_MODULE_ID 0x0FC /* Module ID */
238 #define CGEM_OCTETS_TX_BOT 0x100 /* Octets xmitted [31:0] */
239 #define CGEM_OCTETS_TX_TOP 0x104 /* Octets xmitted [47:32] */
240 #define CGEM_FRAMES_TX 0x108 /* Frames xmitted */
241 #define CGEM_BCAST_FRAMES_TX 0x10C /* Broadcast Frames xmitted */
242 #define CGEM_MULTI_FRAMES_TX 0x110 /* Multicast Frames xmitted */
243 #define CGEM_PAUSE_FRAMES_TX 0x114 /* Pause Frames xmitted */
244 #define CGEM_FRAMES_64B_TX 0x118 /* 64-Byte Frames xmitted */
245 #define CGEM_FRAMES_65_127B_TX 0x11C /* 65-127 Byte Frames xmitted*/
246 #define CGEM_FRAMES_128_255B_TX 0x120 /* 128-255 Byte Frames xmit */
247 #define CGEM_FRAMES_256_511B_TX 0x124 /* 256-511 Byte Frames xmit */
248 #define CGEM_FRAMES_512_1023B_TX 0x128 /* 512-1023 Byte frames xmit */
249 #define CGEM_FRAMES_1024_1518B_TX 0x12C /* 1024-1518 Byte frames xmit*/
250 #define CGEM_TX_UNDERRUNS 0x134 /* Transmit Under-runs */
251 #define CGEM_SINGLE_COLL_FRAMES 0x138 /* Single-Collision Frames */
252 #define CGEM_MULTI_COLL_FRAMES 0x13C /* Multi-Collision Frames */
253 #define CGEM_EXCESSIVE_COLL_FRAMES 0x140 /* Excessive Collision Frames*/
254 #define CGEM_LATE_COLL 0x144 /* Late Collisions */
255 #define CGEM_DEFERRED_TX_FRAMES 0x148 /* Deferred Transmit Frames */
256 #define CGEM_CARRIER_SENSE_ERRS 0x14C /* Carrier Sense Errors */
257 #define CGEM_OCTETS_RX_BOT 0x150 /* Octets Received [31:0] */
258 #define CGEM_OCTETS_RX_TOP 0x154 /* Octets Received [47:32] */
259 #define CGEM_FRAMES_RX 0x158 /* Frames Received */
260 #define CGEM_BCAST_FRAMES_RX 0x15C /* Broadcast Frames Received */
261 #define CGEM_MULTI_FRAMES_RX 0x160 /* Multicast Frames Received */
262 #define CGEM_PAUSE_FRAMES_RX 0x164 /* Pause Frames Reeived */
263 #define CGEM_FRAMES_64B_RX 0x168 /* 64-Byte Frames Received */
264 #define CGEM_FRAMES_65_127B_RX 0x16C /* 65-127 Byte Frames Rx'd */
265 #define CGEM_FRAMES_128_255B_RX 0x170 /* 128-255 Byte Frames Rx'd */
266 #define CGEM_FRAMES_256_511B_RX 0x174 /* 256-511 Byte Frames Rx'd */
267 #define CGEM_FRAMES_512_1023B_RX 0x178 /* 512-1023 Byte Frames Rx'd */
268 #define CGEM_FRAMES_1024_1518B_RX 0x17C /* 1024-1518 Byte Frames Rx'd*/
269 #define CGEM_UNDERSZ_RX 0x184 /* Undersize Frames Rx'd */
270 #define CGEM_OVERSZ_RX 0x188 /* Oversize Frames Rx'd */
271 #define CGEM_JABBERS_RX 0x18C /* Jabbers received */
272 #define CGEM_FCS_ERRS 0x190 /* Frame Check Sequence Errs */
273 #define CGEM_LENGTH_FIELD_ERRS 0x194 /* Length Firled Frame Errs */
274 #define CGEM_RX_SYMBOL_ERRS 0x198 /* Receive Symbol Errs */
275 #define CGEM_ALIGN_ERRS 0x19C /* Alignment Errors */
276 #define CGEM_RX_RESOURCE_ERRS 0x1A0 /* Receive Resoure Errors */
277 #define CGEM_RX_OVERRUN_ERRS 0x1A4 /* Receive Overrun Errors */
278 #define CGEM_IP_HDR_CKSUM_ERRS 0x1A8 /* IP Hdr Checksum Errors */
279 #define CGEM_TCP_CKSUM_ERRS 0x1AC /* TCP Checksum Errors */
280 #define CGEM_UDP_CKSUM_ERRS 0x1B0 /* UDP Checksum Errors */
281 #define CGEM_TIMER_STROBE_S 0x1C8 /* 1588 timer sync strobe s */
282 #define CGEM_TIMER_STROBE_NS 0x1CC /* timer sync strobe ns */
283 #define CGEM_TIMER_S 0x1D0 /* 1588 timer seconds */
284 #define CGEM_TIMER_NS 0x1D4 /* 1588 timer ns */
285 #define CGEM_ADJUST 0x1D8 /* 1588 timer adjust */
286 #define CGEM_INCR 0x1DC /* 1588 timer increment */
287 #define CGEM_PTP_TX_S 0x1E0 /* PTP Event Frame xmit secs */
288 #define CGEM_PTP_TX_NS 0x1E4 /* PTP Event Frame xmit ns */
289 #define CGEM_PTP_RX_S 0x1E8 /* PTP Event Frame rcv'd s */
290 #define CGEM_PTP_RX_NS 0x1EC /* PTP Event Frame rcv'd ns */
291 #define CGEM_PTP_PEER_TX_S 0x1F0 /* PTP Peer Event xmit s */
292 #define CGEM_PTP_PEER_TX_NS 0x1F4 /* PTP Peer Event xmit ns */
293 #define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */
294 #define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */
296 #define CGEM_DESIGN_CFG1 0x280 /* Design Configuration 1 */
297 #define CGEM_DESIGN_CFG1_AXI_CACHE_WIDTH_MASK (0xfU << 28)
306 #define CGEM_DESIGN_CFG1_USER_IN_WIDTH_MASK (0x1f << 15)
307 #define CGEM_DESIGN_CFG1_USER_OUT_WIDTH_MASK (0x1f << 10)
317 #define CGEM_DESIGN_CFG1_NO_PCS (1 << 0)
319 #define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */
321 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf << 26)
323 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_MASK (0xf << 22)
327 #define CGEM_DESIGN_CFG2_HPROT_VAL_MASK (0xf << 16)
328 #define CGEM_DESIGN_CFG2_JUMBO_MAX_LEN_MASK 0xffff
330 #define CGEM_DESIGN_CFG3 0x288 /* Design Configuration 3 */
331 #define CGEM_DESIGN_CFG3_RX_BASE2_FIFO_SZ_MASK (0xffffU << 16)
333 #define CGEM_DESIGN_CFG3_RX_FIFO_SIZE_MASK 0xffff
335 #define CGEM_DESIGN_CFG4 0x28C /* Design Configuration 4 */
337 #define CGEM_DESIGN_CFG4_TX_BASE2_FIFO_SZ_MASK (0xffffU << 16)
338 #define CGEM_DESIGN_CFG4_TX_FIFO_SIZE_MASK 0xffff
340 #define CGEM_DESIGN_CFG5 0x290 /* Design Configuration 5 */
343 #define CGEM_DESIGN_CFG5_RX_BUF_LEN_DEF_MASK (0xff << 20)
356 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf << 4)
357 #define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf
359 #define CGEM_DESIGN_CFG6 0x294 /* Design Configuration 6 */
361 #define CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK 0xfffe
364 #define CGEM_TX_QN_BAR(n) (0x440 + ((n) - 1) * 4)
365 #define CGEM_RX_QN_BAR(n) (0x480 + ((n) - 1) * 4)
367 #define CGEM_TX_QBAR_HI 0x4C8
368 #define CGEM_RX_QBAR_HI 0x4D4
396 #define CGEM_TXDESC_LENGTH_MASK 0x3fff
414 #define CGEM_RXDESC_OWN (1 << 0) /* buf filled */
425 #define CGEM_RXDESC_CKSUM_STAT_NONE (0 << 22)
437 #define CGEM_RXDESC_LENGTH_MASK 0x1fff