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1741 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
1743 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1744 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
1755 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
1756 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1757 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
1758 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
1759 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
1760 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
1761 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
1762 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
1763 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
1764 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
1765 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
1766 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
1767 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
1768 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
1769 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
1770 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
1771 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
1772 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
1773 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
1774 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
1775 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
1776 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
1777 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
1778 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
1779 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
1780 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
1781 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
1782 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
1783 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
1784 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
1785 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
1791 #define EMAC_LED_OVERRIDE (1L<<0)
1792 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
1797 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
1801 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
1809 #define EMAC_MODE_RESET (1L<<0)
1810 #define EMAC_REG_EMAC_LED 0xc
1811 #define EMAC_REG_EMAC_MAC_MATCH 0x10
1812 #define EMAC_REG_EMAC_MDIO_COMM 0xac
1813 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
1814 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0
1815 #define EMAC_REG_EMAC_MODE 0x0
1816 #define EMAC_REG_EMAC_RX_MODE 0xc8
1817 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
1818 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
1819 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
1821 #define EMAC_REG_EMAC_TX_MODE 0xbc
1822 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
1824 #define EMAC_REG_RX_PFC_MODE 0x320
1827 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
1828 #define EMAC_REG_RX_PFC_PARAM 0x324
1829 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
1831 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
1832 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
1833 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
1834 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
1835 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
1836 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
1837 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
1838 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
1843 #define EMAC_RX_MODE_RESET (1L<<0)
1847 #define EMAC_TX_MODE_RESET (1L<<0)
1850 #define MISC_REGISTERS_GPIO_0 0
1855 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
1860 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
1863 #define MISC_REGISTERS_GPIO_LOW 0
1865 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
1868 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
1869 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
1871 (0x1<<19)
1873 (0x1<<29)
1875 (0x1<<26)
1877 (0x1<<27)
1879 (0x1<<17)
1880 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
1881 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
1883 (0x1<<24)
1885 (0x1<<25)
1887 (0x1<<19)
1889 (0x1<<17)
1890 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
1891 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
1892 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
1894 (0x1<<14)
1895 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
1897 (0x1<<15)
1898 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
1899 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
1900 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
1901 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
1902 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
1904 (0x1<<11)
1906 (0x1<<13)
1908 (0x1<<16)
1909 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
1910 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
1912 (0x1<<20)
1914 (0x1<<21)
1916 (0x1<<22)
1918 (0x1<<23)
1919 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
1920 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
1921 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
1922 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
1923 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
1924 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
1925 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
1926 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
1927 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
1928 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
1929 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
1931 #define MISC_SPIO_FLOAT (0xffL<<24)
1936 #define MISC_SPIO_OUTPUT_LOW 0
1938 #define MISC_SPIO_SPIO4 0x10
1939 #define MISC_SPIO_SPIO5 0x20
1943 #define HW_LOCK_RESOURCE_MDIO 0
1953 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
1954 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
1955 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
1956 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
1957 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
1958 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
1959 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
1960 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
1961 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
1962 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
1963 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
1964 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
1965 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
1966 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
1967 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
1968 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
1969 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
1970 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
1971 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
1972 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
1973 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
1974 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
1975 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31)
1976 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
1977 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
1978 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
1979 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
1980 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
1981 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
1982 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31)
1983 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
1984 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
1985 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
1986 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
1987 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
1988 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
1989 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
1990 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
1991 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
1992 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
1993 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
1994 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
1995 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
1996 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
1997 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
1998 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
1999 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
2000 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
2001 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
2002 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
2003 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
2004 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
2005 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
2006 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
2007 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
2008 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
2009 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
2010 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
2011 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
2012 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
2013 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
2014 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
2015 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
2016 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
2017 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
2088 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
2090 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
2091 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
2160 #define GRCBASE_PXPCS 0x000000
2161 #define GRCBASE_PCICONFIG 0x002000
2162 #define GRCBASE_PCIREG 0x002400
2163 #define GRCBASE_EMAC0 0x008000
2164 #define GRCBASE_EMAC1 0x008400
2165 #define GRCBASE_DBU 0x008800
2166 #define GRCBASE_PGLUE_B 0x009000
2167 #define GRCBASE_MISC 0x00A000
2168 #define GRCBASE_DBG 0x00C000
2169 #define GRCBASE_NIG 0x010000
2170 #define GRCBASE_XCM 0x020000
2171 #define GRCBASE_PRS 0x040000
2172 #define GRCBASE_SRCH 0x040400
2173 #define GRCBASE_TSDM 0x042000
2174 #define GRCBASE_TCM 0x050000
2175 #define GRCBASE_BRB1 0x060000
2176 #define GRCBASE_MCP 0x080000
2177 #define GRCBASE_UPB 0x0C1000
2178 #define GRCBASE_CSDM 0x0C2000
2179 #define GRCBASE_USDM 0x0C4000
2180 #define GRCBASE_CCM 0x0D0000
2181 #define GRCBASE_UCM 0x0E0000
2182 #define GRCBASE_CDU 0x101000
2183 #define GRCBASE_DMAE 0x102000
2184 #define GRCBASE_PXP 0x103000
2185 #define GRCBASE_CFC 0x104000
2186 #define GRCBASE_HC 0x108000
2187 #define GRCBASE_ATC 0x110000
2188 #define GRCBASE_PXP2 0x120000
2189 #define GRCBASE_IGU 0x130000
2190 #define GRCBASE_PBF 0x140000
2191 #define GRCBASE_UMAC0 0x160000
2192 #define GRCBASE_UMAC1 0x160400
2193 #define GRCBASE_XPB 0x161000
2194 #define GRCBASE_MSTAT0 0x162000
2195 #define GRCBASE_MSTAT1 0x162800
2196 #define GRCBASE_XMAC0 0x163000
2197 #define GRCBASE_XMAC1 0x163800
2198 #define GRCBASE_TIMERS 0x164000
2199 #define GRCBASE_XSDM 0x166000
2200 #define GRCBASE_QM 0x168000
2201 #define GRCBASE_QM_4PORT 0x168000
2202 #define GRCBASE_DQ 0x170000
2203 #define GRCBASE_TSEM 0x180000
2204 #define GRCBASE_CSEM 0x200000
2205 #define GRCBASE_XSEM 0x280000
2206 #define GRCBASE_XSEM_4PORT 0x280000
2207 #define GRCBASE_USEM 0x300000
2208 #define GRCBASE_MCP_A 0x380000
2217 #define PCICFG_OFFSET 0x2000
2218 #define PCICFG_VENDOR_ID_OFFSET 0x00
2219 #define PCICFG_DEVICE_ID_OFFSET 0x02
2220 #define PCICFG_COMMAND_OFFSET 0x04
2221 #define PCICFG_COMMAND_IO_SPACE (1<<0)
2232 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
2233 #define PCICFG_STATUS_OFFSET 0x06
2234 #define PCICFG_REVISION_ID_OFFSET 0x08
2235 #define PCICFG_REVESION_ID_MASK 0xff
2236 #define PCICFG_REVESION_ID_ERROR_VAL 0xff
2237 #define PCICFG_CACHE_LINE_SIZE 0x0c
2238 #define PCICFG_LATENCY_TIMER 0x0d
2239 #define PCICFG_HEADER_TYPE 0x0e
2240 #define PCICFG_HEADER_TYPE_NORMAL 0
2243 #define PCICFG_BAR_1_LOW 0x10
2244 #define PCICFG_BAR_1_HIGH 0x14
2245 #define PCICFG_BAR_2_LOW 0x18
2246 #define PCICFG_BAR_2_HIGH 0x1c
2247 #define PCICFG_BAR_3_LOW 0x20
2248 #define PCICFG_BAR_3_HIGH 0x24
2249 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
2250 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
2251 #define PCICFG_INT_LINE 0x3c
2252 #define PCICFG_INT_PIN 0x3d
2253 #define PCICFG_PM_CAPABILITY 0x48
2254 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
2258 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
2266 #define PCICFG_PM_CSR_OFFSET 0x4c
2267 #define PCICFG_PM_CSR_STATE (0x3<<0)
2270 #define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50
2271 #define PCICFG_VPD_DATA_OFFSET 0x54
2272 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
2273 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
2274 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
2275 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
2276 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
2277 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
2278 #define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c
2279 #define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60
2280 #define PCICFG_MSI_DATA_OFFSET 0x64
2281 #define PCICFG_GRC_ADDRESS 0x78
2282 #define PCICFG_GRC_DATA 0x80
2283 #define PCICFG_ME_REGISTER 0x98
2284 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
2285 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
2286 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
2287 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
2288 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
2290 #define PCICFG_DEVICE_CONTROL 0xb4
2292 #define PCICFG_DEVICE_STATUS 0xb6
2293 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
2299 #define PCICFG_LINK_CONTROL 0xbc
2303 #define GRC_CONFIG_2_SIZE_REG 0x408
2304 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
2305 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
2306 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
2307 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
2308 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
2309 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
2310 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
2311 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
2312 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
2313 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
2314 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
2315 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
2316 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
2317 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
2318 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
2319 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
2320 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
2325 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
2326 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
2343 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
2346 #define GRC_CONFIG_3_SIZE_REG 0x40c
2347 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
2351 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
2355 #define GRC_REG_DEVICE_CONTROL 0x4d8
2372 #define GRC_BAR2_CONFIG 0x4e0
2373 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
2374 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
2375 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
2376 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
2377 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
2378 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
2379 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
2380 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
2381 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
2382 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
2383 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
2384 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
2385 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
2386 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
2387 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
2388 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
2389 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
2392 #define GRC_BAR3_CONFIG 0x4f4
2393 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0)
2394 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0)
2395 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0)
2396 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0)
2397 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0)
2398 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0)
2399 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0)
2400 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0)
2401 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0)
2402 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0)
2403 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0)
2404 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0)
2405 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0)
2406 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0)
2407 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0)
2408 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0)
2409 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0)
2412 #define PCI_PM_DATA_A 0x410
2413 #define PCI_PM_DATA_B 0x414
2414 #define PCI_ID_VAL1 0x434
2415 #define PCI_ID_VAL2 0x438
2416 #define PCI_ID_VAL3 0x43c
2417 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24)
2420 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608
2421 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf
2423 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C
2425 0x3F /*This field resides in VF only and does not exist in PF.
2426 This register controls the read value of the MSIX_CONTROL[10:0] register
2431 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
2433 0xf /*First VF_NUM for PF is encoded in this register.
2437 Since registers from 0x000-0x7ff are spilt across functions, each PF will have
2440 #define PXPCS_TL_CONTROL_5 0x814
2470 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
2473 #define PXPCS_TL_FUNC345_STAT 0x854
2565 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
2569 #define PXPCS_TL_FUNC678_STAT 0x85C
2661 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
2665 #define BAR_USTRORM_INTMEM 0x400000
2666 #define BAR_CSTRORM_INTMEM 0x410000
2667 #define BAR_XSTRORM_INTMEM 0x420000
2668 #define BAR_TSTRORM_INTMEM 0x430000
2671 #define BAR_IGU_INTMEM 0x440000
2673 #define BAR_DOORBELL_OFFSET 0x800000
2675 #define BAR_ME_REGISTER 0x450000
2676 #define ME_REG_PF_NUM_SHIFT 0
2681 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
2682 #define ME_REG_VF_ERR (0x1<<3)
2693 #define PXP_VF_ADDR_IGU_START 0
2694 #define PXP_VF_ADDR_IGU_SIZE (0x3000)
2698 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
2704 #define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100
2710 #define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200
2716 #define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300
2722 #define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400
2727 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
2732 #define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800
2737 #define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00
2742 #define PXP_VF_ADDR_DB_START 0x7c00
2743 #define PXP_VF_ADDR_DB_SIZE (0x200)
2747 #define PXP_VF_ADDR_GRC_START 0x7e00
2748 #define PXP_VF_ADDR_GRC_SIZE (0x200)
2752 #define PXP_VF_ADDR_DORQ_START (0x0)
2753 #define PXP_VF_ADDR_DORQ_SIZE (0xffffffff)
2754 #define PXP_VF_ADDR_DORQ_END (0xffffffff)
2756 #define PXP_BAR_GRC 0
2757 #define PXP_BAR_TSDM 0
2758 #define PXP_BAR_USDM 0
2759 #define PXP_BAR_XSDM 0
2760 #define PXP_BAR_CSDM 0
2761 #define PXP_BAR_IGU 0
2764 #define PXP_VF_BAR_IGU 0
2765 #define PXP_VF_BAR_USDM_QUEUES 0
2766 #define PXP_VF_BAR_TSDM_QUEUES 0
2767 #define PXP_VF_BAR_XSDM_QUEUES 0
2768 #define PXP_VF_BAR_CSDM_QUEUES 0
2769 #define PXP_VF_BAR_USDM_GLOBAL 0
2770 #define PXP_VF_BAR_TSDM_GLOBAL 0
2771 #define PXP_VF_BAR_XSDM_GLOBAL 0
2772 #define PXP_VF_BAR_CSDM_GLOBAL 0
2773 #define PXP_VF_BAR_DB 0
2774 #define PXP_VF_BAR_GRC 0
2779 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/
2781 #define PCIE_DEV_CAPS 0x04
2783 #define PCIE_DEV_CTRL 0x08
2784 #define PCIE_DEV_CTRL_FLR 0x8000;
2786 #define PCIE_DEV_STATUS 0x0A
2788 #define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/
2790 #define PCI_MSIX_TABLE_SIZE_MASK 0x07FF
2791 #define PCI_MSIX_TABLE_ENABLE_MASK 0x8000
2794 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
2795 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
2796 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
2797 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
2798 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
2800 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
2801 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
2802 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
2803 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
2804 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
2805 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
2806 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
2807 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
2808 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
2809 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
2810 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
2811 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
2812 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
2813 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
2814 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
2815 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
2816 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
2818 #define MDIO_REG_BANK_RX0 0x80b0
2819 #define MDIO_RX0_RX_STATUS 0x10
2820 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
2821 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
2822 #define MDIO_RX0_RX_EQ_BOOST 0x1c
2823 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2824 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
2826 #define MDIO_REG_BANK_RX1 0x80c0
2827 #define MDIO_RX1_RX_EQ_BOOST 0x1c
2828 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2829 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
2831 #define MDIO_REG_BANK_RX2 0x80d0
2832 #define MDIO_RX2_RX_EQ_BOOST 0x1c
2833 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2834 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
2836 #define MDIO_REG_BANK_RX3 0x80e0
2837 #define MDIO_RX3_RX_EQ_BOOST 0x1c
2838 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2839 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
2841 #define MDIO_REG_BANK_RX_ALL 0x80f0
2842 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
2843 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
2844 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
2846 #define MDIO_REG_BANK_TX0 0x8060
2847 #define MDIO_TX0_TX_DRIVER 0x17
2848 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2850 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2852 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2854 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2858 #define MDIO_REG_BANK_TX1 0x8070
2859 #define MDIO_TX1_TX_DRIVER 0x17
2860 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2862 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2864 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2866 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2870 #define MDIO_REG_BANK_TX2 0x8080
2871 #define MDIO_TX2_TX_DRIVER 0x17
2872 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2874 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2876 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2878 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2882 #define MDIO_REG_BANK_TX3 0x8090
2883 #define MDIO_TX3_TX_DRIVER 0x17
2884 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
2886 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
2888 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
2890 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
2894 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
2895 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
2897 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
2898 #define MDIO_BLOCK1_LANE_CTRL0 0x15
2899 #define MDIO_BLOCK1_LANE_CTRL1 0x16
2900 #define MDIO_BLOCK1_LANE_CTRL2 0x17
2901 #define MDIO_BLOCK1_LANE_PRBS 0x19
2903 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
2904 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
2905 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
2906 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
2907 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
2908 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
2909 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
2910 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
2911 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
2912 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
2914 #define MDIO_REG_BANK_GP_STATUS 0x8120
2915 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
2916 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
2917 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
2918 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
2919 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
2920 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
2921 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
2922 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
2923 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
2924 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
2925 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
2926 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
2927 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
2928 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
2929 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
2930 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
2931 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
2932 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
2933 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
2934 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
2935 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
2936 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
2937 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
2938 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
2939 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
2940 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
2941 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
2942 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
2943 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
2944 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
2947 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
2948 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
2949 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
2950 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
2951 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
2952 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
2953 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
2955 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
2956 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
2957 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
2958 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
2959 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
2960 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
2961 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
2962 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
2963 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
2964 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
2965 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
2966 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
2967 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
2968 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
2969 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
2970 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
2972 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
2973 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
2974 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
2975 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
2976 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
2977 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
2978 #define MDIO_SERDES_DIGITAL_MISC1 0x18
2979 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
2980 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
2981 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
2982 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
2983 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
2984 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
2985 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
2986 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
2987 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
2988 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
2989 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
2990 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
2991 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
2992 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
2993 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
2994 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
2995 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
2996 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
2998 #define MDIO_REG_BANK_OVER_1G 0x8320
2999 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
3000 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
3002 #define MDIO_OVER_1G_UP1 0x19
3003 #define MDIO_OVER_1G_UP1_2_5G 0x0001
3004 #define MDIO_OVER_1G_UP1_5G 0x0002
3005 #define MDIO_OVER_1G_UP1_6G 0x0004
3006 #define MDIO_OVER_1G_UP1_10G 0x0010
3007 #define MDIO_OVER_1G_UP1_10GH 0x0008
3008 #define MDIO_OVER_1G_UP1_12G 0x0020
3009 #define MDIO_OVER_1G_UP1_12_5G 0x0040
3010 #define MDIO_OVER_1G_UP1_13G 0x0080
3011 #define MDIO_OVER_1G_UP1_15G 0x0100
3012 #define MDIO_OVER_1G_UP1_16G 0x0200
3013 #define MDIO_OVER_1G_UP2 0x1A
3014 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
3015 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
3016 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
3017 #define MDIO_OVER_1G_UP3 0x1B
3018 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
3019 #define MDIO_OVER_1G_LP_UP1 0x1C
3020 #define MDIO_OVER_1G_LP_UP2 0x1D
3021 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
3022 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
3024 #define MDIO_OVER_1G_LP_UP3 0x1E
3026 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
3027 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
3028 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
3029 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
3031 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
3032 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
3033 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
3034 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
3036 #define MDIO_REG_BANK_CL73_USERB0 0x8370
3037 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
3038 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
3039 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
3040 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
3041 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
3042 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
3043 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
3044 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
3045 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
3046 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
3047 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
3049 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
3050 #define MDIO_AER_BLOCK_AER_REG 0x1E
3052 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
3053 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
3054 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
3055 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
3056 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
3057 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
3058 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
3059 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
3060 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
3061 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
3062 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
3063 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
3064 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
3065 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
3066 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
3067 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
3068 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
3069 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
3070 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
3071 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
3072 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
3073 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
3074 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
3075 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
3076 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
3077 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
3078 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
3079 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
3080 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
3081 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
3082 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
3086 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
3089 #define MDIO_PMA_DEVAD 0x1
3091 #define MDIO_PMA_REG_CTRL 0x0
3092 #define MDIO_PMA_REG_STATUS 0x1
3093 #define MDIO_PMA_REG_10G_CTRL2 0x7
3094 #define MDIO_PMA_REG_TX_DISABLE 0x0009
3095 #define MDIO_PMA_REG_RX_SD 0xa
3097 #define MDIO_PMA_REG_BCM_CTRL 0x0096
3098 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
3099 #define MDIO_PMA_LASI_RXCTRL 0x9000
3100 #define MDIO_PMA_LASI_TXCTRL 0x9001
3101 #define MDIO_PMA_LASI_CTRL 0x9002
3102 #define MDIO_PMA_LASI_RXSTAT 0x9003
3103 #define MDIO_PMA_LASI_TXSTAT 0x9004
3104 #define MDIO_PMA_LASI_STAT 0x9005
3105 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
3106 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
3107 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
3108 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
3109 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
3110 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
3111 #define MDIO_PMA_REG_GEN_CTRL 0xca10
3112 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
3113 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
3114 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
3115 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
3116 #define MDIO_PMA_REG_ROM_VER1 0xca19
3117 #define MDIO_PMA_REG_ROM_VER2 0xca1a
3118 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
3119 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
3120 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
3121 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
3122 #define MDIO_PMA_REG_LRM_MODE 0xca3f
3123 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
3124 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
3126 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
3127 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
3128 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
3129 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
3130 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
3131 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
3132 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
3133 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
3134 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
3135 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
3136 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
3137 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
3139 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
3140 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
3141 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
3142 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
3143 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
3144 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
3145 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
3146 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
3147 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
3148 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
3150 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
3151 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
3152 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
3153 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
3154 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
3156 #define MDIO_PMA_REG_7101_RESET 0xc000
3157 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
3158 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
3159 #define MDIO_PMA_REG_7101_VER1 0xc026
3160 #define MDIO_PMA_REG_7101_VER2 0xc027
3162 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
3163 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
3164 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
3165 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
3166 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
3167 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
3168 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
3169 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
3170 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
3174 #define MDIO_WIS_DEVAD 0x2
3176 #define MDIO_WIS_REG_LASI_CNTL 0x9002
3177 #define MDIO_WIS_REG_LASI_STATUS 0x9005
3179 #define MDIO_PCS_DEVAD 0x3
3180 #define MDIO_PCS_REG_STATUS 0x0020
3181 #define MDIO_PCS_REG_LASI_STATUS 0x9005
3182 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
3183 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
3184 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
3186 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
3188 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
3190 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
3193 #define MDIO_XS_DEVAD 0x4
3194 #define MDIO_XS_REG_STATUS 0x0001
3195 #define MDIO_XS_PLL_SEQUENCER 0x8000
3196 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
3198 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
3199 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
3200 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
3201 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
3202 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
3204 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
3206 #define MDIO_AN_DEVAD 0x7
3208 #define MDIO_AN_REG_CTRL 0x0000
3209 #define MDIO_AN_REG_STATUS 0x0001
3210 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
3211 #define MDIO_AN_REG_ADV_PAUSE 0x0010
3212 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
3213 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
3214 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
3215 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
3216 #define MDIO_AN_REG_ADV 0x0011
3217 #define MDIO_AN_REG_ADV2 0x0012
3218 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
3219 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
3220 #define MDIO_AN_REG_MASTER_STATUS 0x0021
3221 #define MDIO_AN_REG_EEE_ADV 0x003c
3222 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
3224 #define MDIO_AN_REG_LINK_STATUS 0x8304
3225 #define MDIO_AN_REG_CL37_CL73 0x8370
3226 #define MDIO_AN_REG_CL37_AN 0xffe0
3227 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
3228 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
3229 #define MDIO_AN_REG_1000T_STATUS 0xffea
3231 #define MDIO_AN_REG_8073_2_5G 0x8329
3232 #define MDIO_AN_REG_8073_BAM 0x8350
3234 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
3235 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
3236 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
3237 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
3238 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2
3239 #define BCM84858_PHY_ID 0x600d
3240 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3
3241 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
3242 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
3243 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
3244 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
3245 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
3246 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
3247 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
3248 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
3249 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
3252 #define MDIO_CTL_DEVAD 0x1e
3253 #define MDIO_CTL_REG_84823_MEDIA 0x401a
3254 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
3256 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
3257 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
3259 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
3260 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
3261 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
3265 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
3266 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
3267 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
3268 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
3269 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
3270 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
3271 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
3272 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
3273 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
3274 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
3275 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
3276 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
3279 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
3280 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
3281 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
3282 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
3283 #define MDIO_84833_SUPER_ISOLATE 0x8000
3285 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
3286 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
3287 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
3288 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
3289 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
3290 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
3291 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
3292 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
3293 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
3294 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
3295 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
3305 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
3306 #define PHY848xx_CMD_GET_EEE_MODE 0x8008
3307 #define PHY848xx_CMD_SET_EEE_MODE 0x8009
3308 #define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
3310 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
3311 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
3312 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
3313 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
3314 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
3315 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
3316 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
3317 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
3318 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
3326 #define PHY84858_STATUS_CMD_RECEIVED 0x0001
3327 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
3328 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
3329 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
3330 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
3334 #define MDIO_WC_DEVAD 0x3
3335 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
3336 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
3337 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
3338 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
3339 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
3340 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
3341 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
3342 #define MDIO_WC_REG_PCS_STATUS2 0x0021
3343 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
3344 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
3345 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
3346 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
3347 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
3348 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
3349 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
3350 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
3351 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
3352 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
3353 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
3354 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
3355 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
3356 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
3357 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
3358 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
3359 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
3360 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
3361 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
3362 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
3363 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
3364 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
3365 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
3366 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
3367 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
3368 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
3369 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
3370 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
3371 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
3372 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
3373 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
3374 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
3375 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
3376 #define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
3377 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
3378 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
3379 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
3380 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
3381 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
3382 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
3383 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
3384 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
3385 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
3386 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
3387 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
3388 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
3389 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
3390 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
3391 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
3392 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
3393 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
3394 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
3395 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
3396 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
3397 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
3398 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
3399 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
3400 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
3401 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
3402 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
3403 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
3404 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
3405 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
3406 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
3407 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
3409 #define MDIO_WC_REG_DSC_SMC 0x8213
3410 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
3411 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
3412 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
3413 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
3414 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
3415 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
3416 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
3417 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
3418 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
3419 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
3420 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
3421 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
3422 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
3423 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
3424 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
3425 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
3426 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
3427 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
3428 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
3429 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
3430 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
3431 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
3432 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
3433 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
3434 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
3435 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
3436 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
3437 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
3438 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
3439 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
3440 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
3441 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
3442 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
3443 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
3444 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
3445 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
3446 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
3447 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
3448 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
3449 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
3450 #define MDIO_WC_REG_RX66_SCW0 0x83c2
3451 #define MDIO_WC_REG_RX66_SCW1 0x83c3
3452 #define MDIO_WC_REG_RX66_SCW2 0x83c4
3453 #define MDIO_WC_REG_RX66_SCW3 0x83c5
3454 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
3455 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
3456 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
3457 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
3458 #define MDIO_WC_REG_FX100_CTRL1 0x8400
3459 #define MDIO_WC_REG_FX100_CTRL3 0x8402
3460 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
3461 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
3462 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
3463 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
3464 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
3465 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
3466 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
3467 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
3468 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
3469 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
3470 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
3471 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
3472 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
3473 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
3475 #define MDIO_WC_REG_AERBLK_AER 0xffde
3476 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
3477 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
3479 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
3480 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
3483 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
3485 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
3488 #define MDIO_REG_GPHY_MII_STATUS 0x1
3489 #define MDIO_REG_GPHY_PHYID_LSB 0x3
3490 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
3491 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
3492 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
3493 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
3494 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
3495 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
3496 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
3497 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
3498 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
3499 #define MDIO_REG_GPHY_AUX_STATUS 0x19
3500 #define MDIO_REG_INTR_STATUS 0x1a
3501 #define MDIO_REG_INTR_MASK 0x1b
3502 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
3503 #define MDIO_REG_GPHY_SHADOW 0x1c
3504 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
3505 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
3506 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
3507 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
3508 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
3511 #define IGU_FUNC_BASE 0x0400
3513 #define IGU_ADDR_MSIX 0x0000
3514 #define IGU_ADDR_INT_ACK 0x0200
3515 #define IGU_ADDR_PROD_UPD 0x0201
3516 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
3517 #define IGU_ADDR_ATTN_BITS_SET 0x0203
3518 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
3519 #define IGU_ADDR_COALESCE_NOW 0x0205
3520 #define IGU_ADDR_SIMD_MASK 0x0206
3521 #define IGU_ADDR_SIMD_NOMASK 0x0207
3522 #define IGU_ADDR_MSI_CTL 0x0210
3523 #define IGU_ADDR_MSI_ADDR_LO 0x0211
3524 #define IGU_ADDR_MSI_ADDR_HI 0x0212
3525 #define IGU_ADDR_MSI_DATA 0x0213
3528 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
3533 #define COMMAND_REG_INT_ACK 0x0
3534 #define COMMAND_REG_PROD_UPD 0x4
3535 #define COMMAND_REG_ATTN_BITS_UPD 0x8
3536 #define COMMAND_REG_ATTN_BITS_SET 0xc
3537 #define COMMAND_REG_ATTN_BITS_CLR 0x10
3538 #define COMMAND_REG_COALESCE_NOW 0x14
3539 #define COMMAND_REG_SIMD_MASK 0x18
3540 #define COMMAND_REG_SIMD_NOMASK 0x1c
3543 #define IGU_MEM_BASE 0x0000
3545 #define IGU_MEM_MSIX_BASE 0x0000
3546 #define IGU_MEM_MSIX_UPPER 0x007f
3547 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
3549 #define IGU_MEM_PBA_MSIX_BASE 0x0200
3550 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
3552 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
3553 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
3555 #define IGU_CMD_INT_ACK_BASE 0x0400
3558 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
3560 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
3563 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
3565 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
3566 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
3567 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
3569 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
3570 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
3571 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
3572 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
3575 #define IGU_REG_RESERVED_UPPER 0x05ff
3580 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
3581 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3582 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
3583 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
3584 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3585 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
3588 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
3589 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
3590 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
3592 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
3602 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
3603 [5:2] = 0; [1:0] = PF number) */
3604 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
3606 #define IGU_FID_VF_NUM_MASK (0x3f)
3607 #define IGU_FID_PF_NUM_MASK (0x7)
3609 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
3610 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
3612 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
3622 * String-to-compress [3:0] = Type
3625 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
3627 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
3629 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
3631 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
3632 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
3636 * Calculates crc 8 on a word value: polynomial 0-1-2-8
3649 for (i = 0; i < 32; i++) { in calc_crc8()
3655 for (i = 0; i < 8; i++) { in calc_crc8()
3660 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ in calc_crc8()
3661 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ in calc_crc8()
3665 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; in calc_crc8()
3667 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ in calc_crc8()
3668 C[0] ^ C[1] ^ C[4] ^ C[5]; in calc_crc8()
3674 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; in calc_crc8()
3683 crc_res = 0; in calc_crc8()
3684 for (i = 0; i < 8; i++) { in calc_crc8()